[llvm] [AArch64][llvm] Pre-commit tests for enabling streaming with +fprcvt (PR #177333)
Jonathan Thackray via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 4 09:30:39 PST 2026
https://github.com/jthackray updated https://github.com/llvm/llvm-project/pull/177333
>From 88295790abc27e64cf15ed731362d16c39b57299 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray <jonathan.thackray at arm.com>
Date: Wed, 21 Jan 2026 15:43:01 +0000
Subject: [PATCH] [AArch64][llvm] Pre-commit tests for enabling streaming with
+fprcvt
Add pre-commit tests for enabling streaming with +fprcvt. Because I've
added a `+sve,+neon,+fullfp16,+fprcvt -force-streaming-compatible` line
to the testfiles, this required a small change to prevent an assert.
---
.../Target/AArch64/AArch64ISelLowering.cpp | 4 +
.../CodeGen/AArch64/arm64-cvt-simd-fptoi.ll | 1552 +++++++++++++++++
.../CodeGen/AArch64/arm64-cvtf-simd-itofp.ll | 282 +++
.../AArch64/fp16_i16_intrinsic_scalar.ll | 62 +
4 files changed, 1900 insertions(+)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 840298ff965e1..0de367e1fb990 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -20557,6 +20557,10 @@ tryToReplaceScalarFPConversionWithSVE(SDNode *N, SelectionDAG &DAG,
if (DCI.isBeforeLegalizeOps())
return SDValue();
+ if (N->getOpcode() == ISD::FP_TO_SINT_SAT ||
+ N->getOpcode() == ISD::FP_TO_UINT_SAT)
+ return SDValue();
+
if (!Subtarget->isSVEorStreamingSVEAvailable() ||
(!Subtarget->isStreaming() && !Subtarget->isStreamingCompatible()))
return SDValue();
diff --git a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
index 3f6ad552ec200..7dd0806758d28 100644
--- a/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK-NOFPRCVT
; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+sme,+neon,+fullfp16,+fprcvt -force-streaming | FileCheck %s --check-prefixes=CHECK-SME
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+sve,+neon,+fullfp16,+fprcvt -force-streaming-compatible | FileCheck %s --check-prefixes=CHECK-SVE
; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -global-isel-abort=2 -mattr=+fprcvt,+fullfp16 2>&1 | FileCheck %s --check-prefixes=CHECK
; CHECK-GI: warning: Instruction selection used fallback path for fptosi_i32_f16_simd
@@ -31,6 +33,20 @@ define float @test_fptosi_f16_i32_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptosi_f16_i32_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.s
+; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.h
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptosi_f16_i32_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 def $z0
+; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.h
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = fptosi half %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -47,6 +63,20 @@ define double @test_fptosi_f16_i64_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptosi_f16_i64_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptosi_f16_i64_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 def $z0
+; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.h
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = fptosi half %a to i64
%bc = bitcast i64 %r to double
ret double %bc
@@ -63,6 +93,16 @@ define float @test_fptosi_f64_i32_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptosi_f64_i32_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptosi_f64_i32_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, d0
+; CHECK-SVE-NEXT: ret
%r = fptosi double %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -79,6 +119,20 @@ define double @test_fptosi_f32_i64_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptosi_f32_i64_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptosi_f32_i64_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0
+; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = fptosi float %a to i64
%bc = bitcast i64 %r to double
ret double %bc
@@ -94,6 +148,20 @@ define double @test_fptosi_f64_i64_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptosi_f64_i64_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptosi_f64_i64_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = fptosi double %a to i64
%bc = bitcast i64 %r to double
ret double %bc
@@ -110,6 +178,20 @@ define float @test_fptosi_f32_i32_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptosi_f32_i32_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.s
+; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptosi_f32_i32_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0
+; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = fptosi float %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -126,6 +208,20 @@ define float @test_fptoui_f16_i32_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptoui_f16_i32_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.s
+; CHECK-SME-NEXT: fcvtzu z0.s, p0/m, z0.h
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptoui_f16_i32_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 def $z0
+; CHECK-SVE-NEXT: fcvtzu z0.s, p0/m, z0.h
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = fptoui half %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -142,6 +238,20 @@ define double @test_fptoui_f16_i64_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptoui_f16_i64_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.h
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptoui_f16_i64_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 def $z0
+; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.h
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = fptoui half %a to i64
%bc = bitcast i64 %r to double
ret double %bc
@@ -158,6 +268,16 @@ define float @test_fptoui_f64_i32_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptoui_f64_i32_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptoui_f64_i32_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, d0
+; CHECK-SVE-NEXT: ret
%r = fptoui double %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -174,6 +294,20 @@ define double @test_fptoui_f32_i64_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptoui_f32_i64_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptoui_f32_i64_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0
+; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = fptoui float %a to i64
%bc = bitcast i64 %r to double
ret double %bc
@@ -189,6 +323,20 @@ define double @test_fptoui_f64_i64_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptoui_f64_i64_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptoui_f64_i64_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = fptoui double %a to i64
%bc = bitcast i64 %r to double
ret double %bc
@@ -205,6 +353,20 @@ define float @test_fptoui_f32_i32_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: test_fptoui_f32_i32_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.s
+; CHECK-SME-NEXT: fcvtzu z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: test_fptoui_f32_i32_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0
+; CHECK-SVE-NEXT: fcvtzu z0.s, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = fptoui float %a to i32
%bc = bitcast i32 %r to float
ret float %bc
@@ -226,6 +388,16 @@ define float @fptosi_i32_f16_simd(half %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fptosi_i32_f16_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fptosi_i32_f16_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, h0
+; CHECK-SVE-NEXT: ret
%val = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %x, metadata !"fpexcept.strict")
%sum = bitcast i32 %val to float
ret float %sum
@@ -242,6 +414,16 @@ define double @fptosi_i64_f16_simd(half %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fptosi_i64_f16_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fptosi_i64_f16_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, h0
+; CHECK-SVE-NEXT: ret
%val = call i64 @llvm.experimental.constrained.fptosi.i64.f16(half %x, metadata !"fpexcept.strict")
%sum = bitcast i64 %val to double
ret double %sum
@@ -258,6 +440,16 @@ define double @fptosi_i64_f32_simd(float %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fptosi_i64_f32_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fptosi_i64_f32_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, s0
+; CHECK-SVE-NEXT: ret
%val = call i64 @llvm.experimental.constrained.fptosi.i64.f32(float %x, metadata !"fpexcept.strict")
%bc = bitcast i64 %val to double
ret double %bc
@@ -274,6 +466,16 @@ define float @fptosi_i32_f64_simd(double %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fptosi_i32_f64_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fptosi_i32_f64_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, d0
+; CHECK-SVE-NEXT: ret
%val = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %x, metadata !"fpexcept.strict")
%bc = bitcast i32 %val to float
ret float %bc
@@ -289,6 +491,16 @@ define double @fptosi_i64_f64_simd(double %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fptosi_i64_f64_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fptosi_i64_f64_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, d0
+; CHECK-SVE-NEXT: ret
%val = call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %x, metadata !"fpexcept.strict")
%bc = bitcast i64 %val to double
ret double %bc
@@ -304,6 +516,16 @@ define float @fptosi_i32_f32_simd(float %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fptosi_i32_f32_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fptosi_i32_f32_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, s0
+; CHECK-SVE-NEXT: ret
%val = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %x, metadata !"fpexcept.strict")
%bc = bitcast i32 %val to float
ret float %bc
@@ -322,6 +544,16 @@ define float @fptoui_i32_f16_simd(half %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fptoui_i32_f16_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fptoui_i32_f16_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, h0
+; CHECK-SVE-NEXT: ret
%val = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %x, metadata !"fpexcept.strict")
%sum = bitcast i32 %val to float
ret float %sum
@@ -338,6 +570,16 @@ define double @fptoui_i64_f16_simd(half %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fptoui_i64_f16_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fptoui_i64_f16_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu d0, h0
+; CHECK-SVE-NEXT: ret
%val = call i64 @llvm.experimental.constrained.fptoui.i64.f16(half %x, metadata !"fpexcept.strict")
%sum = bitcast i64 %val to double
ret double %sum
@@ -354,6 +596,16 @@ define double @fptoui_i64_f32_simd(float %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fptoui_i64_f32_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fptoui_i64_f32_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu d0, s0
+; CHECK-SVE-NEXT: ret
%val = call i64 @llvm.experimental.constrained.fptoui.i64.f32(float %x, metadata !"fpexcept.strict")
%bc = bitcast i64 %val to double
ret double %bc
@@ -370,6 +622,16 @@ define float @fptoui_i32_f64_simd(double %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fptoui_i32_f64_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fptoui_i32_f64_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, d0
+; CHECK-SVE-NEXT: ret
%val = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %x, metadata !"fpexcept.strict")
%bc = bitcast i32 %val to float
ret float %bc
@@ -385,6 +647,16 @@ define double @fptoui_i64_f64_simd(double %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fptoui_i64_f64_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fptoui_i64_f64_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu d0, d0
+; CHECK-SVE-NEXT: ret
%val = call i64 @llvm.experimental.constrained.fptoui.i64.f64(double %x, metadata !"fpexcept.strict")
%bc = bitcast i64 %val to double
ret double %bc
@@ -400,6 +672,16 @@ define float @fptoui_i32_f32_simd(float %x) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fptoui_i32_f32_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fptoui_i32_f32_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, s0
+; CHECK-SVE-NEXT: ret
%val = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %x, metadata !"fpexcept.strict")
%bc = bitcast i32 %val to float
ret float %bc
@@ -421,6 +703,21 @@ define double @fcvtas_ds_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_ds_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frinta s0, s0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_ds_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frinta s0, s0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -438,6 +735,16 @@ define float @fcvtas_sd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_sd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_sd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -454,6 +761,21 @@ define float @fcvtas_ss_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_ss_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frinta s0, s0
+; CHECK-SME-NEXT: ptrue p0.s
+; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_ss_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frinta s0, s0
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -470,6 +792,21 @@ define double @fcvtas_dd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_dd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frinta d0, d0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_dd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frinta d0, d0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -488,6 +825,21 @@ define double @fcvtau_ds_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtau d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_ds_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frinta s0, s0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_ds_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frinta s0, s0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -505,6 +857,16 @@ define float @fcvtau_sd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtau s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_sd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtau s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_sd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtau s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -521,6 +883,21 @@ define float @fcvtau_ss_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_ss_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frinta s0, s0
+; CHECK-SME-NEXT: ptrue p0.s
+; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_ss_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frinta s0, s0
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -537,6 +914,21 @@ define double @fcvtau_dd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_dd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frinta d0, d0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_dd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frinta d0, d0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -554,6 +946,21 @@ define double @fcvtns_ds_roundeven_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtns d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_ds_roundeven_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintn s0, s0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_ds_roundeven_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintn s0, s0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -571,6 +978,16 @@ define float @fcvtns_sd_roundeven_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtns s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_sd_roundeven_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtns s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_sd_roundeven_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtns s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -587,6 +1004,21 @@ define float @fcvtns_ss_roundeven_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtns s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_ss_roundeven_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintn s0, s0
+; CHECK-SME-NEXT: ptrue p0.s
+; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_ss_roundeven_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintn s0, s0
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -603,6 +1035,21 @@ define double @fcvtns_dd_roundeven_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtns d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_dd_roundeven_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintn d0, d0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_dd_roundeven_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintn d0, d0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -621,6 +1068,21 @@ define double @fcvtnu_ds_roundeven_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtnu d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_ds_roundeven_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintn s0, s0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_ds_roundeven_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintn s0, s0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -638,6 +1100,16 @@ define float @fcvtnu_sd_roundeven_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtnu s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_sd_roundeven_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtnu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_sd_roundeven_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtnu s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -654,6 +1126,21 @@ define float @fcvtnu_ss_roundeven_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtnu s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_ss_roundeven_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintn s0, s0
+; CHECK-SME-NEXT: ptrue p0.s
+; CHECK-SME-NEXT: fcvtzu z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_ss_roundeven_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintn s0, s0
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: fcvtzu z0.s, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = fptoui float %r to i32
%bc = bitcast i32 %i to float
@@ -670,6 +1157,21 @@ define double @fcvtnu_dd_roundeven_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtnu d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_dd_roundeven_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintn d0, d0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_dd_roundeven_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintn d0, d0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = fptoui double %r to i64
%bc = bitcast i64 %i to double
@@ -687,6 +1189,21 @@ define double @fcvtms_ds_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_ds_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintm s0, s0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_ds_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintm s0, s0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -704,6 +1221,16 @@ define float @fcvtms_sd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_sd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_sd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -720,6 +1247,21 @@ define float @fcvtms_ss_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_ss_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintm s0, s0
+; CHECK-SME-NEXT: ptrue p0.s
+; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_ss_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintm s0, s0
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -736,6 +1278,21 @@ define double @fcvtms_dd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_dd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintm d0, d0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_dd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintm d0, d0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -755,6 +1312,21 @@ define double @fcvtmu_ds_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtmu d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_ds_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintm s0, s0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_ds_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintm s0, s0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -772,6 +1344,16 @@ define float @fcvtmu_sd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtmu s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_sd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtmu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_sd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtmu s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -788,6 +1370,21 @@ define float @fcvtmu_ss_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_ss_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintm s0, s0
+; CHECK-SME-NEXT: ptrue p0.s
+; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_ss_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintm s0, s0
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -804,6 +1401,21 @@ define double @fcvtmu_dd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_dd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintm d0, d0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_dd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintm d0, d0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -822,6 +1434,21 @@ define double @fcvtps_ds_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_ds_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintp s0, s0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_ds_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintp s0, s0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -839,6 +1466,16 @@ define float @fcvtps_sd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_sd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_sd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -855,6 +1492,21 @@ define float @fcvtps_ss_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_ss_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintp s0, s0
+; CHECK-SME-NEXT: ptrue p0.s
+; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_ss_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintp s0, s0
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -871,6 +1523,21 @@ define double @fcvtps_dd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_dd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintp d0, d0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_dd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintp d0, d0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -889,6 +1556,21 @@ define double @fcvtpu_ds_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtpu d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_ds_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintp s0, s0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_ds_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintp s0, s0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -906,6 +1588,16 @@ define float @fcvtpu_sd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtpu s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_sd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtpu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_sd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtpu s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -922,6 +1614,21 @@ define float @fcvtpu_ss_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_ss_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintp s0, s0
+; CHECK-SME-NEXT: ptrue p0.s
+; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_ss_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintp s0, s0
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -938,6 +1645,21 @@ define double @fcvtpu_dd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_dd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintp d0, d0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_dd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintp d0, d0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -956,6 +1678,21 @@ define double @fcvtzs_ds_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_ds_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintz s0, s0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_ds_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintz s0, s0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = fptosi float %r to i64
%bc = bitcast i64 %i to double
@@ -973,6 +1710,16 @@ define float @fcvtzs_sd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_sd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_sd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = fptosi double %r to i32
%bc = bitcast i32 %i to float
@@ -989,6 +1736,21 @@ define float @fcvtzs_ss_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_ss_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintz s0, s0
+; CHECK-SME-NEXT: ptrue p0.s
+; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_ss_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintz s0, s0
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -1005,6 +1767,21 @@ define double @fcvtzs_dd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_dd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintz d0, d0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_dd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintz d0, d0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -1022,6 +1799,21 @@ define double @fcvtzu_ds_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_ds_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintz s0, s0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzu z0.d, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_ds_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintz s0, s0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzu z0.d, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = fptoui float %r to i64
%bc = bitcast i64 %i to double
@@ -1039,6 +1831,16 @@ define float @fcvtzu_sd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_sd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_sd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = fptoui double %r to i32
%bc = bitcast i32 %i to float
@@ -1055,6 +1857,21 @@ define float @fcvtzu_ss_round_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_ss_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintz s0, s0
+; CHECK-SME-NEXT: ptrue p0.s
+; CHECK-SME-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_ss_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintz s0, s0
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: fcvtzs z0.s, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = fptosi float %r to i32
%bc = bitcast i32 %i to float
@@ -1071,6 +1888,21 @@ define double @fcvtzu_dd_round_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_dd_round_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: frintz d0, d0
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_dd_round_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: frintz d0, d0
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: fcvtzs z0.d, p0/m, z0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = fptosi double %r to i64
%bc = bitcast i64 %i to double
@@ -1093,6 +1925,16 @@ define float @fcvtzs_sh_sat_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_sh_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_sh_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, h0
+; CHECK-SVE-NEXT: ret
%i = call i32 @llvm.fptosi.sat.i32.f16(half %a)
%bc = bitcast i32 %i to float
ret float %bc
@@ -1109,6 +1951,16 @@ define double @fcvtzs_dh_sat_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_dh_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_dh_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, h0
+; CHECK-SVE-NEXT: ret
%i = call i64 @llvm.fptosi.sat.i64.f16(half %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -1125,6 +1977,16 @@ define double @fcvtzs_ds_sat_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_ds_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_ds_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, s0
+; CHECK-SVE-NEXT: ret
%i = call i64 @llvm.fptosi.sat.i64.f32(float %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -1141,6 +2003,16 @@ define float @fcvtzs_sd_sat_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_sd_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_sd_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, d0
+; CHECK-SVE-NEXT: ret
%i = call i32 @llvm.fptosi.sat.i32.f64(double %a)
%bc = bitcast i32 %i to float
ret float %bc
@@ -1156,6 +2028,16 @@ define float @fcvtzs_ss_sat_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_ss_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_ss_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, s0
+; CHECK-SVE-NEXT: ret
%i = call i32 @llvm.fptosi.sat.i32.f32(float %a)
%bc = bitcast i32 %i to float
ret float %bc
@@ -1171,6 +2053,16 @@ define double @fcvtzs_dd_sat_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_dd_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_dd_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, d0
+; CHECK-SVE-NEXT: ret
%i = call i64 @llvm.fptosi.sat.i64.f64(double %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -1187,6 +2079,16 @@ define float @fcvtzu_sh_sat_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_sh_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_sh_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, h0
+; CHECK-SVE-NEXT: ret
%i = call i32 @llvm.fptoui.sat.i32.f16(half %a)
%bc = bitcast i32 %i to float
ret float %bc
@@ -1203,6 +2105,16 @@ define double @fcvtzu_dh_sat_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_dh_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_dh_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu d0, h0
+; CHECK-SVE-NEXT: ret
%i = call i64 @llvm.fptoui.sat.i64.f16(half %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -1219,6 +2131,16 @@ define double @fcvtzu_ds_sat_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_ds_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_ds_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu d0, s0
+; CHECK-SVE-NEXT: ret
%i = call i64 @llvm.fptoui.sat.i64.f32(float %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -1235,6 +2157,16 @@ define float @fcvtzu_sd_sat_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_sd_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_sd_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, d0
+; CHECK-SVE-NEXT: ret
%i = call i32 @llvm.fptoui.sat.i32.f64(double %a)
%bc = bitcast i32 %i to float
ret float %bc
@@ -1250,6 +2182,16 @@ define float @fcvtzu_ss_sat_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_ss_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_ss_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, s0
+; CHECK-SVE-NEXT: ret
%i = call i32 @llvm.fptosi.sat.i32.f32(float %a)
%bc = bitcast i32 %i to float
ret float %bc
@@ -1265,6 +2207,16 @@ define double @fcvtzu_dd_sat_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_dd_sat_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_dd_sat_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, d0
+; CHECK-SVE-NEXT: ret
%i = call i64 @llvm.fptosi.sat.i64.f64(double %a)
%bc = bitcast i64 %i to double
ret double %bc
@@ -1285,6 +2237,16 @@ define float @fcvtas_sh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.round.f16(half %a)
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1302,6 +2264,16 @@ define double @fcvtas_dh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.round.f16(half %a)
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1319,6 +2291,16 @@ define double @fcvtas_ds_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1336,6 +2318,16 @@ define float @fcvtas_sd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1352,6 +2344,16 @@ define float @fcvtas_ss_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1368,6 +2370,16 @@ define double @fcvtas_dd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtas_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -1385,6 +2397,16 @@ define float @fcvtau_sh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtau s0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtau s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtau s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.round.f16(half %a)
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1402,6 +2424,16 @@ define double @fcvtau_dh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtau d0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtau d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtau d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.round.f16(half %a)
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1419,6 +2451,16 @@ define double @fcvtau_ds_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtau d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtau d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtau d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1436,6 +2478,16 @@ define float @fcvtau_sd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtau s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtau s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtau s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1452,6 +2504,16 @@ define float @fcvtau_ss_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.round.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1468,6 +2530,16 @@ define double @fcvtau_dd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtas d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtau_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtas d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtas d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.round.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -1485,6 +2557,16 @@ define float @fcvtns_sh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtns s0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtns s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtns s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.roundeven.f16(half %a)
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1502,6 +2584,16 @@ define double @fcvtns_dh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtns d0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtns d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtns d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.roundeven.f16(half %a)
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1519,6 +2611,16 @@ define double @fcvtns_ds_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtns d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtns d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtns d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1536,6 +2638,16 @@ define float @fcvtns_sd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtns s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtns s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtns s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1552,6 +2664,16 @@ define float @fcvtns_ss_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtns s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtns s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtns s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1568,6 +2690,16 @@ define double @fcvtns_dd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtns d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtns_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtns d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtns d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -1585,6 +2717,16 @@ define float @fcvtnu_sh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtnu s0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtnu s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtnu s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.roundeven.f16(half %a)
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1602,6 +2744,16 @@ define double @fcvtnu_dh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtnu d0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtnu d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtnu d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.roundeven.f16(half %a)
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1619,6 +2771,16 @@ define double @fcvtnu_ds_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtnu d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtnu d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtnu d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1636,6 +2798,16 @@ define float @fcvtnu_sd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtnu s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtnu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtnu s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1652,6 +2824,16 @@ define float @fcvtnu_ss_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtnu s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtnu s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtnu s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.roundeven.f32(float %a)
%i = call i32 @llvm.fptoui.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1668,6 +2850,16 @@ define double @fcvtnu_dd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtnu d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtnu_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtnu d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtnu d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.roundeven.f64(double %a)
%i = call i64 @llvm.fptoui.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -1685,6 +2877,16 @@ define float @fcvtms_sh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.floor.f16(half %a)
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1702,6 +2904,16 @@ define double @fcvtms_dh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.floor.f16(half %a)
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1719,6 +2931,16 @@ define double @fcvtms_ds_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1736,6 +2958,16 @@ define float @fcvtms_sd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1752,6 +2984,16 @@ define float @fcvtms_ss_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1768,6 +3010,16 @@ define double @fcvtms_dd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtms_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -1785,6 +3037,16 @@ define float @fcvtmu_sh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtmu s0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtmu s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtmu s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.floor.f16(half %a)
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1802,6 +3064,16 @@ define double @fcvtmu_dh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtmu d0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtmu d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtmu d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.floor.f16(half %a)
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1819,6 +3091,16 @@ define double @fcvtmu_ds_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtmu d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtmu d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtmu d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1836,6 +3118,16 @@ define float @fcvtmu_sd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtmu s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtmu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtmu s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1852,6 +3144,16 @@ define float @fcvtmu_ss_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.floor.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1868,6 +3170,16 @@ define double @fcvtmu_dd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtms d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtmu_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtms d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtms d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.floor.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -1885,6 +3197,16 @@ define float @fcvtps_sh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.ceil.f16(half %a)
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -1902,6 +3224,16 @@ define double @fcvtps_dh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.ceil.f16(half %a)
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -1919,6 +3251,16 @@ define double @fcvtps_ds_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -1936,6 +3278,16 @@ define float @fcvtps_sd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -1952,6 +3304,16 @@ define float @fcvtps_ss_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -1968,6 +3330,16 @@ define double @fcvtps_dd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtps_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -1985,6 +3357,16 @@ define float @fcvtpu_sh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtpu s0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtpu s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtpu s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.ceil.f16(half %a)
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -2002,6 +3384,16 @@ define double @fcvtpu_dh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtpu d0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtpu d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtpu d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.ceil.f16(half %a)
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -2019,6 +3411,16 @@ define double @fcvtpu_ds_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtpu d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtpu d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtpu d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -2036,6 +3438,16 @@ define float @fcvtpu_sd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtpu s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtpu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtpu s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -2052,6 +3464,16 @@ define float @fcvtpu_ss_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.ceil.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -2068,6 +3490,16 @@ define double @fcvtpu_dd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtps d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtpu_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtps d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtps d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.ceil.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -2085,6 +3517,16 @@ define float @fcvtzs_sh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.trunc.f16(half %a)
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -2102,6 +3544,16 @@ define double @fcvtzs_dh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.trunc.f16(half %a)
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -2119,6 +3571,16 @@ define double @fcvtzs_ds_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -2136,6 +3598,16 @@ define float @fcvtzs_sd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -2152,6 +3624,16 @@ define float @fcvtzs_ss_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -2168,6 +3650,16 @@ define double @fcvtzs_dd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzs d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzs_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzs d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzs d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
@@ -2185,6 +3677,16 @@ define float @fcvtzu_sh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_sh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_sh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.trunc.f16(half %a)
%i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
%bc = bitcast i32 %i to float
@@ -2202,6 +3704,16 @@ define double @fcvtzu_dh_simd(half %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, h0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_dh_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu d0, h0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_dh_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu d0, h0
+; CHECK-SVE-NEXT: ret
%r = call half @llvm.trunc.f16(half %a)
%i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
%bc = bitcast i64 %i to double
@@ -2219,6 +3731,16 @@ define double @fcvtzu_ds_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_ds_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_ds_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu d0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
%bc = bitcast i64 %i to double
@@ -2236,6 +3758,16 @@ define float @fcvtzu_sd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_sd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_sd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
%bc = bitcast i32 %i to float
@@ -2252,6 +3784,16 @@ define float @fcvtzu_ss_simd(float %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_ss_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_ss_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu s0, s0
+; CHECK-SVE-NEXT: ret
%r = call float @llvm.trunc.f32(float %a)
%i = call i32 @llvm.fptoui.sat.i32.f32(float %r)
%bc = bitcast i32 %i to float
@@ -2268,6 +3810,16 @@ define double @fcvtzu_dd_simd(double %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: fcvtzu d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: fcvtzu_dd_simd:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: fcvtzu d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_dd_simd:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: fcvtzu d0, d0
+; CHECK-SVE-NEXT: ret
%r = call double @llvm.trunc.f64(double %a)
%i = call i64 @llvm.fptoui.sat.i64.f64(double %r)
%bc = bitcast i64 %i to double
diff --git a/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll b/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll
index b5a045005207c..ab7d880b0d8e6 100644
--- a/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-cvtf-simd-itofp.ll
@@ -1,11 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mattr=+neon,+fullfp16,+fprcvt | FileCheck %s --check-prefixes=CHECK
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+sme,+neon,+fullfp16,+fprcvt -force-streaming | FileCheck %s --check-prefixes=CHECK-SME
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+sve,+neon,+fullfp16,+fprcvt -force-streaming-compatible | FileCheck %s --check-prefixes=CHECK-SVE
define double @scvtf_bitcast_f32_to_f64(float %f) nounwind {
; CHECK-LABEL: scvtf_bitcast_f32_to_f64:
; CHECK: // %bb.0:
; CHECK-NEXT: scvtf d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: scvtf_bitcast_f32_to_f64:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: scvtf d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: scvtf_bitcast_f32_to_f64:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: scvtf d0, s0
+; CHECK-SVE-NEXT: ret
%i = bitcast float %f to i32
%r = sitofp i32 %i to double
ret double %r
@@ -16,6 +28,16 @@ define double @ucvtf_bitcast_f32_to_f64(float %f) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: ucvtf d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: ucvtf_bitcast_f32_to_f64:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ucvtf d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: ucvtf_bitcast_f32_to_f64:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ucvtf d0, s0
+; CHECK-SVE-NEXT: ret
%i = bitcast float %f to i32
%r = uitofp i32 %i to double
ret double %r
@@ -26,6 +48,20 @@ define half @scvtf_bitcast_f32_to_f16(float %f) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: scvtf h0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: scvtf_bitcast_f32_to_f16:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.s
+; CHECK-SME-NEXT: scvtf z0.h, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: scvtf_bitcast_f32_to_f16:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0
+; CHECK-SVE-NEXT: scvtf z0.h, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 killed $z0
+; CHECK-SVE-NEXT: ret
%i = bitcast float %f to i32
%r = sitofp i32 %i to half
ret half %r
@@ -36,6 +72,20 @@ define half @ucvtf_bitcast_f32_to_f16(float %f) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: ucvtf h0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: ucvtf_bitcast_f32_to_f16:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.s
+; CHECK-SME-NEXT: ucvtf z0.h, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: ucvtf_bitcast_f32_to_f16:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0
+; CHECK-SVE-NEXT: ucvtf z0.h, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 killed $z0
+; CHECK-SVE-NEXT: ret
%i = bitcast float %f to i32
%r = uitofp i32 %i to half
ret half %r
@@ -46,6 +96,20 @@ define float @scvtf_bitcast_f64_to_f32(double %d) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: scvtf s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: scvtf_bitcast_f64_to_f32:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: scvtf z0.s, p0/m, z0.d
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f32:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-SVE-NEXT: scvtf z0.s, p0/m, z0.d
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ret
%i = bitcast double %d to i64
%r = sitofp i64 %i to float
ret float %r
@@ -56,6 +120,20 @@ define float @ucvtf_bitcast_f64_to_f32(double %d) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: ucvtf s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: ucvtf_bitcast_f64_to_f32:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: ucvtf z0.s, p0/m, z0.d
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f32:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-SVE-NEXT: ucvtf z0.s, p0/m, z0.d
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ret
%i = bitcast double %d to i64
%r = uitofp i64 %i to float
ret float %r
@@ -66,6 +144,20 @@ define half @scvtf_bitcast_f64_to_f16(double %d) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: scvtf h0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: scvtf_bitcast_f64_to_f16:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: scvtf z0.h, p0/m, z0.d
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f16:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-SVE-NEXT: scvtf z0.h, p0/m, z0.d
+; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 killed $z0
+; CHECK-SVE-NEXT: ret
%i = bitcast double %d to i64
%r = sitofp i64 %i to half
ret half %r
@@ -76,6 +168,20 @@ define half @ucvtf_bitcast_f64_to_f16(double %d) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: ucvtf h0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: ucvtf_bitcast_f64_to_f16:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: ucvtf z0.h, p0/m, z0.d
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f16:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-SVE-NEXT: ucvtf z0.h, p0/m, z0.d
+; CHECK-SVE-NEXT: // kill: def $h0 killed $h0 killed $z0
+; CHECK-SVE-NEXT: ret
%i = bitcast double %d to i64
%r = uitofp i64 %i to half
ret half %r
@@ -86,6 +192,20 @@ define float @scvtf_bitcast_f32_to_f32(float %f) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: scvtf s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: scvtf_bitcast_f32_to_f32:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.s
+; CHECK-SME-NEXT: scvtf z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: scvtf_bitcast_f32_to_f32:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0
+; CHECK-SVE-NEXT: scvtf z0.s, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ret
%i = bitcast float %f to i32
%r = sitofp i32 %i to float
ret float %r
@@ -96,6 +216,20 @@ define float @ucvtf_bitcast_f32_to_f32(float %f) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: ucvtf s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: ucvtf_bitcast_f32_to_f32:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.s
+; CHECK-SME-NEXT: ucvtf z0.s, p0/m, z0.s
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: ucvtf_bitcast_f32_to_f32:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 def $z0
+; CHECK-SVE-NEXT: ucvtf z0.s, p0/m, z0.s
+; CHECK-SVE-NEXT: // kill: def $s0 killed $s0 killed $z0
+; CHECK-SVE-NEXT: ret
%i = bitcast float %f to i32
%r = uitofp i32 %i to float
ret float %r
@@ -106,6 +240,20 @@ define double @scvtf_bitcast_f64_to_f64(double %d) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: scvtf d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: scvtf_bitcast_f64_to_f64:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: scvtf z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f64:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-SVE-NEXT: scvtf z0.d, p0/m, z0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%i = bitcast double %d to i64
%r = sitofp i64 %i to double
ret double %r
@@ -116,6 +264,20 @@ define double @ucvtf_bitcast_f64_to_f64(double %d) nounwind {
; CHECK: // %bb.0:
; CHECK-NEXT: ucvtf d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: ucvtf_bitcast_f64_to_f64:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ptrue p0.d
+; CHECK-SME-NEXT: ucvtf z0.d, p0/m, z0.d
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f64:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-SVE-NEXT: ucvtf z0.d, p0/m, z0.d
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 killed $z0
+; CHECK-SVE-NEXT: ret
%i = bitcast double %d to i64
%r = uitofp i64 %i to double
ret double %r
@@ -130,6 +292,16 @@ define double @scvtf_bitcast_f32_to_f64_strict(float %f) nounwind strictfp {
; CHECK: // %bb.0:
; CHECK-NEXT: scvtf d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: scvtf_bitcast_f32_to_f64_strict:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: scvtf d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: scvtf_bitcast_f32_to_f64_strict:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: scvtf d0, s0
+; CHECK-SVE-NEXT: ret
%i = bitcast float %f to i32
%r = call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %i, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret double %r
@@ -140,6 +312,16 @@ define double @ucvtf_bitcast_f32_to_f64_strict(float %f) nounwind strictfp {
; CHECK: // %bb.0:
; CHECK-NEXT: ucvtf d0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: ucvtf_bitcast_f32_to_f64_strict:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ucvtf d0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: ucvtf_bitcast_f32_to_f64_strict:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ucvtf d0, s0
+; CHECK-SVE-NEXT: ret
%i = bitcast float %f to i32
%r = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %i, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret double %r
@@ -150,6 +332,16 @@ define half @scvtf_bitcast_f32_to_f16_strict(float %f) nounwind strictfp {
; CHECK: // %bb.0:
; CHECK-NEXT: scvtf h0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: scvtf_bitcast_f32_to_f16_strict:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: scvtf h0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: scvtf_bitcast_f32_to_f16_strict:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: scvtf h0, s0
+; CHECK-SVE-NEXT: ret
%i = bitcast float %f to i32
%r = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %i, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret half %r
@@ -160,6 +352,16 @@ define half @ucvtf_bitcast_f32_to_f16_strict(float %f) nounwind strictfp {
; CHECK: // %bb.0:
; CHECK-NEXT: ucvtf h0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: ucvtf_bitcast_f32_to_f16_strict:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ucvtf h0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: ucvtf_bitcast_f32_to_f16_strict:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ucvtf h0, s0
+; CHECK-SVE-NEXT: ret
%i = bitcast float %f to i32
%r = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %i, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret half %r
@@ -170,6 +372,16 @@ define float @scvtf_bitcast_f64_to_f32_strict(double %d) nounwind strictfp {
; CHECK: // %bb.0:
; CHECK-NEXT: scvtf s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: scvtf_bitcast_f64_to_f32_strict:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: scvtf s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f32_strict:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: scvtf s0, d0
+; CHECK-SVE-NEXT: ret
%i = bitcast double %d to i64
%r = call float @llvm.experimental.constrained.sitofp.f32.i64(i64 %i, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret float %r
@@ -180,6 +392,16 @@ define float @ucvtf_bitcast_f64_to_f32_strict(double %d) nounwind strictfp {
; CHECK: // %bb.0:
; CHECK-NEXT: ucvtf s0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: ucvtf_bitcast_f64_to_f32_strict:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ucvtf s0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f32_strict:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ucvtf s0, d0
+; CHECK-SVE-NEXT: ret
%i = bitcast double %d to i64
%r = call float @llvm.experimental.constrained.uitofp.f32.i64(i64 %i, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret float %r
@@ -190,6 +412,16 @@ define half @scvtf_bitcast_f64_to_f16_strict(double %d) nounwind strictfp {
; CHECK: // %bb.0:
; CHECK-NEXT: scvtf h0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: scvtf_bitcast_f64_to_f16_strict:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: scvtf h0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f16_strict:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: scvtf h0, d0
+; CHECK-SVE-NEXT: ret
%i = bitcast double %d to i64
%r = call half @llvm.experimental.constrained.sitofp.f16.i64(i64 %i, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret half %r
@@ -200,6 +432,16 @@ define half @ucvtf_bitcast_f64_to_f16_strict(double %d) nounwind strictfp {
; CHECK: // %bb.0:
; CHECK-NEXT: ucvtf h0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: ucvtf_bitcast_f64_to_f16_strict:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ucvtf h0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f16_strict:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ucvtf h0, d0
+; CHECK-SVE-NEXT: ret
%i = bitcast double %d to i64
%r = call half @llvm.experimental.constrained.uitofp.f16.i64(i64 %i, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret half %r
@@ -210,6 +452,16 @@ define float @scvtf_bitcast_f32_to_f32_strict(float %f) nounwind strictfp {
; CHECK: // %bb.0:
; CHECK-NEXT: scvtf s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: scvtf_bitcast_f32_to_f32_strict:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: scvtf s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: scvtf_bitcast_f32_to_f32_strict:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: scvtf s0, s0
+; CHECK-SVE-NEXT: ret
%i = bitcast float %f to i32
%r = call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %i, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret float %r
@@ -220,6 +472,16 @@ define float @ucvtf_bitcast_f32_to_f32_strict(float %f) nounwind strictfp {
; CHECK: // %bb.0:
; CHECK-NEXT: ucvtf s0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: ucvtf_bitcast_f32_to_f32_strict:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ucvtf s0, s0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: ucvtf_bitcast_f32_to_f32_strict:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ucvtf s0, s0
+; CHECK-SVE-NEXT: ret
%i = bitcast float %f to i32
%r = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %i, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret float %r
@@ -230,6 +492,16 @@ define double @scvtf_bitcast_f64_to_f64_strict(double %d) nounwind strictfp {
; CHECK: // %bb.0:
; CHECK-NEXT: scvtf d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: scvtf_bitcast_f64_to_f64_strict:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: scvtf d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: scvtf_bitcast_f64_to_f64_strict:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: scvtf d0, d0
+; CHECK-SVE-NEXT: ret
%i = bitcast double %d to i64
%r = call double @llvm.experimental.constrained.sitofp.f64.i64(i64 %i, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret double %r
@@ -240,6 +512,16 @@ define double @ucvtf_bitcast_f64_to_f64_strict(double %d) nounwind strictfp {
; CHECK: // %bb.0:
; CHECK-NEXT: ucvtf d0, d0
; CHECK-NEXT: ret
+;
+; CHECK-SME-LABEL: ucvtf_bitcast_f64_to_f64_strict:
+; CHECK-SME: // %bb.0:
+; CHECK-SME-NEXT: ucvtf d0, d0
+; CHECK-SME-NEXT: ret
+;
+; CHECK-SVE-LABEL: ucvtf_bitcast_f64_to_f64_strict:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ucvtf d0, d0
+; CHECK-SVE-NEXT: ret
%i = bitcast double %d to i64
%r = call double @llvm.experimental.constrained.uitofp.f64.i64(i64 %i, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret double %r
diff --git a/llvm/test/CodeGen/AArch64/fp16_i16_intrinsic_scalar.ll b/llvm/test/CodeGen/AArch64/fp16_i16_intrinsic_scalar.ll
index ab502508fadbd..46c913a78c1de 100644
--- a/llvm/test/CodeGen/AArch64/fp16_i16_intrinsic_scalar.ll
+++ b/llvm/test/CodeGen/AArch64/fp16_i16_intrinsic_scalar.ll
@@ -1,5 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=aarch64 -global-isel=0 -mattr=+v8.2a,+fullfp16 | FileCheck %s
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+sme,+neon,+fullfp16,+fprcvt -force-streaming | FileCheck %s --check-prefixes=CHECK
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+sve,+neon,+fullfp16,+fprcvt -force-streaming-compatible | FileCheck %s --check-prefixes=CHECK-SVE
; Test f16 -> i16 NEON intrinics, currently only supported in SDAG.
; Should be merged with fp16_intrinsic_scalar_1op.ll once there is
@@ -23,6 +25,12 @@ define i16 @fcvtzs_intrinsic_i16(half %a) {
; CHECK-NEXT: fcvtzs h0, h0
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzs_intrinsic_i16:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: fcvtzs h0, h0
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
entry:
%fcvt = tail call i16 @llvm.aarch64.neon.fcvtzs.i16.f16(half %a)
ret i16 %fcvt
@@ -34,6 +42,12 @@ define i16 @fcvtzu_intrinsic_i16(half %a) {
; CHECK-NEXT: fcvtzu h0, h0
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtzu_intrinsic_i16:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: fcvtzu h0, h0
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
entry:
%fcvt = tail call i16 @llvm.aarch64.neon.fcvtzu.i16.f16(half %a)
ret i16 %fcvt
@@ -45,6 +59,12 @@ define i16 @fcvtas_intrinsic_i16(half %a) {
; CHECK-NEXT: fcvtas h0, h0
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtas_intrinsic_i16:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: fcvtas h0, h0
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
entry:
%fcvt = tail call i16 @llvm.aarch64.neon.fcvtas.i16.f16(half %a)
ret i16 %fcvt
@@ -56,6 +76,12 @@ define i16 @fcvtau_intrinsic_i16(half %a) {
; CHECK-NEXT: fcvtau h0, h0
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtau_intrinsic_i16:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: fcvtau h0, h0
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
entry:
%fcvt = tail call i16 @llvm.aarch64.neon.fcvtau.i16.f16(half %a)
ret i16 %fcvt
@@ -67,6 +93,12 @@ define i16 @fcvtms_intrinsic_i16(half %a) {
; CHECK-NEXT: fcvtms h0, h0
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtms_intrinsic_i16:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: fcvtms h0, h0
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
entry:
%fcvt = tail call i16 @llvm.aarch64.neon.fcvtms.i16.f16(half %a)
ret i16 %fcvt
@@ -78,6 +110,12 @@ define i16 @fcvtmu_intrinsic_i16(half %a) {
; CHECK-NEXT: fcvtmu h0, h0
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtmu_intrinsic_i16:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: fcvtmu h0, h0
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
entry:
%fcvt = tail call i16 @llvm.aarch64.neon.fcvtmu.i16.f16(half %a)
ret i16 %fcvt
@@ -89,6 +127,12 @@ define i16 @fcvtns_intrinsic_i16(half %a) {
; CHECK-NEXT: fcvtns h0, h0
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtns_intrinsic_i16:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: fcvtns h0, h0
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
entry:
%fcvt = tail call i16 @llvm.aarch64.neon.fcvtns.i16.f16(half %a)
ret i16 %fcvt
@@ -100,6 +144,12 @@ define i16 @fcvtnu_intrinsic_i16(half %a) {
; CHECK-NEXT: fcvtnu h0, h0
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtnu_intrinsic_i16:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: fcvtnu h0, h0
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
entry:
%fcvt = tail call i16 @llvm.aarch64.neon.fcvtnu.i16.f16(half %a)
ret i16 %fcvt
@@ -111,6 +161,12 @@ define i16 @fcvtps_intrinsic_i16(half %a) {
; CHECK-NEXT: fcvtps h0, h0
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtps_intrinsic_i16:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: fcvtps h0, h0
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
entry:
%fcvt = tail call i16 @llvm.aarch64.neon.fcvtps.i16.f16(half %a)
ret i16 %fcvt
@@ -122,6 +178,12 @@ define i16 @fcvtpu_intrinsic_i16(half %a) {
; CHECK-NEXT: fcvtpu h0, h0
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
+;
+; CHECK-SVE-LABEL: fcvtpu_intrinsic_i16:
+; CHECK-SVE: // %bb.0: // %entry
+; CHECK-SVE-NEXT: fcvtpu h0, h0
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
entry:
%fcvt = tail call i16 @llvm.aarch64.neon.fcvtpu.i16.f16(half %a)
ret i16 %fcvt
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