[llvm] [AMDGPU][SIInsertWaitcnts][NFC] Clean up loop (PR #179572)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 4 08:10:37 PST 2026
================
@@ -3010,35 +3010,33 @@ bool SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF,
MachineInstr *OldWaitcntInstr = nullptr;
AtomicRMWState RMWState = AtomicRMWState::NotInBlock;
- for (MachineBasicBlock::instr_iterator Iter = Block.instr_begin(),
- E = Block.instr_end();
- Iter != E;) {
+ // NOTE: we may erase Inst and/or may append instrs after Inst while iterating
+ for (MachineBasicBlock::instr_iterator Iter = Block.instr_begin();
+ Iter != Block.instr_end(); ++Iter) {
MachineInstr &Inst = *Iter;
- if (Inst.isMetaInstruction()) {
- ++Iter;
+ if (Inst.isMetaInstruction())
continue;
- }
// Get the atomic RMW block state for current instruction.
RMWState = getAtomicRMWState(Inst, RMWState);
// Track pre-existing waitcnts that were added in earlier iterations or by
// the memory legalizer.
if (isWaitInstr(Inst) ||
(IsExpertMode && Inst.getOpcode() == AMDGPU::S_WAITCNT_DEPCTR)) {
- ++Iter;
bool IsSoftXcnt = isSoftXcnt(Inst);
// The Memory Legalizer conservatively inserts a soft xcnt before each
// atomic RMW operation. However, for sequences of back-to-back atomic
// RMWs, only the first s_wait_xcnt insertion is necessary. Optimize away
// the redundant soft xcnts when we're inside an atomic RMW block.
- if (Iter != E && IsSoftXcnt) {
+ if (&Inst != &Block.back() && IsSoftXcnt) {
// Check if the next instruction can potentially change the atomic RMW
// state.
- RMWState = getAtomicRMWState(*Iter, RMWState);
+ RMWState = getAtomicRMWState(*Inst.getNextNode(), RMWState);
}
if (IsSoftXcnt && RMWState == AtomicRMWState::InsideBlock) {
// Delete this soft xcnt.
+ --Iter;
----------------
vporpo wrote:
also this doesn't look safe if we are about to delete the first instruction
https://github.com/llvm/llvm-project/pull/179572
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