[llvm] [CodeGen] Remove unused first operand of SUBREG_TO_REG (PR #179690)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 4 07:41:16 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-regalloc
Author: Jay Foad (jayfoad)
<details>
<summary>Changes</summary>
The first input operand of SUBREG_TO_REG was an immediate that most
targets set to 0. In practice it had no effect on codegen. Remove it.
---
Patch is 369.40 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/179690.diff
154 Files Affected:
- (modified) llvm/docs/MIRLangRef.rst (+2-2)
- (modified) llvm/include/llvm/CodeGen/MachineInstr.h (+1-1)
- (modified) llvm/include/llvm/Support/TargetOpcodes.def (+4-4)
- (modified) llvm/include/llvm/Target/Target.td (+1-1)
- (modified) llvm/lib/CodeGen/ExpandPostRAPseudos.cpp (+9-11)
- (modified) llvm/lib/CodeGen/MachineFunction.cpp (+2-2)
- (modified) llvm/lib/CodeGen/PeepholeOptimizer.cpp (+7-7)
- (modified) llvm/lib/CodeGen/RegisterCoalescer.cpp (+3-3)
- (modified) llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (+19-14)
- (modified) llvm/lib/CodeGen/TargetRegisterInfo.cpp (+2-2)
- (modified) llvm/lib/CodeGen/TwoAddressInstructionPass.cpp (+2-2)
- (modified) llvm/lib/Target/AArch64/AArch64FastISel.cpp (-9)
- (modified) llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (+7-11)
- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+1-1)
- (modified) llvm/lib/Target/AArch64/AArch64InstrAtomics.td (+13-13)
- (modified) llvm/lib/Target/AArch64/AArch64InstrFormats.td (+11-11)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.cpp (+9-13)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+107-115)
- (modified) llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp (+8-10)
- (modified) llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td (+2-2)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp (+4-16)
- (modified) llvm/lib/Target/AArch64/SVEInstrFormats.td (+11-11)
- (modified) llvm/lib/Target/ARM/ARMInstrNEON.td (+4-8)
- (modified) llvm/lib/Target/BPF/BPFInstrInfo.td (+6-6)
- (modified) llvm/lib/Target/BPF/BPFMIPeephole.cpp (+4-2)
- (modified) llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp (+1-1)
- (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp (-1)
- (modified) llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td (+10-10)
- (modified) llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td (+14-14)
- (modified) llvm/lib/Target/MSP430/MSP430InstrInfo.td (+2-2)
- (modified) llvm/lib/Target/Mips/Mips64r6InstrInfo.td (+4-4)
- (modified) llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp (+4-10)
- (modified) llvm/lib/Target/Mips/MipsSEISelLowering.cpp (-4)
- (modified) llvm/lib/Target/PowerPC/PPCISelLowering.cpp (-1)
- (modified) llvm/lib/Target/PowerPC/PPCInstrP10.td (+2-2)
- (modified) llvm/lib/Target/PowerPC/PPCInstrVSX.td (+137-155)
- (modified) llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp (+5-9)
- (modified) llvm/lib/Target/PowerPC/PPCVSXWACCCopy.cpp (-2)
- (modified) llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp (-4)
- (modified) llvm/lib/Target/X86/X86FastISel.cpp (+8-6)
- (modified) llvm/lib/Target/X86/X86ISelDAGToDAG.cpp (+9-12)
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+2-5)
- (modified) llvm/lib/Target/X86/X86InstrAVX512.td (+32-32)
- (modified) llvm/lib/Target/X86/X86InstrCompiler.td (+18-26)
- (modified) llvm/lib/Target/X86/X86InstrExtension.td (+6-6)
- (modified) llvm/lib/Target/X86/X86InstrInfo.cpp (+8-16)
- (modified) llvm/lib/Target/X86/X86InstrMisc.td (+4-8)
- (modified) llvm/lib/Target/X86/X86InstrSSE.td (+10-10)
- (modified) llvm/lib/Target/X86/X86InstrSystem.td (+2-2)
- (modified) llvm/lib/Target/X86/X86InstrVecCompiler.td (+1-1)
- (modified) llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp (-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/166563.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir (+9-9)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-swap-compare-operands.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-constrain-new-regop.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir (+4-4)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-build-vector.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-cmp.mir (+5-5)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir (+3-3)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-fp-index-load.mir (+12-12)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir (+3-3)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir (+3-3)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-ptr-add.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-reduce-add.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir (+7-7)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-shift-imm.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-truncstore-atomic.mir (+3-3)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-zext-as-copy.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir (+3-3)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/xro-addressing-mode-constant.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-limit-size.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes-with-call.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/aarch64-combine-gather-lanes.mir (+22-22)
- (modified) llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals-1.mir (+5-5)
- (modified) llvm/test/CodeGen/AArch64/aarch64-swp-ws-live-intervals.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/addsub-24bit-imm.mir (+3-3)
- (modified) llvm/test/CodeGen/AArch64/addsub.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/bf16_fast_math.ll (+35-35)
- (modified) llvm/test/CodeGen/AArch64/coalescer-drop-subreg-to-reg-imm-ops.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/instr-ref-ldv.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/loop-sink.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/peephole-insert-subreg.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/peephole-movd.mir (+4-4)
- (modified) llvm/test/CodeGen/AArch64/peephole-sxtw.mir (+5-5)
- (modified) llvm/test/CodeGen/AArch64/ptrauth-isel.ll (+5-5)
- (modified) llvm/test/CodeGen/AArch64/ptrauth-isel.mir (+4-4)
- (modified) llvm/test/CodeGen/AArch64/redundant-orrwrs-from-zero-extend.mir (+2-2)
- (modified) llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir (+4-4)
- (modified) llvm/test/CodeGen/AArch64/sink-and-fold-clear-kill-flags.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/sms-instruction-scheduled-at-correct-cycle.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions2.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/sms-regpress.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/subreg_to_reg_coalescing_issue.mir (+1-1)
- (modified) llvm/test/CodeGen/AArch64/zext-reg-coalesce.mir (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/mi-simplify-code.mir (+4-4)
- (modified) llvm/test/CodeGen/PowerPC/subreg-coalescer.mir (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/xxinsertw.ll (+3-3)
- (modified) llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir (+3-3)
- (modified) llvm/test/CodeGen/X86/GlobalISel/select-ext.mir (+4-4)
- (modified) llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir (+1-1)
- (modified) llvm/test/CodeGen/X86/apx/foldimmediate.mir (+2-2)
- (modified) llvm/test/CodeGen/X86/callbr-asm-different-indirect-target.mir (+2-2)
- (modified) llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir (+1-1)
- (modified) llvm/test/CodeGen/X86/coalescer-implicit-def-regression.mir (+1-1)
- (modified) llvm/test/CodeGen/X86/expand-post-ra-pseudo.mir (+1-1)
- (modified) llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir (+1-1)
- (modified) llvm/test/CodeGen/X86/foldimmediate.mir (+2-2)
- (modified) llvm/test/CodeGen/X86/opt_phis2.mir (+1-1)
- (modified) llvm/test/CodeGen/X86/peephole-test-after-add.mir (+6-6)
- (modified) llvm/test/CodeGen/X86/peephole.mir (+2-2)
- (modified) llvm/test/CodeGen/X86/pr57673.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/regalloc-fast-missing-live-out-spill.mir (+4-4)
- (modified) llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir (+1-1)
- (modified) llvm/test/CodeGen/X86/statepoint-invoke-ra.mir (+1-1)
- (modified) llvm/test/CodeGen/X86/statepoint-vreg-details.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/subreg-fail.mir (+2-2)
- (modified) llvm/test/CodeGen/X86/tail-dup-asm-goto.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/tail-dup-pred-succ-size.mir (+30-30)
- (modified) llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir (+2-2)
- (modified) llvm/test/DebugInfo/MIR/InstrRef/x86-cmov-converter.mir (+1-1)
- (modified) llvm/test/DebugInfo/MIR/X86/machine-cse.mir (+2-2)
- (modified) llvm/test/DebugInfo/X86/salvage-add-node-indirect.ll (+2-2)
- (modified) llvm/test/TableGen/GlobalISelEmitter/Subreg.td (+3-4)
- (modified) llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_asm_mir_mixed.ll.expected (+1-1)
- (modified) llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_isel.ll.expected (+16-16)
- (modified) llvm/utils/TableGen/GlobalISelEmitter.cpp (+6-6)
``````````diff
diff --git a/llvm/docs/MIRLangRef.rst b/llvm/docs/MIRLangRef.rst
index efb20520db1b1..f7df57d05baa0 100644
--- a/llvm/docs/MIRLangRef.rst
+++ b/llvm/docs/MIRLangRef.rst
@@ -495,13 +495,13 @@ In ``AArch64RegisterInfo.td``:
def sub_32 : SubRegIndex<32>;
-If the third operand is an immediate with the value ``15`` (a target-dependent
+If the second operand is an immediate with the value ``15`` (a target-dependent
value), based on the instruction's opcode and the operand's index the operand
will be printed as ``%subreg.sub_32``:
.. code-block:: text
- %1:gpr64 = SUBREG_TO_REG 0, %0, %subreg.sub_32
+ %1:gpr64 = SUBREG_TO_REG %0, %subreg.sub_32
For integers larger than 64 bits, we use a special machine operand, ``MO_CImmediate``,
which stores the immediate in a ``ConstantInt`` using an ``APInt`` (LLVM's
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index 873cad4953541..29da32c931eea 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -672,7 +672,7 @@ class MachineInstr
return true;
if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
return true;
- if (isSubregToReg() && OpIdx == 3)
+ if (isSubregToReg() && OpIdx == 2)
return true;
return false;
}
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 3217ffafc235a..119e7c69efe89 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -62,10 +62,10 @@ HANDLE_TARGET_OPCODE(IMPLICIT_DEF)
HANDLE_TARGET_OPCODE(INIT_UNDEF)
/// SUBREG_TO_REG - Assert the value of bits in a super register.
-/// The result of this instruction is the value of the second operand inserted
-/// into the subregister specified by the third operand. All other bits are
-/// assumed to be equal to the bits in the immediate integer constant in the
-/// first operand. This instruction just communicates information; No code
+/// The result of this instruction is the value of the first operand inserted
+/// into the subregister specified by the second operand. All other bits are
+/// assumed to be zero.
+/// This instruction just communicates information; No code
/// should be generated.
/// This is typically used after an instruction where the write to a subregister
/// implicitly cleared the bits in the super registers.
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index abe3a7d1701ee..3d3cfe6948ded 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -1291,7 +1291,7 @@ def INIT_UNDEF : StandardPseudoInstruction {
}
def SUBREG_TO_REG : StandardPseudoInstruction {
let OutOperandList = (outs unknown:$dst);
- let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
+ let InOperandList = (ins unknown:$subsrc, i32imm:$subidx);
let AsmString = "";
let hasSideEffects = false;
}
diff --git a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
index 9692420c7020b..94e7ee4fa0855 100644
--- a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
+++ b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
@@ -75,15 +75,14 @@ INITIALIZE_PASS(ExpandPostRALegacy, DEBUG_TYPE,
bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
MachineBasicBlock *MBB = MI->getParent();
- assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
- MI->getOperand(1).isImm() &&
- (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
- MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
+ assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
+ MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
+ MI->getOperand(2).isImm() && "Invalid subreg_to_reg");
Register DstReg = MI->getOperand(0).getReg();
- Register InsReg = MI->getOperand(2).getReg();
- assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
- unsigned SubIdx = MI->getOperand(3).getImm();
+ Register InsReg = MI->getOperand(1).getReg();
+ assert(!MI->getOperand(1).getSubReg() && "SubIdx on physreg?");
+ unsigned SubIdx = MI->getOperand(2).getImm();
assert(SubIdx != 0 && "Invalid index for insert_subreg");
Register DstSubReg = TRI->getSubReg(DstReg, SubIdx);
@@ -98,17 +97,16 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
if (MI->allDefsAreDead() || DstSubReg == InsReg) {
// No need to insert an identity copy instruction.
// Watch out for case like this:
- // %rax = SUBREG_TO_REG 0, killed %eax, 3
+ // %rax = SUBREG_TO_REG killed %eax, 3
// We must leave %rax live.
MI->setDesc(TII->get(TargetOpcode::KILL));
- MI->removeOperand(3); // SubIdx
- MI->removeOperand(1); // Imm
+ MI->removeOperand(2); // SubIdx
LLVM_DEBUG(dbgs() << "subreg: replaced by: " << *MI);
return true;
}
TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
- MI->getOperand(2).isKill());
+ MI->getOperand(1).isKill());
// Implicitly define DstReg for subsequent uses.
MachineBasicBlock::iterator CopyMI = MI;
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index 8d7694537e07d..fb35c7e62dad6 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -1119,8 +1119,8 @@ auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI)
SubReg = Cpy.getOperand(1).getSubReg();
} else if (Cpy.isSubregToReg()) {
OldReg = Cpy.getOperand(0).getReg();
- NewReg = Cpy.getOperand(2).getReg();
- SubReg = Cpy.getOperand(3).getImm();
+ NewReg = Cpy.getOperand(1).getReg();
+ SubReg = Cpy.getOperand(2).getImm();
} else {
auto CopyDetails = *TII.isCopyInstr(Cpy);
const MachineOperand &Src = *CopyDetails.Source;
diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
index a28bdd3aefc4e..da30f2d0c0dfc 100644
--- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp
+++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -833,14 +833,14 @@ bool PeepholeOptimizer::optimizeExtInstr(
//
// %reg1025 = <sext> %reg1024
// ...
- // %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
+ // %reg1026 = SUBREG_TO_REG %reg1024, 4
//
// into this:
//
// %reg1025 = <sext> %reg1024
// ...
// %reg1027 = COPY %reg1025:4
- // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
+ // %reg1026 = SUBREG_TO_REG %reg1027, 4
//
// The problem here is that SUBREG_TO_REG is there to assert that an
// implicit zext occurs. It doesn't insert a zext instruction. If we allow
@@ -2131,21 +2131,21 @@ ValueTrackerResult ValueTracker::getNextSourceFromExtractSubreg() {
ValueTrackerResult ValueTracker::getNextSourceFromSubregToReg() {
assert(Def->isSubregToReg() && "Invalid definition");
// We are looking at:
- // Def = SUBREG_TO_REG Imm, v0, sub0
+ // Def = SUBREG_TO_REG v0, sub0
// Bail if we have to compose sub registers.
// If DefSubReg != sub0, we would have to check that all the bits
// we track are included in sub0 and if yes, we would have to
// determine the right subreg in v0.
- if (DefSubReg != Def->getOperand(3).getImm())
+ if (DefSubReg != Def->getOperand(2).getImm())
return ValueTrackerResult();
// Bail if we have to compose sub registers.
// Likewise, if v0.subreg != 0, we would have to compose it with sub0.
- if (Def->getOperand(2).getSubReg())
+ if (Def->getOperand(1).getSubReg())
return ValueTrackerResult();
- return ValueTrackerResult(Def->getOperand(2).getReg(),
- Def->getOperand(3).getImm());
+ return ValueTrackerResult(Def->getOperand(1).getReg(),
+ Def->getOperand(2).getImm());
}
/// Explore each PHI incoming operand and return its sources.
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 527ecca6eab47..586c27b7e3baf 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -430,9 +430,9 @@ INITIALIZE_PASS_END(RegisterCoalescerLegacy, "register-coalescer",
} else if (MI->isSubregToReg()) {
Dst = MI->getOperand(0).getReg();
DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),
- MI->getOperand(3).getImm());
- Src = MI->getOperand(2).getReg();
- SrcSub = MI->getOperand(2).getSubReg();
+ MI->getOperand(2).getImm());
+ Src = MI->getOperand(1).getReg();
+ SrcSub = MI->getOperand(1).getSubReg();
} else
return false;
return true;
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index bb203f6367b5b..d9d847d747334 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -574,10 +574,17 @@ void InstrEmitter::EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap,
}
} else if (Opc == TargetOpcode::INSERT_SUBREG ||
Opc == TargetOpcode::SUBREG_TO_REG) {
- SDValue N0 = Node->getOperand(0);
- SDValue N1 = Node->getOperand(1);
- SDValue N2 = Node->getOperand(2);
- unsigned SubIdx = N2->getAsZExtVal();
+ SDValue Reg;
+ SDValue SubReg;
+ unsigned SubIdx;
+ if (Opc == TargetOpcode::INSERT_SUBREG) {
+ Reg = Node->getOperand(0);
+ SubReg = Node->getOperand(1);
+ SubIdx = Node->getOperand(2)->getAsZExtVal();
+ } else {
+ SubReg = Node->getOperand(0);
+ SubIdx = Node->getOperand(1)->getAsZExtVal();
+ }
// Figure out the register class to create for the destreg. It should be
// the largest legal register class supporting SubIdx sub-registers.
@@ -605,17 +612,15 @@ void InstrEmitter::EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap,
MachineInstrBuilder MIB =
BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
- // If creating a subreg_to_reg, then the first input operand
- // is an implicit value immediate, otherwise it's a register
- if (Opc == TargetOpcode::SUBREG_TO_REG) {
- const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
- MIB.addImm(SD->getZExtValue());
- } else
- AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
- IsClone, IsCloned);
+ // If creating an insert_subreg, then the first input operand
+ // is a register
+ if (Reg) {
+ AddOperand(MIB, Reg, 0, nullptr, VRBaseMap, /*IsDebug=*/false, IsClone,
+ IsCloned);
+ }
// Add the subregister being inserted
- AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
- IsClone, IsCloned);
+ AddOperand(MIB, SubReg, 0, nullptr, VRBaseMap, /*IsDebug=*/false, IsClone,
+ IsCloned);
MIB.addImm(SubIdx);
MBB->insert(InsertPos, MIB);
} else
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index cffb3ed1b8779..a56285679929e 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -646,7 +646,7 @@ TargetRegisterInfo::lookThruCopyLike(Register SrcReg,
CopySrcReg = MI->getOperand(1).getReg();
else {
assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
- CopySrcReg = MI->getOperand(2).getReg();
+ CopySrcReg = MI->getOperand(1).getReg();
}
if (!CopySrcReg.isVirtual())
@@ -669,7 +669,7 @@ Register TargetRegisterInfo::lookThruSingleUseCopyChain(
CopySrcReg = MI->getOperand(1).getReg();
else {
assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
- CopySrcReg = MI->getOperand(2).getReg();
+ CopySrcReg = MI->getOperand(1).getReg();
}
// Continue only if the next definition in the chain is for a virtual
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index ff339d4a23915..fe67e434a4de3 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -357,10 +357,10 @@ bool TwoAddressInstructionImpl::isCopyToReg(MachineInstr &MI, Register &SrcReg,
bool &IsDstPhys) const {
SrcReg = 0;
DstReg = 0;
- if (MI.isCopy()) {
+ if (MI.isCopy() || MI.isSubregToReg()) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
- } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
+ } else if (MI.isInsertSubreg()) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(2).getReg();
} else {
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
index 7cd32ebe2e2f7..8c0377fa5550f 100644
--- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp
@@ -484,7 +484,6 @@ Register AArch64FastISel::materializeGV(const GlobalValue *GV) {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(TargetOpcode::SUBREG_TO_REG))
.addDef(Result64)
- .addImm(0)
.addReg(ResultReg, RegState::Kill)
.addImm(AArch64::sub_32);
return Result64;
@@ -1873,7 +1872,6 @@ Register AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr,
Register Reg64 = createResultReg(&AArch64::GPR64RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(AArch64::SUBREG_TO_REG), Reg64)
- .addImm(0)
.addReg(ResultReg, getKillRegState(true))
.addImm(AArch64::sub_32);
ResultReg = Reg64;
@@ -4031,7 +4029,6 @@ Register AArch64FastISel::emiti1Ext(Register SrcReg, MVT DestVT, bool IsZExt) {
Register Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(AArch64::SUBREG_TO_REG), Reg64)
- .addImm(0)
.addReg(ResultReg)
.addImm(AArch64::sub_32);
ResultReg = Reg64;
@@ -4178,7 +4175,6 @@ Register AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, Register Op0,
Register TmpReg = MRI.createVirtualRegister(RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(AArch64::SUBREG_TO_REG), TmpReg)
- .addImm(0)
.addReg(Op0)
.addImm(AArch64::sub_32);
Op0 = TmpReg;
@@ -4295,7 +4291,6 @@ Register AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, Register Op0,
Register TmpReg = MRI.createVirtualRegister(RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(AArch64::SUBREG_TO_REG), TmpReg)
- .addImm(0)
.addReg(Op0)
.addImm(AArch64::sub_32);
Op0 = TmpReg;
@@ -4401,7 +4396,6 @@ Register AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, Register Op0,
Register TmpReg = MRI.createVirtualRegister(RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(AArch64::SUBREG_TO_REG), TmpReg)
- .addImm(0)
.addReg(Op0)
.addImm(AArch64::sub_32);
Op0 = TmpReg;
@@ -4459,7 +4453,6 @@ Register AArch64FastISel::emitIntExt(MVT SrcVT, Register SrcReg, MVT DestVT,
Register Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(AArch64::SUBREG_TO_REG), Src64)
- .addImm(0)
.addReg(SrcReg)
.addImm(AArch64::sub_32);
SrcReg = Src64;
@@ -4556,7 +4549,6 @@ bool AArch64FastISel::optimizeIntExtLoad(const Instruction *I, MVT RetVT,
Register Reg64 = createResultReg(&AArch64::GPR64RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(AArch64::SUBREG_TO_REG), Reg64)
- .addImm(0)
.addReg(Reg, getKillRegState(true))
.addImm(AArch64::sub_32);
Reg = Reg64;
@@ -4599,7 +4591,6 @@ bool AArch64FastISel::selectIntExt(const Instruction *I) {
Register ResultReg = createResultReg(&AArch64::GPR64RegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(AArch64::SUBREG_TO_REG), ResultReg)
- .addImm(0)
.addReg(SrcReg)
.addImm(AArch64::sub_32);
SrcReg = ResultReg;
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 0fb2b6493e061..5a4f00ea718fb 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -1756,12 +1756,9 @@ bool AArch64DAGToDAGISel::tryIndexedLoad(SDNode *N) {
SDValue LoadedVal = SDValue(Res, 1);
if (InsertTo64) {
SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
- LoadedVal =
- SDValue(CurDAG->getMachineNode(
- AArch64::SUBREG_TO_REG, dl, MVT::i64,
- CurDAG->getTargetConstant(0, dl, MVT::i64), LoadedVal,
- SubReg),
- 0);
+ LoadedVal = SDValue(CurDAG->getMachineNode(AArch64::SUBREG_TO_REG, dl,
+ MVT::i64, LoadedVal, SubReg),
+ 0);
}
ReplaceUses(SDValue(N, 0), LoadedVal);
@@ -3989,9 +3986,8 @@ bool AArch64DAGToDAGISel::tryShiftAmountMod(SDNode *N) {
NewShiftAmt = narrowIfNeeded(CurDAG, NewShiftAmt);
else if (VT == MVT::i64 && NewShiftAmt->getValueType(0) == MVT::i32) {
SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, DL, MVT::i32);
- MachineSDNode *Ext = CurDAG->getMachineNode(
- AArch64::SUBREG_TO_REG, DL, VT,
- CurDAG->getTargetConstant(0, DL, MVT::i64), NewShiftAmt, SubReg);
+ MachineSDNode *Ext = CurDAG->getMachineNode(AArch64::SUBREG_TO_REG, DL, VT,
+ NewShiftAmt, SubReg);
NewShiftAmt = SDValue(Ext, 0);
}
@@ -4710,8 +4706,8 @@ bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) {
SDValue MOVIV = SDValue(MOV, 0);
SDValue ZSub = CurDAG->getTargetConstant(AArch64::zsub, DL, MVT::i32);
- SDNode *SubRegToReg = CurDAG->getMachineNode(AArch64::SUBREG_TO_REG, DL,
- VT, Zero, MOVIV, ZSub);
+ SDNode *SubRegToReg =
+ CurDAG->getMachineNode(AArch64::SUBREG_TO_REG, DL, VT, MOVIV, ZSub);
R1 = N1->getOperand(1);
R2 = SDValue(SubRegToReg, 0);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 840298ff965e1..ea29f89d13f17 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -3378,7 +3378,7 @@ static const MachineInstr *stripVRegCopies(const MachineRegisterInfo &MRI,
continue;
}
if (Opcode == AArch64::SUBREG_TO_REG) {
- Reg = DefMI->getOperand(2).getReg();
+ Reg = DefMI->getOperand(1).getReg();
continue;
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
index 5d9215dd71233..21982300f5213 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td
@@ -313,19 +313,19 @@ def ldxr_8 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{
}
def : Pat<(ldxr_1 GPR64sp:$addr),
- (SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>;
+ (SUBREG_TO_REG (LDXRB GPR64sp:$addr), sub_32)>;
def : Pat<(ldxr_2 GPR64sp:$addr),
- (SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>;
+ (SUBREG_TO_REG (LDXRH GPR64sp:$addr), sub_32)>;
def : Pat<(ldxr_4 GPR64sp:$addr),
- (SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>;
+ (SUBREG_TO_REG (LDXRW GPR64sp:$addr), sub_32)>;
def : Pat<(ldxr_8 GPR64sp:$addr), (LDXRX GPR64sp:$addr)>;
def : Pat<(and (ldxr_1 GPR64sp:$addr), 0xff),
- (SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>;
+ (SUBREG_TO_REG (LDXRB GPR64sp:$addr), sub_32)>;
def : Pat<(and (ldxr_2 GPR64sp:$addr), 0xffff),
- (SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>;
+ (SUBREG_TO_REG (LDXRH GPR64sp:$addr), sub_32)>;
def : Pat<(and (ldxr_4 GPR64sp:$addr), 0xffffffff),
- (SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>;
+ (SUBREG_TO_REG...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/179690
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