[llvm] Add clmul zext AArch64 lowering tests (PR #179641)
Matthew Devereau via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 4 07:10:31 PST 2026
================
@@ -455,4 +455,797 @@ define <2 x i32> @clmul_v2i32_neon(<2 x i32> %x, <2 x i32> %y) {
; ret <1 x i64> %a
; }
-attributes #0 = { "target-features"="+aes" }
\ No newline at end of file
+define <16 x i8> @clmul_v16i8_neon_zext(<16 x i4> %x, <16 x i4> %y) {
+; CHECK-LABEL: clmul_v16i8_neon_zext:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v2.16b, #15
+; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: pmul v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %zextx = zext <16 x i4> %x to <16 x i8>
+ %zexty = zext <16 x i4> %y to <16 x i8>
+ %a = call <16 x i8> @llvm.clmul.v16i8(<16 x i8> %zextx, <16 x i8> %zexty)
+ ret <16 x i8> %a
+}
+
+define <8 x i8> @clmul_v8i8_neon_zext(<8 x i4> %x, <8 x i4> %y) {
+; CHECK-LABEL: clmul_v8i8_neon_zext:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v2.8b, #15
+; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
+; CHECK-NEXT: and v1.8b, v1.8b, v2.8b
+; CHECK-NEXT: pmul v0.8b, v0.8b, v1.8b
+; CHECK-NEXT: ret
+ %zextx = zext <8 x i4> %x to <8 x i8>
+ %zexty = zext <8 x i4> %y to <8 x i8>
+ %a = call <8 x i8> @llvm.clmul.v8i8(<8 x i8> %zextx, <8 x i8> %zexty)
+ ret <8 x i8> %a
+}
+
+define <8 x i16> @clmul_v8i16_neon_zext(<8 x i8> %x, <8 x i8> %y) {
+; CHECK-LABEL: clmul_v8i16_neon_zext:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v2.8h, #2
+; CHECK-NEXT: movi v3.8h, #1
+; CHECK-NEXT: movi v4.8h, #4
+; CHECK-NEXT: movi v5.8h, #8
+; CHECK-NEXT: movi v6.8h, #16
+; CHECK-NEXT: movi v7.8h, #32
+; CHECK-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-NEXT: movi v16.8h, #64
+; CHECK-NEXT: movi v17.8h, #128
+; CHECK-NEXT: and v2.16b, v1.16b, v2.16b
+; CHECK-NEXT: and v3.16b, v1.16b, v3.16b
+; CHECK-NEXT: and v4.16b, v1.16b, v4.16b
+; CHECK-NEXT: and v5.16b, v1.16b, v5.16b
+; CHECK-NEXT: and v6.16b, v1.16b, v6.16b
+; CHECK-NEXT: and v7.16b, v1.16b, v7.16b
+; CHECK-NEXT: and v16.16b, v1.16b, v16.16b
+; CHECK-NEXT: and v1.16b, v1.16b, v17.16b
+; CHECK-NEXT: xtn v2.8b, v2.8h
+; CHECK-NEXT: xtn v3.8b, v3.8h
+; CHECK-NEXT: xtn v4.8b, v4.8h
+; CHECK-NEXT: xtn v5.8b, v5.8h
+; CHECK-NEXT: xtn v6.8b, v6.8h
+; CHECK-NEXT: xtn v7.8b, v7.8h
+; CHECK-NEXT: xtn v16.8b, v16.8h
+; CHECK-NEXT: xtn v1.8b, v1.8h
+; CHECK-NEXT: umull v2.8h, v0.8b, v2.8b
+; CHECK-NEXT: umull v3.8h, v0.8b, v3.8b
+; CHECK-NEXT: umull v4.8h, v0.8b, v4.8b
+; CHECK-NEXT: umull v5.8h, v0.8b, v5.8b
+; CHECK-NEXT: umull v6.8h, v0.8b, v6.8b
+; CHECK-NEXT: umull v7.8h, v0.8b, v7.8b
+; CHECK-NEXT: umull v16.8h, v0.8b, v16.8b
+; CHECK-NEXT: umull v0.8h, v0.8b, v1.8b
+; CHECK-NEXT: eor v2.16b, v3.16b, v2.16b
+; CHECK-NEXT: eor v3.16b, v4.16b, v5.16b
+; CHECK-NEXT: eor v4.16b, v6.16b, v7.16b
+; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b
+; CHECK-NEXT: eor v3.16b, v4.16b, v16.16b
+; CHECK-NEXT: eor v1.16b, v2.16b, v3.16b
+; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: ret
+ %zextx = zext <8 x i8> %x to <8 x i16>
+ %zexty = zext <8 x i8> %y to <8 x i16>
+ %a = call <8 x i16> @llvm.clmul.v8i16(<8 x i16> %zextx, <8 x i16> %zexty)
+ ret <8 x i16> %a
+}
+
+define <4 x i16> @clmul_v4i16_neon_zext(<4 x i8> %x, <4 x i8> %y) {
+; CHECK-LABEL: clmul_v4i16_neon_zext:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v2.4h, #2
+; CHECK-NEXT: movi v3.4h, #1
+; CHECK-NEXT: movi v4.4h, #4
+; CHECK-NEXT: movi v5.4h, #8
+; CHECK-NEXT: movi v6.4h, #16
+; CHECK-NEXT: movi v7.4h, #32
+; CHECK-NEXT: bic v1.4h, #255, lsl #8
+; CHECK-NEXT: movi v16.4h, #64
+; CHECK-NEXT: bic v0.4h, #255, lsl #8
+; CHECK-NEXT: movi v17.4h, #128
+; CHECK-NEXT: and v2.8b, v1.8b, v2.8b
+; CHECK-NEXT: and v3.8b, v1.8b, v3.8b
+; CHECK-NEXT: and v4.8b, v1.8b, v4.8b
+; CHECK-NEXT: and v5.8b, v1.8b, v5.8b
+; CHECK-NEXT: and v6.8b, v1.8b, v6.8b
+; CHECK-NEXT: and v7.8b, v1.8b, v7.8b
+; CHECK-NEXT: and v16.8b, v1.8b, v16.8b
+; CHECK-NEXT: and v1.8b, v1.8b, v17.8b
+; CHECK-NEXT: mul v2.4h, v0.4h, v2.4h
+; CHECK-NEXT: mul v3.4h, v0.4h, v3.4h
+; CHECK-NEXT: mul v4.4h, v0.4h, v4.4h
+; CHECK-NEXT: mul v5.4h, v0.4h, v5.4h
+; CHECK-NEXT: mul v6.4h, v0.4h, v6.4h
+; CHECK-NEXT: mul v7.4h, v0.4h, v7.4h
+; CHECK-NEXT: mul v16.4h, v0.4h, v16.4h
+; CHECK-NEXT: mul v0.4h, v0.4h, v1.4h
+; CHECK-NEXT: eor v2.8b, v3.8b, v2.8b
+; CHECK-NEXT: eor v3.8b, v4.8b, v5.8b
+; CHECK-NEXT: eor v4.8b, v6.8b, v7.8b
+; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b
+; CHECK-NEXT: eor v3.8b, v4.8b, v16.8b
+; CHECK-NEXT: eor v1.8b, v2.8b, v3.8b
+; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
+; CHECK-NEXT: ret
+ %zextx = zext <4 x i8> %x to <4 x i16>
+ %zexty = zext <4 x i8> %y to <4 x i16>
+ %a = call <4 x i16> @llvm.clmul.v4i16(<4 x i16> %zextx, <4 x i16> %zexty)
+ ret <4 x i16> %a
+}
+
+define <4 x i32> @clmul_v4i32_neon_zext(<4 x i16> %x, <4 x i16> %y) {
+; CHECK-LABEL: clmul_v4i32_neon_zext:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v2.4s, #2
+; CHECK-NEXT: movi v3.4s, #1
+; CHECK-NEXT: movi v4.4s, #4
+; CHECK-NEXT: movi v5.4s, #8
+; CHECK-NEXT: ushll v1.4s, v1.4h, #0
+; CHECK-NEXT: movi v6.4s, #16
+; CHECK-NEXT: movi v7.4s, #32
+; CHECK-NEXT: movi v16.4s, #128
+; CHECK-NEXT: movi v17.4s, #1, lsl #8
+; CHECK-NEXT: movi v18.4s, #8, lsl #8
+; CHECK-NEXT: movi v19.4s, #16, lsl #8
+; CHECK-NEXT: movi v20.4s, #64
+; CHECK-NEXT: and v2.16b, v1.16b, v2.16b
+; CHECK-NEXT: and v3.16b, v1.16b, v3.16b
+; CHECK-NEXT: and v4.16b, v1.16b, v4.16b
+; CHECK-NEXT: and v5.16b, v1.16b, v5.16b
+; CHECK-NEXT: movi v21.4s, #2, lsl #8
+; CHECK-NEXT: movi v22.4s, #32, lsl #8
+; CHECK-NEXT: and v6.16b, v1.16b, v6.16b
+; CHECK-NEXT: and v7.16b, v1.16b, v7.16b
+; CHECK-NEXT: and v16.16b, v1.16b, v16.16b
+; CHECK-NEXT: and v17.16b, v1.16b, v17.16b
+; CHECK-NEXT: and v18.16b, v1.16b, v18.16b
+; CHECK-NEXT: and v19.16b, v1.16b, v19.16b
+; CHECK-NEXT: xtn v2.4h, v2.4s
+; CHECK-NEXT: xtn v3.4h, v3.4s
+; CHECK-NEXT: xtn v4.4h, v4.4s
+; CHECK-NEXT: xtn v5.4h, v5.4s
+; CHECK-NEXT: movi v23.4s, #4, lsl #8
+; CHECK-NEXT: movi v24.4s, #64, lsl #8
+; CHECK-NEXT: xtn v6.4h, v6.4s
+; CHECK-NEXT: xtn v7.4h, v7.4s
+; CHECK-NEXT: and v20.16b, v1.16b, v20.16b
+; CHECK-NEXT: xtn v16.4h, v16.4s
+; CHECK-NEXT: xtn v17.4h, v17.4s
+; CHECK-NEXT: and v21.16b, v1.16b, v21.16b
+; CHECK-NEXT: xtn v18.4h, v18.4s
+; CHECK-NEXT: xtn v19.4h, v19.4s
+; CHECK-NEXT: and v22.16b, v1.16b, v22.16b
+; CHECK-NEXT: umull v2.4s, v0.4h, v2.4h
+; CHECK-NEXT: umull v3.4s, v0.4h, v3.4h
+; CHECK-NEXT: umull v4.4s, v0.4h, v4.4h
+; CHECK-NEXT: umull v5.4s, v0.4h, v5.4h
+; CHECK-NEXT: movi v25.4s, #128, lsl #8
+; CHECK-NEXT: xtn v20.4h, v20.4s
+; CHECK-NEXT: xtn v21.4h, v21.4s
+; CHECK-NEXT: and v23.16b, v1.16b, v23.16b
+; CHECK-NEXT: xtn v22.4h, v22.4s
+; CHECK-NEXT: and v24.16b, v1.16b, v24.16b
+; CHECK-NEXT: umull v6.4s, v0.4h, v6.4h
+; CHECK-NEXT: umull v7.4s, v0.4h, v7.4h
+; CHECK-NEXT: umull v16.4s, v0.4h, v16.4h
+; CHECK-NEXT: umull v17.4s, v0.4h, v17.4h
+; CHECK-NEXT: umull v18.4s, v0.4h, v18.4h
+; CHECK-NEXT: umull v19.4s, v0.4h, v19.4h
+; CHECK-NEXT: eor v2.16b, v3.16b, v2.16b
+; CHECK-NEXT: eor v3.16b, v4.16b, v5.16b
+; CHECK-NEXT: and v1.16b, v1.16b, v25.16b
+; CHECK-NEXT: xtn v4.4h, v23.4s
+; CHECK-NEXT: xtn v5.4h, v24.4s
+; CHECK-NEXT: umull v20.4s, v0.4h, v20.4h
+; CHECK-NEXT: umull v21.4s, v0.4h, v21.4h
+; CHECK-NEXT: umull v22.4s, v0.4h, v22.4h
+; CHECK-NEXT: eor v6.16b, v6.16b, v7.16b
+; CHECK-NEXT: eor v7.16b, v16.16b, v17.16b
+; CHECK-NEXT: eor v2.16b, v2.16b, v3.16b
+; CHECK-NEXT: eor v16.16b, v18.16b, v19.16b
+; CHECK-NEXT: xtn v1.4h, v1.4s
+; CHECK-NEXT: umull v3.4s, v0.4h, v4.4h
+; CHECK-NEXT: umull v4.4s, v0.4h, v5.4h
+; CHECK-NEXT: eor v5.16b, v6.16b, v20.16b
+; CHECK-NEXT: eor v6.16b, v7.16b, v21.16b
+; CHECK-NEXT: eor v7.16b, v16.16b, v22.16b
+; CHECK-NEXT: umull v0.4s, v0.4h, v1.4h
+; CHECK-NEXT: eor v1.16b, v2.16b, v5.16b
+; CHECK-NEXT: eor v2.16b, v6.16b, v3.16b
+; CHECK-NEXT: eor v3.16b, v7.16b, v4.16b
+; CHECK-NEXT: eor v1.16b, v1.16b, v2.16b
+; CHECK-NEXT: eor v0.16b, v3.16b, v0.16b
+; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: ret
+ %zextx = zext <4 x i16> %x to <4 x i32>
+ %zexty = zext <4 x i16> %y to <4 x i32>
+ %a = call <4 x i32> @llvm.clmul.v4i32(<4 x i32> %zextx, <4 x i32> %zexty)
+ ret <4 x i32> %a
+}
+
+define <2 x i32> @clmul_v2i32_neon_zext(<2 x i16> %x, <2 x i16> %y) {
+; CHECK-LABEL: clmul_v2i32_neon_zext:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-NEXT: movi v3.2s, #2
+; CHECK-NEXT: movi v4.2s, #1
+; CHECK-NEXT: movi v5.2s, #4
+; CHECK-NEXT: movi v6.2s, #8
+; CHECK-NEXT: movi v7.2s, #16
+; CHECK-NEXT: movi v16.2s, #32
+; CHECK-NEXT: movi v17.2s, #64
+; CHECK-NEXT: movi v18.2s, #128
+; CHECK-NEXT: movi v19.2s, #2, lsl #8
+; CHECK-NEXT: movi v20.2s, #8, lsl #8
+; CHECK-NEXT: movi v21.2s, #128, lsl #16
+; CHECK-NEXT: and v1.8b, v1.8b, v2.8b
+; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
+; CHECK-NEXT: movi v22.2s, #8, lsl #16
+; CHECK-NEXT: movi v23.2s, #2, lsl #24
+; CHECK-NEXT: movi v25.2s, #4, lsl #24
+; CHECK-NEXT: movi v24.2s, #32, lsl #16
+; CHECK-NEXT: movi v26.2s, #8, lsl #24
+; CHECK-NEXT: and v2.8b, v1.8b, v3.8b
+; CHECK-NEXT: and v3.8b, v1.8b, v4.8b
+; CHECK-NEXT: and v4.8b, v1.8b, v5.8b
+; CHECK-NEXT: and v5.8b, v1.8b, v6.8b
+; CHECK-NEXT: and v7.8b, v1.8b, v7.8b
+; CHECK-NEXT: and v16.8b, v1.8b, v16.8b
+; CHECK-NEXT: movi v6.2s, #1, lsl #8
+; CHECK-NEXT: and v17.8b, v1.8b, v17.8b
+; CHECK-NEXT: and v18.8b, v1.8b, v18.8b
+; CHECK-NEXT: mul v2.2s, v0.2s, v2.2s
+; CHECK-NEXT: mul v3.2s, v0.2s, v3.2s
+; CHECK-NEXT: mul v4.2s, v0.2s, v4.2s
+; CHECK-NEXT: mul v5.2s, v0.2s, v5.2s
+; CHECK-NEXT: mul v7.2s, v0.2s, v7.2s
+; CHECK-NEXT: mul v16.2s, v0.2s, v16.2s
+; CHECK-NEXT: and v21.8b, v1.8b, v21.8b
+; CHECK-NEXT: and v23.8b, v1.8b, v23.8b
+; CHECK-NEXT: and v6.8b, v1.8b, v6.8b
+; CHECK-NEXT: eor v2.8b, v3.8b, v2.8b
+; CHECK-NEXT: eor v3.8b, v4.8b, v5.8b
+; CHECK-NEXT: movi v4.2s, #16, lsl #8
+; CHECK-NEXT: mul v5.2s, v0.2s, v17.2s
+; CHECK-NEXT: eor v7.8b, v7.8b, v16.8b
+; CHECK-NEXT: mul v17.2s, v0.2s, v18.2s
+; CHECK-NEXT: mul v6.2s, v0.2s, v6.2s
+; CHECK-NEXT: and v16.8b, v1.8b, v19.8b
+; CHECK-NEXT: movi v19.2s, #32, lsl #8
+; CHECK-NEXT: and v18.8b, v1.8b, v20.8b
+; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b
+; CHECK-NEXT: movi v20.2s, #64, lsl #8
+; CHECK-NEXT: mul v21.2s, v0.2s, v21.2s
+; CHECK-NEXT: and v3.8b, v1.8b, v4.8b
+; CHECK-NEXT: eor v5.8b, v7.8b, v5.8b
+; CHECK-NEXT: movi v7.2s, #2, lsl #16
+; CHECK-NEXT: movi v4.2s, #1, lsl #16
+; CHECK-NEXT: mul v16.2s, v0.2s, v16.2s
+; CHECK-NEXT: eor v6.8b, v17.8b, v6.8b
+; CHECK-NEXT: mul v18.2s, v0.2s, v18.2s
+; CHECK-NEXT: and v19.8b, v1.8b, v19.8b
+; CHECK-NEXT: movi v17.2s, #4, lsl #8
+; CHECK-NEXT: mul v3.2s, v0.2s, v3.2s
+; CHECK-NEXT: eor v2.8b, v2.8b, v5.8b
+; CHECK-NEXT: and v5.8b, v1.8b, v7.8b
+; CHECK-NEXT: movi v7.2s, #64, lsl #16
+; CHECK-NEXT: and v4.8b, v1.8b, v4.8b
+; CHECK-NEXT: eor v6.8b, v6.8b, v16.8b
+; CHECK-NEXT: mul v16.2s, v0.2s, v19.2s
+; CHECK-NEXT: movi v19.2s, #4, lsl #16
+; CHECK-NEXT: and v17.8b, v1.8b, v17.8b
+; CHECK-NEXT: eor v3.8b, v18.8b, v3.8b
+; CHECK-NEXT: and v18.8b, v1.8b, v20.8b
+; CHECK-NEXT: movi v20.2s, #1, lsl #24
+; CHECK-NEXT: and v7.8b, v1.8b, v7.8b
+; CHECK-NEXT: mul v4.2s, v0.2s, v4.2s
+; CHECK-NEXT: mul v5.2s, v0.2s, v5.2s
+; CHECK-NEXT: mul v17.2s, v0.2s, v17.2s
+; CHECK-NEXT: eor v3.8b, v3.8b, v16.8b
+; CHECK-NEXT: and v16.8b, v1.8b, v19.8b
+; CHECK-NEXT: mul v18.2s, v0.2s, v18.2s
+; CHECK-NEXT: mul v7.2s, v0.2s, v7.2s
+; CHECK-NEXT: and v20.8b, v1.8b, v20.8b
+; CHECK-NEXT: movi v19.2s, #128, lsl #8
+; CHECK-NEXT: eor v4.8b, v4.8b, v5.8b
+; CHECK-NEXT: mul v5.2s, v0.2s, v16.2s
+; CHECK-NEXT: and v16.8b, v1.8b, v22.8b
+; CHECK-NEXT: movi v22.2s, #16, lsl #16
+; CHECK-NEXT: mul v20.2s, v0.2s, v20.2s
+; CHECK-NEXT: eor v6.8b, v6.8b, v17.8b
+; CHECK-NEXT: eor v3.8b, v3.8b, v18.8b
+; CHECK-NEXT: eor v7.8b, v7.8b, v21.8b
+; CHECK-NEXT: and v17.8b, v1.8b, v19.8b
+; CHECK-NEXT: mul v18.2s, v0.2s, v23.2s
+; CHECK-NEXT: and v19.8b, v1.8b, v25.8b
+; CHECK-NEXT: and v21.8b, v1.8b, v24.8b
+; CHECK-NEXT: movi v23.2s, #32, lsl #24
+; CHECK-NEXT: eor v4.8b, v4.8b, v5.8b
+; CHECK-NEXT: mul v5.2s, v0.2s, v16.2s
+; CHECK-NEXT: and v16.8b, v1.8b, v22.8b
+; CHECK-NEXT: eor v7.8b, v7.8b, v20.8b
+; CHECK-NEXT: movi v22.2s, #16, lsl #24
+; CHECK-NEXT: movi v24.2s, #64, lsl #24
+; CHECK-NEXT: and v20.8b, v1.8b, v26.8b
+; CHECK-NEXT: mul v17.2s, v0.2s, v17.2s
+; CHECK-NEXT: mul v19.2s, v0.2s, v19.2s
+; CHECK-NEXT: mul v16.2s, v0.2s, v16.2s
+; CHECK-NEXT: eor v2.8b, v2.8b, v6.8b
+; CHECK-NEXT: mul v6.2s, v0.2s, v21.2s
+; CHECK-NEXT: eor v4.8b, v4.8b, v5.8b
+; CHECK-NEXT: eor v5.8b, v7.8b, v18.8b
+; CHECK-NEXT: movi v7.2s, #128, lsl #24
+; CHECK-NEXT: mul v18.2s, v0.2s, v20.2s
+; CHECK-NEXT: and v20.8b, v1.8b, v22.8b
+; CHECK-NEXT: and v21.8b, v1.8b, v23.8b
+; CHECK-NEXT: and v22.8b, v1.8b, v24.8b
+; CHECK-NEXT: eor v3.8b, v3.8b, v17.8b
+; CHECK-NEXT: eor v4.8b, v4.8b, v16.8b
+; CHECK-NEXT: eor v5.8b, v5.8b, v19.8b
+; CHECK-NEXT: and v1.8b, v1.8b, v7.8b
+; CHECK-NEXT: mul v7.2s, v0.2s, v20.2s
+; CHECK-NEXT: mul v16.2s, v0.2s, v21.2s
+; CHECK-NEXT: mul v17.2s, v0.2s, v22.2s
+; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b
+; CHECK-NEXT: eor v3.8b, v4.8b, v6.8b
+; CHECK-NEXT: eor v4.8b, v5.8b, v18.8b
+; CHECK-NEXT: mul v0.2s, v0.2s, v1.2s
+; CHECK-NEXT: eor v1.8b, v2.8b, v3.8b
+; CHECK-NEXT: eor v2.8b, v4.8b, v7.8b
+; CHECK-NEXT: eor v3.8b, v16.8b, v17.8b
+; CHECK-NEXT: eor v1.8b, v1.8b, v2.8b
+; CHECK-NEXT: eor v0.8b, v3.8b, v0.8b
+; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
+; CHECK-NEXT: ret
+ %zextx = zext <2 x i16> %x to <2 x i32>
+ %zexty = zext <2 x i16> %y to <2 x i32>
+ %a = call <2 x i32> @llvm.clmul.v2i32(<2 x i32> %zextx, <2 x i32> %zexty)
----------------
MDevereau wrote:
I've done this for all the neon half vector types. I added 128 tests for sve which currently crash, which i hadn't noticed. I've also used separate run lines instead of duplicated tests.
https://github.com/llvm/llvm-project/pull/179641
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