[llvm] be9ba44 - [AMDGPU] Add machineFunctionInfo to recent MIR tests (#179602)

via llvm-commits llvm-commits at lists.llvm.org
Wed Feb 4 05:12:05 PST 2026


Author: Carl Ritson
Date: 2026-02-04T22:12:01+09:00
New Revision: be9ba44256fe84654da51714b5fa8dd7b13d6937

URL: https://github.com/llvm/llvm-project/commit/be9ba44256fe84654da51714b5fa8dd7b13d6937
DIFF: https://github.com/llvm/llvm-project/commit/be9ba44256fe84654da51714b5fa8dd7b13d6937.diff

LOG: [AMDGPU] Add machineFunctionInfo to recent MIR tests (#179602)

Initialize machineFunctionInfo in recently added MIR tests to assist in
downstream testing.

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
    llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir b/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
index f401d0b515373..29bfeb8fa1bd1 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
+++ b/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
@@ -5,12 +5,13 @@
 ---
 name:            gemm_loop1
 tracksRegLiveness: true
+machineFunctionInfo:
+  isEntryFunction: true
 body:             |
   ; GFX11-LABEL: name: gemm_loop1
   ; GFX11: bb.0:
   ; GFX11-NEXT:   successors: %bb.1(0x80000000)
   ; GFX11-NEXT: {{  $}}
-  ; GFX11-NEXT:   S_WAITCNT 0
   ; GFX11-NEXT:   renamable $vgpr0 = V_MOV_B32_e32 0, implicit $exec
   ; GFX11-NEXT:   renamable $vgpr1 = V_MOV_B32_e32 0, implicit $exec
   ; GFX11-NEXT:   renamable $vgpr2 = V_MOV_B32_e32 0, implicit $exec

diff  --git a/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir b/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
index 7be5b164cd1a1..8e98d0cc27473 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
+++ b/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
@@ -16,7 +16,6 @@
   ; GFX9:       ; %bb.0:
   ; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1
   ; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3
-  ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
   ; GFX9-NEXT:    global_load_ushort v14, v[0:1], off
   ; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
   ; GFX9-NEXT:    global_load_ushort v15, v[4:5], off
@@ -74,7 +73,6 @@
   ; GFX9-TGS:       ; %bb.0:
   ; GFX9-TGS-NEXT:    ; implicit-def: $vgpr0_vgpr1
   ; GFX9-TGS-NEXT:    ; implicit-def: $vgpr2_vgpr3
-  ; GFX9-TGS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
   ; GFX9-TGS-NEXT:    global_load_ushort v14, v[0:1], off
   ; GFX9-TGS-NEXT:    ; implicit-def: $vgpr4_vgpr5
   ; GFX9-TGS-NEXT:    global_load_ushort v15, v[4:5], off
@@ -136,6 +134,8 @@
 ---
 name: test_workgroup
 tracksRegLiveness: true
+machineFunctionInfo:
+  isEntryFunction: true
 body: |
   bb.0:
     %0:sgpr_256 = IMPLICIT_DEF


        


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