[llvm] [AArch64][llvm] Remove `+d128` gating on `sysp`, `msrr` and `mrrs` instructions (PR #178912)

[Jonathan Thackray via llvm-commits]

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@@ -903,10 +903,12 @@ multiclass TLBI<string name, bit hasTLBIP, bits<3> op1, bits<4> crn, bits<4> crm
     let ExtraRequires = ["AArch64::FeatureXS"];
   }
   if !eq(hasTLBIP, true) then {
-    def : TLBIPEntry<name, op1, crn, crm, op2, needsreg, optionalreg>;
+    def : TLBIPEntry<name, op1, crn, crm, op2, needsreg, optionalreg> {
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jthackray wrote:

It's a good suggestion, but actually causes more ripple changes, as the parser has this code:
```
      std::string Name =
          std::string(TLBIP.Name) + (HasnXSQualifier ? "nXS" : "");
      std::string Str("TLBIP " + Name + " requires: ");
      setRequiredFeatureString(TLBIP.getRequiredFeatures(), Str);
```
which means changing `armv9a-sysp.s`:
```
-// CHECK-ERROR: error: instruction requires: d128
+// CHECK-ERROR: error: {{.*}} requires: xs, d128
```
all through the file. I'm updating error message handling in the subsequent PR, so I think I'll keep it like this for now, as those extra 2 lines in the parser are excised in the next PR. They're only there because we've removed `+d128` from all `sysp`s.

Also, this line will require removing in the next PR, since we need to allow "tlbid" or "d128".

https://github.com/llvm/llvm-project/pull/178912