[llvm] 071bb46 - [AMDGPU][SIRegisterInfo] Fix maxoffset calculation in buildSpillLoadStore (#179182)

[via llvm-commits]

Author: Abhinav Garg
Date: 2026-02-04T16:27:48+05:30
New Revision: 071bb466db85f52081b10d6e8d26a2c5395e2ece

URL: https://github.com/llvm/llvm-project/commit/071bb466db85f52081b10d6e8d26a2c5395e2ece
DIFF: https://github.com/llvm/llvm-project/commit/071bb466db85f52081b10d6e8d26a2c5395e2ece.diff

LOG: [AMDGPU][SIRegisterInfo] Fix maxoffset calculation in buildSpillLoadStore (#179182)

This PR addresses Maxoffset calculation bug in SIRegisterInfo. When
RemSize is non-zero, maxoffset, that needs to be encoded in the offset
field, will be equal to "Offset + Size".

---------

Co-authored-by: Abhinav Garg <abhigarg at amd.com>

Added: 
    llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir

Modified: 
    llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 96c2f6530fe4c..849498526e3ea 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1549,7 +1549,10 @@ void SIRegisterInfo::buildSpillLoadStore(
   int64_t Offset = InstOffset + MFI.getObjectOffset(Index);
   int64_t MaterializedOffset = Offset;
 
-  int64_t MaxOffset = Offset + Size + RemSize - EltSize;
+  // Maxoffset is the starting offset for the last chunk to be spilled.
+  // In case of non-zero remainder element, max offset will be the
+  // last address(offset + Size) after spilling  all the EltSize chunks.
+  int64_t MaxOffset = Offset + Size - (RemSize ? 0 : EltSize);
   int64_t ScratchOffsetRegDelta = 0;
 
   if (IsFlat && EltSize > 4) {

diff  --git a/llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir b/llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir
new file mode 100644
index 0000000000000..47b920da5f0f8
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/pei-build-spill-offset-overflow-gfx950.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -verify-machineinstrs -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prologepilog -o - %s | FileCheck %s
+
+# Test that the buildSpillLoadStore does correct calculations for Maxoffset in case of
+# spill instructions. Must emit offset within 13 bit signed number range.
+
+---
+name:            test_spill_v6_offset_overflow
+tracksRegLiveness: true
+fixedStack:
+  - { id: 0, type: spill-slot, offset: 4084, size: 24, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+stack:           []
+machineFunctionInfo:
+  hasSpilledVGPRs: true
+  stackPtrOffsetReg: '$sgpr32'
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
+
+    ; CHECK-LABEL: name: test_spill_v6_offset_overflow
+    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $sgpr0 = S_ADD_I32 $sgpr32, 4084, implicit-def dead $scc
+    ; CHECK-NEXT: SCRATCH_STORE_DWORDX4_SADDR $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0, 0, 0, implicit $exec, implicit $flat_scr, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s128) into %fixed-stack.0, align 4, addrspace 5)
+    ; CHECK-NEXT: SCRATCH_STORE_DWORDX2_SADDR $vgpr4_vgpr5, killed $sgpr0, 16, 0, implicit $exec, implicit $flat_scr, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 :: (store (s64) into %fixed-stack.0 + 16, align 4, addrspace 5)
+    ; CHECK-NEXT: S_ENDPGM 0
+    SI_SPILL_AV192_SAVE $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, %fixed-stack.0, $sgpr32, 0, implicit $exec :: (store (s192) into %fixed-stack.0, align 4, addrspace 5)
+    S_ENDPGM 0
+
+...