[llvm] [RISCV] Remove codegen for trivial VP intrinsics (PR #179622)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 3 23:47:07 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Luke Lau (lukel97)
<details>
<summary>Changes</summary>
This implements the RFC discussed in https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
"Trivial" VP intrinsics which only set lanes to poison can be replaced with their non-VP counterparts without extra vsetvli toggles in the RISC-V backend now that we have RISCVVLOptimizer. And because the loop vectorizer no longer emits trivial VP intrinsics, we don't have any upstream in-tree passes that emit them.
This PR removes codegen support for these trivial intrinsics and instead expands them into their unpredicated equivalent via RISCVTTIImpl::getVPLegalizationStrategy, so any LLVM IR that uses VP intrinsics will continue to compile.
The llvm/test/CodeGen/RISCV/rvv/*-vp.ll tests are left to show how the intrinsics are expanded.
ExpandVectorPredication was missing a few FP intrinsics, so this PR also handles them in CachingVPExpander::expandPredication.
The remaining VP intrinsics that the RISC-V backend lowers are as follows:
* vp_load
* vp_gather
* experimental_vp_strided_load
* vp_load_ff
* vp_store
* vp_scatter
* experimental_vp_strided_store
* vp_udiv
* vp_sdiv
* vp_udiv
* vp_srem
* vp_urem
* vp_reduce_add
* vp_reduce_and
* vp_reduce_mul
* vp_reduce_or
* vp_reduce_xor
* vp_reduce_smax
* vp_reduce_smin
* vp_reduce_umax
* vp_reduce_umin
* vp_reduce_fadd
* vp_reduce_fmul
* vp_reduce_fmax
* vp_reduce_fmin
* vp_reduce_fmaximum
* vp_reduce_fminimum
* vp_merge
* experimental_vp_reverse
* experimental_vp_splice
* vp_cttz_elts
---
Patch is 9.67 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/179622.diff
198 Files Affected:
- (modified) llvm/lib/CodeGen/ExpandVectorPredication.cpp (+27-3)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+48-836)
- (modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h (+34)
- (modified) llvm/test/CodeGen/RISCV/rvv/abs-vp.ll (+100-125)
- (modified) llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll (+1620-1824)
- (modified) llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll (+768-952)
- (modified) llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll (+294-570)
- (modified) llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll (+766-984)
- (modified) llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll (+1061-1192)
- (modified) llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll (+994-2350)
- (modified) llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll (+21-33)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll (+74-99)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll (+1396-1562)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll (+638-803)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll (+242-488)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll (+657-4246)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll (+869-937)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll (+850-3299)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll (+242-488)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll (+215-263)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll (+215-263)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll (+24-38)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll (+26-21)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll (+65-111)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll (+26-21)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll (+65-111)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll (+24-38)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll (+334-363)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll (+4-6)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-inttoptr-ptrtoint.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint-vp.ll (+40-40)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll (+60-60)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-marith-vp.ll (+15-15)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll (+120-242)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll (+59-36)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll (+108-230)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll (+242-488)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll (+242-488)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll (+292-698)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll (+373-450)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp-mask.ll (+56-56)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll (+346-561)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp-mask.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll (+37-61)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll (+21-24)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll (+68-115)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp-mask.ll (+12-12)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll (+148-687)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll (+21-24)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll (+72-119)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp-mask.ll (+6-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll (+201-266)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll (+163-173)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll (+102-145)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll (+151-176)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll (+138-146)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll (+51-58)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll (+135-143)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll (+194-277)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll (+257-129)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll (+70-113)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll (+70-113)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll (+257-129)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll (+135-143)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll (+126-193)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll (+127-152)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll (+257-129)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll (+257-129)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll (+36-36)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll (+36-36)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll (+63-88)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll (+135-143)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll (+318-153)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll (+122-172)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll (+134-178)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll (+122-172)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll (+121-175)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp-mask.ll (+6-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll (+144-167)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll (+318-153)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll (+161-169)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll (+100-108)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll (+181-245)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll (+182-246)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp-bf16.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll (+95-127)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll ()
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll ()
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll ()
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll ()
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll (+274-321)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp-mask.ll (+6-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll (+108-116)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll (+212-220)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp-mask.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll (+37-60)
- (modified) llvm/test/CodeGen/RISCV/rvv/floor-vp.ll (+404-772)
- (modified) llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll (+448-640)
- (modified) llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll (+448-640)
- (modified) llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll (+11-16)
- (modified) llvm/test/CodeGen/RISCV/rvv/fold-vp-fsub-and-vp-fmul.ll (+6-9)
- (modified) llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll (+502-735)
- (modified) llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll (+19-34)
- (modified) llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll (+55-70)
- (modified) llvm/test/CodeGen/RISCV/rvv/marith-vp.ll (+36-36)
- (modified) llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll (+1-1)
- (modified) llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll (+400-768)
- (modified) llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll (+5-10)
- (modified) llvm/test/CodeGen/RISCV/rvv/pr141907.ll (+2-3)
- (modified) llvm/test/CodeGen/RISCV/rvv/pr171231.ll (+15-34)
- (modified) llvm/test/CodeGen/RISCV/rvv/rint-vp.ll (+372-740)
- (modified) llvm/test/CodeGen/RISCV/rvv/round-vp.ll (+404-772)
- (modified) llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll ()
- (modified) llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll ()
- (modified) llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll ()
- (modified) llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll ()
- (modified) llvm/test/CodeGen/RISCV/rvv/setcc-int-vp-mask.ll ()
- (modified) llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll ()
- (modified) llvm/test/CodeGen/RISCV/rvv/sink-splat-operands-i1.ll ()
- (modified) llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll ()
- (modified) llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll (+44-6)
- (modified) llvm/test/CodeGen/RISCV/rvv/vadd-vp-mask.ll (+5-5)
- (modified) llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll (+241-326)
- (modified) llvm/test/CodeGen/RISCV/rvv/vand-vp.ll (+223-223)
- (modified) llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll (+373-373)
- (modified) llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll (+261-261)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll (+215-240)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll (+764-1425)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll (+23-39)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll (+342-592)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll (+18-37)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll (+4452-5808)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll (+48-48)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll (+165-233)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll (+165-233)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll (+48-48)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll (+235-328)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll (+918-1040)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll (+179-204)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll (+48-48)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll (+48-48)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll (+22-38)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll (+35-30)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll (+84-135)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll (+35-30)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll (+84-135)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll (+37-99)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll (+45-45)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll (+45-45)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll (+129-218)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll (+378-564)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfwadd-vp.ll (+7-15)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll (+176-196)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll (+108-124)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll (+188-208)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll (+168-188)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll (+52-52)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll (+52-52)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll (+172-257)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll (+175-260)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll (+172-257)
- (modified) llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll (+175-260)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmul-vp-mask.ll (+5-5)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll (+175-179)
- (modified) llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll (+52-52)
- (modified) llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/rvv/vor-vp.ll (+224-224)
- (modified) llvm/test/CodeGen/RISCV/rvv/vp-inttoptr-ptrtoint.ll (+15-15)
- (modified) llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll (+23-24)
- (modified) llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll (+12-20)
- (modified) llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll (+20-24)
- (modified) llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll (+144-144)
- (modified) llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll (+235-290)
- (modified) llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll (+237-290)
- (modified) llvm/test/CodeGen/RISCV/rvv/vselect-vp-bf16.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll ()
- (modified) llvm/test/CodeGen/RISCV/rvv/vsext-vp-mask.ll ()
- (modified) llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll ()
- (modified) llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll ()
- (modified) llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll (+26-32)
- (modified) llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll (+99-184)
- (modified) llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll (+4-8)
- (modified) llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll (+233-278)
- (modified) llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll (+236-281)
- (modified) llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll (+310-365)
- (modified) llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll (+311-364)
- (modified) llvm/test/CodeGen/RISCV/rvv/vsub-vp-mask.ll (+5-5)
- (modified) llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll (+152-152)
- (modified) llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll (+12-13)
- (modified) llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll (+59-153)
- (modified) llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll (+26-32)
- (modified) llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll (+105-190)
- (modified) llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll (+12-18)
- (modified) llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll (+137-174)
- (modified) llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll (+292-292)
- (modified) llvm/test/CodeGen/RISCV/rvv/vzext-vp-mask.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll (+26-53)
``````````diff
diff --git a/llvm/lib/CodeGen/ExpandVectorPredication.cpp b/llvm/lib/CodeGen/ExpandVectorPredication.cpp
index 17fae8f6c8185..b574f724cf8db 100644
--- a/llvm/lib/CodeGen/ExpandVectorPredication.cpp
+++ b/llvm/lib/CodeGen/ExpandVectorPredication.cpp
@@ -286,14 +286,27 @@ bool CachingVPExpander::expandPredicationToFPCall(
switch (UnpredicatedIntrinsicID) {
case Intrinsic::fabs:
case Intrinsic::sqrt:
+ case Intrinsic::copysign:
case Intrinsic::maxnum:
- case Intrinsic::minnum: {
+ case Intrinsic::minnum:
+ case Intrinsic::maximum:
+ case Intrinsic::minimum:
+ case Intrinsic::ceil:
+ case Intrinsic::floor:
+ case Intrinsic::round:
+ case Intrinsic::roundeven:
+ case Intrinsic::trunc:
+ case Intrinsic::rint:
+ case Intrinsic::nearbyint:
+ case Intrinsic::lrint:
+ case Intrinsic::llrint:
+ case Intrinsic::is_fpclass: {
SmallVector<Value *, 2> Argument;
for (unsigned i = 0; i < VPI.getNumOperands() - 3; i++) {
Argument.push_back(VPI.getOperand(i));
}
- Value *NewOp = Builder.CreateIntrinsic(UnpredicatedIntrinsicID,
- {VPI.getType()}, Argument);
+ Value *NewOp = Builder.CreateIntrinsic(VPI.getType(),
+ UnpredicatedIntrinsicID, Argument);
replaceOperation(*NewOp, VPI);
return true;
}
@@ -609,12 +622,23 @@ bool CachingVPExpander::expandPredication(VPIntrinsic &VPI) {
return expandPredicationToIntCall(Builder, VPI);
case Intrinsic::vp_fabs:
case Intrinsic::vp_sqrt:
+ case Intrinsic::vp_copysign:
case Intrinsic::vp_maxnum:
case Intrinsic::vp_minnum:
case Intrinsic::vp_maximum:
case Intrinsic::vp_minimum:
+ case Intrinsic::vp_ceil:
+ case Intrinsic::vp_floor:
+ case Intrinsic::vp_round:
+ case Intrinsic::vp_roundeven:
+ case Intrinsic::vp_roundtozero:
+ case Intrinsic::vp_rint:
+ case Intrinsic::vp_nearbyint:
+ case Intrinsic::vp_lrint:
+ case Intrinsic::vp_llrint:
case Intrinsic::vp_fma:
case Intrinsic::vp_fmuladd:
+ case Intrinsic::vp_is_fpclass:
return expandPredicationToFPCall(Builder, VPI,
VPI.getFunctionalIntrinsicID().value());
case Intrinsic::vp_load:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b9d8ffc19e51a..2549b786a36ea 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -88,8 +88,6 @@ static cl::opt<bool>
cl::init(true));
// TODO: Support more ops
-static const unsigned ZvfbfaVPOps[] = {
- ISD::VP_FNEG, ISD::VP_FABS, ISD::VP_FCOPYSIGN};
static const unsigned ZvfbfaOps[] = {
ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN, ISD::FADD,
ISD::FSUB, ISD::FMUL, ISD::FMINNUM, ISD::FMAXNUM,
@@ -850,34 +848,17 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
MVT::Other, Custom);
static const unsigned IntegerVPOps[] = {
- ISD::VP_ADD, ISD::VP_SUB, ISD::VP_MUL,
ISD::VP_SDIV, ISD::VP_UDIV, ISD::VP_SREM,
- ISD::VP_UREM, ISD::VP_AND, ISD::VP_OR,
- ISD::VP_XOR, ISD::VP_SRA, ISD::VP_SRL,
- ISD::VP_SHL, ISD::VP_REDUCE_ADD, ISD::VP_REDUCE_AND,
+ ISD::VP_UREM, ISD::VP_REDUCE_ADD, ISD::VP_REDUCE_AND,
ISD::VP_REDUCE_OR, ISD::VP_REDUCE_XOR, ISD::VP_REDUCE_SMAX,
ISD::VP_REDUCE_SMIN, ISD::VP_REDUCE_UMAX, ISD::VP_REDUCE_UMIN,
- ISD::VP_MERGE, ISD::VP_SELECT, ISD::VP_FP_TO_SINT,
- ISD::VP_FP_TO_UINT, ISD::VP_SETCC, ISD::VP_SIGN_EXTEND,
- ISD::VP_ZERO_EXTEND, ISD::VP_TRUNCATE, ISD::VP_SMIN,
- ISD::VP_SMAX, ISD::VP_UMIN, ISD::VP_UMAX,
- ISD::VP_ABS, ISD::EXPERIMENTAL_VP_REVERSE, ISD::EXPERIMENTAL_VP_SPLICE,
- ISD::VP_SADDSAT, ISD::VP_UADDSAT, ISD::VP_SSUBSAT,
- ISD::VP_USUBSAT, ISD::VP_CTTZ_ELTS, ISD::VP_CTTZ_ELTS_ZERO_UNDEF};
+ ISD::VP_MERGE, ISD::EXPERIMENTAL_VP_REVERSE, ISD::EXPERIMENTAL_VP_SPLICE,
+ ISD::VP_CTTZ_ELTS, ISD::VP_CTTZ_ELTS_ZERO_UNDEF};
static const unsigned FloatingPointVPOps[] = {
- ISD::VP_FADD, ISD::VP_FSUB, ISD::VP_FMUL,
- ISD::VP_FDIV, ISD::VP_FNEG, ISD::VP_FABS,
- ISD::VP_FMA, ISD::VP_REDUCE_FADD, ISD::VP_REDUCE_SEQ_FADD,
+ ISD::VP_REDUCE_FADD, ISD::VP_REDUCE_SEQ_FADD,
ISD::VP_REDUCE_FMIN, ISD::VP_REDUCE_FMAX, ISD::VP_MERGE,
- ISD::VP_SELECT, ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP,
- ISD::VP_SETCC, ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND,
- ISD::VP_SQRT, ISD::VP_FMINNUM, ISD::VP_FMAXNUM,
- ISD::VP_FCEIL, ISD::VP_FFLOOR, ISD::VP_FROUND,
- ISD::VP_FROUNDEVEN, ISD::VP_FCOPYSIGN, ISD::VP_FROUNDTOZERO,
- ISD::VP_FRINT, ISD::VP_FNEARBYINT, ISD::VP_IS_FPCLASS,
- ISD::VP_FMINIMUM, ISD::VP_FMAXIMUM, ISD::VP_LRINT,
- ISD::VP_LLRINT, ISD::VP_REDUCE_FMINIMUM,
+ ISD::VP_SELECT, ISD::VP_REDUCE_FMINIMUM,
ISD::VP_REDUCE_FMAXIMUM};
static const unsigned IntegerVecReduceOps[] = {
@@ -924,15 +905,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
Custom);
setOperationAction(ISD::SELECT, VT, Custom);
- setOperationAction({ISD::SELECT_CC, ISD::VSELECT, ISD::VP_SELECT}, VT,
- Expand);
+ setOperationAction({ISD::SELECT_CC, ISD::VSELECT}, VT, Expand);
setOperationAction(ISD::VP_MERGE, VT, Custom);
setOperationAction({ISD::VP_CTTZ_ELTS, ISD::VP_CTTZ_ELTS_ZERO_UNDEF}, VT,
Custom);
- setOperationAction({ISD::VP_AND, ISD::VP_OR, ISD::VP_XOR}, VT, Custom);
-
setOperationAction(
{ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, ISD::VECREDUCE_XOR}, VT,
Custom);
@@ -961,10 +939,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
OtherVT, Expand);
}
- setOperationAction({ISD::VP_FP_TO_SINT, ISD::VP_FP_TO_UINT,
- ISD::VP_TRUNCATE, ISD::VP_SETCC},
- VT, Custom);
-
setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom);
setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom);
@@ -1067,33 +1041,24 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (Subtarget.hasStdExtZvkb()) {
setOperationAction(ISD::BSWAP, VT, Legal);
- setOperationAction(ISD::VP_BSWAP, VT, Custom);
} else {
- setOperationAction({ISD::BSWAP, ISD::VP_BSWAP}, VT, Expand);
+ setOperationAction(ISD::BSWAP, VT, Expand);
setOperationAction({ISD::ROTL, ISD::ROTR}, VT, Expand);
}
if (Subtarget.hasStdExtZvbb()) {
setOperationAction(ISD::BITREVERSE, VT, Legal);
- setOperationAction(ISD::VP_BITREVERSE, VT, Custom);
- setOperationAction({ISD::VP_CTLZ, ISD::VP_CTLZ_ZERO_UNDEF, ISD::VP_CTTZ,
- ISD::VP_CTTZ_ZERO_UNDEF, ISD::VP_CTPOP},
- VT, Custom);
} else {
- setOperationAction({ISD::BITREVERSE, ISD::VP_BITREVERSE}, VT, Expand);
+ setOperationAction(ISD::BITREVERSE, VT, Expand);
setOperationAction({ISD::CTLZ, ISD::CTTZ, ISD::CTPOP}, VT, Expand);
- setOperationAction({ISD::VP_CTLZ, ISD::VP_CTLZ_ZERO_UNDEF, ISD::VP_CTTZ,
- ISD::VP_CTTZ_ZERO_UNDEF, ISD::VP_CTPOP},
- VT, Expand);
// Lower CTLZ_ZERO_UNDEF and CTTZ_ZERO_UNDEF if element of VT in the
// range of f32.
EVT FloatVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount());
if (isTypeLegal(FloatVT)) {
- setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF,
- ISD::CTTZ_ZERO_UNDEF, ISD::VP_CTLZ,
- ISD::VP_CTLZ_ZERO_UNDEF, ISD::VP_CTTZ_ZERO_UNDEF},
- VT, Custom);
+ setOperationAction(
+ {ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ_ZERO_UNDEF}, VT,
+ Custom);
}
}
@@ -1176,26 +1141,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
// TODO: support more vp ops.
static const unsigned ZvfhminZvfbfminPromoteVPOps[] = {
- ISD::VP_FADD,
- ISD::VP_FSUB,
- ISD::VP_FMUL,
- ISD::VP_FDIV,
- ISD::VP_FMA,
ISD::VP_REDUCE_FMIN,
ISD::VP_REDUCE_FMAX,
- ISD::VP_SQRT,
- ISD::VP_FMINNUM,
- ISD::VP_FMAXNUM,
- ISD::VP_FCEIL,
- ISD::VP_FFLOOR,
- ISD::VP_FROUND,
- ISD::VP_FROUNDEVEN,
- ISD::VP_FROUNDTOZERO,
- ISD::VP_FRINT,
- ISD::VP_FNEARBYINT,
- ISD::VP_SETCC,
- ISD::VP_FMINIMUM,
- ISD::VP_FMAXIMUM,
ISD::VP_REDUCE_FMINIMUM,
ISD::VP_REDUCE_FMAXIMUM};
@@ -1291,13 +1238,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);
setOperationAction({ISD::STRICT_FP_ROUND, ISD::STRICT_FP_EXTEND}, VT,
Custom);
- setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom);
setOperationAction({ISD::LROUND, ISD::LLROUND}, VT, Custom);
- setOperationAction({ISD::VP_MERGE, ISD::VP_SELECT, ISD::SELECT}, VT,
- Custom);
+ setOperationAction({ISD::VP_MERGE, ISD::SELECT}, VT, Custom);
setOperationAction(ISD::SELECT_CC, VT, Expand);
- setOperationAction({ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP}, VT, Custom);
setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::CONCAT_VECTORS,
ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR,
ISD::VECTOR_DEINTERLEAVE, ISD::VECTOR_INTERLEAVE,
@@ -1344,13 +1288,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);
setOperationAction({ISD::STRICT_FP_ROUND, ISD::STRICT_FP_EXTEND}, VT,
Custom);
- setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom);
setOperationAction({ISD::LROUND, ISD::LLROUND}, VT, Custom);
- setOperationAction({ISD::VP_MERGE, ISD::VP_SELECT, ISD::SELECT}, VT,
- Custom);
+ setOperationAction({ISD::VP_MERGE, ISD::SELECT}, VT, Custom);
setOperationAction(ISD::SELECT_CC, VT, Expand);
- setOperationAction({ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP}, VT, Custom);
setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR,
ISD::EXTRACT_SUBVECTOR, ISD::VECTOR_DEINTERLEAVE,
@@ -1371,7 +1312,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::STRICT_FADD, ISD::STRICT_FSUB, ISD::STRICT_FMUL,
ISD::STRICT_FMA},
VT, Legal);
- setOperationAction(ZvfbfaVPOps, VT, Custom);
setCondCodeAction(VFPCCToExpand, VT, Expand);
setOperationAction({ISD::LOAD, ISD::STORE, ISD::MLOAD, ISD::MSTORE,
@@ -1518,13 +1458,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
// Operations below are different for between masks and other vectors.
if (VT.getVectorElementType() == MVT::i1) {
- setOperationAction({ISD::VP_AND, ISD::VP_OR, ISD::VP_XOR, ISD::AND,
- ISD::OR, ISD::XOR},
- VT, Custom);
-
- setOperationAction({ISD::VP_FP_TO_SINT, ISD::VP_FP_TO_UINT,
- ISD::VP_SETCC, ISD::VP_TRUNCATE},
- VT, Custom);
+ setOperationAction({ISD::AND, ISD::OR, ISD::XOR}, VT, Custom);
setOperationAction(ISD::VP_MERGE, VT, Custom);
@@ -1655,11 +1589,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
if (VT.getVectorElementType() == MVT::f16 &&
!Subtarget.hasVInstructionsF16()) {
- setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
- setOperationAction(
- {ISD::VP_MERGE, ISD::VP_SELECT, ISD::VSELECT, ISD::SELECT}, VT,
- Custom);
- setOperationAction({ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP}, VT,
+ setOperationAction({ISD::VP_MERGE, ISD::VSELECT, ISD::SELECT}, VT,
Custom);
setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom);
setOperationAction({ISD::LROUND, ISD::LLROUND}, VT, Custom);
@@ -1685,7 +1615,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
if (VT.getVectorElementType() == MVT::bf16) {
- setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom);
setOperationAction({ISD::LROUND, ISD::LLROUND}, VT, Custom);
if (Subtarget.hasStdExtZfbfmin()) {
@@ -1697,12 +1626,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
if (Subtarget.hasStdExtZvfbfa()) {
setOperationAction(ZvfbfaOps, VT, Custom);
- setOperationAction(ZvfbfaVPOps, VT, Custom);
setCondCodeAction(VFPCCToExpand, VT, Expand);
}
- setOperationAction(
- {ISD::VP_MERGE, ISD::VP_SELECT, ISD::VSELECT, ISD::SELECT}, VT,
- Custom);
+ setOperationAction({ISD::VP_MERGE, ISD::VSELECT, ISD::SELECT}, VT,
+ Custom);
MVT F32VecVT = MVT::getVectorVT(MVT::f32, VT.getVectorElementCount());
// Don't promote f16 vector operations to f32 if f32 vector type is
// not legal.
@@ -1870,7 +1797,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::VP_GATHER, ISD::VP_SCATTER, ISD::SRA,
ISD::SRL, ISD::SHL, ISD::STORE,
ISD::SPLAT_VECTOR, ISD::BUILD_VECTOR, ISD::CONCAT_VECTORS,
- ISD::VP_STORE, ISD::VP_TRUNCATE, ISD::EXPERIMENTAL_VP_REVERSE,
+ ISD::VP_STORE, ISD::EXPERIMENTAL_VP_REVERSE,
ISD::MUL, ISD::SDIV, ISD::UDIV,
ISD::SREM, ISD::UREM, ISD::INSERT_VECTOR_ELT,
ISD::ABS, ISD::CTPOP, ISD::VECTOR_SHUFFLE,
@@ -3540,19 +3467,15 @@ static RISCVFPRndMode::RoundingMode matchRoundingOp(unsigned Opc) {
switch (Opc) {
case ISD::FROUNDEVEN:
case ISD::STRICT_FROUNDEVEN:
- case ISD::VP_FROUNDEVEN:
return RISCVFPRndMode::RNE;
case ISD::FTRUNC:
case ISD::STRICT_FTRUNC:
- case ISD::VP_FROUNDTOZERO:
return RISCVFPRndMode::RTZ;
case ISD::FFLOOR:
case ISD::STRICT_FFLOOR:
- case ISD::VP_FFLOOR:
return RISCVFPRndMode::RDN;
case ISD::FCEIL:
case ISD::STRICT_FCEIL:
- case ISD::VP_FCEIL:
return RISCVFPRndMode::RUP;
case ISD::FROUND:
case ISD::LROUND:
@@ -3560,7 +3483,6 @@ static RISCVFPRndMode::RoundingMode matchRoundingOp(unsigned Opc) {
case ISD::STRICT_FROUND:
case ISD::STRICT_LROUND:
case ISD::STRICT_LLROUND:
- case ISD::VP_FROUND:
return RISCVFPRndMode::RMM;
case ISD::FRINT:
case ISD::LRINT:
@@ -3568,17 +3490,13 @@ static RISCVFPRndMode::RoundingMode matchRoundingOp(unsigned Opc) {
case ISD::STRICT_FRINT:
case ISD::STRICT_LRINT:
case ISD::STRICT_LLRINT:
- case ISD::VP_FRINT:
- case ISD::VP_LRINT:
- case ISD::VP_LLRINT:
return RISCVFPRndMode::DYN;
}
return RISCVFPRndMode::Invalid;
}
-// Expand vector FTRUNC, FCEIL, FFLOOR, FROUND, VP_FCEIL, VP_FFLOOR, VP_FROUND
-// VP_FROUNDEVEN, VP_FROUNDTOZERO, VP_FRINT and VP_FNEARBYINT by converting to
+// Expand vector FTRUNC, FCEIL, FFLOOR, FROUND and FNEARBYINT by converting to
// the integer domain and back. Taking care to avoid converting values that are
// nan or already correct.
static SDValue
@@ -3600,16 +3518,7 @@ lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op, SelectionDAG &DAG,
Src = convertToScalableVector(ContainerVT, Src, DAG, Subtarget);
}
- SDValue Mask, VL;
- if (Op->isVPOpcode()) {
- Mask = Op.getOperand(1);
- if (VT.isFixedLengthVector())
- Mask = convertToScalableVector(getMaskTypeFor(ContainerVT), Mask, DAG,
- Subtarget);
- VL = Op.getOperand(2);
- } else {
- std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
- }
+ auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
// We do the conversion on the absolute value and fix the sign at the end.
SDValue Abs = DAG.getNode(RISCVISD::FABS_VL, DL, ContainerVT, Src, Mask, VL);
@@ -3643,16 +3552,10 @@ lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op, SelectionDAG &DAG,
default:
llvm_unreachable("Unexpected opcode");
case ISD::FRINT:
- case ISD::VP_FRINT:
case ISD::FCEIL:
- case ISD::VP_FCEIL:
case ISD::FFLOOR:
- case ISD::VP_FFLOOR:
case ISD::FROUND:
- case ISD::FROUNDEVEN:
- case ISD::VP_FROUND:
- case ISD::VP_FROUNDEVEN:
- case ISD::VP_FROUNDTOZERO: {
+ case ISD::FROUNDEVEN: {
RISCVFPRndMode::RoundingMode FRM = matchRoundingOp(Op.getOpcode());
assert(FRM != RISCVFPRndMode::Invalid);
Truncated = DAG.getNode(RISCVISD::VFCVT_RM_X_F_VL, DL, IntVT, Src, Mask,
@@ -3664,7 +3567,6 @@ lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op, SelectionDAG &DAG,
Mask, VL);
break;
case ISD::FNEARBYINT:
- case ISD::VP_FNEARBYINT:
Truncated = DAG.getNode(RISCVISD::VFROUND_NOEXCEPT_VL, DL, ContainerVT, Src,
Mask, VL);
break;
@@ -6797,15 +6699,6 @@ RISCVTargetLowering::lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op,
SDLoc DL(Op);
MVT ContainerVT = VT;
- SDValue Mask, VL;
- if (Op->isVPOpcode()) {
- Mask = Op.getOperand(1);
- if (VT.isFixedLengthVector())
- Mask = convertToScalableVector(getMaskTypeFor(ContainerVT), Mask, DAG,
- Subtarget);
- VL = Op.getOperand(2);
- }
-
// We choose FP type that can represent the value if possible. Otherwise, we
// use rounding to zero conversion for correct exponent of the result.
// TODO: Use f16 for i8 when possible?
@@ -6825,27 +6718,19 @@ RISCVTargetLowering::lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op,
if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF) {
SDValue Neg = DAG.getNegative(Src, DL, VT);
Src = DAG.getNode(ISD::AND, DL, VT, Src, Neg);
- } else if (Op.getOpcode() == ISD::VP_CTTZ_ZERO_UNDEF) {
- SDValue Neg = DAG.getNode(ISD::VP_SUB, DL, VT, DAG.getConstant(0, DL, VT),
- Src, Mask, VL);
- Src = DAG.getNode(ISD::VP_AND, DL, VT, Src, Neg, Mask, VL);
}
// We have a legal FP type, convert to it.
SDValue FloatVal;
if (FloatVT.bitsGT(VT)) {
- if (Op->isVPOpcode())
- FloatVal = DAG.getNode(ISD::VP_UINT_TO_FP, DL, FloatVT, Src, Mask, VL);
- else
- FloatVal = DAG.getNode(ISD::UINT_TO_FP, DL, FloatVT, Src);
+ FloatVal = DAG.getNode(ISD::UINT_TO_FP, DL, FloatVT, Src);
} else {
// Use RTZ to avoid rounding influencing exponent of FloatVal.
if (VT.isFixedLengthVector()) {
ContainerVT = getContainerForFixedLengthVector(VT);
Src = convertToScalableVector(ContainerVT, Src, DAG, Subtarget);
}
- if (!Op->isVPOpcode())
- std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
+ auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
SDValue RTZRM =
DAG.getTargetConstant(RISCVFPRndMode::RTZ, DL, Subtarget.getXLenVT());
MVT ContainerFloatVT =
@@ -6860,20 +6745,13 @@ RISCVTargetLowering::lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op,
SDValue Bitcast = DAG.getBitcast(IntVT, FloatVal);
unsigned ShiftAmt = FloatEltVT == MVT::f64 ? 52 : 23;
- SDValue Exp;
// Restore back to original type. Truncation after SRL is to generate vnsrl.
- if (Op->isVPOpcode()) {
- Exp = D...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/179622
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