[llvm] 3794b83 - [RISCV] Don't emit VP_SETCC in combineVectorSizedSetCCEquality. NFC (#179479)

[via llvm-commits]

Author: Luke Lau
Date: 2026-02-04T06:59:27Z
New Revision: 3794b83ae59f79910f9ef573a753435c3f99ec68

URL: https://github.com/llvm/llvm-project/commit/3794b83ae59f79910f9ef573a753435c3f99ec68
DIFF: https://github.com/llvm/llvm-project/commit/3794b83ae59f79910f9ef573a753435c3f99ec68.diff

LOG: [RISCV] Don't emit VP_SETCC in combineVectorSizedSetCCEquality. NFC (#179479)

This is part of the work to remove trivial VP intrinsics.

In the combineVectorSizedSetCCEquality combine, used for the compares
that ExpandMemcmp generates, we currently emit a VP_SETCC. We can just
emit a regular SETCC and let RISCVVLOptimizer take care of reducing the
VL.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 2c45185c90bda..b9d8ffc19e51a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17590,8 +17590,7 @@ combineVectorSizedSetCCEquality(EVT VT, SDValue X, SDValue Y, ISD::CondCode CC,
   SDValue Mask = DAG.getAllOnesConstant(DL, CmpVT);
   SDValue VL = DAG.getConstant(VecSize, DL, XLenVT);
 
-  SDValue Cmp = DAG.getNode(ISD::VP_SETCC, DL, CmpVT, VecX, VecY,
-                            DAG.getCondCode(ISD::SETNE), Mask, VL);
+  SDValue Cmp = DAG.getSetCC(DL, CmpVT, VecX, VecY, ISD::SETNE);
   return DAG.getSetCC(DL, VT,
                       DAG.getNode(ISD::VP_REDUCE_OR, DL, XLenVT,
                                   DAG.getConstant(0, DL, XLenVT), Cmp, Mask,