[llvm] d8073d9 - [InstCombine] Bubble splices of binop operands to their result (#179432)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 3 22:09:54 PST 2026
Author: Luke Lau
Date: 2026-02-04T06:09:49Z
New Revision: d8073d9b4bd4af4380e4ce04ad9ee6f41dd8df42
URL: https://github.com/llvm/llvm-project/commit/d8073d9b4bd4af4380e4ce04ad9ee6f41dd8df42
DIFF: https://github.com/llvm/llvm-project/commit/d8073d9b4bd4af4380e4ce04ad9ee6f41dd8df42.diff
LOG: [InstCombine] Bubble splices of binop operands to their result (#179432)
In #172961 we are trying to remove llvm.experimental.vp.reverse now that
llvm.vector.splice.right supports variable offsets.
A VP reverse reverses the first EVL elements of the vector, e.g.
01234567 -> 210xxxxx when EVL=3, where x=poison.
This can now be represented by splice.right(reverse(V), poison, EVL):
01234567
-> 76543210 (reverse)
-> 210xxxxx (splice.right)
This PR implements the vp.reverse combines that pull through binops, but
generalized to vector.splice. Specifically, this implements the
following combines:
Op(splice(V1, poison, offset), splice(V2, poison, offset)) -> splice(Op(V1, V2), poison, offset)
Op(splice(V1, poison, offset), RHSSplat) -> splice(Op(V1, RHSSplat), poison, offset)
Op(LHSSplat, splice(V2, poison, offset)) -> splice(Op(LHSSplat, V2), poison, offset)
We can then remove the vp.reverse intrinsic and its related combines
soon after, once we migrate the loop vectorizer over.
Added:
llvm/test/Transforms/InstCombine/vector-splice.ll
Modified:
llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
index a9904f7867e94..e2bda2450c66f 100644
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -2392,6 +2392,48 @@ static Constant *constantFoldBinOpWithSplat(unsigned Opcode, Constant *Vector,
return ConstantFoldBinaryOpOperands(Opcode, LHS, RHS, DL);
}
+template <Intrinsic::ID SpliceID>
+static Instruction *foldSpliceBinOp(BinaryOperator &Inst,
+ InstCombiner::BuilderTy &Builder) {
+ Value *LHS = Inst.getOperand(0), *RHS = Inst.getOperand(1);
+ auto CreateBinOpSplice = [&](Value *X, Value *Y, Value *Offset) {
+ Value *V = Builder.CreateBinOp(Inst.getOpcode(), X, Y, Inst.getName());
+ if (auto *BO = dyn_cast<BinaryOperator>(V))
+ BO->copyIRFlags(&Inst);
+ Module *M = Inst.getModule();
+ Function *F = Intrinsic::getOrInsertDeclaration(M, SpliceID, V->getType());
+ return CallInst::Create(F, {V, PoisonValue::get(V->getType()), Offset});
+ };
+ Value *V1, *V2, *Offset;
+ if (match(LHS,
+ m_Intrinsic<SpliceID>(m_Value(V1), m_Poison(), m_Value(Offset)))) {
+ // Op(splice(V1, poison, offset), splice(V2, poison, offset))
+ // -> splice(Op(V1, V2), poison, offset)
+ if (match(RHS, m_Intrinsic<SpliceID>(m_Value(V2), m_Poison(),
+ m_Specific(Offset))) &&
+ (LHS->hasOneUse() || RHS->hasOneUse() ||
+ (LHS == RHS && LHS->hasNUses(2))))
+ return CreateBinOpSplice(V1, V2, Offset);
+
+ // Op(splice(V1, poison, offset), RHSSplat)
+ // -> splice(Op(V1, RHSSplat), poison, offset)
+ if (LHS->hasOneUse() && isSplatValue(RHS))
+ return CreateBinOpSplice(V1, RHS, Offset);
+ }
+ // Op(LHSSplat, splice(V2, poison, offset))
+ // -> splice(Op(LHSSplat, V2), poison, offset)
+ else if (isSplatValue(LHS) &&
+ match(RHS, m_OneUse(m_Intrinsic<SpliceID>(m_Value(V2), m_Poison(),
+ m_Value(Offset)))))
+ return CreateBinOpSplice(LHS, V2, Offset);
+
+ // TODO: Fold binops of the form
+ // Op(splice(poison, V1, offset), splice(poison, V2, offset))
+ // -> splice(poison, Op(V1, V2), offset)
+
+ return nullptr;
+}
+
Instruction *InstCombinerImpl::foldVectorBinop(BinaryOperator &Inst) {
if (!isa<VectorType>(Inst.getType()))
return nullptr;
@@ -2520,6 +2562,13 @@ Instruction *InstCombinerImpl::foldVectorBinop(BinaryOperator &Inst) {
m_Value(V2), m_AllOnes(), m_Value(EVL))))
return createBinOpVPReverse(LHS, V2, EVL);
+ if (Instruction *Folded =
+ foldSpliceBinOp<Intrinsic::vector_splice_left>(Inst, Builder))
+ return Folded;
+ if (Instruction *Folded =
+ foldSpliceBinOp<Intrinsic::vector_splice_right>(Inst, Builder))
+ return Folded;
+
// It may not be safe to reorder shuffles and things like div, urem, etc.
// because we may trap when executing those ops on unknown vector elements.
// See PR20059.
diff --git a/llvm/test/Transforms/InstCombine/vector-splice.ll b/llvm/test/Transforms/InstCombine/vector-splice.ll
new file mode 100644
index 0000000000000..902ae96181a71
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/vector-splice.ll
@@ -0,0 +1,123 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt < %s -p instcombine -S | FileCheck %s
+
+define <4 x i32> @binop_splice_left(<4 x i32> %v1, <4 x i32> %v2, i32 %offset) {
+; CHECK-LABEL: define <4 x i32> @binop_splice_left(
+; CHECK-SAME: <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 [[OFFSET:%.*]]) {
+; CHECK-NEXT: [[RES1:%.*]] = add <4 x i32> [[V1]], [[V2]]
+; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.left.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]])
+; CHECK-NEXT: ret <4 x i32> [[RES]]
+;
+ %splice1 = call <4 x i32> @llvm.vector.splice.left(<4 x i32> %v1, <4 x i32> poison, i32 %offset)
+ %splice2 = call <4 x i32> @llvm.vector.splice.left(<4 x i32> %v2, <4 x i32> poison, i32 %offset)
+ %res = add <4 x i32> %splice1, %splice2
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @binop_splice_left_rhs_splat(<4 x i32> %v1, i32 %x, i32 %offset) {
+; CHECK-LABEL: define <4 x i32> @binop_splice_left_rhs_splat(
+; CHECK-SAME: <4 x i32> [[V1:%.*]], i32 [[X:%.*]], i32 [[OFFSET:%.*]]) {
+; CHECK-NEXT: [[HEAD:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0
+; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x i32> [[HEAD]], <4 x i32> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT: [[RES1:%.*]] = add <4 x i32> [[V1]], [[SPLAT]]
+; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.left.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]])
+; CHECK-NEXT: ret <4 x i32> [[RES]]
+;
+ %splice = call <4 x i32> @llvm.vector.splice.left(<4 x i32> %v1, <4 x i32> poison, i32 %offset)
+ %head = insertelement <4 x i32> poison, i32 %x, i32 0
+ %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer
+ %res = add <4 x i32> %splice, %splat
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @binop_splice_left_lhs_splat(<4 x i32> %v1, i32 %x, i32 %offset) {
+; CHECK-LABEL: define <4 x i32> @binop_splice_left_lhs_splat(
+; CHECK-SAME: <4 x i32> [[V1:%.*]], i32 [[X:%.*]], i32 [[OFFSET:%.*]]) {
+; CHECK-NEXT: [[HEAD:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0
+; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x i32> [[HEAD]], <4 x i32> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT: [[RES1:%.*]] = add <4 x i32> [[SPLAT]], [[V1]]
+; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.left.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]])
+; CHECK-NEXT: ret <4 x i32> [[RES]]
+;
+ %splice = call <4 x i32> @llvm.vector.splice.left(<4 x i32> %v1, <4 x i32> poison, i32 %offset)
+ %head = insertelement <4 x i32> poison, i32 %x, i32 0
+ %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer
+ %res = add <4 x i32> %splat, %splice
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @binop_splice_right(<4 x i32> %v1, <4 x i32> %v2, i32 %offset) {
+; CHECK-LABEL: define <4 x i32> @binop_splice_right(
+; CHECK-SAME: <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 [[OFFSET:%.*]]) {
+; CHECK-NEXT: [[RES1:%.*]] = add <4 x i32> [[V1]], [[V2]]
+; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]])
+; CHECK-NEXT: ret <4 x i32> [[RES]]
+;
+ %splice1 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> poison, i32 %offset)
+ %splice2 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v2, <4 x i32> poison, i32 %offset)
+ %res = add <4 x i32> %splice1, %splice2
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @binop_splice_right_rhs_splat(<4 x i32> %v1, i32 %x, i32 %offset) {
+; CHECK-LABEL: define <4 x i32> @binop_splice_right_rhs_splat(
+; CHECK-SAME: <4 x i32> [[V1:%.*]], i32 [[X:%.*]], i32 [[OFFSET:%.*]]) {
+; CHECK-NEXT: [[HEAD:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0
+; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x i32> [[HEAD]], <4 x i32> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT: [[RES1:%.*]] = add <4 x i32> [[V1]], [[SPLAT]]
+; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]])
+; CHECK-NEXT: ret <4 x i32> [[RES]]
+;
+ %splice = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> poison, i32 %offset)
+ %head = insertelement <4 x i32> poison, i32 %x, i32 0
+ %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer
+ %res = add <4 x i32> %splice, %splat
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @binop_splice_right_lhs_splat(<4 x i32> %v1, i32 %x, i32 %offset) {
+; CHECK-LABEL: define <4 x i32> @binop_splice_right_lhs_splat(
+; CHECK-SAME: <4 x i32> [[V1:%.*]], i32 [[X:%.*]], i32 [[OFFSET:%.*]]) {
+; CHECK-NEXT: [[HEAD:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0
+; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x i32> [[HEAD]], <4 x i32> poison, <4 x i32> zeroinitializer
+; CHECK-NEXT: [[RES1:%.*]] = add <4 x i32> [[SPLAT]], [[V1]]
+; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]])
+; CHECK-NEXT: ret <4 x i32> [[RES]]
+;
+ %splice = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> poison, i32 %offset)
+ %head = insertelement <4 x i32> poison, i32 %x, i32 0
+ %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer
+ %res = add <4 x i32> %splat, %splice
+ ret <4 x i32> %res
+}
+
+; Negative test, mismatched offset
+define <4 x i32> @binop_splice_mismatched_offset(<4 x i32> %v1, <4 x i32> %v2, i32 %offset1, i32 %offset2) {
+; CHECK-LABEL: define <4 x i32> @binop_splice_mismatched_offset(
+; CHECK-SAME: <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 [[OFFSET1:%.*]], i32 [[OFFSET2:%.*]]) {
+; CHECK-NEXT: [[SPLICE1:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[V1]], <4 x i32> poison, i32 [[OFFSET1]])
+; CHECK-NEXT: [[SPLICE2:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[V2]], <4 x i32> poison, i32 [[OFFSET2]])
+; CHECK-NEXT: [[RES:%.*]] = add <4 x i32> [[SPLICE1]], [[SPLICE2]]
+; CHECK-NEXT: ret <4 x i32> [[RES]]
+;
+ %splice1 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> poison, i32 %offset1)
+ %splice2 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v2, <4 x i32> poison, i32 %offset2)
+ %res = add <4 x i32> %splice1, %splice2
+ ret <4 x i32> %res
+}
+
+; Negative test, non poison vector operand
+define <4 x i32> @binop_splice_mismatched_vector(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, i32 %offset) {
+; CHECK-LABEL: define <4 x i32> @binop_splice_mismatched_vector(
+; CHECK-SAME: <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], <4 x i32> [[V3:%.*]], i32 [[OFFSET:%.*]]) {
+; CHECK-NEXT: [[SPLICE1:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[V1]], <4 x i32> [[V3]], i32 [[OFFSET]])
+; CHECK-NEXT: [[SPLICE2:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[V2]], <4 x i32> [[V3]], i32 [[OFFSET]])
+; CHECK-NEXT: [[RES:%.*]] = add <4 x i32> [[SPLICE1]], [[SPLICE2]]
+; CHECK-NEXT: ret <4 x i32> [[RES]]
+;
+ %splice1 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> %v3, i32 %offset)
+ %splice2 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v2, <4 x i32> %v3, i32 %offset)
+ %res = add <4 x i32> %splice1, %splice2
+ ret <4 x i32> %res
+}
+
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