[llvm] [AMDGPU] Add machineFunctionInfo to recent MIR tests (PR #179602)

[Carl Ritson via llvm-commits]

https://github.com/perlfu updated https://github.com/llvm/llvm-project/pull/179602

>From 8f663486884ab08d6c5a8ce87a2a2fbcdd3cc8e2 Mon Sep 17 00:00:00 2001
From: Carl Ritson <carl.ritson at amd.com>
Date: Wed, 4 Feb 2026 12:05:01 +0900
Subject: [PATCH 1/2] [AMDGPU] Add machineFunctionInfo to recent MIR tests

Initialize machineFunctionInfo in recently added MIR tests to
assist in downstream testing.
---
 llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir     | 2 ++
 llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir b/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
index f401d0b515373..9c433c7a139a8 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
+++ b/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
@@ -5,6 +5,8 @@
 ---
 name:            gemm_loop1
 tracksRegLiveness: true
+machineFunctionInfo:
+  isEntryFunction: true
 body:             |
   ; GFX11-LABEL: name: gemm_loop1
   ; GFX11: bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir b/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
index 7be5b164cd1a1..eee018f0301e4 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
+++ b/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
@@ -136,6 +136,8 @@
 ---
 name: test_workgroup
 tracksRegLiveness: true
+machineFunctionInfo:
+  isEntryFunction: true
 body: |
   bb.0:
     %0:sgpr_256 = IMPLICIT_DEF

>From 4bb28c68c2a83c7a4e4f4a059b9ce05797ed3c5d Mon Sep 17 00:00:00 2001
From: Carl Ritson <carl.ritson at amd.com>
Date: Wed, 4 Feb 2026 13:33:38 +0900
Subject: [PATCH 2/2] - Fix unnecessary check lines for entry functions

---
 llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir     | 1 -
 llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir | 2 --
 2 files changed, 3 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir b/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
index 9c433c7a139a8..29bfeb8fa1bd1 100644
--- a/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
+++ b/llvm/test/CodeGen/AMDGPU/gfx11-sgpr-hazard-latency.mir
@@ -12,7 +12,6 @@ body:             |
   ; GFX11: bb.0:
   ; GFX11-NEXT:   successors: %bb.1(0x80000000)
   ; GFX11-NEXT: {{  $}}
-  ; GFX11-NEXT:   S_WAITCNT 0
   ; GFX11-NEXT:   renamable $vgpr0 = V_MOV_B32_e32 0, implicit $exec
   ; GFX11-NEXT:   renamable $vgpr1 = V_MOV_B32_e32 0, implicit $exec
   ; GFX11-NEXT:   renamable $vgpr2 = V_MOV_B32_e32 0, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir b/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
index eee018f0301e4..8e98d0cc27473 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
+++ b/llvm/test/CodeGen/AMDGPU/schedule-barrier-latency-gfx9.mir
@@ -16,7 +16,6 @@
   ; GFX9:       ; %bb.0:
   ; GFX9-NEXT:    ; implicit-def: $vgpr0_vgpr1
   ; GFX9-NEXT:    ; implicit-def: $vgpr2_vgpr3
-  ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
   ; GFX9-NEXT:    global_load_ushort v14, v[0:1], off
   ; GFX9-NEXT:    ; implicit-def: $vgpr4_vgpr5
   ; GFX9-NEXT:    global_load_ushort v15, v[4:5], off
@@ -74,7 +73,6 @@
   ; GFX9-TGS:       ; %bb.0:
   ; GFX9-TGS-NEXT:    ; implicit-def: $vgpr0_vgpr1
   ; GFX9-TGS-NEXT:    ; implicit-def: $vgpr2_vgpr3
-  ; GFX9-TGS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
   ; GFX9-TGS-NEXT:    global_load_ushort v14, v[0:1], off
   ; GFX9-TGS-NEXT:    ; implicit-def: $vgpr4_vgpr5
   ; GFX9-TGS-NEXT:    global_load_ushort v15, v[4:5], off