[llvm] [NFC][LLVM] Make constrainSelectedInstRegOperands return void (it always returns true) (PR #179501)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 3 09:10:06 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-mips
Author: Juan Manuel Martinez Caamaño (jmmartinez)
<details>
<summary>Changes</summary>
---
Patch is 62.25 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/179501.diff
13 Files Affected:
- (modified) llvm/include/llvm/CodeGen/GlobalISel/Utils.h (+1-3)
- (modified) llvm/include/llvm/CodeGen/MachineInstrBuilder.h (+2-1)
- (modified) llvm/lib/CodeGen/GlobalISel/Utils.cpp (+1-2)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp (+44-22)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (+65-49)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp (+2-7)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (+1-2)
- (modified) llvm/lib/Target/ARM/ARMInstructionSelector.cpp (+24-30)
- (modified) llvm/lib/Target/Mips/MipsInstructionSelector.cpp (+34-56)
- (modified) llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp (+10-5)
- (modified) llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp (+41-31)
- (modified) llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp (+4-4)
- (modified) llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp (+14-9)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
index da2742e089f8f..de6606e7ed14a 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
@@ -132,12 +132,10 @@ LLVM_ABI Register constrainOperandRegClass(
/// generic) virtual register operands to the instruction's register class.
/// This could involve inserting COPYs before (for uses) or after (for defs).
/// This requires the number of operands to match the instruction description.
-/// \returns whether operand regclass constraining succeeded.
-///
// FIXME: Not all instructions have the same number of operands. We should
// probably expose a constrain helper per operand and let the target selector
// constrain individual registers, like fast-isel.
-LLVM_ABI bool constrainSelectedInstRegOperands(MachineInstr &I,
+LLVM_ABI void constrainSelectedInstRegOperands(MachineInstr &I,
const TargetInstrInfo &TII,
const TargetRegisterInfo &TRI,
const RegisterBankInfo &RBI);
diff --git a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
index 1a33d760fb59e..7e1d67265a7c1 100644
--- a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
+++ b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
@@ -441,7 +441,8 @@ class MachineInstrBuilder {
bool constrainAllUses(const TargetInstrInfo &TII,
const TargetRegisterInfo &TRI,
const RegisterBankInfo &RBI) const {
- return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+ return true;
}
};
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index 658774ec3fcb9..e3ec021085a29 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -152,7 +152,7 @@ Register llvm::constrainOperandRegClass(
RegMO);
}
-bool llvm::constrainSelectedInstRegOperands(MachineInstr &I,
+void llvm::constrainSelectedInstRegOperands(MachineInstr &I,
const TargetInstrInfo &TII,
const TargetRegisterInfo &TRI,
const RegisterBankInfo &RBI) {
@@ -195,7 +195,6 @@ bool llvm::constrainSelectedInstRegOperands(MachineInstr &I,
I.tieOperands(DefIdx, OpI);
}
}
- return true;
}
bool llvm::canReplaceReg(Register DstReg, Register SrcReg,
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index b05da9376d966..c1e64c1ba40a1 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -1792,7 +1792,8 @@ bool AArch64InstructionSelector::selectCompareBranch(
.addImm(AArch64CC::NE)
.addMBB(I.getOperand(1).getMBB());
I.eraseFromParent();
- return constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI);
+ return true;
}
/// Returns the element immediate value of a vector shift operand if found.
@@ -2290,7 +2291,8 @@ bool AArch64InstructionSelector::earlySelectSHL(MachineInstr &I,
RenderFn(NewI);
I.eraseFromParent();
- return constrainSelectedInstRegOperands(*NewI, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*NewI, TII, TRI, RBI);
+ return true;
}
bool AArch64InstructionSelector::contractCrossBankCopyIntoStore(
@@ -2529,8 +2531,10 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
if (!I.isPreISelOpcode() || Opcode == TargetOpcode::G_PHI) {
// Certain non-generic instructions also need some special handling.
- if (Opcode == TargetOpcode::LOAD_STACK_GUARD)
- return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ if (Opcode == TargetOpcode::LOAD_STACK_GUARD) {
+ constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ return true;
+ }
if (Opcode == TargetOpcode::PHI || Opcode == TargetOpcode::G_PHI) {
const Register DefReg = I.getOperand(0).getReg();
@@ -2618,7 +2622,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
.addImm(LSB)
.addImm(LSB + Width - 1);
I.eraseFromParent();
- return constrainSelectedInstRegOperands(*BitfieldInst, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*BitfieldInst, TII, TRI, RBI);
+ return true;
}
case TargetOpcode::G_BRCOND:
return selectCompareBranch(I, MF, MRI);
@@ -2632,10 +2637,12 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
MI.addImm(*BADisc);
MI.addReg(/*AddrDisc=*/AArch64::XZR);
I.eraseFromParent();
- return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+ return true;
}
I.setDesc(TII.get(AArch64::BR));
- return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ return true;
}
case TargetOpcode::G_BRJT:
@@ -2650,7 +2657,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
if (BaseMI->getOpcode() != AArch64::ADRP) {
I.setDesc(TII.get(AArch64::ADDXri));
I.addOperand(MachineOperand::CreateImm(0));
- return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ return true;
}
assert(TM.getCodeModel() == CodeModel::Small &&
"Expected small code model");
@@ -2662,7 +2670,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
.addGlobalAddress(Op2.getGlobal(), Op2.getOffset(),
Op2.getTargetFlags());
I.eraseFromParent();
- return constrainSelectedInstRegOperands(*MovAddr, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*MovAddr, TII, TRI, RBI);
+ return true;
}
case TargetOpcode::G_FCONSTANT:
@@ -2837,7 +2846,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
if (SrcSize < 64) {
assert(SrcSize == 32 && DstTy.getSizeInBits() == 16 &&
"unexpected G_EXTRACT types");
- return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ return true;
}
DstReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
@@ -2848,7 +2858,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
AArch64::GPR32RegClass, MRI);
I.getOperand(0).setReg(DstReg);
- return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ return true;
}
case TargetOpcode::G_INSERT: {
@@ -2869,7 +2880,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
if (DstSize < 64) {
assert(DstSize == 32 && SrcTy.getSizeInBits() == 16 &&
"unexpected G_INSERT types");
- return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ return true;
}
Register SrcReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
@@ -2883,7 +2895,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
AArch64::GPR32RegClass, MRI);
I.getOperand(2).setReg(SrcReg);
- return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ return true;
}
case TargetOpcode::G_FRAME_INDEX: {
// allocas and G_FRAME_INDEX are only supported in addrspace(0).
@@ -2898,7 +2911,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
I.addOperand(MachineOperand::CreateImm(0));
I.addOperand(MachineOperand::CreateImm(0));
- return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ return true;
}
case TargetOpcode::G_GLOBAL_VALUE: {
@@ -2940,7 +2954,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
MIB.addGlobalAddress(GV, I.getOperand(1).getOffset(),
OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
}
- return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ return true;
}
case TargetOpcode::G_PTRAUTH_GLOBAL_VALUE:
@@ -3123,7 +3138,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
return RBI.constrainGenericRegister(DstReg, AArch64::GPR64allRegClass,
MRI);
}
- return constrainSelectedInstRegOperands(*LoadStore, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*LoadStore, TII, TRI, RBI);
+ return true;
}
case TargetOpcode::G_INDEXED_ZEXTLOAD:
@@ -3183,7 +3199,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
// Now that we selected an opcode, we need to constrain the register
// operands to use appropriate classes.
- return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ return true;
}
case TargetOpcode::G_PTR_ADD: {
@@ -3214,7 +3231,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
I.getOperand(2).ChangeToImmediate(
AArch64_AM::encodeLogicalImmediate(Mask, 64));
- return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ return true;
}
case TargetOpcode::G_PTRTOINT:
case TargetOpcode::G_TRUNC: {
@@ -3567,7 +3585,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
I.getOperand(1).getBlockAddress(), /* Offset */ 0,
AArch64II::MO_NC | AArch64II::MO_PAGEOFF);
I.eraseFromParent();
- return constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI);
+ return true;
}
}
case AArch64::G_DUP: {
@@ -3590,7 +3609,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
I.setDesc(TII.get(AArch64::DUPv8i16gpr));
else
return false;
- return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ return true;
}
case TargetOpcode::G_BUILD_VECTOR:
return selectBuildVector(I, MRI);
@@ -3725,7 +3745,8 @@ bool AArch64InstructionSelector::selectBrJT(MachineInstr &I,
// Build the indirect branch.
MIB.buildInstr(AArch64::BR, {}, {TargetReg});
I.eraseFromParent();
- return constrainSelectedInstRegOperands(*JumpTableInst, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*JumpTableInst, TII, TRI, RBI);
+ return true;
}
bool AArch64InstructionSelector::selectJumpTable(MachineInstr &I,
@@ -3741,7 +3762,8 @@ bool AArch64InstructionSelector::selectJumpTable(MachineInstr &I,
.addJumpTableIndex(JTI, AArch64II::MO_PAGE)
.addJumpTableIndex(JTI, AArch64II::MO_NC | AArch64II::MO_PAGEOFF);
I.eraseFromParent();
- return constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*MovMI, TII, TRI, RBI);
+ return true;
}
bool AArch64InstructionSelector::selectTLSGlobalValue(
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index bf1a032ea0f3d..b96c2ef70dd83 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -242,8 +242,7 @@ bool AMDGPUInstructionSelector::selectCOPY_SCC_VCC(MachineInstr &I) const {
.addReg(VCCReg);
}
- if (!constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI))
- return false;
+ constrainSelectedInstRegOperands(*Cmp, TII, TRI, RBI);
Register DstReg = I.getOperand(0).getReg();
BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), DstReg).addReg(AMDGPU::SCC);
@@ -284,7 +283,8 @@ bool AMDGPUInstructionSelector::selectCOPY_VCC_SCC(MachineInstr &I) const {
.addImm(0);
I.eraseFromParent();
- return constrainSelectedInstRegOperands(*Select, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*Select, TII, TRI, RBI);
+ return true;
}
bool AMDGPUInstructionSelector::selectReadAnyLane(MachineInstr &I) const {
@@ -298,7 +298,8 @@ bool AMDGPUInstructionSelector::selectReadAnyLane(MachineInstr &I) const {
.addReg(SrcReg);
I.eraseFromParent();
- return constrainSelectedInstRegOperands(*RFL, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*RFL, TII, TRI, RBI);
+ return true;
}
bool AMDGPUInstructionSelector::selectPHI(MachineInstr &I) const {
@@ -415,10 +416,11 @@ bool AMDGPUInstructionSelector::selectG_AND_OR_XOR(MachineInstr &I) const {
// Dead implicit-def of scc
I.addOperand(MachineOperand::CreateReg(AMDGPU::SCC, true, // isDef
- true, // isImp
- false, // isKill
- true)); // isDead
- return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ true, // isImp
+ false, // isKill
+ true)); // isDead
+ constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ return true;
}
bool AMDGPUInstructionSelector::selectG_ADD_SUB(MachineInstr &I) const {
@@ -444,7 +446,8 @@ bool AMDGPUInstructionSelector::selectG_ADD_SUB(MachineInstr &I) const {
.add(I.getOperand(2))
.setOperandDead(3); // Dead scc
I.eraseFromParent();
- return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*Add, TII, TRI, RBI);
+ return true;
}
if (STI.hasAddNoCarryInsts()) {
@@ -452,7 +455,8 @@ bool AMDGPUInstructionSelector::selectG_ADD_SUB(MachineInstr &I) const {
I.setDesc(TII.get(Opc));
I.addOperand(*MF, MachineOperand::CreateImm(0));
I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
- return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ return true;
}
const unsigned Opc = Sub ? AMDGPU::V_SUB_CO_U32_e64 : AMDGPU::V_ADD_CO_U32_e64;
@@ -465,7 +469,8 @@ bool AMDGPUInstructionSelector::selectG_ADD_SUB(MachineInstr &I) const {
.add(I.getOperand(2))
.addImm(0);
I.eraseFromParent();
- return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*Add, TII, TRI, RBI);
+ return true;
}
assert(!Sub && "illegal sub should not reach here");
@@ -506,8 +511,7 @@ bool AMDGPUInstructionSelector::selectG_ADD_SUB(MachineInstr &I) const {
.addReg(CarryReg, RegState::Kill)
.addImm(0);
- if (!constrainSelectedInstRegOperands(*Addc, TII, TRI, RBI))
- return false;
+ constrainSelectedInstRegOperands(*Addc, TII, TRI, RBI);
}
BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
@@ -543,7 +547,8 @@ bool AMDGPUInstructionSelector::selectG_UADDO_USUBO_UADDE_USUBE(
I.setDesc(TII.get(HasCarryIn ? CarryOpc : NoCarryOpc));
I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
I.addOperand(*MF, MachineOperand::CreateImm(0));
- return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ return true;
}
Register Src0Reg = I.getOperand(2).getReg();
@@ -609,7 +614,8 @@ bool AMDGPUInstructionSelector::selectG_AMDGPU_MAD_64_32(
I.addOperand(*MF, MachineOperand::CreateImm(0));
I.addImplicitDefUseOperands(*MF);
I.getOperand(0).setIsEarlyClobber(true);
- return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ return true;
}
// TODO: We should probably legalize these to only using 32-bit results.
@@ -825,15 +831,13 @@ bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR(MachineInstr &MI) const {
auto MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_AND_B32_e32), TmpReg)
.addImm(0xFFFF)
.addReg(Src0);
- if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI))
- return false;
+ constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_LSHL_OR_B32_e64), Dst)
.addReg(Src1)
.addImm(16)
.addReg(TmpReg);
- if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI))
- return false;
+ constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
MI.eraseFromParent();
return true;
@@ -879,7 +883,8 @@ bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR(MachineInstr &MI) const {
.setOperandDead(3); // Dead scc
MI.eraseFromParent();
- return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
+ return true;
}
if (STI.hasSPackHL()) {
Opc = AMDGPU::S_PACK_HL_B32_B16;
@@ -888,7 +893,8 @@ bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR(MachineInstr &MI) const {
}
MI.setDesc(TII.get(Opc));
- return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
+ return true;
}
bool AMDGPUInstructionSelector::selectG_IMPLICIT_DEF(MachineInstr &I) const {
@@ -986,7 +992,8 @@ bool AMDGPUInstructionSelector::selectG_SBFX_UBFX(MachineInstr &MI) const {
.addReg(OffsetReg)
.addReg(WidthReg);
MI.eraseFromParent();
- return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
+ return true;
}
bool AMDGPUInstructionSelector::selectInterpP1F16(MachineInstr &MI) const {
@@ -1088,7 +1095,8 @@ bool AMDGPUInstructionSelector::selectWritelane(MachineInstr &MI) const {
MIB.addReg(VDstIn);
MI.eraseFromParent();
- return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
+ return true;
}
// We need to handle this here because tablegen doesn't support matching
@@ -1129,7 +1137,8 @@ bool AMDGPUInstructionSelector::selectDivScale(MachineInstr &MI) const {
.addImm(0); // $omod
MI.eraseFromParent();
- return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
+ return true;
}
bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I) const {
@@ -1486,8 +1495,8 @@ bool AMDGPUInstructionSelector::selectG_ICMP_or_FCMP(MachineInstr &I) const {
.add(I.getOperand(3));
BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CCReg)
.addReg(AMDGPU::SCC);
+ constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI);
bool Ret =
- constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI) &&
RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32RegClass, *MRI);
I.eraseFromParent();
return Ret;
@@ -1517,9 +1526,9 @@ bool AMDGPUInstructionSelector::selectG_ICMP_or_FCMP(MachineInstr &I) const {
RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(),
*TRI.getBoolRC(), *MRI);
- bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI);
+ constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI);
I.eraseFromParent();
- return Ret;
+ return true;
}
bool AMDGPUInstructionSelector::selectIntrinsicCmp(MachineInstr &I) const {
@@ -1573,8 +1582,7 @@ bool AMDGPUInstructionSelector::selectIntrinsicCmp(MachineInstr &I) const {
SelectedMI.addImm(0); // op_sel
RBI.constrainGenericRegister(Dst, *TRI.getBoolRC(), *MRI);
- if (!constrainSelectedInstRegOperands(*SelectedMI, TII, TRI, RBI))
- return false;
+ constrainSelectedInstRegOperands(*SelectedMI, TII, TRI, RBI);
I.eraseFromParent();
return true;
@@ -1660,8 +1668,7 @@ bool AMDG...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/179501
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