[llvm] [HEXAGON] Extend/Truncate the shift amount into i32 (PR #179499)

[Abinaya Saravanan via llvm-commits]

https://github.com/quic-asaravan created https://github.com/llvm/llvm-project/pull/179499

Fixes a Backend error 

>From 2ea46bf99eb0358d648c923375b9f772efd5aa3f Mon Sep 17 00:00:00 2001
From: quic-asaravan <quic_asaravan at quicinc.com>
Date: Tue, 3 Feb 2026 08:41:47 -0800
Subject: [PATCH] [HEXAGON] Extend/Truncate the shift amount into i32

Fixes a Backend error
---
 .../Target/Hexagon/HexagonISelLowering.cpp    | 13 ++++++++--
 .../CodeGen/Hexagon/no-invalid-node-v4i16.ll  | 24 +++++++++++++++++++
 2 files changed, 35 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/Hexagon/no-invalid-node-v4i16.ll

diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 0ceb095cdc653..87c31eba8e9b9 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -2342,9 +2342,18 @@ HexagonTargetLowering::getVectorShiftByInt(SDValue Op, SelectionDAG &DAG)
     default:
       llvm_unreachable("Unexpected shift opcode");
   }
+  if (SDValue Sp = getSplatValue(Op.getOperand(1), DAG)) {
+    const SDLoc dl(Op);
+    // Canonicalize shift amount to i32 as required.
+    SDValue Sh = Sp;
+    if (Sh.getValueType() != MVT::i32)
+      Sh = DAG.getZExtOrTrunc(Sh, dl, MVT::i32);
+
+    assert(Sh.getValueType() == MVT::i32 &&
+           "Hexagon vector shift-by-int must use i32 shift operand");
+    return DAG.getNode(NewOpc, dl, ty(Op), Op.getOperand(0), Sh);
+  }
 
-  if (SDValue Sp = getSplatValue(Op.getOperand(1), DAG))
-    return DAG.getNode(NewOpc, SDLoc(Op), ty(Op), Op.getOperand(0), Sp);
   return SDValue();
 }
 
diff --git a/llvm/test/CodeGen/Hexagon/no-invalid-node-v4i16.ll b/llvm/test/CodeGen/Hexagon/no-invalid-node-v4i16.ll
new file mode 100644
index 0000000000000..32b4434faba91
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/no-invalid-node-v4i16.ll
@@ -0,0 +1,24 @@
+; REQUIRES: asserts
+; RUN: llc -march=hexagon -verify-machineinstrs -o - < %s 2>&1 | FileCheck %s
+
+; This is a crash / fatal-error regression test:
+; llc used to hit:
+;   LLVM ERROR: invalid node: operand #1 must have type i32, but has type i16
+; during DAG combine / ISel:
+;   t61: v4i16 = HexagonISD::VASR t56, Constant:i16<1>
+;   t56: v4i16 = mulhs ...
+;
+; The test ensures llc does NOT emit "LLVM ERROR" and produces assembly for the function.
+
+; CHECK-NOT: LLVM ERROR:
+; CHECK-NOT: invalid node:
+
+target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+target triple = "hexagon-unknown-linux-musl"
+
+define <8 x i16> @sq77777777(<8 x i16> %0) {
+; CHECK-LABEL: sq77777777:
+entry:
+  %div = sdiv <8 x i16> %0, splat (i16 7)
+  ret <8 x i16> %div
+}