[llvm] [RISCV] Don't emit VP_SETCC in combineVectorSizedSetCCEquality (PR #179479)

[Craig Topper via llvm-commits]

topperc wrote:

If we move RISCVVLOptimizer earlier as @mshockwave proposed in another PR, does that remove the need to run DeadMachineElim again?

https://github.com/llvm/llvm-project/pull/179479