[llvm] [SPIRV] selectDot4AddPacked: add missing PackedVectorFormat4x8Bit optional operand (PR #179476)
Juan Manuel Martinez CaamaƱo via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 3 07:09:37 PST 2026
https://github.com/jmmartinez updated https://github.com/llvm/llvm-project/pull/179476
>From 2692000d202e0ea317d568ec8e07c13c60f91b55 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Juan=20Manuel=20Martinez=20Caama=C3=B1o?=
<jmartinezcaamao at gmail.com>
Date: Tue, 3 Feb 2026 15:42:08 +0100
Subject: [PATCH] [SPIRV] selectDot4AddPacked: add missing
PackedVectorFormat4x8Bit optional operand
According to SPIRV:
```
PackedVectorFormat4x8Bit (PackedVectorFormat4x8BitKHR)
Interpret 32-bit scalar integer operands as vectors of four 8-bit
components. Vector components follow byte significance order with the
lowest-numbered component stored in the least significant byte.
```
And in OpSDot / OpUDot:
```
When Vector 1 and Vector 2 are scalar integer types, Packed Vector
Format must be specified to select how the integers are to be
interpreted as vectors.
```
---
.../Target/SPIRV/SPIRVInstructionSelector.cpp | 26 ++++++++++---------
.../SPIRV/hlsl-intrinsics/dot4add_i8packed.ll | 2 +-
.../SPIRV/hlsl-intrinsics/dot4add_u8packed.ll | 2 +-
3 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 765fa6277d4ca..6efd48761dafe 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -2534,19 +2534,21 @@ bool SPIRVInstructionSelector::selectDot4AddPacked(Register ResVReg,
auto DotOp = Signed ? SPIRV::OpSDot : SPIRV::OpUDot;
Register Dot = MRI->createVirtualRegister(GR.getRegClass(ResType));
- bool Result = BuildMI(BB, I, I.getDebugLoc(), TII.get(DotOp))
- .addDef(Dot)
- .addUse(GR.getSPIRVTypeID(ResType))
- .addUse(X)
- .addUse(Y)
- .constrainAllUses(TII, TRI, RBI);
+ auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(DotOp))
+ .addDef(Dot)
+ .addUse(GR.getSPIRVTypeID(ResType))
+ .addUse(X)
+ .addUse(Y);
+ MIB.addImm(SPIRV::BuiltIn::PackedVectorFormat4x8Bit);
+ MIB.constrainAllUses(TII, TRI, RBI);
- return Result && BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS))
- .addDef(ResVReg)
- .addUse(GR.getSPIRVTypeID(ResType))
- .addUse(Dot)
- .addUse(Acc)
- .constrainAllUses(TII, TRI, RBI);
+ BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS))
+ .addDef(ResVReg)
+ .addUse(GR.getSPIRVTypeID(ResType))
+ .addUse(Dot)
+ .addUse(Acc)
+ .constrainAllUses(TII, TRI, RBI);
+ return true;
}
// Since pre-1.6 SPIRV has no DotProductInput4x8BitPacked implementation,
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_i8packed.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_i8packed.ll
index 9ff4babd8a918..f756762755b51 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_i8packed.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_i8packed.ll
@@ -25,7 +25,7 @@ entry:
; Test that we use the dot product op when capabilities allow
-; CHECK-DOT: %[[#DOT:]] = OpSDot %[[#int_32]] %[[#X]] %[[#Y]]
+; CHECK-DOT: %[[#DOT:]] = OpSDot %[[#int_32]] %[[#X]] %[[#Y]] PackedVectorFormat4x8Bit
; CHECK-DOT: %[[#RES:]] = OpIAdd %[[#int_32]] %[[#DOT]] %[[#ACC]]
; Test expansion is used when spirv dot product capabilities aren't available:
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_u8packed.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_u8packed.ll
index 5e41c9dc79dd2..907cf622f609f 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_u8packed.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/dot4add_u8packed.ll
@@ -25,7 +25,7 @@ entry:
; Test that we use the dot product op when capabilities allow
-; CHECK-DOT: %[[#DOT:]] = OpUDot %[[#int_32]] %[[#X]] %[[#Y]]
+; CHECK-DOT: %[[#DOT:]] = OpUDot %[[#int_32]] %[[#X]] %[[#Y]] PackedVectorFormat4x8Bit
; CHECK-DOT: %[[#RES:]] = OpIAdd %[[#int_32]] %[[#DOT]] %[[#ACC]]
; Test expansion is used when spirv dot product capabilities aren't available:
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