[llvm] AMDGPU/GlobalISel: add mir test for sgpr s16 unmerge (PR #179440)

[Petar Avramovic via llvm-commits]

https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/179440

>From aff1d3382f0e089c7e4ba534083e8e6bf5792e89 Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Tue, 3 Feb 2026 12:31:43 +0100
Subject: [PATCH] AMDGPU/GlobalISel: add mir test for sgpr s16 unmerge

---
 .../AMDGPU/GlobalISel/unmerge-sgpr-s16.mir    | 65 +++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
new file mode 100644
index 0000000000000..39eaa44bdd090
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/unmerge-sgpr-s16.mir
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=amdgpu-regbanklegalize %s -o - | FileCheck %s
+
+---
+name: unmerge_sgprS16_from_V2S16
+legalized: true
+body: |
+  bb.0:
+    liveins: $sgpr0, $sgpr2_sgpr3
+
+    ; CHECK-LABEL: name: unmerge_sgprS16_from_V2S16
+    ; CHECK: liveins: $sgpr0, $sgpr2_sgpr3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(p1) = COPY $sgpr2_sgpr3
+    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
+    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[C]](s32)
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[BITCAST]](s32)
+    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[LSHR]](s32)
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR [[TRUNC1]](s16), [[TRUNC]](s16)
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR]](<2 x s16>)
+    ; CHECK-NEXT: G_STORE [[COPY2]](<2 x s16>), [[COPY1]](p1) :: (store (<2 x s16>), addrspace 1)
+    ; CHECK-NEXT: S_ENDPGM 0
+    %0:sgpr(<2 x s16>) = COPY $sgpr0
+    %1:sgpr(p1) = COPY $sgpr2_sgpr3
+    %2:sgpr(s16), %3:sgpr(s16) = G_UNMERGE_VALUES %0(<2 x s16>)
+    %4:sgpr(<2 x s16>) = G_BUILD_VECTOR %3(s16), %2(s16)
+    G_STORE %4(<2 x s16>), %1(p1) :: (store (<2 x s16>), addrspace 1)
+    S_ENDPGM 0
+...
+
+---
+name: unmerge_sgprS16_from_V4S16
+legalized: true
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
+
+    ; CHECK-LABEL: name: unmerge_sgprS16_from_V4S16
+    ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(p1) = COPY $sgpr2_sgpr3
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
+    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[UV]](s32)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
+    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST]], [[C]](s32)
+    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[BITCAST]](s32)
+    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[LSHR]](s32)
+    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[UV1]](s32)
+    ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:sgpr(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
+    ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[BITCAST1]](s32)
+    ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:sgpr(s16) = G_TRUNC [[LSHR1]](s32)
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC3]](s16)
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR]](<2 x s16>)
+    ; CHECK-NEXT: G_STORE [[COPY2]](<2 x s16>), [[COPY1]](p1) :: (store (<2 x s16>), addrspace 1)
+    ; CHECK-NEXT: S_ENDPGM 0
+    %0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
+    %1:sgpr(p1) = COPY $sgpr2_sgpr3
+    %2:sgpr(s16), %3:sgpr(s16), %4:sgpr(s16), %5:sgpr(s16) = G_UNMERGE_VALUES %0(<4 x s16>)
+    %6:sgpr(<2 x s16>) = G_BUILD_VECTOR %2(s16), %5(s16)
+    G_STORE %6(<2 x s16>), %1(p1) :: (store (<2 x s16>), addrspace 1)
+    S_ENDPGM 0
+...