[llvm] [AMDGPU] Implement llvm.sponentry (PR #176357)

[Diana Picus via llvm-commits]

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@@ -7759,6 +7760,24 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
   // Replace the use G_BRCOND with the exec manipulate and branch pseudos.
   auto IntrID = cast<GIntrinsic>(MI).getIntrinsicID();
   switch (IntrID) {
+  case Intrinsic::sponentry:
+    if (B.getMF().getInfo<SIMachineFunctionInfo>()->isBottomOfStack()) {
+      // FIXME: The imported pattern checks for i32 instead of p5; if we fix
+      // that we can remove this cast.
+      const LLT S32 = LLT::scalar(32);
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rovka wrote:

I'm not sure where to add the explicit p5. Did you mean in the TableGen definition?

The pattern in SIInstructions.td is already written with p5 for the output, but the generated code in AMDGPUGenGlobalISel.inc looks like this (note the GILLT_s32):
```
/* 2023706 */ // Label 168: @2023706
/* 2023706 */ GIM_Try, /*On fail goto*//*Label 29065*/ GIMT_Encode4(2023731), // Rule ID 4295 //
/* 2023711 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
/* 2023714 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_32RegClassID),
/* 2023718 */   // (sponentry:{ *:[i32] })  =>  (GET_STACK_BASE:{ *:[i32] }:{ *:[i1] })
/* 2023718 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GET_STACK_BASE),
/* 2023723 */   GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(static_cast<unsigned>(RegState::Dead)),
/* 2023729 */   GIR_RootConstrainSelectedInstOperands,
/* 2023730 */   // GIR_Coverage, 4295,
/* 2023730 */   GIR_Done,
```
Did you have some workaround in mind?

For reference, this is what  I was trying to select without the cast: `LLVM ERROR: cannot select: %2:sreg_32(p5) = G_AMDGPU_SPONENTRY (in function: sponentry_cs_dvgpr_16)`.

https://github.com/llvm/llvm-project/pull/176357