[llvm] [AArch64][GlobalISel] Add GISel handling for FCVT fixed. (PR #178903)

[Cullen Rhodes via llvm-commits]

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@@ -7847,6 +7853,60 @@ AArch64InstructionSelector::selectExtractHigh(MachineOperand &Root) const {
   return std::nullopt;
 }
 
+InstructionSelector::ComplexRendererFns
+AArch64InstructionSelector::selectCVTFixedPointVecBase(
+    const MachineOperand &Root) const {
+  if (!Root.isReg())
+    return std::nullopt;
+  const MachineRegisterInfo &MRI =
+      Root.getParent()->getParent()->getParent()->getRegInfo();
+
+  MachineInstr *Dup = getDefIgnoringCopies(Root.getReg(), MRI);
+  if (Dup->getOpcode() != AArch64::G_DUP)
+    return std::nullopt;
+  std::optional<ValueAndVReg> CstVal =
+      getAnyConstantVRegValWithLookThrough(Dup->getOperand(1).getReg(), MRI);
+  if (!CstVal)
+    return std::nullopt;
+
+  unsigned RegWidth = MRI.getType(Root.getReg()).getScalarSizeInBits();
+  APFloat FVal(0.0);
+  switch (RegWidth) {
+  case 16:
+    FVal = APFloat(APFloat::IEEEhalf(), CstVal->Value);
+    break;
+  case 32:
+    FVal = APFloat(APFloat::IEEEsingle(), CstVal->Value);
+    break;
+  case 64:
+    FVal = APFloat(APFloat::IEEEdouble(), CstVal->Value);
+    break;
+  default:
+    return std::nullopt;
+  };
+  if (unsigned FBits = CheckFixedPointOperandConstant(FVal, RegWidth,
+                                                      /*isReciprocal*/ false))
+    return {{[=](MachineInstrBuilder &MIB) { MIB.addImm(FBits); }}};
+
+  return std::nullopt;
+}
+
+InstructionSelector::ComplexRendererFns
+AArch64InstructionSelector::selectCVTFixedPointVec(MachineOperand &Root) const {
+  return selectCVTFixedPointVecBase(Root);
+}
+
+void AArch64InstructionSelector::renderFixedPointXForm(MachineInstrBuilder &MIB,
+                                                       const MachineInstr &MI,
+                                                       int OpIdx) const {
+  // This is only needed to
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c-rhodes wrote:

only needed to? 

https://github.com/llvm/llvm-project/pull/178903