[llvm] 651a451 - [RISCV] Sink conversion from nfields/lmul to nf down one level in RISCVInstrInfoV.td. NFC (#179369)
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Mon Feb 2 23:48:01 PST 2026
Author: Craig Topper
Date: 2026-02-02T23:47:56-08:00
New Revision: 651a45122730ef6aef3dc5c8963fc4d702268af2
URL: https://github.com/llvm/llvm-project/commit/651a45122730ef6aef3dc5c8963fc4d702268af2
DIFF: https://github.com/llvm/llvm-project/commit/651a45122730ef6aef3dc5c8963fc4d702268af2.diff
LOG: [RISCV] Sink conversion from nfields/lmul to nf down one level in RISCVInstrInfoV.td. NFC (#179369)
The nf field is encoded as nfields/lmul minus one. Use asserts to
verify this doesn't lose any information.
The asserts increase the number of lines, but I think this makes the
class interfaces a more logical level than encoding.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 7b6c36f288177..d37f6f1f19bff 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -346,10 +346,12 @@ class VUnitStrideLoad<RISCVWidth width, string opcodestr>
let vm = 1, RVVConstraint = NoConstraint in {
// unit-stride whole register load vl<nf>r.v vd, (rs1)
-class VWholeLoad<bits<3> nf, RISCVWidth width, string opcodestr, RegisterClass VRC>
- : RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideWholeReg,
+class VWholeLoad<int lmul, RISCVWidth width, string opcodestr, RegisterClass VRC>
+ : RVInstVLU<!sub(lmul, 1), width.Value{3}, LUMOPUnitStrideWholeReg,
width.Value{2-0}, (outs VRC:$vd), (ins GPRMemZeroOffset:$rs1),
opcodestr, "$vd, $rs1"> {
+ assert !and(!ge(lmul, 1), !le(lmul, 8)), "lmul must be 1-8";
+
let Uses = [];
}
@@ -381,31 +383,39 @@ class VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
"$vd, $rs1, $vs2$vm">;
// unit-stride segment load vd, (rs1), vm
-class VUnitStrideSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
- : RVInstVLU<nf, width.Value{3}, LUMOPUnitStride, width.Value{2-0},
+class VUnitStrideSegmentLoad<int nfields, RISCVWidth width, string opcodestr>
+ : RVInstVLU<!sub(nfields, 1), width.Value{3}, LUMOPUnitStride, width.Value{2-0},
(outs VR:$vd),
- (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm">;
+ (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm"> {
+ assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8";
+}
// segment fault-only-first load vd, (rs1), vm
-class VUnitStrideSegmentLoadFF<bits<3> nf, RISCVWidth width, string opcodestr>
- : RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideFF, width.Value{2-0},
+class VUnitStrideSegmentLoadFF<int nfields, RISCVWidth width, string opcodestr>
+ : RVInstVLU<!sub(nfields, 1), width.Value{3}, LUMOPUnitStrideFF, width.Value{2-0},
(outs VR:$vd),
- (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm">;
+ (ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm"> {
+ assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8";
+}
// strided segment load vd, (rs1), rs2, vm
-class VStridedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
- : RVInstVLS<nf, width.Value{3}, width.Value{2-0},
+class VStridedSegmentLoad<int nfields, RISCVWidth width, string opcodestr>
+ : RVInstVLS<!sub(nfields, 1), width.Value{3}, width.Value{2-0},
(outs VR:$vd),
(ins GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr,
- "$vd, $rs1, $rs2$vm">;
+ "$vd, $rs1, $rs2$vm"> {
+ assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8";
+}
// indexed segment load vd, (rs1), vs2, vm
-class VIndexedSegmentLoad<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+class VIndexedSegmentLoad<int nfields, RISCVMOP mop, RISCVWidth width,
string opcodestr>
- : RVInstVLX<nf, width.Value{3}, mop, width.Value{2-0},
+ : RVInstVLX<!sub(nfields, 1), width.Value{3}, mop, width.Value{2-0},
(outs VR:$vd),
(ins GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
- "$vd, $rs1, $vs2$vm">;
+ "$vd, $rs1, $vs2$vm"> {
+ assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8";
+}
} // hasSideEffects = 0, mayLoad = 1, mayStore = 0
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
@@ -416,11 +426,13 @@ class VUnitStrideStore<RISCVWidth width, string opcodestr>
"$vs3, ${rs1}$vm">;
let vm = 1 in {
-// vs<nf>r.v vd, (rs1)
-class VWholeStore<bits<3> nf, string opcodestr, RegisterClass VRC>
- : RVInstVSU<nf, 0, SUMOPUnitStrideWholeReg,
+// vs<lmul>r.v vd, (rs1)
+class VWholeStore<int lmul, string opcodestr, RegisterClass VRC>
+ : RVInstVSU<!sub(lmul, 1), 0, SUMOPUnitStrideWholeReg,
0b000, (outs), (ins VRC:$vs3, GPRMemZeroOffset:$rs1),
opcodestr, "$vs3, $rs1"> {
+ assert !and(!ge(lmul, 1), !le(lmul, 8)), "lmul must be 1-8";
+
let Uses = [];
}
@@ -444,23 +456,29 @@ class VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
opcodestr, "$vs3, $rs1, $vs2$vm">;
// segment store vd, vs3, (rs1), vm
-class VUnitStrideSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
- : RVInstVSU<nf, width.Value{3}, SUMOPUnitStride, width.Value{2-0},
+class VUnitStrideSegmentStore<int nfields, RISCVWidth width, string opcodestr>
+ : RVInstVSU<!sub(nfields, 1), width.Value{3}, SUMOPUnitStride, width.Value{2-0},
(outs), (ins VR:$vs3, GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr,
- "$vs3, ${rs1}$vm">;
+ "$vs3, ${rs1}$vm"> {
+ assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8";
+}
// segment store vd, vs3, (rs1), rs2, vm
-class VStridedSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
- : RVInstVSS<nf, width.Value{3}, width.Value{2-0}, (outs),
+class VStridedSegmentStore<int nfields, RISCVWidth width, string opcodestr>
+ : RVInstVSS<!sub(nfields, 1), width.Value{3}, width.Value{2-0}, (outs),
(ins VR:$vs3, GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
- opcodestr, "$vs3, $rs1, $rs2$vm">;
+ opcodestr, "$vs3, $rs1, $rs2$vm"> {
+ assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8";
+}
// segment store vd, vs3, (rs1), vs2, vm
-class VIndexedSegmentStore<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+class VIndexedSegmentStore<int nfields, RISCVMOP mop, RISCVWidth width,
string opcodestr>
- : RVInstVSX<nf, width.Value{3}, mop, width.Value{2-0}, (outs),
+ : RVInstVSX<!sub(nfields, 1), width.Value{3}, mop, width.Value{2-0}, (outs),
(ins VR:$vs3, GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm),
- opcodestr, "$vs3, $rs1, $vs2$vm">;
+ opcodestr, "$vs3, $rs1, $vs2$vm"> {
+ assert !and(!ge(nfields, 2), !le(nfields, 8)), "nfields must be 2-8";
+}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 1
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
@@ -1061,12 +1079,12 @@ multiclass VCPR_MV_Mask<string opcodestr, bits<6> funct6, string vm = "v"> {
SchedBinaryMC<"WriteVCompressV", "ReadVCompressV", "ReadVCompressV">;
}
-multiclass VWholeLoadN<int l, bits<3> nf, string opcodestr, RegisterClass VRC> {
- defvar w = !cast<RISCVWidth>("LSWidth" # l);
- defvar s = !cast<SchedWrite>("WriteVLD" # !add(nf, 1) # "R");
+multiclass VWholeLoadN<int eew, int lmul, string opcodestr, RegisterClass VRC> {
+ defvar w = !cast<RISCVWidth>("LSWidth" # eew);
+ defvar s = !cast<SchedWrite>("WriteVLD" # lmul # "R");
- def E # l # _V : VWholeLoad<nf, w, opcodestr # "e" # l # ".v", VRC>,
- Sched<[s, ReadVLDX]>;
+ def E # eew # _V : VWholeLoad<lmul, w, opcodestr # "e" # eew # ".v", VRC>,
+ Sched<[s, ReadVLDX]>;
}
//===----------------------------------------------------------------------===//
@@ -1104,10 +1122,10 @@ foreach eew = [8, 16, 32, 64] in {
def VLSE#eew#_V : VStridedLoad<w, "vlse"#eew#".v">, VLSSchedMC<eew>;
def VSSE#eew#_V : VStridedStore<w, "vsse"#eew#".v">, VSSSchedMC<eew>;
- defm VL1R : VWholeLoadN<eew, 0, "vl1r", VR>;
- defm VL2R : VWholeLoadN<eew, 1, "vl2r", VRM2>;
- defm VL4R : VWholeLoadN<eew, 3, "vl4r", VRM4>;
- defm VL8R : VWholeLoadN<eew, 7, "vl8r", VRM8>;
+ defm VL1R : VWholeLoadN<eew, 1, "vl1r", VR>;
+ defm VL2R : VWholeLoadN<eew, 2, "vl2r", VRM2>;
+ defm VL4R : VWholeLoadN<eew, 4, "vl4r", VRM4>;
+ defm VL8R : VWholeLoadN<eew, 8, "vl8r", VRM8>;
}
let Predicates = !if(!eq(eew, 64), [IsRV64, HasVInstructionsI64],
@@ -1123,13 +1141,13 @@ def VSM_V : VUnitStrideMaskStore<"vsm.v">,
def : MnemonicAlias<"vle1.v", "vlm.v">;
def : MnemonicAlias<"vse1.v", "vsm.v">;
-def VS1R_V : VWholeStore<0, "vs1r.v", VR>,
+def VS1R_V : VWholeStore<1, "vs1r.v", VR>,
Sched<[WriteVST1R, ReadVST1R, ReadVSTX]>;
-def VS2R_V : VWholeStore<1, "vs2r.v", VRM2>,
+def VS2R_V : VWholeStore<2, "vs2r.v", VRM2>,
Sched<[WriteVST2R, ReadVST2R, ReadVSTX]>;
-def VS4R_V : VWholeStore<3, "vs4r.v", VRM4>,
+def VS4R_V : VWholeStore<4, "vs4r.v", VRM4>,
Sched<[WriteVST4R, ReadVST4R, ReadVSTX]>;
-def VS8R_V : VWholeStore<7, "vs8r.v", VRM8>,
+def VS8R_V : VWholeStore<8, "vs8r.v", VRM8>,
Sched<[WriteVST8R, ReadVST8R, ReadVSTX]>;
def : InstAlias<"vl1r.v $vd, $rs1", (VL1RE8_V VR:$vd, GPRMemZeroOffset:$rs1)>;
@@ -1774,40 +1792,40 @@ let Predicates = [HasVInstructions] in {
defvar w = !cast<RISCVWidth>("LSWidth"#eew);
def VLSEG#nfields#E#eew#_V :
- VUnitStrideSegmentLoad<!add(nfields, -1), w, "vlseg"#nfields#"e"#eew#".v">,
+ VUnitStrideSegmentLoad<nfields, w, "vlseg"#nfields#"e"#eew#".v">,
VLSEGSchedMC<nfields, eew>;
def VLSEG#nfields#E#eew#FF_V :
- VUnitStrideSegmentLoadFF<!add(nfields, -1), w, "vlseg"#nfields#"e"#eew#"ff.v">,
+ VUnitStrideSegmentLoadFF<nfields, w, "vlseg"#nfields#"e"#eew#"ff.v">,
VLSEGFFSchedMC<nfields, eew>;
def VSSEG#nfields#E#eew#_V :
- VUnitStrideSegmentStore<!add(nfields, -1), w, "vsseg"#nfields#"e"#eew#".v">,
+ VUnitStrideSegmentStore<nfields, w, "vsseg"#nfields#"e"#eew#".v">,
VSSEGSchedMC<nfields, eew>;
// Vector Strided Instructions
def VLSSEG#nfields#E#eew#_V :
- VStridedSegmentLoad<!add(nfields, -1), w, "vlsseg"#nfields#"e"#eew#".v">,
+ VStridedSegmentLoad<nfields, w, "vlsseg"#nfields#"e"#eew#".v">,
VLSSEGSchedMC<nfields, eew>;
def VSSSEG#nfields#E#eew#_V :
- VStridedSegmentStore<!add(nfields, -1), w, "vssseg"#nfields#"e"#eew#".v">,
+ VStridedSegmentStore<nfields, w, "vssseg"#nfields#"e"#eew#".v">,
VSSSEGSchedMC<nfields, eew>;
// Vector Indexed Instructions
def VLUXSEG#nfields#EI#eew#_V :
- VIndexedSegmentLoad<!add(nfields, -1), MOPLDIndexedUnord, w,
+ VIndexedSegmentLoad<nfields, MOPLDIndexedUnord, w,
"vluxseg"#nfields#"ei"#eew#".v">,
RISCVVXMemOpMC<!logtwo(eew), Ordered=false, Store=false, N=nfields>,
VLXSEGSchedMC<nfields, eew, isOrdered=0>;
def VLOXSEG#nfields#EI#eew#_V :
- VIndexedSegmentLoad<!add(nfields, -1), MOPLDIndexedOrder, w,
+ VIndexedSegmentLoad<nfields, MOPLDIndexedOrder, w,
"vloxseg"#nfields#"ei"#eew#".v">,
RISCVVXMemOpMC<!logtwo(eew), Ordered=true, Store=false, N=nfields>,
VLXSEGSchedMC<nfields, eew, isOrdered=1>;
def VSUXSEG#nfields#EI#eew#_V :
- VIndexedSegmentStore<!add(nfields, -1), MOPSTIndexedUnord, w,
+ VIndexedSegmentStore<nfields, MOPSTIndexedUnord, w,
"vsuxseg"#nfields#"ei"#eew#".v">,
RISCVVXMemOpMC<!logtwo(eew), Ordered=false, Store=true, N=nfields>,
VSXSEGSchedMC<nfields, eew, isOrdered=0>;
def VSOXSEG#nfields#EI#eew#_V :
- VIndexedSegmentStore<!add(nfields, -1), MOPSTIndexedOrder, w,
+ VIndexedSegmentStore<nfields, MOPSTIndexedOrder, w,
"vsoxseg"#nfields#"ei"#eew#".v">,
RISCVVXMemOpMC<!logtwo(eew), Ordered=true, Store=true, N=nfields>,
VSXSEGSchedMC<nfields, eew, isOrdered=1>;
@@ -1819,21 +1837,21 @@ let Predicates = [HasVInstructionsI64] in {
foreach nfields=2-8 in {
// Vector Unit-strided Segment Instructions
def VLSEG#nfields#E64_V :
- VUnitStrideSegmentLoad<!add(nfields, -1), LSWidth64, "vlseg"#nfields#"e64.v">,
+ VUnitStrideSegmentLoad<nfields, LSWidth64, "vlseg"#nfields#"e64.v">,
VLSEGSchedMC<nfields, 64>;
def VLSEG#nfields#E64FF_V :
- VUnitStrideSegmentLoadFF<!add(nfields, -1), LSWidth64, "vlseg"#nfields#"e64ff.v">,
+ VUnitStrideSegmentLoadFF<nfields, LSWidth64, "vlseg"#nfields#"e64ff.v">,
VLSEGFFSchedMC<nfields, 64>;
def VSSEG#nfields#E64_V :
- VUnitStrideSegmentStore<!add(nfields, -1), LSWidth64, "vsseg"#nfields#"e64.v">,
+ VUnitStrideSegmentStore<nfields, LSWidth64, "vsseg"#nfields#"e64.v">,
VSSEGSchedMC<nfields, 64>;
// Vector Strided Segment Instructions
def VLSSEG#nfields#E64_V :
- VStridedSegmentLoad<!add(nfields, -1), LSWidth64, "vlsseg"#nfields#"e64.v">,
+ VStridedSegmentLoad<nfields, LSWidth64, "vlsseg"#nfields#"e64.v">,
VLSSEGSchedMC<nfields, 64>;
def VSSSEG#nfields#E64_V :
- VStridedSegmentStore<!add(nfields, -1), LSWidth64, "vssseg"#nfields#"e64.v">,
+ VStridedSegmentStore<nfields, LSWidth64, "vssseg"#nfields#"e64.v">,
VSSSEGSchedMC<nfields, 64>;
}
} // Predicates = [HasVInstructionsI64]
@@ -1841,19 +1859,19 @@ let Predicates = [HasVInstructionsI64, IsRV64] in {
foreach nfields = 2 - 8 in {
// Vector Indexed Segment Instructions
def VLUXSEG #nfields #EI64_V
- : VIndexedSegmentLoad<!add(nfields, -1), MOPLDIndexedUnord, LSWidth64,
+ : VIndexedSegmentLoad<nfields, MOPLDIndexedUnord, LSWidth64,
"vluxseg" #nfields #"ei64.v">,
VLXSEGSchedMC<nfields, 64, isOrdered=0>;
def VLOXSEG #nfields #EI64_V
- : VIndexedSegmentLoad<!add(nfields, -1), MOPLDIndexedOrder, LSWidth64,
+ : VIndexedSegmentLoad<nfields, MOPLDIndexedOrder, LSWidth64,
"vloxseg" #nfields #"ei64.v">,
VLXSEGSchedMC<nfields, 64, isOrdered=1>;
def VSUXSEG #nfields #EI64_V
- : VIndexedSegmentStore<!add(nfields, -1), MOPSTIndexedUnord, LSWidth64,
+ : VIndexedSegmentStore<nfields, MOPSTIndexedUnord, LSWidth64,
"vsuxseg" #nfields #"ei64.v">,
VSXSEGSchedMC<nfields, 64, isOrdered=0>;
def VSOXSEG #nfields #EI64_V
- : VIndexedSegmentStore<!add(nfields, -1), MOPSTIndexedOrder, LSWidth64,
+ : VIndexedSegmentStore<nfields, MOPSTIndexedOrder, LSWidth64,
"vsoxseg" #nfields #"ei64.v">,
VSXSEGSchedMC<nfields, 64, isOrdered=1>;
}
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