[llvm] [NFC][TableGen] Adopt CodeGenHelpers in RegInfoEmitter (PR #179017)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 2 08:12:47 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-tablegen
Author: Rahul Joshi (jurahul)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/179017.diff
4 Files Affected:
- (modified) llvm/include/llvm/TableGen/CodeGenHelpers.h (+12-4)
- (modified) llvm/test/TableGen/bare-minimum-psets.td (+3-3)
- (modified) llvm/test/TableGen/pset-enum.td (+2-2)
- (modified) llvm/utils/TableGen/RegisterInfoEmitter.cpp (+69-94)
``````````diff
diff --git a/llvm/include/llvm/TableGen/CodeGenHelpers.h b/llvm/include/llvm/TableGen/CodeGenHelpers.h
index 41b0adc49d1ad..7d778a38abdb0 100644
--- a/llvm/include/llvm/TableGen/CodeGenHelpers.h
+++ b/llvm/include/llvm/TableGen/CodeGenHelpers.h
@@ -83,14 +83,17 @@ class IncludeGuardEmitter {
// namespace scope.
class NamespaceEmitter {
public:
- NamespaceEmitter(raw_ostream &OS, StringRef NameUntrimmed)
- : Name(trim(NameUntrimmed).str()), OS(OS) {
- if (!Name.empty())
+ NamespaceEmitter(raw_ostream &OS, StringRef NameUntrimmed,
+ bool Anonymous = false)
+ : Name(trim(NameUntrimmed).str()), OS(OS), Anonymous(Anonymous) {
+ assert((!Anonymous || NameUntrimmed.empty()) &&
+ "Expect empty name for anonymous namespace");
+ if (enableEmit())
OS << "namespace " << Name << " {\n\n";
}
~NamespaceEmitter() {
- if (!Name.empty())
+ if (enableEmit())
OS << "\n} // namespace " << Name << "\n";
}
@@ -106,8 +109,13 @@ class NamespaceEmitter {
Name.consume_front("::");
return Name;
}
+
+ // Emit the namespace if its not empty or if its anonymous.
+ bool enableEmit() const { return !Name.empty() || Anonymous; }
+
std::string Name;
raw_ostream &OS;
+ bool Anonymous;
};
} // end namespace llvm
diff --git a/llvm/test/TableGen/bare-minimum-psets.td b/llvm/test/TableGen/bare-minimum-psets.td
index 25e0bd2a83d1d..f0cc2b045e396 100644
--- a/llvm/test/TableGen/bare-minimum-psets.td
+++ b/llvm/test/TableGen/bare-minimum-psets.td
@@ -42,10 +42,10 @@ def MyTarget : Target;
// CHECK-LABEL: // Register pressure sets enum.
// CHECK-NEXT: namespace MyTarget {
-// CHECK-NEXT: enum RegisterPressureSets {
+// CHECK: enum RegisterPressureSets {
// CHECK-NEXT: D_32 = 0,
-// CHECK-NEXT: };
-// NAMESPACE-NEXT: } // end namespace TestNamespace
+// CHECK-NEXT: };
+// CHECK: } // namespace MyTarget
// CHECK-LABEL: getRegPressureSetName(unsigned Idx) const {
// CHECK-NEXT: static const char *PressureNameTable[] = {
diff --git a/llvm/test/TableGen/pset-enum.td b/llvm/test/TableGen/pset-enum.td
index c4c58c2ce6409..8010c3438f118 100644
--- a/llvm/test/TableGen/pset-enum.td
+++ b/llvm/test/TableGen/pset-enum.td
@@ -5,7 +5,7 @@ include "reg-with-subregs-common.td"
// CHECK-LABEL: // Register pressure sets enum.
// NAMESPACE-NEXT: namespace TestNamespace {
-// CHECK-NEXT: enum RegisterPressureSets {
+// CHECK: enum RegisterPressureSets {
// CHECK-NEXT: GPR32 = 0,
// CHECK-NEXT: };
-// NAMESPACE-NEXT: } // end namespace TestNamespace
+// NAMESPACE: } // namespace TestNamespace
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 548c1503f4647..d77c2f93d29ba 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -30,6 +30,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/TableGen/CodeGenHelpers.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/SetTheory.h"
@@ -102,10 +103,8 @@ class RegisterInfoEmitter {
static void emitInclude(StringRef FilenamePrefix, StringRef IncludeFile,
StringRef GuardMacro, raw_ostream &OS) {
- OS << "#ifdef " << GuardMacro << '\n';
- OS << "#undef " << GuardMacro << '\n';
+ IfDefEmitter IfDed(OS, GuardMacro);
OS << "#include \"" << FilenamePrefix << IncludeFile << "\"\n";
- OS << "#endif\n\n";
}
// runEnums - Print out enum values for all of the registers.
@@ -122,41 +121,36 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, raw_ostream &MainOS,
emitSourceFileHeader("Target Register Enum Values", OS);
- OS << "namespace llvm {\n\n";
+ NamespaceEmitter LlvmNS(OS, "llvm");
OS << "class MCRegisterClass;\n"
<< "extern const MCRegisterClass " << Target.getName()
<< "MCRegisterClasses[];\n\n";
- if (!Namespace.empty())
- OS << "namespace " << Namespace << " {\n";
- OS << "enum : unsigned {\n NoRegister,\n";
+ {
+ NamespaceEmitter RegNS(OS, Namespace);
+ OS << "enum : unsigned {\n NoRegister,\n";
- for (const auto &Reg : Registers)
- OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n";
- assert(Registers.size() == Registers.back().EnumValue &&
- "Register enum value mismatch!");
- OS << " NUM_TARGET_REGS // " << Registers.size() + 1 << "\n";
- OS << "};\n";
- if (!Namespace.empty())
- OS << "} // end namespace " << Namespace << "\n";
+ for (const auto &Reg : Registers)
+ OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n";
+ assert(Registers.size() == Registers.back().EnumValue &&
+ "Register enum value mismatch!");
+ OS << " NUM_TARGET_REGS // " << Registers.size() + 1 << "\n";
+ OS << "};\n";
+ }
const auto &RegisterClasses = RegBank.getRegClasses();
if (!RegisterClasses.empty()) {
-
// RegisterClass enums are stored as uint16_t in the tables.
assert(RegisterClasses.size() <= 0xffff &&
"Too many register classes to fit in tables");
OS << "\n// Register classes\n\n";
- if (!Namespace.empty())
- OS << "namespace " << Namespace << " {\n";
+ NamespaceEmitter RegNS(OS, Namespace);
OS << "enum {\n";
for (const auto &RC : RegisterClasses)
OS << " " << RC.getIdName() << " = " << RC.EnumValue << ",\n";
OS << "\n};\n";
- if (!Namespace.empty())
- OS << "} // end namespace " << Namespace << "\n\n";
}
ArrayRef<const Record *> RegAltNameIndices = Target.getRegAltNameIndices();
@@ -164,47 +158,36 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, raw_ostream &MainOS,
// emit anything.
if (RegAltNameIndices.size() > 1) {
OS << "\n// Register alternate name indices\n\n";
- if (!Namespace.empty())
- OS << "namespace " << Namespace << " {\n";
+ NamespaceEmitter RegNS(OS, Namespace);
OS << "enum {\n";
for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
OS << "};\n";
- if (!Namespace.empty())
- OS << "} // end namespace " << Namespace << "\n\n";
}
auto &SubRegIndices = RegBank.getSubRegIndices();
if (!SubRegIndices.empty()) {
OS << "\n// Subregister indices\n\n";
- std::string Namespace = SubRegIndices.front().getNamespace();
- if (!Namespace.empty())
- OS << "namespace " << Namespace << " {\n";
+ NamespaceEmitter SubRegNS(OS, SubRegIndices.front().getNamespace());
OS << "enum : uint16_t {\n NoSubRegister,\n";
unsigned i = 0;
for (const auto &Idx : SubRegIndices)
OS << " " << Idx.getName() << ",\t// " << ++i << "\n";
OS << " NUM_TARGET_SUBREGS\n};\n";
- if (!Namespace.empty())
- OS << "} // end namespace " << Namespace << "\n\n";
}
- OS << "// Register pressure sets enum.\n";
- if (!Namespace.empty())
- OS << "namespace " << Namespace << " {\n";
- OS << "enum RegisterPressureSets {\n";
- unsigned NumSets = RegBank.getNumRegPressureSets();
- for (unsigned i = 0; i < NumSets; ++i) {
- const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
- OS << " " << RegUnits.Name << " = " << i << ",\n";
+ {
+ OS << "// Register pressure sets enum.\n";
+ NamespaceEmitter RegNS(OS, Namespace);
+ OS << "enum RegisterPressureSets {\n";
+ unsigned NumSets = RegBank.getNumRegPressureSets();
+ for (unsigned i = 0; i < NumSets; ++i) {
+ const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
+ OS << " " << RegUnits.Name << " = " << i << ",\n";
+ }
+ OS << "};\n";
}
- OS << "};\n";
- if (!Namespace.empty())
- OS << "} // end namespace " << Namespace << '\n';
- OS << '\n';
-
- OS << "} // end namespace llvm\n\n";
}
static void printInt(raw_ostream &OS, int Val) { OS << Val; }
@@ -982,7 +965,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, raw_ostream &MainOS,
LaneMaskSeqs.layout();
SubRegIdxSeqs.layout();
- OS << "namespace llvm {\n\n";
+ NamespaceEmitter LlvmNS(OS, "llvm");
const std::string &TargetName = Target.getName().str();
@@ -1063,40 +1046,40 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, raw_ostream &MainOS,
const auto &RegisterClasses = RegBank.getRegClasses();
- // Loop over all of the register classes... emitting each one.
- OS << "namespace { // Register classes...\n";
-
SequenceToOffsetTable<std::string> RegClassStrings;
- // Emit the register enum value arrays for each RegisterClass
- for (const auto &RC : RegisterClasses) {
- ArrayRef<const Record *> Order = RC.getOrder();
-
- // Give the register class a legal C name if it's anonymous.
- const std::string &Name = RC.getName();
+ // Loop over all of the register classes... emitting each one.
+ {
+ NamespaceEmitter AnonNS(OS, "", /*Anonymous=*/true);
+ OS << "// Register classes...\n";
- RegClassStrings.add(Name);
+ // Emit the register enum value arrays for each RegisterClass
+ for (const auto &RC : RegisterClasses) {
+ ArrayRef<const Record *> Order = RC.getOrder();
- // Emit the register list now (unless it would be a zero-length array).
- if (!Order.empty()) {
- OS << " // " << Name << " Register Class...\n"
- << " const MCPhysReg " << Name << "[] = {\n ";
- for (const Record *Reg : Order) {
- OS << getQualifiedName(Reg) << ", ";
- }
- OS << "\n };\n\n";
+ // Give the register class a legal C name if it's anonymous.
+ const std::string &Name = RC.getName();
- OS << " // " << Name << " Bit set.\n"
- << " const uint8_t " << Name << "Bits[] = {\n ";
- BitVectorEmitter BVE;
- for (const Record *Reg : Order) {
- BVE.add(RegBank.getReg(Reg)->EnumValue);
+ RegClassStrings.add(Name);
+
+ // Emit the register list now (unless it would be a zero-length array).
+ if (!Order.empty()) {
+ OS << " // " << Name << " Register Class...\n"
+ << " const MCPhysReg " << Name << "[] = {\n ";
+ for (const Record *Reg : Order)
+ OS << getQualifiedName(Reg) << ", ";
+ OS << "\n };\n\n";
+
+ OS << " // " << Name << " Bit set.\n"
+ << " const uint8_t " << Name << "Bits[] = {\n ";
+ BitVectorEmitter BVE;
+ for (const Record *Reg : Order)
+ BVE.add(RegBank.getReg(Reg)->EnumValue);
+ BVE.print(OS);
+ OS << "\n };\n\n";
}
- BVE.print(OS);
- OS << "\n };\n\n";
}
- }
- OS << "} // end anonymous namespace\n\n";
+ } // emit end of anynymous namespace.
RegClassStrings.layout();
RegClassStrings.emitStringLiteralDef(
@@ -1155,8 +1138,6 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, raw_ostream &MainOS,
EmitRegMapping(OS, Regs, false);
OS << "}\n\n";
-
- OS << "} // end namespace llvm\n\n";
}
void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, raw_ostream &MainOS,
@@ -1170,7 +1151,7 @@ void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, raw_ostream &MainOS,
OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n";
- OS << "namespace llvm {\n\n";
+ NamespaceEmitter LlvmNS(OS, "llvm");
OS << "class " << TargetName << "FrameLowering;\n\n";
@@ -1228,18 +1209,15 @@ void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, raw_ostream &MainOS,
OS << "};\n\n";
if (!RegisterClasses.empty()) {
- OS << "namespace " << RegisterClasses.front().Namespace
- << " { // Register classes\n";
+ NamespaceEmitter RegClassNS(OS, RegisterClasses.front().Namespace);
+ OS << "// Register classes\n";
for (const auto &RC : RegisterClasses) {
- const std::string &Name = RC.getName();
-
// Output the extern for the instance.
- OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
+ OS << " extern const TargetRegisterClass " << RC.getName()
+ << "RegClass;\n";
}
- OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n";
}
- OS << "} // end namespace llvm\n\n";
}
//
@@ -1252,7 +1230,7 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, raw_ostream &MainOS,
emitSourceFileHeader("Target Register and Register Classes Information", OS);
- OS << "namespace llvm {\n\n";
+ NamespaceEmitter LlvmNS(OS, "llvm");
// Get access to MCRegisterClass data.
OS << "extern const MCRegisterClass " << Target.getName()
@@ -1453,8 +1431,8 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, raw_ostream &MainOS,
}
// Now emit the actual value-initialized register class instances.
- OS << "\nnamespace " << RegisterClasses.front().Namespace
- << " { // Register class instances\n";
+ NamespaceEmitter RegClassNS(OS, RegisterClasses.front().Namespace);
+ OS << "// Register class instances\n";
for (const auto &RC : RegisterClasses) {
OS << " extern const TargetRegisterClass " << RC.getName()
@@ -1481,16 +1459,15 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, raw_ostream &MainOS,
OS << RC.getName() << "GetRawAllocationOrder\n";
OS << " };\n\n";
}
-
- OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n";
}
- OS << "\nnamespace {\n";
- OS << " const TargetRegisterClass *const RegisterClasses[] = {\n";
- for (const auto &RC : RegisterClasses)
- OS << " &" << RC.getQualifiedName() << "RegClass,\n";
- OS << " };\n";
- OS << "} // end anonymous namespace\n";
+ {
+ NamespaceEmitter AnonNS(OS, "", /*Anynymous=*/true);
+ OS << " const TargetRegisterClass *const RegisterClasses[] = {\n";
+ for (const auto &RC : RegisterClasses)
+ OS << " &" << RC.getQualifiedName() << "RegClass,\n";
+ OS << " };\n";
+ }
// Emit extra information about registers.
const std::string &TargetName = Target.getName().str();
@@ -1862,8 +1839,6 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, raw_ostream &MainOS,
<< " return static_cast<const " << TargetName << "FrameLowering *>(\n"
<< " MF.getSubtarget().getFrameLowering());\n"
<< "}\n\n";
-
- OS << "} // end namespace llvm\n\n";
}
TableGenOutputFiles RegisterInfoEmitter::run(StringRef FilenamePrefix) {
``````````
</details>
https://github.com/llvm/llvm-project/pull/179017
More information about the llvm-commits
mailing list