[llvm] [AArch64][GlobalISel] Use GPR for illegal fconstants and extend < 32 bit GPR constants to 32 bits (PR #178692)

[Ryan Cowan via llvm-commits]

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@@ -2121,6 +2123,18 @@ bool AArch64InstructionSelector::preISelLower(MachineInstr &I) {
   MachineRegisterInfo &MRI = MF.getRegInfo();
 
   switch (I.getOpcode()) {
+  case TargetOpcode::G_CONSTANT: {
+    Register DefReg = I.getOperand(0).getReg();
+    const LLT DefTy = MRI.getType(DefReg);
+    if (!DefTy.isPointer())
+      return false;
+    const unsigned PtrSize = DefTy.getSizeInBits();
+    if (PtrSize != 32 && PtrSize != 64)
+      return false;
+    // Convert pointer typed constants to integers so TableGen can select.
+    MRI.setType(DefReg, LLT::scalar(PtrSize));
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HolyMolyCowMan wrote:

I've tried a fair few different approaches now for matching pointer typed patterns but I'm having no luck. As far as I can tell, `imm` doesn't support `p0` and I couldn't make use of any of the `ImmLeaf`/`IntImmLeaf`/`FPImmLeaf` or `GISelLeafPredicateCode` to make this work.

There may be a way that I'm missing or making a mistake on. If you can remember this patch or know of a way of getting around this, I'd be happy to give it a try,

https://github.com/llvm/llvm-project/pull/178692