[llvm] AMDGPU: Add more tests for v_dot2_f32_f16/bf16 (PR #179223)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 2 05:03:57 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Petar Avramovic (petar-avramovic)
<details>
<summary>Changes</summary>
Test for src modifiers, inline constants and vopd codegen.
---
Patch is 73.30 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/179223.diff
2 Files Affected:
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll (+649-122)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll (+1059-48)
``````````diff
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
index dda2e15652597..c6f0adb08f617 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
@@ -1,126 +1,653 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s --check-prefixes=GFX11
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s --check-prefixes=GFX11
-; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck %s --check-prefixes=GFX950
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck %s --check-prefixes=GFX950-ISEL
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "s_wait" --filter-out "s_nop" --filter-out "s_delay_alu" --filter-out "s_setpc_b64" --version 6
+; RUN: llc -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck %s --check-prefixes=GCN,GFX950
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s --check-prefixes=GCN,GFX11PLUS,GFX11
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s --check-prefixes=GCN,GFX11PLUS,GFX12
declare float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %c, i1 %clamp)
-define amdgpu_kernel void @test_llvm_amdgcn_fdot2_f32_bf16_clamp(
-; GFX11-LABEL: test_llvm_amdgcn_fdot2_f32_bf16_clamp:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_load_b256 s[0:7], s[4:5], 0x24
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_load_b32 s6, s[6:7], 0x0
-; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
-; GFX11-NEXT: s_load_b32 s3, s[4:5], 0x0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_dot2_f32_bf16 v0, s2, s3, v0 clamp
-; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX950-LABEL: test_llvm_amdgcn_fdot2_f32_bf16_clamp:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_load_dword s0, s[12:13], 0x0
-; GFX950-NEXT: s_load_dword s1, s[14:15], 0x0
-; GFX950-NEXT: s_load_dword s2, s[10:11], 0x0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: v_mov_b32_e32 v1, s0
-; GFX950-NEXT: v_mov_b32_e32 v2, s1
-; GFX950-NEXT: v_dot2_f32_bf16 v1, s2, v1, v2 clamp
-; GFX950-NEXT: s_nop 2
-; GFX950-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX950-NEXT: s_endpgm
-;
-; GFX950-ISEL-LABEL: test_llvm_amdgcn_fdot2_f32_bf16_clamp:
-; GFX950-ISEL: ; %bb.0: ; %entry
-; GFX950-ISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
-; GFX950-ISEL-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-ISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-ISEL-NEXT: s_load_dword s0, s[12:13], 0x0
-; GFX950-ISEL-NEXT: s_load_dword s1, s[14:15], 0x0
-; GFX950-ISEL-NEXT: s_load_dword s2, s[10:11], 0x0
-; GFX950-ISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-ISEL-NEXT: v_mov_b32_e32 v1, s0
-; GFX950-ISEL-NEXT: v_mov_b32_e32 v2, s1
-; GFX950-ISEL-NEXT: v_dot2_f32_bf16 v1, s2, v1, v2 clamp
-; GFX950-ISEL-NEXT: s_nop 2
-; GFX950-ISEL-NEXT: global_store_dword v0, v1, s[8:9]
-; GFX950-ISEL-NEXT: s_endpgm
- ptr addrspace(1) %r,
- ptr addrspace(1) %a,
- ptr addrspace(1) %b,
- ptr addrspace(1) %c) {
-entry:
- %a.val = load <2 x bfloat>, ptr addrspace(1) %a
- %b.val = load <2 x bfloat>, ptr addrspace(1) %b
- %c.val = load float, ptr addrspace(1) %c
- %r.val = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a.val, <2 x bfloat> %b.val, float %c.val, i1 1)
- store float %r.val, ptr addrspace(1) %r
- ret void
-}
-
-
-define amdgpu_kernel void @test_llvm_amdgcn_fdot2_f32_bf16_no_clamp(
-; GFX11-LABEL: test_llvm_amdgcn_fdot2_f32_bf16_no_clamp:
-; GFX11: ; %bb.0: ; %entry
-; GFX11-NEXT: s_load_b256 s[0:7], s[4:5], 0x24
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_load_b32 s6, s[6:7], 0x0
-; GFX11-NEXT: s_load_b32 s2, s[2:3], 0x0
-; GFX11-NEXT: s_load_b32 s3, s[4:5], 0x0
-; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_dot2_f32_bf16 v0, s2, s3, v0
-; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
-; GFX11-NEXT: s_endpgm
-;
-; GFX950-LABEL: test_llvm_amdgcn_fdot2_f32_bf16_no_clamp:
-; GFX950: ; %bb.0: ; %entry
-; GFX950-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
-; GFX950-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: s_load_dword s0, s[12:13], 0x0
-; GFX950-NEXT: s_load_dword s1, s[14:15], 0x0
-; GFX950-NEXT: s_load_dword s2, s[10:11], 0x0
-; GFX950-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-NEXT: v_mov_b32_e32 v1, s0
-; GFX950-NEXT: v_mov_b32_e32 v2, s1
-; GFX950-NEXT: v_dot2c_f32_bf16_e32 v2, s2, v1
-; GFX950-NEXT: s_nop 2
-; GFX950-NEXT: global_store_dword v0, v2, s[8:9]
-; GFX950-NEXT: s_endpgm
-;
-; GFX950-ISEL-LABEL: test_llvm_amdgcn_fdot2_f32_bf16_no_clamp:
-; GFX950-ISEL: ; %bb.0: ; %entry
-; GFX950-ISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
-; GFX950-ISEL-NEXT: v_mov_b32_e32 v0, 0
-; GFX950-ISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-ISEL-NEXT: s_load_dword s0, s[12:13], 0x0
-; GFX950-ISEL-NEXT: s_load_dword s1, s[14:15], 0x0
-; GFX950-ISEL-NEXT: s_load_dword s2, s[10:11], 0x0
-; GFX950-ISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX950-ISEL-NEXT: v_mov_b32_e32 v1, s0
-; GFX950-ISEL-NEXT: v_mov_b32_e32 v2, s1
-; GFX950-ISEL-NEXT: v_dot2c_f32_bf16_e32 v2, s2, v1
-; GFX950-ISEL-NEXT: s_nop 2
-; GFX950-ISEL-NEXT: global_store_dword v0, v2, s[8:9]
-; GFX950-ISEL-NEXT: s_endpgm
- ptr addrspace(1) %r,
- ptr addrspace(1) %a,
- ptr addrspace(1) %b,
- ptr addrspace(1) %c) {
-entry:
- %a.val = load <2 x bfloat>, ptr addrspace(1) %a
- %b.val = load <2 x bfloat>, ptr addrspace(1) %b
- %c.val = load float, ptr addrspace(1) %c
- %r.val = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a.val, <2 x bfloat> %b.val, float %c.val, i1 0)
- store float %r.val, ptr addrspace(1) %r
- ret void
+define float @v_fdot2_f32_bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %c) {
+; GFX950-LABEL: v_fdot2_f32_bf16:
+; GFX950: ; %bb.0:
+; GFX950: v_dot2c_f32_bf16_e32 v2, v0, v1
+; GFX950: v_mov_b32_e32 v0, v2
+;
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, v2
+ %r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %c, i1 false)
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_neg_a(<2 x bfloat> %a, <2 x bfloat> %b, float %c) {
+; GFX950-LABEL: v_fdot2_f32_bf16_neg_a:
+; GFX950: ; %bb.0:
+; GFX950: v_xor_b32_e32 v0, 0x80008000, v0
+; GFX950: v_dot2c_f32_bf16_e32 v2, v0, v1
+; GFX950: v_mov_b32_e32 v0, v2
+;
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_neg_a:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
+ %neg.a = fneg <2 x bfloat> %a
+ %r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %neg.a, <2 x bfloat> %b, float %c, i1 false)
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_neg_b(<2 x bfloat> %a, <2 x bfloat> %b, float %c) {
+; GFX950-LABEL: v_fdot2_f32_bf16_neg_b:
+; GFX950: ; %bb.0:
+; GFX950: v_xor_b32_e32 v1, 0x80008000, v1
+; GFX950: v_dot2c_f32_bf16_e32 v2, v0, v1
+; GFX950: v_mov_b32_e32 v0, v2
+;
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_neg_b:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
+ %neg.b = fneg <2 x bfloat> %b
+ %r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %neg.b, float %c, i1 false)
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_neg_c(<2 x bfloat> %a, <2 x bfloat> %b, float %c) {
+; GFX950-LABEL: v_fdot2_f32_bf16_neg_c:
+; GFX950: ; %bb.0:
+; GFX950: v_xor_b32_e32 v2, 0x80000000, v2
+; GFX950: v_dot2c_f32_bf16_e32 v2, v0, v1
+; GFX950: v_mov_b32_e32 v0, v2
+;
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_neg_c:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, v2 neg_lo:[0,0,1] neg_hi:[0,0,1]
+ %neg.c = fneg float %c
+ %r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %neg.c, i1 false)
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_abs_c(<2 x bfloat> %a, <2 x bfloat> %b, float %c) {
+; GFX950-LABEL: v_fdot2_f32_bf16_abs_c:
+; GFX950: ; %bb.0:
+; GFX950: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX950: v_dot2c_f32_bf16_e32 v2, v0, v1
+; GFX950: v_mov_b32_e32 v0, v2
+;
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_abs_c:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_and_b32_e32 v2, 0x7fffffff, v2
+; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, v2
+ %abs.c = call float @llvm.fabs.f32(float %c)
+ %r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %abs.c, i1 false)
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_opsel_lo_a(<2 x bfloat> %a, <2 x bfloat> %b, float %c) {
+; GFX950-LABEL: v_fdot2_f32_bf16_opsel_lo_a:
+; GFX950: ; %bb.0:
+; GFX950: s_mov_b32 s0, 0x7060302
+; GFX950: v_perm_b32 v0, v0, v0, s0
+; GFX950: v_dot2c_f32_bf16_e32 v2, v0, v1
+; GFX950: v_mov_b32_e32 v0, v2
+;
+; GFX11-LABEL: v_fdot2_f32_bf16_opsel_lo_a:
+; GFX11: ; %bb.0:
+; GFX11: v_mov_b16_e32 v0.l, v0.h
+; GFX11: v_dot2_f32_bf16 v0, v0, v1, v2
+;
+; GFX12-LABEL: v_fdot2_f32_bf16_opsel_lo_a:
+; GFX12: ; %bb.0:
+; GFX12: v_perm_b32 v0, v0, v0, 0x7060302
+; GFX12: v_dot2_f32_bf16 v0, v0, v1, v2
+ %shuf = shufflevector <2 x bfloat> %a, <2 x bfloat> poison, <2 x i32> <i32 1, i32 1>
+ %r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %shuf, <2 x bfloat> %b, float %c, i1 false)
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_opsel_hi_a(<2 x bfloat> %a, <2 x bfloat> %b, float %c) {
+; GFX950-LABEL: v_fdot2_f32_bf16_opsel_hi_a:
+; GFX950: ; %bb.0:
+; GFX950: s_mov_b32 s0, 0x5040100
+; GFX950: v_perm_b32 v0, v0, v0, s0
+; GFX950: v_dot2c_f32_bf16_e32 v2, v0, v1
+; GFX950: v_mov_b32_e32 v0, v2
+;
+; GFX11-LABEL: v_fdot2_f32_bf16_opsel_hi_a:
+; GFX11: ; %bb.0:
+; GFX11: v_mov_b16_e32 v0.h, v0.l
+; GFX11: v_dot2_f32_bf16 v0, v0, v1, v2
+;
+; GFX12-LABEL: v_fdot2_f32_bf16_opsel_hi_a:
+; GFX12: ; %bb.0:
+; GFX12: v_perm_b32 v0, v0, v0, 0x5040100
+; GFX12: v_dot2_f32_bf16 v0, v0, v1, v2
+ %shuf = shufflevector <2 x bfloat> %a, <2 x bfloat> poison, <2 x i32> <i32 0, i32 0>
+ %r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %shuf, <2 x bfloat> %b, float %c, i1 false)
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_opsel_lo_b(<2 x bfloat> %a, <2 x bfloat> %b, float %c) {
+; GFX950-LABEL: v_fdot2_f32_bf16_opsel_lo_b:
+; GFX950: ; %bb.0:
+; GFX950: s_mov_b32 s0, 0x7060302
+; GFX950: v_perm_b32 v1, v1, v1, s0
+; GFX950: v_dot2c_f32_bf16_e32 v2, v0, v1
+; GFX950: v_mov_b32_e32 v0, v2
+;
+; GFX11-LABEL: v_fdot2_f32_bf16_opsel_lo_b:
+; GFX11: ; %bb.0:
+; GFX11: v_mov_b16_e32 v1.l, v1.h
+; GFX11: v_dot2_f32_bf16 v0, v0, v1, v2
+;
+; GFX12-LABEL: v_fdot2_f32_bf16_opsel_lo_b:
+; GFX12: ; %bb.0:
+; GFX12: v_perm_b32 v1, v1, v1, 0x7060302
+; GFX12: v_dot2_f32_bf16 v0, v0, v1, v2
+ %shuf = shufflevector <2 x bfloat> %b, <2 x bfloat> poison, <2 x i32> <i32 1, i32 1>
+ %r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %shuf, float %c, i1 false)
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_opsel_hi_b(<2 x bfloat> %a, <2 x bfloat> %b, float %c) {
+; GFX950-LABEL: v_fdot2_f32_bf16_opsel_hi_b:
+; GFX950: ; %bb.0:
+; GFX950: s_mov_b32 s0, 0x5040100
+; GFX950: v_perm_b32 v1, v1, v1, s0
+; GFX950: v_dot2c_f32_bf16_e32 v2, v0, v1
+; GFX950: v_mov_b32_e32 v0, v2
+;
+; GFX11-LABEL: v_fdot2_f32_bf16_opsel_hi_b:
+; GFX11: ; %bb.0:
+; GFX11: v_mov_b16_e32 v1.h, v1.l
+; GFX11: v_dot2_f32_bf16 v0, v0, v1, v2
+;
+; GFX12-LABEL: v_fdot2_f32_bf16_opsel_hi_b:
+; GFX12: ; %bb.0:
+; GFX12: v_perm_b32 v1, v1, v1, 0x5040100
+; GFX12: v_dot2_f32_bf16 v0, v0, v1, v2
+ %shuf = shufflevector <2 x bfloat> %b, <2 x bfloat> poison, <2 x i32> <i32 0, i32 0>
+ %r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %shuf, float %c, i1 false)
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_inline_literal_a(<2 x bfloat> %b, float %c) {
+; GFX950-LABEL: v_fdot2_f32_bf16_inline_literal_a:
+; GFX950: ; %bb.0:
+; GFX950: v_dot2c_f32_bf16_e32 v1, 0x3f003f00, v0
+; GFX950: v_mov_b32_e32 v0, v1
+;
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_inline_literal_a:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_dot2_f32_bf16 v0, 0x3f003f00, v0, v1
+ %ret = tail call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> <bfloat 0.5, bfloat 0.5>, <2 x bfloat> %b, float %c, i1 false)
+ ret float %ret
+}
+
+define float @v_fdot2_f32_bf16_inline_literal_b(<2 x bfloat> %a, float %c) {
+; GFX950-LABEL: v_fdot2_f32_bf16_inline_literal_b:
+; GFX950: ; %bb.0:
+; GFX950: v_dot2c_f32_bf16_e32 v1, 0x40004000, v0
+; GFX950: v_mov_b32_e32 v0, v1
+;
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_inline_literal_b:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_dot2_f32_bf16 v0, v0, 0x40004000, v1
+ %ret = tail call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> <bfloat 2.0, bfloat 2.0>, float %c, i1 false)
+ ret float %ret
+}
+
+define float @v_fdot2_f32_bf16_inline_literal_c(<2 x bfloat> %a, <2 x bfloat> %b) {
+; GFX950-LABEL: v_fdot2_f32_bf16_inline_literal_c:
+; GFX950: ; %bb.0:
+; GFX950: v_mov_b32_e32 v2, 2.0
+; GFX950: v_dot2c_f32_bf16_e32 v2, v0, v1
+; GFX950: v_mov_b32_e32 v0, v2
+;
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_inline_literal_c:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_dot2_f32_bf16 v0, v0, v1, 2.0
+ %ret = tail call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float 2.0, i1 false)
+ ret float %ret
+}
+
+define float @v_fdot2_f32_bf16_clamp(<2 x bfloat> %a, <2 x bfloat> %b, float %c) {
+; GCN-LABEL: v_fdot2_f32_bf16_clamp:
+; GCN: ; %bb.0:
+; GCN: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
+ %r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %c, i1 true)
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_neg_a_clamp(<2 x bfloat> %a, <2 x bfloat> %b, float %c) {
+; GCN-LABEL: v_fdot2_f32_bf16_neg_a_clamp:
+; GCN: ; %bb.0:
+; GCN: v_dot2_f32_bf16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0] clamp
+ %neg.a = fneg <2 x bfloat> %a
+ %r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %neg.a, <2 x bfloat> %b, float %c, i1 true)
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_neg_b_clamp(<2 x bfloat> %a, <2 x bfloat> %b, float %c) {
+; GCN-LABEL: v_fdot2_f32_bf16_neg_b_clamp:
+; GCN: ; %bb.0:
+; GCN: v_dot2_f32_bf16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0] clamp
+ %neg.b = fneg <2 x bfloat> %b
+ %r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %neg.b, float %c, i1 true)
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_neg_c_clamp(<2 x bfloat> %a, <2 x bfloat> %b, float %c) {
+; GCN-LABEL: v_fdot2_f32_bf16_neg_c_clamp:
+; GCN: ; %bb.0:
+; GCN: v_dot2_f32_bf16 v0, v0, v1, v2 neg_lo:[0,0,1] neg_hi:[0,0,1] clamp
+ %neg.c = fneg float %c
+ %r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %neg.c, i1 true)
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_abs_c_clamp(<2 x bfloat> %a, <2 x bfloat> %b, float %c) {
+; GCN-LABEL: v_fdot2_f32_bf16_abs_c_clamp:
+; GCN: ; %bb.0:
+; GCN: v_and_b32_e32 v2, 0x7fffffff, v2
+; GCN: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
+ %abs.c = call float @llvm.fabs.f32(float %c)
+ %r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b, float %abs.c, i1 true)
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_opsel_lo_a_clamp(<2 x bfloat> %a, <2 x bfloat> %b, float %c) {
+; GFX950-LABEL: v_fdot2_f32_bf16_opsel_lo_a_clamp:
+; GFX950: ; %bb.0:
+; GFX950: s_mov_b32 s0, 0x7060302
+; GFX950: v_perm_b32 v0, v0, v0, s0
+; GFX950: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
+;
+; GFX11-LABEL: v_fdot2_f32_bf16_opsel_lo_a_clamp:
+; GFX11: ; %bb.0:
+; GFX11: v_mov_b16_e32 v0.l, v0.h
+; GFX11: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
+;
+; GFX12-LABEL: v_fdot2_f32_bf16_opsel_lo_a_clamp:
+; GFX12: ; %bb.0:
+; GFX12: v_perm_b32 v0, v0, v0, 0x7060302
+; GFX12: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
+ %shuf = shufflevector <2 x bfloat> %a, <2 x bfloat> poison, <2 x i32> <i32 1, i32 1>
+ %r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %shuf, <2 x bfloat> %b, float %c, i1 true)
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_opsel_hi_a_clamp(<2 x bfloat> %a, <2 x bfloat> %b, float %c) {
+; GFX950-LABEL: v_fdot2_f32_bf16_opsel_hi_a_clamp:
+; GFX950: ; %bb.0:
+; GFX950: s_mov_b32 s0, 0x5040100
+; GFX950: v_perm_b32 v0, v0, v0, s0
+; GFX950: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
+;
+; GFX11-LABEL: v_fdot2_f32_bf16_opsel_hi_a_clamp:
+; GFX11: ; %bb.0:
+; GFX11: v_mov_b16_e32 v0.h, v0.l
+; GFX11: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
+;
+; GFX12-LABEL: v_fdot2_f32_bf16_opsel_hi_a_clamp:
+; GFX12: ; %bb.0:
+; GFX12: v_perm_b32 v0, v0, v0, 0x5040100
+; GFX12: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
+ %shuf = shufflevector <2 x bfloat> %a, <2 x bfloat> poison, <2 x i32> <i32 0, i32 0>
+ %r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %shuf, <2 x bfloat> %b, float %c, i1 true)
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_opsel_lo_b_clamp(<2 x bfloat> %a, <2 x bfloat> %b, float %c) {
+; GFX950-LABEL: v_fdot2_f32_bf16_opsel_lo_b_clamp:
+; GFX950: ; %bb.0:
+; GFX950: s_mov_b32 s0, 0x7060302
+; GFX950: v_perm_b32 v1, v1, v1, s0
+; GFX950: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
+;
+; GFX11-LABEL: v_fdot2_f32_bf16_opsel_lo_b_clamp:
+; GFX11: ; %bb.0:
+; GFX11: v_mov_b16_e32 v1.l, v1.h
+; GFX11: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
+;
+; GFX12-LABEL: v_fdot2_f32_bf16_opsel_lo_b_clamp:
+; GFX12: ; %bb.0:
+; GFX12: v_perm_b32 v1, v1, v1, 0x7060302
+; GFX12: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
+ %shuf = shufflevector <2 x bfloat> %b, <2 x bfloat> poison, <2 x i32> <i32 1, i32 1>
+ %r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %shuf, float %c, i1 true)
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_opsel_hi_b_clamp(<2 x bfloat> %a, <2 x bfloat> %b, float %c) {
+; GFX950-LABEL: v_fdot2_f32_bf16_opsel_hi_b_clamp:
+; GFX950: ; %bb.0:
+; GFX950: s_mov_b32 s0, 0x5040100
+; GFX950: v_perm_b32 v1, v1, v1, s0
+; GFX950: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
+;
+; GFX11-LABEL: v_fdot2_f32_bf16_opsel_hi_b_clamp:
+; GFX11: ; %bb.0:
+; GFX11: v_mov_b16_e32 v1.h, v1.l
+; GFX11: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
+;
+; GFX12-LABEL: v_fdot2_f32_bf16_opsel_hi_b_clamp:
+; GFX12: ; %bb.0:
+; GFX12: v_perm_b32 v1, v1, v1, 0x5040100
+; GFX12: v_dot2_f32_bf16 v0, v0, v1, v2 clamp
+ %shuf = shufflevector <2 x bfloat> %b, <2 x bfloat> poison, <2 x i32> <i32 0, i32 0>
+ %r = call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %shuf, float %c, i1 true)
+ ret float %r
+}
+
+define float @v_fdot2_f32_bf16_inline_literal_a_clamp(<2 x bfloat> %b, float %c) {
+; GFX950-LABEL: v_fdot2_f32_bf16_inline_literal_a_clamp:
+; GFX950: ; %bb.0:
+; GFX950: s_mov_b32 s0, 0x40004000
+; GFX950: v_dot2_f32_bf16 v0, s0, v0, v1 clamp
+;
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_inline_literal_a_clamp:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_dot2_f32_bf16 v0, 0x40004000, v0, v1 clamp
+ %ret = tail call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> <bfloat 2.0, bfloat 2.0>, <2 x bfloat> %b, float %c, i1 true)
+ ret float %ret
+}
+
+define float @v_fdot2_f32_bf16_inline_literal_b_clamp(<2 x bfloat> %a, float %c) {
+; GFX950-LABEL: v_fdot2_f32_bf16_inline_literal_b_clamp:
+; GFX950: ; %bb.0:
+; GFX950: s_mov_b32 s0, 0x40004000
+; GFX950: v_dot2_f32_bf16 v0, v0, s0, v1 clamp
+;
+; GFX11PLUS-LABEL: v_fdot2_f32_bf16_inline_literal_b_clamp:
+; GFX11PLUS: ; %bb.0:
+; GFX11PLUS: v_dot2_f32_bf16 v0, v0, 0x40004000, v1 clamp
+ %ret = tail call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> <bfloat 2.0, bfloat 2.0>, float %c, i1 true)
+ ret float %r...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/179223
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