[llvm] [AArch64] Fix cttz.elts codegen for fixed-length vectors (PR #178902)

[David Sherwood via llvm-commits]

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@@ -6903,16 +6903,21 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     EVT VT = CttzOp.getValueType();
     assert(VT.getVectorElementType() == MVT::i1 && "Expected MVT::i1");
 
+    // Default to all for scalable vectors
+    unsigned PgPattern = AArch64SVEPredPattern::all;
     if (VT.isFixedLengthVector()) {
       // We can use SVE instructions to lower this intrinsic by first creating
       // an SVE predicate register mask from the fixed-width vector.
       EVT NewVT = getTypeToTransformTo(*DAG.getContext(), VT);
       SDValue Mask = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, CttzOp);
       CttzOp = convertFixedMaskToScalableVector(Mask, DAG);
+      // Override with a VLx.
+      PgPattern = *getSVEPredPatternFromNumElements(VT.getVectorNumElements());
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david-arm wrote:

I guess if the types are guaranteed to be legal at this point it shouldn't crash, and even if you're using fixed-width SVE via -msve-vector-bits=128,256,512 or 1024 it should work. However, in this case I think it's worth adding some tests for <9 x i1> and larger vectors such as <32 x i1> in combination with `-aarch64-sve-vector-bits-min=256`.

https://github.com/llvm/llvm-project/pull/178902