[llvm] Handle IMPLICIT_DEF in TripleMBB for WindowScheduler (PR #179190)

[Chandana Mudda via llvm-commits]

https://github.com/chandmudda created https://github.com/llvm/llvm-project/pull/179190

Previously, IMPLICIT_DEF instructions were not copied into the triple-MBB region used by the WindowScheduler. This left the machine-level liveness inconsistent with the triplicated code and could trigger a LiveIntervals assertion:
  LiveIntervals::HMEditor::updateRange: Assertion `LR.verify()' failed.
Copy IMPLICIT_DEF into the triple region so that the triplicated block has a consistent set of defs and LiveIntervals can update ranges correctly.

>From e87d1f810c06c1700cbb084e908d4dfe2a61a9cf Mon Sep 17 00:00:00 2001
From: Chandana Mudda <quic_csinderi at quicinc.com>
Date: Sun, 1 Feb 2026 21:48:52 -0800
Subject: [PATCH] Handle IMPLICIT_DEF in TripleMBB for WindowScheduler

Previously, IMPLICIT_DEF instructions were not copied into the
triple-MBB region used by the WindowScheduler. This left the
machine-level liveness inconsistent with the triplicated code and
could trigger a LiveIntervals assertion:
  LiveIntervals::HMEditor::updateRange: Assertion `LR.verify()' failed.
Copy IMPLICIT_DEF into the triple region so that the triplicated
block has a consistent set of defs and LiveIntervals can update
ranges correctly.
---
 llvm/lib/CodeGen/WindowScheduler.cpp          |  8 +--
 .../Hexagon/win-sched-implicit-def.mir        | 54 +++++++++++++++++++
 2 files changed, 58 insertions(+), 4 deletions(-)
 create mode 100644 llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir

diff --git a/llvm/lib/CodeGen/WindowScheduler.cpp b/llvm/lib/CodeGen/WindowScheduler.cpp
index 2492dfc3ca553..0d5794542cd36 100644
--- a/llvm/lib/CodeGen/WindowScheduler.cpp
+++ b/llvm/lib/CodeGen/WindowScheduler.cpp
@@ -211,7 +211,7 @@ bool WindowScheduler::initialize() {
   };
   auto PLI = TII->analyzeLoopForPipelining(MBB);
   for (auto &MI : *MBB) {
-    if (MI.isMetaInstruction() || MI.isTerminator())
+    if ((MI.isMetaInstruction() && !MI.isImplicitDef()) || MI.isTerminator())
       continue;
     if (MI.isPHI()) {
       if (IsLoopCarried(MI)) {
@@ -297,7 +297,7 @@ void WindowScheduler::generateTripleMBB() {
   // DefPairs hold the old and new define register pairs.
   DenseMap<Register, Register> DefPairs;
   for (auto *MI : OriMIs) {
-    if (MI->isMetaInstruction() || MI->isTerminator())
+    if ((MI->isMetaInstruction() && !MI->isImplicitDef()) || MI->isTerminator())
       continue;
     if (MI->isPHI())
       if (Register AntiReg = getAntiRegister(MI))
@@ -312,7 +312,7 @@ void WindowScheduler::generateTripleMBB() {
   // are updated accordingly.
   for (size_t Cnt = 1; Cnt < DuplicateNum; ++Cnt) {
     for (auto *MI : OriMIs) {
-      if (MI->isPHI() || MI->isMetaInstruction() ||
+      if (MI->isPHI() || (MI->isMetaInstruction() && !MI->isImplicitDef()) ||
           (MI->isTerminator() && Cnt < DuplicateNum - 1))
         continue;
       auto *NewMI = MF->CloneMachineInstr(MI);
@@ -687,7 +687,7 @@ unsigned WindowScheduler::getOriStage(MachineInstr *OriMI, unsigned Offset) {
   // while the rest are set to 1.
   unsigned Id = 0;
   for (auto *MI : OriMIs) {
-    if (MI->isMetaInstruction())
+    if (MI->isMetaInstruction() && !MI->isImplicitDef())
       continue;
     if (MI == OriMI)
       break;
diff --git a/llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir b/llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir
new file mode 100644
index 0000000000000..05c86535ee325
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/win-sched-implicit-def.mir
@@ -0,0 +1,54 @@
+# RUN: llc -mtriple=hexagon -run-pass pipeliner %s -o - | FileCheck %s
+# REQUIRES: asserts
+# Ensure WindowScheduler copies IMPLICIT_DEF into the triple-MBB region
+# so LiveIntervals no longer hits LR.verify()
+# CHECK: foo
+
+--- |
+  define void @foo() {
+    ret void
+  }
+...
+
+---
+name:            foo
+tracksRegLiveness: true
+
+body:             |
+  bb.0:
+    successors: %bb.1(0x60000000), %bb.2(0x20000000)
+    liveins: $r0, $r1, $r2
+
+    %bb0_e75bf3f0bba6b3ae__1:hvxqr = IMPLICIT_DEF
+    %bb0_e75bf3f0bba6b3ae__2:intregslow8 = IMPLICIT_DEF
+    %bb0_e75bf3f0bba6b3ae__3:predregs = IMPLICIT_DEF
+    %bb0_e75bf3f0bba6b3ae__4:intregs = IMPLICIT_DEF
+    J2_jumpf undef %bb0_e75bf3f0bba6b3ae__3, %bb.2, implicit-def $pc
+    J2_jump %bb.1, implicit-def $pc
+
+  bb.1:
+    successors: %bb.4(0x55555555), %bb.2(0x2aaaaaab)
+
+    J2_jumpt undef %bb0_e75bf3f0bba6b3ae__3, %bb.4, implicit-def $pc
+    J2_jump %bb.2, implicit-def $pc
+
+  bb.2:
+    successors: %bb.3(0x80000000)
+
+    J2_loop0r %bb.3, undef %bb0_e75bf3f0bba6b3ae__4, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
+    J2_jump %bb.3, implicit-def $pc
+
+  bb.3 (machine-block-address-taken):
+    successors: %bb.4(0x04000000), %bb.3(0x7c000000)
+
+    %bb3_e75bf3f0bba6b3ae__1:hvxwr = IMPLICIT_DEF
+    %bb3_d787b15822067ced__1:hvxvr = V6_vL32Ub_ai undef %bb0_e75bf3f0bba6b3ae__4, 0 :: (load (s1024), align 8)
+    %bb3_734170929685adbc__1:hvxvr = V6_vlalignb undef %bb3_e75bf3f0bba6b3ae__1.vsub_lo, undef %bb3_d787b15822067ced__1, undef %bb0_e75bf3f0bba6b3ae__2
+    %bb3_ba5a00bd10a880fa__1:hvxvr = V6_vlalignb %bb3_e75bf3f0bba6b3ae__1.vsub_lo, undef %bb3_e75bf3f0bba6b3ae__1.vsub_hi, undef %bb0_e75bf3f0bba6b3ae__2
+    V6_vS32b_qpred_ai undef %bb0_e75bf3f0bba6b3ae__1, undef %bb0_e75bf3f0bba6b3ae__4, 0, %bb3_ba5a00bd10a880fa__1 :: (store (s1024))
+    ENDLOOP0 %bb.3, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
+    J2_jump %bb.4, implicit-def $pc
+
+  bb.4:
+    PS_jmpret $r31, implicit-def $pc
+...