[llvm] [RISCV] Remove RISCVVMV0Elimination pass (PR #175147)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

Status updates:
1. We can pass `llvm-testsuite` after this PR so the correctness is not a noticeable concern now.
2. For the in-tree unit tests, we saw some improvements of removing `vmv`s but somehow there are several cases where we generate more spills/reloads. Overall the spilling issue is more significant than the gain.
3. We measured the dynamic instruction count of SPEC CPU 2017 and we didn't see big differences.

https://github.com/llvm/llvm-project/pull/175147