[llvm] [RISCV] Remove RISCVVMV0Elimination pass (PR #175147)
Pengcheng Wang via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 21 04:05:39 PST 2026
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/175147
>From e69ebbb4e3aa7a4b83ada5fdc9fc3e3b068de2e2 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Wed, 7 Jan 2026 18:08:45 +0800
Subject: [PATCH 1/5] [RISCV] Remove RISCVVMV0Elimination pass
[RISCV] Add an artificial between copies of v0 and vmv0 users
This avoids the overlap of v0 and fixes some correctness issues.
---
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 7 +-
llvm/test/CodeGen/RISCV/O0-pipeline.ll | 1 -
llvm/test/CodeGen/RISCV/O3-pipeline.ll | 1 -
.../CodeGen/RISCV/combine-storetomstore.ll | 109 +-
llvm/test/CodeGen/RISCV/rvv/abs-vp.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll | 1544 +++--
llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll | 980 +--
llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll | 388 +-
.../RISCV/rvv/combine-reduce-add-to-vcpop.ll | 438 +-
.../RISCV/rvv/constant-folding-crash.ll | 51 +-
llvm/test/CodeGen/RISCV/rvv/copyprop.mir | 4 +-
llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll | 52 +-
llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll | 339 +-
llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll | 40 +-
llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll | 434 +-
.../CodeGen/RISCV/rvv/double-round-conv.ll | 32 +-
llvm/test/CodeGen/RISCV/rvv/expandload.ll | 410 +-
llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll | 26 +-
.../RISCV/rvv/fceil-constrained-sdnode.ll | 58 +-
llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll | 102 +-
.../RISCV/rvv/ffloor-constrained-sdnode.ll | 58 +-
llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll | 102 +-
.../rvv/fixed-vector-i8-index-cornercase.ll | 35 +-
.../RISCV/rvv/fixed-vectors-bitreverse-vp.ll | 1454 +++--
.../RISCV/rvv/fixed-vectors-bswap-vp.ll | 870 ++-
.../rvv/fixed-vectors-buildvec-of-binop.ll | 2 +-
.../RISCV/rvv/fixed-vectors-ceil-vp.ll | 422 +-
.../RISCV/rvv/fixed-vectors-ctlz-vp.ll | 1456 +++--
.../RISCV/rvv/fixed-vectors-ctpop-vp.ll | 341 +-
.../RISCV/rvv/fixed-vectors-cttz-vp.ll | 1054 ++--
.../CodeGen/RISCV/rvv/fixed-vectors-cttz.ll | 8 +-
.../rvv/fixed-vectors-extload-truncstore.ll | 4 +-
.../RISCV/rvv/fixed-vectors-extract-i1.ll | 112 +-
.../rvv/fixed-vectors-extract-subvector.ll | 61 +-
.../fixed-vectors-fceil-constrained-sdnode.ll | 56 +-
...fixed-vectors-ffloor-constrained-sdnode.ll | 56 +-
.../RISCV/rvv/fixed-vectors-floor-vp.ll | 422 +-
.../RISCV/rvv/fixed-vectors-fmaximum-vp.ll | 435 +-
.../RISCV/rvv/fixed-vectors-fmaximum.ll | 124 +-
.../RISCV/rvv/fixed-vectors-fminimum-vp.ll | 435 +-
.../RISCV/rvv/fixed-vectors-fminimum.ll | 124 +-
...d-vectors-fnearbyint-constrained-sdnode.ll | 12 +-
.../RISCV/rvv/fixed-vectors-fp-buildvec.ll | 7 +-
.../RISCV/rvv/fixed-vectors-fp-setcc.ll | 56 +-
.../CodeGen/RISCV/rvv/fixed-vectors-fp.ll | 112 +-
.../RISCV/rvv/fixed-vectors-fpext-vp.ll | 11 +-
...fixed-vectors-fround-constrained-sdnode.ll | 56 +-
.../CodeGen/RISCV/rvv/fixed-vectors-fround.ll | 86 +-
...d-vectors-froundeven-constrained-sdnode.ll | 56 +-
.../RISCV/rvv/fixed-vectors-froundeven.ll | 86 +-
.../RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll | 310 +-
...fixed-vectors-ftrunc-constrained-sdnode.ll | 28 +-
.../rvv/fixed-vectors-insert-subvector.ll | 54 +-
.../RISCV/rvv/fixed-vectors-int-buildvec.ll | 174 +-
.../CodeGen/RISCV/rvv/fixed-vectors-int.ll | 115 +-
...fixed-vectors-interleaved-access-zve32x.ll | 29 +-
.../rvv/fixed-vectors-interleaved-access.ll | 1153 ++--
.../RISCV/rvv/fixed-vectors-mask-buildvec.ll | 24 +-
.../RISCV/rvv/fixed-vectors-mask-splat.ll | 16 +-
.../RISCV/rvv/fixed-vectors-masked-gather.ll | 161 +-
.../RISCV/rvv/fixed-vectors-masked-load-fp.ll | 8 +-
.../rvv/fixed-vectors-masked-load-int.ll | 6 +-
.../RISCV/rvv/fixed-vectors-masked-scatter.ll | 6 +-
.../rvv/fixed-vectors-masked-store-fp.ll | 8 +-
.../rvv/fixed-vectors-masked-store-int.ll | 14 +-
.../RISCV/rvv/fixed-vectors-nearbyint-vp.ll | 134 +-
.../rvv/fixed-vectors-reduction-fp-vp.ll | 24 +-
.../RISCV/rvv/fixed-vectors-reduction-fp.ll | 472 +-
.../rvv/fixed-vectors-reduction-int-vp.ll | 12 +-
.../rvv/fixed-vectors-reduction-mask-vp.ll | 9 +-
.../RISCV/rvv/fixed-vectors-rint-vp.ll | 102 +-
.../RISCV/rvv/fixed-vectors-round-vp.ll | 422 +-
.../RISCV/rvv/fixed-vectors-roundeven-vp.ll | 422 +-
.../RISCV/rvv/fixed-vectors-roundtozero-vp.ll | 422 +-
.../RISCV/rvv/fixed-vectors-select-addsub.ll | 2 +-
.../RISCV/rvv/fixed-vectors-setcc-fp-vp.ll | 40 +-
.../RISCV/rvv/fixed-vectors-setcc-int-vp.ll | 64 +-
.../RISCV/rvv/fixed-vectors-sext-vp.ll | 11 +-
.../fixed-vectors-shuffle-changes-length.ll | 10 +-
.../rvv/fixed-vectors-shuffle-deinterleave.ll | 28 +-
.../fixed-vectors-shuffle-deinterleave2.ll | 320 +-
.../rvv/fixed-vectors-shuffle-exact-vlen.ll | 39 +-
.../fixed-vectors-shuffle-fp-interleave.ll | 8 +-
.../RISCV/rvv/fixed-vectors-shuffle-fp.ll | 32 +-
.../fixed-vectors-shuffle-int-interleave.ll | 75 +-
.../RISCV/rvv/fixed-vectors-shuffle-int.ll | 109 +-
.../RISCV/rvv/fixed-vectors-shuffle-rotate.ll | 50 +-
.../fixed-vectors-strided-load-store-asm.ll | 2 +-
.../RISCV/rvv/fixed-vectors-strided-vpload.ll | 51 +-
.../rvv/fixed-vectors-strided-vpstore.ll | 2 +-
.../RISCV/rvv/fixed-vectors-trunc-vp.ll | 466 +-
.../CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll | 16 +-
.../RISCV/rvv/fixed-vectors-vadd-vp.ll | 8 +-
.../RISCV/rvv/fixed-vectors-vcopysign-vp.ll | 20 +-
.../RISCV/rvv/fixed-vectors-vdiv-vp.ll | 2 +-
.../fixed-vectors-vfcmp-constrained-sdnode.ll | 360 +-
.../RISCV/rvv/fixed-vectors-vfma-vp.ll | 69 +-
.../RISCV/rvv/fixed-vectors-vfmax-vp.ll | 20 +-
.../RISCV/rvv/fixed-vectors-vfmin-vp.ll | 20 +-
.../RISCV/rvv/fixed-vectors-vfmuladd-vp.ll | 69 +-
.../RISCV/rvv/fixed-vectors-vmax-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-vmaxu-vp.ll | 8 +-
.../RISCV/rvv/fixed-vectors-vmin-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-vminu-vp.ll | 8 +-
.../RISCV/rvv/fixed-vectors-vpgather.ll | 84 +-
.../CodeGen/RISCV/rvv/fixed-vectors-vpload.ll | 28 +-
.../RISCV/rvv/fixed-vectors-vpmerge.ll | 34 +-
.../RISCV/rvv/fixed-vectors-vpscatter.ll | 151 +-
.../RISCV/rvv/fixed-vectors-vpstore.ll | 6 +-
.../RISCV/rvv/fixed-vectors-vrem-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-vsadd-vp.ll | 8 +-
.../RISCV/rvv/fixed-vectors-vsaddu-vp.ll | 8 +-
.../RISCV/rvv/fixed-vectors-vselect-vp.ll | 40 +-
.../RISCV/rvv/fixed-vectors-vselect.ll | 48 +-
.../RISCV/rvv/fixed-vectors-vsra-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-vssub-vp.ll | 8 +-
.../RISCV/rvv/fixed-vectors-vssubu-vp.ll | 8 +-
.../RISCV/rvv/fixed-vectors-vwadd-mask.ll | 21 +-
.../RISCV/rvv/fixed-vectors-vwsub-mask.ll | 14 +-
.../RISCV/rvv/fixed-vectors-zext-vp.ll | 11 +-
.../CodeGen/RISCV/rvv/float-round-conv.ll | 16 +-
llvm/test/CodeGen/RISCV/rvv/floor-vp.ll | 428 +-
.../test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll | 140 +-
llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll | 1115 ++--
.../test/CodeGen/RISCV/rvv/fminimum-sdnode.ll | 140 +-
llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll | 1115 ++--
.../rvv/fnearbyint-constrained-sdnode.ll | 16 +-
.../CodeGen/RISCV/rvv/fnearbyint-sdnode.ll | 8 +-
.../RISCV/rvv/fround-constrained-sdnode.ll | 58 +-
llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll | 102 +-
.../rvv/froundeven-constrained-sdnode.ll | 58 +-
.../CodeGen/RISCV/rvv/froundeven-sdnode.ll | 102 +-
llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll | 1067 +++-
.../RISCV/rvv/ftrunc-constrained-sdnode.ll | 26 +-
.../test/CodeGen/RISCV/rvv/half-round-conv.ll | 8 +-
.../CodeGen/RISCV/rvv/insert-subvector.ll | 20 +-
llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll | 4 +-
.../test/CodeGen/RISCV/rvv/mask-reg-alloc.mir | 6 +-
llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll | 66 +-
.../test/CodeGen/RISCV/rvv/mscatter-sdnode.ll | 32 +-
.../RISCV/rvv/mutate-prior-vsetvli-avl.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll | 280 +-
llvm/test/CodeGen/RISCV/rvv/pr165232.ll | 269 +-
llvm/test/CodeGen/RISCV/rvv/pr88576.ll | 29 +-
.../CodeGen/RISCV/rvv/reproducer-pr146855.ll | 23 +-
llvm/test/CodeGen/RISCV/rvv/rint-vp.ll | 292 +-
llvm/test/CodeGen/RISCV/rvv/round-vp.ll | 428 +-
llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll | 428 +-
llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll | 428 +-
.../RISCV/rvv/rvv-peephole-vmerge-vops.ll | 2 +-
llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll | 392 +-
llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll | 56 +-
.../CodeGen/RISCV/rvv/sink-splat-operands.ll | 24 +-
llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll | 44 +-
.../test/CodeGen/RISCV/rvv/strided-vpstore.ll | 16 +-
llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll | 176 +-
llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll | 12 +-
.../RISCV/rvv/vector-deinterleave-fixed.ll | 79 +-
.../RISCV/rvv/vector-deinterleave-load.ll | 18 +-
.../CodeGen/RISCV/rvv/vector-deinterleave.ll | 319 +-
.../RISCV/rvv/vector-interleave-store.ll | 2 +-
.../CodeGen/RISCV/rvv/vector-interleave.ll | 709 +--
llvm/test/CodeGen/RISCV/rvv/vector-splice.ll | 360 +-
llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll | 1066 +++-
.../RISCV/rvv/vfcmp-constrained-sdnode.ll | 300 +-
llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll | 426 +-
llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll | 5438 +++++++++++------
llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll | 270 +-
llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll | 270 +-
llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll | 213 +-
llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll | 6 +-
llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll | 8 +-
llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll | 8 +-
llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll | 15 +-
llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll | 52 +-
llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll | 426 +-
llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll | 32 +-
llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/vmseq.ll | 16 +-
llvm/test/CodeGen/RISCV/rvv/vmsge.ll | 16 +-
llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll | 16 +-
llvm/test/CodeGen/RISCV/rvv/vmsgt.ll | 16 +-
llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll | 16 +-
llvm/test/CodeGen/RISCV/rvv/vmsle.ll | 16 +-
llvm/test/CodeGen/RISCV/rvv/vmsleu.ll | 16 +-
llvm/test/CodeGen/RISCV/rvv/vmslt.ll | 16 +-
llvm/test/CodeGen/RISCV/rvv/vmsltu.ll | 16 +-
llvm/test/CodeGen/RISCV/rvv/vmsne.ll | 16 +-
.../rvv/vp-reverse-mask-fixed-vectors.ll | 48 +-
.../test/CodeGen/RISCV/rvv/vp-reverse-mask.ll | 105 +-
.../RISCV/rvv/vp-splice-mask-fixed-vectors.ll | 344 +-
.../RISCV/rvv/vp-splice-mask-vectors.ll | 622 +-
llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll | 2 +-
.../RISCV/rvv/vp-vector-interleaved-access.ll | 130 +-
.../test/CodeGen/RISCV/rvv/vpgather-sdnode.ll | 71 +-
llvm/test/CodeGen/RISCV/rvv/vpload.ll | 60 +-
llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll | 65 +-
.../CodeGen/RISCV/rvv/vpscatter-sdnode.ll | 40 +-
llvm/test/CodeGen/RISCV/rvv/vpstore.ll | 20 +-
.../CodeGen/RISCV/rvv/vreductions-fp-vp.ll | 24 +-
.../CodeGen/RISCV/rvv/vreductions-int-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll | 8 +-
llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll | 8 +-
.../RISCV/rvv/vscale-vw-web-simplification.ll | 128 +-
llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll | 24 +-
llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll | 54 +-
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll | 8 +-
llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll | 8 +-
llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll | 41 +-
llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll | 12 +-
.../CodeGen/RISCV/rvv/vwadd-mask-sdnode.ll | 21 +-
.../CodeGen/RISCV/rvv/vwsub-mask-sdnode.ll | 14 +-
llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll | 4 +-
.../CodeGen/RISCV/srem-seteq-illegal-types.ll | 4 +-
.../CodeGen/RISCV/urem-seteq-illegal-types.ll | 44 +-
225 files changed, 22931 insertions(+), 16373 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 62a5cd3a7c840..199660f0374fe 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -109,6 +109,10 @@ static cl::opt<bool> EnableCFIInstrInserter(
cl::desc("Enable CFI Instruction Inserter for RISC-V"), cl::init(false),
cl::Hidden);
+static cl::opt<bool> EnableV0Elimination("riscv-enable-v0-elimination",
+ cl::desc("Enable V0 Elimination Pass"),
+ cl::init(false), cl::Hidden);
+
extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
@@ -623,7 +627,8 @@ void RISCVPassConfig::addPreRegAlloc() {
if (TM->getOptLevel() != CodeGenOptLevel::None && EnableMachinePipeliner)
addPass(&MachinePipelinerID);
- addPass(createRISCVVMV0EliminationPass());
+ if (EnableV0Elimination)
+ addPass(createRISCVVMV0EliminationPass());
}
void RISCVPassConfig::addFastRegAlloc() {
diff --git a/llvm/test/CodeGen/RISCV/O0-pipeline.ll b/llvm/test/CodeGen/RISCV/O0-pipeline.ll
index c3e0ed9b85ec7..aed52de365cf7 100644
--- a/llvm/test/CodeGen/RISCV/O0-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O0-pipeline.ll
@@ -44,7 +44,6 @@
; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
; CHECK-NEXT: RISC-V Insert Write VXRM Pass
; CHECK-NEXT: RISC-V Landing Pad Setup
-; CHECK-NEXT: RISC-V VMV0 Elimination
; CHECK-NEXT: Init Undef Pass
; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Two-Address instruction pass
diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
index 3b63c1d86d3b1..c8016e3d48345 100644
--- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -131,7 +131,6 @@
; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
; CHECK-NEXT: RISC-V Insert Write VXRM Pass
; CHECK-NEXT: RISC-V Landing Pad Setup
-; CHECK-NEXT: RISC-V VMV0 Elimination
; CHECK-NEXT: Detect Dead Lanes
; CHECK-NEXT: Init Undef Pass
; CHECK-NEXT: Process Implicit Definitions
diff --git a/llvm/test/CodeGen/RISCV/combine-storetomstore.ll b/llvm/test/CodeGen/RISCV/combine-storetomstore.ll
index c7d1f76e73cf2..19882d41b5445 100644
--- a/llvm/test/CodeGen/RISCV/combine-storetomstore.ll
+++ b/llvm/test/CodeGen/RISCV/combine-storetomstore.ll
@@ -53,7 +53,6 @@ define void @test_masked_store_success_v4f16(<4 x half> %x, ptr %ptr, <4 x i1> %
; RISCV-LABEL: test_masked_store_success_v4f16:
; RISCV: # %bb.0:
; RISCV-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; RISCV-NEXT: vmv1r.v v9, v0
; RISCV-NEXT: vfirst.m a3, v0
; RISCV-NEXT: mv a2, a0
; RISCV-NEXT: beqz a3, .LBB4_2
@@ -62,17 +61,17 @@ define void @test_masked_store_success_v4f16(<4 x half> %x, ptr %ptr, <4 x i1> %
; RISCV-NEXT: .LBB4_2:
; RISCV-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RISCV-NEXT: vmv.v.i v8, 0
-; RISCV-NEXT: vmv1r.v v0, v9
+; RISCV-NEXT: vmv1r.v v11, v0
; RISCV-NEXT: vmerge.vim v8, v8, 1, v0
; RISCV-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RISCV-NEXT: vslidedown.vi v8, v8, 2
; RISCV-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; RISCV-NEXT: vmsne.vi v8, v8, 0
-; RISCV-NEXT: vmv.v.i v10, 0
-; RISCV-NEXT: vmv1r.v v0, v8
-; RISCV-NEXT: vmerge.vim v11, v10, 1, v0
-; RISCV-NEXT: vslidedown.vi v11, v11, 1
-; RISCV-NEXT: vmv.x.s a3, v11
+; RISCV-NEXT: vmsne.vi v0, v8, 0
+; RISCV-NEXT: vmv.v.i v8, 0
+; RISCV-NEXT: vmv1r.v v10, v0
+; RISCV-NEXT: vmerge.vim v9, v8, 1, v0
+; RISCV-NEXT: vslidedown.vi v9, v9, 1
+; RISCV-NEXT: vmv.x.s a3, v9
; RISCV-NEXT: andi a3, a3, 1
; RISCV-NEXT: bnez a3, .LBB4_4
; RISCV-NEXT: # %bb.3:
@@ -81,10 +80,10 @@ define void @test_masked_store_success_v4f16(<4 x half> %x, ptr %ptr, <4 x i1> %
; RISCV-NEXT: .LBB4_4:
; RISCV-NEXT: addi a3, a0, 24
; RISCV-NEXT: .LBB4_5:
-; RISCV-NEXT: vmv1r.v v0, v9
-; RISCV-NEXT: vmerge.vim v9, v10, 1, v0
-; RISCV-NEXT: vslidedown.vi v9, v9, 1
-; RISCV-NEXT: vmv.x.s a4, v9
+; RISCV-NEXT: vmv1r.v v0, v11
+; RISCV-NEXT: vmerge.vim v8, v8, 1, v0
+; RISCV-NEXT: vslidedown.vi v8, v8, 1
+; RISCV-NEXT: vmv.x.s a4, v8
; RISCV-NEXT: andi a4, a4, 1
; RISCV-NEXT: bnez a4, .LBB4_7
; RISCV-NEXT: # %bb.6:
@@ -96,7 +95,7 @@ define void @test_masked_store_success_v4f16(<4 x half> %x, ptr %ptr, <4 x i1> %
; RISCV-NEXT: lh a4, 0(a2)
; RISCV-NEXT: lh a2, 0(a3)
; RISCV-NEXT: lh a3, 0(a5)
-; RISCV-NEXT: vfirst.m a5, v8
+; RISCV-NEXT: vfirst.m a5, v10
; RISCV-NEXT: beqz a5, .LBB4_10
; RISCV-NEXT: # %bb.9:
; RISCV-NEXT: addi a0, a1, 4
@@ -192,7 +191,7 @@ define void @test_masked_store_success_v8f16(<8 x half> %x, ptr %ptr, <8 x i1> %
; RISCV-LABEL: test_masked_store_success_v8f16:
; RISCV: # %bb.0:
; RISCV-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; RISCV-NEXT: vmv1r.v v8, v0
+; RISCV-NEXT: vmv1r.v v11, v0
; RISCV-NEXT: vfirst.m a3, v0
; RISCV-NEXT: mv a2, a0
; RISCV-NEXT: beqz a3, .LBB11_2
@@ -200,25 +199,27 @@ define void @test_masked_store_success_v8f16(<8 x half> %x, ptr %ptr, <8 x i1> %
; RISCV-NEXT: mv a2, a1
; RISCV-NEXT: .LBB11_2:
; RISCV-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; RISCV-NEXT: vmv.v.i v8, 0
+; RISCV-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; RISCV-NEXT: vmv.v.i v9, 0
-; RISCV-NEXT: vmv1r.v v0, v8
-; RISCV-NEXT: vmerge.vim v9, v9, 1, v0
+; RISCV-NEXT: vmv1r.v v0, v11
+; RISCV-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; RISCV-NEXT: vmerge.vim v8, v8, 1, v0
; RISCV-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RISCV-NEXT: vslidedown.vi v9, v9, 4
+; RISCV-NEXT: vslidedown.vi v8, v8, 4
; RISCV-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; RISCV-NEXT: vmsne.vi v11, v9, 0
-; RISCV-NEXT: vmv.v.i v10, 0
-; RISCV-NEXT: vmv1r.v v0, v11
-; RISCV-NEXT: vmerge.vim v9, v10, 1, v0
+; RISCV-NEXT: vmsne.vi v0, v8, 0
+; RISCV-NEXT: vmv1r.v v13, v0
+; RISCV-NEXT: vmerge.vim v8, v9, 1, v0
; RISCV-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RISCV-NEXT: vslidedown.vi v9, v9, 2
+; RISCV-NEXT: vslidedown.vi v8, v8, 2
; RISCV-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; RISCV-NEXT: vmsne.vi v9, v9, 0
-; RISCV-NEXT: vmv.v.i v12, 0
-; RISCV-NEXT: vmv1r.v v0, v9
-; RISCV-NEXT: vmerge.vim v13, v12, 1, v0
-; RISCV-NEXT: vslidedown.vi v13, v13, 1
-; RISCV-NEXT: vmv.x.s a3, v13
+; RISCV-NEXT: vmsne.vi v0, v8, 0
+; RISCV-NEXT: vmv.v.i v8, 0
+; RISCV-NEXT: vmv1r.v v12, v0
+; RISCV-NEXT: vmerge.vim v10, v8, 1, v0
+; RISCV-NEXT: vslidedown.vi v10, v10, 1
+; RISCV-NEXT: vmv.x.s a3, v10
; RISCV-NEXT: andi a3, a3, 1
; RISCV-NEXT: bnez a3, .LBB11_4
; RISCV-NEXT: # %bb.3:
@@ -227,42 +228,42 @@ define void @test_masked_store_success_v8f16(<8 x half> %x, ptr %ptr, <8 x i1> %
; RISCV-NEXT: .LBB11_4:
; RISCV-NEXT: addi a3, a0, 56
; RISCV-NEXT: .LBB11_5:
-; RISCV-NEXT: vmv1r.v v0, v8
+; RISCV-NEXT: vmv1r.v v0, v11
; RISCV-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; RISCV-NEXT: vmerge.vim v10, v10, 1, v0
+; RISCV-NEXT: vmerge.vim v9, v9, 1, v0
; RISCV-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RISCV-NEXT: vslidedown.vi v10, v10, 2
+; RISCV-NEXT: vslidedown.vi v9, v9, 2
; RISCV-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; RISCV-NEXT: vmsne.vi v10, v10, 0
-; RISCV-NEXT: vmv1r.v v0, v10
-; RISCV-NEXT: vmerge.vim v13, v12, 1, v0
-; RISCV-NEXT: vslidedown.vi v13, v13, 1
-; RISCV-NEXT: vmv.x.s a4, v13
+; RISCV-NEXT: vmsne.vi v0, v9, 0
+; RISCV-NEXT: vmv1r.v v10, v0
+; RISCV-NEXT: vmerge.vim v9, v8, 1, v0
+; RISCV-NEXT: vslidedown.vi v9, v9, 1
+; RISCV-NEXT: vmv.x.s a4, v9
; RISCV-NEXT: andi a4, a4, 1
; RISCV-NEXT: bnez a4, .LBB11_8
; RISCV-NEXT: # %bb.6:
; RISCV-NEXT: addi a4, a1, 6
-; RISCV-NEXT: vfirst.m a5, v11
+; RISCV-NEXT: vfirst.m a5, v13
; RISCV-NEXT: bnez a5, .LBB11_9
; RISCV-NEXT: .LBB11_7:
; RISCV-NEXT: addi a5, a0, 32
; RISCV-NEXT: j .LBB11_10
; RISCV-NEXT: .LBB11_8:
; RISCV-NEXT: addi a4, a0, 24
-; RISCV-NEXT: vfirst.m a5, v11
+; RISCV-NEXT: vfirst.m a5, v13
; RISCV-NEXT: beqz a5, .LBB11_7
; RISCV-NEXT: .LBB11_9:
; RISCV-NEXT: addi a5, a1, 8
; RISCV-NEXT: .LBB11_10:
-; RISCV-NEXT: vmv1r.v v0, v11
-; RISCV-NEXT: vmerge.vim v11, v12, 1, v0
-; RISCV-NEXT: vslidedown.vi v11, v11, 1
-; RISCV-NEXT: vmv.x.s a6, v11
+; RISCV-NEXT: vmv1r.v v0, v13
+; RISCV-NEXT: vmerge.vim v9, v8, 1, v0
+; RISCV-NEXT: vslidedown.vi v9, v9, 1
+; RISCV-NEXT: vmv.x.s a6, v9
; RISCV-NEXT: andi a6, a6, 1
; RISCV-NEXT: bnez a6, .LBB11_14
; RISCV-NEXT: # %bb.11:
; RISCV-NEXT: addi a6, a1, 10
-; RISCV-NEXT: vfirst.m a7, v9
+; RISCV-NEXT: vfirst.m a7, v12
; RISCV-NEXT: bnez a7, .LBB11_15
; RISCV-NEXT: .LBB11_12:
; RISCV-NEXT: addi a7, a0, 48
@@ -273,7 +274,7 @@ define void @test_masked_store_success_v8f16(<8 x half> %x, ptr %ptr, <8 x i1> %
; RISCV-NEXT: j .LBB11_17
; RISCV-NEXT: .LBB11_14:
; RISCV-NEXT: addi a6, a0, 40
-; RISCV-NEXT: vfirst.m a7, v9
+; RISCV-NEXT: vfirst.m a7, v12
; RISCV-NEXT: beqz a7, .LBB11_12
; RISCV-NEXT: .LBB11_15:
; RISCV-NEXT: addi a7, a1, 12
@@ -282,7 +283,6 @@ define void @test_masked_store_success_v8f16(<8 x half> %x, ptr %ptr, <8 x i1> %
; RISCV-NEXT: .LBB11_16:
; RISCV-NEXT: addi t1, a1, 4
; RISCV-NEXT: .LBB11_17:
-; RISCV-NEXT: vmv1r.v v0, v8
; RISCV-NEXT: lh t0, 0(a2)
; RISCV-NEXT: lh a2, 0(a3)
; RISCV-NEXT: lh a3, 0(a4)
@@ -290,7 +290,8 @@ define void @test_masked_store_success_v8f16(<8 x half> %x, ptr %ptr, <8 x i1> %
; RISCV-NEXT: lh a5, 0(a6)
; RISCV-NEXT: lh a6, 0(a7)
; RISCV-NEXT: lh a7, 0(t1)
-; RISCV-NEXT: vmerge.vim v8, v12, 1, v0
+; RISCV-NEXT: vmv1r.v v0, v11
+; RISCV-NEXT: vmerge.vim v8, v8, 1, v0
; RISCV-NEXT: vslidedown.vi v8, v8, 1
; RISCV-NEXT: vmv.x.s t1, v8
; RISCV-NEXT: andi t1, t1, 1
@@ -566,13 +567,11 @@ define void @test_masked_store_multiple_v8i32(<8 x i32> %x, <8 x i32> %y, ptr %p
; RISCV-LABEL: test_masked_store_multiple_v8i32:
; RISCV: # %bb.0:
; RISCV-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RISCV-NEXT: vmv1r.v v13, v0
; RISCV-NEXT: vle32.v v14, (a1)
-; RISCV-NEXT: vmv1r.v v0, v12
-; RISCV-NEXT: vmerge.vvm v10, v14, v10, v0
-; RISCV-NEXT: vmv1r.v v0, v13
; RISCV-NEXT: vse32.v v8, (a0), v0.t
-; RISCV-NEXT: vse32.v v10, (a1)
+; RISCV-NEXT: vmv1r.v v0, v12
+; RISCV-NEXT: vmerge.vvm v8, v14, v10, v0
+; RISCV-NEXT: vse32.v v8, (a1)
; RISCV-NEXT: ret
%load = load <8 x i32>, ptr %ptr1, align 32
%load2 = load <8 x i32>, ptr %ptr2, align 32
@@ -587,13 +586,11 @@ define void @test_masked_store_multiple_v8i64(<8 x i64> %x, <8 x i64> %y, ptr %p
; RISCV-LABEL: test_masked_store_multiple_v8i64:
; RISCV: # %bb.0:
; RISCV-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RISCV-NEXT: vmv1r.v v17, v0
; RISCV-NEXT: vle64.v v20, (a1)
-; RISCV-NEXT: vmv1r.v v0, v16
-; RISCV-NEXT: vmerge.vvm v12, v20, v12, v0
-; RISCV-NEXT: vmv1r.v v0, v17
; RISCV-NEXT: vse64.v v8, (a0), v0.t
-; RISCV-NEXT: vse64.v v12, (a1)
+; RISCV-NEXT: vmv1r.v v0, v16
+; RISCV-NEXT: vmerge.vvm v8, v20, v12, v0
+; RISCV-NEXT: vse64.v v8, (a1)
; RISCV-NEXT: ret
%load = load <8 x i64>, ptr %ptr1, align 32
%load2 = load <8 x i64>, ptr %ptr2, align 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
index 5b215c5173211..dbe3609d61934 100644
--- a/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
@@ -513,11 +513,11 @@ define <vscale x 8 x i64> @vp_abs_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 z
define <vscale x 16 x i64> @vp_abs_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_abs_nxv16i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
diff --git a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
index 09b8fdbf11d26..5c7667b902863 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
@@ -13,20 +13,20 @@ define <vscale x 1 x i8> @vp_bitreverse_nxv1i8(<vscale x 1 x i8> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vand.vi v9, v8, 15, v0.t
+; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
@@ -77,20 +77,20 @@ define <vscale x 2 x i8> @vp_bitreverse_nxv2i8(<vscale x 2 x i8> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vand.vi v9, v8, 15, v0.t
+; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
@@ -141,20 +141,20 @@ define <vscale x 4 x i8> @vp_bitreverse_nxv4i8(<vscale x 4 x i8> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vand.vi v9, v8, 15, v0.t
+; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
@@ -205,20 +205,20 @@ define <vscale x 8 x i8> @vp_bitreverse_nxv8i8(<vscale x 8 x i8> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vand.vi v9, v8, 15, v0.t
+; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
@@ -269,20 +269,20 @@ define <vscale x 16 x i8> @vp_bitreverse_nxv16i8(<vscale x 16 x i8> %va, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vand.vi v10, v8, 15, v0.t
+; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsll.vi v10, v10, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
@@ -333,20 +333,20 @@ define <vscale x 32 x i8> @vp_bitreverse_nxv32i8(<vscale x 32 x i8> %va, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vand.vi v12, v8, 15, v0.t
+; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsll.vi v12, v12, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
@@ -397,20 +397,20 @@ define <vscale x 64 x i8> @vp_bitreverse_nxv64i8(<vscale x 64 x i8> %va, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vand.vi v16, v8, 15, v0.t
+; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
-; CHECK-NEXT: vor.vv v16, v8, v16, v0.t
-; CHECK-NEXT: vsrl.vi v8, v16, 2, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsrl.vi v16, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
; CHECK-NEXT: li a0, 85
-; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
+; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
; CHECK-NEXT: ret
@@ -461,27 +461,27 @@ define <vscale x 1 x i16> @vp_bitreverse_nxv1i16(<vscale x 1 x i16> %va, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
-; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: addi a0, a0, -241
+; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, -241
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
@@ -539,27 +539,27 @@ define <vscale x 2 x i16> @vp_bitreverse_nxv2i16(<vscale x 2 x i16> %va, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
-; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: addi a0, a0, -241
+; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, -241
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
@@ -617,27 +617,27 @@ define <vscale x 4 x i16> @vp_bitreverse_nxv4i16(<vscale x 4 x i16> %va, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
-; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: addi a0, a0, -241
+; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, -241
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
@@ -695,27 +695,27 @@ define <vscale x 8 x i16> @vp_bitreverse_nxv8i16(<vscale x 8 x i16> %va, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t
-; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: addi a0, a0, -241
+; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
+; CHECK-NEXT: addi a0, a0, -241
; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
@@ -773,27 +773,27 @@ define <vscale x 16 x i16> @vp_bitreverse_nxv16i16(<vscale x 16 x i16> %va, <vsc
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t
-; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: addi a0, a0, -241
+; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
+; CHECK-NEXT: addi a0, a0, -241
; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
@@ -851,27 +851,27 @@ define <vscale x 32 x i16> @vp_bitreverse_nxv32i16(<vscale x 32 x i16> %va, <vsc
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v16, v8, 8, v0.t
-; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: lui a0, 1
+; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vor.vv v16, v8, v16, v0.t
-; CHECK-NEXT: vsrl.vi v8, v16, 4, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
+; CHECK-NEXT: vsrl.vi v24, v8, 4, v0.t
+; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
-; CHECK-NEXT: vor.vv v16, v8, v16, v0.t
-; CHECK-NEXT: vsrl.vi v8, v16, 2, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsrl.vi v24, v8, 2, v0.t
+; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
; CHECK-NEXT: ret
@@ -930,34 +930,34 @@ define <vscale x 1 x i32> @vp_bitreverse_nxv1i32(<vscale x 1 x i32> %va, <vscale
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
; CHECK-NEXT: vor.vv v9, v9, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v10, v8, 24, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: lui a0, 61681
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 209715
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
@@ -1024,34 +1024,34 @@ define <vscale x 2 x i32> @vp_bitreverse_nxv2i32(<vscale x 2 x i32> %va, <vscale
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
; CHECK-NEXT: vor.vv v9, v9, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v10, v8, 24, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: lui a0, 61681
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 209715
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
@@ -1118,34 +1118,34 @@ define <vscale x 4 x i32> @vp_bitreverse_nxv4i32(<vscale x 4 x i32> %va, <vscale
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v12, v8, 24, v0.t
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 24, v0.t
; CHECK-NEXT: vor.vv v10, v10, v12, v0.t
-; CHECK-NEXT: vand.vx v12, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v12, v8, 24, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: lui a0, 61681
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vsll.vi v12, v12, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: lui a0, 209715
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
@@ -1212,34 +1212,34 @@ define <vscale x 8 x i32> @vp_bitreverse_nxv8i32(<vscale x 8 x i32> %va, <vscale
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v16, v8, 24, v0.t
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vsrl.vi v16, v8, 24, v0.t
; CHECK-NEXT: vor.vv v12, v12, v16, v0.t
-; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v16, v8, 24, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: lui a0, 61681
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: lui a0, 209715
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
@@ -1306,34 +1306,34 @@ define <vscale x 16 x i32> @vp_bitreverse_nxv16i32(<vscale x 16 x i32> %va, <vsc
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vsrl.vi v16, v8, 8, v0.t
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v24, v8, 24, v0.t
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
-; CHECK-NEXT: vsrl.vi v24, v8, 24, v0.t
; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
-; CHECK-NEXT: vand.vx v24, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v24, v8, 24, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: lui a0, 61681
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vsll.vi v24, v24, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v24, v0.t
-; CHECK-NEXT: vor.vv v16, v8, v16, v0.t
-; CHECK-NEXT: vsrl.vi v8, v16, 4, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsrl.vi v24, v8, 4, v0.t
+; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
; CHECK-NEXT: lui a0, 209715
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
-; CHECK-NEXT: vor.vv v16, v8, v16, v0.t
-; CHECK-NEXT: vsrl.vi v8, v16, 2, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsrl.vi v24, v8, 2, v0.t
+; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
; CHECK-NEXT: ret
@@ -1399,66 +1399,66 @@ define <vscale x 1 x i64> @vp_bitreverse_nxv1i64(<vscale x 1 x i64> %va, <vscale
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a4, 1044480
-; RV32-NEXT: li a3, 56
-; RV32-NEXT: lui a5, 16
-; RV32-NEXT: li a2, 40
-; RV32-NEXT: lui a1, 4080
+; RV32-NEXT: lui a1, 1044480
+; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a3, 16
+; RV32-NEXT: li a4, 40
+; RV32-NEXT: lui a5, 4080
; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a4, 8(sp)
-; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vlse64.v v9, (a6), zero
-; RV32-NEXT: lui a4, 61681
-; RV32-NEXT: vsll.vx v10, v8, a3, v0.t
-; RV32-NEXT: addi a5, a5, -256
-; RV32-NEXT: vand.vx v11, v8, a5, v0.t
-; RV32-NEXT: vsll.vx v11, v11, a2, v0.t
-; RV32-NEXT: vor.vv v10, v10, v11, v0.t
-; RV32-NEXT: vand.vx v11, v8, a1, v0.t
-; RV32-NEXT: vsll.vi v11, v11, 24, v0.t
-; RV32-NEXT: vand.vv v12, v8, v9, v0.t
-; RV32-NEXT: vsll.vi v12, v12, 8, v0.t
-; RV32-NEXT: vor.vv v11, v11, v12, v0.t
-; RV32-NEXT: vor.vv v10, v10, v11, v0.t
-; RV32-NEXT: vsrl.vx v11, v8, a3, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t
-; RV32-NEXT: lui a2, 349525
-; RV32-NEXT: addi a4, a4, -241
-; RV32-NEXT: addi a3, a3, 819
-; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vand.vx v12, v12, a5, v0.t
-; RV32-NEXT: vor.vv v11, v12, v11, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t
+; RV32-NEXT: vsrl.vi v9, v8, 24, v0.t
+; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: vsll.vx v10, v8, a2, v0.t
+; RV32-NEXT: addi a1, a3, -256
+; RV32-NEXT: vsrl.vx v11, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v12, v8, a4, v0.t
+; RV32-NEXT: vand.vx v13, v8, a1, v0.t
; RV32-NEXT: vand.vx v12, v12, a1, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v9, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; RV32-NEXT: vmv.v.x v9, a4
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; RV32-NEXT: vor.vv v11, v12, v11, v0.t
+; RV32-NEXT: vlse64.v v12, (a6), zero
+; RV32-NEXT: vsll.vx v13, v13, a4, v0.t
+; RV32-NEXT: vor.vv v10, v10, v13, v0.t
+; RV32-NEXT: vsrl.vi v13, v8, 8, v0.t
+; RV32-NEXT: vand.vx v9, v9, a5, v0.t
+; RV32-NEXT: vand.vv v13, v13, v12, v0.t
+; RV32-NEXT: vor.vv v9, v13, v9, v0.t
+; RV32-NEXT: lui a1, 61681
+; RV32-NEXT: lui a2, 209715
+; RV32-NEXT: lui a3, 349525
+; RV32-NEXT: vand.vv v12, v8, v12, v0.t
+; RV32-NEXT: vand.vx v8, v8, a5, v0.t
+; RV32-NEXT: addi a1, a1, -241
+; RV32-NEXT: addi a2, a2, 819
+; RV32-NEXT: addi a3, a3, 1365
+; RV32-NEXT: vsll.vi v8, v8, 24, v0.t
+; RV32-NEXT: vsll.vi v12, v12, 8, v0.t
; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; RV32-NEXT: vmv.v.x v12, a3
+; RV32-NEXT: vsetvli a4, zero, e32, m1, ta, ma
+; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v11, v0.t
+; RV32-NEXT: vor.vv v9, v9, v11, v0.t
; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v11, a2
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vor.vv v8, v10, v8, v0.t
-; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t
-; RV32-NEXT: vand.vv v10, v10, v9, v0.t
-; RV32-NEXT: vand.vv v8, v8, v9, v0.t
+; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; RV32-NEXT: vmv.v.x v10, a3
+; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v9, v0.t
+; RV32-NEXT: vsrl.vi v9, v8, 4, v0.t
+; RV32-NEXT: vand.vv v8, v8, v12, v0.t
+; RV32-NEXT: vand.vv v9, v9, v12, v0.t
; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v10, v8, v0.t
+; RV32-NEXT: vor.vv v8, v9, v8, v0.t
; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t
-; RV32-NEXT: vand.vv v9, v9, v12, v0.t
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
+; RV32-NEXT: vand.vv v8, v8, v11, v0.t
+; RV32-NEXT: vand.vv v9, v9, v11, v0.t
; RV32-NEXT: vsll.vi v8, v8, 2, v0.t
; RV32-NEXT: vor.vv v8, v9, v8, v0.t
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
-; RV32-NEXT: vand.vv v9, v9, v11, v0.t
-; RV32-NEXT: vand.vv v8, v8, v11, v0.t
+; RV32-NEXT: vand.vv v8, v8, v10, v0.t
+; RV32-NEXT: vand.vv v9, v9, v10, v0.t
; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v9, v8, v0.t
; RV32-NEXT: addi sp, sp, 16
@@ -1468,59 +1468,59 @@ define <vscale x 1 x i64> @vp_bitreverse_nxv1i64(<vscale x 1 x i64> %va, <vscale
; RV64-LABEL: vp_bitreverse_nxv1i64:
; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a3, 255
-; RV64-NEXT: li a2, 56
+; RV64-NEXT: li a2, 255
+; RV64-NEXT: li a3, 56
; RV64-NEXT: lui a4, 16
-; RV64-NEXT: lui a5, 61681
-; RV64-NEXT: lui a6, 209715
-; RV64-NEXT: lui a7, 349525
-; RV64-NEXT: addi a5, a5, -241
-; RV64-NEXT: addi a6, a6, 819
-; RV64-NEXT: addi a7, a7, 1365
-; RV64-NEXT: slli t0, a5, 32
-; RV64-NEXT: add t0, a5, t0
-; RV64-NEXT: slli a5, a6, 32
-; RV64-NEXT: add a6, a6, a5
-; RV64-NEXT: slli a5, a7, 32
-; RV64-NEXT: add a5, a7, a5
-; RV64-NEXT: li a7, 40
+; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV64-NEXT: vand.vx v9, v8, a1, v0.t
-; RV64-NEXT: slli a3, a3, 24
+; RV64-NEXT: vsrl.vi v9, v8, 24, v0.t
+; RV64-NEXT: vsrl.vi v10, v8, 8, v0.t
; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v9, v9, 24, v0.t
-; RV64-NEXT: vand.vx v10, v8, a3, v0.t
-; RV64-NEXT: vsll.vi v10, v10, 8, v0.t
-; RV64-NEXT: vor.vv v9, v9, v10, v0.t
-; RV64-NEXT: vsll.vx v10, v8, a2, v0.t
-; RV64-NEXT: vand.vx v11, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v11, v11, a7, v0.t
-; RV64-NEXT: vor.vv v10, v10, v11, v0.t
+; RV64-NEXT: vsrl.vx v11, v8, a3, v0.t
+; RV64-NEXT: vsrl.vx v12, v8, a5, v0.t
+; RV64-NEXT: vand.vx v12, v12, a0, v0.t
+; RV64-NEXT: vor.vv v11, v12, v11, v0.t
+; RV64-NEXT: vand.vx v12, v8, a1, v0.t
+; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vand.vx v9, v9, a1, v0.t
+; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
+; RV64-NEXT: vand.vx v10, v10, a2, v0.t
; RV64-NEXT: vor.vv v9, v10, v9, v0.t
-; RV64-NEXT: vsrl.vx v10, v8, a2, v0.t
-; RV64-NEXT: vsrl.vx v11, v8, a7, v0.t
-; RV64-NEXT: vand.vx v11, v11, a0, v0.t
-; RV64-NEXT: vor.vv v10, v11, v10, v0.t
-; RV64-NEXT: vsrl.vi v11, v8, 24, v0.t
-; RV64-NEXT: vand.vx v11, v11, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: vor.vv v8, v8, v11, v0.t
+; RV64-NEXT: vand.vx v10, v8, a2, v0.t
+; RV64-NEXT: vsll.vi v10, v10, 8, v0.t
+; RV64-NEXT: vor.vv v10, v12, v10, v0.t
+; RV64-NEXT: vsll.vx v12, v8, a3, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsll.vx v8, v8, a5, v0.t
+; RV64-NEXT: vor.vv v8, v12, v8, v0.t
+; RV64-NEXT: lui a0, 61681
+; RV64-NEXT: lui a1, 209715
+; RV64-NEXT: lui a2, 349525
+; RV64-NEXT: addi a0, a0, -241
+; RV64-NEXT: addi a1, a1, 819
+; RV64-NEXT: addi a2, a2, 1365
+; RV64-NEXT: slli a3, a0, 32
+; RV64-NEXT: slli a4, a1, 32
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: slli a3, a2, 32
+; RV64-NEXT: add a1, a1, a4
+; RV64-NEXT: add a2, a2, a3
+; RV64-NEXT: vor.vv v9, v9, v11, v0.t
; RV64-NEXT: vor.vv v8, v8, v10, v0.t
-; RV64-NEXT: vor.vv v8, v9, v8, v0.t
+; RV64-NEXT: vor.vv v8, v8, v9, v0.t
; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
-; RV64-NEXT: vand.vx v9, v9, t0, v0.t
-; RV64-NEXT: vand.vx v8, v8, t0, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vand.vx v9, v9, a0, v0.t
; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
; RV64-NEXT: vor.vv v8, v9, v8, v0.t
; RV64-NEXT: vsrl.vi v9, v8, 2, v0.t
-; RV64-NEXT: vand.vx v9, v9, a6, v0.t
-; RV64-NEXT: vand.vx v8, v8, a6, v0.t
+; RV64-NEXT: vand.vx v8, v8, a1, v0.t
+; RV64-NEXT: vand.vx v9, v9, a1, v0.t
; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
; RV64-NEXT: vor.vv v8, v9, v8, v0.t
; RV64-NEXT: vsrl.vi v9, v8, 1, v0.t
-; RV64-NEXT: vand.vx v9, v9, a5, v0.t
-; RV64-NEXT: vand.vx v8, v8, a5, v0.t
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vand.vx v9, v9, a2, v0.t
; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
; RV64-NEXT: vor.vv v8, v9, v8, v0.t
; RV64-NEXT: ret
@@ -1679,66 +1679,66 @@ define <vscale x 2 x i64> @vp_bitreverse_nxv2i64(<vscale x 2 x i64> %va, <vscale
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a4, 1044480
-; RV32-NEXT: li a3, 56
-; RV32-NEXT: lui a5, 16
-; RV32-NEXT: li a2, 40
-; RV32-NEXT: lui a1, 4080
+; RV32-NEXT: lui a1, 1044480
+; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a3, 16
+; RV32-NEXT: li a4, 40
+; RV32-NEXT: lui a5, 4080
; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a4, 8(sp)
-; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vlse64.v v10, (a6), zero
-; RV32-NEXT: lui a4, 61681
-; RV32-NEXT: vsll.vx v12, v8, a3, v0.t
-; RV32-NEXT: addi a5, a5, -256
-; RV32-NEXT: vand.vx v14, v8, a5, v0.t
-; RV32-NEXT: vsll.vx v14, v14, a2, v0.t
-; RV32-NEXT: vor.vv v12, v12, v14, v0.t
-; RV32-NEXT: vand.vx v14, v8, a1, v0.t
-; RV32-NEXT: vsll.vi v14, v14, 24, v0.t
-; RV32-NEXT: vand.vv v16, v8, v10, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v14, v14, v16, v0.t
-; RV32-NEXT: vor.vv v12, v12, v14, v0.t
-; RV32-NEXT: vsrl.vx v14, v8, a3, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: lui a2, 349525
-; RV32-NEXT: addi a4, a4, -241
-; RV32-NEXT: addi a3, a3, 819
-; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vand.vx v16, v16, a5, v0.t
-; RV32-NEXT: vor.vv v14, v16, v14, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV32-NEXT: vand.vx v16, v16, a1, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v10, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v10, a4
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; RV32-NEXT: vsrl.vi v14, v8, 24, v0.t
+; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: vsll.vx v12, v8, a2, v0.t
+; RV32-NEXT: addi a1, a3, -256
+; RV32-NEXT: vsrl.vx v10, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a4, v0.t
+; RV32-NEXT: vand.vx v18, v8, a1, v0.t
+; RV32-NEXT: vand.vx v16, v16, a1, v0.t
+; RV32-NEXT: vor.vv v10, v16, v10, v0.t
+; RV32-NEXT: vlse64.v v16, (a6), zero
+; RV32-NEXT: vsll.vx v18, v18, a4, v0.t
+; RV32-NEXT: vor.vv v12, v12, v18, v0.t
+; RV32-NEXT: vsrl.vi v18, v8, 8, v0.t
+; RV32-NEXT: vand.vx v14, v14, a5, v0.t
+; RV32-NEXT: vand.vv v18, v18, v16, v0.t
+; RV32-NEXT: vor.vv v14, v18, v14, v0.t
+; RV32-NEXT: lui a1, 61681
+; RV32-NEXT: lui a2, 209715
+; RV32-NEXT: lui a3, 349525
+; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vand.vx v8, v8, a5, v0.t
+; RV32-NEXT: addi a1, a1, -241
+; RV32-NEXT: addi a2, a2, 819
+; RV32-NEXT: addi a3, a3, 1365
+; RV32-NEXT: vsll.vi v8, v8, 24, v0.t
+; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
+; RV32-NEXT: vsetvli a4, zero, e32, m2, ta, ma
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v14, v0.t
+; RV32-NEXT: vor.vv v10, v14, v10, v0.t
; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v14, a2
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vor.vv v8, v12, v8, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
-; RV32-NEXT: vand.vv v12, v12, v10, v0.t
-; RV32-NEXT: vand.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; RV32-NEXT: vmv.v.x v12, a3
+; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vand.vv v10, v10, v16, v0.t
; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v12, v8, v0.t
+; RV32-NEXT: vor.vv v8, v10, v8, v0.t
; RV32-NEXT: vsrl.vi v10, v8, 2, v0.t
-; RV32-NEXT: vand.vv v10, v10, v16, v0.t
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vand.vv v8, v8, v14, v0.t
+; RV32-NEXT: vand.vv v10, v10, v14, v0.t
; RV32-NEXT: vsll.vi v8, v8, 2, v0.t
; RV32-NEXT: vor.vv v8, v10, v8, v0.t
; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
-; RV32-NEXT: vand.vv v10, v10, v14, v0.t
-; RV32-NEXT: vand.vv v8, v8, v14, v0.t
+; RV32-NEXT: vand.vv v8, v8, v12, v0.t
+; RV32-NEXT: vand.vv v10, v10, v12, v0.t
; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v10, v8, v0.t
; RV32-NEXT: addi sp, sp, 16
@@ -1748,59 +1748,59 @@ define <vscale x 2 x i64> @vp_bitreverse_nxv2i64(<vscale x 2 x i64> %va, <vscale
; RV64-LABEL: vp_bitreverse_nxv2i64:
; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a3, 255
-; RV64-NEXT: li a2, 56
+; RV64-NEXT: li a2, 255
+; RV64-NEXT: li a3, 56
; RV64-NEXT: lui a4, 16
-; RV64-NEXT: lui a5, 61681
-; RV64-NEXT: lui a6, 209715
-; RV64-NEXT: lui a7, 349525
-; RV64-NEXT: addi a5, a5, -241
-; RV64-NEXT: addi a6, a6, 819
-; RV64-NEXT: addi a7, a7, 1365
-; RV64-NEXT: slli t0, a5, 32
-; RV64-NEXT: add t0, a5, t0
-; RV64-NEXT: slli a5, a6, 32
-; RV64-NEXT: add a6, a6, a5
-; RV64-NEXT: slli a5, a7, 32
-; RV64-NEXT: add a5, a7, a5
-; RV64-NEXT: li a7, 40
+; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV64-NEXT: vand.vx v10, v8, a1, v0.t
-; RV64-NEXT: slli a3, a3, 24
+; RV64-NEXT: vsrl.vi v12, v8, 24, v0.t
+; RV64-NEXT: vsrl.vi v14, v8, 8, v0.t
; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v10, v10, 24, v0.t
-; RV64-NEXT: vand.vx v12, v8, a3, v0.t
-; RV64-NEXT: vsll.vi v12, v12, 8, v0.t
-; RV64-NEXT: vor.vv v10, v10, v12, v0.t
-; RV64-NEXT: vsll.vx v12, v8, a2, v0.t
-; RV64-NEXT: vand.vx v14, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v14, v14, a7, v0.t
-; RV64-NEXT: vor.vv v12, v12, v14, v0.t
-; RV64-NEXT: vor.vv v10, v12, v10, v0.t
-; RV64-NEXT: vsrl.vx v12, v8, a2, v0.t
-; RV64-NEXT: vsrl.vx v14, v8, a7, v0.t
-; RV64-NEXT: vand.vx v14, v14, a0, v0.t
+; RV64-NEXT: vsrl.vx v10, v8, a3, v0.t
+; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
+; RV64-NEXT: vand.vx v16, v16, a0, v0.t
+; RV64-NEXT: vor.vv v10, v16, v10, v0.t
+; RV64-NEXT: vand.vx v16, v8, a1, v0.t
+; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vand.vx v12, v12, a1, v0.t
+; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
+; RV64-NEXT: vand.vx v14, v14, a2, v0.t
; RV64-NEXT: vor.vv v12, v14, v12, v0.t
-; RV64-NEXT: vsrl.vi v14, v8, 24, v0.t
-; RV64-NEXT: vand.vx v14, v14, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
+; RV64-NEXT: vand.vx v14, v8, a2, v0.t
+; RV64-NEXT: vsll.vi v14, v14, 8, v0.t
+; RV64-NEXT: vor.vv v14, v16, v14, v0.t
+; RV64-NEXT: vsll.vx v16, v8, a3, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsll.vx v8, v8, a5, v0.t
+; RV64-NEXT: vor.vv v8, v16, v8, v0.t
+; RV64-NEXT: lui a0, 61681
+; RV64-NEXT: lui a1, 209715
+; RV64-NEXT: lui a2, 349525
+; RV64-NEXT: addi a0, a0, -241
+; RV64-NEXT: addi a1, a1, 819
+; RV64-NEXT: addi a2, a2, 1365
+; RV64-NEXT: slli a3, a0, 32
+; RV64-NEXT: slli a4, a1, 32
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: slli a3, a2, 32
+; RV64-NEXT: add a1, a1, a4
+; RV64-NEXT: add a2, a2, a3
+; RV64-NEXT: vor.vv v10, v12, v10, v0.t
; RV64-NEXT: vor.vv v8, v8, v14, v0.t
-; RV64-NEXT: vor.vv v8, v8, v12, v0.t
-; RV64-NEXT: vor.vv v8, v10, v8, v0.t
+; RV64-NEXT: vor.vv v8, v8, v10, v0.t
; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
-; RV64-NEXT: vand.vx v10, v10, t0, v0.t
-; RV64-NEXT: vand.vx v8, v8, t0, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vand.vx v10, v10, a0, v0.t
; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
; RV64-NEXT: vor.vv v8, v10, v8, v0.t
; RV64-NEXT: vsrl.vi v10, v8, 2, v0.t
-; RV64-NEXT: vand.vx v10, v10, a6, v0.t
-; RV64-NEXT: vand.vx v8, v8, a6, v0.t
+; RV64-NEXT: vand.vx v8, v8, a1, v0.t
+; RV64-NEXT: vand.vx v10, v10, a1, v0.t
; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
; RV64-NEXT: vor.vv v8, v10, v8, v0.t
; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t
-; RV64-NEXT: vand.vx v10, v10, a5, v0.t
-; RV64-NEXT: vand.vx v8, v8, a5, v0.t
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vand.vx v10, v10, a2, v0.t
; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
; RV64-NEXT: vor.vv v8, v10, v8, v0.t
; RV64-NEXT: ret
@@ -1959,68 +1959,68 @@ define <vscale x 4 x i64> @vp_bitreverse_nxv4i64(<vscale x 4 x i64> %va, <vscale
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a4, 1044480
-; RV32-NEXT: li a3, 56
-; RV32-NEXT: lui a5, 16
-; RV32-NEXT: li a2, 40
-; RV32-NEXT: lui a1, 4080
+; RV32-NEXT: lui a1, 1044480
+; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a3, 16
+; RV32-NEXT: li a4, 40
+; RV32-NEXT: lui a5, 4080
; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a4, 8(sp)
-; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vlse64.v v12, (a6), zero
-; RV32-NEXT: lui a4, 61681
-; RV32-NEXT: vsll.vx v16, v8, a3, v0.t
-; RV32-NEXT: addi a5, a5, -256
-; RV32-NEXT: vand.vx v20, v8, a5, v0.t
-; RV32-NEXT: vsll.vx v20, v20, a2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vand.vx v20, v8, a1, v0.t
-; RV32-NEXT: vsll.vi v20, v20, 24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v12, v0.t
-; RV32-NEXT: vsll.vi v24, v24, 8, v0.t
-; RV32-NEXT: vor.vv v20, v20, v24, v0.t
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vsrl.vx v20, v8, a3, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t
-; RV32-NEXT: lui a2, 349525
-; RV32-NEXT: addi a4, a4, -241
-; RV32-NEXT: addi a3, a3, 819
-; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vand.vx v24, v24, a5, v0.t
-; RV32-NEXT: vor.vv v20, v24, v20, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
+; RV32-NEXT: vsrl.vi v20, v8, 24, v0.t
+; RV32-NEXT: sw a1, 8(sp)
+; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
+; RV32-NEXT: addi a1, a3, -256
+; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
+; RV32-NEXT: vand.vx v28, v8, a1, v0.t
; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
-; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v28, a4
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; RV32-NEXT: vor.vv v12, v24, v12, v0.t
+; RV32-NEXT: vlse64.v v24, (a6), zero
+; RV32-NEXT: vsll.vx v28, v28, a4, v0.t
+; RV32-NEXT: vor.vv v16, v16, v28, v0.t
+; RV32-NEXT: vsrl.vi v28, v8, 8, v0.t
+; RV32-NEXT: vand.vx v20, v20, a5, v0.t
+; RV32-NEXT: vand.vv v28, v28, v24, v0.t
+; RV32-NEXT: vor.vv v20, v28, v20, v0.t
+; RV32-NEXT: lui a1, 61681
+; RV32-NEXT: lui a2, 209715
+; RV32-NEXT: lui a3, 349525
+; RV32-NEXT: vand.vv v24, v8, v24, v0.t
+; RV32-NEXT: vand.vx v8, v8, a5, v0.t
+; RV32-NEXT: addi a1, a1, -241
+; RV32-NEXT: addi a2, a2, 819
+; RV32-NEXT: addi a3, a3, 1365
+; RV32-NEXT: vsll.vi v8, v8, 24, v0.t
+; RV32-NEXT: vsll.vi v24, v24, 8, v0.t
; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsetvli a4, zero, e32, m4, ta, ma
+; RV32-NEXT: vmv.v.x v24, a1
+; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; RV32-NEXT: vor.vv v12, v20, v12, v0.t
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v12, a3
+; RV32-NEXT: vmv.v.x v20, a2
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v20, v8, v20, v0.t
+; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v8, a2
+; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vsrl.vi v20, v16, 4, v0.t
-; RV32-NEXT: vand.vv v20, v20, v28, v0.t
-; RV32-NEXT: vand.vv v16, v16, v28, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 4, v0.t
-; RV32-NEXT: vor.vv v16, v20, v16, v0.t
-; RV32-NEXT: vsrl.vi v20, v16, 2, v0.t
-; RV32-NEXT: vand.vv v20, v20, v12, v0.t
-; RV32-NEXT: vand.vv v12, v16, v12, v0.t
-; RV32-NEXT: vsll.vi v12, v12, 2, v0.t
-; RV32-NEXT: vor.vv v12, v20, v12, v0.t
-; RV32-NEXT: vsrl.vi v16, v12, 1, v0.t
-; RV32-NEXT: vand.vv v16, v16, v8, v0.t
-; RV32-NEXT: vand.vv v8, v12, v8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v12, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vand.vv v12, v12, v24, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v12, v8, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 2, v0.t
+; RV32-NEXT: vand.vv v8, v8, v20, v0.t
+; RV32-NEXT: vand.vv v12, v12, v20, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v12, v8, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vand.vv v12, v12, v16, v0.t
; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vor.vv v8, v12, v8, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
@@ -2028,59 +2028,59 @@ define <vscale x 4 x i64> @vp_bitreverse_nxv4i64(<vscale x 4 x i64> %va, <vscale
; RV64-LABEL: vp_bitreverse_nxv4i64:
; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a3, 255
-; RV64-NEXT: li a2, 56
+; RV64-NEXT: li a2, 255
+; RV64-NEXT: li a3, 56
; RV64-NEXT: lui a4, 16
-; RV64-NEXT: lui a5, 61681
-; RV64-NEXT: lui a6, 209715
-; RV64-NEXT: lui a7, 349525
-; RV64-NEXT: addi a5, a5, -241
-; RV64-NEXT: addi a6, a6, 819
-; RV64-NEXT: addi a7, a7, 1365
-; RV64-NEXT: slli t0, a5, 32
-; RV64-NEXT: add t0, a5, t0
-; RV64-NEXT: slli a5, a6, 32
-; RV64-NEXT: add a6, a6, a5
-; RV64-NEXT: slli a5, a7, 32
-; RV64-NEXT: add a5, a7, a5
-; RV64-NEXT: li a7, 40
+; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV64-NEXT: vand.vx v12, v8, a1, v0.t
-; RV64-NEXT: slli a3, a3, 24
+; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
+; RV64-NEXT: vsrl.vi v20, v8, 8, v0.t
; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
-; RV64-NEXT: vand.vx v16, v8, a3, v0.t
-; RV64-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV64-NEXT: vor.vv v12, v12, v16, v0.t
-; RV64-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV64-NEXT: vand.vx v20, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v20, v20, a7, v0.t
-; RV64-NEXT: vor.vv v16, v16, v20, v0.t
-; RV64-NEXT: vor.vv v12, v16, v12, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV64-NEXT: vsrl.vx v20, v8, a7, v0.t
-; RV64-NEXT: vand.vx v20, v20, a0, v0.t
+; RV64-NEXT: vsrl.vx v12, v8, a3, v0.t
+; RV64-NEXT: vsrl.vx v24, v8, a5, v0.t
+; RV64-NEXT: vand.vx v24, v24, a0, v0.t
+; RV64-NEXT: vor.vv v12, v24, v12, v0.t
+; RV64-NEXT: vand.vx v24, v8, a1, v0.t
+; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vand.vx v16, v16, a1, v0.t
+; RV64-NEXT: vsll.vi v24, v24, 24, v0.t
+; RV64-NEXT: vand.vx v20, v20, a2, v0.t
; RV64-NEXT: vor.vv v16, v20, v16, v0.t
-; RV64-NEXT: vsrl.vi v20, v8, 24, v0.t
-; RV64-NEXT: vand.vx v20, v20, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
+; RV64-NEXT: vand.vx v20, v8, a2, v0.t
+; RV64-NEXT: vsll.vi v20, v20, 8, v0.t
+; RV64-NEXT: vor.vv v20, v24, v20, v0.t
+; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsll.vx v8, v8, a5, v0.t
+; RV64-NEXT: vor.vv v8, v24, v8, v0.t
+; RV64-NEXT: lui a0, 61681
+; RV64-NEXT: lui a1, 209715
+; RV64-NEXT: lui a2, 349525
+; RV64-NEXT: addi a0, a0, -241
+; RV64-NEXT: addi a1, a1, 819
+; RV64-NEXT: addi a2, a2, 1365
+; RV64-NEXT: slli a3, a0, 32
+; RV64-NEXT: slli a4, a1, 32
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: slli a3, a2, 32
+; RV64-NEXT: add a1, a1, a4
+; RV64-NEXT: add a2, a2, a3
+; RV64-NEXT: vor.vv v12, v16, v12, v0.t
; RV64-NEXT: vor.vv v8, v8, v20, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v12, v8, v0.t
+; RV64-NEXT: vor.vv v8, v8, v12, v0.t
; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
-; RV64-NEXT: vand.vx v12, v12, t0, v0.t
-; RV64-NEXT: vand.vx v8, v8, t0, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vand.vx v12, v12, a0, v0.t
; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
; RV64-NEXT: vor.vv v8, v12, v8, v0.t
; RV64-NEXT: vsrl.vi v12, v8, 2, v0.t
-; RV64-NEXT: vand.vx v12, v12, a6, v0.t
-; RV64-NEXT: vand.vx v8, v8, a6, v0.t
+; RV64-NEXT: vand.vx v8, v8, a1, v0.t
+; RV64-NEXT: vand.vx v12, v12, a1, v0.t
; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
; RV64-NEXT: vor.vv v8, v12, v8, v0.t
; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t
-; RV64-NEXT: vand.vx v12, v12, a5, v0.t
-; RV64-NEXT: vand.vx v8, v8, a5, v0.t
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vand.vx v12, v12, a2, v0.t
; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
; RV64-NEXT: vor.vv v8, v12, v8, v0.t
; RV64-NEXT: ret
@@ -2240,75 +2240,142 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64(<vscale x 7 x i64> %va, <vscale
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a2, a1, 5
+; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: lui a2, 16
+; RV32-NEXT: li a3, 40
+; RV32-NEXT: addi a2, a2, -256
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: vsrl.vx v24, v8, a3, v0.t
+; RV32-NEXT: vand.vx v24, v24, a2, v0.t
+; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: li a5, 24
+; RV32-NEXT: mul a4, a4, a5
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: slli a4, a4, 5
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vand.vx v24, v8, a2, v0.t
+; RV32-NEXT: vsll.vx v24, v24, a3, v0.t
+; RV32-NEXT: vsll.vx v16, v8, a1, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 4
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: lui a2, 4080
+; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vand.vx v24, v8, a1, v0.t
-; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vlse64.v v16, (a5), zero
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a3, 4080
-; RV32-NEXT: vand.vx v16, v8, a3, v0.t
-; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 4
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 3
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 3
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: vlse64.v v16, (a3), zero
; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a3, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
+; RV32-NEXT: vand.vx v24, v24, a2, v0.t
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vor.vv v24, v24, v16, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vx v24, v8, a2, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vor.vv v16, v24, v8, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 24
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 4
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v16, v24, v16, v0.t
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: lui a2, 209715
; RV32-NEXT: lui a3, 349525
@@ -2318,36 +2385,36 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64(<vscale x 7 x i64> %va, <vscale
; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v24, v0.t
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a2
+; RV32-NEXT: vmv.v.x v24, a2
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vi v24, v24, 4, v0.t
-; RV32-NEXT: vor.vv v24, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v16, v24, 2, v0.t
-; RV32-NEXT: vand.vv v16, v16, v8, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vand.vv v16, v16, v24, v0.t
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a3
+; RV32-NEXT: vmv.v.x v24, a3
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vi v24, v24, 2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vand.vv v16, v16, v24, v0.t
; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: slli a1, a0, 5
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
; RV32-NEXT: addi sp, sp, 16
@@ -2359,41 +2426,134 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64(<vscale x 7 x i64> %va, <vscale
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: li a2, 25
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
+; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
+; RV64-NEXT: lui a2, 4080
+; RV64-NEXT: li a3, 255
+; RV64-NEXT: li a1, 56
; RV64-NEXT: lui a4, 16
; RV64-NEXT: li a5, 40
+; RV64-NEXT: addi a4, a4, -256
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
+; RV64-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV64-NEXT: vsrl.vx v24, v8, a5, v0.t
+; RV64-NEXT: vand.vx v24, v24, a4, v0.t
+; RV64-NEXT: vor.vv v16, v24, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a6, 24
+; RV64-NEXT: mul a0, a0, a6
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs1r.v v0, (a0) # vscale x 8-byte Folded Spill
+; RV64-NEXT: vsrl.vi v24, v8, 24, v0.t
+; RV64-NEXT: slli a3, a3, 24
+; RV64-NEXT: vand.vx v24, v24, a2, v0.t
+; RV64-NEXT: vsrl.vi v16, v8, 8, v0.t
+; RV64-NEXT: vand.vx v16, v16, a3, v0.t
+; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a6, 24
+; RV64-NEXT: mul a0, a0, a6
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v16, v8, a2, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v24, v8, a3, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
-; RV64-NEXT: vand.vx v16, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v16, v16, a5, v0.t
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v24, v8, a4, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsll.vx v24, v24, a5, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsll.vx v8, v8, a1, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a1, 24
+; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vor.vv v24, v8, v24, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a1, 24
+; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vor.vv v8, v16, v8, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a1, 24
+; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: vor.vv v16, v24, v16, v0.t
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vor.vv v24, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: lui a0, 61681
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 349525
@@ -2406,26 +2566,25 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64(<vscale x 7 x i64> %va, <vscale
; RV64-NEXT: slli a3, a2, 32
; RV64-NEXT: add a1, a1, a4
; RV64-NEXT: add a2, a2, a3
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
; RV64-NEXT: vor.vv v8, v16, v8, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vand.vx v16, v16, a0, v0.t
; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
; RV64-NEXT: vor.vv v8, v16, v8, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
; RV64-NEXT: vand.vx v8, v8, a1, v0.t
+; RV64-NEXT: vand.vx v16, v16, a1, v0.t
; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
; RV64-NEXT: vor.vv v8, v16, v8, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV64-NEXT: vand.vx v16, v16, a2, v0.t
; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vand.vx v16, v16, a2, v0.t
; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
; RV64-NEXT: vor.vv v8, v16, v8, v0.t
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: li a1, 25
+; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 16
; RV64-NEXT: addi sp, sp, 16
@@ -2625,75 +2784,142 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64(<vscale x 8 x i64> %va, <vscale
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a2, a1, 5
+; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: lui a2, 16
+; RV32-NEXT: li a3, 40
+; RV32-NEXT: addi a2, a2, -256
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: vsrl.vx v24, v8, a3, v0.t
+; RV32-NEXT: vand.vx v24, v24, a2, v0.t
+; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: li a5, 24
+; RV32-NEXT: mul a4, a4, a5
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: slli a4, a4, 5
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vand.vx v24, v8, a2, v0.t
+; RV32-NEXT: vsll.vx v24, v24, a3, v0.t
+; RV32-NEXT: vsll.vx v16, v8, a1, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 4
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: lui a2, 4080
+; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vand.vx v24, v8, a1, v0.t
-; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vlse64.v v16, (a5), zero
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a3, 4080
-; RV32-NEXT: vand.vx v16, v8, a3, v0.t
-; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 4
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 3
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 3
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: vlse64.v v16, (a3), zero
; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a3, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
+; RV32-NEXT: vand.vx v24, v24, a2, v0.t
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vor.vv v24, v24, v16, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vx v24, v8, a2, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vor.vv v16, v24, v8, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 24
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 4
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v16, v24, v16, v0.t
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: lui a2, 209715
; RV32-NEXT: lui a3, 349525
@@ -2703,36 +2929,36 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64(<vscale x 8 x i64> %va, <vscale
; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v24, v0.t
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a2
+; RV32-NEXT: vmv.v.x v24, a2
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vi v24, v24, 4, v0.t
-; RV32-NEXT: vor.vv v24, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v16, v24, 2, v0.t
-; RV32-NEXT: vand.vv v16, v16, v8, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vand.vv v16, v16, v24, v0.t
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a3
+; RV32-NEXT: vmv.v.x v24, a3
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vi v24, v24, 2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vand.vv v16, v16, v24, v0.t
; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: slli a1, a0, 5
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
; RV32-NEXT: addi sp, sp, 16
@@ -2744,41 +2970,134 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64(<vscale x 8 x i64> %va, <vscale
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: li a2, 25
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
+; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
+; RV64-NEXT: lui a2, 4080
+; RV64-NEXT: li a3, 255
+; RV64-NEXT: li a1, 56
; RV64-NEXT: lui a4, 16
; RV64-NEXT: li a5, 40
+; RV64-NEXT: addi a4, a4, -256
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
+; RV64-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV64-NEXT: vsrl.vx v24, v8, a5, v0.t
+; RV64-NEXT: vand.vx v24, v24, a4, v0.t
+; RV64-NEXT: vor.vv v16, v24, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a6, 24
+; RV64-NEXT: mul a0, a0, a6
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs1r.v v0, (a0) # vscale x 8-byte Folded Spill
+; RV64-NEXT: vsrl.vi v24, v8, 24, v0.t
+; RV64-NEXT: slli a3, a3, 24
+; RV64-NEXT: vand.vx v24, v24, a2, v0.t
+; RV64-NEXT: vsrl.vi v16, v8, 8, v0.t
+; RV64-NEXT: vand.vx v16, v16, a3, v0.t
+; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a6, 24
+; RV64-NEXT: mul a0, a0, a6
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v16, v8, a2, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v24, v8, a3, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
-; RV64-NEXT: vand.vx v16, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v16, v16, a5, v0.t
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v24, v8, a4, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsll.vx v24, v24, a5, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsll.vx v8, v8, a1, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a1, 24
+; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vor.vv v24, v8, v24, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a1, 24
+; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vor.vv v8, v16, v8, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a1, 24
+; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: vor.vv v16, v24, v16, v0.t
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vor.vv v24, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: lui a0, 61681
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 349525
@@ -2791,26 +3110,25 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64(<vscale x 8 x i64> %va, <vscale
; RV64-NEXT: slli a3, a2, 32
; RV64-NEXT: add a1, a1, a4
; RV64-NEXT: add a2, a2, a3
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
; RV64-NEXT: vor.vv v8, v16, v8, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vand.vx v16, v16, a0, v0.t
; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
; RV64-NEXT: vor.vv v8, v16, v8, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
; RV64-NEXT: vand.vx v8, v8, a1, v0.t
+; RV64-NEXT: vand.vx v16, v16, a1, v0.t
; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
; RV64-NEXT: vor.vv v8, v16, v8, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV64-NEXT: vand.vx v16, v16, a2, v0.t
; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vand.vx v16, v16, a2, v0.t
; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
; RV64-NEXT: vor.vv v8, v16, v8, v0.t
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: li a1, 25
+; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 16
; RV64-NEXT: addi sp, sp, 16
@@ -3009,44 +3327,44 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64_unmasked(<vscale x 8 x i64> %va
define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv64i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: lui a1, 1
-; CHECK-NEXT: lui a2, 3
-; CHECK-NEXT: srli a4, a3, 1
-; CHECK-NEXT: slli a3, a3, 2
+; CHECK-NEXT: lui a3, 3
+; CHECK-NEXT: srli a4, a2, 1
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: vsetvli a5, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a4
-; CHECK-NEXT: sub a4, a0, a3
+; CHECK-NEXT: sub a4, a0, a2
; CHECK-NEXT: sltu a5, a0, a4
; CHECK-NEXT: addi a5, a5, -1
; CHECK-NEXT: and a5, a5, a4
; CHECK-NEXT: lui a6, 5
; CHECK-NEXT: addi a4, a1, -241
-; CHECK-NEXT: addi a2, a2, 819
+; CHECK-NEXT: addi a3, a3, 819
; CHECK-NEXT: addi a1, a6, 1365
; CHECK-NEXT: vsetvli zero, a5, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
; CHECK-NEXT: vsrl.vi v24, v16, 4, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a4, v0.t
; CHECK-NEXT: vand.vx v16, v16, a4, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a4, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: vsrl.vi v24, v16, 2, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a2, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a3, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a3, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: vsrl.vi v24, v16, 1, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 1, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
-; CHECK-NEXT: bltu a0, a3, .LBB46_2
+; CHECK-NEXT: bltu a0, a2, .LBB46_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a3
+; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: .LBB46_2:
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -3054,29 +3372,29 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
; CHECK-NEXT: vor.vv v8, v8, v24, v0.t
; CHECK-NEXT: vsrl.vi v24, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a4, v0.t
; CHECK-NEXT: vand.vx v8, v8, a4, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a4, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
; CHECK-NEXT: vsrl.vi v24, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a2, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a3, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
; CHECK-NEXT: vsrl.vi v24, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv64i16:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
; CHECK-ZVBB-NEXT: csrr a1, vlenb
; CHECK-ZVBB-NEXT: srli a2, a1, 1
; CHECK-ZVBB-NEXT: slli a1, a1, 2
+; CHECK-ZVBB-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
; CHECK-ZVBB-NEXT: sub a2, a0, a1
; CHECK-ZVBB-NEXT: sltu a3, a0, a2
@@ -3182,27 +3500,27 @@ define <vscale x 1 x i9> @vp_bitreverse_nxv1i9(<vscale x 1 x i9> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
-; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: addi a0, a0, -241
+; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, -241
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 7, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
index 0177b8cfd4393..fc2940e1649b2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
@@ -230,9 +230,9 @@ define <vscale x 1 x i32> @vp_bswap_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
; CHECK-NEXT: vor.vv v9, v9, v10, v0.t
; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t
@@ -282,9 +282,9 @@ define <vscale x 2 x i32> @vp_bswap_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
; CHECK-NEXT: vor.vv v9, v9, v10, v0.t
; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t
@@ -334,9 +334,9 @@ define <vscale x 4 x i32> @vp_bswap_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v12, v8, 24, v0.t
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 24, v0.t
; CHECK-NEXT: vor.vv v10, v10, v12, v0.t
; CHECK-NEXT: vand.vx v12, v8, a0, v0.t
; CHECK-NEXT: vsll.vi v12, v12, 8, v0.t
@@ -386,9 +386,9 @@ define <vscale x 8 x i32> @vp_bswap_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v16, v8, 24, v0.t
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vsrl.vi v16, v8, 24, v0.t
; CHECK-NEXT: vor.vv v12, v12, v16, v0.t
; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
@@ -438,9 +438,9 @@ define <vscale x 16 x i32> @vp_bswap_nxv16i32(<vscale x 16 x i32> %va, <vscale x
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vsrl.vi v16, v8, 8, v0.t
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v24, v8, 24, v0.t
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
-; CHECK-NEXT: vsrl.vi v24, v8, 24, v0.t
; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
; CHECK-NEXT: vand.vx v24, v8, a0, v0.t
; CHECK-NEXT: vsll.vi v24, v24, 8, v0.t
@@ -495,32 +495,32 @@ define <vscale x 1 x i64> @vp_bswap_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
; RV32-NEXT: li a4, 40
; RV32-NEXT: lui a5, 4080
; RV32-NEXT: addi a6, sp, 8
+; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; RV32-NEXT: vsrl.vi v9, v8, 24, v0.t
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vsll.vx v9, v8, a2, v0.t
+; RV32-NEXT: vsll.vx v10, v8, a2, v0.t
; RV32-NEXT: addi a0, a3, -256
-; RV32-NEXT: vand.vx v10, v8, a0, v0.t
-; RV32-NEXT: vlse64.v v11, (a6), zero
-; RV32-NEXT: vsll.vx v10, v10, a4, v0.t
-; RV32-NEXT: vor.vv v9, v9, v10, v0.t
-; RV32-NEXT: vand.vx v10, v8, a5, v0.t
-; RV32-NEXT: vsll.vi v10, v10, 24, v0.t
-; RV32-NEXT: vand.vv v12, v8, v11, v0.t
-; RV32-NEXT: vsll.vi v12, v12, 8, v0.t
-; RV32-NEXT: vor.vv v10, v10, v12, v0.t
-; RV32-NEXT: vor.vv v9, v9, v10, v0.t
-; RV32-NEXT: vsrl.vx v10, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v11, v8, a2, v0.t
; RV32-NEXT: vsrl.vx v12, v8, a4, v0.t
+; RV32-NEXT: vand.vx v13, v8, a0, v0.t
; RV32-NEXT: vand.vx v12, v12, a0, v0.t
-; RV32-NEXT: vor.vv v10, v12, v10, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t
-; RV32-NEXT: vand.vx v12, v12, a5, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v11, v0.t
+; RV32-NEXT: vor.vv v11, v12, v11, v0.t
+; RV32-NEXT: vlse64.v v12, (a6), zero
+; RV32-NEXT: vsll.vx v13, v13, a4, v0.t
+; RV32-NEXT: vor.vv v10, v10, v13, v0.t
+; RV32-NEXT: vsrl.vi v13, v8, 8, v0.t
+; RV32-NEXT: vand.vx v9, v9, a5, v0.t
+; RV32-NEXT: vand.vv v13, v13, v12, v0.t
+; RV32-NEXT: vor.vv v9, v13, v9, v0.t
+; RV32-NEXT: vand.vv v12, v8, v12, v0.t
+; RV32-NEXT: vand.vx v8, v8, a5, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 24, v0.t
+; RV32-NEXT: vsll.vi v12, v12, 8, v0.t
; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vor.vv v8, v8, v10, v0.t
-; RV32-NEXT: vor.vv v8, v9, v8, v0.t
+; RV32-NEXT: vor.vv v8, v10, v8, v0.t
+; RV32-NEXT: vor.vv v9, v9, v11, v0.t
+; RV32-NEXT: vor.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
@@ -533,29 +533,29 @@ define <vscale x 1 x i64> @vp_bswap_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
; RV64-NEXT: lui a4, 16
; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV64-NEXT: vand.vx v9, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vsrl.vi v9, v8, 24, v0.t
+; RV64-NEXT: vsrl.vi v10, v8, 8, v0.t
; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v9, v9, 24, v0.t
+; RV64-NEXT: vsrl.vx v11, v8, a3, v0.t
+; RV64-NEXT: vsrl.vx v12, v8, a5, v0.t
+; RV64-NEXT: vand.vx v12, v12, a0, v0.t
+; RV64-NEXT: vor.vv v11, v12, v11, v0.t
+; RV64-NEXT: vand.vx v12, v8, a1, v0.t
+; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vand.vx v9, v9, a1, v0.t
+; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
+; RV64-NEXT: vand.vx v10, v10, a2, v0.t
+; RV64-NEXT: vor.vv v9, v10, v9, v0.t
; RV64-NEXT: vand.vx v10, v8, a2, v0.t
; RV64-NEXT: vsll.vi v10, v10, 8, v0.t
-; RV64-NEXT: vor.vv v9, v9, v10, v0.t
-; RV64-NEXT: vsll.vx v10, v8, a3, v0.t
-; RV64-NEXT: vand.vx v11, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v11, v11, a5, v0.t
-; RV64-NEXT: vor.vv v10, v10, v11, v0.t
-; RV64-NEXT: vor.vv v9, v10, v9, v0.t
-; RV64-NEXT: vsrl.vx v10, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v11, v8, a5, v0.t
-; RV64-NEXT: vand.vx v11, v11, a0, v0.t
-; RV64-NEXT: vor.vv v10, v11, v10, v0.t
-; RV64-NEXT: vsrl.vi v11, v8, 24, v0.t
-; RV64-NEXT: vand.vx v11, v11, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v11, v0.t
+; RV64-NEXT: vor.vv v10, v12, v10, v0.t
+; RV64-NEXT: vsll.vx v12, v8, a3, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsll.vx v8, v8, a5, v0.t
+; RV64-NEXT: vor.vv v8, v12, v8, v0.t
; RV64-NEXT: vor.vv v8, v8, v10, v0.t
-; RV64-NEXT: vor.vv v8, v9, v8, v0.t
+; RV64-NEXT: vor.vv v9, v9, v11, v0.t
+; RV64-NEXT: vor.vv v8, v8, v9, v0.t
; RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv1i64:
@@ -661,32 +661,32 @@ define <vscale x 2 x i64> @vp_bswap_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
; RV32-NEXT: li a4, 40
; RV32-NEXT: lui a5, 4080
; RV32-NEXT: addi a6, sp, 8
+; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; RV32-NEXT: vsrl.vi v10, v8, 24, v0.t
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vsll.vx v10, v8, a2, v0.t
+; RV32-NEXT: vsll.vx v12, v8, a2, v0.t
; RV32-NEXT: addi a0, a3, -256
-; RV32-NEXT: vand.vx v12, v8, a0, v0.t
-; RV32-NEXT: vlse64.v v14, (a6), zero
-; RV32-NEXT: vsll.vx v12, v12, a4, v0.t
-; RV32-NEXT: vor.vv v10, v10, v12, v0.t
-; RV32-NEXT: vand.vx v12, v8, a5, v0.t
-; RV32-NEXT: vsll.vi v12, v12, 24, v0.t
-; RV32-NEXT: vand.vv v16, v8, v14, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v12, v12, v16, v0.t
-; RV32-NEXT: vor.vv v10, v10, v12, v0.t
-; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v14, v8, a2, v0.t
; RV32-NEXT: vsrl.vx v16, v8, a4, v0.t
+; RV32-NEXT: vand.vx v18, v8, a0, v0.t
; RV32-NEXT: vand.vx v16, v16, a0, v0.t
-; RV32-NEXT: vor.vv v12, v16, v12, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV32-NEXT: vand.vx v16, v16, a5, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v14, v0.t
+; RV32-NEXT: vor.vv v14, v16, v14, v0.t
+; RV32-NEXT: vlse64.v v16, (a6), zero
+; RV32-NEXT: vsll.vx v18, v18, a4, v0.t
+; RV32-NEXT: vor.vv v12, v12, v18, v0.t
+; RV32-NEXT: vsrl.vi v18, v8, 8, v0.t
+; RV32-NEXT: vand.vx v10, v10, a5, v0.t
+; RV32-NEXT: vand.vv v18, v18, v16, v0.t
+; RV32-NEXT: vor.vv v10, v18, v10, v0.t
+; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vand.vx v8, v8, a5, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 24, v0.t
+; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vor.vv v8, v10, v8, v0.t
+; RV32-NEXT: vor.vv v8, v12, v8, v0.t
+; RV32-NEXT: vor.vv v10, v10, v14, v0.t
+; RV32-NEXT: vor.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
@@ -699,29 +699,29 @@ define <vscale x 2 x i64> @vp_bswap_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
; RV64-NEXT: lui a4, 16
; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV64-NEXT: vand.vx v10, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vsrl.vi v10, v8, 24, v0.t
+; RV64-NEXT: vsrl.vi v12, v8, 8, v0.t
; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v10, v10, 24, v0.t
+; RV64-NEXT: vsrl.vx v14, v8, a3, v0.t
+; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
+; RV64-NEXT: vand.vx v16, v16, a0, v0.t
+; RV64-NEXT: vor.vv v14, v16, v14, v0.t
+; RV64-NEXT: vand.vx v16, v8, a1, v0.t
+; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vand.vx v10, v10, a1, v0.t
+; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
+; RV64-NEXT: vand.vx v12, v12, a2, v0.t
+; RV64-NEXT: vor.vv v10, v12, v10, v0.t
; RV64-NEXT: vand.vx v12, v8, a2, v0.t
; RV64-NEXT: vsll.vi v12, v12, 8, v0.t
-; RV64-NEXT: vor.vv v10, v10, v12, v0.t
-; RV64-NEXT: vsll.vx v12, v8, a3, v0.t
-; RV64-NEXT: vand.vx v14, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v14, v14, a5, v0.t
-; RV64-NEXT: vor.vv v12, v12, v14, v0.t
-; RV64-NEXT: vor.vv v10, v12, v10, v0.t
-; RV64-NEXT: vsrl.vx v12, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v14, v8, a5, v0.t
-; RV64-NEXT: vand.vx v14, v14, a0, v0.t
-; RV64-NEXT: vor.vv v12, v14, v12, v0.t
-; RV64-NEXT: vsrl.vi v14, v8, 24, v0.t
-; RV64-NEXT: vand.vx v14, v14, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v14, v0.t
+; RV64-NEXT: vor.vv v12, v16, v12, v0.t
+; RV64-NEXT: vsll.vx v16, v8, a3, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsll.vx v8, v8, a5, v0.t
+; RV64-NEXT: vor.vv v8, v16, v8, v0.t
; RV64-NEXT: vor.vv v8, v8, v12, v0.t
-; RV64-NEXT: vor.vv v8, v10, v8, v0.t
+; RV64-NEXT: vor.vv v10, v10, v14, v0.t
+; RV64-NEXT: vor.vv v8, v8, v10, v0.t
; RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv2i64:
@@ -827,32 +827,32 @@ define <vscale x 4 x i64> @vp_bswap_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
; RV32-NEXT: li a4, 40
; RV32-NEXT: lui a5, 4080
; RV32-NEXT: addi a6, sp, 8
+; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
+; RV32-NEXT: vsll.vx v20, v8, a2, v0.t
; RV32-NEXT: addi a0, a3, -256
-; RV32-NEXT: vand.vx v20, v8, a0, v0.t
-; RV32-NEXT: vlse64.v v12, (a6), zero
-; RV32-NEXT: vsll.vx v20, v20, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vand.vx v20, v8, a5, v0.t
-; RV32-NEXT: vsll.vi v20, v20, 24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v12, v0.t
-; RV32-NEXT: vsll.vi v24, v24, 8, v0.t
-; RV32-NEXT: vor.vv v20, v20, v24, v0.t
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vsrl.vx v20, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t
; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
+; RV32-NEXT: vand.vx v28, v8, a0, v0.t
; RV32-NEXT: vand.vx v24, v24, a0, v0.t
-; RV32-NEXT: vor.vv v20, v24, v20, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a5, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
+; RV32-NEXT: vor.vv v12, v24, v12, v0.t
+; RV32-NEXT: vlse64.v v24, (a6), zero
+; RV32-NEXT: vsll.vx v28, v28, a4, v0.t
+; RV32-NEXT: vor.vv v20, v20, v28, v0.t
+; RV32-NEXT: vsrl.vi v28, v8, 8, v0.t
+; RV32-NEXT: vand.vx v16, v16, a5, v0.t
+; RV32-NEXT: vand.vv v28, v28, v24, v0.t
+; RV32-NEXT: vor.vv v16, v28, v16, v0.t
+; RV32-NEXT: vand.vv v24, v8, v24, v0.t
+; RV32-NEXT: vand.vx v8, v8, a5, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 24, v0.t
+; RV32-NEXT: vsll.vi v24, v24, 8, v0.t
; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vor.vv v8, v8, v20, v0.t
-; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vor.vv v8, v20, v8, v0.t
+; RV32-NEXT: vor.vv v12, v16, v12, v0.t
+; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
@@ -865,29 +865,29 @@ define <vscale x 4 x i64> @vp_bswap_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
; RV64-NEXT: lui a4, 16
; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV64-NEXT: vand.vx v12, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
+; RV64-NEXT: vsrl.vi v20, v8, 8, v0.t
; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
-; RV64-NEXT: vand.vx v16, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV64-NEXT: vor.vv v12, v12, v16, v0.t
-; RV64-NEXT: vsll.vx v16, v8, a3, v0.t
-; RV64-NEXT: vand.vx v20, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v20, v20, a5, v0.t
-; RV64-NEXT: vor.vv v16, v16, v20, v0.t
-; RV64-NEXT: vor.vv v12, v16, v12, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v20, v8, a5, v0.t
-; RV64-NEXT: vand.vx v20, v20, a0, v0.t
+; RV64-NEXT: vsrl.vx v12, v8, a3, v0.t
+; RV64-NEXT: vsrl.vx v24, v8, a5, v0.t
+; RV64-NEXT: vand.vx v24, v24, a0, v0.t
+; RV64-NEXT: vor.vv v12, v24, v12, v0.t
+; RV64-NEXT: vand.vx v24, v8, a1, v0.t
+; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vand.vx v16, v16, a1, v0.t
+; RV64-NEXT: vsll.vi v24, v24, 24, v0.t
+; RV64-NEXT: vand.vx v20, v20, a2, v0.t
; RV64-NEXT: vor.vv v16, v20, v16, v0.t
-; RV64-NEXT: vsrl.vi v20, v8, 24, v0.t
-; RV64-NEXT: vand.vx v20, v20, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vand.vx v20, v8, a2, v0.t
+; RV64-NEXT: vsll.vi v20, v20, 8, v0.t
+; RV64-NEXT: vor.vv v20, v24, v20, v0.t
+; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsll.vx v8, v8, a5, v0.t
+; RV64-NEXT: vor.vv v8, v24, v8, v0.t
; RV64-NEXT: vor.vv v8, v8, v20, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v12, v8, v0.t
+; RV64-NEXT: vor.vv v12, v16, v12, v0.t
+; RV64-NEXT: vor.vv v8, v8, v12, v0.t
; RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv4i64:
@@ -988,75 +988,132 @@ define <vscale x 7 x i64> @vp_bswap_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a2, a1, 5
+; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: addi a5, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
-; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: lui a2, 16
+; RV32-NEXT: li a3, 40
+; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV32-NEXT: addi a0, a3, -256
-; RV32-NEXT: vand.vx v24, v8, a0, v0.t
-; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vlse64.v v16, (a5), zero
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a1, 4080
-; RV32-NEXT: vand.vx v16, v8, a1, v0.t
-; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: vsrl.vx v24, v8, a3, v0.t
+; RV32-NEXT: vand.vx v24, v24, a2, v0.t
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a0, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vs1r.v v0, (a0) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vand.vx v16, v8, a2, v0.t
+; RV32-NEXT: vsll.vx v16, v16, a3, v0.t
+; RV32-NEXT: vsll.vx v24, v8, a1, v0.t
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: lui a1, 4080
+; RV32-NEXT: addi a2, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: vlse64.v v16, (a2), zero
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 24
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vx v16, v24, a1, v0.t
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 24
+; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vor.vv v24, v24, v16, v0.t
+; RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vx v24, v8, a1, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 24
+; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
@@ -1064,8 +1121,22 @@ define <vscale x 7 x i64> @vp_bswap_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a1, a0, 5
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
; RV32-NEXT: addi sp, sp, 16
@@ -1077,46 +1148,121 @@ define <vscale x 7 x i64> @vp_bswap_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: slli a2, a1, 4
+; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
+; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
+; RV64-NEXT: lui a2, 4080
+; RV64-NEXT: li a3, 255
+; RV64-NEXT: li a1, 56
; RV64-NEXT: lui a4, 16
; RV64-NEXT: li a5, 40
+; RV64-NEXT: addi a4, a4, -256
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
+; RV64-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV64-NEXT: vsrl.vx v24, v8, a5, v0.t
+; RV64-NEXT: vand.vx v24, v24, a4, v0.t
+; RV64-NEXT: vor.vv v16, v24, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs1r.v v0, (a0) # vscale x 8-byte Folded Spill
+; RV64-NEXT: vsrl.vi v24, v8, 24, v0.t
+; RV64-NEXT: slli a3, a3, 24
+; RV64-NEXT: vand.vx v24, v24, a2, v0.t
+; RV64-NEXT: vsrl.vi v16, v8, 8, v0.t
+; RV64-NEXT: vand.vx v16, v16, a3, v0.t
+; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v16, v8, a2, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v24, v8, a3, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
-; RV64-NEXT: vand.vx v16, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v16, v16, a5, v0.t
-; RV64-NEXT: vor.vv v16, v24, v16, v0.t
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vor.vv v24, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v24, v8, a4, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsll.vx v24, v24, a5, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsll.vx v8, v8, a1, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vor.vv v8, v8, v16, v0.t
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vor.vv v16, v24, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vor.vv v8, v8, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a1, a0, 4
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 16
; RV64-NEXT: addi sp, sp, 16
@@ -1258,75 +1404,132 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a2, a1, 5
+; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: addi a5, sp, 8
-; RV32-NEXT: sw a1, 8(sp)
-; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: lui a2, 16
+; RV32-NEXT: li a3, 40
+; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV32-NEXT: addi a0, a3, -256
-; RV32-NEXT: vand.vx v24, v8, a0, v0.t
-; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vlse64.v v16, (a5), zero
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a1, 4080
-; RV32-NEXT: vand.vx v16, v8, a1, v0.t
-; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: vsrl.vx v24, v8, a3, v0.t
+; RV32-NEXT: vand.vx v24, v24, a2, v0.t
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a0, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vs1r.v v0, (a0) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vand.vx v16, v8, a2, v0.t
+; RV32-NEXT: vsll.vx v16, v16, a3, v0.t
+; RV32-NEXT: vsll.vx v24, v8, a1, v0.t
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: lui a0, 1044480
+; RV32-NEXT: lui a1, 4080
+; RV32-NEXT: addi a2, sp, 8
+; RV32-NEXT: sw a0, 8(sp)
+; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: vlse64.v v16, (a2), zero
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 24
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vx v16, v24, a1, v0.t
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 24
+; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vor.vv v24, v24, v16, v0.t
+; RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vx v24, v8, a1, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 24
+; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
@@ -1334,8 +1537,22 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a1, a0, 5
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
; RV32-NEXT: addi sp, sp, 16
@@ -1347,46 +1564,121 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: slli a2, a1, 4
+; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
+; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
+; RV64-NEXT: lui a2, 4080
+; RV64-NEXT: li a3, 255
+; RV64-NEXT: li a1, 56
; RV64-NEXT: lui a4, 16
; RV64-NEXT: li a5, 40
+; RV64-NEXT: addi a4, a4, -256
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
+; RV64-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV64-NEXT: vsrl.vx v24, v8, a5, v0.t
+; RV64-NEXT: vand.vx v24, v24, a4, v0.t
+; RV64-NEXT: vor.vv v16, v24, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs1r.v v0, (a0) # vscale x 8-byte Folded Spill
+; RV64-NEXT: vsrl.vi v24, v8, 24, v0.t
+; RV64-NEXT: slli a3, a3, 24
+; RV64-NEXT: vand.vx v24, v24, a2, v0.t
+; RV64-NEXT: vsrl.vi v16, v8, 8, v0.t
+; RV64-NEXT: vand.vx v16, v16, a3, v0.t
+; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v16, v8, a2, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v24, v8, a3, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
-; RV64-NEXT: vand.vx v16, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v16, v16, a5, v0.t
-; RV64-NEXT: vor.vv v16, v24, v16, v0.t
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vor.vv v24, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v24, v8, a4, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsll.vx v24, v24, a5, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsll.vx v8, v8, a1, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vor.vv v8, v8, v16, v0.t
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vor.vv v16, v24, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vor.vv v8, v8, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a1, a0, 4
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 16
; RV64-NEXT: addi sp, sp, 16
@@ -1527,11 +1819,11 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32
define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv64i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1
; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2
@@ -1554,11 +1846,11 @@ define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv64i16:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-ZVKB-NEXT: vmv1r.v v24, v0
; CHECK-ZVKB-NEXT: csrr a1, vlenb
; CHECK-ZVKB-NEXT: srli a2, a1, 1
; CHECK-ZVKB-NEXT: slli a1, a1, 2
+; CHECK-ZVKB-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-ZVKB-NEXT: vmv1r.v v24, v0
; CHECK-ZVKB-NEXT: vslidedown.vx v0, v0, a2
; CHECK-ZVKB-NEXT: sub a2, a0, a1
; CHECK-ZVKB-NEXT: sltu a3, a0, a2
@@ -1634,32 +1926,32 @@ define <vscale x 1 x i48> @vp_bswap_nxv1i48(<vscale x 1 x i48> %va, <vscale x 1
; RV32-NEXT: li a4, 40
; RV32-NEXT: lui a5, 4080
; RV32-NEXT: addi a6, sp, 8
+; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; RV32-NEXT: vsrl.vi v9, v8, 24, v0.t
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vsll.vx v9, v8, a2, v0.t
+; RV32-NEXT: vsll.vx v10, v8, a2, v0.t
; RV32-NEXT: addi a0, a3, -256
-; RV32-NEXT: vand.vx v10, v8, a0, v0.t
-; RV32-NEXT: vlse64.v v11, (a6), zero
-; RV32-NEXT: vsll.vx v10, v10, a4, v0.t
-; RV32-NEXT: vor.vv v9, v9, v10, v0.t
-; RV32-NEXT: vand.vx v10, v8, a5, v0.t
-; RV32-NEXT: vsll.vi v10, v10, 24, v0.t
-; RV32-NEXT: vand.vv v12, v8, v11, v0.t
-; RV32-NEXT: vsll.vi v12, v12, 8, v0.t
-; RV32-NEXT: vor.vv v10, v10, v12, v0.t
-; RV32-NEXT: vor.vv v9, v9, v10, v0.t
-; RV32-NEXT: vsrl.vx v10, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v11, v8, a2, v0.t
; RV32-NEXT: vsrl.vx v12, v8, a4, v0.t
+; RV32-NEXT: vand.vx v13, v8, a0, v0.t
; RV32-NEXT: vand.vx v12, v12, a0, v0.t
-; RV32-NEXT: vor.vv v10, v12, v10, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t
-; RV32-NEXT: vand.vx v12, v12, a5, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v11, v0.t
+; RV32-NEXT: vor.vv v11, v12, v11, v0.t
+; RV32-NEXT: vlse64.v v12, (a6), zero
+; RV32-NEXT: vsll.vx v13, v13, a4, v0.t
+; RV32-NEXT: vor.vv v10, v10, v13, v0.t
+; RV32-NEXT: vsrl.vi v13, v8, 8, v0.t
+; RV32-NEXT: vand.vx v9, v9, a5, v0.t
+; RV32-NEXT: vand.vv v13, v13, v12, v0.t
+; RV32-NEXT: vor.vv v9, v13, v9, v0.t
+; RV32-NEXT: vand.vv v12, v8, v12, v0.t
+; RV32-NEXT: vand.vx v8, v8, a5, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 24, v0.t
+; RV32-NEXT: vsll.vi v12, v12, 8, v0.t
; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vor.vv v8, v8, v10, v0.t
-; RV32-NEXT: vor.vv v8, v9, v8, v0.t
+; RV32-NEXT: vor.vv v8, v10, v8, v0.t
+; RV32-NEXT: vor.vv v9, v9, v11, v0.t
+; RV32-NEXT: vor.vv v8, v8, v9, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 16, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
@@ -1673,29 +1965,29 @@ define <vscale x 1 x i48> @vp_bswap_nxv1i48(<vscale x 1 x i48> %va, <vscale x 1
; RV64-NEXT: lui a4, 16
; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV64-NEXT: vand.vx v9, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vsrl.vi v9, v8, 24, v0.t
+; RV64-NEXT: vsrl.vi v10, v8, 8, v0.t
; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v9, v9, 24, v0.t
+; RV64-NEXT: vsrl.vx v11, v8, a3, v0.t
+; RV64-NEXT: vsrl.vx v12, v8, a5, v0.t
+; RV64-NEXT: vand.vx v12, v12, a0, v0.t
+; RV64-NEXT: vor.vv v11, v12, v11, v0.t
+; RV64-NEXT: vand.vx v12, v8, a1, v0.t
+; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vand.vx v9, v9, a1, v0.t
+; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
+; RV64-NEXT: vand.vx v10, v10, a2, v0.t
+; RV64-NEXT: vor.vv v9, v10, v9, v0.t
; RV64-NEXT: vand.vx v10, v8, a2, v0.t
; RV64-NEXT: vsll.vi v10, v10, 8, v0.t
-; RV64-NEXT: vor.vv v9, v9, v10, v0.t
-; RV64-NEXT: vsll.vx v10, v8, a3, v0.t
-; RV64-NEXT: vand.vx v11, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v11, v11, a5, v0.t
-; RV64-NEXT: vor.vv v10, v10, v11, v0.t
-; RV64-NEXT: vor.vv v9, v10, v9, v0.t
-; RV64-NEXT: vsrl.vx v10, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v11, v8, a5, v0.t
-; RV64-NEXT: vand.vx v11, v11, a0, v0.t
-; RV64-NEXT: vor.vv v10, v11, v10, v0.t
-; RV64-NEXT: vsrl.vi v11, v8, 24, v0.t
-; RV64-NEXT: vand.vx v11, v11, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v11, v0.t
+; RV64-NEXT: vor.vv v10, v12, v10, v0.t
+; RV64-NEXT: vsll.vx v12, v8, a3, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsll.vx v8, v8, a5, v0.t
+; RV64-NEXT: vor.vv v8, v12, v8, v0.t
; RV64-NEXT: vor.vv v8, v8, v10, v0.t
-; RV64-NEXT: vor.vv v8, v9, v8, v0.t
+; RV64-NEXT: vor.vv v9, v9, v11, v0.t
+; RV64-NEXT: vor.vv v8, v8, v9, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 16, v0.t
; RV64-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
index 00fef2e6304ce..b84878f227a7a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
@@ -16,26 +16,24 @@ define <vscale x 1 x bfloat> @vp_ceil_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vs
; CHECK-LABEL: vp_ceil_vv_nxv1bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfabs.v v11, v10, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 3
-; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
-; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 1 x bfloat> @llvm.vp.ceil.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x bfloat> %v
@@ -47,11 +45,11 @@ define <vscale x 1 x bfloat> @vp_ceil_vv_nxv1bf16_unmasked(<vscale x 1 x bfloat>
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -68,26 +66,24 @@ define <vscale x 2 x bfloat> @vp_ceil_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vs
; CHECK-LABEL: vp_ceil_vv_nxv2bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfabs.v v11, v10, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 3
-; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
-; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 2 x bfloat> @llvm.vp.ceil.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x bfloat> %v
@@ -99,11 +95,11 @@ define <vscale x 2 x bfloat> @vp_ceil_vv_nxv2bf16_unmasked(<vscale x 2 x bfloat>
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -123,21 +119,21 @@ define <vscale x 4 x bfloat> @vp_ceil_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vs
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v8, v10, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v13, v8, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fsrmi a0, 3
-; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
; CHECK-NEXT: ret
@@ -151,11 +147,11 @@ define <vscale x 4 x bfloat> @vp_ceil_vv_nxv4bf16_unmasked(<vscale x 4 x bfloat>
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v8, v10
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -175,21 +171,21 @@ define <vscale x 8 x bfloat> @vp_ceil_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vs
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v17, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfabs.v v8, v12, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v17, v8, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v17, v0
; CHECK-NEXT: fsrmi a0, 3
-; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
; CHECK-NEXT: ret
@@ -203,11 +199,11 @@ define <vscale x 8 x bfloat> @vp_ceil_vv_nxv8bf16_unmasked(<vscale x 8 x bfloat>
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfabs.v v8, v12
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -227,21 +223,21 @@ define <vscale x 16 x bfloat> @vp_ceil_vv_nxv16bf16(<vscale x 16 x bfloat> %va,
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v8, v16, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v24, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fsrmi a0, 3
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vfsgnj.vv v16, v8, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: ret
@@ -255,11 +251,11 @@ define <vscale x 16 x bfloat> @vp_ceil_vv_nxv16bf16_unmasked(<vscale x 16 x bflo
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v8, v16
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -285,50 +281,50 @@ define <vscale x 32 x bfloat> @vp_ceil_vv_nxv32bf16(<vscale x 32 x bfloat> %va,
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vslidedown.vx v6, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: vmv1r.v v5, v6
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v5, v16, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: fsrmi a2, 3
-; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a2
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB10_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB10_2:
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t
-; CHECK-NEXT: vmv1r.v v8, v7
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v16, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: fsrmi a0, 3
-; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a0
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 32 x bfloat> @llvm.vp.ceil.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x bfloat> %v
@@ -348,37 +344,37 @@ define <vscale x 32 x bfloat> @vp_ceil_vv_nxv32bf16_unmasked(<vscale x 32 x bflo
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v7, v16, a2
; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: vmv1r.v v6, v7
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v6, v16, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: fsrmi a2, 3
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a2
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB11_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB11_2:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v24, v16
; CHECK-NEXT: vmflt.vf v0, v24, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -399,9 +395,9 @@ define <vscale x 1 x half> @vp_ceil_vv_nxv1f16(<vscale x 1 x half> %va, <vscale
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 3
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 3
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -413,26 +409,24 @@ define <vscale x 1 x half> @vp_ceil_vv_nxv1f16(<vscale x 1 x half> %va, <vscale
; ZVFHMIN-LABEL: vp_ceil_vv_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 3
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x half> @llvm.vp.ceil.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x half> %v
@@ -446,8 +440,8 @@ define <vscale x 1 x half> @vp_ceil_vv_nxv1f16_unmasked(<vscale x 1 x half> %va,
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 3
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -460,11 +454,11 @@ define <vscale x 1 x half> @vp_ceil_vv_nxv1f16_unmasked(<vscale x 1 x half> %va,
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -485,9 +479,9 @@ define <vscale x 2 x half> @vp_ceil_vv_nxv2f16(<vscale x 2 x half> %va, <vscale
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 3
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 3
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -499,26 +493,24 @@ define <vscale x 2 x half> @vp_ceil_vv_nxv2f16(<vscale x 2 x half> %va, <vscale
; ZVFHMIN-LABEL: vp_ceil_vv_nxv2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 3
-; ZVFHMIN-NEXT: vmv.v.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 2 x half> @llvm.vp.ceil.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x half> %v
@@ -532,8 +524,8 @@ define <vscale x 2 x half> @vp_ceil_vv_nxv2f16_unmasked(<vscale x 2 x half> %va,
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 3
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -546,11 +538,11 @@ define <vscale x 2 x half> @vp_ceil_vv_nxv2f16_unmasked(<vscale x 2 x half> %va,
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -571,9 +563,9 @@ define <vscale x 4 x half> @vp_ceil_vv_nxv4f16(<vscale x 4 x half> %va, <vscale
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 3
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 3
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -588,21 +580,21 @@ define <vscale x 4 x half> @vp_ceil_vv_nxv4f16(<vscale x 4 x half> %va, <vscale
; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v13, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: fsrmi a0, 3
-; ZVFHMIN-NEXT: vmv1r.v v0, v13
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
+; ZVFHMIN-NEXT: vmv1r.v v0, v13
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: ret
@@ -618,8 +610,8 @@ define <vscale x 4 x half> @vp_ceil_vv_nxv4f16_unmasked(<vscale x 4 x half> %va,
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 3
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -632,11 +624,11 @@ define <vscale x 4 x half> @vp_ceil_vv_nxv4f16_unmasked(<vscale x 4 x half> %va,
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -676,21 +668,21 @@ define <vscale x 8 x half> @vp_ceil_vv_nxv8f16(<vscale x 8 x half> %va, <vscale
; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: fsrmi a0, 3
-; ZVFHMIN-NEXT: vmv1r.v v0, v17
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vmv1r.v v0, v17
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
@@ -706,8 +698,8 @@ define <vscale x 8 x half> @vp_ceil_vv_nxv8f16_unmasked(<vscale x 8 x half> %va,
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 3
+; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -720,11 +712,11 @@ define <vscale x 8 x half> @vp_ceil_vv_nxv8f16_unmasked(<vscale x 8 x half> %va,
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -764,21 +756,21 @@ define <vscale x 16 x half> @vp_ceil_vv_nxv16f16(<vscale x 16 x half> %va, <vsca
; ZVFHMIN-NEXT: vmv1r.v v24, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v25, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v16, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v25, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v24, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v25, v0
; ZVFHMIN-NEXT: fsrmi a0, 3
-; ZVFHMIN-NEXT: vmv1r.v v0, v25
+; ZVFHMIN-NEXT: vmv1r.v v0, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v24
+; ZVFHMIN-NEXT: vmv1r.v v0, v25
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
@@ -794,8 +786,8 @@ define <vscale x 16 x half> @vp_ceil_vv_nxv16f16_unmasked(<vscale x 16 x half> %
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: fsrmi a0, 3
+; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -808,11 +800,11 @@ define <vscale x 16 x half> @vp_ceil_vv_nxv16f16_unmasked(<vscale x 16 x half> %
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v16
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -858,50 +850,50 @@ define <vscale x 32 x half> @vp_ceil_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: vmv1r.v v5, v6
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v5, v16, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: fsrmi a2, 3
-; ZVFHMIN-NEXT: vmv1r.v v0, v5
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a2
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB22_2:
; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v8, v7
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v16, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v8, v0
; ZVFHMIN-NEXT: fsrmi a0, 3
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 32 x half> @llvm.vp.ceil.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x half> %v
@@ -915,8 +907,8 @@ define <vscale x 32 x half> @vp_ceil_vv_nxv32f16_unmasked(<vscale x 32 x half> %
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: fsrmi a0, 3
+; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -937,37 +929,37 @@ define <vscale x 32 x half> @vp_ceil_vv_nxv32f16_unmasked(<vscale x 32 x half> %
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v7, v16, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: vmv1r.v v6, v7
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v6, v16, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: fsrmi a2, 3
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a2
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB23_2:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v24, v16
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -987,9 +979,9 @@ define <vscale x 1 x float> @vp_ceil_vv_nxv1f32(<vscale x 1 x float> %va, <vscal
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -1008,8 +1000,8 @@ define <vscale x 1 x float> @vp_ceil_vv_nxv1f32_unmasked(<vscale x 1 x float> %v
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1027,9 +1019,9 @@ define <vscale x 2 x float> @vp_ceil_vv_nxv2f32(<vscale x 2 x float> %va, <vscal
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -1048,8 +1040,8 @@ define <vscale x 2 x float> @vp_ceil_vv_nxv2f32_unmasked(<vscale x 2 x float> %v
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1090,8 +1082,8 @@ define <vscale x 4 x float> @vp_ceil_vv_nxv4f32_unmasked(<vscale x 4 x float> %v
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1132,8 +1124,8 @@ define <vscale x 8 x float> @vp_ceil_vv_nxv8f32_unmasked(<vscale x 8 x float> %v
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1174,8 +1166,8 @@ define <vscale x 16 x float> @vp_ceil_vv_nxv16f32_unmasked(<vscale x 16 x float>
; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1193,9 +1185,9 @@ define <vscale x 1 x double> @vp_ceil_vv_nxv1f64(<vscale x 1 x double> %va, <vsc
; RV32ZFH-NEXT: fld fa5, %lo(.LCPI34_0)(a1)
; RV32ZFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZFH-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZFH-NEXT: fsrmi a0, 3
; RV32ZFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZFH-NEXT: fsrmi a0, 3
; RV32ZFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZFH-NEXT: fsrm a0
@@ -1211,9 +1203,9 @@ define <vscale x 1 x double> @vp_ceil_vv_nxv1f64(<vscale x 1 x double> %va, <vsc
; RV64ZFH-NEXT: li a0, 1075
; RV64ZFH-NEXT: slli a0, a0, 52
; RV64ZFH-NEXT: fmv.d.x fa5, a0
+; RV64ZFH-NEXT: fsrmi a0, 3
; RV64ZFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZFH-NEXT: fsrmi a0, 3
; RV64ZFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZFH-NEXT: fsrm a0
@@ -1232,8 +1224,8 @@ define <vscale x 1 x double> @vp_ceil_vv_nxv1f64_unmasked(<vscale x 1 x double>
; RV32ZFH-NEXT: fld fa5, %lo(.LCPI35_0)(a1)
; RV32ZFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZFH-NEXT: vfabs.v v9, v8
-; RV32ZFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZFH-NEXT: fsrmi a0, 3
+; RV32ZFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZFH-NEXT: fsrm a0
; RV32ZFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1248,8 +1240,8 @@ define <vscale x 1 x double> @vp_ceil_vv_nxv1f64_unmasked(<vscale x 1 x double>
; RV64ZFH-NEXT: li a0, 1075
; RV64ZFH-NEXT: slli a0, a0, 52
; RV64ZFH-NEXT: fmv.d.x fa5, a0
-; RV64ZFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZFH-NEXT: fsrmi a0, 3
+; RV64ZFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZFH-NEXT: fsrm a0
; RV64ZFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1310,8 +1302,8 @@ define <vscale x 2 x double> @vp_ceil_vv_nxv2f64_unmasked(<vscale x 2 x double>
; RV32ZFH-NEXT: fld fa5, %lo(.LCPI37_0)(a1)
; RV32ZFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZFH-NEXT: vfabs.v v10, v8
-; RV32ZFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZFH-NEXT: fsrmi a0, 3
+; RV32ZFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZFH-NEXT: fsrm a0
; RV32ZFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1326,8 +1318,8 @@ define <vscale x 2 x double> @vp_ceil_vv_nxv2f64_unmasked(<vscale x 2 x double>
; RV64ZFH-NEXT: li a0, 1075
; RV64ZFH-NEXT: slli a0, a0, 52
; RV64ZFH-NEXT: fmv.d.x fa5, a0
-; RV64ZFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZFH-NEXT: fsrmi a0, 3
+; RV64ZFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZFH-NEXT: fsrm a0
; RV64ZFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1388,8 +1380,8 @@ define <vscale x 4 x double> @vp_ceil_vv_nxv4f64_unmasked(<vscale x 4 x double>
; RV32ZFH-NEXT: fld fa5, %lo(.LCPI39_0)(a1)
; RV32ZFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZFH-NEXT: vfabs.v v12, v8
-; RV32ZFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZFH-NEXT: fsrmi a0, 3
+; RV32ZFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZFH-NEXT: fsrm a0
; RV32ZFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1404,8 +1396,8 @@ define <vscale x 4 x double> @vp_ceil_vv_nxv4f64_unmasked(<vscale x 4 x double>
; RV64ZFH-NEXT: li a0, 1075
; RV64ZFH-NEXT: slli a0, a0, 52
; RV64ZFH-NEXT: fmv.d.x fa5, a0
-; RV64ZFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZFH-NEXT: fsrmi a0, 3
+; RV64ZFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZFH-NEXT: fsrm a0
; RV64ZFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1466,8 +1458,8 @@ define <vscale x 7 x double> @vp_ceil_vv_nxv7f64_unmasked(<vscale x 7 x double>
; RV32ZFH-NEXT: fld fa5, %lo(.LCPI41_0)(a1)
; RV32ZFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZFH-NEXT: vfabs.v v16, v8
-; RV32ZFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZFH-NEXT: fsrmi a0, 3
+; RV32ZFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZFH-NEXT: fsrm a0
; RV32ZFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1482,8 +1474,8 @@ define <vscale x 7 x double> @vp_ceil_vv_nxv7f64_unmasked(<vscale x 7 x double>
; RV64ZFH-NEXT: li a0, 1075
; RV64ZFH-NEXT: slli a0, a0, 52
; RV64ZFH-NEXT: fmv.d.x fa5, a0
-; RV64ZFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZFH-NEXT: fsrmi a0, 3
+; RV64ZFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZFH-NEXT: fsrm a0
; RV64ZFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1544,8 +1536,8 @@ define <vscale x 8 x double> @vp_ceil_vv_nxv8f64_unmasked(<vscale x 8 x double>
; RV32ZFH-NEXT: fld fa5, %lo(.LCPI43_0)(a1)
; RV32ZFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZFH-NEXT: vfabs.v v16, v8
-; RV32ZFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZFH-NEXT: fsrmi a0, 3
+; RV32ZFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZFH-NEXT: fsrm a0
; RV32ZFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1560,8 +1552,8 @@ define <vscale x 8 x double> @vp_ceil_vv_nxv8f64_unmasked(<vscale x 8 x double>
; RV64ZFH-NEXT: li a0, 1075
; RV64ZFH-NEXT: slli a0, a0, 52
; RV64ZFH-NEXT: fmv.d.x fa5, a0
-; RV64ZFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZFH-NEXT: fsrmi a0, 3
+; RV64ZFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZFH-NEXT: fsrm a0
; RV64ZFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1587,8 +1579,8 @@ define <vscale x 16 x double> @vp_ceil_vv_nxv16f64(<vscale x 16 x double> %va, <
; RV32ZFH-NEXT: vslidedown.vx v6, v0, a3
; RV32ZFH-NEXT: sltu a3, a0, a2
; RV32ZFH-NEXT: addi a3, a3, -1
-; RV32ZFH-NEXT: and a2, a3, a2
; RV32ZFH-NEXT: vmv1r.v v0, v6
+; RV32ZFH-NEXT: and a2, a3, a2
; RV32ZFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZFH-NEXT: vfabs.v v24, v16, v0.t
; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -1633,8 +1625,8 @@ define <vscale x 16 x double> @vp_ceil_vv_nxv16f64(<vscale x 16 x double> %va, <
; RV64ZFH-NEXT: fmv.d.x fa5, a2
; RV64ZFH-NEXT: sltu a2, a0, a3
; RV64ZFH-NEXT: addi a2, a2, -1
-; RV64ZFH-NEXT: and a2, a2, a3
; RV64ZFH-NEXT: vmv1r.v v0, v6
+; RV64ZFH-NEXT: and a2, a2, a3
; RV64ZFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZFH-NEXT: vfabs.v v24, v16, v0.t
; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -1679,12 +1671,12 @@ define <vscale x 16 x double> @vp_ceil_vv_nxv16f64_unmasked(<vscale x 16 x doubl
; RV32ZFH-NEXT: sltu a2, a0, a3
; RV32ZFH-NEXT: addi a2, a2, -1
; RV32ZFH-NEXT: and a2, a2, a3
+; RV32ZFH-NEXT: fsrmi a3, 3
; RV32ZFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZFH-NEXT: vfabs.v v24, v16
; RV32ZFH-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZFH-NEXT: fsrmi a2, 3
; RV32ZFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZFH-NEXT: fsrm a2
+; RV32ZFH-NEXT: fsrm a3
; RV32ZFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1694,8 +1686,8 @@ define <vscale x 16 x double> @vp_ceil_vv_nxv16f64_unmasked(<vscale x 16 x doubl
; RV32ZFH-NEXT: .LBB45_2:
; RV32ZFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZFH-NEXT: vfabs.v v24, v8
-; RV32ZFH-NEXT: vmflt.vf v0, v24, fa5
; RV32ZFH-NEXT: fsrmi a0, 3
+; RV32ZFH-NEXT: vmflt.vf v0, v24, fa5
; RV32ZFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV32ZFH-NEXT: fsrm a0
; RV32ZFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -1713,12 +1705,12 @@ define <vscale x 16 x double> @vp_ceil_vv_nxv16f64_unmasked(<vscale x 16 x doubl
; RV64ZFH-NEXT: sltu a2, a0, a3
; RV64ZFH-NEXT: addi a2, a2, -1
; RV64ZFH-NEXT: and a2, a2, a3
+; RV64ZFH-NEXT: fsrmi a3, 3
; RV64ZFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZFH-NEXT: vfabs.v v24, v16
; RV64ZFH-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZFH-NEXT: fsrmi a2, 3
; RV64ZFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZFH-NEXT: fsrm a2
+; RV64ZFH-NEXT: fsrm a3
; RV64ZFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1728,8 +1720,8 @@ define <vscale x 16 x double> @vp_ceil_vv_nxv16f64_unmasked(<vscale x 16 x doubl
; RV64ZFH-NEXT: .LBB45_2:
; RV64ZFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64ZFH-NEXT: vfabs.v v24, v8
-; RV64ZFH-NEXT: vmflt.vf v0, v24, fa5
; RV64ZFH-NEXT: fsrmi a0, 3
+; RV64ZFH-NEXT: vmflt.vf v0, v24, fa5
; RV64ZFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV64ZFH-NEXT: fsrm a0
; RV64ZFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll b/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
index 96252f070a580..acc1c794c5e94 100644
--- a/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
@@ -95,81 +95,156 @@ define i32 @test_v256i1(<256 x i1> %x) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 2
+; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: slli a0, a0, 2
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v8
-; CHECK-NEXT: vmv1r.v v6, v0
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x14, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 20 * vlenb
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs1r.v v0, (a0) # vscale x 8-byte Folded Spill
; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vslidedown.vi v5, v8, 8
-; CHECK-NEXT: vslidedown.vi v4, v0, 8
-; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v5, 4
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
+; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v4, 4
+; CHECK-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vslidedown.vi v8, v8, 8
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v8, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vslidedown.vi v8, v8, 8
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a2, a1, 4
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
+; CHECK-NEXT: vadd.vv v16, v24, v16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a2, a1, 3
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a2, a1, 4
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT: vadd.vv v16, v16, v24
; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v16, (a1) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v7, 4
+; CHECK-NEXT: vslidedown.vi v0, v16, 4
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v16, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vslidedown.vi v24, v16, 4
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
-; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v6, 4
+; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
+; CHECK-NEXT: vadd.vv v16, v24, v16
; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl1r.v v24, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v24, 4
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a2, a1, 4
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v24, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vslidedown.vi v7, v24, 4
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vadd.vv v16, v16, v24
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
-; CHECK-NEXT: vadd.vv v8, v24, v8
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v5
-; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v4
-; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
-; CHECK-NEXT: vadd.vv v8, v24, v8
+; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
-; CHECK-NEXT: vadd.vv v16, v16, v24
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vadd.vv v8, v8, v24
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vv v24, v0, v24
+; CHECK-NEXT: vadd.vv v24, v24, v0
; CHECK-NEXT: vadd.vv v8, v16, v8
-; CHECK-NEXT: vadd.vv v8, v8, v24
+; CHECK-NEXT: vadd.vv v8, v24, v8
; CHECK-NEXT: vmv.s.x v16, zero
; CHECK-NEXT: vredsum.vs v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add sp, sp, a1
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -284,62 +359,46 @@ entry:
define i32 @test_nxv128i1(<vscale x 128 x i1> %x) {
; CHECK-LABEL: test_nxv128i1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v8
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmv1r.v v24, v8
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
-; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
; CHECK-NEXT: srli a1, a0, 1
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a1
+; CHECK-NEXT: vslidedown.vx v6, v24, a1
+; CHECK-NEXT: vslidedown.vx v5, v0, a1
+; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
+; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
+; CHECK-NEXT: vmv1r.v v4, v24
+; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
+; CHECK-NEXT: vadd.vv v16, v16, v24
; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vmv8r.v v8, v16
-; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a0
-; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v6, a0
-; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v6, v7, a1
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v7, a0
-; CHECK-NEXT: vslidedown.vx v5, v6, a0
+; CHECK-NEXT: vslidedown.vx v7, v5, a0
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v4, a0
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
+; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v6, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v5
-; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
-; CHECK-NEXT: vadd.vv v8, v8, v16
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
-; CHECK-NEXT: vadd.vv v16, v16, v24
+; CHECK-NEXT: vadd.vv v8, v24, v8
; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vmv.s.x v16, zero
; CHECK-NEXT: vredsum.vs v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add sp, sp, a1
-; CHECK-NEXT: .cfi_def_cfa sp, 16
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
entry:
%a = zext <vscale x 128 x i1> %x to <vscale x 128 x i32>
@@ -354,165 +413,97 @@ define i32 @test_nxv256i1(<vscale x 256 x i1> %x) {
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vmv1r.v v6, v10
-; CHECK-NEXT: vmv1r.v v7, v9
-; CHECK-NEXT: vmv1r.v v5, v8
-; CHECK-NEXT: vmv1r.v v4, v0
-; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmv1r.v v4, v9
+; CHECK-NEXT: vmv1r.v v24, v8
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: mv a2, a0
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: add a0, a0, a2
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v5
-; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: srli a0, a1, 1
-; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v3, v4, a0
-; CHECK-NEXT: vslidedown.vx v2, v5, a0
-; CHECK-NEXT: vmv.v.v v0, v3
-; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: add a2, a2, a3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v2
-; CHECK-NEXT: vmv8r.v v8, v16
-; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 4
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v3, a1
-; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
+; CHECK-NEXT: srli a0, a1, 2
+; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v3, v4, a0
+; CHECK-NEXT: vslidedown.vx v2, v0, a0
+; CHECK-NEXT: vmv1r.v v5, v0
+; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
+; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
+; CHECK-NEXT: vmv1r.v v0, v4
+; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
+; CHECK-NEXT: vadd.vv v16, v16, v24
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v2, a1
-; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v2
; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v4, a1
-; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v5, a1
-; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v6, a1
+; CHECK-NEXT: vslidedown.vx v0, v6, a0
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
+; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v7, a1
+; CHECK-NEXT: vslidedown.vx v0, v7, a0
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
+; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v3
; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
-; CHECK-NEXT: vadd.vv v8, v16, v8
+; CHECK-NEXT: vadd.vv v16, v16, v24
; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: srli a1, a1, 1
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v5, v7, a0
-; CHECK-NEXT: vslidedown.vx v4, v6, a0
-; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v4, a1
-; CHECK-NEXT: vslidedown.vx v3, v5, a1
-; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
+; CHECK-NEXT: vslidedown.vx v4, v4, a1
+; CHECK-NEXT: vslidedown.vx v3, v7, a1
+; CHECK-NEXT: vslidedown.vx v6, v6, a1
+; CHECK-NEXT: vslidedown.vx v0, v5, a1
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
+; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT: vmv1r.v v5, v0
+; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
; CHECK-NEXT: vmv1r.v v0, v3
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vadd.vv v8, v8, v24
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vmv1r.v v0, v4
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v5
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vadd.vv v16, v8, v16
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v24, v8, v16
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v3, a0
+; CHECK-NEXT: vslidedown.vx v5, v5, a0
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v6, a0
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
+; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v4, a0
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
-; CHECK-NEXT: vadd.vv v24, v24, v8
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v16, v16, v24
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vv v8, v8, v0
-; CHECK-NEXT: vadd.vv v16, v24, v16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v8, v24, v8
; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vmv.s.x v16, zero
; CHECK-NEXT: vredsum.vs v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add sp, sp, a1
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -541,16 +532,15 @@ define i16 @test_narrow_nxv64i1(<vscale x 64 x i1> %x) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: srli a0, a0, 1
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v0, a0
+; CHECK-NEXT: vslidedown.vx v0, v0, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
-; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
-; CHECK-NEXT: vmv.s.x v8, zero
-; CHECK-NEXT: vredsum.vs v8, v16, v8
+; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
+; CHECK-NEXT: vmv.s.x v16, zero
+; CHECK-NEXT: vredsum.vs v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll b/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
index 3248f3f34eedf..f05f07eacaf4c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
@@ -18,52 +18,43 @@
define void @constant_folding_crash(ptr %v54, <4 x ptr> %lanes.a, <4 x ptr> %lanes.b, <4 x i1> %sel) {
; RV32-LABEL: constant_folding_crash:
; RV32: # %bb.0: # %entry
-; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: lw a0, 8(a0)
+; RV32-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; RV32-NEXT: vmv.v.i v10, 0
+; RV32-NEXT: vmerge.vim v10, v10, 1, v0
+; RV32-NEXT: vrgather.vi v11, v10, 0
+; RV32-NEXT: vmsne.vi v11, v11, 0
; RV32-NEXT: andi a0, a0, 1
; RV32-NEXT: seqz a0, a0
-; RV32-NEXT: vmv.v.x v11, a0
-; RV32-NEXT: vmsne.vi v0, v11, 0
-; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
-; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; RV32-NEXT: vmv.v.i v9, 0
-; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV32-NEXT: vmv.v.i v11, 10
-; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; RV32-NEXT: vmerge.vim v9, v9, 1, v0
-; RV32-NEXT: vrgather.vi v10, v9, 0
+; RV32-NEXT: vmv.v.x v10, a0
; RV32-NEXT: vmsne.vi v0, v10, 0
; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
; RV32-NEXT: vmv.x.s a0, v8
-; RV32-NEXT: vse32.v v11, (a0), v0.t
+; RV32-NEXT: vmv.v.i v8, 10
+; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vse32.v v8, (a0), v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: constant_folding_crash:
; RV64: # %bb.0: # %entry
-; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v12, v0
; RV64-NEXT: ld a0, 8(a0)
+; RV64-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; RV64-NEXT: vmv.v.i v12, 0
+; RV64-NEXT: vmerge.vim v12, v12, 1, v0
+; RV64-NEXT: vrgather.vi v13, v12, 0
+; RV64-NEXT: vmsne.vi v13, v13, 0
; RV64-NEXT: andi a0, a0, 1
; RV64-NEXT: seqz a0, a0
-; RV64-NEXT: vmv.v.x v13, a0
-; RV64-NEXT: vmsne.vi v0, v13, 0
+; RV64-NEXT: vmv.v.x v12, a0
+; RV64-NEXT: vmsne.vi v0, v12, 0
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vmerge.vvm v8, v10, v8, v0
-; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmv.v.i v9, 0
-; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64-NEXT: vmv.v.i v10, 10
-; RV64-NEXT: vmv1r.v v0, v12
-; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmerge.vim v9, v9, 1, v0
-; RV64-NEXT: vrgather.vi v11, v9, 0
-; RV64-NEXT: vmsne.vi v0, v11, 0
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
-; RV64-NEXT: vse32.v v10, (a0), v0.t
+; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-NEXT: vmv.v.i v8, 10
+; RV64-NEXT: vmv1r.v v0, v13
+; RV64-NEXT: vse32.v v8, (a0), v0.t
; RV64-NEXT: ret
entry:
%sunkaddr = getelementptr i8, ptr %v54, i64 8
diff --git a/llvm/test/CodeGen/RISCV/rvv/copyprop.mir b/llvm/test/CodeGen/RISCV/rvv/copyprop.mir
index aba75ffe29d33..5ecea631bcfce 100644
--- a/llvm/test/CodeGen/RISCV/rvv/copyprop.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/copyprop.mir
@@ -19,9 +19,9 @@
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: bgeu a0, a2, .LBB0_2
; CHECK-NEXT: .LBB0_4: # %entry
+ ; CHECK-NEXT: vsll.vi v9, v8, 5
; CHECK-NEXT: vmsne.vi v0, v8, 0
- ; CHECK-NEXT: vsll.vi v8, v8, 5
- ; CHECK-NEXT: vmerge.vim v9, v8, -1, v0
+ ; CHECK-NEXT: vmerge.vim v9, v9, -1, v0
; CHECK-NEXT: vse64.v v9, (a1)
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
index 20f397b694180..b2d5fb276ba66 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
@@ -1187,13 +1187,13 @@ define <vscale x 8 x i64> @vp_ctlz_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32
define <vscale x 16 x i64> @vp_ctlz_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_nxv16i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: fsrmi a4, 1
; CHECK-NEXT: li a2, 52
; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: sub a5, a0, a1
+; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: sltu a3, a0, a5
; CHECK-NEXT: addi a3, a3, -1
@@ -1222,11 +1222,11 @@ define <vscale x 16 x i64> @vp_ctlz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
;
; CHECK-ZVBB-LABEL: vp_ctlz_nxv16i64:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
; CHECK-ZVBB-NEXT: csrr a1, vlenb
; CHECK-ZVBB-NEXT: srli a2, a1, 3
; CHECK-ZVBB-NEXT: sub a3, a0, a1
+; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
; CHECK-ZVBB-NEXT: sltu a2, a0, a3
; CHECK-ZVBB-NEXT: addi a2, a2, -1
@@ -1301,7 +1301,6 @@ define <vscale x 1 x i8> @vp_ctlz_zero_undef_nxv1i8(<vscale x 1 x i8> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vzext.vf2 v9, v8, v0.t
-; CHECK-NEXT: li a0, 134
; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
@@ -1309,6 +1308,7 @@ define <vscale x 1 x i8> @vp_ctlz_zero_undef_nxv1i8(<vscale x 1 x i8> %va, <vsca
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: li a0, 134
; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
@@ -1348,7 +1348,6 @@ define <vscale x 2 x i8> @vp_ctlz_zero_undef_nxv2i8(<vscale x 2 x i8> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v9, v8, v0.t
-; CHECK-NEXT: li a0, 134
; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
@@ -1356,6 +1355,7 @@ define <vscale x 2 x i8> @vp_ctlz_zero_undef_nxv2i8(<vscale x 2 x i8> %va, <vsca
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: li a0, 134
; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
@@ -1395,7 +1395,6 @@ define <vscale x 4 x i8> @vp_ctlz_zero_undef_nxv4i8(<vscale x 4 x i8> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8, v0.t
-; CHECK-NEXT: li a0, 134
; CHECK-NEXT: vfwcvt.f.xu.v v8, v10, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
@@ -1403,6 +1402,7 @@ define <vscale x 4 x i8> @vp_ctlz_zero_undef_nxv4i8(<vscale x 4 x i8> %va, <vsca
; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t
+; CHECK-NEXT: li a0, 134
; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
@@ -1442,7 +1442,6 @@ define <vscale x 8 x i8> @vp_ctlz_zero_undef_nxv8i8(<vscale x 8 x i8> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v12, v8, v0.t
-; CHECK-NEXT: li a0, 134
; CHECK-NEXT: vfwcvt.f.xu.v v8, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
@@ -1450,6 +1449,7 @@ define <vscale x 8 x i8> @vp_ctlz_zero_undef_nxv8i8(<vscale x 8 x i8> %va, <vsca
; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0, v0.t
+; CHECK-NEXT: li a0, 134
; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
@@ -1489,7 +1489,6 @@ define <vscale x 16 x i8> @vp_ctlz_zero_undef_nxv16i8(<vscale x 16 x i8> %va, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vzext.vf2 v16, v8, v0.t
-; CHECK-NEXT: li a0, 134
; CHECK-NEXT: vfwcvt.f.xu.v v8, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
@@ -1497,6 +1496,7 @@ define <vscale x 16 x i8> @vp_ctlz_zero_undef_nxv16i8(<vscale x 16 x i8> %va, <v
; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; CHECK-NEXT: li a0, 134
; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
@@ -1672,11 +1672,11 @@ define <vscale x 1 x i16> @vp_ctlz_zero_undef_nxv1i16(<vscale x 1 x i16> %va, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
-; CHECK-NEXT: li a0, 142
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: li a0, 142
; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
@@ -1713,11 +1713,11 @@ define <vscale x 2 x i16> @vp_ctlz_zero_undef_nxv2i16(<vscale x 2 x i16> %va, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
-; CHECK-NEXT: li a0, 142
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: li a0, 142
; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
@@ -1754,11 +1754,11 @@ define <vscale x 4 x i16> @vp_ctlz_zero_undef_nxv4i16(<vscale x 4 x i16> %va, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v10, v8, v0.t
-; CHECK-NEXT: li a0, 142
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vsrl.vi v8, v10, 23, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
+; CHECK-NEXT: li a0, 142
; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret
;
@@ -1795,11 +1795,11 @@ define <vscale x 8 x i16> @vp_ctlz_zero_undef_nxv8i16(<vscale x 8 x i16> %va, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v12, v8, v0.t
-; CHECK-NEXT: li a0, 142
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vsrl.vi v8, v12, 23, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t
+; CHECK-NEXT: li a0, 142
; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret
;
@@ -1836,11 +1836,11 @@ define <vscale x 16 x i16> @vp_ctlz_zero_undef_nxv16i16(<vscale x 16 x i16> %va,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vfwcvt.f.xu.v v16, v8, v0.t
-; CHECK-NEXT: li a0, 142
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vsrl.vi v8, v16, 23, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
+; CHECK-NEXT: li a0, 142
; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t
; CHECK-NEXT: ret
;
@@ -1966,9 +1966,9 @@ define <vscale x 1 x i32> @vp_ctlz_zero_undef_nxv1i32(<vscale x 1 x i32> %va, <v
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
-; CHECK-NEXT: li a0, 1054
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: li a0, 1054
; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
@@ -2009,9 +2009,9 @@ define <vscale x 2 x i32> @vp_ctlz_zero_undef_nxv2i32(<vscale x 2 x i32> %va, <v
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t
-; CHECK-NEXT: li a0, 1054
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
+; CHECK-NEXT: li a0, 1054
; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret
;
@@ -2052,9 +2052,9 @@ define <vscale x 4 x i32> @vp_ctlz_zero_undef_nxv4i32(<vscale x 4 x i32> %va, <v
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t
-; CHECK-NEXT: li a0, 1054
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t
+; CHECK-NEXT: li a0, 1054
; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret
;
@@ -2095,9 +2095,9 @@ define <vscale x 8 x i32> @vp_ctlz_zero_undef_nxv8i32(<vscale x 8 x i32> %va, <v
; CHECK-NEXT: li a0, 52
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t
-; CHECK-NEXT: li a0, 1054
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
+; CHECK-NEXT: li a0, 1054
; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t
; CHECK-NEXT: ret
;
@@ -2136,8 +2136,8 @@ define <vscale x 16 x i32> @vp_ctlz_zero_undef_nxv16i32(<vscale x 16 x i32> %va,
; CHECK-NEXT: fsrmi a1, 1
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
-; CHECK-NEXT: li a0, 158
; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
+; CHECK-NEXT: li a0, 158
; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: ret
@@ -2395,12 +2395,12 @@ define <vscale x 8 x i64> @vp_ctlz_zero_undef_nxv8i64_unmasked(<vscale x 8 x i64
define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: fsrmi a3, 1
; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: sub a4, a0, a1
+; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sltu a2, a0, a4
; CHECK-NEXT: addi a2, a2, -1
@@ -2427,11 +2427,11 @@ define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
;
; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i64:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
; CHECK-ZVBB-NEXT: csrr a1, vlenb
; CHECK-ZVBB-NEXT: srli a2, a1, 3
; CHECK-ZVBB-NEXT: sub a3, a0, a1
+; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
; CHECK-ZVBB-NEXT: sltu a2, a0, a3
; CHECK-ZVBB-NEXT: addi a2, a2, -1
@@ -2533,12 +2533,12 @@ define <vscale x 1 x i9> @vp_ctlz_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 7, v0.t
-; CHECK-NEXT: li a0, 142
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: li a0, 142
; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
@@ -2556,13 +2556,13 @@ define <vscale x 1 x i9> @vp_ctlo_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 7, v0.t
-; CHECK-NEXT: li a0, 142
; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: li a0, 142
; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
@@ -2611,13 +2611,13 @@ define <vscale x 1 x i9> @vp_ctlo_nxv1i9_vp_xor(<vscale x 1 x i9> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 7, v0.t
-; CHECK-NEXT: li a0, 142
; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: li a0, 142
; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
index 1bbefc65d3e39..1b03694ee3b36 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
@@ -1176,11 +1176,11 @@ define <vscale x 1 x i64> @vp_ctpop_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
; RV32-NEXT: vadd.vv v8, v8, v9, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v9, a1
-; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v8, v8, v10, v0.t
; RV32-NEXT: vmul.vv v8, v8, v9, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctpop_nxv1i64:
@@ -1212,8 +1212,8 @@ define <vscale x 1 x i64> @vp_ctpop_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1
; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
;
@@ -1340,11 +1340,11 @@ define <vscale x 2 x i64> @vp_ctpop_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
; RV32-NEXT: vadd.vv v8, v8, v10, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v10, a1
-; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: vmul.vv v8, v8, v10, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctpop_nxv2i64:
@@ -1376,8 +1376,8 @@ define <vscale x 2 x i64> @vp_ctpop_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2
; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
;
@@ -1484,31 +1484,31 @@ define <vscale x 4 x i64> @vp_ctpop_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vand.vv v16, v12, v16, v0.t
+; RV32-NEXT: vand.vv v12, v12, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v12, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
-; RV32-NEXT: vand.vv v16, v8, v12, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v12, v0.t
+; RV32-NEXT: vand.vv v12, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v12, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vadd.vv v8, v12, v8, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v12, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v16, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v12, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctpop_nxv4i64:
@@ -1540,8 +1540,8 @@ define <vscale x 4 x i64> @vp_ctpop_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4
; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
;
@@ -1654,25 +1654,25 @@ define <vscale x 7 x i64> @vp_ctpop_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: vand.vv v8, v24, v16, v0.t
+; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
+; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vv v16, v24, v16, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctpop_nxv7i64:
@@ -1704,8 +1704,8 @@ define <vscale x 7 x i64> @vp_ctpop_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
;
@@ -1818,25 +1818,25 @@ define <vscale x 8 x i64> @vp_ctpop_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: vand.vv v8, v24, v16, v0.t
+; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
+; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vv v16, v24, v16, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctpop_nxv8i64:
@@ -1868,8 +1868,8 @@ define <vscale x 8 x i64> @vp_ctpop_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
;
@@ -1970,12 +1970,10 @@ define <vscale x 16 x i64> @vp_ctpop_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 48
+; RV32-NEXT: li a2, 49
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb
-; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v7, v0
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 40
; RV32-NEXT: mul a1, a1, a2
@@ -1985,114 +1983,138 @@ define <vscale x 16 x i64> @vp_ctpop_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: lui a2, 349525
; RV32-NEXT: srli a3, a1, 3
-; RV32-NEXT: vslidedown.vx v0, v0, a3
-; RV32-NEXT: sub a3, a0, a1
+; RV32-NEXT: sub a4, a0, a1
; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: csrr a5, vlenb
+; RV32-NEXT: li a6, 48
+; RV32-NEXT: mul a5, a5, a6
+; RV32-NEXT: add a5, sp, a5
+; RV32-NEXT: addi a5, a5, 16
+; RV32-NEXT: vs1r.v v0, (a5) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vx v0, v0, a3
+; RV32-NEXT: sltu a3, a0, a4
+; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a2
-; RV32-NEXT: sltu a2, a0, a3
-; RV32-NEXT: addi a2, a2, -1
-; RV32-NEXT: and a2, a2, a3
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: addi a3, a3, -1
+; RV32-NEXT: and a3, a3, a4
+; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 5
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 5
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vsub.vv v8, v16, v8, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: addi a3, a3, 819
+; RV32-NEXT: lui a2, 209715
+; RV32-NEXT: addi a2, a2, 819
; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a3
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vmv.v.x v24, a2
+; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v8, v24, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 24
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a3, 61681
-; RV32-NEXT: addi a3, a3, -241
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: lui a2, 61681
+; RV32-NEXT: lui a4, 4112
+; RV32-NEXT: addi a2, a2, -241
+; RV32-NEXT: addi a4, a4, 257
+; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a5, 24
+; RV32-NEXT: mul a2, a2, a5
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: lui a3, 4112
-; RV32-NEXT: addi a3, a3, 257
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a3
+; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v8, a4
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v16, v16, v8, v0.t
+; RV32-NEXT: li a2, 56
+; RV32-NEXT: vsrl.vx v8, v16, a2, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v16, v16, v8, v0.t
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: vsrl.vx v8, v16, a2, v0.t
-; RV32-NEXT: addi a3, sp, 16
-; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: bltu a0, a1, .LBB46_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a0, a1
; RV32-NEXT: .LBB46_2:
-; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: li a3, 40
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 48
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsub.vv v16, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
+; RV32-NEXT: li a1, 48
+; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsub.vv v8, v16, v8, v0.t
+; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vand.vv v16, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: li a1, 24
+; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t
-; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 48
+; RV32-NEXT: li a1, 49
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -2102,72 +2124,93 @@ define <vscale x 16 x i64> @vp_ctpop_nxv16i64(<vscale x 16 x i64> %va, <vscale x
;
; RV64-LABEL: vp_ctpop_nxv16i64:
; RV64: # %bb.0:
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: srli a2, a1, 3
-; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v7, v0, a2
-; RV64-NEXT: mv a2, a0
-; RV64-NEXT: bltu a0, a1, .LBB46_2
+; RV64-NEXT: csrr a5, vlenb
+; RV64-NEXT: srli a1, a5, 3
+; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vx v7, v0, a1
+; RV64-NEXT: mv a1, a0
+; RV64-NEXT: bltu a0, a5, .LBB46_2
; RV64-NEXT: # %bb.1:
-; RV64-NEXT: mv a2, a1
+; RV64-NEXT: mv a1, a5
; RV64-NEXT: .LBB46_2:
-; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
-; RV64-NEXT: lui a5, 4112
+; RV64-NEXT: lui a6, 4112
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: addi a3, a3, 819
; RV64-NEXT: addi a4, a4, -241
-; RV64-NEXT: addi a5, a5, 257
-; RV64-NEXT: slli a6, a2, 32
-; RV64-NEXT: add a2, a2, a6
-; RV64-NEXT: slli a6, a3, 32
-; RV64-NEXT: add a3, a3, a6
-; RV64-NEXT: slli a6, a4, 32
-; RV64-NEXT: add a4, a4, a6
-; RV64-NEXT: slli a6, a5, 32
-; RV64-NEXT: add a5, a5, a6
-; RV64-NEXT: li a6, 56
-; RV64-NEXT: sub a1, a0, a1
-; RV64-NEXT: sltu a0, a0, a1
+; RV64-NEXT: addi a6, a6, 257
+; RV64-NEXT: slli a7, a2, 32
+; RV64-NEXT: add a7, a2, a7
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: add t0, a3, a2
+; RV64-NEXT: slli a2, a4, 32
+; RV64-NEXT: add a4, a4, a2
+; RV64-NEXT: slli a2, a6, 32
+; RV64-NEXT: add a2, a6, a2
+; RV64-NEXT: li a3, 56
+; RV64-NEXT: sub a5, a0, a5
+; RV64-NEXT: sltu a0, a0, a5
; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a0, a0, a1
-; RV64-NEXT: vand.vx v24, v24, a2, v0.t
+; RV64-NEXT: and a0, a0, a5
+; RV64-NEXT: vand.vx v24, v24, a7, v0.t
; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v8, v8, a4, v0.t
-; RV64-NEXT: vmul.vx v8, v8, a5, v0.t
-; RV64-NEXT: vsrl.vx v8, v8, a6, v0.t
+; RV64-NEXT: vmv1r.v v6, v0
; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a2, v0.t
+; RV64-NEXT: vand.vx v24, v24, a7, v0.t
; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vand.vx v24, v16, a3, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v8, t0, v0.t
+; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV64-NEXT: vand.vx v8, v8, t0, v0.t
+; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v16, t0, v0.t
; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a3, v0.t
+; RV64-NEXT: vand.vx v16, v16, t0, v0.t
; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v8, v8, a4, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vmul.vx v8, v8, a2, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v16, a4, v0.t
-; RV64-NEXT: vmul.vx v16, v16, a5, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a6, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v8, v8, a3, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vmul.vx v16, v16, a2, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a3, v0.t
; RV64-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_ctpop_nxv16i64:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
; CHECK-ZVBB-NEXT: csrr a1, vlenb
; CHECK-ZVBB-NEXT: srli a2, a1, 3
; CHECK-ZVBB-NEXT: sub a3, a0, a1
+; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
; CHECK-ZVBB-NEXT: sltu a2, a0, a3
; CHECK-ZVBB-NEXT: addi a2, a2, -1
diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
index 79af06db4171e..181c8b6ffc3db 100644
--- a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
@@ -41,9 +41,9 @@ define <vscale x 1 x i8> @cttz_nxv1i8(<vscale x 1 x i8> %va) {
; CHECK-F-NEXT: vnsrl.wi v9, v9, 23
; CHECK-F-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-F-NEXT: vnsrl.wi v9, v9, 0
+; CHECK-F-NEXT: vsub.vx v9, v9, a0
; CHECK-F-NEXT: vmseq.vi v0, v8, 0
-; CHECK-F-NEXT: vsub.vx v8, v9, a0
-; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
+; CHECK-F-NEXT: vmerge.vim v8, v9, 8, v0
; CHECK-F-NEXT: ret
;
; CHECK-D-LABEL: cttz_nxv1i8:
@@ -58,9 +58,9 @@ define <vscale x 1 x i8> @cttz_nxv1i8(<vscale x 1 x i8> %va) {
; CHECK-D-NEXT: vnsrl.wi v9, v9, 23
; CHECK-D-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-D-NEXT: vnsrl.wi v9, v9, 0
+; CHECK-D-NEXT: vsub.vx v9, v9, a0
; CHECK-D-NEXT: vmseq.vi v0, v8, 0
-; CHECK-D-NEXT: vsub.vx v8, v9, a0
-; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
+; CHECK-D-NEXT: vmerge.vim v8, v9, 8, v0
; CHECK-D-NEXT: ret
;
; CHECK-ZVBB-LABEL: cttz_nxv1i8:
@@ -105,9 +105,9 @@ define <vscale x 2 x i8> @cttz_nxv2i8(<vscale x 2 x i8> %va) {
; CHECK-F-NEXT: vnsrl.wi v9, v9, 23
; CHECK-F-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-F-NEXT: vnsrl.wi v9, v9, 0
+; CHECK-F-NEXT: vsub.vx v9, v9, a0
; CHECK-F-NEXT: vmseq.vi v0, v8, 0
-; CHECK-F-NEXT: vsub.vx v8, v9, a0
-; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
+; CHECK-F-NEXT: vmerge.vim v8, v9, 8, v0
; CHECK-F-NEXT: ret
;
; CHECK-D-LABEL: cttz_nxv2i8:
@@ -122,9 +122,9 @@ define <vscale x 2 x i8> @cttz_nxv2i8(<vscale x 2 x i8> %va) {
; CHECK-D-NEXT: vnsrl.wi v9, v9, 23
; CHECK-D-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-D-NEXT: vnsrl.wi v9, v9, 0
+; CHECK-D-NEXT: vsub.vx v9, v9, a0
; CHECK-D-NEXT: vmseq.vi v0, v8, 0
-; CHECK-D-NEXT: vsub.vx v8, v9, a0
-; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
+; CHECK-D-NEXT: vmerge.vim v8, v9, 8, v0
; CHECK-D-NEXT: ret
;
; CHECK-ZVBB-LABEL: cttz_nxv2i8:
@@ -169,9 +169,9 @@ define <vscale x 4 x i8> @cttz_nxv4i8(<vscale x 4 x i8> %va) {
; CHECK-F-NEXT: vnsrl.wi v9, v10, 23
; CHECK-F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; CHECK-F-NEXT: vnsrl.wi v9, v9, 0
+; CHECK-F-NEXT: vsub.vx v9, v9, a0
; CHECK-F-NEXT: vmseq.vi v0, v8, 0
-; CHECK-F-NEXT: vsub.vx v8, v9, a0
-; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
+; CHECK-F-NEXT: vmerge.vim v8, v9, 8, v0
; CHECK-F-NEXT: ret
;
; CHECK-D-LABEL: cttz_nxv4i8:
@@ -186,9 +186,9 @@ define <vscale x 4 x i8> @cttz_nxv4i8(<vscale x 4 x i8> %va) {
; CHECK-D-NEXT: vnsrl.wi v9, v10, 23
; CHECK-D-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; CHECK-D-NEXT: vnsrl.wi v9, v9, 0
+; CHECK-D-NEXT: vsub.vx v9, v9, a0
; CHECK-D-NEXT: vmseq.vi v0, v8, 0
-; CHECK-D-NEXT: vsub.vx v8, v9, a0
-; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
+; CHECK-D-NEXT: vmerge.vim v8, v9, 8, v0
; CHECK-D-NEXT: ret
;
; CHECK-ZVBB-LABEL: cttz_nxv4i8:
@@ -233,9 +233,9 @@ define <vscale x 8 x i8> @cttz_nxv8i8(<vscale x 8 x i8> %va) {
; CHECK-F-NEXT: vnsrl.wi v10, v12, 23
; CHECK-F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-F-NEXT: vnsrl.wi v9, v10, 0
+; CHECK-F-NEXT: vsub.vx v9, v9, a0
; CHECK-F-NEXT: vmseq.vi v0, v8, 0
-; CHECK-F-NEXT: vsub.vx v8, v9, a0
-; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
+; CHECK-F-NEXT: vmerge.vim v8, v9, 8, v0
; CHECK-F-NEXT: ret
;
; CHECK-D-LABEL: cttz_nxv8i8:
@@ -250,9 +250,9 @@ define <vscale x 8 x i8> @cttz_nxv8i8(<vscale x 8 x i8> %va) {
; CHECK-D-NEXT: vnsrl.wi v10, v12, 23
; CHECK-D-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-D-NEXT: vnsrl.wi v9, v10, 0
+; CHECK-D-NEXT: vsub.vx v9, v9, a0
; CHECK-D-NEXT: vmseq.vi v0, v8, 0
-; CHECK-D-NEXT: vsub.vx v8, v9, a0
-; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
+; CHECK-D-NEXT: vmerge.vim v8, v9, 8, v0
; CHECK-D-NEXT: ret
;
; CHECK-ZVBB-LABEL: cttz_nxv8i8:
@@ -297,9 +297,9 @@ define <vscale x 16 x i8> @cttz_nxv16i8(<vscale x 16 x i8> %va) {
; CHECK-F-NEXT: vnsrl.wi v12, v16, 23
; CHECK-F-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; CHECK-F-NEXT: vnsrl.wi v10, v12, 0
+; CHECK-F-NEXT: vsub.vx v10, v10, a0
; CHECK-F-NEXT: vmseq.vi v0, v8, 0
-; CHECK-F-NEXT: vsub.vx v8, v10, a0
-; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
+; CHECK-F-NEXT: vmerge.vim v8, v10, 8, v0
; CHECK-F-NEXT: ret
;
; CHECK-D-LABEL: cttz_nxv16i8:
@@ -314,9 +314,9 @@ define <vscale x 16 x i8> @cttz_nxv16i8(<vscale x 16 x i8> %va) {
; CHECK-D-NEXT: vnsrl.wi v12, v16, 23
; CHECK-D-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; CHECK-D-NEXT: vnsrl.wi v10, v12, 0
+; CHECK-D-NEXT: vsub.vx v10, v10, a0
; CHECK-D-NEXT: vmseq.vi v0, v8, 0
-; CHECK-D-NEXT: vsub.vx v8, v10, a0
-; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
+; CHECK-D-NEXT: vmerge.vim v8, v10, 8, v0
; CHECK-D-NEXT: ret
;
; CHECK-ZVBB-LABEL: cttz_nxv16i8:
diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
index c82ad17545a6a..bf003ef675a36 100644
--- a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
@@ -13,8 +13,8 @@ define <vscale x 1 x i8> @vp_cttz_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
@@ -73,8 +73,8 @@ define <vscale x 2 x i8> @vp_cttz_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
@@ -133,8 +133,8 @@ define <vscale x 4 x i8> @vp_cttz_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
@@ -193,8 +193,8 @@ define <vscale x 8 x i8> @vp_cttz_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
@@ -253,8 +253,8 @@ define <vscale x 16 x i8> @vp_cttz_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vadd.vi v10, v8, -1, v0.t
-; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
@@ -313,8 +313,8 @@ define <vscale x 32 x i8> @vp_cttz_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vadd.vi v12, v8, -1, v0.t
-; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
@@ -373,8 +373,8 @@ define <vscale x 64 x i8> @vp_cttz_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1, v0.t
-; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
@@ -433,10 +433,10 @@ define <vscale x 1 x i16> @vp_cttz_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 3
@@ -507,10 +507,10 @@ define <vscale x 2 x i16> @vp_cttz_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 3
@@ -581,10 +581,10 @@ define <vscale x 4 x i16> @vp_cttz_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 3
@@ -655,10 +655,10 @@ define <vscale x 8 x i16> @vp_cttz_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vadd.vi v10, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: lui a0, 3
@@ -729,10 +729,10 @@ define <vscale x 16 x i16> @vp_cttz_nxv16i16(<vscale x 16 x i16> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vadd.vi v12, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: lui a0, 3
@@ -803,10 +803,10 @@ define <vscale x 32 x i16> @vp_cttz_nxv32i16(<vscale x 32 x i16> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
; CHECK-NEXT: lui a0, 3
@@ -877,10 +877,10 @@ define <vscale x 1 x i32> @vp_cttz_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 209715
@@ -953,10 +953,10 @@ define <vscale x 2 x i32> @vp_cttz_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 209715
@@ -1029,10 +1029,10 @@ define <vscale x 4 x i32> @vp_cttz_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vadd.vi v10, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: lui a0, 209715
@@ -1105,10 +1105,10 @@ define <vscale x 8 x i32> @vp_cttz_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vadd.vi v12, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: lui a0, 209715
@@ -1181,10 +1181,10 @@ define <vscale x 16 x i32> @vp_cttz_nxv16i32(<vscale x 16 x i32> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
; CHECK-NEXT: lui a0, 209715
@@ -1257,15 +1257,15 @@ define <vscale x 1 x i64> @vp_cttz_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vadd.vi v9, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v10, a1
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vand.vv v8, v8, v9, v0.t
+; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
; RV32-NEXT: vand.vv v9, v9, v10, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma
@@ -1287,11 +1287,11 @@ define <vscale x 1 x i64> @vp_cttz_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x
; RV32-NEXT: vadd.vv v8, v8, v9, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v9, a1
-; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v8, v8, v10, v0.t
; RV32-NEXT: vmul.vv v8, v8, v9, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_cttz_nxv1i64:
@@ -1326,8 +1326,8 @@ define <vscale x 1 x i64> @vp_cttz_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x
; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
;
@@ -1433,15 +1433,15 @@ define <vscale x 2 x i64> @vp_cttz_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vadd.vi v10, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vand.vv v8, v8, v10, v0.t
+; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV32-NEXT: vand.vv v10, v10, v12, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma
@@ -1463,11 +1463,11 @@ define <vscale x 2 x i64> @vp_cttz_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x
; RV32-NEXT: vadd.vv v8, v8, v10, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v10, a1
-; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: vmul.vv v8, v8, v10, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_cttz_nxv2i64:
@@ -1502,8 +1502,8 @@ define <vscale x 2 x i64> @vp_cttz_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x
; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
;
@@ -1609,41 +1609,41 @@ define <vscale x 4 x i64> @vp_cttz_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vadd.vi v12, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma
; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vand.vv v12, v8, v12, v0.t
-; RV32-NEXT: vsrl.vi v8, v12, 1, v0.t
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
+; RV32-NEXT: vand.vv v12, v12, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsub.vv v12, v12, v16, v0.t
-; RV32-NEXT: vand.vv v16, v12, v8, v0.t
-; RV32-NEXT: vsrl.vi v12, v12, 2, v0.t
-; RV32-NEXT: vand.vv v8, v12, v8, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v12, v0.t
+; RV32-NEXT: vand.vv v12, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v12, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vadd.vv v8, v12, v8, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v12, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v16, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v12, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_cttz_nxv4i64:
@@ -1678,8 +1678,8 @@ define <vscale x 4 x i64> @vp_cttz_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x
; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
;
@@ -1785,41 +1785,41 @@ define <vscale x 7 x i64> @vp_cttz_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vadd.vi v16, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t
-; RV32-NEXT: vand.vv v24, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v24, v16, v24, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsub.vv v24, v16, v24, v0.t
-; RV32-NEXT: vand.vv v16, v24, v8, v0.t
+; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: vand.vv v8, v24, v16, v0.t
; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
+; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_cttz_nxv7i64:
@@ -1854,8 +1854,8 @@ define <vscale x 7 x i64> @vp_cttz_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
;
@@ -1961,41 +1961,41 @@ define <vscale x 8 x i64> @vp_cttz_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vadd.vi v16, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t
-; RV32-NEXT: vand.vv v24, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v24, v16, v24, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsub.vv v24, v16, v24, v0.t
-; RV32-NEXT: vand.vv v16, v24, v8, v0.t
+; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: vand.vv v8, v24, v16, v0.t
; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
+; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_cttz_nxv8i64:
@@ -2030,8 +2030,8 @@ define <vscale x 8 x i64> @vp_cttz_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
;
@@ -2138,12 +2138,10 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 48
+; RV32-NEXT: li a2, 49
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb
-; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v7, v0
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 40
; RV32-NEXT: mul a1, a1, a2
@@ -2151,77 +2149,89 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: srli a2, a1, 3
-; RV32-NEXT: sub a3, a0, a1
-; RV32-NEXT: vslidedown.vx v0, v0, a2
-; RV32-NEXT: sltu a2, a0, a3
-; RV32-NEXT: addi a2, a2, -1
-; RV32-NEXT: and a2, a2, a3
-; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: addi a3, a3, 1365
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: srli a3, a1, 3
+; RV32-NEXT: sub a4, a0, a1
+; RV32-NEXT: addi a2, a2, 1365
+; RV32-NEXT: csrr a5, vlenb
+; RV32-NEXT: li a6, 48
+; RV32-NEXT: mul a5, a5, a6
+; RV32-NEXT: add a5, sp, a5
+; RV32-NEXT: addi a5, a5, 16
+; RV32-NEXT: vs1r.v v0, (a5) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vx v0, v0, a3
+; RV32-NEXT: sltu a3, a0, a4
+; RV32-NEXT: addi a3, a3, -1
+; RV32-NEXT: and a3, a3, a4
+; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV32-NEXT: vadd.vi v8, v16, -1, v0.t
; RV32-NEXT: vnot.v v16, v16, v0.t
; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a3
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 5
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: addi a3, a3, 819
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 5
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV32-NEXT: lui a2, 209715
+; RV32-NEXT: addi a2, a2, 819
; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a3
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vmv.v.x v24, a2
+; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v8, v24, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 24
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a3, 61681
-; RV32-NEXT: addi a3, a3, -241
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: lui a2, 61681
+; RV32-NEXT: lui a4, 4112
+; RV32-NEXT: addi a2, a2, -241
+; RV32-NEXT: addi a4, a4, 257
+; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a5, 24
+; RV32-NEXT: mul a2, a2, a5
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: lui a3, 4112
-; RV32-NEXT: addi a3, a3, 257
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a3
+; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v8, a4
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v16, v16, v8, v0.t
+; RV32-NEXT: li a2, 56
+; RV32-NEXT: vsrl.vx v8, v16, a2, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v16, v16, v8, v0.t
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: vsrl.vx v8, v16, a2, v0.t
-; RV32-NEXT: addi a3, sp, 16
-; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: bltu a0, a1, .LBB46_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a0, a1
; RV32-NEXT: .LBB46_2:
-; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: li a3, 48
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a3, 40
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
@@ -2237,13 +2247,21 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 48
+; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
+; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
+; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v16, v8, v24, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
@@ -2252,22 +2270,26 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: li a1, 24
+; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t
-; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 48
+; RV32-NEXT: li a1, 49
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -2277,8 +2299,6 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
;
; RV64-LABEL: vp_cttz_nxv16i64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v7, v0
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: lui a3, 209715
@@ -2288,37 +2308,39 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV64-NEXT: sub a7, a0, a1
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: addi a3, a3, 819
-; RV64-NEXT: addi a4, a4, -241
-; RV64-NEXT: addi t0, a5, 257
+; RV64-NEXT: addi t0, a4, -241
+; RV64-NEXT: addi t1, a5, 257
+; RV64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; RV64-NEXT: vmv1r.v v7, v0
; RV64-NEXT: vslidedown.vx v0, v0, a6
-; RV64-NEXT: slli a6, a2, 32
-; RV64-NEXT: add a6, a2, a6
-; RV64-NEXT: slli a5, a3, 32
-; RV64-NEXT: add a5, a3, a5
-; RV64-NEXT: slli a2, a4, 32
-; RV64-NEXT: add a2, a4, a2
-; RV64-NEXT: slli a3, t0, 32
-; RV64-NEXT: add a3, t0, a3
-; RV64-NEXT: sltu a4, a0, a7
-; RV64-NEXT: addi a4, a4, -1
-; RV64-NEXT: and a7, a4, a7
-; RV64-NEXT: li a4, 56
-; RV64-NEXT: vsetvli zero, a7, e64, m8, ta, ma
+; RV64-NEXT: slli a5, a2, 32
+; RV64-NEXT: add a5, a2, a5
+; RV64-NEXT: slli a4, a3, 32
+; RV64-NEXT: add a4, a3, a4
+; RV64-NEXT: slli a2, t0, 32
+; RV64-NEXT: add a2, t0, a2
+; RV64-NEXT: slli a3, t1, 32
+; RV64-NEXT: add a3, t1, a3
+; RV64-NEXT: sltu a6, a0, a7
+; RV64-NEXT: addi a6, a6, -1
+; RV64-NEXT: and a6, a6, a7
+; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; RV64-NEXT: vadd.vi v24, v16, -1, v0.t
; RV64-NEXT: vnot.v v16, v16, v0.t
; RV64-NEXT: vand.vv v16, v16, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: vand.vx v24, v24, a5, v0.t
; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vand.vx v24, v16, a5, v0.t
+; RV64-NEXT: vand.vx v24, v16, a4, v0.t
; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a5, v0.t
+; RV64-NEXT: vand.vx v16, v16, a4, v0.t
; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
; RV64-NEXT: vand.vx v16, v16, a2, v0.t
; RV64-NEXT: vmul.vx v16, v16, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a4, v0.t
+; RV64-NEXT: li a6, 56
+; RV64-NEXT: vsrl.vx v16, v16, a6, v0.t
; RV64-NEXT: bltu a0, a1, .LBB46_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a0, a1
@@ -2329,26 +2351,26 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV64-NEXT: vnot.v v8, v8, v0.t
; RV64-NEXT: vand.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: vand.vx v24, v24, a5, v0.t
; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a5, v0.t
+; RV64-NEXT: vand.vx v24, v8, a4, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a5, v0.t
+; RV64-NEXT: vand.vx v8, v8, a4, v0.t
; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
; RV64-NEXT: vand.vx v8, v8, a2, v0.t
; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v8, v8, a4, v0.t
+; RV64-NEXT: vsrl.vx v8, v8, a6, v0.t
; RV64-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_cttz_nxv16i64:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
; CHECK-ZVBB-NEXT: csrr a1, vlenb
; CHECK-ZVBB-NEXT: srli a2, a1, 3
; CHECK-ZVBB-NEXT: sub a3, a0, a1
+; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
; CHECK-ZVBB-NEXT: sltu a2, a0, a3
; CHECK-ZVBB-NEXT: addi a2, a2, -1
@@ -2568,7 +2590,6 @@ define <vscale x 1 x i8> @vp_cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
-; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vzext.vf2 v9, v8, v0.t
@@ -2579,6 +2600,7 @@ define <vscale x 1 x i8> @vp_cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va, <vsca
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
@@ -2621,7 +2643,6 @@ define <vscale x 2 x i8> @vp_cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
-; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v9, v8, v0.t
@@ -2632,6 +2653,7 @@ define <vscale x 2 x i8> @vp_cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va, <vsca
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
@@ -2674,7 +2696,6 @@ define <vscale x 4 x i8> @vp_cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
-; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8, v0.t
@@ -2685,6 +2706,7 @@ define <vscale x 4 x i8> @vp_cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va, <vsca
; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t
+; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
@@ -2727,7 +2749,6 @@ define <vscale x 8 x i8> @vp_cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
-; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v12, v8, v0.t
@@ -2738,6 +2759,7 @@ define <vscale x 8 x i8> @vp_cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va, <vsca
; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0, v0.t
+; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
@@ -2780,7 +2802,6 @@ define <vscale x 16 x i8> @vp_cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t
-; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vzext.vf2 v16, v8, v0.t
@@ -2791,6 +2812,7 @@ define <vscale x 16 x i8> @vp_cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va, <v
; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
@@ -2833,8 +2855,8 @@ define <vscale x 32 x i8> @vp_cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vadd.vi v12, v8, -1, v0.t
-; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
@@ -2893,8 +2915,8 @@ define <vscale x 64 x i8> @vp_cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1, v0.t
-; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
@@ -2953,13 +2975,13 @@ define <vscale x 1 x i16> @vp_cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
-; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
@@ -2998,13 +3020,13 @@ define <vscale x 2 x i16> @vp_cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
-; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
@@ -3043,13 +3065,13 @@ define <vscale x 4 x i16> @vp_cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
-; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v10, v8, v9, v0.t
; CHECK-NEXT: vfwcvt.f.xu.v v8, v10, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
+; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret
;
@@ -3088,13 +3110,13 @@ define <vscale x 8 x i16> @vp_cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t
-; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v12, v8, v10, v0.t
; CHECK-NEXT: vfwcvt.f.xu.v v8, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t
+; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret
;
@@ -3133,13 +3155,13 @@ define <vscale x 16 x i16> @vp_cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t
-; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v16, v8, v12, v0.t
; CHECK-NEXT: vfwcvt.f.xu.v v8, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
+; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v16, a0, v0.t
; CHECK-NEXT: ret
;
@@ -3178,10 +3200,10 @@ define <vscale x 32 x i16> @vp_cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
; CHECK-NEXT: lui a0, 3
@@ -3257,9 +3279,9 @@ define <vscale x 1 x i32> @vp_cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va, <v
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
-; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
@@ -3304,9 +3326,9 @@ define <vscale x 2 x i32> @vp_cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va, <v
; CHECK-NEXT: vfwcvt.f.xu.v v8, v10, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t
-; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
+; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vsub.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret
;
@@ -3351,9 +3373,9 @@ define <vscale x 4 x i32> @vp_cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va, <v
; CHECK-NEXT: vfwcvt.f.xu.v v8, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t
-; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t
+; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vsub.vx v8, v12, a0, v0.t
; CHECK-NEXT: ret
;
@@ -3398,9 +3420,9 @@ define <vscale x 8 x i32> @vp_cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va, <v
; CHECK-NEXT: vfwcvt.f.xu.v v8, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t
-; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
+; CHECK-NEXT: li a0, 1023
; CHECK-NEXT: vsub.vx v8, v16, a0, v0.t
; CHECK-NEXT: ret
;
@@ -3441,10 +3463,10 @@ define <vscale x 16 x i32> @vp_cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va,
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t
; CHECK-NEXT: fsrmi a0, 1
-; CHECK-NEXT: li a1, 127
; CHECK-NEXT: vand.vv v8, v8, v16, v0.t
; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
+; CHECK-NEXT: li a1, 127
; CHECK-NEXT: vsub.vx v8, v8, a1, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
@@ -3724,12 +3746,12 @@ define <vscale x 8 x i64> @vp_cttz_zero_undef_nxv8i64_unmasked(<vscale x 8 x i64
define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_cttz_zero_undef_nxv16i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: fsrmi a3, 1
; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: sub a4, a0, a1
+; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sltu a2, a0, a4
; CHECK-NEXT: addi a2, a2, -1
@@ -3750,8 +3772,8 @@ define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v8, 0, v0.t
-; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vand.vv v8, v8, v24, v0.t
+; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
; CHECK-NEXT: vsrl.vx v8, v8, a2, v0.t
; CHECK-NEXT: vsub.vx v8, v8, a3, v0.t
@@ -3760,11 +3782,11 @@ define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
;
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i64:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
; CHECK-ZVBB-NEXT: csrr a1, vlenb
; CHECK-ZVBB-NEXT: srli a2, a1, 3
; CHECK-ZVBB-NEXT: sub a3, a0, a1
+; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
; CHECK-ZVBB-NEXT: sltu a2, a0, a3
; CHECK-ZVBB-NEXT: addi a2, a2, -1
@@ -3868,13 +3890,13 @@ define <vscale x 1 x i9> @vp_zero_undef_cttz_nxv1i9(<vscale x 1 x i9> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t
-; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
+; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll b/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
index fb4391a5e30c1..c69e30d074325 100644
--- a/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
@@ -503,8 +503,8 @@ define <vscale x 1 x i8> @ceil_nxv1f64_to_si8(<vscale x 1 x double> %x) {
; RV32-NEXT: fld fa5, %lo(.LCPI16_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT: vfabs.v v9, v8
-; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: fsrmi a0, 3
+; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -525,8 +525,8 @@ define <vscale x 1 x i8> @ceil_nxv1f64_to_si8(<vscale x 1 x double> %x) {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: slli a0, a0, 52
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -551,8 +551,8 @@ define <vscale x 1 x i8> @ceil_nxv1f64_to_ui8(<vscale x 1 x double> %x) {
; RV32-NEXT: fld fa5, %lo(.LCPI17_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT: vfabs.v v9, v8
-; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: fsrmi a0, 3
+; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -573,8 +573,8 @@ define <vscale x 1 x i8> @ceil_nxv1f64_to_ui8(<vscale x 1 x double> %x) {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: slli a0, a0, 52
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -599,8 +599,8 @@ define <vscale x 1 x i16> @ceil_nxv1f64_to_si16(<vscale x 1 x double> %x) {
; RV32-NEXT: fld fa5, %lo(.LCPI18_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT: vfabs.v v9, v8
-; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: fsrmi a0, 3
+; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -619,8 +619,8 @@ define <vscale x 1 x i16> @ceil_nxv1f64_to_si16(<vscale x 1 x double> %x) {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: slli a0, a0, 52
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -643,8 +643,8 @@ define <vscale x 1 x i16> @ceil_nxv1f64_to_ui16(<vscale x 1 x double> %x) {
; RV32-NEXT: fld fa5, %lo(.LCPI19_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT: vfabs.v v9, v8
-; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: fsrmi a0, 3
+; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -663,8 +663,8 @@ define <vscale x 1 x i16> @ceil_nxv1f64_to_ui16(<vscale x 1 x double> %x) {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: slli a0, a0, 52
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -779,8 +779,8 @@ define <vscale x 4 x i8> @ceil_nxv4f64_to_si8(<vscale x 4 x double> %x) {
; RV32-NEXT: fld fa5, %lo(.LCPI24_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32-NEXT: vfabs.v v12, v8
-; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: fsrmi a0, 3
+; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -801,8 +801,8 @@ define <vscale x 4 x i8> @ceil_nxv4f64_to_si8(<vscale x 4 x double> %x) {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: slli a0, a0, 52
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -827,8 +827,8 @@ define <vscale x 4 x i8> @ceil_nxv4f64_to_ui8(<vscale x 4 x double> %x) {
; RV32-NEXT: fld fa5, %lo(.LCPI25_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32-NEXT: vfabs.v v12, v8
-; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: fsrmi a0, 3
+; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -849,8 +849,8 @@ define <vscale x 4 x i8> @ceil_nxv4f64_to_ui8(<vscale x 4 x double> %x) {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: slli a0, a0, 52
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -875,8 +875,8 @@ define <vscale x 4 x i16> @ceil_nxv4f64_to_si16(<vscale x 4 x double> %x) {
; RV32-NEXT: fld fa5, %lo(.LCPI26_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32-NEXT: vfabs.v v12, v8
-; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: fsrmi a0, 3
+; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -895,8 +895,8 @@ define <vscale x 4 x i16> @ceil_nxv4f64_to_si16(<vscale x 4 x double> %x) {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: slli a0, a0, 52
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -919,8 +919,8 @@ define <vscale x 4 x i16> @ceil_nxv4f64_to_ui16(<vscale x 4 x double> %x) {
; RV32-NEXT: fld fa5, %lo(.LCPI27_0)(a0)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32-NEXT: vfabs.v v12, v8
-; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: fsrmi a0, 3
+; RV32-NEXT: vmflt.vf v0, v12, fa5
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -939,8 +939,8 @@ define <vscale x 4 x i16> @ceil_nxv4f64_to_ui16(<vscale x 4 x double> %x) {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: slli a0, a0, 52
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v12, v12, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/expandload.ll b/llvm/test/CodeGen/RISCV/rvv/expandload.ll
index cc1282a9119da..f13a9d0764c8b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/expandload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/expandload.ll
@@ -218,18 +218,23 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: csrr a2, vlenb
-; CHECK-RV32-NEXT: slli a2, a2, 5
+; CHECK-RV32-NEXT: slli a3, a2, 5
+; CHECK-RV32-NEXT: add a2, a3, a2
; CHECK-RV32-NEXT: sub sp, sp, a2
-; CHECK-RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; CHECK-RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; CHECK-RV32-NEXT: csrr a2, vlenb
; CHECK-RV32-NEXT: li a3, 24
; CHECK-RV32-NEXT: mul a2, a2, a3
; CHECK-RV32-NEXT: add a2, sp, a2
; CHECK-RV32-NEXT: addi a2, a2, 16
; CHECK-RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vmv1r.v v7, v8
+; CHECK-RV32-NEXT: csrr a2, vlenb
+; CHECK-RV32-NEXT: slli a2, a2, 5
+; CHECK-RV32-NEXT: add a2, sp, a2
+; CHECK-RV32-NEXT: addi a2, a2, 16
+; CHECK-RV32-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: li a2, 128
+; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV32-NEXT: vslidedown.vi v8, v0, 1
; CHECK-RV32-NEXT: li a3, 32
; CHECK-RV32-NEXT: vmv.x.s a4, v0
@@ -264,34 +269,48 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV32-NEXT: add a1, a1, a5
; CHECK-RV32-NEXT: add a1, a3, a1
; CHECK-RV32-NEXT: add a0, a0, a1
+; CHECK-RV32-NEXT: csrr a1, vlenb
+; CHECK-RV32-NEXT: slli a1, a1, 5
+; CHECK-RV32-NEXT: add a1, sp, a1
+; CHECK-RV32-NEXT: addi a1, a1, 16
+; CHECK-RV32-NEXT: vl1r.v v8, (a1) # vscale x 8-byte Folded Reload
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; CHECK-RV32-NEXT: vcpop.m a1, v7
+; CHECK-RV32-NEXT: vcpop.m a1, v8
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-RV32-NEXT: vle8.v v8, (a0)
; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, mu
-; CHECK-RV32-NEXT: viota.m v24, v0
+; CHECK-RV32-NEXT: viota.m v16, v0
; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: slli a0, a0, 4
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: li a1, 24
; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: vrgather.vv v8, v16, v24, v0.t
+; CHECK-RV32-NEXT: vrgather.vv v8, v24, v16, v0.t
; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: li a1, 24
; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
; CHECK-RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: viota.m v8, v7
-; CHECK-RV32-NEXT: vmv1r.v v0, v7
+; CHECK-RV32-NEXT: csrr a0, vlenb
+; CHECK-RV32-NEXT: slli a0, a0, 5
+; CHECK-RV32-NEXT: add a0, sp, a0
+; CHECK-RV32-NEXT: addi a0, a0, 16
+; CHECK-RV32-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV32-NEXT: viota.m v8, v24
+; CHECK-RV32-NEXT: csrr a0, vlenb
+; CHECK-RV32-NEXT: slli a0, a0, 5
+; CHECK-RV32-NEXT: add a0, sp, a0
+; CHECK-RV32-NEXT: addi a0, a0, 16
+; CHECK-RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: slli a0, a0, 3
; CHECK-RV32-NEXT: add a0, sp, a0
@@ -307,7 +326,8 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV32-NEXT: addi a0, a0, 16
; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 5
+; CHECK-RV32-NEXT: slli a1, a0, 5
+; CHECK-RV32-NEXT: add a0, a1, a0
; CHECK-RV32-NEXT: add sp, sp, a0
; CHECK-RV32-NEXT: .cfi_def_cfa sp, 16
; CHECK-RV32-NEXT: addi sp, sp, 16
@@ -319,18 +339,23 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV64-NEXT: addi sp, sp, -16
; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV64-NEXT: csrr a2, vlenb
-; CHECK-RV64-NEXT: slli a2, a2, 5
+; CHECK-RV64-NEXT: slli a3, a2, 5
+; CHECK-RV64-NEXT: add a2, a3, a2
; CHECK-RV64-NEXT: sub sp, sp, a2
-; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; CHECK-RV64-NEXT: csrr a2, vlenb
; CHECK-RV64-NEXT: li a3, 24
; CHECK-RV64-NEXT: mul a2, a2, a3
; CHECK-RV64-NEXT: add a2, sp, a2
; CHECK-RV64-NEXT: addi a2, a2, 16
; CHECK-RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vmv1r.v v7, v8
+; CHECK-RV64-NEXT: csrr a2, vlenb
+; CHECK-RV64-NEXT: slli a2, a2, 5
+; CHECK-RV64-NEXT: add a2, sp, a2
+; CHECK-RV64-NEXT: addi a2, a2, 16
+; CHECK-RV64-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: li a2, 128
+; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV64-NEXT: vslidedown.vi v8, v0, 1
; CHECK-RV64-NEXT: vmv.x.s a3, v0
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -351,8 +376,13 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV64-NEXT: add a4, sp, a4
; CHECK-RV64-NEXT: addi a4, a4, 16
; CHECK-RV64-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: csrr a4, vlenb
+; CHECK-RV64-NEXT: slli a4, a4, 5
+; CHECK-RV64-NEXT: add a4, sp, a4
+; CHECK-RV64-NEXT: addi a4, a4, 16
+; CHECK-RV64-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; CHECK-RV64-NEXT: vcpop.m a4, v7
+; CHECK-RV64-NEXT: vcpop.m a4, v8
; CHECK-RV64-NEXT: cpop a3, a3
; CHECK-RV64-NEXT: cpop a1, a1
; CHECK-RV64-NEXT: add a0, a0, a3
@@ -381,16 +411,25 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: viota.m v8, v7
-; CHECK-RV64-NEXT: vmv1r.v v0, v7
+; CHECK-RV64-NEXT: csrr a0, vlenb
+; CHECK-RV64-NEXT: slli a0, a0, 5
+; CHECK-RV64-NEXT: add a0, sp, a0
+; CHECK-RV64-NEXT: addi a0, a0, 16
+; CHECK-RV64-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV64-NEXT: viota.m v24, v8
+; CHECK-RV64-NEXT: csrr a0, vlenb
+; CHECK-RV64-NEXT: slli a0, a0, 5
+; CHECK-RV64-NEXT: add a0, sp, a0
+; CHECK-RV64-NEXT: addi a0, a0, 16
+; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
; CHECK-RV64-NEXT: slli a0, a0, 3
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: addi a0, sp, 16
-; CHECK-RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV64-NEXT: vrgather.vv v16, v24, v8, v0.t
+; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vrgather.vv v16, v8, v24, v0.t
; CHECK-RV64-NEXT: csrr a0, vlenb
; CHECK-RV64-NEXT: li a1, 24
; CHECK-RV64-NEXT: mul a0, a0, a1
@@ -398,7 +437,8 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 5
+; CHECK-RV64-NEXT: slli a1, a0, 5
+; CHECK-RV64-NEXT: add a0, a1, a0
; CHECK-RV64-NEXT: add sp, sp, a0
; CHECK-RV64-NEXT: .cfi_def_cfa sp, 16
; CHECK-RV64-NEXT: addi sp, sp, 16
@@ -644,27 +684,39 @@ define <128 x i16> @test_expandload_v128i16(ptr %base, <128 x i1> %mask, <128 x
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: csrr a1, vlenb
-; CHECK-RV32-NEXT: slli a1, a1, 5
+; CHECK-RV32-NEXT: slli a2, a1, 5
+; CHECK-RV32-NEXT: add a1, a2, a1
; CHECK-RV32-NEXT: sub sp, sp, a1
-; CHECK-RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; CHECK-RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; CHECK-RV32-NEXT: csrr a1, vlenb
; CHECK-RV32-NEXT: li a2, 24
; CHECK-RV32-NEXT: mul a1, a1, a2
; CHECK-RV32-NEXT: add a1, sp, a1
; CHECK-RV32-NEXT: addi a1, a1, 16
; CHECK-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: li a1, 64
; CHECK-RV32-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v7, v0, 8
+; CHECK-RV32-NEXT: vmv8r.v v16, v8
+; CHECK-RV32-NEXT: li a1, 64
+; CHECK-RV32-NEXT: vslidedown.vi v8, v0, 8
+; CHECK-RV32-NEXT: csrr a2, vlenb
+; CHECK-RV32-NEXT: slli a2, a2, 5
+; CHECK-RV32-NEXT: add a2, sp, a2
+; CHECK-RV32-NEXT: addi a2, a2, 16
+; CHECK-RV32-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: li a2, 32
; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-RV32-NEXT: vmv.x.s a3, v0
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-RV32-NEXT: vcpop.m a4, v0
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vsrl.vx v16, v0, a2
+; CHECK-RV32-NEXT: vsrl.vx v8, v0, a2
+; CHECK-RV32-NEXT: csrr a2, vlenb
+; CHECK-RV32-NEXT: slli a2, a2, 5
+; CHECK-RV32-NEXT: add a2, sp, a2
+; CHECK-RV32-NEXT: addi a2, a2, 16
+; CHECK-RV32-NEXT: vl1r.v v9, (a2) # vscale x 8-byte Folded Reload
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; CHECK-RV32-NEXT: vcpop.m a2, v7
+; CHECK-RV32-NEXT: vcpop.m a2, v9
; CHECK-RV32-NEXT: vsetvli zero, a4, e16, m8, ta, ma
; CHECK-RV32-NEXT: vle16.v v24, (a0)
; CHECK-RV32-NEXT: csrr a5, vlenb
@@ -673,48 +725,58 @@ define <128 x i16> @test_expandload_v128i16(ptr %base, <128 x i1> %mask, <128 x
; CHECK-RV32-NEXT: addi a5, a5, 16
; CHECK-RV32-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: vsetvli zero, a4, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vmv.x.s a4, v16
+; CHECK-RV32-NEXT: vmv.x.s a4, v8
; CHECK-RV32-NEXT: cpop a4, a4
; CHECK-RV32-NEXT: cpop a3, a3
; CHECK-RV32-NEXT: add a3, a3, a4
; CHECK-RV32-NEXT: slli a3, a3, 1
; CHECK-RV32-NEXT: add a0, a0, a3
; CHECK-RV32-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-RV32-NEXT: vle16.v v16, (a0)
+; CHECK-RV32-NEXT: vle16.v v24, (a0)
; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: slli a0, a0, 3
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-RV32-NEXT: viota.m v24, v0
; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: slli a0, a0, 4
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: vrgather.vv v8, v16, v24, v0.t
+; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vrgather.vv v16, v8, v24, v0.t
; CHECK-RV32-NEXT: addi a0, sp, 16
-; CHECK-RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: viota.m v8, v7
-; CHECK-RV32-NEXT: vmv1r.v v0, v7
+; CHECK-RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: csrr a0, vlenb
+; CHECK-RV32-NEXT: slli a0, a0, 5
+; CHECK-RV32-NEXT: add a0, sp, a0
+; CHECK-RV32-NEXT: addi a0, a0, 16
+; CHECK-RV32-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV32-NEXT: viota.m v16, v24
+; CHECK-RV32-NEXT: csrr a0, vlenb
+; CHECK-RV32-NEXT: slli a0, a0, 5
+; CHECK-RV32-NEXT: add a0, sp, a0
+; CHECK-RV32-NEXT: addi a0, a0, 16
+; CHECK-RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: li a1, 24
; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: slli a0, a0, 3
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: vrgather.vv v24, v16, v8, v0.t
+; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vrgather.vv v8, v24, v16, v0.t
+; CHECK-RV32-NEXT: vmv.v.v v16, v8
; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: vmv.v.v v16, v24
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 5
+; CHECK-RV32-NEXT: slli a1, a0, 5
+; CHECK-RV32-NEXT: add a0, a1, a0
; CHECK-RV32-NEXT: add sp, sp, a0
; CHECK-RV32-NEXT: .cfi_def_cfa sp, 16
; CHECK-RV32-NEXT: addi sp, sp, 16
@@ -726,9 +788,10 @@ define <128 x i16> @test_expandload_v128i16(ptr %base, <128 x i1> %mask, <128 x
; CHECK-RV64-NEXT: addi sp, sp, -16
; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV64-NEXT: csrr a1, vlenb
-; CHECK-RV64-NEXT: slli a1, a1, 5
+; CHECK-RV64-NEXT: slli a2, a1, 5
+; CHECK-RV64-NEXT: add a1, a2, a1
; CHECK-RV64-NEXT: sub sp, sp, a1
-; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; CHECK-RV64-NEXT: csrr a1, vlenb
; CHECK-RV64-NEXT: slli a1, a1, 3
; CHECK-RV64-NEXT: add a1, sp, a1
@@ -736,14 +799,25 @@ define <128 x i16> @test_expandload_v128i16(ptr %base, <128 x i1> %mask, <128 x
; CHECK-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: li a1, 64
; CHECK-RV64-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v7, v0, 8
+; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 8
+; CHECK-RV64-NEXT: csrr a2, vlenb
+; CHECK-RV64-NEXT: slli a2, a2, 5
+; CHECK-RV64-NEXT: add a2, sp, a2
+; CHECK-RV64-NEXT: addi a2, a2, 16
+; CHECK-RV64-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-RV64-NEXT: vcpop.m a2, v0
-; CHECK-RV64-NEXT: vcpop.m a3, v7
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 16
+; CHECK-RV64-NEXT: vl1r.v v24, (a3) # vscale x 8-byte Folded Reload
+; CHECK-RV64-NEXT: vcpop.m a3, v24
; CHECK-RV64-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-RV64-NEXT: vle16.v v24, (a0)
; CHECK-RV64-NEXT: csrr a4, vlenb
-; CHECK-RV64-NEXT: slli a4, a4, 4
+; CHECK-RV64-NEXT: li a5, 24
+; CHECK-RV64-NEXT: mul a4, a4, a5
; CHECK-RV64-NEXT: add a4, sp, a4
; CHECK-RV64-NEXT: addi a4, a4, 16
; CHECK-RV64-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
@@ -752,49 +826,49 @@ define <128 x i16> @test_expandload_v128i16(ptr %base, <128 x i1> %mask, <128 x
; CHECK-RV64-NEXT: vsetvli zero, a3, e16, m8, ta, ma
; CHECK-RV64-NEXT: vle16.v v24, (a0)
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a2, 24
-; CHECK-RV64-NEXT: mul a0, a0, a2
+; CHECK-RV64-NEXT: slli a0, a0, 4
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a1, e16, m8, ta, mu
; CHECK-RV64-NEXT: viota.m v24, v0
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 4
+; CHECK-RV64-NEXT: li a1, 24
+; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: viota.m v16, v7
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 4
+; CHECK-RV64-NEXT: slli a0, a0, 5
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: vmv1r.v v0, v7
+; CHECK-RV64-NEXT: vl1r.v v7, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV64-NEXT: viota.m v8, v7
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 24
-; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: slli a0, a0, 5
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 3
+; CHECK-RV64-NEXT: slli a0, a0, 4
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 4
+; CHECK-RV64-NEXT: slli a0, a0, 3
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV64-NEXT: vrgather.vv v16, v24, v8, v0.t
+; CHECK-RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vrgather.vv v24, v16, v8, v0.t
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vmv.v.v v16, v24
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 5
+; CHECK-RV64-NEXT: slli a1, a0, 5
+; CHECK-RV64-NEXT: add a0, a1, a0
; CHECK-RV64-NEXT: add sp, sp, a0
; CHECK-RV64-NEXT: .cfi_def_cfa sp, 16
; CHECK-RV64-NEXT: addi sp, sp, 16
@@ -1000,9 +1074,10 @@ define <64 x i32> @test_expandload_v64i32(ptr %base, <64 x i1> %mask, <64 x i32>
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: csrr a1, vlenb
-; CHECK-RV32-NEXT: slli a1, a1, 5
+; CHECK-RV32-NEXT: slli a2, a1, 5
+; CHECK-RV32-NEXT: add a1, a2, a1
; CHECK-RV32-NEXT: sub sp, sp, a1
-; CHECK-RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; CHECK-RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; CHECK-RV32-NEXT: csrr a1, vlenb
; CHECK-RV32-NEXT: slli a1, a1, 3
; CHECK-RV32-NEXT: add a1, sp, a1
@@ -1010,14 +1085,25 @@ define <64 x i32> @test_expandload_v64i32(ptr %base, <64 x i1> %mask, <64 x i32>
; CHECK-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: li a1, 32
; CHECK-RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v7, v0, 4
+; CHECK-RV32-NEXT: vslidedown.vi v24, v0, 4
+; CHECK-RV32-NEXT: csrr a2, vlenb
+; CHECK-RV32-NEXT: slli a2, a2, 5
+; CHECK-RV32-NEXT: add a2, sp, a2
+; CHECK-RV32-NEXT: addi a2, a2, 16
+; CHECK-RV32-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vcpop.m a2, v0
-; CHECK-RV32-NEXT: vcpop.m a3, v7
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 16
+; CHECK-RV32-NEXT: vl1r.v v24, (a3) # vscale x 8-byte Folded Reload
+; CHECK-RV32-NEXT: vcpop.m a3, v24
; CHECK-RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-RV32-NEXT: vle32.v v24, (a0)
; CHECK-RV32-NEXT: csrr a4, vlenb
-; CHECK-RV32-NEXT: slli a4, a4, 4
+; CHECK-RV32-NEXT: li a5, 24
+; CHECK-RV32-NEXT: mul a4, a4, a5
; CHECK-RV32-NEXT: add a4, sp, a4
; CHECK-RV32-NEXT: addi a4, a4, 16
; CHECK-RV32-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
@@ -1026,49 +1112,49 @@ define <64 x i32> @test_expandload_v64i32(ptr %base, <64 x i1> %mask, <64 x i32>
; CHECK-RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-RV32-NEXT: vle32.v v24, (a0)
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: li a2, 24
-; CHECK-RV32-NEXT: mul a0, a0, a2
+; CHECK-RV32-NEXT: slli a0, a0, 4
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
; CHECK-RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-RV32-NEXT: viota.m v24, v0
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 4
+; CHECK-RV32-NEXT: li a1, 24
+; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
; CHECK-RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: viota.m v16, v7
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 4
+; CHECK-RV32-NEXT: slli a0, a0, 5
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: vmv1r.v v0, v7
+; CHECK-RV32-NEXT: vl1r.v v7, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV32-NEXT: viota.m v8, v7
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: li a1, 24
-; CHECK-RV32-NEXT: mul a0, a0, a1
+; CHECK-RV32-NEXT: slli a0, a0, 5
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 3
+; CHECK-RV32-NEXT: slli a0, a0, 4
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
; CHECK-RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 4
+; CHECK-RV32-NEXT: slli a0, a0, 3
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: vrgather.vv v16, v24, v8, v0.t
+; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vrgather.vv v24, v16, v8, v0.t
; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv.v.v v16, v24
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 5
+; CHECK-RV32-NEXT: slli a1, a0, 5
+; CHECK-RV32-NEXT: add a0, a1, a0
; CHECK-RV32-NEXT: add sp, sp, a0
; CHECK-RV32-NEXT: .cfi_def_cfa sp, 16
; CHECK-RV32-NEXT: addi sp, sp, 16
@@ -1080,17 +1166,24 @@ define <64 x i32> @test_expandload_v64i32(ptr %base, <64 x i1> %mask, <64 x i32>
; CHECK-RV64-NEXT: addi sp, sp, -16
; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV64-NEXT: csrr a1, vlenb
-; CHECK-RV64-NEXT: slli a1, a1, 5
+; CHECK-RV64-NEXT: slli a2, a1, 5
+; CHECK-RV64-NEXT: add a1, a2, a1
; CHECK-RV64-NEXT: sub sp, sp, a1
-; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; CHECK-RV64-NEXT: csrr a1, vlenb
-; CHECK-RV64-NEXT: slli a1, a1, 4
+; CHECK-RV64-NEXT: li a2, 24
+; CHECK-RV64-NEXT: mul a1, a1, a2
; CHECK-RV64-NEXT: add a1, sp, a1
; CHECK-RV64-NEXT: addi a1, a1, 16
; CHECK-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: li a1, 32
; CHECK-RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v7, v0, 4
+; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 4
+; CHECK-RV64-NEXT: csrr a2, vlenb
+; CHECK-RV64-NEXT: slli a2, a2, 5
+; CHECK-RV64-NEXT: add a2, sp, a2
+; CHECK-RV64-NEXT: addi a2, a2, 16
+; CHECK-RV64-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-RV64-NEXT: vmv.x.s a2, v0
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
@@ -1098,63 +1191,66 @@ define <64 x i32> @test_expandload_v64i32(ptr %base, <64 x i1> %mask, <64 x i32>
; CHECK-RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-RV64-NEXT: vle32.v v24, (a0)
; CHECK-RV64-NEXT: csrr a3, vlenb
-; CHECK-RV64-NEXT: li a4, 24
-; CHECK-RV64-NEXT: mul a3, a3, a4
+; CHECK-RV64-NEXT: slli a3, a3, 4
; CHECK-RV64-NEXT: add a3, sp, a3
; CHECK-RV64-NEXT: addi a3, a3, 16
; CHECK-RV64-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 16
+; CHECK-RV64-NEXT: vl1r.v v24, (a3) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-RV64-NEXT: vcpop.m a3, v7
+; CHECK-RV64-NEXT: vcpop.m a3, v24
; CHECK-RV64-NEXT: cpopw a2, a2
; CHECK-RV64-NEXT: slli a2, a2, 2
; CHECK-RV64-NEXT: add a0, a0, a2
; CHECK-RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; CHECK-RV64-NEXT: vle32.v v16, (a0)
+; CHECK-RV64-NEXT: vle32.v v24, (a0)
; CHECK-RV64-NEXT: csrr a0, vlenb
; CHECK-RV64-NEXT: slli a0, a0, 3
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-RV64-NEXT: viota.m v24, v0
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 24
-; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: slli a0, a0, 4
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: viota.m v16, v7
-; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 24
-; CHECK-RV64-NEXT: mul a0, a0, a1
-; CHECK-RV64-NEXT: add a0, sp, a0
-; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: vmv1r.v v0, v7
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 4
+; CHECK-RV64-NEXT: slli a0, a0, 5
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV64-NEXT: viota.m v16, v24
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 3
+; CHECK-RV64-NEXT: slli a0, a0, 5
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
; CHECK-RV64-NEXT: li a1, 24
; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV64-NEXT: vrgather.vv v16, v24, v8, v0.t
+; CHECK-RV64-NEXT: csrr a0, vlenb
+; CHECK-RV64-NEXT: slli a0, a0, 3
+; CHECK-RV64-NEXT: add a0, sp, a0
+; CHECK-RV64-NEXT: addi a0, a0, 16
+; CHECK-RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vrgather.vv v8, v24, v16, v0.t
+; CHECK-RV64-NEXT: vmv.v.v v16, v8
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 5
+; CHECK-RV64-NEXT: slli a1, a0, 5
+; CHECK-RV64-NEXT: add a0, a1, a0
; CHECK-RV64-NEXT: add sp, sp, a0
; CHECK-RV64-NEXT: .cfi_def_cfa sp, 16
; CHECK-RV64-NEXT: addi sp, sp, 16
@@ -1322,9 +1418,10 @@ define <32 x i64> @test_expandload_v32i64(ptr %base, <32 x i1> %mask, <32 x i64>
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: csrr a1, vlenb
-; CHECK-RV32-NEXT: slli a1, a1, 5
+; CHECK-RV32-NEXT: slli a2, a1, 5
+; CHECK-RV32-NEXT: add a1, a2, a1
; CHECK-RV32-NEXT: sub sp, sp, a1
-; CHECK-RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; CHECK-RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; CHECK-RV32-NEXT: csrr a1, vlenb
; CHECK-RV32-NEXT: slli a1, a1, 4
; CHECK-RV32-NEXT: add a1, sp, a1
@@ -1342,13 +1439,23 @@ define <32 x i64> @test_expandload_v32i64(ptr %base, <32 x i1> %mask, <32 x i64>
; CHECK-RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: vmv.x.s a1, v0
; CHECK-RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v7, v0, 2
+; CHECK-RV32-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-RV32-NEXT: csrr a2, vlenb
+; CHECK-RV32-NEXT: slli a2, a2, 5
+; CHECK-RV32-NEXT: add a2, sp, a2
+; CHECK-RV32-NEXT: addi a2, a2, 16
+; CHECK-RV32-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: zext.h a1, a1
; CHECK-RV32-NEXT: cpop a1, a1
; CHECK-RV32-NEXT: slli a1, a1, 3
; CHECK-RV32-NEXT: add a0, a0, a1
+; CHECK-RV32-NEXT: csrr a1, vlenb
+; CHECK-RV32-NEXT: slli a1, a1, 5
+; CHECK-RV32-NEXT: add a1, sp, a1
+; CHECK-RV32-NEXT: addi a1, a1, 16
+; CHECK-RV32-NEXT: vl1r.v v24, (a1) # vscale x 8-byte Folded Reload
; CHECK-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-RV32-NEXT: vcpop.m a1, v7
+; CHECK-RV32-NEXT: vcpop.m a1, v24
; CHECK-RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-RV32-NEXT: vle64.v v16, (a0)
; CHECK-RV32-NEXT: csrr a0, vlenb
@@ -1357,45 +1464,44 @@ define <32 x i64> @test_expandload_v32i64(ptr %base, <32 x i1> %mask, <32 x i64>
; CHECK-RV32-NEXT: addi a0, a0, 16
; CHECK-RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; CHECK-RV32-NEXT: viota.m v24, v0
+; CHECK-RV32-NEXT: viota.m v16, v0
; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: li a1, 24
; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: vrgather.vv v8, v16, v24, v0.t
+; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vrgather.vv v8, v24, v16, v0.t
; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: viota.m v16, v7
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: li a1, 24
-; CHECK-RV32-NEXT: mul a0, a0, a1
+; CHECK-RV32-NEXT: slli a0, a0, 5
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: vmv1r.v v0, v7
+; CHECK-RV32-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV32-NEXT: viota.m v16, v24
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 4
+; CHECK-RV32-NEXT: slli a0, a0, 5
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 3
+; CHECK-RV32-NEXT: slli a0, a0, 4
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: li a1, 24
-; CHECK-RV32-NEXT: mul a0, a0, a1
+; CHECK-RV32-NEXT: slli a0, a0, 3
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: vrgather.vv v16, v24, v8, v0.t
+; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vrgather.vv v8, v24, v16, v0.t
+; CHECK-RV32-NEXT: vmv.v.v v16, v8
; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 5
+; CHECK-RV32-NEXT: slli a1, a0, 5
+; CHECK-RV32-NEXT: add a0, a1, a0
; CHECK-RV32-NEXT: add sp, sp, a0
; CHECK-RV32-NEXT: .cfi_def_cfa sp, 16
; CHECK-RV32-NEXT: addi sp, sp, 16
@@ -1407,9 +1513,10 @@ define <32 x i64> @test_expandload_v32i64(ptr %base, <32 x i1> %mask, <32 x i64>
; CHECK-RV64-NEXT: addi sp, sp, -16
; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV64-NEXT: csrr a1, vlenb
-; CHECK-RV64-NEXT: slli a1, a1, 5
+; CHECK-RV64-NEXT: slli a2, a1, 5
+; CHECK-RV64-NEXT: add a1, a2, a1
; CHECK-RV64-NEXT: sub sp, sp, a1
-; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; CHECK-RV64-NEXT: csrr a1, vlenb
; CHECK-RV64-NEXT: slli a1, a1, 4
; CHECK-RV64-NEXT: add a1, sp, a1
@@ -1427,13 +1534,23 @@ define <32 x i64> @test_expandload_v32i64(ptr %base, <32 x i1> %mask, <32 x i64>
; CHECK-RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: vmv.x.s a1, v0
; CHECK-RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v7, v0, 2
+; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-RV64-NEXT: csrr a2, vlenb
+; CHECK-RV64-NEXT: slli a2, a2, 5
+; CHECK-RV64-NEXT: add a2, sp, a2
+; CHECK-RV64-NEXT: addi a2, a2, 16
+; CHECK-RV64-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: zext.h a1, a1
; CHECK-RV64-NEXT: cpopw a1, a1
; CHECK-RV64-NEXT: slli a1, a1, 3
; CHECK-RV64-NEXT: add a0, a0, a1
+; CHECK-RV64-NEXT: csrr a1, vlenb
+; CHECK-RV64-NEXT: slli a1, a1, 5
+; CHECK-RV64-NEXT: add a1, sp, a1
+; CHECK-RV64-NEXT: addi a1, a1, 16
+; CHECK-RV64-NEXT: vl1r.v v24, (a1) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-RV64-NEXT: vcpop.m a1, v7
+; CHECK-RV64-NEXT: vcpop.m a1, v24
; CHECK-RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-RV64-NEXT: vle64.v v16, (a0)
; CHECK-RV64-NEXT: csrr a0, vlenb
@@ -1442,45 +1559,44 @@ define <32 x i64> @test_expandload_v32i64(ptr %base, <32 x i1> %mask, <32 x i64>
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
-; CHECK-RV64-NEXT: viota.m v24, v0
+; CHECK-RV64-NEXT: viota.m v16, v0
; CHECK-RV64-NEXT: csrr a0, vlenb
; CHECK-RV64-NEXT: li a1, 24
; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV64-NEXT: vrgather.vv v8, v16, v24, v0.t
+; CHECK-RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vrgather.vv v8, v24, v16, v0.t
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: viota.m v16, v7
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 24
-; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: slli a0, a0, 5
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: vmv1r.v v0, v7
+; CHECK-RV64-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV64-NEXT: viota.m v16, v24
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 4
+; CHECK-RV64-NEXT: slli a0, a0, 5
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 3
+; CHECK-RV64-NEXT: slli a0, a0, 4
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 24
-; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: slli a0, a0, 3
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV64-NEXT: vrgather.vv v16, v24, v8, v0.t
+; CHECK-RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vrgather.vv v8, v24, v16, v0.t
+; CHECK-RV64-NEXT: vmv.v.v v16, v8
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 5
+; CHECK-RV64-NEXT: slli a1, a0, 5
+; CHECK-RV64-NEXT: add a0, a1, a0
; CHECK-RV64-NEXT: add sp, sp, a0
; CHECK-RV64-NEXT: .cfi_def_cfa sp, 16
; CHECK-RV64-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
index 15417da962bd3..62dadfe936e44 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
@@ -139,6 +139,7 @@ define i1 @extractelt_nxv128i1(ptr %x, i64 %idx) nounwind {
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: sub sp, sp, a3
; RV32-NEXT: andi sp, sp, -64
+; RV32-NEXT: addi a3, sp, 64
; RV32-NEXT: vl8r.v v8, (a0)
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a0, a0, a2
@@ -146,12 +147,12 @@ define i1 @extractelt_nxv128i1(ptr %x, i64 %idx) nounwind {
; RV32-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-NEXT: vmseq.vi v0, v8, 0
; RV32-NEXT: vmv.v.i v8, 0
-; RV32-NEXT: vmerge.vim v24, v8, 1, v0
-; RV32-NEXT: vmseq.vi v0, v16, 0
-; RV32-NEXT: addi a0, sp, 64
-; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: add a2, a0, a2
-; RV32-NEXT: vs8r.v v24, (a0)
+; RV32-NEXT: add a1, a3, a1
+; RV32-NEXT: vmseq.vi v25, v16, 0
+; RV32-NEXT: vmerge.vim v16, v8, 1, v0
+; RV32-NEXT: vs8r.v v16, (a3)
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: vmv1r.v v0, v25
; RV32-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-NEXT: vs8r.v v8, (a2)
; RV32-NEXT: lbu a0, 0(a1)
@@ -178,6 +179,7 @@ define i1 @extractelt_nxv128i1(ptr %x, i64 %idx) nounwind {
; RV64-NEXT: slli a3, a3, 4
; RV64-NEXT: sub sp, sp, a3
; RV64-NEXT: andi sp, sp, -64
+; RV64-NEXT: addi a3, sp, 64
; RV64-NEXT: vl8r.v v8, (a0)
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: add a0, a0, a2
@@ -185,12 +187,12 @@ define i1 @extractelt_nxv128i1(ptr %x, i64 %idx) nounwind {
; RV64-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV64-NEXT: vmseq.vi v0, v8, 0
; RV64-NEXT: vmv.v.i v8, 0
-; RV64-NEXT: vmerge.vim v24, v8, 1, v0
-; RV64-NEXT: vmseq.vi v0, v16, 0
-; RV64-NEXT: addi a0, sp, 64
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: add a2, a0, a2
-; RV64-NEXT: vs8r.v v24, (a0)
+; RV64-NEXT: add a1, a3, a1
+; RV64-NEXT: vmseq.vi v25, v16, 0
+; RV64-NEXT: vmerge.vim v16, v8, 1, v0
+; RV64-NEXT: vs8r.v v16, (a3)
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: vmv1r.v v0, v25
; RV64-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-NEXT: vs8r.v v8, (a2)
; RV64-NEXT: lbu a0, 0(a1)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
index 1f4eaea90628b..10fd69db9eaa0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
@@ -12,10 +12,10 @@ define <vscale x 1 x half> @ceil_nxv1f16(<vscale x 1 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -35,10 +35,10 @@ define <vscale x 2 x half> @ceil_nxv2f16(<vscale x 2 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -58,10 +58,10 @@ define <vscale x 4 x half> @ceil_nxv4f16(<vscale x 4 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -81,10 +81,10 @@ define <vscale x 8 x half> @ceil_nxv8f16(<vscale x 8 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -104,10 +104,10 @@ define <vscale x 16 x half> @ceil_nxv16f16(<vscale x 16 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -127,10 +127,10 @@ define <vscale x 32 x half> @ceil_nxv32f16(<vscale x 32 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -150,9 +150,9 @@ define <vscale x 1 x float> @ceil_nxv1f32(<vscale x 1 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -172,9 +172,9 @@ define <vscale x 2 x float> @ceil_nxv2f32(<vscale x 2 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -194,9 +194,9 @@ define <vscale x 4 x float> @ceil_nxv4f32(<vscale x 4 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -216,9 +216,9 @@ define <vscale x 8 x float> @ceil_nxv8f32(<vscale x 8 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -238,9 +238,9 @@ define <vscale x 16 x float> @ceil_nxv16f32(<vscale x 16 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -260,9 +260,9 @@ define <vscale x 1 x double> @ceil_nxv1f64(<vscale x 1 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI11_0)
; RV32-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -278,10 +278,10 @@ define <vscale x 1 x double> @ceil_nxv1f64(<vscale x 1 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v9, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vfabs.v v9, v8
+; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -301,9 +301,9 @@ define <vscale x 2 x double> @ceil_nxv2f64(<vscale x 2 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: vmflt.vf v0, v10, fa5
-; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -319,10 +319,10 @@ define <vscale x 2 x double> @ceil_nxv2f64(<vscale x 2 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v10, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vfabs.v v10, v8
+; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -342,9 +342,9 @@ define <vscale x 4 x double> @ceil_nxv4f64(<vscale x 4 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vfabs.v v12, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
-; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -360,10 +360,10 @@ define <vscale x 4 x double> @ceil_nxv4f64(<vscale x 4 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v12, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -383,9 +383,9 @@ define <vscale x 8 x double> @ceil_nxv8f64(<vscale x 8 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI14_0)
; RV32-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vfabs.v v16, v8
; RV32-NEXT: vmflt.vf v0, v16, fa5
-; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -401,10 +401,10 @@ define <vscale x 8 x double> @ceil_nxv8f64(<vscale x 8 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v16, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v16, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vfabs.v v16, v8
+; RV64-NEXT: vmflt.vf v0, v16, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64-NEXT: fsrm a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
index 504930f07bb13..2df2afde55df7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
@@ -18,11 +18,11 @@ define <vscale x 1 x bfloat> @ceil_nxv1bf16(<vscale x 1 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -41,11 +41,11 @@ define <vscale x 2 x bfloat> @ceil_nxv2bf16(<vscale x 2 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -64,11 +64,11 @@ define <vscale x 4 x bfloat> @ceil_nxv4bf16(<vscale x 4 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v8, v10
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -87,11 +87,11 @@ define <vscale x 8 x bfloat> @ceil_nxv8bf16(<vscale x 8 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfabs.v v8, v12
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -110,11 +110,11 @@ define <vscale x 16 x bfloat> @ceil_nxv16bf16(<vscale x 16 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v8, v16
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -133,11 +133,11 @@ define <vscale x 32 x bfloat> @ceil_nxv32bf16(<vscale x 32 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v24, v16
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v24, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -172,8 +172,8 @@ define <vscale x 1 x half> @ceil_nxv1f16(<vscale x 1 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 3
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -186,11 +186,11 @@ define <vscale x 1 x half> @ceil_nxv1f16(<vscale x 1 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -211,8 +211,8 @@ define <vscale x 2 x half> @ceil_nxv2f16(<vscale x 2 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 3
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -225,11 +225,11 @@ define <vscale x 2 x half> @ceil_nxv2f16(<vscale x 2 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -250,8 +250,8 @@ define <vscale x 4 x half> @ceil_nxv4f16(<vscale x 4 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 3
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -264,11 +264,11 @@ define <vscale x 4 x half> @ceil_nxv4f16(<vscale x 4 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -289,8 +289,8 @@ define <vscale x 8 x half> @ceil_nxv8f16(<vscale x 8 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 3
+; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -303,11 +303,11 @@ define <vscale x 8 x half> @ceil_nxv8f16(<vscale x 8 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -328,8 +328,8 @@ define <vscale x 16 x half> @ceil_nxv16f16(<vscale x 16 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: fsrmi a0, 3
+; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -342,11 +342,11 @@ define <vscale x 16 x half> @ceil_nxv16f16(<vscale x 16 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v16
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -367,8 +367,8 @@ define <vscale x 32 x half> @ceil_nxv32f16(<vscale x 32 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: fsrmi a0, 3
+; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -381,11 +381,11 @@ define <vscale x 32 x half> @ceil_nxv32f16(<vscale x 32 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v24, v16
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -419,8 +419,8 @@ define <vscale x 1 x float> @ceil_nxv1f32(<vscale x 1 x float> %x) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -438,8 +438,8 @@ define <vscale x 2 x float> @ceil_nxv2f32(<vscale x 2 x float> %x) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -457,8 +457,8 @@ define <vscale x 4 x float> @ceil_nxv4f32(<vscale x 4 x float> %x) {
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -476,8 +476,8 @@ define <vscale x 8 x float> @ceil_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -495,8 +495,8 @@ define <vscale x 16 x float> @ceil_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -514,8 +514,8 @@ define <vscale x 1 x double> @ceil_nxv1f64(<vscale x 1 x double> %x) {
; RV32ZFH-NEXT: fld fa5, %lo(.LCPI17_0)(a0)
; RV32ZFH-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32ZFH-NEXT: vfabs.v v9, v8
-; RV32ZFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZFH-NEXT: fsrmi a0, 3
+; RV32ZFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZFH-NEXT: fsrm a0
; RV32ZFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -530,8 +530,8 @@ define <vscale x 1 x double> @ceil_nxv1f64(<vscale x 1 x double> %x) {
; RV64ZFH-NEXT: li a0, 1075
; RV64ZFH-NEXT: slli a0, a0, 52
; RV64ZFH-NEXT: fmv.d.x fa5, a0
-; RV64ZFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZFH-NEXT: fsrmi a0, 3
+; RV64ZFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZFH-NEXT: fsrm a0
; RV64ZFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -545,8 +545,8 @@ define <vscale x 1 x double> @ceil_nxv1f64(<vscale x 1 x double> %x) {
; RV32ZFHMIN-NEXT: fld fa5, %lo(.LCPI17_0)(a0)
; RV32ZFHMIN-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32ZFHMIN-NEXT: vfabs.v v9, v8
-; RV32ZFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZFHMIN-NEXT: fsrmi a0, 3
+; RV32ZFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZFHMIN-NEXT: fsrm a0
; RV32ZFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -561,8 +561,8 @@ define <vscale x 1 x double> @ceil_nxv1f64(<vscale x 1 x double> %x) {
; RV64ZFHMIN-NEXT: li a0, 1075
; RV64ZFHMIN-NEXT: slli a0, a0, 52
; RV64ZFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZFHMIN-NEXT: fsrmi a0, 3
+; RV64ZFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZFHMIN-NEXT: fsrm a0
; RV64ZFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -580,8 +580,8 @@ define <vscale x 2 x double> @ceil_nxv2f64(<vscale x 2 x double> %x) {
; RV32ZFH-NEXT: fld fa5, %lo(.LCPI18_0)(a0)
; RV32ZFH-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV32ZFH-NEXT: vfabs.v v10, v8
-; RV32ZFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZFH-NEXT: fsrmi a0, 3
+; RV32ZFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZFH-NEXT: fsrm a0
; RV32ZFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -596,8 +596,8 @@ define <vscale x 2 x double> @ceil_nxv2f64(<vscale x 2 x double> %x) {
; RV64ZFH-NEXT: li a0, 1075
; RV64ZFH-NEXT: slli a0, a0, 52
; RV64ZFH-NEXT: fmv.d.x fa5, a0
-; RV64ZFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZFH-NEXT: fsrmi a0, 3
+; RV64ZFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZFH-NEXT: fsrm a0
; RV64ZFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -611,8 +611,8 @@ define <vscale x 2 x double> @ceil_nxv2f64(<vscale x 2 x double> %x) {
; RV32ZFHMIN-NEXT: fld fa5, %lo(.LCPI18_0)(a0)
; RV32ZFHMIN-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV32ZFHMIN-NEXT: vfabs.v v10, v8
-; RV32ZFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZFHMIN-NEXT: fsrmi a0, 3
+; RV32ZFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZFHMIN-NEXT: fsrm a0
; RV32ZFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -627,8 +627,8 @@ define <vscale x 2 x double> @ceil_nxv2f64(<vscale x 2 x double> %x) {
; RV64ZFHMIN-NEXT: li a0, 1075
; RV64ZFHMIN-NEXT: slli a0, a0, 52
; RV64ZFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZFHMIN-NEXT: fsrmi a0, 3
+; RV64ZFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZFHMIN-NEXT: fsrm a0
; RV64ZFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -646,8 +646,8 @@ define <vscale x 4 x double> @ceil_nxv4f64(<vscale x 4 x double> %x) {
; RV32ZFH-NEXT: fld fa5, %lo(.LCPI19_0)(a0)
; RV32ZFH-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32ZFH-NEXT: vfabs.v v12, v8
-; RV32ZFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZFH-NEXT: fsrmi a0, 3
+; RV32ZFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZFH-NEXT: fsrm a0
; RV32ZFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -662,8 +662,8 @@ define <vscale x 4 x double> @ceil_nxv4f64(<vscale x 4 x double> %x) {
; RV64ZFH-NEXT: li a0, 1075
; RV64ZFH-NEXT: slli a0, a0, 52
; RV64ZFH-NEXT: fmv.d.x fa5, a0
-; RV64ZFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZFH-NEXT: fsrmi a0, 3
+; RV64ZFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZFH-NEXT: fsrm a0
; RV64ZFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -677,8 +677,8 @@ define <vscale x 4 x double> @ceil_nxv4f64(<vscale x 4 x double> %x) {
; RV32ZFHMIN-NEXT: fld fa5, %lo(.LCPI19_0)(a0)
; RV32ZFHMIN-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32ZFHMIN-NEXT: vfabs.v v12, v8
-; RV32ZFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZFHMIN-NEXT: fsrmi a0, 3
+; RV32ZFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZFHMIN-NEXT: fsrm a0
; RV32ZFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -693,8 +693,8 @@ define <vscale x 4 x double> @ceil_nxv4f64(<vscale x 4 x double> %x) {
; RV64ZFHMIN-NEXT: li a0, 1075
; RV64ZFHMIN-NEXT: slli a0, a0, 52
; RV64ZFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZFHMIN-NEXT: fsrmi a0, 3
+; RV64ZFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZFHMIN-NEXT: fsrm a0
; RV64ZFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -712,8 +712,8 @@ define <vscale x 8 x double> @ceil_nxv8f64(<vscale x 8 x double> %x) {
; RV32ZFH-NEXT: fld fa5, %lo(.LCPI20_0)(a0)
; RV32ZFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32ZFH-NEXT: vfabs.v v16, v8
-; RV32ZFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZFH-NEXT: fsrmi a0, 3
+; RV32ZFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZFH-NEXT: fsrm a0
; RV32ZFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -728,8 +728,8 @@ define <vscale x 8 x double> @ceil_nxv8f64(<vscale x 8 x double> %x) {
; RV64ZFH-NEXT: li a0, 1075
; RV64ZFH-NEXT: slli a0, a0, 52
; RV64ZFH-NEXT: fmv.d.x fa5, a0
-; RV64ZFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZFH-NEXT: fsrmi a0, 3
+; RV64ZFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZFH-NEXT: fsrm a0
; RV64ZFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -743,8 +743,8 @@ define <vscale x 8 x double> @ceil_nxv8f64(<vscale x 8 x double> %x) {
; RV32ZFHMIN-NEXT: fld fa5, %lo(.LCPI20_0)(a0)
; RV32ZFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32ZFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZFHMIN-NEXT: fsrmi a0, 3
+; RV32ZFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZFHMIN-NEXT: fsrm a0
; RV32ZFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -759,8 +759,8 @@ define <vscale x 8 x double> @ceil_nxv8f64(<vscale x 8 x double> %x) {
; RV64ZFHMIN-NEXT: li a0, 1075
; RV64ZFHMIN-NEXT: slli a0, a0, 52
; RV64ZFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZFHMIN-NEXT: fsrmi a0, 3
+; RV64ZFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZFHMIN-NEXT: fsrm a0
; RV64ZFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
index 3a7de21c14390..2a961814daf53 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
@@ -12,10 +12,10 @@ define <vscale x 1 x half> @floor_nxv1f16(<vscale x 1 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -35,10 +35,10 @@ define <vscale x 2 x half> @floor_nxv2f16(<vscale x 2 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -58,10 +58,10 @@ define <vscale x 4 x half> @floor_nxv4f16(<vscale x 4 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -81,10 +81,10 @@ define <vscale x 8 x half> @floor_nxv8f16(<vscale x 8 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -104,10 +104,10 @@ define <vscale x 16 x half> @floor_nxv16f16(<vscale x 16 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -127,10 +127,10 @@ define <vscale x 32 x half> @floor_nxv32f16(<vscale x 32 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -150,9 +150,9 @@ define <vscale x 1 x float> @floor_nxv1f32(<vscale x 1 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -172,9 +172,9 @@ define <vscale x 2 x float> @floor_nxv2f32(<vscale x 2 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -194,9 +194,9 @@ define <vscale x 4 x float> @floor_nxv4f32(<vscale x 4 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -216,9 +216,9 @@ define <vscale x 8 x float> @floor_nxv8f32(<vscale x 8 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -238,9 +238,9 @@ define <vscale x 16 x float> @floor_nxv16f32(<vscale x 16 x float> %x) strictfp
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -260,9 +260,9 @@ define <vscale x 1 x double> @floor_nxv1f64(<vscale x 1 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI11_0)
; RV32-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 2
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: fsrmi a0, 2
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -278,10 +278,10 @@ define <vscale x 1 x double> @floor_nxv1f64(<vscale x 1 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v9, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 2
+; RV64-NEXT: vfabs.v v9, v8
+; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -301,9 +301,9 @@ define <vscale x 2 x double> @floor_nxv2f64(<vscale x 2 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 2
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: vmflt.vf v0, v10, fa5
-; RV32-NEXT: fsrmi a0, 2
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -319,10 +319,10 @@ define <vscale x 2 x double> @floor_nxv2f64(<vscale x 2 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v10, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: fsrmi a0, 2
+; RV64-NEXT: vfabs.v v10, v8
+; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -342,9 +342,9 @@ define <vscale x 4 x double> @floor_nxv4f64(<vscale x 4 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 2
; RV32-NEXT: vfabs.v v12, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
-; RV32-NEXT: fsrmi a0, 2
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -360,10 +360,10 @@ define <vscale x 4 x double> @floor_nxv4f64(<vscale x 4 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v12, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 2
+; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -383,9 +383,9 @@ define <vscale x 8 x double> @floor_nxv8f64(<vscale x 8 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI14_0)
; RV32-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 2
; RV32-NEXT: vfabs.v v16, v8
; RV32-NEXT: vmflt.vf v0, v16, fa5
-; RV32-NEXT: fsrmi a0, 2
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -401,10 +401,10 @@ define <vscale x 8 x double> @floor_nxv8f64(<vscale x 8 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v16, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v16, fa5
; RV64-NEXT: fsrmi a0, 2
+; RV64-NEXT: vfabs.v v16, v8
+; RV64-NEXT: vmflt.vf v0, v16, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64-NEXT: fsrm a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
index 326ac8c8c607d..ee93068c82114 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
@@ -18,11 +18,11 @@ define <vscale x 1 x bfloat> @floor_nxv1bf16(<vscale x 1 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -41,11 +41,11 @@ define <vscale x 2 x bfloat> @floor_nxv2bf16(<vscale x 2 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -64,11 +64,11 @@ define <vscale x 4 x bfloat> @floor_nxv4bf16(<vscale x 4 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v8, v10
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -87,11 +87,11 @@ define <vscale x 8 x bfloat> @floor_nxv8bf16(<vscale x 8 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfabs.v v8, v12
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -110,11 +110,11 @@ define <vscale x 16 x bfloat> @floor_nxv16bf16(<vscale x 16 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v8, v16
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -133,11 +133,11 @@ define <vscale x 32 x bfloat> @floor_nxv32bf16(<vscale x 32 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v24, v16
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v24, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -172,8 +172,8 @@ define <vscale x 1 x half> @floor_nxv1f16(<vscale x 1 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 2
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -186,11 +186,11 @@ define <vscale x 1 x half> @floor_nxv1f16(<vscale x 1 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -211,8 +211,8 @@ define <vscale x 2 x half> @floor_nxv2f16(<vscale x 2 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 2
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -225,11 +225,11 @@ define <vscale x 2 x half> @floor_nxv2f16(<vscale x 2 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -250,8 +250,8 @@ define <vscale x 4 x half> @floor_nxv4f16(<vscale x 4 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 2
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -264,11 +264,11 @@ define <vscale x 4 x half> @floor_nxv4f16(<vscale x 4 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -289,8 +289,8 @@ define <vscale x 8 x half> @floor_nxv8f16(<vscale x 8 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 2
+; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -303,11 +303,11 @@ define <vscale x 8 x half> @floor_nxv8f16(<vscale x 8 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -328,8 +328,8 @@ define <vscale x 16 x half> @floor_nxv16f16(<vscale x 16 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: fsrmi a0, 2
+; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -342,11 +342,11 @@ define <vscale x 16 x half> @floor_nxv16f16(<vscale x 16 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v16
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -367,8 +367,8 @@ define <vscale x 32 x half> @floor_nxv32f16(<vscale x 32 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: fsrmi a0, 2
+; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -381,11 +381,11 @@ define <vscale x 32 x half> @floor_nxv32f16(<vscale x 32 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v24, v16
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -419,8 +419,8 @@ define <vscale x 1 x float> @floor_nxv1f32(<vscale x 1 x float> %x) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -438,8 +438,8 @@ define <vscale x 2 x float> @floor_nxv2f32(<vscale x 2 x float> %x) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -457,8 +457,8 @@ define <vscale x 4 x float> @floor_nxv4f32(<vscale x 4 x float> %x) {
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -476,8 +476,8 @@ define <vscale x 8 x float> @floor_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -495,8 +495,8 @@ define <vscale x 16 x float> @floor_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -514,8 +514,8 @@ define <vscale x 1 x double> @floor_nxv1f64(<vscale x 1 x double> %x) {
; RV32ZFH-NEXT: fld fa5, %lo(.LCPI17_0)(a0)
; RV32ZFH-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32ZFH-NEXT: vfabs.v v9, v8
-; RV32ZFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZFH-NEXT: fsrmi a0, 2
+; RV32ZFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZFH-NEXT: fsrm a0
; RV32ZFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -530,8 +530,8 @@ define <vscale x 1 x double> @floor_nxv1f64(<vscale x 1 x double> %x) {
; RV64ZFH-NEXT: li a0, 1075
; RV64ZFH-NEXT: slli a0, a0, 52
; RV64ZFH-NEXT: fmv.d.x fa5, a0
-; RV64ZFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZFH-NEXT: fsrmi a0, 2
+; RV64ZFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZFH-NEXT: fsrm a0
; RV64ZFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -545,8 +545,8 @@ define <vscale x 1 x double> @floor_nxv1f64(<vscale x 1 x double> %x) {
; RV32ZFHMIN-NEXT: fld fa5, %lo(.LCPI17_0)(a0)
; RV32ZFHMIN-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32ZFHMIN-NEXT: vfabs.v v9, v8
-; RV32ZFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZFHMIN-NEXT: fsrmi a0, 2
+; RV32ZFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZFHMIN-NEXT: fsrm a0
; RV32ZFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -561,8 +561,8 @@ define <vscale x 1 x double> @floor_nxv1f64(<vscale x 1 x double> %x) {
; RV64ZFHMIN-NEXT: li a0, 1075
; RV64ZFHMIN-NEXT: slli a0, a0, 52
; RV64ZFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZFHMIN-NEXT: fsrmi a0, 2
+; RV64ZFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZFHMIN-NEXT: fsrm a0
; RV64ZFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -580,8 +580,8 @@ define <vscale x 2 x double> @floor_nxv2f64(<vscale x 2 x double> %x) {
; RV32ZFH-NEXT: fld fa5, %lo(.LCPI18_0)(a0)
; RV32ZFH-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV32ZFH-NEXT: vfabs.v v10, v8
-; RV32ZFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZFH-NEXT: fsrmi a0, 2
+; RV32ZFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZFH-NEXT: fsrm a0
; RV32ZFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -596,8 +596,8 @@ define <vscale x 2 x double> @floor_nxv2f64(<vscale x 2 x double> %x) {
; RV64ZFH-NEXT: li a0, 1075
; RV64ZFH-NEXT: slli a0, a0, 52
; RV64ZFH-NEXT: fmv.d.x fa5, a0
-; RV64ZFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZFH-NEXT: fsrmi a0, 2
+; RV64ZFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZFH-NEXT: fsrm a0
; RV64ZFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -611,8 +611,8 @@ define <vscale x 2 x double> @floor_nxv2f64(<vscale x 2 x double> %x) {
; RV32ZFHMIN-NEXT: fld fa5, %lo(.LCPI18_0)(a0)
; RV32ZFHMIN-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV32ZFHMIN-NEXT: vfabs.v v10, v8
-; RV32ZFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZFHMIN-NEXT: fsrmi a0, 2
+; RV32ZFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZFHMIN-NEXT: fsrm a0
; RV32ZFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -627,8 +627,8 @@ define <vscale x 2 x double> @floor_nxv2f64(<vscale x 2 x double> %x) {
; RV64ZFHMIN-NEXT: li a0, 1075
; RV64ZFHMIN-NEXT: slli a0, a0, 52
; RV64ZFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZFHMIN-NEXT: fsrmi a0, 2
+; RV64ZFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZFHMIN-NEXT: fsrm a0
; RV64ZFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -646,8 +646,8 @@ define <vscale x 4 x double> @floor_nxv4f64(<vscale x 4 x double> %x) {
; RV32ZFH-NEXT: fld fa5, %lo(.LCPI19_0)(a0)
; RV32ZFH-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32ZFH-NEXT: vfabs.v v12, v8
-; RV32ZFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZFH-NEXT: fsrmi a0, 2
+; RV32ZFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZFH-NEXT: fsrm a0
; RV32ZFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -662,8 +662,8 @@ define <vscale x 4 x double> @floor_nxv4f64(<vscale x 4 x double> %x) {
; RV64ZFH-NEXT: li a0, 1075
; RV64ZFH-NEXT: slli a0, a0, 52
; RV64ZFH-NEXT: fmv.d.x fa5, a0
-; RV64ZFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZFH-NEXT: fsrmi a0, 2
+; RV64ZFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZFH-NEXT: fsrm a0
; RV64ZFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -677,8 +677,8 @@ define <vscale x 4 x double> @floor_nxv4f64(<vscale x 4 x double> %x) {
; RV32ZFHMIN-NEXT: fld fa5, %lo(.LCPI19_0)(a0)
; RV32ZFHMIN-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32ZFHMIN-NEXT: vfabs.v v12, v8
-; RV32ZFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZFHMIN-NEXT: fsrmi a0, 2
+; RV32ZFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZFHMIN-NEXT: fsrm a0
; RV32ZFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -693,8 +693,8 @@ define <vscale x 4 x double> @floor_nxv4f64(<vscale x 4 x double> %x) {
; RV64ZFHMIN-NEXT: li a0, 1075
; RV64ZFHMIN-NEXT: slli a0, a0, 52
; RV64ZFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZFHMIN-NEXT: fsrmi a0, 2
+; RV64ZFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZFHMIN-NEXT: fsrm a0
; RV64ZFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -712,8 +712,8 @@ define <vscale x 8 x double> @floor_nxv8f64(<vscale x 8 x double> %x) {
; RV32ZFH-NEXT: fld fa5, %lo(.LCPI20_0)(a0)
; RV32ZFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32ZFH-NEXT: vfabs.v v16, v8
-; RV32ZFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZFH-NEXT: fsrmi a0, 2
+; RV32ZFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZFH-NEXT: fsrm a0
; RV32ZFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -728,8 +728,8 @@ define <vscale x 8 x double> @floor_nxv8f64(<vscale x 8 x double> %x) {
; RV64ZFH-NEXT: li a0, 1075
; RV64ZFH-NEXT: slli a0, a0, 52
; RV64ZFH-NEXT: fmv.d.x fa5, a0
-; RV64ZFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZFH-NEXT: fsrmi a0, 2
+; RV64ZFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZFH-NEXT: fsrm a0
; RV64ZFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -743,8 +743,8 @@ define <vscale x 8 x double> @floor_nxv8f64(<vscale x 8 x double> %x) {
; RV32ZFHMIN-NEXT: fld fa5, %lo(.LCPI20_0)(a0)
; RV32ZFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32ZFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZFHMIN-NEXT: fsrmi a0, 2
+; RV32ZFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZFHMIN-NEXT: fsrm a0
; RV32ZFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -759,8 +759,8 @@ define <vscale x 8 x double> @floor_nxv8f64(<vscale x 8 x double> %x) {
; RV64ZFHMIN-NEXT: li a0, 1075
; RV64ZFHMIN-NEXT: slli a0, a0, 52
; RV64ZFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZFHMIN-NEXT: fsrmi a0, 2
+; RV64ZFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZFHMIN-NEXT: fsrm a0
; RV64ZFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
index 7a337aa253805..4a6a1a90b3bd9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
@@ -117,42 +117,43 @@ define <512 x i8> @two_source(<512 x i8> %a, <512 x i8> %b) {
; CHECK-NEXT: vmv.x.s a2, v24
; CHECK-NEXT: li a3, 432
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vmv.v.x v8, a2
+; CHECK-NEXT: vmv.v.x v16, a2
; CHECK-NEXT: li a2, 431
; CHECK-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-NEXT: vslideup.vx v8, v0, a2
+; CHECK-NEXT: vslideup.vx v16, v0, a2
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v24, 4
; CHECK-NEXT: li a2, 466
; CHECK-NEXT: li a3, 465
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vse8.v v24, (a1)
+; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: lbu a1, 985(sp)
; CHECK-NEXT: vsetvli zero, a2, e8, m8, tu, ma
-; CHECK-NEXT: vslideup.vx v8, v0, a3
+; CHECK-NEXT: vslideup.vx v16, v0, a3
; CHECK-NEXT: li a2, 478
; CHECK-NEXT: lbu a3, 1012(sp)
; CHECK-NEXT: vmv.s.x v24, a1
; CHECK-NEXT: li a1, 477
; CHECK-NEXT: vsetvli zero, a2, e8, m8, tu, ma
-; CHECK-NEXT: vslideup.vx v8, v24, a1
+; CHECK-NEXT: vslideup.vx v16, v24, a1
; CHECK-NEXT: li a1, 501
-; CHECK-NEXT: lui a2, %hi(.LCPI2_1)
-; CHECK-NEXT: addi a2, a2, %lo(.LCPI2_1)
-; CHECK-NEXT: vsetivli zero, 8, e64, m1, ta, ma
-; CHECK-NEXT: vle64.v v0, (a2)
-; CHECK-NEXT: li a2, 500
-; CHECK-NEXT: vmv.s.x v24, a3
-; CHECK-NEXT: lui a3, %hi(.LCPI2_0)
-; CHECK-NEXT: addi a3, a3, %lo(.LCPI2_0)
+; CHECK-NEXT: lui a2, %hi(.LCPI2_0)
+; CHECK-NEXT: addi a2, a2, %lo(.LCPI2_0)
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vle8.v v16, (a3)
+; CHECK-NEXT: vle8.v v24, (a2)
+; CHECK-NEXT: li a2, 500
+; CHECK-NEXT: vmv.s.x v8, a3
+; CHECK-NEXT: lui a3, %hi(.LCPI2_1)
+; CHECK-NEXT: addi a3, a3, %lo(.LCPI2_1)
+; CHECK-NEXT: vsetivli zero, 8, e64, m1, ta, ma
+; CHECK-NEXT: vle64.v v0, (a3)
; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
-; CHECK-NEXT: vslideup.vx v8, v24, a2
+; CHECK-NEXT: vslideup.vx v16, v8, a2
; CHECK-NEXT: addi a1, sp, 1520
-; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
-; CHECK-NEXT: vrgather.vv v8, v24, v16, v0.t
+; CHECK-NEXT: vrgather.vv v16, v8, v24, v0.t
+; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: addi sp, s0, -1536
; CHECK-NEXT: .cfi_def_cfa sp, 1536
; CHECK-NEXT: ld ra, 1528(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
index f436bbb9a66ca..faf9e630b0e10 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
@@ -9,20 +9,20 @@ define <2 x i8> @vp_bitreverse_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vand.vi v9, v8, 15, v0.t
+; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
@@ -61,20 +61,20 @@ define <4 x i8> @vp_bitreverse_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vand.vi v9, v8, 15, v0.t
+; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
@@ -113,20 +113,20 @@ define <8 x i8> @vp_bitreverse_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vand.vi v9, v8, 15, v0.t
+; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
@@ -165,20 +165,20 @@ define <16 x i8> @vp_bitreverse_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vand.vi v9, v8, 15, v0.t
+; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: li a0, 51
; CHECK-NEXT: vsll.vi v9, v9, 4, v0.t
-; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
@@ -217,27 +217,27 @@ define <2 x i16> @vp_bitreverse_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %e
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
-; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: addi a0, a0, -241
+; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, -241
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
@@ -283,27 +283,27 @@ define <4 x i16> @vp_bitreverse_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %e
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
-; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: addi a0, a0, -241
+; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, -241
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
@@ -349,27 +349,27 @@ define <8 x i16> @vp_bitreverse_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %e
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
-; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: addi a0, a0, -241
+; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, -241
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
@@ -415,27 +415,27 @@ define <16 x i16> @vp_bitreverse_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroex
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t
-; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: addi a0, a0, -241
+; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
+; CHECK-NEXT: addi a0, a0, -241
; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: lui a0, 3
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
@@ -482,34 +482,34 @@ define <2 x i32> @vp_bitreverse_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %e
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
; CHECK-NEXT: vor.vv v9, v9, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v10, v8, 24, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: lui a0, 61681
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 209715
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
@@ -564,34 +564,34 @@ define <4 x i32> @vp_bitreverse_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %e
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
; CHECK-NEXT: vor.vv v9, v9, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v10, v8, 24, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: lui a0, 61681
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 209715
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
; CHECK-NEXT: ret
@@ -646,34 +646,34 @@ define <8 x i32> @vp_bitreverse_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %e
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v12, v8, 24, v0.t
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 24, v0.t
; CHECK-NEXT: vor.vv v10, v10, v12, v0.t
-; CHECK-NEXT: vand.vx v12, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v12, v8, 24, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: lui a0, 61681
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vsll.vi v12, v12, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: lui a0, 209715
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
@@ -728,34 +728,34 @@ define <16 x i32> @vp_bitreverse_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroex
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v16, v8, 24, v0.t
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vsrl.vi v16, v8, 24, v0.t
; CHECK-NEXT: vor.vv v12, v12, v16, v0.t
-; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
+; CHECK-NEXT: vsll.vi v16, v8, 24, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: lui a0, 61681
; CHECK-NEXT: addi a0, a0, -241
-; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: lui a0, 209715
; CHECK-NEXT: addi a0, a0, 819
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret
@@ -809,67 +809,68 @@ define <2 x i64> @vp_bitreverse_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %e
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a4, 1044480
-; RV32-NEXT: li a3, 56
-; RV32-NEXT: lui a5, 16
-; RV32-NEXT: li a2, 40
-; RV32-NEXT: lui a1, 4080
+; RV32-NEXT: lui a1, 1044480
+; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a3, 16
+; RV32-NEXT: li a4, 40
+; RV32-NEXT: lui a5, 4080
; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a4, 8(sp)
+; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; RV32-NEXT: vsrl.vi v9, v8, 24, v0.t
+; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: vsll.vx v10, v8, a2, v0.t
+; RV32-NEXT: addi a1, a3, -256
+; RV32-NEXT: vsrl.vx v11, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v12, v8, a4, v0.t
+; RV32-NEXT: vand.vx v13, v8, a1, v0.t
+; RV32-NEXT: vand.vx v12, v12, a1, v0.t
+; RV32-NEXT: vor.vv v11, v12, v11, v0.t
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vlse64.v v9, (a6), zero
-; RV32-NEXT: lui a4, 61681
+; RV32-NEXT: vlse64.v v12, (a6), zero
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vsll.vx v10, v8, a3, v0.t
-; RV32-NEXT: addi a5, a5, -256
-; RV32-NEXT: vand.vx v11, v8, a5, v0.t
-; RV32-NEXT: vsll.vx v11, v11, a2, v0.t
-; RV32-NEXT: vor.vv v10, v10, v11, v0.t
-; RV32-NEXT: vand.vx v11, v8, a1, v0.t
-; RV32-NEXT: vsll.vi v11, v11, 24, v0.t
-; RV32-NEXT: vand.vv v12, v8, v9, v0.t
+; RV32-NEXT: vsll.vx v13, v13, a4, v0.t
+; RV32-NEXT: vor.vv v10, v10, v13, v0.t
+; RV32-NEXT: vsrl.vi v13, v8, 8, v0.t
+; RV32-NEXT: vand.vx v9, v9, a5, v0.t
+; RV32-NEXT: vand.vv v13, v13, v12, v0.t
+; RV32-NEXT: vor.vv v9, v13, v9, v0.t
+; RV32-NEXT: lui a1, 61681
+; RV32-NEXT: lui a2, 209715
+; RV32-NEXT: lui a3, 349525
+; RV32-NEXT: vand.vv v12, v8, v12, v0.t
+; RV32-NEXT: vand.vx v8, v8, a5, v0.t
+; RV32-NEXT: addi a1, a1, -241
+; RV32-NEXT: addi a2, a2, 819
+; RV32-NEXT: addi a3, a3, 1365
+; RV32-NEXT: vsll.vi v8, v8, 24, v0.t
; RV32-NEXT: vsll.vi v12, v12, 8, v0.t
-; RV32-NEXT: vor.vv v11, v11, v12, v0.t
-; RV32-NEXT: vor.vv v10, v10, v11, v0.t
-; RV32-NEXT: vsrl.vx v11, v8, a3, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t
-; RV32-NEXT: lui a2, 349525
-; RV32-NEXT: addi a4, a4, -241
-; RV32-NEXT: addi a3, a3, 819
-; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vand.vx v12, v12, a5, v0.t
-; RV32-NEXT: vor.vv v11, v12, v11, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t
-; RV32-NEXT: vand.vx v12, v12, a1, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v9, v0.t
-; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV32-NEXT: vmv.v.x v9, a4
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV32-NEXT: vmv.v.x v12, a3
+; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v11, v0.t
+; RV32-NEXT: vor.vv v9, v9, v11, v0.t
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v11, a2
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vor.vv v8, v10, v8, v0.t
-; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t
-; RV32-NEXT: vand.vv v10, v10, v9, v0.t
-; RV32-NEXT: vand.vv v8, v8, v9, v0.t
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV32-NEXT: vmv.v.x v10, a3
+; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v9, v0.t
+; RV32-NEXT: vsrl.vi v9, v8, 4, v0.t
+; RV32-NEXT: vand.vv v8, v8, v12, v0.t
+; RV32-NEXT: vand.vv v9, v9, v12, v0.t
; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v10, v8, v0.t
+; RV32-NEXT: vor.vv v8, v9, v8, v0.t
; RV32-NEXT: vsrl.vi v9, v8, 2, v0.t
-; RV32-NEXT: vand.vv v9, v9, v12, v0.t
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
+; RV32-NEXT: vand.vv v8, v8, v11, v0.t
+; RV32-NEXT: vand.vv v9, v9, v11, v0.t
; RV32-NEXT: vsll.vi v8, v8, 2, v0.t
; RV32-NEXT: vor.vv v8, v9, v8, v0.t
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
-; RV32-NEXT: vand.vv v9, v9, v11, v0.t
-; RV32-NEXT: vand.vv v8, v8, v11, v0.t
+; RV32-NEXT: vand.vv v8, v8, v10, v0.t
+; RV32-NEXT: vand.vv v9, v9, v10, v0.t
; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v9, v8, v0.t
; RV32-NEXT: addi sp, sp, 16
@@ -879,59 +880,59 @@ define <2 x i64> @vp_bitreverse_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %e
; RV64-LABEL: vp_bitreverse_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a3, 255
-; RV64-NEXT: li a2, 56
+; RV64-NEXT: li a2, 255
+; RV64-NEXT: li a3, 56
; RV64-NEXT: lui a4, 16
-; RV64-NEXT: lui a5, 61681
-; RV64-NEXT: lui a6, 209715
-; RV64-NEXT: lui a7, 349525
-; RV64-NEXT: addi a5, a5, -241
-; RV64-NEXT: addi a6, a6, 819
-; RV64-NEXT: addi a7, a7, 1365
-; RV64-NEXT: slli t0, a5, 32
-; RV64-NEXT: add t0, a5, t0
-; RV64-NEXT: slli a5, a6, 32
-; RV64-NEXT: add a6, a6, a5
-; RV64-NEXT: slli a5, a7, 32
-; RV64-NEXT: add a5, a7, a5
-; RV64-NEXT: li a7, 40
+; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV64-NEXT: vand.vx v9, v8, a1, v0.t
-; RV64-NEXT: slli a3, a3, 24
+; RV64-NEXT: vsrl.vi v9, v8, 24, v0.t
+; RV64-NEXT: vsrl.vi v10, v8, 8, v0.t
; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v9, v9, 24, v0.t
-; RV64-NEXT: vand.vx v10, v8, a3, v0.t
-; RV64-NEXT: vsll.vi v10, v10, 8, v0.t
-; RV64-NEXT: vor.vv v9, v9, v10, v0.t
-; RV64-NEXT: vsll.vx v10, v8, a2, v0.t
-; RV64-NEXT: vand.vx v11, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v11, v11, a7, v0.t
-; RV64-NEXT: vor.vv v10, v10, v11, v0.t
+; RV64-NEXT: vsrl.vx v11, v8, a3, v0.t
+; RV64-NEXT: vsrl.vx v12, v8, a5, v0.t
+; RV64-NEXT: vand.vx v12, v12, a0, v0.t
+; RV64-NEXT: vor.vv v11, v12, v11, v0.t
+; RV64-NEXT: vand.vx v12, v8, a1, v0.t
+; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vand.vx v9, v9, a1, v0.t
+; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
+; RV64-NEXT: vand.vx v10, v10, a2, v0.t
; RV64-NEXT: vor.vv v9, v10, v9, v0.t
-; RV64-NEXT: vsrl.vx v10, v8, a2, v0.t
-; RV64-NEXT: vsrl.vx v11, v8, a7, v0.t
-; RV64-NEXT: vand.vx v11, v11, a0, v0.t
-; RV64-NEXT: vor.vv v10, v11, v10, v0.t
-; RV64-NEXT: vsrl.vi v11, v8, 24, v0.t
-; RV64-NEXT: vand.vx v11, v11, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: vor.vv v8, v8, v11, v0.t
+; RV64-NEXT: vand.vx v10, v8, a2, v0.t
+; RV64-NEXT: vsll.vi v10, v10, 8, v0.t
+; RV64-NEXT: vor.vv v10, v12, v10, v0.t
+; RV64-NEXT: vsll.vx v12, v8, a3, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsll.vx v8, v8, a5, v0.t
+; RV64-NEXT: vor.vv v8, v12, v8, v0.t
+; RV64-NEXT: lui a0, 61681
+; RV64-NEXT: lui a1, 209715
+; RV64-NEXT: lui a2, 349525
+; RV64-NEXT: addi a0, a0, -241
+; RV64-NEXT: addi a1, a1, 819
+; RV64-NEXT: addi a2, a2, 1365
+; RV64-NEXT: slli a3, a0, 32
+; RV64-NEXT: slli a4, a1, 32
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: slli a3, a2, 32
+; RV64-NEXT: add a1, a1, a4
+; RV64-NEXT: add a2, a2, a3
+; RV64-NEXT: vor.vv v9, v9, v11, v0.t
; RV64-NEXT: vor.vv v8, v8, v10, v0.t
-; RV64-NEXT: vor.vv v8, v9, v8, v0.t
+; RV64-NEXT: vor.vv v8, v8, v9, v0.t
; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
-; RV64-NEXT: vand.vx v9, v9, t0, v0.t
-; RV64-NEXT: vand.vx v8, v8, t0, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vand.vx v9, v9, a0, v0.t
; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
; RV64-NEXT: vor.vv v8, v9, v8, v0.t
; RV64-NEXT: vsrl.vi v9, v8, 2, v0.t
-; RV64-NEXT: vand.vx v9, v9, a6, v0.t
-; RV64-NEXT: vand.vx v8, v8, a6, v0.t
+; RV64-NEXT: vand.vx v8, v8, a1, v0.t
+; RV64-NEXT: vand.vx v9, v9, a1, v0.t
; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
; RV64-NEXT: vor.vv v8, v9, v8, v0.t
; RV64-NEXT: vsrl.vi v9, v8, 1, v0.t
-; RV64-NEXT: vand.vx v9, v9, a5, v0.t
-; RV64-NEXT: vand.vx v8, v8, a5, v0.t
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vand.vx v9, v9, a2, v0.t
; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
; RV64-NEXT: vor.vv v8, v9, v8, v0.t
; RV64-NEXT: ret
@@ -1080,67 +1081,68 @@ define <4 x i64> @vp_bitreverse_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %e
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a4, 1044480
-; RV32-NEXT: li a3, 56
-; RV32-NEXT: lui a5, 16
-; RV32-NEXT: li a2, 40
-; RV32-NEXT: lui a1, 4080
+; RV32-NEXT: lui a1, 1044480
+; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a3, 16
+; RV32-NEXT: li a4, 40
+; RV32-NEXT: lui a5, 4080
; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a4, 8(sp)
+; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; RV32-NEXT: vsrl.vi v14, v8, 24, v0.t
+; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: vsll.vx v12, v8, a2, v0.t
+; RV32-NEXT: addi a1, a3, -256
+; RV32-NEXT: vsrl.vx v10, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a4, v0.t
+; RV32-NEXT: vand.vx v18, v8, a1, v0.t
+; RV32-NEXT: vand.vx v16, v16, a1, v0.t
+; RV32-NEXT: vor.vv v10, v16, v10, v0.t
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32-NEXT: vlse64.v v10, (a6), zero
-; RV32-NEXT: lui a4, 61681
+; RV32-NEXT: vlse64.v v16, (a6), zero
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vsll.vx v12, v8, a3, v0.t
-; RV32-NEXT: addi a5, a5, -256
-; RV32-NEXT: vand.vx v14, v8, a5, v0.t
-; RV32-NEXT: vsll.vx v14, v14, a2, v0.t
-; RV32-NEXT: vor.vv v12, v12, v14, v0.t
-; RV32-NEXT: vand.vx v14, v8, a1, v0.t
-; RV32-NEXT: vsll.vi v14, v14, 24, v0.t
-; RV32-NEXT: vand.vv v16, v8, v10, v0.t
+; RV32-NEXT: vsll.vx v18, v18, a4, v0.t
+; RV32-NEXT: vor.vv v12, v12, v18, v0.t
+; RV32-NEXT: vsrl.vi v18, v8, 8, v0.t
+; RV32-NEXT: vand.vx v14, v14, a5, v0.t
+; RV32-NEXT: vand.vv v18, v18, v16, v0.t
+; RV32-NEXT: vor.vv v14, v18, v14, v0.t
+; RV32-NEXT: lui a1, 61681
+; RV32-NEXT: lui a2, 209715
+; RV32-NEXT: lui a3, 349525
+; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vand.vx v8, v8, a5, v0.t
+; RV32-NEXT: addi a1, a1, -241
+; RV32-NEXT: addi a2, a2, 819
+; RV32-NEXT: addi a3, a3, 1365
+; RV32-NEXT: vsll.vi v8, v8, 24, v0.t
; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v14, v14, v16, v0.t
-; RV32-NEXT: vor.vv v12, v12, v14, v0.t
-; RV32-NEXT: vsrl.vx v14, v8, a3, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: lui a2, 349525
-; RV32-NEXT: addi a4, a4, -241
-; RV32-NEXT: addi a3, a3, 819
-; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vand.vx v16, v16, a5, v0.t
-; RV32-NEXT: vor.vv v14, v16, v14, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV32-NEXT: vand.vx v16, v16, a1, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v10, v0.t
-; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v10, a4
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v14, v0.t
+; RV32-NEXT: vor.vv v10, v14, v10, v0.t
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v14, a2
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vor.vv v8, v12, v8, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
-; RV32-NEXT: vand.vv v12, v12, v10, v0.t
-; RV32-NEXT: vand.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV32-NEXT: vmv.v.x v12, a3
+; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; RV32-NEXT: vor.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vand.vv v10, v10, v16, v0.t
; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v12, v8, v0.t
+; RV32-NEXT: vor.vv v8, v10, v8, v0.t
; RV32-NEXT: vsrl.vi v10, v8, 2, v0.t
-; RV32-NEXT: vand.vv v10, v10, v16, v0.t
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vand.vv v8, v8, v14, v0.t
+; RV32-NEXT: vand.vv v10, v10, v14, v0.t
; RV32-NEXT: vsll.vi v8, v8, 2, v0.t
; RV32-NEXT: vor.vv v8, v10, v8, v0.t
; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
-; RV32-NEXT: vand.vv v10, v10, v14, v0.t
-; RV32-NEXT: vand.vv v8, v8, v14, v0.t
+; RV32-NEXT: vand.vv v8, v8, v12, v0.t
+; RV32-NEXT: vand.vv v10, v10, v12, v0.t
; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
; RV32-NEXT: vor.vv v8, v10, v8, v0.t
; RV32-NEXT: addi sp, sp, 16
@@ -1150,59 +1152,59 @@ define <4 x i64> @vp_bitreverse_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %e
; RV64-LABEL: vp_bitreverse_v4i64:
; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a3, 255
-; RV64-NEXT: li a2, 56
+; RV64-NEXT: li a2, 255
+; RV64-NEXT: li a3, 56
; RV64-NEXT: lui a4, 16
-; RV64-NEXT: lui a5, 61681
-; RV64-NEXT: lui a6, 209715
-; RV64-NEXT: lui a7, 349525
-; RV64-NEXT: addi a5, a5, -241
-; RV64-NEXT: addi a6, a6, 819
-; RV64-NEXT: addi a7, a7, 1365
-; RV64-NEXT: slli t0, a5, 32
-; RV64-NEXT: add t0, a5, t0
-; RV64-NEXT: slli a5, a6, 32
-; RV64-NEXT: add a6, a6, a5
-; RV64-NEXT: slli a5, a7, 32
-; RV64-NEXT: add a5, a7, a5
-; RV64-NEXT: li a7, 40
+; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV64-NEXT: vand.vx v10, v8, a1, v0.t
-; RV64-NEXT: slli a3, a3, 24
+; RV64-NEXT: vsrl.vi v12, v8, 24, v0.t
+; RV64-NEXT: vsrl.vi v14, v8, 8, v0.t
; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v10, v10, 24, v0.t
-; RV64-NEXT: vand.vx v12, v8, a3, v0.t
-; RV64-NEXT: vsll.vi v12, v12, 8, v0.t
-; RV64-NEXT: vor.vv v10, v10, v12, v0.t
-; RV64-NEXT: vsll.vx v12, v8, a2, v0.t
-; RV64-NEXT: vand.vx v14, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v14, v14, a7, v0.t
-; RV64-NEXT: vor.vv v12, v12, v14, v0.t
-; RV64-NEXT: vor.vv v10, v12, v10, v0.t
-; RV64-NEXT: vsrl.vx v12, v8, a2, v0.t
-; RV64-NEXT: vsrl.vx v14, v8, a7, v0.t
-; RV64-NEXT: vand.vx v14, v14, a0, v0.t
+; RV64-NEXT: vsrl.vx v10, v8, a3, v0.t
+; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
+; RV64-NEXT: vand.vx v16, v16, a0, v0.t
+; RV64-NEXT: vor.vv v10, v16, v10, v0.t
+; RV64-NEXT: vand.vx v16, v8, a1, v0.t
+; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vand.vx v12, v12, a1, v0.t
+; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
+; RV64-NEXT: vand.vx v14, v14, a2, v0.t
; RV64-NEXT: vor.vv v12, v14, v12, v0.t
-; RV64-NEXT: vsrl.vi v14, v8, 24, v0.t
-; RV64-NEXT: vand.vx v14, v14, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
+; RV64-NEXT: vand.vx v14, v8, a2, v0.t
+; RV64-NEXT: vsll.vi v14, v14, 8, v0.t
+; RV64-NEXT: vor.vv v14, v16, v14, v0.t
+; RV64-NEXT: vsll.vx v16, v8, a3, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsll.vx v8, v8, a5, v0.t
+; RV64-NEXT: vor.vv v8, v16, v8, v0.t
+; RV64-NEXT: lui a0, 61681
+; RV64-NEXT: lui a1, 209715
+; RV64-NEXT: lui a2, 349525
+; RV64-NEXT: addi a0, a0, -241
+; RV64-NEXT: addi a1, a1, 819
+; RV64-NEXT: addi a2, a2, 1365
+; RV64-NEXT: slli a3, a0, 32
+; RV64-NEXT: slli a4, a1, 32
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: slli a3, a2, 32
+; RV64-NEXT: add a1, a1, a4
+; RV64-NEXT: add a2, a2, a3
+; RV64-NEXT: vor.vv v10, v12, v10, v0.t
; RV64-NEXT: vor.vv v8, v8, v14, v0.t
-; RV64-NEXT: vor.vv v8, v8, v12, v0.t
-; RV64-NEXT: vor.vv v8, v10, v8, v0.t
+; RV64-NEXT: vor.vv v8, v8, v10, v0.t
; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
-; RV64-NEXT: vand.vx v10, v10, t0, v0.t
-; RV64-NEXT: vand.vx v8, v8, t0, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vand.vx v10, v10, a0, v0.t
; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
; RV64-NEXT: vor.vv v8, v10, v8, v0.t
; RV64-NEXT: vsrl.vi v10, v8, 2, v0.t
-; RV64-NEXT: vand.vx v10, v10, a6, v0.t
-; RV64-NEXT: vand.vx v8, v8, a6, v0.t
+; RV64-NEXT: vand.vx v8, v8, a1, v0.t
+; RV64-NEXT: vand.vx v10, v10, a1, v0.t
; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
; RV64-NEXT: vor.vv v8, v10, v8, v0.t
; RV64-NEXT: vsrl.vi v10, v8, 1, v0.t
-; RV64-NEXT: vand.vx v10, v10, a5, v0.t
-; RV64-NEXT: vand.vx v8, v8, a5, v0.t
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vand.vx v10, v10, a2, v0.t
; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
; RV64-NEXT: vor.vv v8, v10, v8, v0.t
; RV64-NEXT: ret
@@ -1351,69 +1353,70 @@ define <8 x i64> @vp_bitreverse_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %e
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: lui a4, 1044480
-; RV32-NEXT: li a3, 56
-; RV32-NEXT: lui a5, 16
-; RV32-NEXT: li a2, 40
-; RV32-NEXT: lui a1, 4080
+; RV32-NEXT: lui a1, 1044480
+; RV32-NEXT: li a2, 56
+; RV32-NEXT: lui a3, 16
+; RV32-NEXT: li a4, 40
+; RV32-NEXT: lui a5, 4080
; RV32-NEXT: addi a6, sp, 8
-; RV32-NEXT: sw a4, 8(sp)
+; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; RV32-NEXT: vsrl.vi v20, v8, 24, v0.t
+; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
+; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
+; RV32-NEXT: addi a1, a3, -256
+; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
+; RV32-NEXT: vand.vx v28, v8, a1, v0.t
+; RV32-NEXT: vand.vx v24, v24, a1, v0.t
+; RV32-NEXT: vor.vv v12, v24, v12, v0.t
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vlse64.v v12, (a6), zero
-; RV32-NEXT: lui a4, 61681
+; RV32-NEXT: vlse64.v v24, (a6), zero
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a3, v0.t
-; RV32-NEXT: addi a5, a5, -256
-; RV32-NEXT: vand.vx v20, v8, a5, v0.t
-; RV32-NEXT: vsll.vx v20, v20, a2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vand.vx v20, v8, a1, v0.t
-; RV32-NEXT: vsll.vi v20, v20, 24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v12, v0.t
+; RV32-NEXT: vsll.vx v28, v28, a4, v0.t
+; RV32-NEXT: vor.vv v16, v16, v28, v0.t
+; RV32-NEXT: vsrl.vi v28, v8, 8, v0.t
+; RV32-NEXT: vand.vx v20, v20, a5, v0.t
+; RV32-NEXT: vand.vv v28, v28, v24, v0.t
+; RV32-NEXT: vor.vv v20, v28, v20, v0.t
+; RV32-NEXT: lui a1, 61681
+; RV32-NEXT: lui a2, 209715
+; RV32-NEXT: lui a3, 349525
+; RV32-NEXT: vand.vv v24, v8, v24, v0.t
+; RV32-NEXT: vand.vx v8, v8, a5, v0.t
+; RV32-NEXT: addi a1, a1, -241
+; RV32-NEXT: addi a2, a2, 819
+; RV32-NEXT: addi a3, a3, 1365
+; RV32-NEXT: vsll.vi v8, v8, 24, v0.t
; RV32-NEXT: vsll.vi v24, v24, 8, v0.t
-; RV32-NEXT: vor.vv v20, v20, v24, v0.t
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vsrl.vx v20, v8, a3, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t
-; RV32-NEXT: lui a2, 349525
-; RV32-NEXT: addi a4, a4, -241
-; RV32-NEXT: addi a3, a3, 819
-; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vand.vx v24, v24, a5, v0.t
-; RV32-NEXT: vor.vv v20, v24, v20, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v28, a4
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vor.vv v12, v20, v12, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v12, a3
+; RV32-NEXT: vmv.v.x v20, a2
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v20, v8, v20, v0.t
+; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v8, a2
+; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vsrl.vi v20, v16, 4, v0.t
-; RV32-NEXT: vand.vv v20, v20, v28, v0.t
-; RV32-NEXT: vand.vv v16, v16, v28, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 4, v0.t
-; RV32-NEXT: vor.vv v16, v20, v16, v0.t
-; RV32-NEXT: vsrl.vi v20, v16, 2, v0.t
-; RV32-NEXT: vand.vv v20, v20, v12, v0.t
-; RV32-NEXT: vand.vv v12, v16, v12, v0.t
-; RV32-NEXT: vsll.vi v12, v12, 2, v0.t
-; RV32-NEXT: vor.vv v12, v20, v12, v0.t
-; RV32-NEXT: vsrl.vi v16, v12, 1, v0.t
-; RV32-NEXT: vand.vv v16, v16, v8, v0.t
-; RV32-NEXT: vand.vv v8, v12, v8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v12, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vand.vv v12, v12, v24, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v12, v8, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 2, v0.t
+; RV32-NEXT: vand.vv v8, v8, v20, v0.t
+; RV32-NEXT: vand.vv v12, v12, v20, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v12, v8, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vand.vv v12, v12, v16, v0.t
; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vor.vv v8, v12, v8, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
@@ -1421,59 +1424,59 @@ define <8 x i64> @vp_bitreverse_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %e
; RV64-LABEL: vp_bitreverse_v8i64:
; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a3, 255
-; RV64-NEXT: li a2, 56
+; RV64-NEXT: li a2, 255
+; RV64-NEXT: li a3, 56
; RV64-NEXT: lui a4, 16
-; RV64-NEXT: lui a5, 61681
-; RV64-NEXT: lui a6, 209715
-; RV64-NEXT: lui a7, 349525
-; RV64-NEXT: addi a5, a5, -241
-; RV64-NEXT: addi a6, a6, 819
-; RV64-NEXT: addi a7, a7, 1365
-; RV64-NEXT: slli t0, a5, 32
-; RV64-NEXT: add t0, a5, t0
-; RV64-NEXT: slli a5, a6, 32
-; RV64-NEXT: add a6, a6, a5
-; RV64-NEXT: slli a5, a7, 32
-; RV64-NEXT: add a5, a7, a5
-; RV64-NEXT: li a7, 40
+; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV64-NEXT: vand.vx v12, v8, a1, v0.t
-; RV64-NEXT: slli a3, a3, 24
+; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
+; RV64-NEXT: vsrl.vi v20, v8, 8, v0.t
; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
-; RV64-NEXT: vand.vx v16, v8, a3, v0.t
-; RV64-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV64-NEXT: vor.vv v12, v12, v16, v0.t
-; RV64-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV64-NEXT: vand.vx v20, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v20, v20, a7, v0.t
-; RV64-NEXT: vor.vv v16, v16, v20, v0.t
-; RV64-NEXT: vor.vv v12, v16, v12, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV64-NEXT: vsrl.vx v20, v8, a7, v0.t
-; RV64-NEXT: vand.vx v20, v20, a0, v0.t
+; RV64-NEXT: vsrl.vx v12, v8, a3, v0.t
+; RV64-NEXT: vsrl.vx v24, v8, a5, v0.t
+; RV64-NEXT: vand.vx v24, v24, a0, v0.t
+; RV64-NEXT: vor.vv v12, v24, v12, v0.t
+; RV64-NEXT: vand.vx v24, v8, a1, v0.t
+; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vand.vx v16, v16, a1, v0.t
+; RV64-NEXT: vsll.vi v24, v24, 24, v0.t
+; RV64-NEXT: vand.vx v20, v20, a2, v0.t
; RV64-NEXT: vor.vv v16, v20, v16, v0.t
-; RV64-NEXT: vsrl.vi v20, v8, 24, v0.t
-; RV64-NEXT: vand.vx v20, v20, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
+; RV64-NEXT: vand.vx v20, v8, a2, v0.t
+; RV64-NEXT: vsll.vi v20, v20, 8, v0.t
+; RV64-NEXT: vor.vv v20, v24, v20, v0.t
+; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsll.vx v8, v8, a5, v0.t
+; RV64-NEXT: vor.vv v8, v24, v8, v0.t
+; RV64-NEXT: lui a0, 61681
+; RV64-NEXT: lui a1, 209715
+; RV64-NEXT: lui a2, 349525
+; RV64-NEXT: addi a0, a0, -241
+; RV64-NEXT: addi a1, a1, 819
+; RV64-NEXT: addi a2, a2, 1365
+; RV64-NEXT: slli a3, a0, 32
+; RV64-NEXT: slli a4, a1, 32
+; RV64-NEXT: add a0, a0, a3
+; RV64-NEXT: slli a3, a2, 32
+; RV64-NEXT: add a1, a1, a4
+; RV64-NEXT: add a2, a2, a3
+; RV64-NEXT: vor.vv v12, v16, v12, v0.t
; RV64-NEXT: vor.vv v8, v8, v20, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v12, v8, v0.t
+; RV64-NEXT: vor.vv v8, v8, v12, v0.t
; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
-; RV64-NEXT: vand.vx v12, v12, t0, v0.t
-; RV64-NEXT: vand.vx v8, v8, t0, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vand.vx v12, v12, a0, v0.t
; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
; RV64-NEXT: vor.vv v8, v12, v8, v0.t
; RV64-NEXT: vsrl.vi v12, v8, 2, v0.t
-; RV64-NEXT: vand.vx v12, v12, a6, v0.t
-; RV64-NEXT: vand.vx v8, v8, a6, v0.t
+; RV64-NEXT: vand.vx v8, v8, a1, v0.t
+; RV64-NEXT: vand.vx v12, v12, a1, v0.t
; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
; RV64-NEXT: vor.vv v8, v12, v8, v0.t
; RV64-NEXT: vsrl.vi v12, v8, 1, v0.t
-; RV64-NEXT: vand.vx v12, v12, a5, v0.t
-; RV64-NEXT: vand.vx v8, v8, a5, v0.t
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vand.vx v12, v12, a2, v0.t
; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
; RV64-NEXT: vor.vv v8, v12, v8, v0.t
; RV64-NEXT: ret
@@ -1623,77 +1626,144 @@ define <15 x i64> @vp_bitreverse_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroex
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a2, a1, 5
+; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: lui a2, 16
+; RV32-NEXT: li a3, 40
+; RV32-NEXT: addi a2, a2, -256
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: vsrl.vx v24, v8, a3, v0.t
+; RV32-NEXT: vand.vx v24, v24, a2, v0.t
+; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: li a5, 24
+; RV32-NEXT: mul a4, a4, a5
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: slli a4, a4, 5
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vand.vx v24, v8, a2, v0.t
+; RV32-NEXT: vsll.vx v24, v24, a3, v0.t
+; RV32-NEXT: vsll.vx v16, v8, a1, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 4
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: lui a2, 4080
+; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vand.vx v24, v8, a1, v0.t
-; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vlse64.v v16, (a5), zero
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a3, 4080
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vx v16, v8, a3, v0.t
-; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 4
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 3
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 3
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: vlse64.v v16, (a3), zero
; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a3, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
+; RV32-NEXT: vand.vx v24, v24, a2, v0.t
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vor.vv v24, v24, v16, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vx v24, v8, a2, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vor.vv v16, v24, v8, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 24
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 4
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v16, v24, v16, v0.t
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: lui a2, 209715
; RV32-NEXT: lui a3, 349525
@@ -1703,36 +1773,36 @@ define <15 x i64> @vp_bitreverse_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroex
; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v24, v0.t
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a2
+; RV32-NEXT: vmv.v.x v24, a2
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vi v24, v24, 4, v0.t
-; RV32-NEXT: vor.vv v24, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v16, v24, 2, v0.t
-; RV32-NEXT: vand.vv v16, v16, v8, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vand.vv v16, v16, v24, v0.t
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a3
+; RV32-NEXT: vmv.v.x v24, a3
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vi v24, v24, 2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vand.vv v16, v16, v24, v0.t
; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: slli a1, a0, 5
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
; RV32-NEXT: addi sp, sp, 16
@@ -1744,41 +1814,134 @@ define <15 x i64> @vp_bitreverse_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroex
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: li a2, 25
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
+; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
+; RV64-NEXT: lui a2, 4080
+; RV64-NEXT: li a3, 255
+; RV64-NEXT: li a1, 56
; RV64-NEXT: lui a4, 16
; RV64-NEXT: li a5, 40
+; RV64-NEXT: addi a4, a4, -256
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
+; RV64-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV64-NEXT: vsrl.vx v24, v8, a5, v0.t
+; RV64-NEXT: vand.vx v24, v24, a4, v0.t
+; RV64-NEXT: vor.vv v16, v24, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a6, 24
+; RV64-NEXT: mul a0, a0, a6
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs1r.v v0, (a0) # vscale x 8-byte Folded Spill
+; RV64-NEXT: vsrl.vi v24, v8, 24, v0.t
+; RV64-NEXT: slli a3, a3, 24
+; RV64-NEXT: vand.vx v24, v24, a2, v0.t
+; RV64-NEXT: vsrl.vi v16, v8, 8, v0.t
+; RV64-NEXT: vand.vx v16, v16, a3, v0.t
+; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a6, 24
+; RV64-NEXT: mul a0, a0, a6
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v16, v8, a2, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v24, v8, a3, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
-; RV64-NEXT: vand.vx v16, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v16, v16, a5, v0.t
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v24, v8, a4, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsll.vx v24, v24, a5, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsll.vx v8, v8, a1, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a1, 24
+; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vor.vv v24, v8, v24, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a1, 24
+; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vor.vv v8, v16, v8, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a1, 24
+; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: vor.vv v16, v24, v16, v0.t
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vor.vv v24, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: lui a0, 61681
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 349525
@@ -1791,26 +1954,25 @@ define <15 x i64> @vp_bitreverse_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroex
; RV64-NEXT: slli a3, a2, 32
; RV64-NEXT: add a1, a1, a4
; RV64-NEXT: add a2, a2, a3
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
; RV64-NEXT: vor.vv v8, v16, v8, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vand.vx v16, v16, a0, v0.t
; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
; RV64-NEXT: vor.vv v8, v16, v8, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
; RV64-NEXT: vand.vx v8, v8, a1, v0.t
+; RV64-NEXT: vand.vx v16, v16, a1, v0.t
; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
; RV64-NEXT: vor.vv v8, v16, v8, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV64-NEXT: vand.vx v16, v16, a2, v0.t
; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vand.vx v16, v16, a2, v0.t
; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
; RV64-NEXT: vor.vv v8, v16, v8, v0.t
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: li a1, 25
+; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 16
; RV64-NEXT: addi sp, sp, 16
@@ -2000,77 +2162,144 @@ define <16 x i64> @vp_bitreverse_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroex
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a2, a1, 5
+; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: lui a2, 16
+; RV32-NEXT: li a3, 40
+; RV32-NEXT: addi a2, a2, -256
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: vsrl.vx v24, v8, a3, v0.t
+; RV32-NEXT: vand.vx v24, v24, a2, v0.t
+; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: li a5, 24
+; RV32-NEXT: mul a4, a4, a5
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: slli a4, a4, 5
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vand.vx v24, v8, a2, v0.t
+; RV32-NEXT: vsll.vx v24, v24, a3, v0.t
+; RV32-NEXT: vsll.vx v16, v8, a1, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 4
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: lui a2, 4080
+; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vand.vx v24, v8, a1, v0.t
-; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vlse64.v v16, (a5), zero
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a3, 4080
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vx v16, v8, a3, v0.t
-; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 4
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 3
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 3
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: vlse64.v v16, (a3), zero
; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a3, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
+; RV32-NEXT: vand.vx v24, v24, a2, v0.t
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vor.vv v24, v24, v16, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vx v24, v8, a2, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vor.vv v16, v24, v8, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 24
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 4
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v16, v24, v16, v0.t
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: lui a2, 209715
; RV32-NEXT: lui a3, 349525
@@ -2080,36 +2309,36 @@ define <16 x i64> @vp_bitreverse_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroex
; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v24, v0.t
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a2
+; RV32-NEXT: vmv.v.x v24, a2
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vi v24, v24, 4, v0.t
-; RV32-NEXT: vor.vv v24, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v16, v24, 2, v0.t
-; RV32-NEXT: vand.vv v16, v16, v8, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vand.vv v16, v16, v24, v0.t
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a3
+; RV32-NEXT: vmv.v.x v24, a3
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vi v24, v24, 2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vand.vv v16, v16, v24, v0.t
; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
-; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: slli a1, a0, 5
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
; RV32-NEXT: addi sp, sp, 16
@@ -2121,41 +2350,134 @@ define <16 x i64> @vp_bitreverse_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroex
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: li a2, 25
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
+; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
+; RV64-NEXT: lui a2, 4080
+; RV64-NEXT: li a3, 255
+; RV64-NEXT: li a1, 56
; RV64-NEXT: lui a4, 16
; RV64-NEXT: li a5, 40
+; RV64-NEXT: addi a4, a4, -256
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
+; RV64-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV64-NEXT: vsrl.vx v24, v8, a5, v0.t
+; RV64-NEXT: vand.vx v24, v24, a4, v0.t
+; RV64-NEXT: vor.vv v16, v24, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a6, 24
+; RV64-NEXT: mul a0, a0, a6
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs1r.v v0, (a0) # vscale x 8-byte Folded Spill
+; RV64-NEXT: vsrl.vi v24, v8, 24, v0.t
+; RV64-NEXT: slli a3, a3, 24
+; RV64-NEXT: vand.vx v24, v24, a2, v0.t
+; RV64-NEXT: vsrl.vi v16, v8, 8, v0.t
+; RV64-NEXT: vand.vx v16, v16, a3, v0.t
+; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a6, 24
+; RV64-NEXT: mul a0, a0, a6
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v16, v8, a2, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v24, v8, a3, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
-; RV64-NEXT: vand.vx v16, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v16, v16, a5, v0.t
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v24, v8, a4, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsll.vx v24, v24, a5, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a2, 24
+; RV64-NEXT: mul a0, a0, a2
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsll.vx v8, v8, a1, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a1, 24
+; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vor.vv v24, v8, v24, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a1, 24
+; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vor.vv v8, v16, v8, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: li a1, 24
+; RV64-NEXT: mul a0, a0, a1
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: vor.vv v16, v24, v16, v0.t
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vor.vv v24, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: lui a0, 61681
; RV64-NEXT: lui a1, 209715
; RV64-NEXT: lui a2, 349525
@@ -2168,26 +2490,25 @@ define <16 x i64> @vp_bitreverse_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroex
; RV64-NEXT: slli a3, a2, 32
; RV64-NEXT: add a1, a1, a4
; RV64-NEXT: add a2, a2, a3
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
; RV64-NEXT: vor.vv v8, v16, v8, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vand.vx v16, v16, a0, v0.t
; RV64-NEXT: vsll.vi v8, v8, 4, v0.t
; RV64-NEXT: vor.vv v8, v16, v8, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
; RV64-NEXT: vand.vx v8, v8, a1, v0.t
+; RV64-NEXT: vand.vx v16, v16, a1, v0.t
; RV64-NEXT: vsll.vi v8, v8, 2, v0.t
; RV64-NEXT: vor.vv v8, v16, v8, v0.t
; RV64-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV64-NEXT: vand.vx v16, v16, a2, v0.t
; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vand.vx v16, v16, a2, v0.t
; RV64-NEXT: vsll.vi v8, v8, 1, v0.t
; RV64-NEXT: vor.vv v8, v16, v8, v0.t
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: li a1, 25
+; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 16
; RV64-NEXT: addi sp, sp, 16
@@ -2384,51 +2705,60 @@ define <128 x i16> @vp_bitreverse_v128i16(<128 x i16> %va, <128 x i1> %m, i32 ze
; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v8, 8, v0.t
-; CHECK-NEXT: lui a1, 1
-; CHECK-NEXT: lui a2, 3
+; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
+; CHECK-NEXT: lui a2, 1
+; CHECK-NEXT: lui a4, 3
; CHECK-NEXT: addi a3, a0, -64
; CHECK-NEXT: sltu a0, a0, a3
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a3, a0, a3
; CHECK-NEXT: lui a0, 5
-; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: addi a1, a1, -241
-; CHECK-NEXT: addi a2, a2, 819
-; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vor.vv v8, v8, v24, v0.t
+; CHECK-NEXT: addi a5, a2, -241
+; CHECK-NEXT: addi a2, a4, 819
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v24, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a5, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a5, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
+; CHECK-NEXT: vmv1r.v v6, v0
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma
+; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
+; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
+; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
+; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a2, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma
+; CHECK-NEXT: vsrl.vi v24, v16, 4, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a5, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a5, v0.t
+; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
+; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a0, v0.t
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a0, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
-; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
-; CHECK-NEXT: vsrl.vi v24, v16, 4, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
-; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: vsrl.vi v24, v16, 2, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
; CHECK-NEXT: vand.vx v16, v16, a2, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: vsrl.vi v24, v16, 1, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a0, v0.t
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a0, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 1, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
index eca94ccb9bf7f..d8b109fcbf77f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
@@ -106,9 +106,9 @@ define <2 x i32> @vp_bswap_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
; CHECK-NEXT: vor.vv v9, v9, v10, v0.t
; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t
@@ -146,9 +146,9 @@ define <4 x i32> @vp_bswap_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v8, 8, v0.t
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
-; CHECK-NEXT: vsrl.vi v10, v8, 24, v0.t
; CHECK-NEXT: vor.vv v9, v9, v10, v0.t
; CHECK-NEXT: vand.vx v10, v8, a0, v0.t
; CHECK-NEXT: vsll.vi v10, v10, 8, v0.t
@@ -186,9 +186,9 @@ define <8 x i32> @vp_bswap_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v8, 8, v0.t
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v12, v8, 24, v0.t
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
-; CHECK-NEXT: vsrl.vi v12, v8, 24, v0.t
; CHECK-NEXT: vor.vv v10, v10, v12, v0.t
; CHECK-NEXT: vand.vx v12, v8, a0, v0.t
; CHECK-NEXT: vsll.vi v12, v12, 8, v0.t
@@ -226,9 +226,9 @@ define <16 x i32> @vp_bswap_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %ev
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v8, 8, v0.t
; CHECK-NEXT: lui a0, 16
+; CHECK-NEXT: vsrl.vi v16, v8, 24, v0.t
; CHECK-NEXT: addi a0, a0, -256
; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
-; CHECK-NEXT: vsrl.vi v16, v8, 24, v0.t
; CHECK-NEXT: vor.vv v12, v12, v16, v0.t
; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
@@ -271,34 +271,34 @@ define <2 x i64> @vp_bswap_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV32-NEXT: li a4, 40
; RV32-NEXT: lui a5, 4080
; RV32-NEXT: addi a6, sp, 8
+; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; RV32-NEXT: vsrl.vi v9, v8, 24, v0.t
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vsll.vx v9, v8, a2, v0.t
+; RV32-NEXT: vsll.vx v10, v8, a2, v0.t
; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vand.vx v10, v8, a1, v0.t
+; RV32-NEXT: vsrl.vx v11, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v12, v8, a4, v0.t
+; RV32-NEXT: vand.vx v13, v8, a1, v0.t
+; RV32-NEXT: vand.vx v12, v12, a1, v0.t
+; RV32-NEXT: vor.vv v11, v12, v11, v0.t
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vlse64.v v11, (a6), zero
+; RV32-NEXT: vlse64.v v12, (a6), zero
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vsll.vx v10, v10, a4, v0.t
-; RV32-NEXT: vor.vv v9, v9, v10, v0.t
-; RV32-NEXT: vand.vx v10, v8, a5, v0.t
-; RV32-NEXT: vsll.vi v10, v10, 24, v0.t
-; RV32-NEXT: vand.vv v12, v8, v11, v0.t
+; RV32-NEXT: vsll.vx v13, v13, a4, v0.t
+; RV32-NEXT: vor.vv v10, v10, v13, v0.t
+; RV32-NEXT: vsrl.vi v13, v8, 8, v0.t
+; RV32-NEXT: vand.vx v9, v9, a5, v0.t
+; RV32-NEXT: vand.vv v13, v13, v12, v0.t
+; RV32-NEXT: vor.vv v9, v13, v9, v0.t
+; RV32-NEXT: vand.vv v12, v8, v12, v0.t
+; RV32-NEXT: vand.vx v8, v8, a5, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 24, v0.t
; RV32-NEXT: vsll.vi v12, v12, 8, v0.t
-; RV32-NEXT: vor.vv v10, v10, v12, v0.t
-; RV32-NEXT: vor.vv v9, v9, v10, v0.t
-; RV32-NEXT: vsrl.vx v10, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v12, v8, a4, v0.t
-; RV32-NEXT: vand.vx v12, v12, a1, v0.t
-; RV32-NEXT: vor.vv v10, v12, v10, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t
-; RV32-NEXT: vand.vx v12, v12, a5, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v11, v0.t
; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vor.vv v8, v8, v10, v0.t
-; RV32-NEXT: vor.vv v8, v9, v8, v0.t
+; RV32-NEXT: vor.vv v8, v10, v8, v0.t
+; RV32-NEXT: vor.vv v9, v9, v11, v0.t
+; RV32-NEXT: vor.vv v8, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
@@ -311,29 +311,29 @@ define <2 x i64> @vp_bswap_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: lui a4, 16
; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV64-NEXT: vand.vx v9, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vsrl.vi v9, v8, 24, v0.t
+; RV64-NEXT: vsrl.vi v10, v8, 8, v0.t
; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v9, v9, 24, v0.t
+; RV64-NEXT: vsrl.vx v11, v8, a3, v0.t
+; RV64-NEXT: vsrl.vx v12, v8, a5, v0.t
+; RV64-NEXT: vand.vx v12, v12, a0, v0.t
+; RV64-NEXT: vor.vv v11, v12, v11, v0.t
+; RV64-NEXT: vand.vx v12, v8, a1, v0.t
+; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vand.vx v9, v9, a1, v0.t
+; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
+; RV64-NEXT: vand.vx v10, v10, a2, v0.t
+; RV64-NEXT: vor.vv v9, v10, v9, v0.t
; RV64-NEXT: vand.vx v10, v8, a2, v0.t
; RV64-NEXT: vsll.vi v10, v10, 8, v0.t
-; RV64-NEXT: vor.vv v9, v9, v10, v0.t
-; RV64-NEXT: vsll.vx v10, v8, a3, v0.t
-; RV64-NEXT: vand.vx v11, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v11, v11, a5, v0.t
-; RV64-NEXT: vor.vv v10, v10, v11, v0.t
-; RV64-NEXT: vor.vv v9, v10, v9, v0.t
-; RV64-NEXT: vsrl.vx v10, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v11, v8, a5, v0.t
-; RV64-NEXT: vand.vx v11, v11, a0, v0.t
-; RV64-NEXT: vor.vv v10, v11, v10, v0.t
-; RV64-NEXT: vsrl.vi v11, v8, 24, v0.t
-; RV64-NEXT: vand.vx v11, v11, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v11, v0.t
+; RV64-NEXT: vor.vv v10, v12, v10, v0.t
+; RV64-NEXT: vsll.vx v12, v8, a3, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsll.vx v8, v8, a5, v0.t
+; RV64-NEXT: vor.vv v8, v12, v8, v0.t
; RV64-NEXT: vor.vv v8, v8, v10, v0.t
-; RV64-NEXT: vor.vv v8, v9, v8, v0.t
+; RV64-NEXT: vor.vv v9, v9, v11, v0.t
+; RV64-NEXT: vor.vv v8, v8, v9, v0.t
; RV64-NEXT: ret
%v = call <2 x i64> @llvm.vp.bswap.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl)
ret <2 x i64> %v
@@ -429,34 +429,34 @@ define <4 x i64> @vp_bswap_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-NEXT: li a4, 40
; RV32-NEXT: lui a5, 4080
; RV32-NEXT: addi a6, sp, 8
+; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
+; RV32-NEXT: vsrl.vi v10, v8, 24, v0.t
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vsll.vx v10, v8, a2, v0.t
+; RV32-NEXT: vsll.vx v12, v8, a2, v0.t
; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vand.vx v12, v8, a1, v0.t
+; RV32-NEXT: vsrl.vx v14, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a4, v0.t
+; RV32-NEXT: vand.vx v18, v8, a1, v0.t
+; RV32-NEXT: vand.vx v16, v16, a1, v0.t
+; RV32-NEXT: vor.vv v14, v16, v14, v0.t
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32-NEXT: vlse64.v v14, (a6), zero
+; RV32-NEXT: vlse64.v v16, (a6), zero
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vsll.vx v12, v12, a4, v0.t
-; RV32-NEXT: vor.vv v10, v10, v12, v0.t
-; RV32-NEXT: vand.vx v12, v8, a5, v0.t
-; RV32-NEXT: vsll.vi v12, v12, 24, v0.t
-; RV32-NEXT: vand.vv v16, v8, v14, v0.t
+; RV32-NEXT: vsll.vx v18, v18, a4, v0.t
+; RV32-NEXT: vor.vv v12, v12, v18, v0.t
+; RV32-NEXT: vsrl.vi v18, v8, 8, v0.t
+; RV32-NEXT: vand.vx v10, v10, a5, v0.t
+; RV32-NEXT: vand.vv v18, v18, v16, v0.t
+; RV32-NEXT: vor.vv v10, v18, v10, v0.t
+; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vand.vx v8, v8, a5, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 24, v0.t
; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v12, v12, v16, v0.t
-; RV32-NEXT: vor.vv v10, v10, v12, v0.t
-; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a4, v0.t
-; RV32-NEXT: vand.vx v16, v16, a1, v0.t
-; RV32-NEXT: vor.vv v12, v16, v12, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV32-NEXT: vand.vx v16, v16, a5, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v14, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vor.vv v8, v10, v8, v0.t
+; RV32-NEXT: vor.vv v8, v12, v8, v0.t
+; RV32-NEXT: vor.vv v10, v10, v14, v0.t
+; RV32-NEXT: vor.vv v8, v8, v10, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
@@ -469,29 +469,29 @@ define <4 x i64> @vp_bswap_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: lui a4, 16
; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV64-NEXT: vand.vx v10, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vsrl.vi v10, v8, 24, v0.t
+; RV64-NEXT: vsrl.vi v12, v8, 8, v0.t
; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v10, v10, 24, v0.t
+; RV64-NEXT: vsrl.vx v14, v8, a3, v0.t
+; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
+; RV64-NEXT: vand.vx v16, v16, a0, v0.t
+; RV64-NEXT: vor.vv v14, v16, v14, v0.t
+; RV64-NEXT: vand.vx v16, v8, a1, v0.t
+; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vand.vx v10, v10, a1, v0.t
+; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
+; RV64-NEXT: vand.vx v12, v12, a2, v0.t
+; RV64-NEXT: vor.vv v10, v12, v10, v0.t
; RV64-NEXT: vand.vx v12, v8, a2, v0.t
; RV64-NEXT: vsll.vi v12, v12, 8, v0.t
-; RV64-NEXT: vor.vv v10, v10, v12, v0.t
-; RV64-NEXT: vsll.vx v12, v8, a3, v0.t
-; RV64-NEXT: vand.vx v14, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v14, v14, a5, v0.t
-; RV64-NEXT: vor.vv v12, v12, v14, v0.t
-; RV64-NEXT: vor.vv v10, v12, v10, v0.t
-; RV64-NEXT: vsrl.vx v12, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v14, v8, a5, v0.t
-; RV64-NEXT: vand.vx v14, v14, a0, v0.t
-; RV64-NEXT: vor.vv v12, v14, v12, v0.t
-; RV64-NEXT: vsrl.vi v14, v8, 24, v0.t
-; RV64-NEXT: vand.vx v14, v14, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v14, v0.t
+; RV64-NEXT: vor.vv v12, v16, v12, v0.t
+; RV64-NEXT: vsll.vx v16, v8, a3, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsll.vx v8, v8, a5, v0.t
+; RV64-NEXT: vor.vv v8, v16, v8, v0.t
; RV64-NEXT: vor.vv v8, v8, v12, v0.t
-; RV64-NEXT: vor.vv v8, v10, v8, v0.t
+; RV64-NEXT: vor.vv v10, v10, v14, v0.t
+; RV64-NEXT: vor.vv v8, v8, v10, v0.t
; RV64-NEXT: ret
%v = call <4 x i64> @llvm.vp.bswap.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)
ret <4 x i64> %v
@@ -587,34 +587,34 @@ define <8 x i64> @vp_bswap_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32-NEXT: li a4, 40
; RV32-NEXT: lui a5, 4080
; RV32-NEXT: addi a6, sp, 8
+; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
+; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
+; RV32-NEXT: vsll.vx v20, v8, a2, v0.t
; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vand.vx v20, v8, a1, v0.t
+; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t
+; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
+; RV32-NEXT: vand.vx v28, v8, a1, v0.t
+; RV32-NEXT: vand.vx v24, v24, a1, v0.t
+; RV32-NEXT: vor.vv v12, v24, v12, v0.t
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vlse64.v v12, (a6), zero
+; RV32-NEXT: vlse64.v v24, (a6), zero
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsll.vx v20, v20, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vand.vx v20, v8, a5, v0.t
-; RV32-NEXT: vsll.vi v20, v20, 24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v12, v0.t
+; RV32-NEXT: vsll.vx v28, v28, a4, v0.t
+; RV32-NEXT: vor.vv v20, v20, v28, v0.t
+; RV32-NEXT: vsrl.vi v28, v8, 8, v0.t
+; RV32-NEXT: vand.vx v16, v16, a5, v0.t
+; RV32-NEXT: vand.vv v28, v28, v24, v0.t
+; RV32-NEXT: vor.vv v16, v28, v16, v0.t
+; RV32-NEXT: vand.vv v24, v8, v24, v0.t
+; RV32-NEXT: vand.vx v8, v8, a5, v0.t
+; RV32-NEXT: vsll.vi v8, v8, 24, v0.t
; RV32-NEXT: vsll.vi v24, v24, 8, v0.t
-; RV32-NEXT: vor.vv v20, v20, v24, v0.t
-; RV32-NEXT: vor.vv v16, v16, v20, v0.t
-; RV32-NEXT: vsrl.vx v20, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vor.vv v20, v24, v20, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a5, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vor.vv v8, v8, v20, v0.t
-; RV32-NEXT: vor.vv v8, v16, v8, v0.t
+; RV32-NEXT: vor.vv v8, v20, v8, v0.t
+; RV32-NEXT: vor.vv v12, v16, v12, v0.t
+; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
@@ -627,29 +627,29 @@ define <8 x i64> @vp_bswap_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: lui a4, 16
; RV64-NEXT: li a5, 40
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV64-NEXT: vand.vx v12, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
+; RV64-NEXT: vsrl.vi v20, v8, 8, v0.t
; RV64-NEXT: addi a0, a4, -256
-; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
-; RV64-NEXT: vand.vx v16, v8, a2, v0.t
-; RV64-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV64-NEXT: vor.vv v12, v12, v16, v0.t
-; RV64-NEXT: vsll.vx v16, v8, a3, v0.t
-; RV64-NEXT: vand.vx v20, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v20, v20, a5, v0.t
-; RV64-NEXT: vor.vv v16, v16, v20, v0.t
-; RV64-NEXT: vor.vv v12, v16, v12, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v20, v8, a5, v0.t
-; RV64-NEXT: vand.vx v20, v20, a0, v0.t
+; RV64-NEXT: vsrl.vx v12, v8, a3, v0.t
+; RV64-NEXT: vsrl.vx v24, v8, a5, v0.t
+; RV64-NEXT: vand.vx v24, v24, a0, v0.t
+; RV64-NEXT: vor.vv v12, v24, v12, v0.t
+; RV64-NEXT: vand.vx v24, v8, a1, v0.t
+; RV64-NEXT: slli a2, a2, 24
+; RV64-NEXT: vand.vx v16, v16, a1, v0.t
+; RV64-NEXT: vsll.vi v24, v24, 24, v0.t
+; RV64-NEXT: vand.vx v20, v20, a2, v0.t
; RV64-NEXT: vor.vv v16, v20, v16, v0.t
-; RV64-NEXT: vsrl.vi v20, v8, 24, v0.t
-; RV64-NEXT: vand.vx v20, v20, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vand.vx v20, v8, a2, v0.t
+; RV64-NEXT: vsll.vi v20, v20, 8, v0.t
+; RV64-NEXT: vor.vv v20, v24, v20, v0.t
+; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
+; RV64-NEXT: vand.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsll.vx v8, v8, a5, v0.t
+; RV64-NEXT: vor.vv v8, v24, v8, v0.t
; RV64-NEXT: vor.vv v8, v8, v20, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
-; RV64-NEXT: vor.vv v8, v12, v8, v0.t
+; RV64-NEXT: vor.vv v12, v16, v12, v0.t
+; RV64-NEXT: vor.vv v8, v8, v12, v0.t
; RV64-NEXT: ret
%v = call <8 x i64> @llvm.vp.bswap.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl)
ret <8 x i64> %v
@@ -740,77 +740,134 @@ define <15 x i64> @vp_bswap_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %ev
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a2, a1, 5
+; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: lui a2, 16
+; RV32-NEXT: li a3, 40
+; RV32-NEXT: addi a2, a2, -256
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: vsrl.vx v24, v8, a3, v0.t
+; RV32-NEXT: vand.vx v24, v24, a2, v0.t
+; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: slli a4, a4, 4
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: slli a4, a4, 5
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vand.vx v16, v8, a2, v0.t
+; RV32-NEXT: vsll.vx v16, v16, a3, v0.t
+; RV32-NEXT: vsll.vx v24, v8, a1, v0.t
+; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: lui a2, 4080
+; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vand.vx v24, v8, a1, v0.t
-; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vlse64.v v16, (a5), zero
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a3, 4080
+; RV32-NEXT: vlse64.v v16, (a3), zero
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vx v16, v8, a3, v0.t
-; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vx v16, v24, a2, v0.t
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a3, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: li a1, 24
+; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vor.vv v24, v24, v16, v0.t
+; RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vx v24, v8, a2, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 24
+; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
@@ -818,8 +875,22 @@ define <15 x i64> @vp_bswap_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %ev
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a1, a0, 5
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
; RV32-NEXT: addi sp, sp, 16
@@ -831,46 +902,121 @@ define <15 x i64> @vp_bswap_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %ev
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: slli a2, a1, 4
+; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
+; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
+; RV64-NEXT: lui a2, 4080
+; RV64-NEXT: li a3, 255
+; RV64-NEXT: li a1, 56
; RV64-NEXT: lui a4, 16
; RV64-NEXT: li a5, 40
+; RV64-NEXT: addi a4, a4, -256
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
+; RV64-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV64-NEXT: vsrl.vx v24, v8, a5, v0.t
+; RV64-NEXT: vand.vx v24, v24, a4, v0.t
+; RV64-NEXT: vor.vv v16, v24, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs1r.v v0, (a0) # vscale x 8-byte Folded Spill
+; RV64-NEXT: vsrl.vi v24, v8, 24, v0.t
+; RV64-NEXT: slli a3, a3, 24
+; RV64-NEXT: vand.vx v24, v24, a2, v0.t
+; RV64-NEXT: vsrl.vi v16, v8, 8, v0.t
+; RV64-NEXT: vand.vx v16, v16, a3, v0.t
+; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v16, v8, a2, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v24, v8, a3, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
-; RV64-NEXT: vand.vx v16, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v16, v16, a5, v0.t
-; RV64-NEXT: vor.vv v16, v24, v16, v0.t
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vor.vv v24, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v24, v8, a4, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsll.vx v24, v24, a5, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsll.vx v8, v8, a1, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vor.vv v8, v8, v16, v0.t
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vor.vv v16, v24, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vor.vv v8, v8, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a1, a0, 4
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 16
; RV64-NEXT: addi sp, sp, 16
@@ -1003,77 +1149,134 @@ define <16 x i64> @vp_bswap_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %ev
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a2, a1, 5
+; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: lui a2, 16
+; RV32-NEXT: li a3, 40
+; RV32-NEXT: addi a2, a2, -256
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: vsrl.vx v24, v8, a3, v0.t
+; RV32-NEXT: vand.vx v24, v24, a2, v0.t
+; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: slli a4, a4, 4
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: slli a4, a4, 5
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vand.vx v16, v8, a2, v0.t
+; RV32-NEXT: vsll.vx v16, v16, a3, v0.t
+; RV32-NEXT: vsll.vx v24, v8, a1, v0.t
+; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: lui a1, 1044480
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: lui a3, 16
-; RV32-NEXT: li a4, 40
-; RV32-NEXT: addi a5, sp, 8
+; RV32-NEXT: lui a2, 4080
+; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: sw zero, 12(sp)
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsll.vx v16, v8, a2, v0.t
-; RV32-NEXT: addi a1, a3, -256
-; RV32-NEXT: vand.vx v24, v8, a1, v0.t
-; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vlse64.v v16, (a5), zero
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a3, 4080
+; RV32-NEXT: vlse64.v v16, (a3), zero
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vx v16, v8, a3, v0.t
-; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vx v16, v24, a2, v0.t
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t
-; RV32-NEXT: vand.vx v24, v24, a1, v0.t
-; RV32-NEXT: vor.vv v16, v24, v16, v0.t
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
-; RV32-NEXT: vand.vx v24, v24, a3, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: li a1, 24
+; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vor.vv v24, v24, v16, v0.t
+; RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vx v24, v8, a2, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 24
+; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
@@ -1081,8 +1284,22 @@ define <16 x i64> @vp_bswap_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %ev
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 5
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vor.vv v16, v24, v16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a1, a0, 5
+; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
; RV32-NEXT: addi sp, sp, 16
@@ -1094,46 +1311,121 @@ define <16 x i64> @vp_bswap_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %ev
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: slli a2, a1, 4
+; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: sub sp, sp, a1
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; RV64-NEXT: lui a1, 4080
-; RV64-NEXT: li a2, 255
-; RV64-NEXT: li a3, 56
+; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
+; RV64-NEXT: lui a2, 4080
+; RV64-NEXT: li a3, 255
+; RV64-NEXT: li a1, 56
; RV64-NEXT: lui a4, 16
; RV64-NEXT: li a5, 40
+; RV64-NEXT: addi a4, a4, -256
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v8, a1, v0.t
-; RV64-NEXT: slli a2, a2, 24
-; RV64-NEXT: addi a0, a4, -256
+; RV64-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV64-NEXT: vsrl.vx v24, v8, a5, v0.t
+; RV64-NEXT: vand.vx v24, v24, a4, v0.t
+; RV64-NEXT: vor.vv v16, v24, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vs1r.v v0, (a0) # vscale x 8-byte Folded Spill
+; RV64-NEXT: vsrl.vi v24, v8, 24, v0.t
+; RV64-NEXT: slli a3, a3, 24
+; RV64-NEXT: vand.vx v24, v24, a2, v0.t
+; RV64-NEXT: vsrl.vi v16, v8, 8, v0.t
+; RV64-NEXT: vand.vx v16, v16, a3, v0.t
+; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v16, v8, a2, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsll.vi v16, v16, 24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v24, v8, a3, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsll.vi v24, v24, 8, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: addi a4, sp, 16
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsll.vx v24, v8, a3, v0.t
-; RV64-NEXT: vand.vx v16, v8, a0, v0.t
-; RV64-NEXT: vsll.vx v16, v16, a5, v0.t
-; RV64-NEXT: vor.vv v16, v24, v16, v0.t
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsrl.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v8, a5, v0.t
-; RV64-NEXT: vand.vx v16, v16, a0, v0.t
-; RV64-NEXT: vor.vv v24, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v16, v8, 24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vor.vv v8, v8, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vand.vx v24, v8, a4, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsll.vx v24, v24, a5, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsll.vx v8, v8, a1, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vor.vv v8, v16, v8, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vor.vv v8, v8, v16, v0.t
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vor.vv v16, v24, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vor.vv v8, v8, v16, v0.t
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a1, a0, 4
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 16
; RV64-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
index f3406b5c470ce..f4a60d33faaa6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
@@ -132,8 +132,8 @@ define <4 x i32> @udiv_constant_rhs(i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK-NEXT: vsub.vv v12, v8, v10
; CHECK-NEXT: vmulhu.vv v9, v12, v9
; CHECK-NEXT: vadd.vv v9, v9, v10
-; CHECK-NEXT: vmv.v.i v0, 4
; CHECK-NEXT: vsrl.vv v9, v9, v11
+; CHECK-NEXT: vmv.v.i v0, 4
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
; CHECK-NEXT: ret
%e0 = udiv i32 %a, 23
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
index 4452e161ad593..5d1a22368ddef 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
@@ -16,9 +16,9 @@ define <2 x half> @vp_ceil_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl)
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 3
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 3
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -30,26 +30,24 @@ define <2 x half> @vp_ceil_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl)
; ZVFHMIN-LABEL: vp_ceil_v2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 3
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <2 x half> @llvm.vp.ceil.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl)
ret <2 x half> %v
@@ -63,8 +61,8 @@ define <2 x half> @vp_ceil_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 3
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -77,11 +75,11 @@ define <2 x half> @vp_ceil_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) {
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -102,9 +100,9 @@ define <4 x half> @vp_ceil_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl)
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 3
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 3
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -116,26 +114,24 @@ define <4 x half> @vp_ceil_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl)
; ZVFHMIN-LABEL: vp_ceil_v4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 3
-; ZVFHMIN-NEXT: vmv.v.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <4 x half> @llvm.vp.ceil.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)
ret <4 x half> %v
@@ -149,8 +145,8 @@ define <4 x half> @vp_ceil_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 3
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -163,11 +159,11 @@ define <4 x half> @vp_ceil_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -188,9 +184,9 @@ define <8 x half> @vp_ceil_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl)
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 3
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 3
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -205,21 +201,21 @@ define <8 x half> @vp_ceil_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl)
; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v13, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: fsrmi a0, 3
-; ZVFHMIN-NEXT: vmv1r.v v0, v13
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
+; ZVFHMIN-NEXT: vmv1r.v v0, v13
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: ret
@@ -235,8 +231,8 @@ define <8 x half> @vp_ceil_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 3
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -249,11 +245,11 @@ define <8 x half> @vp_ceil_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) {
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -293,21 +289,21 @@ define <16 x half> @vp_ceil_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %e
; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: fsrmi a0, 3
-; ZVFHMIN-NEXT: vmv1r.v v0, v17
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vmv1r.v v0, v17
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
@@ -323,8 +319,8 @@ define <16 x half> @vp_ceil_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 3
+; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -337,11 +333,11 @@ define <16 x half> @vp_ceil_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl) {
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -361,9 +357,9 @@ define <2 x float> @vp_ceil_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroext %evl
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -382,8 +378,8 @@ define <2 x float> @vp_ceil_v2f32_unmasked(<2 x float> %va, i32 zeroext %evl) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -401,9 +397,9 @@ define <4 x float> @vp_ceil_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -422,8 +418,8 @@ define <4 x float> @vp_ceil_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -464,8 +460,8 @@ define <8 x float> @vp_ceil_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) {
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -506,8 +502,8 @@ define <16 x float> @vp_ceil_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl)
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -525,9 +521,9 @@ define <2 x double> @vp_ceil_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %e
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI16_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZVFH-NEXT: fsrmi a0, 3
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a0, 3
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
@@ -543,9 +539,9 @@ define <2 x double> @vp_ceil_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %e
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
+; RV64ZVFH-NEXT: fsrmi a0, 3
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZVFH-NEXT: fsrmi a0, 3
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
@@ -560,9 +556,9 @@ define <2 x double> @vp_ceil_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %e
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI16_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZVFHMIN-NEXT: fsrmi a0, 3
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a0, 3
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
@@ -578,9 +574,9 @@ define <2 x double> @vp_ceil_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %e
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
+; RV64ZVFHMIN-NEXT: fsrmi a0, 3
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a0, 3
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
@@ -599,8 +595,8 @@ define <2 x double> @vp_ceil_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl)
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI17_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: fsrmi a0, 3
+; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -615,8 +611,8 @@ define <2 x double> @vp_ceil_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl)
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: fsrmi a0, 3
+; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -630,8 +626,8 @@ define <2 x double> @vp_ceil_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl)
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI17_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 3
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -646,8 +642,8 @@ define <2 x double> @vp_ceil_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl)
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 3
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -747,8 +743,8 @@ define <4 x double> @vp_ceil_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl)
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI19_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZVFH-NEXT: vfabs.v v10, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: fsrmi a0, 3
+; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -763,8 +759,8 @@ define <4 x double> @vp_ceil_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl)
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: fsrmi a0, 3
+; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -778,8 +774,8 @@ define <4 x double> @vp_ceil_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl)
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI19_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v10, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 3
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -794,8 +790,8 @@ define <4 x double> @vp_ceil_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl)
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 3
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -895,8 +891,8 @@ define <8 x double> @vp_ceil_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI21_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZVFH-NEXT: vfabs.v v12, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: fsrmi a0, 3
+; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -911,8 +907,8 @@ define <8 x double> @vp_ceil_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: fsrmi a0, 3
+; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -926,8 +922,8 @@ define <8 x double> @vp_ceil_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI21_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v12, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 3
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -942,8 +938,8 @@ define <8 x double> @vp_ceil_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 3
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1043,8 +1039,8 @@ define <15 x double> @vp_ceil_v15f64_unmasked(<15 x double> %va, i32 zeroext %ev
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI23_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 3
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1059,8 +1055,8 @@ define <15 x double> @vp_ceil_v15f64_unmasked(<15 x double> %va, i32 zeroext %ev
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 3
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1074,8 +1070,8 @@ define <15 x double> @vp_ceil_v15f64_unmasked(<15 x double> %va, i32 zeroext %ev
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI23_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 3
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1090,8 +1086,8 @@ define <15 x double> @vp_ceil_v15f64_unmasked(<15 x double> %va, i32 zeroext %ev
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 3
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1191,8 +1187,8 @@ define <16 x double> @vp_ceil_v16f64_unmasked(<16 x double> %va, i32 zeroext %ev
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 3
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1207,8 +1203,8 @@ define <16 x double> @vp_ceil_v16f64_unmasked(<16 x double> %va, i32 zeroext %ev
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 3
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1222,8 +1218,8 @@ define <16 x double> @vp_ceil_v16f64_unmasked(<16 x double> %va, i32 zeroext %ev
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 3
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1238,8 +1234,8 @@ define <16 x double> @vp_ceil_v16f64_unmasked(<16 x double> %va, i32 zeroext %ev
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 3
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1254,43 +1250,43 @@ define <32 x double> @vp_ceil_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroex
; RV32ZVFH-LABEL: vp_ceil_v32f64:
; RV32ZVFH: # %bb.0:
; RV32ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32ZVFH-NEXT: vmv1r.v v6, v0
+; RV32ZVFH-NEXT: vmv1r.v v7, v0
; RV32ZVFH-NEXT: li a2, 16
-; RV32ZVFH-NEXT: vslidedown.vi v7, v0, 2
+; RV32ZVFH-NEXT: vslidedown.vi v6, v0, 2
; RV32ZVFH-NEXT: mv a1, a0
; RV32ZVFH-NEXT: bltu a0, a2, .LBB26_2
; RV32ZVFH-NEXT: # %bb.1:
; RV32ZVFH-NEXT: li a1, 16
; RV32ZVFH-NEXT: .LBB26_2:
-; RV32ZVFH-NEXT: vmv1r.v v0, v6
+; RV32ZVFH-NEXT: vmv1r.v v0, v7
; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v8, v0.t
-; RV32ZVFH-NEXT: lui a1, %hi(.LCPI26_0)
-; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
-; RV32ZVFH-NEXT: addi a1, a0, -16
-; RV32ZVFH-NEXT: sltu a0, a0, a1
+; RV32ZVFH-NEXT: lui a2, %hi(.LCPI26_0)
+; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
+; RV32ZVFH-NEXT: addi a2, a0, -16
+; RV32ZVFH-NEXT: sltu a0, a0, a2
; RV32ZVFH-NEXT: addi a0, a0, -1
-; RV32ZVFH-NEXT: and a0, a0, a1
+; RV32ZVFH-NEXT: and a0, a0, a2
+; RV32ZVFH-NEXT: fsrmi a2, 3
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a1, 3
+; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV32ZVFH-NEXT: vmv1r.v v0, v6
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t
+; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV32ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV32ZVFH-NEXT: vmv1r.v v0, v7
+; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFH-NEXT: fsrm a1
+; RV32ZVFH-NEXT: fsrm a2
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFH-NEXT: vmv1r.v v0, v7
+; RV32ZVFH-NEXT: vmv1r.v v0, v6
+; RV32ZVFH-NEXT: fsrmi a1, 3
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a0, 3
-; RV32ZVFH-NEXT: vmv1r.v v0, v7
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFH-NEXT: fsrm a0
+; RV32ZVFH-NEXT: fsrm a1
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1299,44 +1295,44 @@ define <32 x double> @vp_ceil_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroex
; RV64ZVFH-LABEL: vp_ceil_v32f64:
; RV64ZVFH: # %bb.0:
; RV64ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVFH-NEXT: vmv1r.v v6, v0
+; RV64ZVFH-NEXT: vmv1r.v v7, v0
; RV64ZVFH-NEXT: li a2, 16
-; RV64ZVFH-NEXT: vslidedown.vi v7, v0, 2
+; RV64ZVFH-NEXT: vslidedown.vi v6, v0, 2
; RV64ZVFH-NEXT: mv a1, a0
; RV64ZVFH-NEXT: bltu a0, a2, .LBB26_2
; RV64ZVFH-NEXT: # %bb.1:
; RV64ZVFH-NEXT: li a1, 16
; RV64ZVFH-NEXT: .LBB26_2:
-; RV64ZVFH-NEXT: vmv1r.v v0, v6
+; RV64ZVFH-NEXT: vmv1r.v v0, v7
; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v8, v0.t
-; RV64ZVFH-NEXT: li a1, 1075
-; RV64ZVFH-NEXT: slli a1, a1, 52
-; RV64ZVFH-NEXT: fmv.d.x fa5, a1
-; RV64ZVFH-NEXT: addi a1, a0, -16
-; RV64ZVFH-NEXT: sltu a0, a0, a1
+; RV64ZVFH-NEXT: li a2, 1075
+; RV64ZVFH-NEXT: slli a2, a2, 52
+; RV64ZVFH-NEXT: fmv.d.x fa5, a2
+; RV64ZVFH-NEXT: addi a2, a0, -16
+; RV64ZVFH-NEXT: sltu a0, a0, a2
; RV64ZVFH-NEXT: addi a0, a0, -1
+; RV64ZVFH-NEXT: and a0, a0, a2
+; RV64ZVFH-NEXT: fsrmi a2, 3
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV64ZVFH-NEXT: and a0, a0, a1
-; RV64ZVFH-NEXT: fsrmi a1, 3
+; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV64ZVFH-NEXT: vmv1r.v v0, v6
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t
+; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV64ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV64ZVFH-NEXT: vmv1r.v v0, v7
+; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFH-NEXT: fsrm a1
+; RV64ZVFH-NEXT: fsrm a2
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
+; RV64ZVFH-NEXT: fsrmi a1, 3
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFH-NEXT: vmv1r.v v0, v7
+; RV64ZVFH-NEXT: vmv1r.v v0, v6
; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV64ZVFH-NEXT: fsrmi a0, 3
-; RV64ZVFH-NEXT: vmv1r.v v0, v7
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFH-NEXT: fsrm a0
+; RV64ZVFH-NEXT: fsrm a1
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1345,43 +1341,43 @@ define <32 x double> @vp_ceil_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroex
; RV32ZVFHMIN-LABEL: vp_ceil_v32f64:
; RV32ZVFHMIN: # %bb.0:
; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32ZVFHMIN-NEXT: vmv1r.v v6, v0
+; RV32ZVFHMIN-NEXT: vmv1r.v v7, v0
; RV32ZVFHMIN-NEXT: li a2, 16
-; RV32ZVFHMIN-NEXT: vslidedown.vi v7, v0, 2
+; RV32ZVFHMIN-NEXT: vslidedown.vi v6, v0, 2
; RV32ZVFHMIN-NEXT: mv a1, a0
; RV32ZVFHMIN-NEXT: bltu a0, a2, .LBB26_2
; RV32ZVFHMIN-NEXT: # %bb.1:
; RV32ZVFHMIN-NEXT: li a1, 16
; RV32ZVFHMIN-NEXT: .LBB26_2:
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI26_0)
-; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
-; RV32ZVFHMIN-NEXT: addi a1, a0, -16
-; RV32ZVFHMIN-NEXT: sltu a0, a0, a1
+; RV32ZVFHMIN-NEXT: lui a2, %hi(.LCPI26_0)
+; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
+; RV32ZVFHMIN-NEXT: addi a2, a0, -16
+; RV32ZVFHMIN-NEXT: sltu a0, a0, a2
; RV32ZVFHMIN-NEXT: addi a0, a0, -1
-; RV32ZVFHMIN-NEXT: and a0, a0, a1
+; RV32ZVFHMIN-NEXT: and a0, a0, a2
+; RV32ZVFHMIN-NEXT: fsrmi a2, 3
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a1, 3
+; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
+; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV32ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a1
+; RV32ZVFHMIN-NEXT: fsrm a2
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV32ZVFHMIN-NEXT: fsrmi a1, 3
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a0, 3
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a0
+; RV32ZVFHMIN-NEXT: fsrm a1
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1390,44 +1386,44 @@ define <32 x double> @vp_ceil_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroex
; RV64ZVFHMIN-LABEL: vp_ceil_v32f64:
; RV64ZVFHMIN: # %bb.0:
; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVFHMIN-NEXT: vmv1r.v v6, v0
+; RV64ZVFHMIN-NEXT: vmv1r.v v7, v0
; RV64ZVFHMIN-NEXT: li a2, 16
-; RV64ZVFHMIN-NEXT: vslidedown.vi v7, v0, 2
+; RV64ZVFHMIN-NEXT: vslidedown.vi v6, v0, 2
; RV64ZVFHMIN-NEXT: mv a1, a0
; RV64ZVFHMIN-NEXT: bltu a0, a2, .LBB26_2
; RV64ZVFHMIN-NEXT: # %bb.1:
; RV64ZVFHMIN-NEXT: li a1, 16
; RV64ZVFHMIN-NEXT: .LBB26_2:
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: li a1, 1075
-; RV64ZVFHMIN-NEXT: slli a1, a1, 52
-; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a1
-; RV64ZVFHMIN-NEXT: addi a1, a0, -16
-; RV64ZVFHMIN-NEXT: sltu a0, a0, a1
+; RV64ZVFHMIN-NEXT: li a2, 1075
+; RV64ZVFHMIN-NEXT: slli a2, a2, 52
+; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a2
+; RV64ZVFHMIN-NEXT: addi a2, a0, -16
+; RV64ZVFHMIN-NEXT: sltu a0, a0, a2
; RV64ZVFHMIN-NEXT: addi a0, a0, -1
+; RV64ZVFHMIN-NEXT: and a0, a0, a2
+; RV64ZVFHMIN-NEXT: fsrmi a2, 3
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV64ZVFHMIN-NEXT: and a0, a0, a1
-; RV64ZVFHMIN-NEXT: fsrmi a1, 3
+; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
+; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV64ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a1
+; RV64ZVFHMIN-NEXT: fsrm a2
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
+; RV64ZVFHMIN-NEXT: fsrmi a1, 3
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a0, 3
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a0
+; RV64ZVFHMIN-NEXT: fsrm a1
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1447,28 +1443,25 @@ define <32 x double> @vp_ceil_v32f64_unmasked(<32 x double> %va, i32 zeroext %ev
; RV32ZVFH-NEXT: .LBB27_2:
; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v8
-; RV32ZVFH-NEXT: lui a2, %hi(.LCPI27_0)
-; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
-; RV32ZVFH-NEXT: addi a2, a0, -16
-; RV32ZVFH-NEXT: sltu a0, a0, a2
+; RV32ZVFH-NEXT: lui a1, %hi(.LCPI27_0)
+; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
+; RV32ZVFH-NEXT: addi a1, a0, -16
+; RV32ZVFH-NEXT: sltu a0, a0, a1
; RV32ZVFH-NEXT: addi a0, a0, -1
-; RV32ZVFH-NEXT: and a0, a0, a2
-; RV32ZVFH-NEXT: fsrmi a2, 3
+; RV32ZVFH-NEXT: and a0, a0, a1
+; RV32ZVFH-NEXT: fsrmi a1, 3
; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFH-NEXT: vfabs.v v24, v16
-; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5
-; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFH-NEXT: fsrm a2
+; RV32ZVFH-NEXT: fsrm a1
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV32ZVFH-NEXT: fsrmi a1, 3
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFH-NEXT: vmv1r.v v0, v7
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFH-NEXT: vfabs.v v24, v16
+; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
+; RV32ZVFH-NEXT: fsrmi a0, 3
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFH-NEXT: fsrm a1
+; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1484,29 +1477,26 @@ define <32 x double> @vp_ceil_v32f64_unmasked(<32 x double> %va, i32 zeroext %ev
; RV64ZVFH-NEXT: .LBB27_2:
; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v8
-; RV64ZVFH-NEXT: li a2, 1075
-; RV64ZVFH-NEXT: slli a2, a2, 52
-; RV64ZVFH-NEXT: fmv.d.x fa5, a2
-; RV64ZVFH-NEXT: addi a2, a0, -16
-; RV64ZVFH-NEXT: sltu a0, a0, a2
+; RV64ZVFH-NEXT: li a1, 1075
+; RV64ZVFH-NEXT: slli a1, a1, 52
+; RV64ZVFH-NEXT: fmv.d.x fa5, a1
+; RV64ZVFH-NEXT: addi a1, a0, -16
+; RV64ZVFH-NEXT: sltu a0, a0, a1
; RV64ZVFH-NEXT: addi a0, a0, -1
-; RV64ZVFH-NEXT: and a0, a0, a2
-; RV64ZVFH-NEXT: fsrmi a2, 3
+; RV64ZVFH-NEXT: and a0, a0, a1
+; RV64ZVFH-NEXT: fsrmi a1, 3
; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFH-NEXT: vfabs.v v24, v16
-; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5
-; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFH-NEXT: fsrm a2
+; RV64ZVFH-NEXT: fsrm a1
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV64ZVFH-NEXT: fsrmi a1, 3
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFH-NEXT: vmv1r.v v0, v7
; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFH-NEXT: vfabs.v v24, v16
+; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
+; RV64ZVFH-NEXT: fsrmi a0, 3
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFH-NEXT: fsrm a1
+; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1522,28 +1512,25 @@ define <32 x double> @vp_ceil_v32f64_unmasked(<32 x double> %va, i32 zeroext %ev
; RV32ZVFHMIN-NEXT: .LBB27_2:
; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v8
-; RV32ZVFHMIN-NEXT: lui a2, %hi(.LCPI27_0)
-; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
-; RV32ZVFHMIN-NEXT: addi a2, a0, -16
-; RV32ZVFHMIN-NEXT: sltu a0, a0, a2
+; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI27_0)
+; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
+; RV32ZVFHMIN-NEXT: addi a1, a0, -16
+; RV32ZVFHMIN-NEXT: sltu a0, a0, a1
; RV32ZVFHMIN-NEXT: addi a0, a0, -1
-; RV32ZVFHMIN-NEXT: and a0, a0, a2
-; RV32ZVFHMIN-NEXT: fsrmi a2, 3
+; RV32ZVFHMIN-NEXT: and a0, a0, a1
+; RV32ZVFHMIN-NEXT: fsrmi a1, 3
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFHMIN-NEXT: vfabs.v v24, v16
-; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5
-; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a2
+; RV32ZVFHMIN-NEXT: fsrm a1
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a1, 3
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFHMIN-NEXT: vfabs.v v24, v16
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
+; RV32ZVFHMIN-NEXT: fsrmi a0, 3
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a1
+; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1559,29 +1546,26 @@ define <32 x double> @vp_ceil_v32f64_unmasked(<32 x double> %va, i32 zeroext %ev
; RV64ZVFHMIN-NEXT: .LBB27_2:
; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v8
-; RV64ZVFHMIN-NEXT: li a2, 1075
-; RV64ZVFHMIN-NEXT: slli a2, a2, 52
-; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a2
-; RV64ZVFHMIN-NEXT: addi a2, a0, -16
-; RV64ZVFHMIN-NEXT: sltu a0, a0, a2
+; RV64ZVFHMIN-NEXT: li a1, 1075
+; RV64ZVFHMIN-NEXT: slli a1, a1, 52
+; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a1
+; RV64ZVFHMIN-NEXT: addi a1, a0, -16
+; RV64ZVFHMIN-NEXT: sltu a0, a0, a1
; RV64ZVFHMIN-NEXT: addi a0, a0, -1
-; RV64ZVFHMIN-NEXT: and a0, a0, a2
-; RV64ZVFHMIN-NEXT: fsrmi a2, 3
+; RV64ZVFHMIN-NEXT: and a0, a0, a1
+; RV64ZVFHMIN-NEXT: fsrmi a1, 3
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFHMIN-NEXT: vfabs.v v24, v16
-; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5
-; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a2
+; RV64ZVFHMIN-NEXT: fsrm a1
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a1, 3
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFHMIN-NEXT: vfabs.v v24, v16
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
+; RV64ZVFHMIN-NEXT: fsrmi a0, 3
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a1
+; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
index 00c36cb7f7327..0a1dcd4c6abb7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
@@ -890,11 +890,11 @@ define <2 x i64> @vp_ctlz_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV32-NEXT: vadd.vv v8, v8, v9, v0.t
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v9, a1
-; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v8, v8, v10, v0.t
; RV32-NEXT: vmul.vv v8, v8, v9, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctlz_v2i64:
@@ -940,8 +940,8 @@ define <2 x i64> @vp_ctlz_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl)
@@ -1056,29 +1056,29 @@ define <4 x i64> @vp_ctlz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v4i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
+; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v10, a1
+; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t
+; RV32-NEXT: vor.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsrl.vi v10, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsrl.vi v10, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsrl.vi v10, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsrl.vx v10, v8, a1, v0.t
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
+; RV32-NEXT: vor.vv v8, v8, v10, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
-; RV32-NEXT: vand.vv v10, v12, v10, v0.t
+; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
+; RV32-NEXT: vand.vv v10, v10, v12, v0.t
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: lui a1, 61681
@@ -1098,11 +1098,11 @@ define <4 x i64> @vp_ctlz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-NEXT: vadd.vv v8, v8, v10, v0.t
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v10, a1
-; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: vmul.vv v8, v8, v10, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctlz_v4i64:
@@ -1148,8 +1148,8 @@ define <4 x i64> @vp_ctlz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl)
@@ -1264,53 +1264,53 @@ define <8 x i64> @vp_ctlz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v12, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: vor.vv v8, v8, v12, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v12, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v12, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v12, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v12, v0.t
+; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vnot.v v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t
-; RV32-NEXT: vand.vv v12, v8, v12, v0.t
+; RV32-NEXT: vor.vv v8, v8, v12, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
+; RV32-NEXT: vand.vv v12, v12, v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsub.vv v12, v16, v12, v0.t
-; RV32-NEXT: vand.vv v16, v12, v8, v0.t
-; RV32-NEXT: vsrl.vi v12, v12, 2, v0.t
-; RV32-NEXT: vand.vv v8, v12, v8, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v12, v0.t
+; RV32-NEXT: vand.vv v12, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v12, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vadd.vv v8, v12, v8, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v12, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v16, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v12, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctlz_v8i64:
@@ -1356,8 +1356,8 @@ define <8 x i64> @vp_ctlz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl)
@@ -1472,53 +1472,53 @@ define <15 x i64> @vp_ctlz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl
; RV32-LABEL: vp_ctlz_v15i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vnot.v v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v8, v24, 1, v0.t
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v24, v16, v24, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsub.vv v24, v24, v16, v0.t
-; RV32-NEXT: vand.vv v16, v24, v8, v0.t
+; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: vand.vv v8, v24, v16, v0.t
; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
+; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctlz_v15i64:
@@ -1564,8 +1564,8 @@ define <15 x i64> @vp_ctlz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl)
@@ -1680,53 +1680,53 @@ define <16 x i64> @vp_ctlz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl
; RV32-LABEL: vp_ctlz_v16i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vnot.v v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v8, v24, 1, v0.t
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v24, v16, v24, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsub.vv v24, v24, v16, v0.t
-; RV32-NEXT: vand.vv v16, v24, v8, v0.t
+; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: vand.vv v8, v24, v16, v0.t
; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
+; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctlz_v16i64:
@@ -1772,8 +1772,8 @@ define <16 x i64> @vp_ctlz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl)
@@ -1887,160 +1887,301 @@ define <16 x i64> @vp_ctlz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v32i64:
; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 48
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 40
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: li a1, 16
+; RV32-NEXT: li a2, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV32-NEXT: vmv1r.v v24, v0
; RV32-NEXT: vslidedown.vi v7, v0, 2
-; RV32-NEXT: mv a2, a0
-; RV32-NEXT: bltu a0, a1, .LBB34_2
+; RV32-NEXT: mv a1, a0
+; RV32-NEXT: bltu a0, a2, .LBB34_2
; RV32-NEXT: # %bb.1:
-; RV32-NEXT: li a2, 16
+; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB34_2:
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV32-NEXT: li a1, 32
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 26
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: sub sp, sp, a2
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
+; RV32-NEXT: vmv1r.v v0, v24
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: li a2, 32
+; RV32-NEXT: addi a3, a0, -16
+; RV32-NEXT: sltu a0, a0, a3
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: and a0, a0, a3
; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: addi a3, a3, 1365
-; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v6, v0
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v16, 2, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v16, 8, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v16, 16, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: slli a5, a4, 3
+; RV32-NEXT: add a4, a5, a4
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: li a5, 25
+; RV32-NEXT: mul a4, a4, a5
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs1r.v v6, (a4) # vscale x 8-byte Folded Spill
; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a3
+; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 5
+; RV32-NEXT: slli a4, a3, 4
+; RV32-NEXT: add a3, a4, a3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 25
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: addi a3, a3, 819
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
+; RV32-NEXT: li a4, 25
+; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV32-NEXT: lui a3, 61681
-; RV32-NEXT: addi a3, a3, -241
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 24
+; RV32-NEXT: li a4, 25
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a3, 4112
-; RV32-NEXT: addi a3, a3, 257
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
-; RV32-NEXT: addi a3, sp, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
+; RV32-NEXT: slli a4, a3, 4
+; RV32-NEXT: add a3, a4, a3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: addi a3, a0, -16
-; RV32-NEXT: sltu a0, a0, a3
-; RV32-NEXT: addi a0, a0, -1
-; RV32-NEXT: and a0, a0, a3
-; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 40
+; RV32-NEXT: li a4, 25
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a4, a3, 3
+; RV32-NEXT: add a3, a4, a3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t
-; RV32-NEXT: vor.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 5
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v24, v0.t
+; RV32-NEXT: vsrl.vx v24, v16, a2, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: lui a2, 209715
+; RV32-NEXT: addi a2, a2, 819
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v8, v16, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 3
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs1r.v v7, (a2) # vscale x 8-byte Folded Spill
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 4
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
+; RV32-NEXT: vmv1r.v v7, v0
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 3
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v24, 4, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 3
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vadd.vv v24, v8, v24, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 4
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a2, 61681
+; RV32-NEXT: lui a3, 4112
+; RV32-NEXT: addi a2, a2, -241
+; RV32-NEXT: addi a3, a3, 257
+; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a4, 25
+; RV32-NEXT: mul a2, a2, a4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a4, a2, 4
+; RV32-NEXT: add a2, a4, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a3
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
+; RV32-NEXT: li a2, 56
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 25
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 48
+; RV32-NEXT: li a1, 26
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -2060,74 +2201,119 @@ define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV64-NEXT: .LBB34_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: li a1, 32
+; RV64-NEXT: li a6, 32
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
; RV64-NEXT: lui a5, 4112
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: addi a3, a3, 819
-; RV64-NEXT: addi a6, a4, -241
-; RV64-NEXT: addi a7, a5, 257
+; RV64-NEXT: addi a7, a2, 1365
+; RV64-NEXT: addi a2, a3, 819
+; RV64-NEXT: addi a3, a4, -241
+; RV64-NEXT: addi a4, a5, 257
+; RV64-NEXT: slli a5, a7, 32
+; RV64-NEXT: add a7, a7, a5
; RV64-NEXT: slli a5, a2, 32
; RV64-NEXT: add a5, a2, a5
-; RV64-NEXT: slli a4, a3, 32
-; RV64-NEXT: add a4, a3, a4
-; RV64-NEXT: slli a2, a6, 32
-; RV64-NEXT: add a2, a6, a2
-; RV64-NEXT: slli a3, a7, 32
-; RV64-NEXT: add a3, a7, a3
-; RV64-NEXT: addi a6, a0, -16
-; RV64-NEXT: sltu a0, a0, a6
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a4, 32
+; RV64-NEXT: add a3, a4, a3
+; RV64-NEXT: addi a4, a0, -16
+; RV64-NEXT: sltu a0, a0, a4
; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a6, a0, a6
+; RV64-NEXT: and a4, a0, a4
; RV64-NEXT: li a0, 56
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 2, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 8, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 16, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vsrl.vx v24, v8, a1, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a5, v0.t
-; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a4, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a4, v0.t
-; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
+; RV64-NEXT: vmv1r.v v6, v0
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 8, v0.t
+; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 2, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 16, v0.t
+; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v24, v8, a6, v0.t
+; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 8, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 16, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vsrl.vx v24, v16, a1, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a7, v0.t
+; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v24, v16, a6, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v8, a5, v0.t
+; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vnot.v v16, v16, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v8, v8, a5, v0.t
+; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a5, v0.t
+; RV64-NEXT: vand.vx v24, v24, a7, v0.t
; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vand.vx v24, v16, a4, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v16, a5, v0.t
; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a4, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v16, v16, a5, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
; RV64-NEXT: vand.vx v16, v16, a2, v0.t
@@ -3265,11 +3451,11 @@ define <2 x i64> @vp_ctlz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroe
; RV32-NEXT: vadd.vv v8, v8, v9, v0.t
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v9, a1
-; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v8, v8, v10, v0.t
; RV32-NEXT: vmul.vv v8, v8, v9, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctlz_zero_undef_v2i64:
@@ -3315,8 +3501,8 @@ define <2 x i64> @vp_ctlz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroe
; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 true, <2 x i1> %m, i32 %evl)
@@ -3431,29 +3617,29 @@ define <4 x i64> @vp_ctlz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroe
; RV32-LABEL: vp_ctlz_zero_undef_v4i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
+; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.x v10, a1
+; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
-; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t
+; RV32-NEXT: vor.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsrl.vi v10, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsrl.vi v10, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsrl.vi v10, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v10, v0.t
+; RV32-NEXT: vsrl.vx v10, v8, a1, v0.t
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vor.vv v8, v8, v12, v0.t
+; RV32-NEXT: vor.vv v8, v8, v10, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
-; RV32-NEXT: vand.vv v10, v12, v10, v0.t
+; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
+; RV32-NEXT: vand.vv v10, v10, v12, v0.t
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: lui a1, 61681
@@ -3473,11 +3659,11 @@ define <4 x i64> @vp_ctlz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroe
; RV32-NEXT: vadd.vv v8, v8, v10, v0.t
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v10, a1
-; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: vmul.vv v8, v8, v10, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctlz_zero_undef_v4i64:
@@ -3523,8 +3709,8 @@ define <4 x i64> @vp_ctlz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroe
; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 true, <4 x i1> %m, i32 %evl)
@@ -3639,53 +3825,53 @@ define <8 x i64> @vp_ctlz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroe
; RV32-LABEL: vp_ctlz_zero_undef_v8i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v12, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: vor.vv v8, v8, v12, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v12, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v12, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v12, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v12, v0.t
+; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vnot.v v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t
-; RV32-NEXT: vand.vv v12, v8, v12, v0.t
+; RV32-NEXT: vor.vv v8, v8, v12, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
+; RV32-NEXT: vand.vv v12, v12, v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsub.vv v12, v16, v12, v0.t
-; RV32-NEXT: vand.vv v16, v12, v8, v0.t
-; RV32-NEXT: vsrl.vi v12, v12, 2, v0.t
-; RV32-NEXT: vand.vv v8, v12, v8, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v12, v0.t
+; RV32-NEXT: vand.vv v12, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v12, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vadd.vv v8, v12, v8, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v12, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v16, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v12, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctlz_zero_undef_v8i64:
@@ -3731,8 +3917,8 @@ define <8 x i64> @vp_ctlz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroe
; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 true, <8 x i1> %m, i32 %evl)
@@ -3847,53 +4033,53 @@ define <15 x i64> @vp_ctlz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 z
; RV32-LABEL: vp_ctlz_zero_undef_v15i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vnot.v v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v8, v24, 1, v0.t
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v24, v16, v24, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsub.vv v24, v24, v16, v0.t
-; RV32-NEXT: vand.vv v16, v24, v8, v0.t
+; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: vand.vv v8, v24, v16, v0.t
; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
+; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctlz_zero_undef_v15i64:
@@ -3939,8 +4125,8 @@ define <15 x i64> @vp_ctlz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 z
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 true, <15 x i1> %m, i32 %evl)
@@ -4055,53 +4241,53 @@ define <16 x i64> @vp_ctlz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 z
; RV32-LABEL: vp_ctlz_zero_undef_v16i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vnot.v v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v8, v24, 1, v0.t
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v24, v16, v24, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsub.vv v24, v24, v16, v0.t
-; RV32-NEXT: vand.vv v16, v24, v8, v0.t
+; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: vand.vv v8, v24, v16, v0.t
; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
+; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctlz_zero_undef_v16i64:
@@ -4147,8 +4333,8 @@ define <16 x i64> @vp_ctlz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 z
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 true, <16 x i1> %m, i32 %evl)
@@ -4262,160 +4448,301 @@ define <16 x i64> @vp_ctlz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroex
define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v32i64:
; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 48
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 40
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: li a1, 16
+; RV32-NEXT: li a2, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV32-NEXT: vmv1r.v v24, v0
; RV32-NEXT: vslidedown.vi v7, v0, 2
-; RV32-NEXT: mv a2, a0
-; RV32-NEXT: bltu a0, a1, .LBB70_2
+; RV32-NEXT: mv a1, a0
+; RV32-NEXT: bltu a0, a2, .LBB70_2
; RV32-NEXT: # %bb.1:
-; RV32-NEXT: li a2, 16
+; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB70_2:
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV32-NEXT: li a1, 32
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 26
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: sub sp, sp, a2
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
+; RV32-NEXT: vmv1r.v v0, v24
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: li a2, 32
+; RV32-NEXT: addi a3, a0, -16
+; RV32-NEXT: sltu a0, a0, a3
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: and a0, a0, a3
; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: addi a3, a3, 1365
-; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v6, v0
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v16, 2, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v16, 8, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v16, 16, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: slli a5, a4, 3
+; RV32-NEXT: add a4, a5, a4
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: li a5, 25
+; RV32-NEXT: mul a4, a4, a5
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs1r.v v6, (a4) # vscale x 8-byte Folded Spill
; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a3
+; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 5
+; RV32-NEXT: slli a4, a3, 4
+; RV32-NEXT: add a3, a4, a3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 25
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: addi a3, a3, 819
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
+; RV32-NEXT: li a4, 25
+; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV32-NEXT: lui a3, 61681
-; RV32-NEXT: addi a3, a3, -241
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 24
+; RV32-NEXT: li a4, 25
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a3, 4112
-; RV32-NEXT: addi a3, a3, 257
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
-; RV32-NEXT: addi a3, sp, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
+; RV32-NEXT: slli a4, a3, 4
+; RV32-NEXT: add a3, a4, a3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: addi a3, a0, -16
-; RV32-NEXT: sltu a0, a0, a3
-; RV32-NEXT: addi a0, a0, -1
-; RV32-NEXT: and a0, a0, a3
-; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 40
+; RV32-NEXT: li a4, 25
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a4, a3, 3
+; RV32-NEXT: add a3, a4, a3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t
-; RV32-NEXT: vor.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 5
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v24, v0.t
+; RV32-NEXT: vsrl.vx v24, v16, a2, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: lui a2, 209715
+; RV32-NEXT: addi a2, a2, 819
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v8, v16, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 3
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs1r.v v7, (a2) # vscale x 8-byte Folded Spill
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 4
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
+; RV32-NEXT: vmv1r.v v7, v0
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 3
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v24, 4, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 3
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vadd.vv v24, v8, v24, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 4
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a2, 61681
+; RV32-NEXT: lui a3, 4112
+; RV32-NEXT: addi a2, a2, -241
+; RV32-NEXT: addi a3, a3, 257
+; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a4, 25
+; RV32-NEXT: mul a2, a2, a4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a4, a2, 4
+; RV32-NEXT: add a2, a4, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a3
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
+; RV32-NEXT: li a2, 56
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 25
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 48
+; RV32-NEXT: li a1, 26
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -4435,74 +4762,119 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV64-NEXT: .LBB70_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: li a1, 32
+; RV64-NEXT: li a6, 32
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
; RV64-NEXT: lui a5, 4112
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: addi a3, a3, 819
-; RV64-NEXT: addi a6, a4, -241
-; RV64-NEXT: addi a7, a5, 257
+; RV64-NEXT: addi a7, a2, 1365
+; RV64-NEXT: addi a2, a3, 819
+; RV64-NEXT: addi a3, a4, -241
+; RV64-NEXT: addi a4, a5, 257
+; RV64-NEXT: slli a5, a7, 32
+; RV64-NEXT: add a7, a7, a5
; RV64-NEXT: slli a5, a2, 32
; RV64-NEXT: add a5, a2, a5
-; RV64-NEXT: slli a4, a3, 32
-; RV64-NEXT: add a4, a3, a4
-; RV64-NEXT: slli a2, a6, 32
-; RV64-NEXT: add a2, a6, a2
-; RV64-NEXT: slli a3, a7, 32
-; RV64-NEXT: add a3, a7, a3
-; RV64-NEXT: addi a6, a0, -16
-; RV64-NEXT: sltu a0, a0, a6
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a4, 32
+; RV64-NEXT: add a3, a4, a3
+; RV64-NEXT: addi a4, a0, -16
+; RV64-NEXT: sltu a0, a0, a4
; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a6, a0, a6
+; RV64-NEXT: and a4, a0, a4
; RV64-NEXT: li a0, 56
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 2, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 8, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 16, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vsrl.vx v24, v8, a1, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a5, v0.t
-; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a4, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a4, v0.t
-; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
-; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
+; RV64-NEXT: vmv1r.v v6, v0
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 8, v0.t
+; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 2, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 16, v0.t
+; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v24, v8, a6, v0.t
+; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 8, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 16, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vsrl.vx v24, v16, a1, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a7, v0.t
+; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v24, v16, a6, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v8, a5, v0.t
+; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vnot.v v16, v16, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v8, v8, a5, v0.t
+; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a5, v0.t
+; RV64-NEXT: vand.vx v24, v24, a7, v0.t
; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vand.vx v24, v16, a4, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v16, a5, v0.t
; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a4, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v16, v16, a5, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
; RV64-NEXT: vand.vx v16, v16, a2, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
index f56438bf87e6a..ec6b0290a18ce 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
@@ -660,11 +660,11 @@ define <2 x i64> @vp_ctpop_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV32-NEXT: vadd.vv v8, v8, v9, v0.t
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v9, a1
-; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v8, v8, v10, v0.t
; RV32-NEXT: vmul.vv v8, v8, v9, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctpop_v2i64:
@@ -696,8 +696,8 @@ define <2 x i64> @vp_ctpop_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <2 x i64> @llvm.vp.ctpop.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl)
@@ -812,11 +812,11 @@ define <4 x i64> @vp_ctpop_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-NEXT: vadd.vv v8, v8, v10, v0.t
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v10, a1
-; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: vmul.vv v8, v8, v10, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctpop_v4i64:
@@ -848,8 +848,8 @@ define <4 x i64> @vp_ctpop_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <4 x i64> @llvm.vp.ctpop.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl)
@@ -944,31 +944,31 @@ define <8 x i64> @vp_ctpop_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vand.vv v16, v12, v16, v0.t
+; RV32-NEXT: vand.vv v12, v12, v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v12, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
-; RV32-NEXT: vand.vv v16, v8, v12, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v12, v0.t
+; RV32-NEXT: vand.vv v12, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v12, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vadd.vv v8, v12, v8, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v12, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v16, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v12, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctpop_v8i64:
@@ -1000,8 +1000,8 @@ define <8 x i64> @vp_ctpop_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <8 x i64> @llvm.vp.ctpop.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl)
@@ -1102,25 +1102,25 @@ define <15 x i64> @vp_ctpop_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %ev
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: vand.vv v8, v24, v16, v0.t
+; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
+; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vv v16, v24, v16, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctpop_v15i64:
@@ -1152,8 +1152,8 @@ define <15 x i64> @vp_ctpop_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %ev
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <15 x i64> @llvm.vp.ctpop.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl)
@@ -1254,25 +1254,25 @@ define <16 x i64> @vp_ctpop_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %ev
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV32-NEXT: vand.vv v24, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: vand.vv v8, v24, v16, v0.t
+; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
+; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vv v16, v24, v16, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_ctpop_v16i64:
@@ -1304,8 +1304,8 @@ define <16 x i64> @vp_ctpop_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %ev
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <16 x i64> @llvm.vp.ctpop.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl)
@@ -1394,130 +1394,122 @@ define <32 x i64> @vp_ctpop_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 48
+; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 40
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: li a2, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vslidedown.vi v7, v0, 2
; RV32-NEXT: mv a1, a0
; RV32-NEXT: bltu a0, a2, .LBB34_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB34_2:
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: lui a2, 349525
; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a2
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 5
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24, v0.t
; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a2
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v16, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a2, 61681
-; RV32-NEXT: addi a2, a2, -241
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a2, 4112
-; RV32-NEXT: addi a2, a2, 257
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v6, v0
+; RV32-NEXT: addi a2, a0, -16
+; RV32-NEXT: sltu a0, a0, a2
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: and a0, a0, a2
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v16, v16, v24, v0.t
+; RV32-NEXT: lui a2, 209715
+; RV32-NEXT: addi a2, a2, 819
+; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
+; RV32-NEXT: addi a3, sp, 16
+; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: vmv1r.v v0, v6
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: li a1, 56
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v24, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: addi a2, a0, -16
-; RV32-NEXT: sltu a0, a0, a2
-; RV32-NEXT: addi a0, a0, -1
-; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 40
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 5
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsub.vv v8, v16, v8, v0.t
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v16, v8, v24, v0.t
+; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a2, 61681
+; RV32-NEXT: addi a2, a2, -241
+; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: lui a2, 4112
+; RV32-NEXT: addi a2, a2, 257
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
+; RV32-NEXT: li a2, 56
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 48
+; RV32-NEXT: li a1, 24
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -1537,52 +1529,73 @@ define <32 x i64> @vp_ctpop_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; RV64-NEXT: .LBB34_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: lui a1, 349525
-; RV64-NEXT: lui a2, 209715
-; RV64-NEXT: lui a3, 61681
-; RV64-NEXT: lui a4, 4112
-; RV64-NEXT: addi a1, a1, 1365
-; RV64-NEXT: addi a2, a2, 819
-; RV64-NEXT: addi a3, a3, -241
-; RV64-NEXT: addi a4, a4, 257
-; RV64-NEXT: slli a5, a1, 32
-; RV64-NEXT: add a1, a1, a5
-; RV64-NEXT: slli a5, a2, 32
-; RV64-NEXT: add a2, a2, a5
-; RV64-NEXT: slli a5, a3, 32
-; RV64-NEXT: add a3, a3, a5
-; RV64-NEXT: slli a5, a4, 32
-; RV64-NEXT: add a4, a4, a5
-; RV64-NEXT: addi a5, a0, -16
-; RV64-NEXT: sltu a0, a0, a5
+; RV64-NEXT: lui a2, 349525
+; RV64-NEXT: lui a3, 209715
+; RV64-NEXT: lui a4, 61681
+; RV64-NEXT: lui a5, 4112
+; RV64-NEXT: addi a2, a2, 1365
+; RV64-NEXT: addi a3, a3, 819
+; RV64-NEXT: addi a4, a4, -241
+; RV64-NEXT: addi a5, a5, 257
+; RV64-NEXT: slli a6, a2, 32
+; RV64-NEXT: add a6, a2, a6
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: add a7, a3, a2
+; RV64-NEXT: slli a3, a4, 32
+; RV64-NEXT: add a3, a4, a3
+; RV64-NEXT: slli a2, a5, 32
+; RV64-NEXT: add a2, a5, a2
+; RV64-NEXT: addi a4, a0, -16
+; RV64-NEXT: sltu a0, a0, a4
; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a0, a0, a5
-; RV64-NEXT: li a5, 56
-; RV64-NEXT: vand.vx v24, v24, a1, v0.t
+; RV64-NEXT: and a4, a0, a4
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: vand.vx v24, v24, a6, v0.t
; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
-; RV64-NEXT: vsrl.vx v8, v8, a5, v0.t
+; RV64-NEXT: vmv1r.v v6, v0
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a6, v0.t
; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vand.vx v24, v16, a2, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v8, a7, v0.t
+; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV64-NEXT: vand.vx v8, v8, a7, v0.t
+; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v16, a7, v0.t
; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a2, v0.t
+; RV64-NEXT: vand.vx v16, v16, a7, v0.t
; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v8, v8, a3, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vmul.vx v8, v8, a2, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v16, a3, v0.t
-; RV64-NEXT: vmul.vx v16, v16, a4, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a5, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vmul.vx v16, v16, a2, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t
; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.ctpop.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
index 098384d200045..5ad84a7fe96c5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
@@ -9,8 +9,8 @@ define <2 x i8> @vp_cttz_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
@@ -57,8 +57,8 @@ define <4 x i8> @vp_cttz_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
@@ -105,8 +105,8 @@ define <8 x i8> @vp_cttz_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
@@ -153,8 +153,8 @@ define <16 x i8> @vp_cttz_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
@@ -201,10 +201,10 @@ define <2 x i16> @vp_cttz_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 3
@@ -263,10 +263,10 @@ define <4 x i16> @vp_cttz_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 3
@@ -325,10 +325,10 @@ define <8 x i16> @vp_cttz_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 3
@@ -387,10 +387,10 @@ define <16 x i16> @vp_cttz_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vadd.vi v10, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: lui a0, 3
@@ -449,10 +449,10 @@ define <2 x i32> @vp_cttz_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 209715
@@ -513,10 +513,10 @@ define <4 x i32> @vp_cttz_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 209715
@@ -577,10 +577,10 @@ define <8 x i32> @vp_cttz_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vadd.vi v10, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: lui a0, 209715
@@ -641,10 +641,10 @@ define <16 x i32> @vp_cttz_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vadd.vi v12, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: lui a0, 209715
@@ -705,15 +705,15 @@ define <2 x i64> @vp_cttz_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vadd.vi v9, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v10, a1
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vand.vv v8, v8, v9, v0.t
+; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
; RV32-NEXT: vand.vv v9, v9, v10, v0.t
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
@@ -735,11 +735,11 @@ define <2 x i64> @vp_cttz_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV32-NEXT: vadd.vv v8, v8, v9, v0.t
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v9, a1
-; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v8, v8, v10, v0.t
; RV32-NEXT: vmul.vv v8, v8, v9, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_cttz_v2i64:
@@ -774,8 +774,8 @@ define <2 x i64> @vp_cttz_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl)
@@ -869,15 +869,15 @@ define <4 x i64> @vp_cttz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vadd.vi v10, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vand.vv v8, v8, v10, v0.t
+; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV32-NEXT: vand.vv v10, v10, v12, v0.t
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
@@ -899,11 +899,11 @@ define <4 x i64> @vp_cttz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV32-NEXT: vadd.vv v8, v8, v10, v0.t
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v10, a1
-; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: vmul.vv v8, v8, v10, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_cttz_v4i64:
@@ -938,8 +938,8 @@ define <4 x i64> @vp_cttz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl)
@@ -1033,41 +1033,41 @@ define <8 x i64> @vp_cttz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vadd.vi v12, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vand.vv v12, v8, v12, v0.t
-; RV32-NEXT: vsrl.vi v8, v12, 1, v0.t
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
+; RV32-NEXT: vand.vv v12, v12, v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsub.vv v12, v12, v16, v0.t
-; RV32-NEXT: vand.vv v16, v12, v8, v0.t
-; RV32-NEXT: vsrl.vi v12, v12, 2, v0.t
-; RV32-NEXT: vand.vv v8, v12, v8, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v12, v0.t
+; RV32-NEXT: vand.vv v12, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v12, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vadd.vv v8, v12, v8, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v12, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v16, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v12, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_cttz_v8i64:
@@ -1102,8 +1102,8 @@ define <8 x i64> @vp_cttz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) {
; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl)
@@ -1197,41 +1197,41 @@ define <15 x i64> @vp_cttz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vadd.vi v16, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t
-; RV32-NEXT: vand.vv v24, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v24, v16, v24, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsub.vv v24, v16, v24, v0.t
-; RV32-NEXT: vand.vv v16, v24, v8, v0.t
+; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: vand.vv v8, v24, v16, v0.t
; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
+; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_cttz_v15i64:
@@ -1266,8 +1266,8 @@ define <15 x i64> @vp_cttz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl)
@@ -1361,41 +1361,41 @@ define <16 x i64> @vp_cttz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vadd.vi v16, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t
-; RV32-NEXT: vand.vv v24, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v24, v16, v24, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsub.vv v24, v16, v24, v0.t
-; RV32-NEXT: vand.vv v16, v24, v8, v0.t
+; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: vand.vv v8, v24, v16, v0.t
; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
+; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_cttz_v16i64:
@@ -1430,8 +1430,8 @@ define <16 x i64> @vp_cttz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl)
@@ -1526,136 +1526,253 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 48
+; RV32-NEXT: li a2, 26
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 40
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: li a2, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v7, v0, 2
+; RV32-NEXT: vslidedown.vi v24, v0, 2
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
; RV32-NEXT: mv a1, a0
; RV32-NEXT: bltu a0, a2, .LBB34_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB34_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vadd.vi v16, v8, -1, v0.t
-; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: vadd.vi v24, v8, -1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 25
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a2
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 5
+; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
+; RV32-NEXT: vand.vv v24, v16, v24, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: addi a2, a0, -16
+; RV32-NEXT: sltu a0, a0, a2
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: and a0, a0, a2
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vadd.vi v8, v16, -1, v0.t
+; RV32-NEXT: vnot.v v16, v16, v0.t
+; RV32-NEXT: vand.vv v8, v16, v8, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: lui a2, 209715
; RV32-NEXT: addi a2, a2, 819
; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a2
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vand.vv v8, v24, v16, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV32-NEXT: lui a2, 61681
-; RV32-NEXT: addi a2, a2, -241
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: li a3, 24
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a2, 4112
-; RV32-NEXT: addi a2, a2, 257
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: li a1, 56
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: addi a2, a0, -16
-; RV32-NEXT: sltu a0, a0, a2
-; RV32-NEXT: addi a0, a0, -1
-; RV32-NEXT: and a0, a0, a2
-; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v24, 4, v0.t
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vadd.vv v24, v8, v24, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v7, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 40
+; RV32-NEXT: li a3, 24
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vi v24, v8, -1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 5
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a2, 61681
+; RV32-NEXT: addi a2, a2, -241
; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vmv1r.v v6, v0
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: lui a2, 4112
+; RV32-NEXT: addi a2, a2, 257
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
+; RV32-NEXT: li a2, 56
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 48
+; RV32-NEXT: li a1, 26
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -1675,57 +1792,78 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV64-NEXT: .LBB34_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vadd.vi v24, v8, -1, v0.t
-; RV64-NEXT: lui a1, 349525
-; RV64-NEXT: lui a2, 209715
-; RV64-NEXT: lui a3, 61681
-; RV64-NEXT: lui a4, 4112
-; RV64-NEXT: addi a1, a1, 1365
-; RV64-NEXT: addi a2, a2, 819
-; RV64-NEXT: addi a5, a3, -241
-; RV64-NEXT: addi a4, a4, 257
-; RV64-NEXT: slli a3, a1, 32
-; RV64-NEXT: add a6, a1, a3
-; RV64-NEXT: slli a3, a2, 32
-; RV64-NEXT: add a3, a2, a3
-; RV64-NEXT: slli a1, a5, 32
-; RV64-NEXT: add a1, a5, a1
+; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: lui a2, 349525
+; RV64-NEXT: lui a3, 209715
+; RV64-NEXT: lui a4, 61681
+; RV64-NEXT: lui a5, 4112
+; RV64-NEXT: addi a2, a2, 1365
+; RV64-NEXT: addi a3, a3, 819
+; RV64-NEXT: addi a4, a4, -241
+; RV64-NEXT: addi a5, a5, 257
+; RV64-NEXT: slli a6, a2, 32
+; RV64-NEXT: add a6, a2, a6
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: add a7, a3, a2
; RV64-NEXT: slli a2, a4, 32
; RV64-NEXT: add a2, a4, a2
+; RV64-NEXT: slli a3, a5, 32
+; RV64-NEXT: add a3, a5, a3
; RV64-NEXT: addi a4, a0, -16
; RV64-NEXT: sltu a0, a0, a4
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: and a4, a0, a4
; RV64-NEXT: li a0, 56
-; RV64-NEXT: vnot.v v8, v8, v0.t
; RV64-NEXT: vand.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
; RV64-NEXT: vand.vx v24, v24, a6, v0.t
-; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v8, v8, a1, v0.t
-; RV64-NEXT: vmul.vx v8, v8, a2, v0.t
-; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v6, v0
; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vadd.vi v24, v16, -1, v0.t
+; RV64-NEXT: vadd.vi v8, v16, -1, v0.t
; RV64-NEXT: vnot.v v16, v16, v0.t
-; RV64-NEXT: vand.vv v16, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
+; RV64-NEXT: vand.vv v8, v16, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v16, v24, a7, v0.t
+; RV64-NEXT: vsrl.vi v24, v24, 2, v0.t
+; RV64-NEXT: vand.vx v24, v24, a7, v0.t
+; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
; RV64-NEXT: vand.vx v24, v24, a6, v0.t
-; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vand.vx v24, v16, a3, v0.t
-; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a3, v0.t
-; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vmul.vx v16, v16, a2, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v8, a7, v0.t
+; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV64-NEXT: vand.vx v8, v8, a7, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v16, v16, a2, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vadd.vv v24, v24, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vmul.vx v8, v16, a3, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v16, v24, 4, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vand.vx v16, v16, a2, v0.t
+; RV64-NEXT: vmul.vx v16, v16, a3, v0.t
; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t
; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl)
@@ -1914,8 +2052,8 @@ define <2 x i8> @vp_cttz_zero_undef_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
@@ -1962,8 +2100,8 @@ define <4 x i8> @vp_cttz_zero_undef_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
@@ -2010,8 +2148,8 @@ define <8 x i8> @vp_cttz_zero_undef_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
@@ -2058,8 +2196,8 @@ define <16 x i8> @vp_cttz_zero_undef_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zero
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: li a0, 85
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
@@ -2106,10 +2244,10 @@ define <2 x i16> @vp_cttz_zero_undef_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroe
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 3
@@ -2168,10 +2306,10 @@ define <4 x i16> @vp_cttz_zero_undef_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroe
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 3
@@ -2230,10 +2368,10 @@ define <8 x i16> @vp_cttz_zero_undef_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroe
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 3
@@ -2292,10 +2430,10 @@ define <16 x i16> @vp_cttz_zero_undef_v16i16(<16 x i16> %va, <16 x i1> %m, i32 z
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vadd.vi v10, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: lui a0, 3
@@ -2354,10 +2492,10 @@ define <2 x i32> @vp_cttz_zero_undef_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroe
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 209715
@@ -2418,10 +2556,10 @@ define <4 x i32> @vp_cttz_zero_undef_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroe
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vadd.vi v9, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vand.vv v8, v8, v9, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v9, v8, 1, v0.t
; CHECK-NEXT: vand.vx v9, v9, a0, v0.t
; CHECK-NEXT: lui a0, 209715
@@ -2482,10 +2620,10 @@ define <8 x i32> @vp_cttz_zero_undef_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroe
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; CHECK-NEXT: vadd.vi v10, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vand.vv v8, v8, v10, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v10, v8, 1, v0.t
; CHECK-NEXT: vand.vx v10, v10, a0, v0.t
; CHECK-NEXT: lui a0, 209715
@@ -2546,10 +2684,10 @@ define <16 x i32> @vp_cttz_zero_undef_v16i32(<16 x i32> %va, <16 x i1> %m, i32 z
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vadd.vi v12, v8, -1, v0.t
-; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: lui a0, 349525
; CHECK-NEXT: vand.vv v8, v8, v12, v0.t
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
; CHECK-NEXT: lui a0, 209715
@@ -2610,15 +2748,15 @@ define <2 x i64> @vp_cttz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroe
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vadd.vi v9, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v10, a1
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vand.vv v8, v8, v9, v0.t
+; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vsrl.vi v9, v8, 1, v0.t
; RV32-NEXT: vand.vv v9, v9, v10, v0.t
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
@@ -2640,11 +2778,11 @@ define <2 x i64> @vp_cttz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroe
; RV32-NEXT: vadd.vv v8, v8, v9, v0.t
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v9, a1
-; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v8, v8, v10, v0.t
; RV32-NEXT: vmul.vv v8, v8, v9, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_cttz_zero_undef_v2i64:
@@ -2679,8 +2817,8 @@ define <2 x i64> @vp_cttz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroe
; RV64-NEXT: vsrl.vi v9, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v9, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, i1 true, <2 x i1> %m, i32 %evl)
@@ -2774,15 +2912,15 @@ define <4 x i64> @vp_cttz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroe
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vadd.vi v10, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vand.vv v8, v8, v10, v0.t
+; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vsrl.vi v10, v8, 1, v0.t
; RV32-NEXT: vand.vv v10, v10, v12, v0.t
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
@@ -2804,11 +2942,11 @@ define <4 x i64> @vp_cttz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroe
; RV32-NEXT: vadd.vv v8, v8, v10, v0.t
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v10, a1
-; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: vmul.vv v8, v8, v10, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_cttz_zero_undef_v4i64:
@@ -2843,8 +2981,8 @@ define <4 x i64> @vp_cttz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroe
; RV64-NEXT: vsrl.vi v10, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v10, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, i1 true, <4 x i1> %m, i32 %evl)
@@ -2938,41 +3076,41 @@ define <8 x i64> @vp_cttz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroe
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vadd.vi v12, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vand.vv v12, v8, v12, v0.t
-; RV32-NEXT: vsrl.vi v8, v12, 1, v0.t
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 1, v0.t
+; RV32-NEXT: vand.vv v12, v12, v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vsub.vv v12, v12, v16, v0.t
-; RV32-NEXT: vand.vv v16, v12, v8, v0.t
-; RV32-NEXT: vsrl.vi v12, v12, 2, v0.t
-; RV32-NEXT: vand.vv v8, v12, v8, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v12, v0.t
+; RV32-NEXT: vand.vv v12, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v12, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vadd.vv v8, v12, v8, v0.t
+; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v12, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmv.v.x v16, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; RV32-NEXT: vand.vv v8, v8, v12, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v12, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_cttz_zero_undef_v8i64:
@@ -3007,8 +3145,8 @@ define <8 x i64> @vp_cttz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroe
; RV64-NEXT: vsrl.vi v12, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v12, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, i1 true, <8 x i1> %m, i32 %evl)
@@ -3102,41 +3240,41 @@ define <15 x i64> @vp_cttz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 z
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vadd.vi v16, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t
-; RV32-NEXT: vand.vv v24, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v24, v16, v24, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsub.vv v24, v16, v24, v0.t
-; RV32-NEXT: vand.vv v16, v24, v8, v0.t
+; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: vand.vv v8, v24, v16, v0.t
; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
+; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_cttz_zero_undef_v15i64:
@@ -3171,8 +3309,8 @@ define <15 x i64> @vp_cttz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 z
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, i1 true, <15 x i1> %m, i32 %evl)
@@ -3266,41 +3404,41 @@ define <16 x i64> @vp_cttz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 z
; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vadd.vi v16, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 209715
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t
-; RV32-NEXT: vand.vv v24, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v24, v16, v24, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsub.vv v24, v16, v24, v0.t
-; RV32-NEXT: vand.vv v16, v24, v8, v0.t
+; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: vand.vv v8, v24, v16, v0.t
; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
-; RV32-NEXT: vand.vv v24, v24, v8, v0.t
+; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: li a1, 56
+; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: vmul.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: li a0, 56
+; RV32-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: vp_cttz_zero_undef_v16i64:
@@ -3335,8 +3473,8 @@ define <16 x i64> @vp_cttz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 z
; RV64-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v16, v0.t
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: li a0, 56
; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
; RV64-NEXT: ret
%v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, i1 true, <16 x i1> %m, i32 %evl)
@@ -3431,136 +3569,253 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 48
+; RV32-NEXT: li a2, 26
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 40
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: li a2, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v7, v0, 2
+; RV32-NEXT: vslidedown.vi v24, v0, 2
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
; RV32-NEXT: mv a1, a0
; RV32-NEXT: bltu a0, a2, .LBB70_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB70_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vadd.vi v16, v8, -1, v0.t
-; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: vadd.vi v24, v8, -1, v0.t
; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 25
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a2
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 5
+; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
+; RV32-NEXT: vand.vv v24, v16, v24, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: addi a2, a0, -16
+; RV32-NEXT: sltu a0, a0, a2
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: and a0, a0, a2
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vadd.vi v8, v16, -1, v0.t
+; RV32-NEXT: vnot.v v16, v16, v0.t
+; RV32-NEXT: vand.vv v8, v16, v8, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: lui a2, 209715
; RV32-NEXT: addi a2, a2, 819
; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a2
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vand.vv v8, v24, v16, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV32-NEXT: lui a2, 61681
-; RV32-NEXT: addi a2, a2, -241
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: li a3, 24
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a2, 4112
-; RV32-NEXT: addi a2, a2, 257
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: li a1, 56
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: addi a2, a0, -16
-; RV32-NEXT: sltu a0, a0, a2
-; RV32-NEXT: addi a0, a0, -1
-; RV32-NEXT: and a0, a0, a2
-; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v24, 4, v0.t
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vadd.vv v24, v8, v24, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 40
+; RV32-NEXT: li a3, 25
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v7, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vi v24, v8, -1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 5
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a2, 61681
+; RV32-NEXT: addi a2, a2, -241
; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmv1r.v v6, v0
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: lui a2, 4112
+; RV32-NEXT: addi a2, a2, 257
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
+; RV32-NEXT: li a2, 56
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 48
+; RV32-NEXT: li a1, 26
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -3580,57 +3835,78 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV64-NEXT: .LBB70_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vadd.vi v24, v8, -1, v0.t
-; RV64-NEXT: lui a1, 349525
-; RV64-NEXT: lui a2, 209715
-; RV64-NEXT: lui a3, 61681
-; RV64-NEXT: lui a4, 4112
-; RV64-NEXT: addi a1, a1, 1365
-; RV64-NEXT: addi a2, a2, 819
-; RV64-NEXT: addi a5, a3, -241
-; RV64-NEXT: addi a4, a4, 257
-; RV64-NEXT: slli a3, a1, 32
-; RV64-NEXT: add a6, a1, a3
-; RV64-NEXT: slli a3, a2, 32
-; RV64-NEXT: add a3, a2, a3
-; RV64-NEXT: slli a1, a5, 32
-; RV64-NEXT: add a1, a5, a1
+; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: lui a2, 349525
+; RV64-NEXT: lui a3, 209715
+; RV64-NEXT: lui a4, 61681
+; RV64-NEXT: lui a5, 4112
+; RV64-NEXT: addi a2, a2, 1365
+; RV64-NEXT: addi a3, a3, 819
+; RV64-NEXT: addi a4, a4, -241
+; RV64-NEXT: addi a5, a5, 257
+; RV64-NEXT: slli a6, a2, 32
+; RV64-NEXT: add a6, a2, a6
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: add a7, a3, a2
; RV64-NEXT: slli a2, a4, 32
; RV64-NEXT: add a2, a4, a2
+; RV64-NEXT: slli a3, a5, 32
+; RV64-NEXT: add a3, a5, a3
; RV64-NEXT: addi a4, a0, -16
; RV64-NEXT: sltu a0, a0, a4
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: and a4, a0, a4
; RV64-NEXT: li a0, 56
-; RV64-NEXT: vnot.v v8, v8, v0.t
; RV64-NEXT: vand.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
; RV64-NEXT: vand.vx v24, v24, a6, v0.t
-; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v8, v8, a1, v0.t
-; RV64-NEXT: vmul.vx v8, v8, a2, v0.t
-; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
+; RV64-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v6, v0
; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vadd.vi v24, v16, -1, v0.t
+; RV64-NEXT: vadd.vi v8, v16, -1, v0.t
; RV64-NEXT: vnot.v v16, v16, v0.t
-; RV64-NEXT: vand.vv v16, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
+; RV64-NEXT: vand.vv v8, v16, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v16, v24, a7, v0.t
+; RV64-NEXT: vsrl.vi v24, v24, 2, v0.t
+; RV64-NEXT: vand.vx v24, v24, a7, v0.t
+; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
; RV64-NEXT: vand.vx v24, v24, a6, v0.t
-; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vand.vx v24, v16, a3, v0.t
-; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a3, v0.t
-; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a1, v0.t
-; RV64-NEXT: vmul.vx v16, v16, a2, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v8, a7, v0.t
+; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV64-NEXT: vand.vx v8, v8, a7, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v16, v16, a2, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vadd.vv v24, v24, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vmul.vx v8, v16, a3, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v16, v24, 4, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vand.vx v16, v16, a2, v0.t
+; RV64-NEXT: vmul.vx v16, v16, a3, v0.t
; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t
; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
index ad51cab1ba8d2..54fa8dd977714 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
@@ -44,8 +44,8 @@ define void @cttz_v16i8(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vnsrl.wi v12, v8, 23
; RVF-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; RVF-NEXT: vnsrl.wi v8, v12, 0
-; RVF-NEXT: vmseq.vi v0, v14, 0
; RVF-NEXT: vsub.vx v8, v8, a1
+; RVF-NEXT: vmseq.vi v0, v14, 0
; RVF-NEXT: vmerge.vim v8, v8, 8, v0
; RVF-NEXT: vse8.v v8, (a0)
; RVF-NEXT: ret
@@ -63,8 +63,8 @@ define void @cttz_v16i8(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vnsrl.wi v12, v8, 23
; RVD-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; RVD-NEXT: vnsrl.wi v8, v12, 0
-; RVD-NEXT: vmseq.vi v0, v14, 0
; RVD-NEXT: vsub.vx v8, v8, a1
+; RVD-NEXT: vmseq.vi v0, v14, 0
; RVD-NEXT: vmerge.vim v8, v8, 8, v0
; RVD-NEXT: vse8.v v8, (a0)
; RVD-NEXT: ret
@@ -415,8 +415,8 @@ define void @cttz_v32i8(ptr %x, ptr %y) nounwind {
; RVF-NEXT: vnsrl.wi v16, v8, 23
; RVF-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; RVF-NEXT: vnsrl.wi v8, v16, 0
-; RVF-NEXT: vmseq.vi v0, v20, 0
; RVF-NEXT: vsub.vx v8, v8, a1
+; RVF-NEXT: vmseq.vi v0, v20, 0
; RVF-NEXT: vmerge.vim v8, v8, 8, v0
; RVF-NEXT: vse8.v v8, (a0)
; RVF-NEXT: ret
@@ -435,8 +435,8 @@ define void @cttz_v32i8(ptr %x, ptr %y) nounwind {
; RVD-NEXT: vnsrl.wi v16, v8, 23
; RVD-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; RVD-NEXT: vnsrl.wi v8, v16, 0
-; RVD-NEXT: vmseq.vi v0, v20, 0
; RVD-NEXT: vsub.vx v8, v8, a1
+; RVD-NEXT: vmseq.vi v0, v20, 0
; RVD-NEXT: vmerge.vim v8, v8, 8, v0
; RVD-NEXT: vse8.v v8, (a0)
; RVD-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
index bb2b57fbcc3b7..54489765cff1a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
@@ -308,9 +308,9 @@ define void @truncstore_v2i8_v2i1(<2 x i8> %x, ptr %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
index fb070b24a4f34..f37a3cf5e6bb2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
@@ -10,9 +10,9 @@ define i1 @extractelt_v1i1(ptr %x, i64 %idx) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
+; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vmseq.vi v0, v8, 0
-; CHECK-NEXT: vmv.s.x v8, zero
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@@ -324,23 +324,24 @@ define i1 @extractelt_v256i1(ptr %x, i64 %idx) nounwind {
; RV32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
; RV32-NEXT: addi s0, sp, 384
; RV32-NEXT: andi sp, sp, -128
+; RV32-NEXT: zext.b a1, a1
; RV32-NEXT: li a2, 128
+; RV32-NEXT: addi a3, a0, 128
; RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; RV32-NEXT: vle8.v v16, (a3)
+; RV32-NEXT: mv a2, sp
; RV32-NEXT: vle8.v v8, (a0)
-; RV32-NEXT: addi a0, a0, 128
-; RV32-NEXT: vle8.v v16, (a0)
+; RV32-NEXT: addi a0, sp, 128
+; RV32-NEXT: add a1, a2, a1
+; RV32-NEXT: vmseq.vi v24, v16, 0
+; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: vmseq.vi v0, v8, 0
-; RV32-NEXT: vmv.v.i v8, 0
-; RV32-NEXT: vmerge.vim v24, v8, 1, v0
-; RV32-NEXT: vmseq.vi v0, v16, 0
-; RV32-NEXT: zext.b a0, a1
-; RV32-NEXT: mv a1, sp
-; RV32-NEXT: add a0, a1, a0
-; RV32-NEXT: vse8.v v24, (a1)
-; RV32-NEXT: vmerge.vim v8, v8, 1, v0
-; RV32-NEXT: addi a1, sp, 128
-; RV32-NEXT: vse8.v v8, (a1)
-; RV32-NEXT: lbu a0, 0(a0)
+; RV32-NEXT: vmerge.vim v8, v16, 1, v0
+; RV32-NEXT: vmv1r.v v0, v24
+; RV32-NEXT: vmerge.vim v16, v16, 1, v0
+; RV32-NEXT: vse8.v v8, (a2)
+; RV32-NEXT: vse8.v v16, (a0)
+; RV32-NEXT: lbu a0, 0(a1)
; RV32-NEXT: addi sp, s0, -384
; RV32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
@@ -354,23 +355,24 @@ define i1 @extractelt_v256i1(ptr %x, i64 %idx) nounwind {
; RV64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
; RV64-NEXT: addi s0, sp, 384
; RV64-NEXT: andi sp, sp, -128
+; RV64-NEXT: zext.b a1, a1
; RV64-NEXT: li a2, 128
+; RV64-NEXT: addi a3, a0, 128
; RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; RV64-NEXT: vle8.v v16, (a3)
+; RV64-NEXT: mv a2, sp
; RV64-NEXT: vle8.v v8, (a0)
-; RV64-NEXT: addi a0, a0, 128
-; RV64-NEXT: vle8.v v16, (a0)
+; RV64-NEXT: addi a0, sp, 128
+; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: vmseq.vi v24, v16, 0
+; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: vmseq.vi v0, v8, 0
-; RV64-NEXT: vmv.v.i v8, 0
-; RV64-NEXT: vmerge.vim v24, v8, 1, v0
-; RV64-NEXT: vmseq.vi v0, v16, 0
-; RV64-NEXT: zext.b a0, a1
-; RV64-NEXT: mv a1, sp
-; RV64-NEXT: add a0, a1, a0
-; RV64-NEXT: vse8.v v24, (a1)
-; RV64-NEXT: vmerge.vim v8, v8, 1, v0
-; RV64-NEXT: addi a1, sp, 128
-; RV64-NEXT: vse8.v v8, (a1)
-; RV64-NEXT: lbu a0, 0(a0)
+; RV64-NEXT: vmerge.vim v8, v16, 1, v0
+; RV64-NEXT: vmv1r.v v0, v24
+; RV64-NEXT: vmerge.vim v16, v16, 1, v0
+; RV64-NEXT: vse8.v v8, (a2)
+; RV64-NEXT: vse8.v v16, (a0)
+; RV64-NEXT: lbu a0, 0(a1)
; RV64-NEXT: addi sp, s0, -384
; RV64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
@@ -384,23 +386,24 @@ define i1 @extractelt_v256i1(ptr %x, i64 %idx) nounwind {
; RV32ZBS-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
; RV32ZBS-NEXT: addi s0, sp, 384
; RV32ZBS-NEXT: andi sp, sp, -128
+; RV32ZBS-NEXT: zext.b a1, a1
; RV32ZBS-NEXT: li a2, 128
+; RV32ZBS-NEXT: addi a3, a0, 128
; RV32ZBS-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; RV32ZBS-NEXT: vle8.v v16, (a3)
+; RV32ZBS-NEXT: mv a2, sp
; RV32ZBS-NEXT: vle8.v v8, (a0)
-; RV32ZBS-NEXT: addi a0, a0, 128
-; RV32ZBS-NEXT: vle8.v v16, (a0)
+; RV32ZBS-NEXT: addi a0, sp, 128
+; RV32ZBS-NEXT: add a1, a2, a1
+; RV32ZBS-NEXT: vmseq.vi v24, v16, 0
+; RV32ZBS-NEXT: vmv.v.i v16, 0
; RV32ZBS-NEXT: vmseq.vi v0, v8, 0
-; RV32ZBS-NEXT: vmv.v.i v8, 0
-; RV32ZBS-NEXT: vmerge.vim v24, v8, 1, v0
-; RV32ZBS-NEXT: vmseq.vi v0, v16, 0
-; RV32ZBS-NEXT: zext.b a0, a1
-; RV32ZBS-NEXT: mv a1, sp
-; RV32ZBS-NEXT: add a0, a1, a0
-; RV32ZBS-NEXT: vse8.v v24, (a1)
-; RV32ZBS-NEXT: vmerge.vim v8, v8, 1, v0
-; RV32ZBS-NEXT: addi a1, sp, 128
-; RV32ZBS-NEXT: vse8.v v8, (a1)
-; RV32ZBS-NEXT: lbu a0, 0(a0)
+; RV32ZBS-NEXT: vmerge.vim v8, v16, 1, v0
+; RV32ZBS-NEXT: vmv1r.v v0, v24
+; RV32ZBS-NEXT: vmerge.vim v16, v16, 1, v0
+; RV32ZBS-NEXT: vse8.v v8, (a2)
+; RV32ZBS-NEXT: vse8.v v16, (a0)
+; RV32ZBS-NEXT: lbu a0, 0(a1)
; RV32ZBS-NEXT: addi sp, s0, -384
; RV32ZBS-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
; RV32ZBS-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
@@ -414,23 +417,24 @@ define i1 @extractelt_v256i1(ptr %x, i64 %idx) nounwind {
; RV64ZBS-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
; RV64ZBS-NEXT: addi s0, sp, 384
; RV64ZBS-NEXT: andi sp, sp, -128
+; RV64ZBS-NEXT: zext.b a1, a1
; RV64ZBS-NEXT: li a2, 128
+; RV64ZBS-NEXT: addi a3, a0, 128
; RV64ZBS-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; RV64ZBS-NEXT: vle8.v v16, (a3)
+; RV64ZBS-NEXT: mv a2, sp
; RV64ZBS-NEXT: vle8.v v8, (a0)
-; RV64ZBS-NEXT: addi a0, a0, 128
-; RV64ZBS-NEXT: vle8.v v16, (a0)
+; RV64ZBS-NEXT: addi a0, sp, 128
+; RV64ZBS-NEXT: add a1, a2, a1
+; RV64ZBS-NEXT: vmseq.vi v24, v16, 0
+; RV64ZBS-NEXT: vmv.v.i v16, 0
; RV64ZBS-NEXT: vmseq.vi v0, v8, 0
-; RV64ZBS-NEXT: vmv.v.i v8, 0
-; RV64ZBS-NEXT: vmerge.vim v24, v8, 1, v0
-; RV64ZBS-NEXT: vmseq.vi v0, v16, 0
-; RV64ZBS-NEXT: zext.b a0, a1
-; RV64ZBS-NEXT: mv a1, sp
-; RV64ZBS-NEXT: add a0, a1, a0
-; RV64ZBS-NEXT: vse8.v v24, (a1)
-; RV64ZBS-NEXT: vmerge.vim v8, v8, 1, v0
-; RV64ZBS-NEXT: addi a1, sp, 128
-; RV64ZBS-NEXT: vse8.v v8, (a1)
-; RV64ZBS-NEXT: lbu a0, 0(a0)
+; RV64ZBS-NEXT: vmerge.vim v8, v16, 1, v0
+; RV64ZBS-NEXT: vmv1r.v v0, v24
+; RV64ZBS-NEXT: vmerge.vim v16, v16, 1, v0
+; RV64ZBS-NEXT: vse8.v v8, (a2)
+; RV64ZBS-NEXT: vse8.v v16, (a0)
+; RV64ZBS-NEXT: lbu a0, 0(a1)
; RV64ZBS-NEXT: addi sp, s0, -384
; RV64ZBS-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; RV64ZBS-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
index 3263539d5c20d..674908c463bfa 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
@@ -473,12 +473,13 @@ define void @extract_v2i1_v64i1_2(ptr %x, ptr %y) {
; VLA-NEXT: vlm.v v0, (a0)
; VLA-NEXT: vmv.v.i v8, 0
; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLA-NEXT: vmv.v.i v9, 0
; VLA-NEXT: vsetivli zero, 2, e8, m1, ta, ma
; VLA-NEXT: vslidedown.vi v8, v8, 2
; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; VLA-NEXT: vmsne.vi v0, v8, 0
-; VLA-NEXT: vmv.v.i v8, 0
-; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vmerge.vim v8, v9, 1, v0
; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; VLA-NEXT: vmv.v.i v9, 0
; VLA-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
@@ -494,12 +495,13 @@ define void @extract_v2i1_v64i1_2(ptr %x, ptr %y) {
; VLS-NEXT: vlm.v v0, (a0)
; VLS-NEXT: vmv.v.i v8, 0
; VLS-NEXT: vmerge.vim v8, v8, 1, v0
+; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLS-NEXT: vmv.v.i v9, 0
; VLS-NEXT: vsetivli zero, 2, e8, m1, ta, ma
; VLS-NEXT: vslidedown.vi v8, v8, 2
; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; VLS-NEXT: vmsne.vi v0, v8, 0
-; VLS-NEXT: vmv.v.i v8, 0
-; VLS-NEXT: vmerge.vim v8, v8, 1, v0
+; VLS-NEXT: vmerge.vim v8, v9, 1, v0
; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; VLS-NEXT: vmv.v.i v9, 0
; VLS-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
@@ -523,12 +525,13 @@ define void @extract_v2i1_v64i1_42(ptr %x, ptr %y) {
; VLA-NEXT: li a0, 42
; VLA-NEXT: vmv.v.i v8, 0
; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLA-NEXT: vmv.v.i v12, 0
; VLA-NEXT: vsetivli zero, 2, e8, m4, ta, ma
; VLA-NEXT: vslidedown.vx v8, v8, a0
; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; VLA-NEXT: vmsne.vi v0, v8, 0
-; VLA-NEXT: vmv.v.i v8, 0
-; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vmerge.vim v8, v12, 1, v0
; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; VLA-NEXT: vmv.v.i v9, 0
; VLA-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
@@ -544,11 +547,12 @@ define void @extract_v2i1_v64i1_42(ptr %x, ptr %y) {
; VLS-NEXT: vlm.v v0, (a0)
; VLS-NEXT: vmv.v.i v8, 0
; VLS-NEXT: vmerge.vim v8, v8, 1, v0
-; VLS-NEXT: vsetivli zero, 2, e8, m1, ta, ma
-; VLS-NEXT: vslidedown.vi v8, v10, 10
; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; VLS-NEXT: vmsne.vi v0, v8, 0
; VLS-NEXT: vmv.v.i v8, 0
+; VLS-NEXT: vsetivli zero, 2, e8, m1, ta, ma
+; VLS-NEXT: vslidedown.vi v9, v10, 10
+; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLS-NEXT: vmsne.vi v0, v9, 0
; VLS-NEXT: vmerge.vim v8, v8, 1, v0
; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; VLS-NEXT: vmv.v.i v9, 0
@@ -589,12 +593,13 @@ define void @extract_v2i1_nxv2i1_2(<vscale x 2 x i1> %x, ptr %y) {
; VLA-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; VLA-NEXT: vmv.v.i v8, 0
; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLA-NEXT: vmv.v.i v9, 0
; VLA-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; VLA-NEXT: vslidedown.vi v8, v8, 2
; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; VLA-NEXT: vmsne.vi v0, v8, 0
-; VLA-NEXT: vmv.v.i v8, 0
-; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vmerge.vim v8, v9, 1, v0
; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; VLA-NEXT: vmv.v.i v9, 0
; VLA-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
@@ -609,12 +614,13 @@ define void @extract_v2i1_nxv2i1_2(<vscale x 2 x i1> %x, ptr %y) {
; VLS-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; VLS-NEXT: vmv.v.i v8, 0
; VLS-NEXT: vmerge.vim v8, v8, 1, v0
+; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLS-NEXT: vmv.v.i v9, 0
; VLS-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; VLS-NEXT: vslidedown.vi v8, v8, 2
; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; VLS-NEXT: vmsne.vi v0, v8, 0
-; VLS-NEXT: vmv.v.i v8, 0
-; VLS-NEXT: vmerge.vim v8, v8, 1, v0
+; VLS-NEXT: vmerge.vim v8, v9, 1, v0
; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; VLS-NEXT: vmv.v.i v9, 0
; VLS-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
@@ -653,12 +659,13 @@ define void @extract_v2i1_nxv64i1_2(<vscale x 64 x i1> %x, ptr %y) {
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmsne.vi v0, v8, 0
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
@@ -679,12 +686,13 @@ define void @extract_v2i1_nxv64i1_42(<vscale x 64 x i1> %x, ptr %y) {
; VLA-NEXT: vmv.v.i v8, 0
; VLA-NEXT: li a1, 42
; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLA-NEXT: vmv.v.i v12, 0
; VLA-NEXT: vsetivli zero, 2, e8, m4, ta, ma
; VLA-NEXT: vslidedown.vx v8, v8, a1
; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; VLA-NEXT: vmsne.vi v0, v8, 0
-; VLA-NEXT: vmv.v.i v8, 0
-; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vmerge.vim v8, v12, 1, v0
; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; VLA-NEXT: vmv.v.i v9, 0
; VLA-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
@@ -699,11 +707,12 @@ define void @extract_v2i1_nxv64i1_42(<vscale x 64 x i1> %x, ptr %y) {
; VLS-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; VLS-NEXT: vmv.v.i v8, 0
; VLS-NEXT: vmerge.vim v8, v8, 1, v0
-; VLS-NEXT: vsetivli zero, 2, e8, m1, ta, ma
-; VLS-NEXT: vslidedown.vi v8, v10, 10
; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; VLS-NEXT: vmsne.vi v0, v8, 0
; VLS-NEXT: vmv.v.i v8, 0
+; VLS-NEXT: vsetivli zero, 2, e8, m1, ta, ma
+; VLS-NEXT: vslidedown.vi v9, v10, 10
+; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLS-NEXT: vmsne.vi v0, v9, 0
; VLS-NEXT: vmerge.vim v8, v8, 1, v0
; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; VLS-NEXT: vmv.v.i v9, 0
@@ -724,12 +733,13 @@ define void @extract_v2i1_nxv32i1_26(<vscale x 32 x i1> %x, ptr %y) {
; VLA-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; VLA-NEXT: vmv.v.i v8, 0
; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLA-NEXT: vmv.v.i v10, 0
; VLA-NEXT: vsetivli zero, 2, e8, m2, ta, ma
; VLA-NEXT: vslidedown.vi v8, v8, 26
; VLA-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; VLA-NEXT: vmsne.vi v0, v8, 0
-; VLA-NEXT: vmv.v.i v8, 0
-; VLA-NEXT: vmerge.vim v8, v8, 1, v0
+; VLA-NEXT: vmerge.vim v8, v10, 1, v0
; VLA-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; VLA-NEXT: vmv.v.i v9, 0
; VLA-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
@@ -744,11 +754,12 @@ define void @extract_v2i1_nxv32i1_26(<vscale x 32 x i1> %x, ptr %y) {
; VLS-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; VLS-NEXT: vmv.v.i v8, 0
; VLS-NEXT: vmerge.vim v8, v8, 1, v0
-; VLS-NEXT: vsetivli zero, 2, e8, m1, ta, ma
-; VLS-NEXT: vslidedown.vi v8, v9, 10
; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; VLS-NEXT: vmsne.vi v0, v8, 0
; VLS-NEXT: vmv.v.i v8, 0
+; VLS-NEXT: vsetivli zero, 2, e8, m1, ta, ma
+; VLS-NEXT: vslidedown.vi v9, v9, 10
+; VLS-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; VLS-NEXT: vmsne.vi v0, v9, 0
; VLS-NEXT: vmerge.vim v8, v8, 1, v0
; VLS-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; VLS-NEXT: vmv.v.i v9, 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
index 22aef4899a6c2..2a5c25c15dbb5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
@@ -12,10 +12,10 @@ define <1 x half> @ceil_v1f16(<1 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -35,10 +35,10 @@ define <2 x half> @ceil_v2f16(<2 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -58,10 +58,10 @@ define <4 x half> @ceil_v4f16(<4 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -81,10 +81,10 @@ define <8 x half> @ceil_v8f16(<8 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -104,10 +104,10 @@ define <16 x half> @ceil_v16f16(<16 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -129,9 +129,9 @@ define <32 x half> @ceil_v32f16(<32 x half> %x) strictfp {
; CHECK-NEXT: slli a1, a1, 10
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.h.x fa5, a1
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -151,9 +151,9 @@ define <1 x float> @ceil_v1f32(<1 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -173,9 +173,9 @@ define <2 x float> @ceil_v2f32(<2 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -195,9 +195,9 @@ define <4 x float> @ceil_v4f32(<4 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -217,9 +217,9 @@ define <8 x float> @ceil_v8f32(<8 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -239,9 +239,9 @@ define <16 x float> @ceil_v16f32(<16 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
-; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -261,9 +261,9 @@ define <1 x double> @ceil_v1f64(<1 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI11_0)
; RV32-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -279,10 +279,10 @@ define <1 x double> @ceil_v1f64(<1 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v9, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vfabs.v v9, v8
+; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -302,9 +302,9 @@ define <2 x double> @ceil_v2f64(<2 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -320,10 +320,10 @@ define <2 x double> @ceil_v2f64(<2 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v9, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vfabs.v v9, v8
+; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -343,9 +343,9 @@ define <4 x double> @ceil_v4f64(<4 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: vmflt.vf v0, v10, fa5
-; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -361,10 +361,10 @@ define <4 x double> @ceil_v4f64(<4 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v10, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vfabs.v v10, v8
+; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -384,9 +384,9 @@ define <8 x double> @ceil_v8f64(<8 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI14_0)
; RV32-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vfabs.v v12, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
-; RV32-NEXT: fsrmi a0, 3
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -402,10 +402,10 @@ define <8 x double> @ceil_v8f64(<8 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v12, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: fsrm a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
index 511382cf5436e..78b11d04df693 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
@@ -12,10 +12,10 @@ define <1 x half> @floor_v1f16(<1 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -35,10 +35,10 @@ define <2 x half> @floor_v2f16(<2 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -58,10 +58,10 @@ define <4 x half> @floor_v4f16(<4 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -81,10 +81,10 @@ define <8 x half> @floor_v8f16(<8 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -104,10 +104,10 @@ define <16 x half> @floor_v16f16(<16 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -129,9 +129,9 @@ define <32 x half> @floor_v32f16(<32 x half> %x) strictfp {
; CHECK-NEXT: slli a1, a1, 10
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.h.x fa5, a1
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -151,9 +151,9 @@ define <1 x float> @floor_v1f32(<1 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -173,9 +173,9 @@ define <2 x float> @floor_v2f32(<2 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -195,9 +195,9 @@ define <4 x float> @floor_v4f32(<4 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -217,9 +217,9 @@ define <8 x float> @floor_v8f32(<8 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -239,9 +239,9 @@ define <16 x float> @floor_v16f32(<16 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -261,9 +261,9 @@ define <1 x double> @floor_v1f64(<1 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI11_0)
; RV32-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 2
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: fsrmi a0, 2
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -279,10 +279,10 @@ define <1 x double> @floor_v1f64(<1 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v9, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 2
+; RV64-NEXT: vfabs.v v9, v8
+; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -302,9 +302,9 @@ define <2 x double> @floor_v2f64(<2 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 2
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: fsrmi a0, 2
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -320,10 +320,10 @@ define <2 x double> @floor_v2f64(<2 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v9, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 2
+; RV64-NEXT: vfabs.v v9, v8
+; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -343,9 +343,9 @@ define <4 x double> @floor_v4f64(<4 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 2
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: vmflt.vf v0, v10, fa5
-; RV32-NEXT: fsrmi a0, 2
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -361,10 +361,10 @@ define <4 x double> @floor_v4f64(<4 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v10, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: fsrmi a0, 2
+; RV64-NEXT: vfabs.v v10, v8
+; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -384,9 +384,9 @@ define <8 x double> @floor_v8f64(<8 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI14_0)
; RV32-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 2
; RV32-NEXT: vfabs.v v12, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
-; RV32-NEXT: fsrmi a0, 2
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -402,10 +402,10 @@ define <8 x double> @floor_v8f64(<8 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v12, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 2
+; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: fsrm a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
index 69a136d6e9358..b5ec8d73c48de 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
@@ -16,9 +16,9 @@ define <2 x half> @vp_floor_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl)
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 2
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 2
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -30,26 +30,24 @@ define <2 x half> @vp_floor_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl)
; ZVFHMIN-LABEL: vp_floor_v2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 2
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <2 x half> @llvm.vp.floor.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl)
ret <2 x half> %v
@@ -63,8 +61,8 @@ define <2 x half> @vp_floor_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 2
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -77,11 +75,11 @@ define <2 x half> @vp_floor_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) {
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -102,9 +100,9 @@ define <4 x half> @vp_floor_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl)
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 2
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 2
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -116,26 +114,24 @@ define <4 x half> @vp_floor_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl)
; ZVFHMIN-LABEL: vp_floor_v4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 2
-; ZVFHMIN-NEXT: vmv.v.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <4 x half> @llvm.vp.floor.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)
ret <4 x half> %v
@@ -149,8 +145,8 @@ define <4 x half> @vp_floor_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 2
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -163,11 +159,11 @@ define <4 x half> @vp_floor_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -188,9 +184,9 @@ define <8 x half> @vp_floor_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl)
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 2
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 2
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -205,21 +201,21 @@ define <8 x half> @vp_floor_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl)
; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v13, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: fsrmi a0, 2
-; ZVFHMIN-NEXT: vmv1r.v v0, v13
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
+; ZVFHMIN-NEXT: vmv1r.v v0, v13
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: ret
@@ -235,8 +231,8 @@ define <8 x half> @vp_floor_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 2
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -249,11 +245,11 @@ define <8 x half> @vp_floor_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) {
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -293,21 +289,21 @@ define <16 x half> @vp_floor_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %
; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: fsrmi a0, 2
-; ZVFHMIN-NEXT: vmv1r.v v0, v17
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vmv1r.v v0, v17
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
@@ -323,8 +319,8 @@ define <16 x half> @vp_floor_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl)
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 2
+; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -337,11 +333,11 @@ define <16 x half> @vp_floor_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl)
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -361,9 +357,9 @@ define <2 x float> @vp_floor_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroext %ev
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -382,8 +378,8 @@ define <2 x float> @vp_floor_v2f32_unmasked(<2 x float> %va, i32 zeroext %evl) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -401,9 +397,9 @@ define <4 x float> @vp_floor_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %ev
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -422,8 +418,8 @@ define <4 x float> @vp_floor_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -464,8 +460,8 @@ define <8 x float> @vp_floor_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) {
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -506,8 +502,8 @@ define <16 x float> @vp_floor_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -525,9 +521,9 @@ define <2 x double> @vp_floor_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI16_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZVFH-NEXT: fsrmi a0, 2
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a0, 2
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
@@ -543,9 +539,9 @@ define <2 x double> @vp_floor_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
+; RV64ZVFH-NEXT: fsrmi a0, 2
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZVFH-NEXT: fsrmi a0, 2
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
@@ -560,9 +556,9 @@ define <2 x double> @vp_floor_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI16_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZVFHMIN-NEXT: fsrmi a0, 2
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a0, 2
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
@@ -578,9 +574,9 @@ define <2 x double> @vp_floor_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
+; RV64ZVFHMIN-NEXT: fsrmi a0, 2
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a0, 2
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
@@ -599,8 +595,8 @@ define <2 x double> @vp_floor_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl)
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI17_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: fsrmi a0, 2
+; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -615,8 +611,8 @@ define <2 x double> @vp_floor_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl)
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: fsrmi a0, 2
+; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -630,8 +626,8 @@ define <2 x double> @vp_floor_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl)
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI17_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -646,8 +642,8 @@ define <2 x double> @vp_floor_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl)
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -747,8 +743,8 @@ define <4 x double> @vp_floor_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl)
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI19_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZVFH-NEXT: vfabs.v v10, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: fsrmi a0, 2
+; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -763,8 +759,8 @@ define <4 x double> @vp_floor_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl)
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: fsrmi a0, 2
+; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -778,8 +774,8 @@ define <4 x double> @vp_floor_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl)
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI19_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v10, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -794,8 +790,8 @@ define <4 x double> @vp_floor_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl)
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -895,8 +891,8 @@ define <8 x double> @vp_floor_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI21_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZVFH-NEXT: vfabs.v v12, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: fsrmi a0, 2
+; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -911,8 +907,8 @@ define <8 x double> @vp_floor_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: fsrmi a0, 2
+; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -926,8 +922,8 @@ define <8 x double> @vp_floor_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI21_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v12, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -942,8 +938,8 @@ define <8 x double> @vp_floor_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1043,8 +1039,8 @@ define <15 x double> @vp_floor_v15f64_unmasked(<15 x double> %va, i32 zeroext %e
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI23_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 2
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1059,8 +1055,8 @@ define <15 x double> @vp_floor_v15f64_unmasked(<15 x double> %va, i32 zeroext %e
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 2
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1074,8 +1070,8 @@ define <15 x double> @vp_floor_v15f64_unmasked(<15 x double> %va, i32 zeroext %e
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI23_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1090,8 +1086,8 @@ define <15 x double> @vp_floor_v15f64_unmasked(<15 x double> %va, i32 zeroext %e
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1191,8 +1187,8 @@ define <16 x double> @vp_floor_v16f64_unmasked(<16 x double> %va, i32 zeroext %e
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 2
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1207,8 +1203,8 @@ define <16 x double> @vp_floor_v16f64_unmasked(<16 x double> %va, i32 zeroext %e
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 2
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1222,8 +1218,8 @@ define <16 x double> @vp_floor_v16f64_unmasked(<16 x double> %va, i32 zeroext %e
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1238,8 +1234,8 @@ define <16 x double> @vp_floor_v16f64_unmasked(<16 x double> %va, i32 zeroext %e
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1254,43 +1250,43 @@ define <32 x double> @vp_floor_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; RV32ZVFH-LABEL: vp_floor_v32f64:
; RV32ZVFH: # %bb.0:
; RV32ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32ZVFH-NEXT: vmv1r.v v6, v0
+; RV32ZVFH-NEXT: vmv1r.v v7, v0
; RV32ZVFH-NEXT: li a2, 16
-; RV32ZVFH-NEXT: vslidedown.vi v7, v0, 2
+; RV32ZVFH-NEXT: vslidedown.vi v6, v0, 2
; RV32ZVFH-NEXT: mv a1, a0
; RV32ZVFH-NEXT: bltu a0, a2, .LBB26_2
; RV32ZVFH-NEXT: # %bb.1:
; RV32ZVFH-NEXT: li a1, 16
; RV32ZVFH-NEXT: .LBB26_2:
-; RV32ZVFH-NEXT: vmv1r.v v0, v6
+; RV32ZVFH-NEXT: vmv1r.v v0, v7
; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v8, v0.t
-; RV32ZVFH-NEXT: lui a1, %hi(.LCPI26_0)
-; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
-; RV32ZVFH-NEXT: addi a1, a0, -16
-; RV32ZVFH-NEXT: sltu a0, a0, a1
+; RV32ZVFH-NEXT: lui a2, %hi(.LCPI26_0)
+; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
+; RV32ZVFH-NEXT: addi a2, a0, -16
+; RV32ZVFH-NEXT: sltu a0, a0, a2
; RV32ZVFH-NEXT: addi a0, a0, -1
-; RV32ZVFH-NEXT: and a0, a0, a1
+; RV32ZVFH-NEXT: and a0, a0, a2
+; RV32ZVFH-NEXT: fsrmi a2, 2
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a1, 2
+; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV32ZVFH-NEXT: vmv1r.v v0, v6
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t
+; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV32ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV32ZVFH-NEXT: vmv1r.v v0, v7
+; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFH-NEXT: fsrm a1
+; RV32ZVFH-NEXT: fsrm a2
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFH-NEXT: vmv1r.v v0, v7
+; RV32ZVFH-NEXT: vmv1r.v v0, v6
+; RV32ZVFH-NEXT: fsrmi a1, 2
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a0, 2
-; RV32ZVFH-NEXT: vmv1r.v v0, v7
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFH-NEXT: fsrm a0
+; RV32ZVFH-NEXT: fsrm a1
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1299,44 +1295,44 @@ define <32 x double> @vp_floor_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; RV64ZVFH-LABEL: vp_floor_v32f64:
; RV64ZVFH: # %bb.0:
; RV64ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVFH-NEXT: vmv1r.v v6, v0
+; RV64ZVFH-NEXT: vmv1r.v v7, v0
; RV64ZVFH-NEXT: li a2, 16
-; RV64ZVFH-NEXT: vslidedown.vi v7, v0, 2
+; RV64ZVFH-NEXT: vslidedown.vi v6, v0, 2
; RV64ZVFH-NEXT: mv a1, a0
; RV64ZVFH-NEXT: bltu a0, a2, .LBB26_2
; RV64ZVFH-NEXT: # %bb.1:
; RV64ZVFH-NEXT: li a1, 16
; RV64ZVFH-NEXT: .LBB26_2:
-; RV64ZVFH-NEXT: vmv1r.v v0, v6
+; RV64ZVFH-NEXT: vmv1r.v v0, v7
; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v8, v0.t
-; RV64ZVFH-NEXT: li a1, 1075
-; RV64ZVFH-NEXT: slli a1, a1, 52
-; RV64ZVFH-NEXT: fmv.d.x fa5, a1
-; RV64ZVFH-NEXT: addi a1, a0, -16
-; RV64ZVFH-NEXT: sltu a0, a0, a1
+; RV64ZVFH-NEXT: li a2, 1075
+; RV64ZVFH-NEXT: slli a2, a2, 52
+; RV64ZVFH-NEXT: fmv.d.x fa5, a2
+; RV64ZVFH-NEXT: addi a2, a0, -16
+; RV64ZVFH-NEXT: sltu a0, a0, a2
; RV64ZVFH-NEXT: addi a0, a0, -1
+; RV64ZVFH-NEXT: and a0, a0, a2
+; RV64ZVFH-NEXT: fsrmi a2, 2
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV64ZVFH-NEXT: and a0, a0, a1
-; RV64ZVFH-NEXT: fsrmi a1, 2
+; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV64ZVFH-NEXT: vmv1r.v v0, v6
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t
+; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV64ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV64ZVFH-NEXT: vmv1r.v v0, v7
+; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFH-NEXT: fsrm a1
+; RV64ZVFH-NEXT: fsrm a2
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
+; RV64ZVFH-NEXT: fsrmi a1, 2
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFH-NEXT: vmv1r.v v0, v7
+; RV64ZVFH-NEXT: vmv1r.v v0, v6
; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV64ZVFH-NEXT: fsrmi a0, 2
-; RV64ZVFH-NEXT: vmv1r.v v0, v7
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFH-NEXT: fsrm a0
+; RV64ZVFH-NEXT: fsrm a1
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1345,43 +1341,43 @@ define <32 x double> @vp_floor_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; RV32ZVFHMIN-LABEL: vp_floor_v32f64:
; RV32ZVFHMIN: # %bb.0:
; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32ZVFHMIN-NEXT: vmv1r.v v6, v0
+; RV32ZVFHMIN-NEXT: vmv1r.v v7, v0
; RV32ZVFHMIN-NEXT: li a2, 16
-; RV32ZVFHMIN-NEXT: vslidedown.vi v7, v0, 2
+; RV32ZVFHMIN-NEXT: vslidedown.vi v6, v0, 2
; RV32ZVFHMIN-NEXT: mv a1, a0
; RV32ZVFHMIN-NEXT: bltu a0, a2, .LBB26_2
; RV32ZVFHMIN-NEXT: # %bb.1:
; RV32ZVFHMIN-NEXT: li a1, 16
; RV32ZVFHMIN-NEXT: .LBB26_2:
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI26_0)
-; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
-; RV32ZVFHMIN-NEXT: addi a1, a0, -16
-; RV32ZVFHMIN-NEXT: sltu a0, a0, a1
+; RV32ZVFHMIN-NEXT: lui a2, %hi(.LCPI26_0)
+; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
+; RV32ZVFHMIN-NEXT: addi a2, a0, -16
+; RV32ZVFHMIN-NEXT: sltu a0, a0, a2
; RV32ZVFHMIN-NEXT: addi a0, a0, -1
-; RV32ZVFHMIN-NEXT: and a0, a0, a1
+; RV32ZVFHMIN-NEXT: and a0, a0, a2
+; RV32ZVFHMIN-NEXT: fsrmi a2, 2
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a1, 2
+; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
+; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV32ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a1
+; RV32ZVFHMIN-NEXT: fsrm a2
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV32ZVFHMIN-NEXT: fsrmi a1, 2
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a0, 2
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a0
+; RV32ZVFHMIN-NEXT: fsrm a1
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1390,44 +1386,44 @@ define <32 x double> @vp_floor_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; RV64ZVFHMIN-LABEL: vp_floor_v32f64:
; RV64ZVFHMIN: # %bb.0:
; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVFHMIN-NEXT: vmv1r.v v6, v0
+; RV64ZVFHMIN-NEXT: vmv1r.v v7, v0
; RV64ZVFHMIN-NEXT: li a2, 16
-; RV64ZVFHMIN-NEXT: vslidedown.vi v7, v0, 2
+; RV64ZVFHMIN-NEXT: vslidedown.vi v6, v0, 2
; RV64ZVFHMIN-NEXT: mv a1, a0
; RV64ZVFHMIN-NEXT: bltu a0, a2, .LBB26_2
; RV64ZVFHMIN-NEXT: # %bb.1:
; RV64ZVFHMIN-NEXT: li a1, 16
; RV64ZVFHMIN-NEXT: .LBB26_2:
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: li a1, 1075
-; RV64ZVFHMIN-NEXT: slli a1, a1, 52
-; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a1
-; RV64ZVFHMIN-NEXT: addi a1, a0, -16
-; RV64ZVFHMIN-NEXT: sltu a0, a0, a1
+; RV64ZVFHMIN-NEXT: li a2, 1075
+; RV64ZVFHMIN-NEXT: slli a2, a2, 52
+; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a2
+; RV64ZVFHMIN-NEXT: addi a2, a0, -16
+; RV64ZVFHMIN-NEXT: sltu a0, a0, a2
; RV64ZVFHMIN-NEXT: addi a0, a0, -1
+; RV64ZVFHMIN-NEXT: and a0, a0, a2
+; RV64ZVFHMIN-NEXT: fsrmi a2, 2
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV64ZVFHMIN-NEXT: and a0, a0, a1
-; RV64ZVFHMIN-NEXT: fsrmi a1, 2
+; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
+; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV64ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a1
+; RV64ZVFHMIN-NEXT: fsrm a2
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
+; RV64ZVFHMIN-NEXT: fsrmi a1, 2
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a0, 2
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a0
+; RV64ZVFHMIN-NEXT: fsrm a1
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1447,28 +1443,25 @@ define <32 x double> @vp_floor_v32f64_unmasked(<32 x double> %va, i32 zeroext %e
; RV32ZVFH-NEXT: .LBB27_2:
; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v8
-; RV32ZVFH-NEXT: lui a2, %hi(.LCPI27_0)
-; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
-; RV32ZVFH-NEXT: addi a2, a0, -16
-; RV32ZVFH-NEXT: sltu a0, a0, a2
+; RV32ZVFH-NEXT: lui a1, %hi(.LCPI27_0)
+; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
+; RV32ZVFH-NEXT: addi a1, a0, -16
+; RV32ZVFH-NEXT: sltu a0, a0, a1
; RV32ZVFH-NEXT: addi a0, a0, -1
-; RV32ZVFH-NEXT: and a0, a0, a2
-; RV32ZVFH-NEXT: fsrmi a2, 2
+; RV32ZVFH-NEXT: and a0, a0, a1
+; RV32ZVFH-NEXT: fsrmi a1, 2
; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFH-NEXT: vfabs.v v24, v16
-; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5
-; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFH-NEXT: fsrm a2
+; RV32ZVFH-NEXT: fsrm a1
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV32ZVFH-NEXT: fsrmi a1, 2
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFH-NEXT: vmv1r.v v0, v7
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFH-NEXT: vfabs.v v24, v16
+; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
+; RV32ZVFH-NEXT: fsrmi a0, 2
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFH-NEXT: fsrm a1
+; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1484,29 +1477,26 @@ define <32 x double> @vp_floor_v32f64_unmasked(<32 x double> %va, i32 zeroext %e
; RV64ZVFH-NEXT: .LBB27_2:
; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v8
-; RV64ZVFH-NEXT: li a2, 1075
-; RV64ZVFH-NEXT: slli a2, a2, 52
-; RV64ZVFH-NEXT: fmv.d.x fa5, a2
-; RV64ZVFH-NEXT: addi a2, a0, -16
-; RV64ZVFH-NEXT: sltu a0, a0, a2
+; RV64ZVFH-NEXT: li a1, 1075
+; RV64ZVFH-NEXT: slli a1, a1, 52
+; RV64ZVFH-NEXT: fmv.d.x fa5, a1
+; RV64ZVFH-NEXT: addi a1, a0, -16
+; RV64ZVFH-NEXT: sltu a0, a0, a1
; RV64ZVFH-NEXT: addi a0, a0, -1
-; RV64ZVFH-NEXT: and a0, a0, a2
-; RV64ZVFH-NEXT: fsrmi a2, 2
+; RV64ZVFH-NEXT: and a0, a0, a1
+; RV64ZVFH-NEXT: fsrmi a1, 2
; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFH-NEXT: vfabs.v v24, v16
-; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5
-; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFH-NEXT: fsrm a2
+; RV64ZVFH-NEXT: fsrm a1
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV64ZVFH-NEXT: fsrmi a1, 2
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFH-NEXT: vmv1r.v v0, v7
; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFH-NEXT: vfabs.v v24, v16
+; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
+; RV64ZVFH-NEXT: fsrmi a0, 2
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFH-NEXT: fsrm a1
+; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1522,28 +1512,25 @@ define <32 x double> @vp_floor_v32f64_unmasked(<32 x double> %va, i32 zeroext %e
; RV32ZVFHMIN-NEXT: .LBB27_2:
; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v8
-; RV32ZVFHMIN-NEXT: lui a2, %hi(.LCPI27_0)
-; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
-; RV32ZVFHMIN-NEXT: addi a2, a0, -16
-; RV32ZVFHMIN-NEXT: sltu a0, a0, a2
+; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI27_0)
+; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
+; RV32ZVFHMIN-NEXT: addi a1, a0, -16
+; RV32ZVFHMIN-NEXT: sltu a0, a0, a1
; RV32ZVFHMIN-NEXT: addi a0, a0, -1
-; RV32ZVFHMIN-NEXT: and a0, a0, a2
-; RV32ZVFHMIN-NEXT: fsrmi a2, 2
+; RV32ZVFHMIN-NEXT: and a0, a0, a1
+; RV32ZVFHMIN-NEXT: fsrmi a1, 2
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFHMIN-NEXT: vfabs.v v24, v16
-; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5
-; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a2
+; RV32ZVFHMIN-NEXT: fsrm a1
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a1, 2
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFHMIN-NEXT: vfabs.v v24, v16
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
+; RV32ZVFHMIN-NEXT: fsrmi a0, 2
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a1
+; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1559,29 +1546,26 @@ define <32 x double> @vp_floor_v32f64_unmasked(<32 x double> %va, i32 zeroext %e
; RV64ZVFHMIN-NEXT: .LBB27_2:
; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v8
-; RV64ZVFHMIN-NEXT: li a2, 1075
-; RV64ZVFHMIN-NEXT: slli a2, a2, 52
-; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a2
-; RV64ZVFHMIN-NEXT: addi a2, a0, -16
-; RV64ZVFHMIN-NEXT: sltu a0, a0, a2
+; RV64ZVFHMIN-NEXT: li a1, 1075
+; RV64ZVFHMIN-NEXT: slli a1, a1, 52
+; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a1
+; RV64ZVFHMIN-NEXT: addi a1, a0, -16
+; RV64ZVFHMIN-NEXT: sltu a0, a0, a1
; RV64ZVFHMIN-NEXT: addi a0, a0, -1
-; RV64ZVFHMIN-NEXT: and a0, a0, a2
-; RV64ZVFHMIN-NEXT: fsrmi a2, 2
+; RV64ZVFHMIN-NEXT: and a0, a0, a1
+; RV64ZVFHMIN-NEXT: fsrmi a1, 2
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFHMIN-NEXT: vfabs.v v24, v16
-; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5
-; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a2
+; RV64ZVFHMIN-NEXT: fsrm a1
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a1, 2
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFHMIN-NEXT: vfabs.v v24, v16
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
+; RV64ZVFHMIN-NEXT: fsrmi a0, 2
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a1
+; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
index 29797f616777b..d0dd105deb029 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
@@ -12,29 +12,29 @@ define <2 x half> @vfmax_vv_v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> %m, i
; ZVFH-LABEL: vfmax_vv_v2f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT: vmv1r.v v10, v0
+; ZVFH-NEXT: vmv1r.v v11, v0
; ZVFH-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0
+; ZVFH-NEXT: vmv1r.v v0, v11
; ZVFH-NEXT: vmfeq.vv v0, v9, v9, v0.t
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
-; ZVFH-NEXT: vfmax.vv v8, v8, v11, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v11
+; ZVFH-NEXT: vfmax.vv v8, v8, v10, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfmax_vv_v2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v11, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9, v0.t
-; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v11, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
-; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t
-; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v9, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v11
+; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v11
; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
@@ -57,16 +57,14 @@ define <2 x half> @vfmax_vv_v2f16_unmasked(<2 x half> %va, <2 x half> %vb, i32 z
; ZVFHMIN-LABEL: vfmax_vv_v2f16_unmasked:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFHMIN-NEXT: vfmax.vv v9, v8, v9
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
@@ -78,29 +76,29 @@ define <4 x half> @vfmax_vv_v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> %m, i
; ZVFH-LABEL: vfmax_vv_v4f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vmv1r.v v10, v0
+; ZVFH-NEXT: vmv1r.v v11, v0
; ZVFH-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0
+; ZVFH-NEXT: vmv1r.v v0, v11
; ZVFH-NEXT: vmfeq.vv v0, v9, v9, v0.t
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
-; ZVFH-NEXT: vfmax.vv v8, v8, v11, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v11
+; ZVFH-NEXT: vfmax.vv v8, v8, v10, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfmax_vv_v4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v11, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9, v0.t
-; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v11, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
-; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t
-; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v9, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v11
+; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v11
; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
@@ -123,16 +121,14 @@ define <4 x half> @vfmax_vv_v4f16_unmasked(<4 x half> %va, <4 x half> %vb, i32 z
; ZVFHMIN-LABEL: vfmax_vv_v4f16_unmasked:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFHMIN-NEXT: vfmax.vv v9, v8, v9
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
@@ -144,34 +140,33 @@ define <8 x half> @vfmax_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i
; ZVFH-LABEL: vfmax_vv_v8f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFH-NEXT: vmv1r.v v10, v0
+; ZVFH-NEXT: vmv1r.v v11, v0
; ZVFH-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0
+; ZVFH-NEXT: vmv1r.v v0, v11
; ZVFH-NEXT: vmfeq.vv v0, v9, v9, v0.t
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
-; ZVFH-NEXT: vfmax.vv v8, v8, v11, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v11
+; ZVFH-NEXT: vfmax.vv v8, v8, v10, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfmax_vv_v8f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v8, v14, v14, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v14, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v15, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v14, v12, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
-; ZVFHMIN-NEXT: vmfeq.vv v11, v12, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v11
-; ZVFHMIN-NEXT: vmerge.vvm v12, v12, v14, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
-; ZVFHMIN-NEXT: vfmax.vv v12, v12, v8, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v10, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v14
+; ZVFHMIN-NEXT: vmerge.vvm v10, v10, v12, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v15
+; ZVFHMIN-NEXT: vfmax.vv v10, v10, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: ret
%v = call <8 x half> @llvm.vp.maximum.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 %evl)
ret <8 x half> %v
@@ -191,15 +186,13 @@ define <8 x half> @vfmax_vv_v8f16_unmasked(<8 x half> %va, <8 x half> %vb, i32 z
; ZVFHMIN-LABEL: vfmax_vv_v8f16_unmasked:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v10, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
+; ZVFHMIN-NEXT: vmerge.vvm v10, v10, v12, v0
; ZVFHMIN-NEXT: vfmax.vv v10, v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
@@ -212,36 +205,34 @@ define <16 x half> @vfmax_vv_v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1>
; ZVFH-LABEL: vfmax_vv_v16f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vmv1r.v v12, v0
-; ZVFH-NEXT: vmfeq.vv v13, v8, v8, v0.t
-; ZVFH-NEXT: vmv1r.v v0, v13
-; ZVFH-NEXT: vmerge.vvm v14, v8, v10, v0
+; ZVFH-NEXT: vmfeq.vv v12, v8, v8, v0.t
+; ZVFH-NEXT: vmfeq.vv v14, v10, v10, v0.t
+; ZVFH-NEXT: vmv1r.v v15, v0
; ZVFH-NEXT: vmv1r.v v0, v12
-; ZVFH-NEXT: vmfeq.vv v13, v10, v10, v0.t
-; ZVFH-NEXT: vmv1r.v v0, v13
+; ZVFH-NEXT: vmerge.vvm v12, v8, v10, v0
+; ZVFH-NEXT: vmv1r.v v0, v14
; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v12
-; ZVFH-NEXT: vfmax.vv v8, v8, v14, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v15
+; ZVFH-NEXT: vfmax.vv v8, v8, v12, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfmax_vv_v16f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v12, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v8, v20, v20, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v16, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v20, v12, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v21, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v20, v16, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
-; ZVFHMIN-NEXT: vmfeq.vv v13, v16, v16, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v13
-; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v20, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
-; ZVFHMIN-NEXT: vfmax.vv v16, v16, v8, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v12, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v20
+; ZVFHMIN-NEXT: vmerge.vvm v12, v12, v16, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v21
+; ZVFHMIN-NEXT: vfmax.vv v12, v12, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
%v = call <16 x half> @llvm.vp.maximum.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> %m, i32 %evl)
ret <16 x half> %v
@@ -261,15 +252,13 @@ define <16 x half> @vfmax_vv_v16f16_unmasked(<16 x half> %va, <16 x half> %vb, i
; ZVFHMIN-LABEL: vfmax_vv_v16f16_unmasked:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
-; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v12, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
+; ZVFHMIN-NEXT: vmerge.vvm v12, v12, v16, v0
; ZVFHMIN-NEXT: vfmax.vv v12, v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
@@ -282,14 +271,14 @@ define <2 x float> @vfmax_vv_v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m
; CHECK-LABEL: vfmax_vv_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; CHECK-NEXT: vmerge.vvm v11, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vfmax.vv v8, v8, v11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vfmax.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%v = call <2 x float> @llvm.vp.maximum.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m, i32 %evl)
ret <2 x float> %v
@@ -313,14 +302,14 @@ define <4 x float> @vfmax_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m
; CHECK-LABEL: vfmax_vv_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; CHECK-NEXT: vmerge.vvm v11, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vfmax.vv v8, v8, v11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vfmax.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%v = call <4 x float> @llvm.vp.maximum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl)
ret <4 x float> %v
@@ -344,16 +333,15 @@ define <8 x float> @vfmax_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m
; CHECK-LABEL: vfmax_vv_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v12, v0
-; CHECK-NEXT: vmfeq.vv v13, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: vmerge.vvm v14, v8, v10, v0
+; CHECK-NEXT: vmfeq.vv v12, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v14, v10, v10, v0.t
+; CHECK-NEXT: vmv1r.v v15, v0
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vv v13, v10, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmerge.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vfmax.vv v8, v8, v14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v15
+; CHECK-NEXT: vfmax.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%v = call <8 x float> @llvm.vp.maximum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl)
ret <8 x float> %v
@@ -377,16 +365,15 @@ define <16 x float> @vfmax_vv_v16f32(<16 x float> %va, <16 x float> %vb, <16 x i
; CHECK-LABEL: vfmax_vv_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vmv1r.v v16, v0
-; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v17
-; CHECK-NEXT: vmerge.vvm v20, v8, v12, v0
+; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v20, v12, v12, v0.t
+; CHECK-NEXT: vmv1r.v v21, v0
; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vmfeq.vv v17, v12, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmerge.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vfmax.vv v8, v8, v20, v0.t
+; CHECK-NEXT: vmv1r.v v0, v21
+; CHECK-NEXT: vfmax.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret
%v = call <16 x float> @llvm.vp.maximum.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> %m, i32 %evl)
ret <16 x float> %v
@@ -410,14 +397,14 @@ define <2 x double> @vfmax_vv_v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1>
; CHECK-LABEL: vfmax_vv_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; CHECK-NEXT: vmerge.vvm v11, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vfmax.vv v8, v8, v11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vfmax.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%v = call <2 x double> @llvm.vp.maximum.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> %m, i32 %evl)
ret <2 x double> %v
@@ -441,16 +428,15 @@ define <4 x double> @vfmax_vv_v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1>
; CHECK-LABEL: vfmax_vv_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v12, v0
-; CHECK-NEXT: vmfeq.vv v13, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: vmerge.vvm v14, v8, v10, v0
+; CHECK-NEXT: vmfeq.vv v12, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v14, v10, v10, v0.t
+; CHECK-NEXT: vmv1r.v v15, v0
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vv v13, v10, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmerge.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vfmax.vv v8, v8, v14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v15
+; CHECK-NEXT: vfmax.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%v = call <4 x double> @llvm.vp.maximum.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> %m, i32 %evl)
ret <4 x double> %v
@@ -474,16 +460,15 @@ define <8 x double> @vfmax_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1>
; CHECK-LABEL: vfmax_vv_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vmv1r.v v16, v0
-; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v17
-; CHECK-NEXT: vmerge.vvm v20, v8, v12, v0
+; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v20, v12, v12, v0.t
+; CHECK-NEXT: vmv1r.v v21, v0
; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vmfeq.vv v17, v12, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmerge.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vfmax.vv v8, v8, v20, v0.t
+; CHECK-NEXT: vmv1r.v v0, v21
+; CHECK-NEXT: vfmax.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret
%v = call <8 x double> @llvm.vp.maximum.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 %evl)
ret <8 x double> %v
@@ -507,15 +492,14 @@ define <16 x double> @vfmax_vv_v16f64(<16 x double> %va, <16 x double> %vb, <16
; CHECK-LABEL: vfmax_vv_v16f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vmfeq.vv v24, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; CHECK-NEXT: vmv1r.v v6, v0
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmfeq.vv v6, v16, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vfmax.vv v8, v8, v24, v0.t
; CHECK-NEXT: ret
%v = call <16 x double> @llvm.vp.maximum.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> %m, i32 %evl)
@@ -527,9 +511,8 @@ define <16 x double> @vfmax_vv_v16f64_unmasked(<16 x double> %va, <16 x double>
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v16, v16
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: vfmax.vv v8, v8, v24
; CHECK-NEXT: ret
@@ -543,75 +526,140 @@ define <32 x double> @vfmax_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: li a3, 41
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v6, v0
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a1, a0, 128
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a1)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vle64.v v24, (a0)
+; CHECK-NEXT: vle64.v v16, (a0)
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a4, a3, 5
+; CHECK-NEXT: add a3, a4, a3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v7, v0, 2
+; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 5
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
; CHECK-NEXT: bltu a2, a1, .LBB24_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB24_2:
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v5, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v5
-; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmfeq.vv v5, v24, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v5
-; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vfmax.vv v8, v8, v16, v0.t
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: addi a0, a2, -16
-; CHECK-NEXT: sltu a1, a2, a0
-; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a3, a1, 5
+; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v24, v16, v16, v0.t
+; CHECK-NEXT: vmfeq.vv v24, v8, v8, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a3, a1, 5
+; CHECK-NEXT: add a1, a3, a1
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmfeq.vv v25, v16, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v7, v25
+; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: addi a1, a2, -16
+; CHECK-NEXT: sltu a2, a2, a1
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a1, a2, a1
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 5
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; CHECK-NEXT: vmfeq.vv v7, v8, v8, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmfeq.vv v6, v8, v8, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: vfmax.vv v16, v16, v24, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a2, a0, 5
+; CHECK-NEXT: add a0, a2, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0
+; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmfeq.vv v6, v8, v8, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a2, 24
+; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vfmax.vv v16, v16, v24, v0.t
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 5
+; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 24
+; CHECK-NEXT: li a1, 41
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
@@ -632,16 +680,13 @@ define <32 x double> @vfmax_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a1)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
@@ -659,30 +704,32 @@ define <32 x double> @vfmax_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
; CHECK-NEXT: vfmax.vv v8, v8, v16
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v7, v8, v8
; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
; CHECK-NEXT: vfmax.vv v16, v16, v24
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
index a38f8585f9cce..36ceaf4ce31e1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll
@@ -16,16 +16,14 @@ define <2 x bfloat> @vfmax_v2bf16_vv(<2 x bfloat> %a, <2 x bfloat> %b) {
; ZVFBFMIN-LABEL: vfmax_v2bf16_vv:
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v9
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v9
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFBFMIN-NEXT: vfmax.vv v9, v8, v9
+; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFBFMIN-NEXT: vfmax.vv v9, v9, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
; ZVFBFMIN-NEXT: ret
@@ -47,16 +45,14 @@ define <4 x bfloat> @vfmax_v4bf16_vv(<4 x bfloat> %a, <4 x bfloat> %b) {
; ZVFBFMIN-LABEL: vfmax_v4bf16_vv:
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v9
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v9
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFBFMIN-NEXT: vfmax.vv v9, v8, v9
+; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFBFMIN-NEXT: vfmax.vv v9, v9, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
; ZVFBFMIN-NEXT: ret
@@ -78,15 +74,13 @@ define <8 x bfloat> @vfmax_v8bf16_vv(<8 x bfloat> %a, <8 x bfloat> %b) {
; ZVFBFMIN-LABEL: vfmax_v8bf16_vv:
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v9
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v9
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v10, v12, v0
; ZVFBFMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFBFMIN-NEXT: vmerge.vvm v10, v12, v10, v0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v12, v10, v0
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
+; ZVFBFMIN-NEXT: vmerge.vvm v10, v10, v12, v0
; ZVFBFMIN-NEXT: vfmax.vv v10, v10, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
@@ -109,15 +103,13 @@ define <16 x bfloat> @vfmax_v16bf16_vv(<16 x bfloat> %a, <16 x bfloat> %b) {
; ZVFBFMIN-LABEL: vfmax_v16bf16_vv:
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v10
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v10
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v12, v16, v0
; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
-; ZVFBFMIN-NEXT: vmerge.vvm v12, v16, v12, v0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v12, v0
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v12, v12
+; ZVFBFMIN-NEXT: vmerge.vvm v12, v12, v16, v0
; ZVFBFMIN-NEXT: vfmax.vv v12, v12, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
@@ -150,16 +142,14 @@ define <2 x half> @vfmax_v2f16_vv(<2 x half> %a, <2 x half> %b) {
; ZVFHMIN-LABEL: vfmax_v2f16_vv:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFHMIN-NEXT: vfmax.vv v9, v8, v9
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
@@ -181,16 +171,14 @@ define <4 x half> @vfmax_v4f16_vv(<4 x half> %a, <4 x half> %b) {
; ZVFHMIN-LABEL: vfmax_v4f16_vv:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFHMIN-NEXT: vfmax.vv v9, v8, v9
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
@@ -212,15 +200,13 @@ define <8 x half> @vfmax_v8f16_vv(<8 x half> %a, <8 x half> %b) {
; ZVFHMIN-LABEL: vfmax_v8f16_vv:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v10, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
+; ZVFHMIN-NEXT: vmerge.vvm v10, v10, v12, v0
; ZVFHMIN-NEXT: vfmax.vv v10, v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
@@ -243,15 +229,13 @@ define <16 x half> @vfmax_v16f16_vv(<16 x half> %a, <16 x half> %b) {
; ZVFHMIN-LABEL: vfmax_v16f16_vv:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
-; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v12, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
+; ZVFHMIN-NEXT: vmerge.vvm v12, v12, v16, v0
; ZVFHMIN-NEXT: vfmax.vv v12, v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
@@ -363,9 +347,8 @@ define <16 x double> @vfmax_v16f64_vv(<16 x double> %a, <16 x double> %b) nounwi
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v16, v16
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: vfmax.vv v8, v8, v24
; CHECK-NEXT: ret
@@ -469,8 +452,8 @@ define <4 x half> @vfmax_v2f16_vv_nnan_insert_subvector(<2 x half> %a, <2 x half
; ZVFH-NEXT: vfadd.vv v8, v8, v8
; ZVFH-NEXT: vfadd.vv v9, v9, v9
; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVFH-NEXT: vmfeq.vv v0, v10, v10
; ZVFH-NEXT: vslideup.vi v8, v9, 2
+; ZVFH-NEXT: vmfeq.vv v0, v10, v10
; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0
; ZVFH-NEXT: vfmax.vv v8, v8, v10
; ZVFH-NEXT: ret
@@ -480,20 +463,19 @@ define <4 x half> @vfmax_v2f16_vv_nnan_insert_subvector(<2 x half> %a, <2 x half
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfadd.vv v9, v11, v11
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfadd.vv v10, v11, v11
; ZVFHMIN-NEXT: vfadd.vv v8, v8, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v9
-; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v8
+; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vslideup.vi v11, v9, 2
+; ZVFHMIN-NEXT: vslideup.vi v11, v10, 2
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmerge.vvm v10, v8, v9, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
index 8c18675c2162b..6897082b4fb83 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
@@ -12,29 +12,29 @@ define <2 x half> @vfmin_vv_v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> %m, i
; ZVFH-LABEL: vfmin_vv_v2f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT: vmv1r.v v10, v0
+; ZVFH-NEXT: vmv1r.v v11, v0
; ZVFH-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0
+; ZVFH-NEXT: vmv1r.v v0, v11
; ZVFH-NEXT: vmfeq.vv v0, v9, v9, v0.t
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
-; ZVFH-NEXT: vfmin.vv v8, v8, v11, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v11
+; ZVFH-NEXT: vfmin.vv v8, v8, v10, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfmin_vv_v2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v11, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9, v0.t
-; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v11, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
-; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t
-; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v9, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v11
+; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v11
; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
@@ -57,16 +57,14 @@ define <2 x half> @vfmin_vv_v2f16_unmasked(<2 x half> %va, <2 x half> %vb, i32 z
; ZVFHMIN-LABEL: vfmin_vv_v2f16_unmasked:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFHMIN-NEXT: vfmin.vv v9, v8, v9
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
@@ -78,29 +76,29 @@ define <4 x half> @vfmin_vv_v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> %m, i
; ZVFH-LABEL: vfmin_vv_v4f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vmv1r.v v10, v0
+; ZVFH-NEXT: vmv1r.v v11, v0
; ZVFH-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0
+; ZVFH-NEXT: vmv1r.v v0, v11
; ZVFH-NEXT: vmfeq.vv v0, v9, v9, v0.t
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
-; ZVFH-NEXT: vfmin.vv v8, v8, v11, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v11
+; ZVFH-NEXT: vfmin.vv v8, v8, v10, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfmin_vv_v4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v11, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9, v0.t
-; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v11, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
-; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t
-; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v9, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v11
+; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v11
; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
@@ -123,16 +121,14 @@ define <4 x half> @vfmin_vv_v4f16_unmasked(<4 x half> %va, <4 x half> %vb, i32 z
; ZVFHMIN-LABEL: vfmin_vv_v4f16_unmasked:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFHMIN-NEXT: vfmin.vv v9, v8, v9
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
@@ -144,34 +140,33 @@ define <8 x half> @vfmin_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i
; ZVFH-LABEL: vfmin_vv_v8f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFH-NEXT: vmv1r.v v10, v0
+; ZVFH-NEXT: vmv1r.v v11, v0
; ZVFH-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0
+; ZVFH-NEXT: vmv1r.v v0, v11
; ZVFH-NEXT: vmfeq.vv v0, v9, v9, v0.t
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
-; ZVFH-NEXT: vfmin.vv v8, v8, v11, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v11
+; ZVFH-NEXT: vfmin.vv v8, v8, v10, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfmin_vv_v8f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v8, v14, v14, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v14, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v15, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v14, v12, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
-; ZVFHMIN-NEXT: vmfeq.vv v11, v12, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v11
-; ZVFHMIN-NEXT: vmerge.vvm v12, v12, v14, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
-; ZVFHMIN-NEXT: vfmin.vv v12, v12, v8, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v10, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v14
+; ZVFHMIN-NEXT: vmerge.vvm v10, v10, v12, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v15
+; ZVFHMIN-NEXT: vfmin.vv v10, v10, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: ret
%v = call <8 x half> @llvm.vp.minimum.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 %evl)
ret <8 x half> %v
@@ -191,15 +186,13 @@ define <8 x half> @vfmin_vv_v8f16_unmasked(<8 x half> %va, <8 x half> %vb, i32 z
; ZVFHMIN-LABEL: vfmin_vv_v8f16_unmasked:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v10, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
+; ZVFHMIN-NEXT: vmerge.vvm v10, v10, v12, v0
; ZVFHMIN-NEXT: vfmin.vv v10, v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
@@ -212,36 +205,34 @@ define <16 x half> @vfmin_vv_v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1>
; ZVFH-LABEL: vfmin_vv_v16f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vmv1r.v v12, v0
-; ZVFH-NEXT: vmfeq.vv v13, v8, v8, v0.t
-; ZVFH-NEXT: vmv1r.v v0, v13
-; ZVFH-NEXT: vmerge.vvm v14, v8, v10, v0
+; ZVFH-NEXT: vmfeq.vv v12, v8, v8, v0.t
+; ZVFH-NEXT: vmfeq.vv v14, v10, v10, v0.t
+; ZVFH-NEXT: vmv1r.v v15, v0
; ZVFH-NEXT: vmv1r.v v0, v12
-; ZVFH-NEXT: vmfeq.vv v13, v10, v10, v0.t
-; ZVFH-NEXT: vmv1r.v v0, v13
+; ZVFH-NEXT: vmerge.vvm v12, v8, v10, v0
+; ZVFH-NEXT: vmv1r.v v0, v14
; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v12
-; ZVFH-NEXT: vfmin.vv v8, v8, v14, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v15
+; ZVFH-NEXT: vfmin.vv v8, v8, v12, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfmin_vv_v16f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v12, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v8, v20, v20, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v16, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v20, v12, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v21, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v20, v16, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
-; ZVFHMIN-NEXT: vmfeq.vv v13, v16, v16, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v13
-; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v20, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
-; ZVFHMIN-NEXT: vfmin.vv v16, v16, v8, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v12, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v20
+; ZVFHMIN-NEXT: vmerge.vvm v12, v12, v16, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v21
+; ZVFHMIN-NEXT: vfmin.vv v12, v12, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
%v = call <16 x half> @llvm.vp.minimum.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> %m, i32 %evl)
ret <16 x half> %v
@@ -261,15 +252,13 @@ define <16 x half> @vfmin_vv_v16f16_unmasked(<16 x half> %va, <16 x half> %vb, i
; ZVFHMIN-LABEL: vfmin_vv_v16f16_unmasked:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
-; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v12, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
+; ZVFHMIN-NEXT: vmerge.vvm v12, v12, v16, v0
; ZVFHMIN-NEXT: vfmin.vv v12, v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
@@ -282,14 +271,14 @@ define <2 x float> @vfmin_vv_v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m
; CHECK-LABEL: vfmin_vv_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; CHECK-NEXT: vmerge.vvm v11, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vfmin.vv v8, v8, v11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vfmin.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%v = call <2 x float> @llvm.vp.minimum.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m, i32 %evl)
ret <2 x float> %v
@@ -313,14 +302,14 @@ define <4 x float> @vfmin_vv_v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m
; CHECK-LABEL: vfmin_vv_v4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; CHECK-NEXT: vmerge.vvm v11, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vfmin.vv v8, v8, v11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vfmin.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%v = call <4 x float> @llvm.vp.minimum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl)
ret <4 x float> %v
@@ -344,16 +333,15 @@ define <8 x float> @vfmin_vv_v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m
; CHECK-LABEL: vfmin_vv_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v12, v0
-; CHECK-NEXT: vmfeq.vv v13, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: vmerge.vvm v14, v8, v10, v0
+; CHECK-NEXT: vmfeq.vv v12, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v14, v10, v10, v0.t
+; CHECK-NEXT: vmv1r.v v15, v0
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vv v13, v10, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmerge.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vfmin.vv v8, v8, v14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v15
+; CHECK-NEXT: vfmin.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%v = call <8 x float> @llvm.vp.minimum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl)
ret <8 x float> %v
@@ -377,16 +365,15 @@ define <16 x float> @vfmin_vv_v16f32(<16 x float> %va, <16 x float> %vb, <16 x i
; CHECK-LABEL: vfmin_vv_v16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vmv1r.v v16, v0
-; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v17
-; CHECK-NEXT: vmerge.vvm v20, v8, v12, v0
+; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v20, v12, v12, v0.t
+; CHECK-NEXT: vmv1r.v v21, v0
; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vmfeq.vv v17, v12, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmerge.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vfmin.vv v8, v8, v20, v0.t
+; CHECK-NEXT: vmv1r.v v0, v21
+; CHECK-NEXT: vfmin.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret
%v = call <16 x float> @llvm.vp.minimum.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> %m, i32 %evl)
ret <16 x float> %v
@@ -410,14 +397,14 @@ define <2 x double> @vfmin_vv_v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1>
; CHECK-LABEL: vfmin_vv_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; CHECK-NEXT: vmerge.vvm v11, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vfmin.vv v8, v8, v11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vfmin.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%v = call <2 x double> @llvm.vp.minimum.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> %m, i32 %evl)
ret <2 x double> %v
@@ -441,16 +428,15 @@ define <4 x double> @vfmin_vv_v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1>
; CHECK-LABEL: vfmin_vv_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v12, v0
-; CHECK-NEXT: vmfeq.vv v13, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: vmerge.vvm v14, v8, v10, v0
+; CHECK-NEXT: vmfeq.vv v12, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v14, v10, v10, v0.t
+; CHECK-NEXT: vmv1r.v v15, v0
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vv v13, v10, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmerge.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vfmin.vv v8, v8, v14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v15
+; CHECK-NEXT: vfmin.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%v = call <4 x double> @llvm.vp.minimum.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> %m, i32 %evl)
ret <4 x double> %v
@@ -474,16 +460,15 @@ define <8 x double> @vfmin_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1>
; CHECK-LABEL: vfmin_vv_v8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vmv1r.v v16, v0
-; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v17
-; CHECK-NEXT: vmerge.vvm v20, v8, v12, v0
+; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v20, v12, v12, v0.t
+; CHECK-NEXT: vmv1r.v v21, v0
; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vmfeq.vv v17, v12, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmerge.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vfmin.vv v8, v8, v20, v0.t
+; CHECK-NEXT: vmv1r.v v0, v21
+; CHECK-NEXT: vfmin.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret
%v = call <8 x double> @llvm.vp.minimum.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 %evl)
ret <8 x double> %v
@@ -507,15 +492,14 @@ define <16 x double> @vfmin_vv_v16f64(<16 x double> %va, <16 x double> %vb, <16
; CHECK-LABEL: vfmin_vv_v16f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vmfeq.vv v24, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; CHECK-NEXT: vmv1r.v v6, v0
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmfeq.vv v6, v16, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vfmin.vv v8, v8, v24, v0.t
; CHECK-NEXT: ret
%v = call <16 x double> @llvm.vp.minimum.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> %m, i32 %evl)
@@ -527,9 +511,8 @@ define <16 x double> @vfmin_vv_v16f64_unmasked(<16 x double> %va, <16 x double>
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v16, v16
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: vfmin.vv v8, v8, v24
; CHECK-NEXT: ret
@@ -543,75 +526,140 @@ define <32 x double> @vfmin_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: li a3, 41
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v6, v0
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a1, a0, 128
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a1)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vle64.v v24, (a0)
+; CHECK-NEXT: vle64.v v16, (a0)
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a4, a3, 5
+; CHECK-NEXT: add a3, a4, a3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v7, v0, 2
+; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 5
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
; CHECK-NEXT: bltu a2, a1, .LBB24_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB24_2:
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v5, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v5
-; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmfeq.vv v5, v24, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v5
-; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vfmin.vv v8, v8, v16, v0.t
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: addi a0, a2, -16
-; CHECK-NEXT: sltu a1, a2, a0
-; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a3, a1, 5
+; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v24, v16, v16, v0.t
+; CHECK-NEXT: vmfeq.vv v24, v8, v8, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a3, a1, 5
+; CHECK-NEXT: add a1, a3, a1
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmfeq.vv v25, v16, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v7, v25
+; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: addi a1, a2, -16
+; CHECK-NEXT: sltu a2, a2, a1
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a1, a2, a1
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 5
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; CHECK-NEXT: vmfeq.vv v7, v8, v8, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmfeq.vv v6, v8, v8, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; CHECK-NEXT: vfmin.vv v16, v16, v24, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a2, a0, 5
+; CHECK-NEXT: add a0, a2, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0
+; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmfeq.vv v6, v8, v8, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a2, 24
+; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vfmin.vv v16, v16, v24, v0.t
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 5
+; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 24
+; CHECK-NEXT: li a1, 41
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
@@ -632,16 +680,13 @@ define <32 x double> @vfmin_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a1)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
@@ -659,30 +704,32 @@ define <32 x double> @vfmin_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
; CHECK-NEXT: vfmin.vv v8, v8, v16
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v7, v8, v8
; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
; CHECK-NEXT: vfmin.vv v16, v16, v24
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
index 0c2269ff55d79..2955aa7e2b2b4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll
@@ -16,16 +16,14 @@ define <2 x bfloat> @vfmin_v2bf16_vv(<2 x bfloat> %a, <2 x bfloat> %b) {
; ZVFBFMIN-LABEL: vfmin_v2bf16_vv:
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v9
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v9
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFBFMIN-NEXT: vfmin.vv v9, v8, v9
+; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFBFMIN-NEXT: vfmin.vv v9, v9, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
; ZVFBFMIN-NEXT: ret
@@ -47,16 +45,14 @@ define <4 x bfloat> @vfmin_v4bf16_vv(<4 x bfloat> %a, <4 x bfloat> %b) {
; ZVFBFMIN-LABEL: vfmin_v4bf16_vv:
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v9
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v9
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFBFMIN-NEXT: vfmin.vv v9, v8, v9
+; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFBFMIN-NEXT: vfmin.vv v9, v9, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
; ZVFBFMIN-NEXT: ret
@@ -78,15 +74,13 @@ define <8 x bfloat> @vfmin_v8bf16_vv(<8 x bfloat> %a, <8 x bfloat> %b) {
; ZVFBFMIN-LABEL: vfmin_v8bf16_vv:
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v9
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v9
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v10, v12, v0
; ZVFBFMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFBFMIN-NEXT: vmerge.vvm v10, v12, v10, v0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v12, v10, v0
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
+; ZVFBFMIN-NEXT: vmerge.vvm v10, v10, v12, v0
; ZVFBFMIN-NEXT: vfmin.vv v10, v10, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
@@ -109,15 +103,13 @@ define <16 x bfloat> @vfmin_v16bf16_vv(<16 x bfloat> %a, <16 x bfloat> %b) {
; ZVFBFMIN-LABEL: vfmin_v16bf16_vv:
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v10
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v10
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v12, v16, v0
; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
-; ZVFBFMIN-NEXT: vmerge.vvm v12, v16, v12, v0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v12, v0
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v12, v12
+; ZVFBFMIN-NEXT: vmerge.vvm v12, v12, v16, v0
; ZVFBFMIN-NEXT: vfmin.vv v12, v12, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
@@ -150,16 +142,14 @@ define <2 x half> @vfmin_v2f16_vv(<2 x half> %a, <2 x half> %b) {
; ZVFHMIN-LABEL: vfmin_v2f16_vv:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFHMIN-NEXT: vfmin.vv v9, v8, v9
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
@@ -181,16 +171,14 @@ define <4 x half> @vfmin_v4f16_vv(<4 x half> %a, <4 x half> %b) {
; ZVFHMIN-LABEL: vfmin_v4f16_vv:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFHMIN-NEXT: vfmin.vv v9, v8, v9
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
@@ -212,15 +200,13 @@ define <8 x half> @vfmin_v8f16_vv(<8 x half> %a, <8 x half> %b) {
; ZVFHMIN-LABEL: vfmin_v8f16_vv:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v10, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
+; ZVFHMIN-NEXT: vmerge.vvm v10, v10, v12, v0
; ZVFHMIN-NEXT: vfmin.vv v10, v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
@@ -243,15 +229,13 @@ define <16 x half> @vfmin_v16f16_vv(<16 x half> %a, <16 x half> %b) {
; ZVFHMIN-LABEL: vfmin_v16f16_vv:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
-; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v12, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
+; ZVFHMIN-NEXT: vmerge.vvm v12, v12, v16, v0
; ZVFHMIN-NEXT: vfmin.vv v12, v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
@@ -363,9 +347,8 @@ define <16 x double> @vfmin_v16f64_vv(<16 x double> %a, <16 x double> %b) nounwi
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v16, v16
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: vfmin.vv v8, v8, v24
; CHECK-NEXT: ret
@@ -469,8 +452,8 @@ define <4 x half> @vfmin_v2f16_vv_nnan_insert_subvector(<2 x half> %a, <2 x half
; ZVFH-NEXT: vfadd.vv v8, v8, v8
; ZVFH-NEXT: vfadd.vv v9, v9, v9
; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVFH-NEXT: vmfeq.vv v0, v10, v10
; ZVFH-NEXT: vslideup.vi v8, v9, 2
+; ZVFH-NEXT: vmfeq.vv v0, v10, v10
; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0
; ZVFH-NEXT: vfmin.vv v8, v8, v10
; ZVFH-NEXT: ret
@@ -480,20 +463,19 @@ define <4 x half> @vfmin_v2f16_vv_nnan_insert_subvector(<2 x half> %a, <2 x half
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfadd.vv v9, v11, v11
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfadd.vv v10, v11, v11
; ZVFHMIN-NEXT: vfadd.vv v8, v8, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v9
-; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v8
+; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v10
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vslideup.vi v11, v9, 2
+; ZVFHMIN-NEXT: vslideup.vi v11, v10, 2
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmerge.vvm v10, v8, v9, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
index 8485eb8ac1caa..549c901fb3e7f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
@@ -211,10 +211,10 @@ define <16 x float> @nearbyint_v16f32(<16 x float> %v) strictfp {
define <2 x double> @nearbyint_v2f64(<2 x double> %v) strictfp {
; RV32-LABEL: nearbyint_v2f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: lui a0, %hi(.LCPI9_0)
; RV32-NEXT: fld fa5, %lo(.LCPI9_0)(a0)
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
@@ -252,10 +252,10 @@ define <2 x double> @nearbyint_v2f64(<2 x double> %v) strictfp {
define <4 x double> @nearbyint_v4f64(<4 x double> %v) strictfp {
; RV32-LABEL: nearbyint_v4f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: lui a0, %hi(.LCPI10_0)
; RV32-NEXT: fld fa5, %lo(.LCPI10_0)(a0)
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
+; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: vmflt.vf v0, v10, fa5
@@ -293,10 +293,10 @@ define <4 x double> @nearbyint_v4f64(<4 x double> %v) strictfp {
define <8 x double> @nearbyint_v8f64(<8 x double> %v) strictfp {
; RV32-LABEL: nearbyint_v8f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: lui a0, %hi(.LCPI11_0)
; RV32-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
+; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v12, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
index 248ec1369076b..35b3d98cee01f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
@@ -39,10 +39,11 @@ define void @buildvec_no_vid_v4f32(ptr %x) {
define <4 x float> @hang_when_merging_stores_after_legalization(<8 x float> %x, <8 x float> %y) optsize {
; CHECK-LABEL: hang_when_merging_stores_after_legalization:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 4
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v12, v10, 4
; CHECK-NEXT: vslideup.vi v12, v10, 2, v0.t
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 2
@@ -1758,13 +1759,13 @@ define <8 x float> @buildvec_v8f32_zvl256(float %e0, float %e1, float %e2, float
; CHECK-NEXT: vsetivli zero, 8, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v8, fa4
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmv.v.i v0, 15
; CHECK-NEXT: vfslide1down.vf v8, v8, fa5
; CHECK-NEXT: vfslide1down.vf v9, v9, fa1
; CHECK-NEXT: vfslide1down.vf v8, v8, fa6
; CHECK-NEXT: vfslide1down.vf v9, v9, fa2
; CHECK-NEXT: vfslide1down.vf v8, v8, fa7
; CHECK-NEXT: vfslide1down.vf v9, v9, fa3
+; CHECK-NEXT: vmv.v.i v0, 15
; CHECK-NEXT: vslidedown.vi v8, v9, 4, v0.t
; CHECK-NEXT: ret
%v0 = insertelement <8 x float> poison, float %e0, i64 0
@@ -1809,13 +1810,13 @@ define <8 x double> @buildvec_v8f64_zvl512(double %e0, double %e1, double %e2, d
; CHECK-NEXT: vsetivli zero, 8, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v8, fa4
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmv.v.i v0, 15
; CHECK-NEXT: vfslide1down.vf v8, v8, fa5
; CHECK-NEXT: vfslide1down.vf v9, v9, fa1
; CHECK-NEXT: vfslide1down.vf v8, v8, fa6
; CHECK-NEXT: vfslide1down.vf v9, v9, fa2
; CHECK-NEXT: vfslide1down.vf v8, v8, fa7
; CHECK-NEXT: vfslide1down.vf v9, v9, fa3
+; CHECK-NEXT: vmv.v.i v0, 15
; CHECK-NEXT: vslidedown.vi v8, v9, 4, v0.t
; CHECK-NEXT: ret
%v0 = insertelement <8 x double> poison, double %e0, i64 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
index e256ba9dd5997..506c530e22a54 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
@@ -2624,12 +2624,13 @@ define void @fcmp_oeq_vf_v8f16_nonans(ptr %x, half %y, ptr %z) {
define void @fcmp_une_vf_v4f32(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_une_vf_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
@@ -2649,12 +2650,13 @@ define void @fcmp_une_vf_v4f32(ptr %x, float %y, ptr %z) {
define void @fcmp_une_vf_v4f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_une_vf_v4f32_nonans:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
@@ -2674,12 +2676,13 @@ define void @fcmp_une_vf_v4f32_nonans(ptr %x, float %y, ptr %z) {
define void @fcmp_ogt_vf_v2f64(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ogt_vf_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
@@ -2699,12 +2702,13 @@ define void @fcmp_ogt_vf_v2f64(ptr %x, double %y, ptr %z) {
define void @fcmp_ogt_vf_v2f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ogt_vf_v2f64_nonans:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vmfgt.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
@@ -4613,12 +4617,13 @@ define void @fcmp_oeq_fv_v8f16_nonans(ptr %x, half %y, ptr %z) {
define void @fcmp_une_fv_v4f32(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_une_fv_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
@@ -4638,12 +4643,13 @@ define void @fcmp_une_fv_v4f32(ptr %x, float %y, ptr %z) {
define void @fcmp_une_fv_v4f32_nonans(ptr %x, float %y, ptr %z) {
; CHECK-LABEL: fcmp_une_fv_v4f32_nonans:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vmfne.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
@@ -4663,12 +4669,13 @@ define void @fcmp_une_fv_v4f32_nonans(ptr %x, float %y, ptr %z) {
define void @fcmp_ogt_fv_v2f64(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ogt_fv_v2f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
@@ -4688,12 +4695,13 @@ define void @fcmp_ogt_fv_v2f64(ptr %x, double %y, ptr %z) {
define void @fcmp_ogt_fv_v2f64_nonans(ptr %x, double %y, ptr %z) {
; CHECK-LABEL: fcmp_ogt_fv_v2f64_nonans:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vmflt.vf v0, v8, fa0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
index dd415116c2327..591abb387b9eb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
@@ -3876,10 +3876,10 @@ define void @trunc_v8bf16(ptr %x) {
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: lui a1, 307200
-; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -3901,10 +3901,10 @@ define void @trunc_v6bf16(ptr %x) {
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: lui a1, 307200
-; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -3927,8 +3927,8 @@ define void @trunc_v8f16(ptr %x) {
; ZVFH-NEXT: vle16.v v8, (a0)
; ZVFH-NEXT: li a1, 25
; ZVFH-NEXT: slli a1, a1, 10
-; ZVFH-NEXT: fmv.h.x fa5, a1
; ZVFH-NEXT: vfabs.v v9, v8
+; ZVFH-NEXT: fmv.h.x fa5, a1
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -3942,10 +3942,10 @@ define void @trunc_v8f16(ptr %x) {
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vle16.v v10, (a0)
; ZVFHMIN-NEXT: lui a1, 307200
-; ZVFHMIN-NEXT: fmv.w.x fa5, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
+; ZVFHMIN-NEXT: fmv.w.x fa5, a1
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -3968,8 +3968,8 @@ define void @trunc_v6f16(ptr %x) {
; ZVFH-NEXT: vle16.v v8, (a0)
; ZVFH-NEXT: li a1, 25
; ZVFH-NEXT: slli a1, a1, 10
-; ZVFH-NEXT: fmv.h.x fa5, a1
; ZVFH-NEXT: vfabs.v v9, v8
+; ZVFH-NEXT: fmv.h.x fa5, a1
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -3983,10 +3983,10 @@ define void @trunc_v6f16(ptr %x) {
; ZVFHMIN-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; ZVFHMIN-NEXT: vle16.v v10, (a0)
; ZVFHMIN-NEXT: lui a1, 307200
-; ZVFHMIN-NEXT: fmv.w.x fa5, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
+; ZVFHMIN-NEXT: fmv.w.x fa5, a1
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -4008,8 +4008,8 @@ define void @trunc_v4f32(ptr %x) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a1, 307200
-; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4045,8 +4045,8 @@ define void @trunc_v2f64(ptr %x) {
; RV64ZVFH-NEXT: vle64.v v8, (a0)
; RV64ZVFH-NEXT: li a1, 1075
; RV64ZVFH-NEXT: slli a1, a1, 52
-; RV64ZVFH-NEXT: fmv.d.x fa5, a1
; RV64ZVFH-NEXT: vfabs.v v9, v8
+; RV64ZVFH-NEXT: fmv.d.x fa5, a1
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4076,8 +4076,8 @@ define void @trunc_v2f64(ptr %x) {
; RV64ZVFHMIN-NEXT: vle64.v v8, (a0)
; RV64ZVFHMIN-NEXT: li a1, 1075
; RV64ZVFHMIN-NEXT: slli a1, a1, 52
-; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a1
; RV64ZVFHMIN-NEXT: vfabs.v v9, v8
+; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a1
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4098,11 +4098,11 @@ define void @ceil_v8bf16(ptr %x) {
; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
+; CHECK-NEXT: fsrmi a1, 3
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
-; CHECK-NEXT: fsrmi a1, 3
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -4125,11 +4125,11 @@ define void @ceil_v6bf16(ptr %x) {
; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
+; CHECK-NEXT: fsrmi a1, 3
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
-; CHECK-NEXT: fsrmi a1, 3
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -4153,9 +4153,9 @@ define void @ceil_v8f16(ptr %x) {
; ZVFH-NEXT: li a1, 25
; ZVFH-NEXT: slli a1, a1, 10
; ZVFH-NEXT: fmv.h.x fa5, a1
+; ZVFH-NEXT: fsrmi a1, 3
; ZVFH-NEXT: vfabs.v v9, v8
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
-; ZVFH-NEXT: fsrmi a1, 3
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a1
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4170,11 +4170,11 @@ define void @ceil_v8f16(ptr %x) {
; ZVFHMIN-NEXT: vle16.v v10, (a0)
; ZVFHMIN-NEXT: lui a1, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
+; ZVFHMIN-NEXT: fsrmi a1, 3
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
-; ZVFHMIN-NEXT: fsrmi a1, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: fsrm a1
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -4198,9 +4198,9 @@ define void @ceil_v6f16(ptr %x) {
; ZVFH-NEXT: li a1, 25
; ZVFH-NEXT: slli a1, a1, 10
; ZVFH-NEXT: fmv.h.x fa5, a1
+; ZVFH-NEXT: fsrmi a1, 3
; ZVFH-NEXT: vfabs.v v9, v8
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
-; ZVFH-NEXT: fsrmi a1, 3
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a1
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4215,11 +4215,11 @@ define void @ceil_v6f16(ptr %x) {
; ZVFHMIN-NEXT: vle16.v v10, (a0)
; ZVFHMIN-NEXT: lui a1, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
+; ZVFHMIN-NEXT: fsrmi a1, 3
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
-; ZVFHMIN-NEXT: fsrmi a1, 3
; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: fsrm a1
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -4242,9 +4242,9 @@ define void @ceil_v4f32(ptr %x) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
+; CHECK-NEXT: fsrmi a1, 3
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a1, 3
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4265,9 +4265,9 @@ define void @ceil_v2f64(ptr %x) {
; RV32ZVFH-NEXT: vle64.v v8, (a0)
; RV32ZVFH-NEXT: lui a1, %hi(.LCPI180_0)
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI180_0)(a1)
+; RV32ZVFH-NEXT: fsrmi a1, 3
; RV32ZVFH-NEXT: vfabs.v v9, v8
; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
-; RV32ZVFH-NEXT: fsrmi a1, 3
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a1
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4283,9 +4283,9 @@ define void @ceil_v2f64(ptr %x) {
; RV64ZVFH-NEXT: li a1, 1075
; RV64ZVFH-NEXT: slli a1, a1, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a1
+; RV64ZVFH-NEXT: fsrmi a1, 3
; RV64ZVFH-NEXT: vfabs.v v9, v8
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
-; RV64ZVFH-NEXT: fsrmi a1, 3
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a1
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4300,9 +4300,9 @@ define void @ceil_v2f64(ptr %x) {
; RV32ZVFHMIN-NEXT: vle64.v v8, (a0)
; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI180_0)
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI180_0)(a1)
+; RV32ZVFHMIN-NEXT: fsrmi a1, 3
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
-; RV32ZVFHMIN-NEXT: fsrmi a1, 3
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a1
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4318,9 +4318,9 @@ define void @ceil_v2f64(ptr %x) {
; RV64ZVFHMIN-NEXT: li a1, 1075
; RV64ZVFHMIN-NEXT: slli a1, a1, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a1
+; RV64ZVFHMIN-NEXT: fsrmi a1, 3
; RV64ZVFHMIN-NEXT: vfabs.v v9, v8
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
-; RV64ZVFHMIN-NEXT: fsrmi a1, 3
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a1
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4341,11 +4341,11 @@ define void @floor_v8bf16(ptr %x) {
; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
+; CHECK-NEXT: fsrmi a1, 2
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
-; CHECK-NEXT: fsrmi a1, 2
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -4368,11 +4368,11 @@ define void @floor_v6bf16(ptr %x) {
; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
+; CHECK-NEXT: fsrmi a1, 2
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
-; CHECK-NEXT: fsrmi a1, 2
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -4396,9 +4396,9 @@ define void @floor_v8f16(ptr %x) {
; ZVFH-NEXT: li a1, 25
; ZVFH-NEXT: slli a1, a1, 10
; ZVFH-NEXT: fmv.h.x fa5, a1
+; ZVFH-NEXT: fsrmi a1, 2
; ZVFH-NEXT: vfabs.v v9, v8
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
-; ZVFH-NEXT: fsrmi a1, 2
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a1
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4413,11 +4413,11 @@ define void @floor_v8f16(ptr %x) {
; ZVFHMIN-NEXT: vle16.v v10, (a0)
; ZVFHMIN-NEXT: lui a1, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
+; ZVFHMIN-NEXT: fsrmi a1, 2
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
-; ZVFHMIN-NEXT: fsrmi a1, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: fsrm a1
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -4441,9 +4441,9 @@ define void @floor_v6f16(ptr %x) {
; ZVFH-NEXT: li a1, 25
; ZVFH-NEXT: slli a1, a1, 10
; ZVFH-NEXT: fmv.h.x fa5, a1
+; ZVFH-NEXT: fsrmi a1, 2
; ZVFH-NEXT: vfabs.v v9, v8
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
-; ZVFH-NEXT: fsrmi a1, 2
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a1
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4458,11 +4458,11 @@ define void @floor_v6f16(ptr %x) {
; ZVFHMIN-NEXT: vle16.v v10, (a0)
; ZVFHMIN-NEXT: lui a1, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
+; ZVFHMIN-NEXT: fsrmi a1, 2
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
-; ZVFHMIN-NEXT: fsrmi a1, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: fsrm a1
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -4485,9 +4485,9 @@ define void @floor_v4f32(ptr %x) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
+; CHECK-NEXT: fsrmi a1, 2
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a1, 2
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4508,9 +4508,9 @@ define void @floor_v2f64(ptr %x) {
; RV32ZVFH-NEXT: vle64.v v8, (a0)
; RV32ZVFH-NEXT: lui a1, %hi(.LCPI186_0)
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI186_0)(a1)
+; RV32ZVFH-NEXT: fsrmi a1, 2
; RV32ZVFH-NEXT: vfabs.v v9, v8
; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
-; RV32ZVFH-NEXT: fsrmi a1, 2
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a1
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4526,9 +4526,9 @@ define void @floor_v2f64(ptr %x) {
; RV64ZVFH-NEXT: li a1, 1075
; RV64ZVFH-NEXT: slli a1, a1, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a1
+; RV64ZVFH-NEXT: fsrmi a1, 2
; RV64ZVFH-NEXT: vfabs.v v9, v8
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
-; RV64ZVFH-NEXT: fsrmi a1, 2
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a1
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4543,9 +4543,9 @@ define void @floor_v2f64(ptr %x) {
; RV32ZVFHMIN-NEXT: vle64.v v8, (a0)
; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI186_0)
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI186_0)(a1)
+; RV32ZVFHMIN-NEXT: fsrmi a1, 2
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
-; RV32ZVFHMIN-NEXT: fsrmi a1, 2
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a1
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4561,9 +4561,9 @@ define void @floor_v2f64(ptr %x) {
; RV64ZVFHMIN-NEXT: li a1, 1075
; RV64ZVFHMIN-NEXT: slli a1, a1, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a1
+; RV64ZVFHMIN-NEXT: fsrmi a1, 2
; RV64ZVFHMIN-NEXT: vfabs.v v9, v8
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
-; RV64ZVFHMIN-NEXT: fsrmi a1, 2
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a1
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4584,11 +4584,11 @@ define void @round_v8bf16(ptr %x) {
; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
+; CHECK-NEXT: fsrmi a1, 4
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
-; CHECK-NEXT: fsrmi a1, 4
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -4611,11 +4611,11 @@ define void @round_v6bf16(ptr %x) {
; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
+; CHECK-NEXT: fsrmi a1, 4
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
-; CHECK-NEXT: fsrmi a1, 4
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -4639,9 +4639,9 @@ define void @round_v8f16(ptr %x) {
; ZVFH-NEXT: li a1, 25
; ZVFH-NEXT: slli a1, a1, 10
; ZVFH-NEXT: fmv.h.x fa5, a1
+; ZVFH-NEXT: fsrmi a1, 4
; ZVFH-NEXT: vfabs.v v9, v8
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
-; ZVFH-NEXT: fsrmi a1, 4
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a1
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4656,11 +4656,11 @@ define void @round_v8f16(ptr %x) {
; ZVFHMIN-NEXT: vle16.v v10, (a0)
; ZVFHMIN-NEXT: lui a1, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
+; ZVFHMIN-NEXT: fsrmi a1, 4
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
-; ZVFHMIN-NEXT: fsrmi a1, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: fsrm a1
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -4684,9 +4684,9 @@ define void @round_v6f16(ptr %x) {
; ZVFH-NEXT: li a1, 25
; ZVFH-NEXT: slli a1, a1, 10
; ZVFH-NEXT: fmv.h.x fa5, a1
+; ZVFH-NEXT: fsrmi a1, 4
; ZVFH-NEXT: vfabs.v v9, v8
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
-; ZVFH-NEXT: fsrmi a1, 4
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a1
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4701,11 +4701,11 @@ define void @round_v6f16(ptr %x) {
; ZVFHMIN-NEXT: vle16.v v10, (a0)
; ZVFHMIN-NEXT: lui a1, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
+; ZVFHMIN-NEXT: fsrmi a1, 4
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
-; ZVFHMIN-NEXT: fsrmi a1, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: fsrm a1
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -4728,9 +4728,9 @@ define void @round_v4f32(ptr %x) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
+; CHECK-NEXT: fsrmi a1, 4
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a1, 4
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4751,9 +4751,9 @@ define void @round_v2f64(ptr %x) {
; RV32ZVFH-NEXT: vle64.v v8, (a0)
; RV32ZVFH-NEXT: lui a1, %hi(.LCPI192_0)
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI192_0)(a1)
+; RV32ZVFH-NEXT: fsrmi a1, 4
; RV32ZVFH-NEXT: vfabs.v v9, v8
; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
-; RV32ZVFH-NEXT: fsrmi a1, 4
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a1
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4769,9 +4769,9 @@ define void @round_v2f64(ptr %x) {
; RV64ZVFH-NEXT: li a1, 1075
; RV64ZVFH-NEXT: slli a1, a1, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a1
+; RV64ZVFH-NEXT: fsrmi a1, 4
; RV64ZVFH-NEXT: vfabs.v v9, v8
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
-; RV64ZVFH-NEXT: fsrmi a1, 4
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a1
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4786,9 +4786,9 @@ define void @round_v2f64(ptr %x) {
; RV32ZVFHMIN-NEXT: vle64.v v8, (a0)
; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI192_0)
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI192_0)(a1)
+; RV32ZVFHMIN-NEXT: fsrmi a1, 4
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
-; RV32ZVFHMIN-NEXT: fsrmi a1, 4
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a1
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4804,9 +4804,9 @@ define void @round_v2f64(ptr %x) {
; RV64ZVFHMIN-NEXT: li a1, 1075
; RV64ZVFHMIN-NEXT: slli a1, a1, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a1
+; RV64ZVFHMIN-NEXT: fsrmi a1, 4
; RV64ZVFHMIN-NEXT: vfabs.v v9, v8
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
-; RV64ZVFHMIN-NEXT: fsrmi a1, 4
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a1
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4826,10 +4826,10 @@ define void @rint_v8bf16(ptr %x) {
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: lui a1, 307200
-; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -4852,8 +4852,8 @@ define void @rint_v8f16(ptr %x) {
; ZVFH-NEXT: vle16.v v8, (a0)
; ZVFH-NEXT: li a1, 25
; ZVFH-NEXT: slli a1, a1, 10
-; ZVFH-NEXT: fmv.h.x fa5, a1
; ZVFH-NEXT: vfabs.v v9, v8
+; ZVFH-NEXT: fmv.h.x fa5, a1
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4867,10 +4867,10 @@ define void @rint_v8f16(ptr %x) {
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vle16.v v10, (a0)
; ZVFHMIN-NEXT: lui a1, 307200
-; ZVFHMIN-NEXT: fmv.w.x fa5, a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
+; ZVFHMIN-NEXT: fmv.w.x fa5, a1
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -4892,8 +4892,8 @@ define void @rint_v4f32(ptr %x) {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a1, 307200
-; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: fmv.w.x fa5, a1
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4929,8 +4929,8 @@ define void @rint_v2f64(ptr %x) {
; RV64ZVFH-NEXT: vle64.v v8, (a0)
; RV64ZVFH-NEXT: li a1, 1075
; RV64ZVFH-NEXT: slli a1, a1, 52
-; RV64ZVFH-NEXT: fmv.d.x fa5, a1
; RV64ZVFH-NEXT: vfabs.v v9, v8
+; RV64ZVFH-NEXT: fmv.d.x fa5, a1
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4960,8 +4960,8 @@ define void @rint_v2f64(ptr %x) {
; RV64ZVFHMIN-NEXT: vle64.v v8, (a0)
; RV64ZVFHMIN-NEXT: li a1, 1075
; RV64ZVFHMIN-NEXT: slli a1, a1, 52
-; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a1
; RV64ZVFHMIN-NEXT: vfabs.v v9, v8
+; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a1
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -4982,11 +4982,11 @@ define void @nearbyint_v8bf16(ptr %x) {
; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
+; CHECK-NEXT: frflags a1
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
-; CHECK-NEXT: frflags a1
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
; CHECK-NEXT: fsflags a1
@@ -5010,9 +5010,9 @@ define void @nearbyint_v8f16(ptr %x) {
; ZVFH-NEXT: li a1, 25
; ZVFH-NEXT: slli a1, a1, 10
; ZVFH-NEXT: fmv.h.x fa5, a1
+; ZVFH-NEXT: frflags a1
; ZVFH-NEXT: vfabs.v v9, v8
; ZVFH-NEXT: vmflt.vf v0, v9, fa5
-; ZVFH-NEXT: frflags a1
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
; ZVFH-NEXT: fsflags a1
@@ -5027,11 +5027,11 @@ define void @nearbyint_v8f16(ptr %x) {
; ZVFHMIN-NEXT: vle16.v v10, (a0)
; ZVFHMIN-NEXT: lui a1, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a1
+; ZVFHMIN-NEXT: frflags a1
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v10, v8
; ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
-; ZVFHMIN-NEXT: frflags a1
; ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
; ZVFHMIN-NEXT: fsflags a1
@@ -5054,9 +5054,9 @@ define void @nearbyint_v4f32(ptr %x) {
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a1, 307200
; CHECK-NEXT: fmv.w.x fa5, a1
+; CHECK-NEXT: frflags a1
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: frflags a1
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: fsflags a1
@@ -5077,9 +5077,9 @@ define void @nearbyint_v2f64(ptr %x) {
; RV32ZVFH-NEXT: vle64.v v8, (a0)
; RV32ZVFH-NEXT: lui a1, %hi(.LCPI200_0)
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI200_0)(a1)
+; RV32ZVFH-NEXT: frflags a1
; RV32ZVFH-NEXT: vfabs.v v9, v8
; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
-; RV32ZVFH-NEXT: frflags a1
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
; RV32ZVFH-NEXT: fsflags a1
@@ -5095,9 +5095,9 @@ define void @nearbyint_v2f64(ptr %x) {
; RV64ZVFH-NEXT: li a1, 1075
; RV64ZVFH-NEXT: slli a1, a1, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a1
+; RV64ZVFH-NEXT: frflags a1
; RV64ZVFH-NEXT: vfabs.v v9, v8
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
-; RV64ZVFH-NEXT: frflags a1
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
; RV64ZVFH-NEXT: fsflags a1
@@ -5112,9 +5112,9 @@ define void @nearbyint_v2f64(ptr %x) {
; RV32ZVFHMIN-NEXT: vle64.v v8, (a0)
; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI200_0)
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI200_0)(a1)
+; RV32ZVFHMIN-NEXT: frflags a1
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
-; RV32ZVFHMIN-NEXT: frflags a1
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
; RV32ZVFHMIN-NEXT: fsflags a1
@@ -5130,9 +5130,9 @@ define void @nearbyint_v2f64(ptr %x) {
; RV64ZVFHMIN-NEXT: li a1, 1075
; RV64ZVFHMIN-NEXT: slli a1, a1, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a1
+; RV64ZVFHMIN-NEXT: frflags a1
; RV64ZVFHMIN-NEXT: vfabs.v v9, v8
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
-; RV64ZVFHMIN-NEXT: frflags a1
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
; RV64ZVFHMIN-NEXT: fsflags a1
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
index 465b166826a37..135088631abac 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
@@ -88,25 +88,24 @@ define <32 x double> @vfpext_v32f32_v32f64(<32 x float> %a, <32 x i1> %m, i32 ze
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: vslidedown.vi v16, v0, 2
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB7_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; CHECK-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; CHECK-NEXT: vfwcvt.f.f.v v24, v8, v0.t
; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 16
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vfwcvt.f.f.v v24, v8, v0.t
-; CHECK-NEXT: vmv8r.v v8, v16
-; CHECK-NEXT: vmv8r.v v16, v24
+; CHECK-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret
%v = call <32 x double> @llvm.vp.fpext.v32f64.v32f32(<32 x float> %a, <32 x i1> %m, i32 %vl)
ret <32 x double> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
index ad56aee72a432..8a8b7bcd94854 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll
@@ -14,10 +14,10 @@ define <1 x half> @round_v1f16(<1 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -37,10 +37,10 @@ define <2 x half> @round_v2f16(<2 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -60,10 +60,10 @@ define <4 x half> @round_v4f16(<4 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -83,10 +83,10 @@ define <8 x half> @round_v8f16(<8 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -106,10 +106,10 @@ define <16 x half> @round_v16f16(<16 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -131,9 +131,9 @@ define <32 x half> @round_v32f16(<32 x half> %x) strictfp {
; CHECK-NEXT: slli a1, a1, 10
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.h.x fa5, a1
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -153,9 +153,9 @@ define <1 x float> @round_v1f32(<1 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -175,9 +175,9 @@ define <2 x float> @round_v2f32(<2 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -197,9 +197,9 @@ define <4 x float> @round_v4f32(<4 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -219,9 +219,9 @@ define <8 x float> @round_v8f32(<8 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -241,9 +241,9 @@ define <16 x float> @round_v16f32(<16 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -263,9 +263,9 @@ define <1 x double> @round_v1f64(<1 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI11_0)
; RV32-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 4
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: fsrmi a0, 4
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -281,10 +281,10 @@ define <1 x double> @round_v1f64(<1 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v9, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 4
+; RV64-NEXT: vfabs.v v9, v8
+; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -304,9 +304,9 @@ define <2 x double> @round_v2f64(<2 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 4
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: fsrmi a0, 4
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -322,10 +322,10 @@ define <2 x double> @round_v2f64(<2 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v9, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 4
+; RV64-NEXT: vfabs.v v9, v8
+; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -345,9 +345,9 @@ define <4 x double> @round_v4f64(<4 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 4
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: vmflt.vf v0, v10, fa5
-; RV32-NEXT: fsrmi a0, 4
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -363,10 +363,10 @@ define <4 x double> @round_v4f64(<4 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v10, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: fsrmi a0, 4
+; RV64-NEXT: vfabs.v v10, v8
+; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -386,9 +386,9 @@ define <8 x double> @round_v8f64(<8 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI14_0)
; RV32-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 4
; RV32-NEXT: vfabs.v v12, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
-; RV32-NEXT: fsrmi a0, 4
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -404,10 +404,10 @@ define <8 x double> @round_v8f64(<8 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v12, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 4
+; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: fsrm a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
index 4c6d420767ebf..878e7f28c4ee0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
@@ -18,8 +18,8 @@ define <1 x half> @round_v1f16(<1 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -32,11 +32,11 @@ define <1 x half> @round_v1f16(<1 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -57,8 +57,8 @@ define <2 x half> @round_v2f16(<2 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -71,11 +71,11 @@ define <2 x half> @round_v2f16(<2 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -96,8 +96,8 @@ define <4 x half> @round_v4f16(<4 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -110,11 +110,11 @@ define <4 x half> @round_v4f16(<4 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -135,8 +135,8 @@ define <8 x half> @round_v8f16(<8 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -149,11 +149,11 @@ define <8 x half> @round_v8f16(<8 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -174,8 +174,8 @@ define <16 x half> @round_v16f16(<16 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -188,11 +188,11 @@ define <16 x half> @round_v16f16(<16 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -210,14 +210,14 @@ define <32 x half> @round_v32f16(<32 x half> %x) {
; ZVFH: # %bb.0:
; ZVFH-NEXT: li a0, 32
; ZVFH-NEXT: li a1, 25
-; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8
; ZVFH-NEXT: slli a1, a1, 10
; ZVFH-NEXT: fmv.h.x fa5, a1
+; ZVFH-NEXT: fsrmi a1, 4
+; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFH-NEXT: vfabs.v v12, v8
; ZVFH-NEXT: vmflt.vf v0, v12, fa5
-; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
-; ZVFH-NEXT: fsrm a0
+; ZVFH-NEXT: fsrm a1
; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t
@@ -227,15 +227,15 @@ define <32 x half> @round_v32f16(<32 x half> %x) {
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: li a0, 32
; ZVFHMIN-NEXT: lui a1, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a1
+; ZVFHMIN-NEXT: fsrmi a1, 4
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
-; ZVFHMIN-NEXT: fmv.w.x fa5, a1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v16
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
-; ZVFHMIN-NEXT: fsrm a0
+; ZVFHMIN-NEXT: fsrm a1
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t
@@ -253,8 +253,8 @@ define <1 x float> @round_v1f32(<1 x float> %x) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -272,8 +272,8 @@ define <2 x float> @round_v2f32(<2 x float> %x) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -291,8 +291,8 @@ define <4 x float> @round_v4f32(<4 x float> %x) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -310,8 +310,8 @@ define <8 x float> @round_v8f32(<8 x float> %x) {
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -329,8 +329,8 @@ define <16 x float> @round_v16f32(<16 x float> %x) {
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -348,8 +348,8 @@ define <1 x double> @round_v1f64(<1 x double> %x) {
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
; RV32ZVFH-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -364,8 +364,8 @@ define <1 x double> @round_v1f64(<1 x double> %x) {
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -379,8 +379,8 @@ define <1 x double> @round_v1f64(<1 x double> %x) {
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
; RV32ZVFHMIN-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -395,8 +395,8 @@ define <1 x double> @round_v1f64(<1 x double> %x) {
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -414,8 +414,8 @@ define <2 x double> @round_v2f64(<2 x double> %x) {
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; RV32ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -430,8 +430,8 @@ define <2 x double> @round_v2f64(<2 x double> %x) {
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -445,8 +445,8 @@ define <2 x double> @round_v2f64(<2 x double> %x) {
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -461,8 +461,8 @@ define <2 x double> @round_v2f64(<2 x double> %x) {
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -480,8 +480,8 @@ define <4 x double> @round_v4f64(<4 x double> %x) {
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; RV32ZVFH-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32ZVFH-NEXT: vfabs.v v10, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -496,8 +496,8 @@ define <4 x double> @round_v4f64(<4 x double> %x) {
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -511,8 +511,8 @@ define <4 x double> @round_v4f64(<4 x double> %x) {
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; RV32ZVFHMIN-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v10, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -527,8 +527,8 @@ define <4 x double> @round_v4f64(<4 x double> %x) {
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -546,8 +546,8 @@ define <8 x double> @round_v8f64(<8 x double> %x) {
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; RV32ZVFH-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32ZVFH-NEXT: vfabs.v v12, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -562,8 +562,8 @@ define <8 x double> @round_v8f64(<8 x double> %x) {
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -577,8 +577,8 @@ define <8 x double> @round_v8f64(<8 x double> %x) {
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; RV32ZVFHMIN-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v12, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -593,8 +593,8 @@ define <8 x double> @round_v8f64(<8 x double> %x) {
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
index 5e5c64fd891fd..49c7c0703d2ce 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
@@ -14,10 +14,10 @@ define <1 x half> @roundeven_v1f16(<1 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -37,10 +37,10 @@ define <2 x half> @roundeven_v2f16(<2 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -60,10 +60,10 @@ define <4 x half> @roundeven_v4f16(<4 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -83,10 +83,10 @@ define <8 x half> @roundeven_v8f16(<8 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -106,10 +106,10 @@ define <16 x half> @roundeven_v16f16(<16 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -131,9 +131,9 @@ define <32 x half> @roundeven_v32f16(<32 x half> %x) strictfp {
; CHECK-NEXT: slli a1, a1, 10
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.h.x fa5, a1
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -153,9 +153,9 @@ define <1 x float> @roundeven_v1f32(<1 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -175,9 +175,9 @@ define <2 x float> @roundeven_v2f32(<2 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -197,9 +197,9 @@ define <4 x float> @roundeven_v4f32(<4 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -219,9 +219,9 @@ define <8 x float> @roundeven_v8f32(<8 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -241,9 +241,9 @@ define <16 x float> @roundeven_v16f32(<16 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -263,9 +263,9 @@ define <1 x double> @roundeven_v1f64(<1 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI11_0)
; RV32-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 0
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: fsrmi a0, 0
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -281,10 +281,10 @@ define <1 x double> @roundeven_v1f64(<1 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v9, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 0
+; RV64-NEXT: vfabs.v v9, v8
+; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -304,9 +304,9 @@ define <2 x double> @roundeven_v2f64(<2 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 0
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: fsrmi a0, 0
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -322,10 +322,10 @@ define <2 x double> @roundeven_v2f64(<2 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v9, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 0
+; RV64-NEXT: vfabs.v v9, v8
+; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -345,9 +345,9 @@ define <4 x double> @roundeven_v4f64(<4 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 0
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: vmflt.vf v0, v10, fa5
-; RV32-NEXT: fsrmi a0, 0
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -363,10 +363,10 @@ define <4 x double> @roundeven_v4f64(<4 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v10, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: fsrmi a0, 0
+; RV64-NEXT: vfabs.v v10, v8
+; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -386,9 +386,9 @@ define <8 x double> @roundeven_v8f64(<8 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI14_0)
; RV32-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 0
; RV32-NEXT: vfabs.v v12, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
-; RV32-NEXT: fsrmi a0, 0
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -404,10 +404,10 @@ define <8 x double> @roundeven_v8f64(<8 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v12, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 0
+; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: fsrm a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
index b175549c132b4..c62bb24daf521 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
@@ -18,8 +18,8 @@ define <1 x half> @roundeven_v1f16(<1 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -32,11 +32,11 @@ define <1 x half> @roundeven_v1f16(<1 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -57,8 +57,8 @@ define <2 x half> @roundeven_v2f16(<2 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -71,11 +71,11 @@ define <2 x half> @roundeven_v2f16(<2 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -96,8 +96,8 @@ define <4 x half> @roundeven_v4f16(<4 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -110,11 +110,11 @@ define <4 x half> @roundeven_v4f16(<4 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -135,8 +135,8 @@ define <8 x half> @roundeven_v8f16(<8 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -149,11 +149,11 @@ define <8 x half> @roundeven_v8f16(<8 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -174,8 +174,8 @@ define <16 x half> @roundeven_v16f16(<16 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -188,11 +188,11 @@ define <16 x half> @roundeven_v16f16(<16 x half> %x) {
; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -210,14 +210,14 @@ define <32 x half> @roundeven_v32f16(<32 x half> %x) {
; ZVFH: # %bb.0:
; ZVFH-NEXT: li a0, 32
; ZVFH-NEXT: li a1, 25
-; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfabs.v v12, v8
; ZVFH-NEXT: slli a1, a1, 10
; ZVFH-NEXT: fmv.h.x fa5, a1
+; ZVFH-NEXT: fsrmi a1, 0
+; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFH-NEXT: vfabs.v v12, v8
; ZVFH-NEXT: vmflt.vf v0, v12, fa5
-; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
-; ZVFH-NEXT: fsrm a0
+; ZVFH-NEXT: fsrm a1
; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu
; ZVFH-NEXT: vfsgnj.vv v8, v12, v8, v0.t
@@ -227,15 +227,15 @@ define <32 x half> @roundeven_v32f16(<32 x half> %x) {
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: li a0, 32
; ZVFHMIN-NEXT: lui a1, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a1
+; ZVFHMIN-NEXT: fsrmi a1, 0
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
-; ZVFHMIN-NEXT: fmv.w.x fa5, a1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v16
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
-; ZVFHMIN-NEXT: fsrm a0
+; ZVFHMIN-NEXT: fsrm a1
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t
@@ -253,8 +253,8 @@ define <1 x float> @roundeven_v1f32(<1 x float> %x) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -272,8 +272,8 @@ define <2 x float> @roundeven_v2f32(<2 x float> %x) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -291,8 +291,8 @@ define <4 x float> @roundeven_v4f32(<4 x float> %x) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -310,8 +310,8 @@ define <8 x float> @roundeven_v8f32(<8 x float> %x) {
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -329,8 +329,8 @@ define <16 x float> @roundeven_v16f32(<16 x float> %x) {
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -348,8 +348,8 @@ define <1 x double> @roundeven_v1f64(<1 x double> %x) {
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
; RV32ZVFH-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -364,8 +364,8 @@ define <1 x double> @roundeven_v1f64(<1 x double> %x) {
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -379,8 +379,8 @@ define <1 x double> @roundeven_v1f64(<1 x double> %x) {
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
; RV32ZVFHMIN-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -395,8 +395,8 @@ define <1 x double> @roundeven_v1f64(<1 x double> %x) {
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -414,8 +414,8 @@ define <2 x double> @roundeven_v2f64(<2 x double> %x) {
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; RV32ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -430,8 +430,8 @@ define <2 x double> @roundeven_v2f64(<2 x double> %x) {
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -445,8 +445,8 @@ define <2 x double> @roundeven_v2f64(<2 x double> %x) {
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -461,8 +461,8 @@ define <2 x double> @roundeven_v2f64(<2 x double> %x) {
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -480,8 +480,8 @@ define <4 x double> @roundeven_v4f64(<4 x double> %x) {
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; RV32ZVFH-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32ZVFH-NEXT: vfabs.v v10, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -496,8 +496,8 @@ define <4 x double> @roundeven_v4f64(<4 x double> %x) {
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -511,8 +511,8 @@ define <4 x double> @roundeven_v4f64(<4 x double> %x) {
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; RV32ZVFHMIN-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v10, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -527,8 +527,8 @@ define <4 x double> @roundeven_v4f64(<4 x double> %x) {
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -546,8 +546,8 @@ define <8 x double> @roundeven_v8f64(<8 x double> %x) {
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; RV32ZVFH-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32ZVFH-NEXT: vfabs.v v12, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -562,8 +562,8 @@ define <8 x double> @roundeven_v8f64(<8 x double> %x) {
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -577,8 +577,8 @@ define <8 x double> @roundeven_v8f64(<8 x double> %x) {
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; RV32ZVFHMIN-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v12, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -593,8 +593,8 @@ define <8 x double> @roundeven_v8f64(<8 x double> %x) {
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
index da04b08aa5db5..5f718cd422630 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll
@@ -8,9 +8,9 @@ define <2 x i8> @fshr_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i1> %m, i
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vand.vi v11, v11, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -24,9 +24,9 @@ define <2 x i8> @fshl_v2i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i1> %m, i
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vand.vi v11, v11, 7, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -40,9 +40,9 @@ define <4 x i8> @fshr_v4i8(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c, <4 x i1> %m, i
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vand.vi v11, v11, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -56,9 +56,9 @@ define <4 x i8> @fshl_v4i8(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c, <4 x i1> %m, i
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vand.vi v11, v11, 7, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -72,9 +72,9 @@ define <8 x i8> @fshr_v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i1> %m, i
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vand.vi v11, v11, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -88,9 +88,9 @@ define <8 x i8> @fshl_v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i1> %m, i
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vand.vi v11, v11, 7, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -104,9 +104,9 @@ define <16 x i8> @fshr_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i1>
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vand.vi v11, v11, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -120,9 +120,9 @@ define <16 x i8> @fshl_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i1>
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vand.vi v11, v11, 7, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -136,9 +136,9 @@ define <32 x i8> @fshr_v32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %c, <32 x i1>
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v14, v12, v0.t
+; CHECK-NEXT: vand.vi v12, v12, 7, v0.t
; CHECK-NEXT: vand.vi v14, v14, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
-; CHECK-NEXT: vand.vi v12, v12, 7, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
@@ -152,9 +152,9 @@ define <32 x i8> @fshl_v32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %c, <32 x i1>
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t
; CHECK-NEXT: vnot.v v14, v12, v0.t
+; CHECK-NEXT: vand.vi v12, v12, 7, v0.t
; CHECK-NEXT: vand.vi v14, v14, 7, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
-; CHECK-NEXT: vand.vi v12, v12, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
@@ -168,9 +168,9 @@ define <64 x i8> @fshr_v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %c, <64 x i1>
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v20, v16, v0.t
+; CHECK-NEXT: vand.vi v16, v16, 7, v0.t
; CHECK-NEXT: vand.vi v20, v20, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
-; CHECK-NEXT: vand.vi v16, v16, 7, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
@@ -184,9 +184,9 @@ define <64 x i8> @fshl_v64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %c, <64 x i1>
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t
; CHECK-NEXT: vnot.v v20, v16, v0.t
+; CHECK-NEXT: vand.vi v16, v16, 7, v0.t
; CHECK-NEXT: vand.vi v20, v20, 7, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
-; CHECK-NEXT: vand.vi v16, v16, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
@@ -200,9 +200,9 @@ define <2 x i16> @fshr_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i1>
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vand.vi v11, v11, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -216,9 +216,9 @@ define <2 x i16> @fshl_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i1>
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vand.vi v11, v11, 15, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -232,9 +232,9 @@ define <4 x i16> @fshr_v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i1>
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vand.vi v11, v11, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -248,9 +248,9 @@ define <4 x i16> @fshl_v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i1>
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vand.vi v11, v11, 15, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -264,9 +264,9 @@ define <8 x i16> @fshr_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i1>
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vand.vi v11, v11, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -280,9 +280,9 @@ define <8 x i16> @fshl_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i1>
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vand.vi v11, v11, 15, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -296,9 +296,9 @@ define <16 x i16> @fshr_v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c, <16
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v14, v12, v0.t
+; CHECK-NEXT: vand.vi v12, v12, 15, v0.t
; CHECK-NEXT: vand.vi v14, v14, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
-; CHECK-NEXT: vand.vi v12, v12, 15, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
@@ -312,9 +312,9 @@ define <16 x i16> @fshl_v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c, <16
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t
; CHECK-NEXT: vnot.v v14, v12, v0.t
+; CHECK-NEXT: vand.vi v12, v12, 15, v0.t
; CHECK-NEXT: vand.vi v14, v14, 15, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
-; CHECK-NEXT: vand.vi v12, v12, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
@@ -328,9 +328,9 @@ define <32 x i16> @fshr_v32i16(<32 x i16> %a, <32 x i16> %b, <32 x i16> %c, <32
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v20, v16, v0.t
+; CHECK-NEXT: vand.vi v16, v16, 15, v0.t
; CHECK-NEXT: vand.vi v20, v20, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
-; CHECK-NEXT: vand.vi v16, v16, 15, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
@@ -344,9 +344,9 @@ define <32 x i16> @fshl_v32i16(<32 x i16> %a, <32 x i16> %b, <32 x i16> %c, <32
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t
; CHECK-NEXT: vnot.v v20, v16, v0.t
+; CHECK-NEXT: vand.vi v16, v16, 15, v0.t
; CHECK-NEXT: vand.vi v20, v20, 15, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
-; CHECK-NEXT: vand.vi v16, v16, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
@@ -359,12 +359,12 @@ define <2 x i32> @fshr_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 31
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vand.vx v11, v10, a1, v0.t
-; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vnot.v v10, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vnot.v v11, v10, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vand.vx v11, v11, a1, v0.t
+; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <2 x i32> @llvm.vp.fshr.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i1> %m, i32 %evl)
@@ -376,12 +376,12 @@ define <2 x i32> @fshl_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 31
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vand.vx v11, v10, a1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vnot.v v10, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vnot.v v11, v10, v0.t
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
-; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vand.vx v11, v11, a1, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <2 x i32> @llvm.vp.fshl.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i1> %m, i32 %evl)
@@ -393,12 +393,12 @@ define <4 x i32> @fshr_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 31
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vand.vx v11, v10, a1, v0.t
-; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vnot.v v10, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vnot.v v11, v10, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vand.vx v11, v11, a1, v0.t
+; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <4 x i32> @llvm.vp.fshr.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i1> %m, i32 %evl)
@@ -410,12 +410,12 @@ define <4 x i32> @fshl_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 31
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vand.vx v11, v10, a1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vnot.v v10, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vnot.v v11, v10, v0.t
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
-; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vand.vx v11, v11, a1, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <4 x i32> @llvm.vp.fshl.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i1> %m, i32 %evl)
@@ -427,12 +427,12 @@ define <8 x i32> @fshr_v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 31
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vand.vx v14, v12, a1, v0.t
-; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
-; CHECK-NEXT: vnot.v v12, v12, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
+; CHECK-NEXT: vnot.v v14, v12, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
+; CHECK-NEXT: vand.vx v14, v14, a1, v0.t
+; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <8 x i32> @llvm.vp.fshr.v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i1> %m, i32 %evl)
@@ -444,12 +444,12 @@ define <8 x i32> @fshl_v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 31
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vand.vx v14, v12, a1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
-; CHECK-NEXT: vnot.v v12, v12, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
+; CHECK-NEXT: vnot.v v14, v12, v0.t
; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t
-; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
+; CHECK-NEXT: vand.vx v14, v14, a1, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <8 x i32> @llvm.vp.fshl.v8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i1> %m, i32 %evl)
@@ -461,12 +461,12 @@ define <16 x i32> @fshr_v16i32(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 31
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
-; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vnot.v v20, v16, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vand.vx v20, v20, a1, v0.t
+; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%res = call <16 x i32> @llvm.vp.fshr.v16i32(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16 x i1> %m, i32 %evl)
@@ -478,12 +478,12 @@ define <16 x i32> @fshl_v16i32(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 31
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vnot.v v20, v16, v0.t
; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t
-; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vand.vx v20, v20, a1, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%res = call <16 x i32> @llvm.vp.fshl.v16i32(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c, <16 x i1> %m, i32 %evl)
@@ -495,12 +495,12 @@ define <2 x i64> @fshr_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 63
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vand.vx v11, v10, a1, v0.t
-; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vnot.v v10, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vnot.v v11, v10, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vand.vx v11, v11, a1, v0.t
+; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <2 x i64> @llvm.vp.fshr.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i1> %m, i32 %evl)
@@ -512,12 +512,12 @@ define <2 x i64> @fshl_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 63
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vand.vx v11, v10, a1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vnot.v v10, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vnot.v v11, v10, v0.t
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
-; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vand.vx v11, v11, a1, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <2 x i64> @llvm.vp.fshl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i1> %m, i32 %evl)
@@ -529,12 +529,12 @@ define <4 x i64> @fshr_v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, <4 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 63
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vand.vx v14, v12, a1, v0.t
-; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
-; CHECK-NEXT: vnot.v v12, v12, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
+; CHECK-NEXT: vnot.v v14, v12, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
+; CHECK-NEXT: vand.vx v14, v14, a1, v0.t
+; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <4 x i64> @llvm.vp.fshr.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, <4 x i1> %m, i32 %evl)
@@ -546,12 +546,12 @@ define <4 x i64> @fshl_v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, <4 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 63
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vand.vx v14, v12, a1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
-; CHECK-NEXT: vnot.v v12, v12, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
+; CHECK-NEXT: vnot.v v14, v12, v0.t
; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t
-; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
+; CHECK-NEXT: vand.vx v14, v14, a1, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <4 x i64> @llvm.vp.fshl.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, <4 x i1> %m, i32 %evl)
@@ -563,12 +563,12 @@ define <7 x i64> @fshr_v7i64(<7 x i64> %a, <7 x i64> %b, <7 x i64> %c, <7 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 63
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
-; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vnot.v v20, v16, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vand.vx v20, v20, a1, v0.t
+; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%res = call <7 x i64> @llvm.vp.fshr.v7i64(<7 x i64> %a, <7 x i64> %b, <7 x i64> %c, <7 x i1> %m, i32 %evl)
@@ -580,12 +580,12 @@ define <7 x i64> @fshl_v7i64(<7 x i64> %a, <7 x i64> %b, <7 x i64> %c, <7 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 63
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vnot.v v20, v16, v0.t
; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t
-; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vand.vx v20, v20, a1, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%res = call <7 x i64> @llvm.vp.fshl.v7i64(<7 x i64> %a, <7 x i64> %b, <7 x i64> %c, <7 x i1> %m, i32 %evl)
@@ -597,12 +597,12 @@ define <8 x i64> @fshr_v8i64(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, <8 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 63
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
-; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vnot.v v20, v16, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vand.vx v20, v20, a1, v0.t
+; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%res = call <8 x i64> @llvm.vp.fshr.v8i64(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, <8 x i1> %m, i32 %evl)
@@ -614,12 +614,12 @@ define <8 x i64> @fshl_v8i64(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, <8 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 63
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vnot.v v20, v16, v0.t
; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t
-; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vand.vx v20, v20, a1, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%res = call <8 x i64> @llvm.vp.fshl.v8i64(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, <8 x i1> %m, i32 %evl)
@@ -632,26 +632,63 @@ define <16 x i64> @fshr_v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: sub sp, sp, a2
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; CHECK-NEXT: vle64.v v24, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: li a0, 63
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
-; CHECK-NEXT: vsrl.vv v16, v16, v8, v0.t
-; CHECK-NEXT: vnot.v v8, v24, v0.t
+; CHECK-NEXT: vand.vx v24, v8, a0, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsrl.vv v16, v16, v24, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsll.vi v24, v24, 1, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsll.vv v8, v24, v8, v0.t
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -667,27 +704,64 @@ define <16 x i64> @fshl_v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: sub sp, sp, a2
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vmv8r.v v16, v8
-; CHECK-NEXT: vle64.v v24, (a0)
+; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: li a0, 63
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
-; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t
-; CHECK-NEXT: vnot.v v16, v24, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
+; CHECK-NEXT: vand.vx v24, v8, a0, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsll.vv v16, v16, v24, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsrl.vi v24, v24, 1, v0.t
-; CHECK-NEXT: vsrl.vv v16, v24, v16, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsrl.vv v8, v24, v8, v0.t
+; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
index 7813d7f309b6a..8863e0605ba77 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
@@ -118,8 +118,8 @@ define <32 x half> @trunc_v32f16(<32 x half> %x) strictfp {
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: slli a1, a1, 10
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: fmv.h.x fa5, a1
; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: fmv.h.x fa5, a1
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
@@ -138,8 +138,8 @@ define <1 x float> @trunc_v1f32(<1 x float> %x) strictfp {
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
@@ -158,8 +158,8 @@ define <2 x float> @trunc_v2f32(<2 x float> %x) strictfp {
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
@@ -178,8 +178,8 @@ define <4 x float> @trunc_v4f32(<4 x float> %x) strictfp {
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
@@ -198,8 +198,8 @@ define <8 x float> @trunc_v8f32(<8 x float> %x) strictfp {
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
@@ -218,8 +218,8 @@ define <16 x float> @trunc_v16f32(<16 x float> %x) strictfp {
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
@@ -234,10 +234,10 @@ define <16 x float> @trunc_v16f32(<16 x float> %x) strictfp {
define <1 x double> @trunc_v1f64(<1 x double> %x) strictfp {
; RV32-LABEL: trunc_v1f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: lui a0, %hi(.LCPI11_0)
; RV32-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
+; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, mu
+; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
@@ -271,10 +271,10 @@ define <1 x double> @trunc_v1f64(<1 x double> %x) strictfp {
define <2 x double> @trunc_v2f64(<2 x double> %x) strictfp {
; RV32-LABEL: trunc_v2f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
-; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
@@ -308,10 +308,10 @@ define <2 x double> @trunc_v2f64(<2 x double> %x) strictfp {
define <4 x double> @trunc_v4f64(<4 x double> %x) strictfp {
; RV32-LABEL: trunc_v4f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
+; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: vmflt.vf v0, v10, fa5
@@ -345,10 +345,10 @@ define <4 x double> @trunc_v4f64(<4 x double> %x) strictfp {
define <8 x double> @trunc_v8f64(<8 x double> %x) strictfp {
; RV32-LABEL: trunc_v8f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: lui a0, %hi(.LCPI14_0)
; RV32-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
+; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v12, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
index c0473eea56552..6b2f5e3a108ce 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
@@ -468,18 +468,18 @@ define void @insert_v8i1_v4i1_0(ptr %vp, ptr %svp) {
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vlm.v v8, (a1)
+; CHECK-NEXT: vlm.v v10, (a1)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
-; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; CHECK-NEXT: vmv.v.v v9, v8
+; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vmsne.vi v8, v8, 0
; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%v = load <8 x i1>, ptr %vp
@@ -495,17 +495,17 @@ define void @insert_v8i1_v4i1_4(ptr %vp, ptr %svp) {
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vlm.v v8, (a1)
+; CHECK-NEXT: vlm.v v10, (a1)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
-; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vi v9, v8, 4
-; CHECK-NEXT: vmsne.vi v8, v9, 0
+; CHECK-NEXT: vslideup.vi v8, v9, 4
+; CHECK-NEXT: vmsne.vi v8, v8, 0
; CHECK-NEXT: vsm.v v8, (a0)
; CHECK-NEXT: ret
%v = load <8 x i1>, ptr %vp
@@ -545,30 +545,30 @@ define <vscale x 2 x i1> @insert_nxv2i1_v4i1_0(<vscale x 2 x i1> %v, ptr %svp) {
; VLA-LABEL: insert_nxv2i1_v4i1_0:
; VLA: # %bb.0:
; VLA-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; VLA-NEXT: vlm.v v8, (a0)
+; VLA-NEXT: vlm.v v10, (a0)
; VLA-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; VLA-NEXT: vmv.v.i v9, 0
-; VLA-NEXT: vmerge.vim v9, v9, 1, v0
+; VLA-NEXT: vmv.v.i v8, 0
+; VLA-NEXT: vmerge.vim v8, v8, 1, v0
; VLA-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; VLA-NEXT: vmv.v.i v10, 0
-; VLA-NEXT: vmv1r.v v0, v8
+; VLA-NEXT: vmv.v.i v9, 0
+; VLA-NEXT: vmv1r.v v0, v10
; VLA-NEXT: vsetvli zero, zero, e8, mf4, tu, ma
-; VLA-NEXT: vmerge.vim v9, v10, 1, v0
+; VLA-NEXT: vmerge.vim v8, v9, 1, v0
; VLA-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; VLA-NEXT: vmsne.vi v0, v9, 0
+; VLA-NEXT: vmsne.vi v0, v8, 0
; VLA-NEXT: ret
;
; VLS-LABEL: insert_nxv2i1_v4i1_0:
; VLS: # %bb.0:
; VLS-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; VLS-NEXT: vlm.v v8, (a0)
-; VLS-NEXT: vmv.v.i v9, 0
-; VLS-NEXT: vmerge.vim v10, v9, 1, v0
-; VLS-NEXT: vmv1r.v v0, v8
+; VLS-NEXT: vlm.v v10, (a0)
+; VLS-NEXT: vmv.v.i v8, 0
+; VLS-NEXT: vmerge.vim v9, v8, 1, v0
+; VLS-NEXT: vmv1r.v v0, v10
; VLS-NEXT: vsetvli zero, zero, e8, mf4, tu, ma
-; VLS-NEXT: vmerge.vim v10, v9, 1, v0
+; VLS-NEXT: vmerge.vim v9, v8, 1, v0
; VLS-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; VLS-NEXT: vmsne.vi v0, v10, 0
+; VLS-NEXT: vmsne.vi v0, v9, 0
; VLS-NEXT: ret
%sv = load <4 x i1>, ptr %svp
%c = call <vscale x 2 x i1> @llvm.vector.insert.v4i1.nxv2i1(<vscale x 2 x i1> %v, <4 x i1> %sv, i64 0)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
index e04dc58b25d46..68f6b0cb95818 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
@@ -929,11 +929,13 @@ define <512 x i8> @buildvec_not_vid_v512i8_indices_overflow_1() vscale_range(16,
; RV32: # %bb.0:
; RV32-NEXT: li a0, 512
; RV32-NEXT: vsetivli zero, 16, e32, mf2, ta, ma
-; RV32-NEXT: vid.v v8
-; RV32-NEXT: vsrl.vi v8, v8, 3
-; RV32-NEXT: vadd.vi v0, v8, -1
+; RV32-NEXT: vid.v v12
; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; RV32-NEXT: vmv.v.i v8, 1
+; RV32-NEXT: vsetivli zero, 16, e32, mf2, ta, ma
+; RV32-NEXT: vsrl.vi v12, v12, 3
+; RV32-NEXT: vadd.vi v0, v12, -1
+; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; RV32-NEXT: vmerge.vim v8, v8, 0, v0
; RV32-NEXT: ret
;
@@ -941,11 +943,13 @@ define <512 x i8> @buildvec_not_vid_v512i8_indices_overflow_1() vscale_range(16,
; RV64V: # %bb.0:
; RV64V-NEXT: li a0, 512
; RV64V-NEXT: vsetivli zero, 8, e64, m1, ta, ma
-; RV64V-NEXT: vid.v v8
-; RV64V-NEXT: vsrl.vi v8, v8, 2
-; RV64V-NEXT: vadd.vi v0, v8, -1
+; RV64V-NEXT: vid.v v12
; RV64V-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; RV64V-NEXT: vmv.v.i v8, 1
+; RV64V-NEXT: vsetivli zero, 8, e64, m1, ta, ma
+; RV64V-NEXT: vsrl.vi v12, v12, 2
+; RV64V-NEXT: vadd.vi v0, v12, -1
+; RV64V-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; RV64V-NEXT: vmerge.vim v8, v8, 0, v0
; RV64V-NEXT: ret
;
@@ -953,11 +957,13 @@ define <512 x i8> @buildvec_not_vid_v512i8_indices_overflow_1() vscale_range(16,
; RV64ZVE32: # %bb.0:
; RV64ZVE32-NEXT: li a0, 512
; RV64ZVE32-NEXT: vsetivli zero, 16, e32, m1, ta, ma
-; RV64ZVE32-NEXT: vid.v v8
-; RV64ZVE32-NEXT: vsrl.vi v8, v8, 3
-; RV64ZVE32-NEXT: vadd.vi v0, v8, -1
+; RV64ZVE32-NEXT: vid.v v12
; RV64ZVE32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; RV64ZVE32-NEXT: vmv.v.i v8, 1
+; RV64ZVE32-NEXT: vsetivli zero, 16, e32, m1, ta, ma
+; RV64ZVE32-NEXT: vsrl.vi v12, v12, 3
+; RV64ZVE32-NEXT: vadd.vi v0, v12, -1
+; RV64ZVE32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; RV64ZVE32-NEXT: vmerge.vim v8, v8, 0, v0
; RV64ZVE32-NEXT: ret
ret <512 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -979,18 +985,15 @@ define <512 x i8> @buildvec_not_vid_v512i8_indices_overflow_2() vscale_range(16,
; RV32-NEXT: vsetvli zero, zero, e16, m8, ta, ma
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: li a1, 15
+; RV32-NEXT: slli a1, a1, 8
; RV32-NEXT: vsetivli zero, 16, e32, mf2, ta, ma
; RV32-NEXT: vmerge.vim v13, v12, -1, v0
-; RV32-NEXT: slli a1, a1, 8
+; RV32-NEXT: vmv.s.x v0, a1
+; RV32-NEXT: vmerge.vim v12, v12, -1, v0
; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; RV32-NEXT: vmerge.vim v8, v8, 1, v0
-; RV32-NEXT: vsetvli zero, zero, e16, m8, ta, ma
-; RV32-NEXT: vmv.s.x v0, a1
-; RV32-NEXT: vsetivli zero, 16, e32, mf2, ta, ma
-; RV32-NEXT: vmerge.vim v12, v12, -1, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; RV32-NEXT: vmerge.vim v8, v8, 2, v0
; RV32-NEXT: ret
;
@@ -1001,22 +1004,22 @@ define <512 x i8> @buildvec_not_vid_v512i8_indices_overflow_2() vscale_range(16,
; RV64V-NEXT: vmv.v.i v12, 0
; RV64V-NEXT: li a0, 512
; RV64V-NEXT: vmerge.vim v13, v12, -1, v0
+; RV64V-NEXT: vmv.v.i v0, 12
+; RV64V-NEXT: li a1, 48
; RV64V-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; RV64V-NEXT: vmv.v.i v8, 3
-; RV64V-NEXT: vmv1r.v v0, v13
-; RV64V-NEXT: vmerge.vim v8, v8, 0, v0
; RV64V-NEXT: vsetivli zero, 8, e64, m1, ta, ma
-; RV64V-NEXT: vmv.v.i v0, 12
-; RV64V-NEXT: vmerge.vim v13, v12, -1, v0
-; RV64V-NEXT: li a1, 48
-; RV64V-NEXT: vmv.v.v v0, v13
+; RV64V-NEXT: vmerge.vim v14, v12, -1, v0
+; RV64V-NEXT: vmv1r.v v0, v13
; RV64V-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; RV64V-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64V-NEXT: vmerge.vim v8, v8, 0, v0
; RV64V-NEXT: vmv.s.x v0, a1
; RV64V-NEXT: vsetivli zero, 8, e64, m1, ta, ma
; RV64V-NEXT: vmerge.vim v12, v12, -1, v0
-; RV64V-NEXT: vmv.v.v v0, v12
+; RV64V-NEXT: vmv1r.v v0, v14
; RV64V-NEXT: vsetvli zero, a0, e8, m4, ta, ma
+; RV64V-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64V-NEXT: vmv1r.v v0, v12
; RV64V-NEXT: vmerge.vim v8, v8, 2, v0
; RV64V-NEXT: ret
;
@@ -1035,18 +1038,15 @@ define <512 x i8> @buildvec_not_vid_v512i8_indices_overflow_2() vscale_range(16,
; RV64ZVE32-NEXT: vsetvli zero, zero, e16, m8, ta, ma
; RV64ZVE32-NEXT: vmv.s.x v0, a1
; RV64ZVE32-NEXT: li a1, 15
+; RV64ZVE32-NEXT: slli a1, a1, 8
; RV64ZVE32-NEXT: vsetivli zero, 16, e32, m1, ta, ma
; RV64ZVE32-NEXT: vmerge.vim v13, v12, -1, v0
-; RV64ZVE32-NEXT: slli a1, a1, 8
-; RV64ZVE32-NEXT: vmv.v.v v0, v13
-; RV64ZVE32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; RV64ZVE32-NEXT: vmerge.vim v8, v8, 1, v0
-; RV64ZVE32-NEXT: vsetvli zero, zero, e16, m8, ta, ma
; RV64ZVE32-NEXT: vmv.s.x v0, a1
-; RV64ZVE32-NEXT: vsetivli zero, 16, e32, m1, ta, ma
; RV64ZVE32-NEXT: vmerge.vim v12, v12, -1, v0
-; RV64ZVE32-NEXT: vmv.v.v v0, v12
+; RV64ZVE32-NEXT: vmv.v.v v0, v13
; RV64ZVE32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
+; RV64ZVE32-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64ZVE32-NEXT: vmv1r.v v0, v12
; RV64ZVE32-NEXT: vmerge.vim v8, v8, 2, v0
; RV64ZVE32-NEXT: ret
ret <512 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
@@ -1351,15 +1351,13 @@ define <16 x i8> @buildvec_v16i8_loads_contigous(ptr %p) {
; RV32-ONLY-NEXT: lbu t2, 9(a0)
; RV32-ONLY-NEXT: lbu t3, 10(a0)
; RV32-ONLY-NEXT: lbu t4, 11(a0)
-; RV32-ONLY-NEXT: li t5, 255
-; RV32-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV32-ONLY-NEXT: vmv.s.x v0, t5
; RV32-ONLY-NEXT: lbu t5, 12(a0)
; RV32-ONLY-NEXT: lbu t6, 13(a0)
; RV32-ONLY-NEXT: lbu s0, 14(a0)
; RV32-ONLY-NEXT: lbu a0, 15(a0)
-; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu
+; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-ONLY-NEXT: vmv.v.x v8, t1
+; RV32-ONLY-NEXT: li t1, 255
; RV32-ONLY-NEXT: vmv.v.x v9, a1
; RV32-ONLY-NEXT: vslide1down.vx v8, v8, t2
; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a2
@@ -1375,6 +1373,9 @@ define <16 x i8> @buildvec_v16i8_loads_contigous(ptr %p) {
; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a7
; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a0
; RV32-ONLY-NEXT: vslide1down.vx v9, v9, t0
+; RV32-ONLY-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32-ONLY-NEXT: vmv.s.x v0, t1
+; RV32-ONLY-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV32-ONLY-NEXT: vslidedown.vi v8, v9, 8, v0.t
; RV32-ONLY-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32-ONLY-NEXT: .cfi_restore s0
@@ -1486,15 +1487,13 @@ define <16 x i8> @buildvec_v16i8_loads_contigous(ptr %p) {
; RV64V-ONLY-NEXT: lbu t2, 9(a0)
; RV64V-ONLY-NEXT: lbu t3, 10(a0)
; RV64V-ONLY-NEXT: lbu t4, 11(a0)
-; RV64V-ONLY-NEXT: li t5, 255
-; RV64V-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64V-ONLY-NEXT: vmv.s.x v0, t5
; RV64V-ONLY-NEXT: lbu t5, 12(a0)
; RV64V-ONLY-NEXT: lbu t6, 13(a0)
; RV64V-ONLY-NEXT: lbu s0, 14(a0)
; RV64V-ONLY-NEXT: lbu a0, 15(a0)
-; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu
+; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64V-ONLY-NEXT: vmv.v.x v8, t1
+; RV64V-ONLY-NEXT: li t1, 255
; RV64V-ONLY-NEXT: vmv.v.x v9, a1
; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, t2
; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a2
@@ -1510,6 +1509,9 @@ define <16 x i8> @buildvec_v16i8_loads_contigous(ptr %p) {
; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a7
; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a0
; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, t0
+; RV64V-ONLY-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64V-ONLY-NEXT: vmv.s.x v0, t1
+; RV64V-ONLY-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64V-ONLY-NEXT: vslidedown.vi v8, v9, 8, v0.t
; RV64V-ONLY-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
; RV64V-ONLY-NEXT: .cfi_restore s0
@@ -1623,15 +1625,13 @@ define <16 x i8> @buildvec_v16i8_loads_contigous(ptr %p) {
; RV64ZVE32-NEXT: lbu t2, 9(a0)
; RV64ZVE32-NEXT: lbu t3, 10(a0)
; RV64ZVE32-NEXT: lbu t4, 11(a0)
-; RV64ZVE32-NEXT: li t5, 255
-; RV64ZVE32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32-NEXT: vmv.s.x v0, t5
; RV64ZVE32-NEXT: lbu t5, 12(a0)
; RV64ZVE32-NEXT: lbu t6, 13(a0)
; RV64ZVE32-NEXT: lbu s0, 14(a0)
; RV64ZVE32-NEXT: lbu a0, 15(a0)
-; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
+; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64ZVE32-NEXT: vmv.v.x v8, t1
+; RV64ZVE32-NEXT: li t1, 255
; RV64ZVE32-NEXT: vmv.v.x v9, a1
; RV64ZVE32-NEXT: vslide1down.vx v8, v8, t2
; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a2
@@ -1647,6 +1647,9 @@ define <16 x i8> @buildvec_v16i8_loads_contigous(ptr %p) {
; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a7
; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a0
; RV64ZVE32-NEXT: vslide1down.vx v9, v9, t0
+; RV64ZVE32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32-NEXT: vmv.s.x v0, t1
+; RV64ZVE32-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64ZVE32-NEXT: vslidedown.vi v8, v9, 8, v0.t
; RV64ZVE32-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
; RV64ZVE32-NEXT: .cfi_restore s0
@@ -1725,15 +1728,13 @@ define <16 x i8> @buildvec_v16i8_loads_gather(ptr %p) {
; RV32-ONLY-NEXT: lbu t2, 154(a0)
; RV32-ONLY-NEXT: lbu t3, 161(a0)
; RV32-ONLY-NEXT: lbu t4, 163(a0)
-; RV32-ONLY-NEXT: li t5, 255
-; RV32-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV32-ONLY-NEXT: vmv.s.x v0, t5
; RV32-ONLY-NEXT: lbu t5, 93(a0)
; RV32-ONLY-NEXT: lbu t6, 105(a0)
; RV32-ONLY-NEXT: lbu s0, 124(a0)
; RV32-ONLY-NEXT: lbu a0, 144(a0)
-; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu
+; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-ONLY-NEXT: vmv.v.x v8, t1
+; RV32-ONLY-NEXT: li t1, 255
; RV32-ONLY-NEXT: vmv.v.x v9, a1
; RV32-ONLY-NEXT: vslide1down.vx v8, v8, t5
; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a2
@@ -1749,6 +1750,9 @@ define <16 x i8> @buildvec_v16i8_loads_gather(ptr %p) {
; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a5
; RV32-ONLY-NEXT: vslide1down.vx v8, v8, t2
; RV32-ONLY-NEXT: vslide1down.vx v9, v9, t0
+; RV32-ONLY-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32-ONLY-NEXT: vmv.s.x v0, t1
+; RV32-ONLY-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV32-ONLY-NEXT: vslidedown.vi v8, v9, 8, v0.t
; RV32-ONLY-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32-ONLY-NEXT: .cfi_restore s0
@@ -1860,15 +1864,13 @@ define <16 x i8> @buildvec_v16i8_loads_gather(ptr %p) {
; RV64V-ONLY-NEXT: lbu t2, 154(a0)
; RV64V-ONLY-NEXT: lbu t3, 161(a0)
; RV64V-ONLY-NEXT: lbu t4, 163(a0)
-; RV64V-ONLY-NEXT: li t5, 255
-; RV64V-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64V-ONLY-NEXT: vmv.s.x v0, t5
; RV64V-ONLY-NEXT: lbu t5, 93(a0)
; RV64V-ONLY-NEXT: lbu t6, 105(a0)
; RV64V-ONLY-NEXT: lbu s0, 124(a0)
; RV64V-ONLY-NEXT: lbu a0, 144(a0)
-; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu
+; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64V-ONLY-NEXT: vmv.v.x v8, t1
+; RV64V-ONLY-NEXT: li t1, 255
; RV64V-ONLY-NEXT: vmv.v.x v9, a1
; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, t5
; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a2
@@ -1884,6 +1886,9 @@ define <16 x i8> @buildvec_v16i8_loads_gather(ptr %p) {
; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a5
; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, t2
; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, t0
+; RV64V-ONLY-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64V-ONLY-NEXT: vmv.s.x v0, t1
+; RV64V-ONLY-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64V-ONLY-NEXT: vslidedown.vi v8, v9, 8, v0.t
; RV64V-ONLY-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
; RV64V-ONLY-NEXT: .cfi_restore s0
@@ -2005,15 +2010,13 @@ define <16 x i8> @buildvec_v16i8_loads_gather(ptr %p) {
; RV64ZVE32-NEXT: lbu t2, 154(a0)
; RV64ZVE32-NEXT: lbu t3, 161(a0)
; RV64ZVE32-NEXT: lbu t4, 163(a0)
-; RV64ZVE32-NEXT: li t5, 255
-; RV64ZVE32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32-NEXT: vmv.s.x v0, t5
; RV64ZVE32-NEXT: lbu t5, 93(a0)
; RV64ZVE32-NEXT: lbu t6, 105(a0)
; RV64ZVE32-NEXT: lbu s0, 124(a0)
; RV64ZVE32-NEXT: lbu a0, 144(a0)
-; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
+; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64ZVE32-NEXT: vmv.v.x v8, t1
+; RV64ZVE32-NEXT: li t1, 255
; RV64ZVE32-NEXT: vmv.v.x v9, a1
; RV64ZVE32-NEXT: vslide1down.vx v8, v8, t5
; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a2
@@ -2029,6 +2032,9 @@ define <16 x i8> @buildvec_v16i8_loads_gather(ptr %p) {
; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a5
; RV64ZVE32-NEXT: vslide1down.vx v8, v8, t2
; RV64ZVE32-NEXT: vslide1down.vx v9, v9, t0
+; RV64ZVE32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32-NEXT: vmv.s.x v0, t1
+; RV64ZVE32-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64ZVE32-NEXT: vslidedown.vi v8, v9, 8, v0.t
; RV64ZVE32-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
; RV64ZVE32-NEXT: .cfi_restore s0
@@ -2497,15 +2503,13 @@ define <16 x i8> @buildvec_v16i8_undef_edges(ptr %p) {
; RV32-ONLY-NEXT: lbu a3, 44(a0)
; RV32-ONLY-NEXT: lbu a4, 55(a0)
; RV32-ONLY-NEXT: lbu a5, 75(a0)
-; RV32-ONLY-NEXT: li a6, 255
-; RV32-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV32-ONLY-NEXT: vmv.s.x v0, a6
; RV32-ONLY-NEXT: lbu a6, 82(a0)
; RV32-ONLY-NEXT: lbu a7, 93(a0)
; RV32-ONLY-NEXT: lbu t0, 105(a0)
; RV32-ONLY-NEXT: lbu a0, 161(a0)
-; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu
+; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-ONLY-NEXT: vmv.v.x v8, a6
+; RV32-ONLY-NEXT: li a6, 255
; RV32-ONLY-NEXT: vmv.v.x v9, a2
; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a7
; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a3
@@ -2515,6 +2519,9 @@ define <16 x i8> @buildvec_v16i8_undef_edges(ptr %p) {
; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a1
; RV32-ONLY-NEXT: vslidedown.vi v8, v8, 4
; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a5
+; RV32-ONLY-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32-ONLY-NEXT: vmv.s.x v0, a6
+; RV32-ONLY-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV32-ONLY-NEXT: vslidedown.vi v8, v9, 8, v0.t
; RV32-ONLY-NEXT: ret
;
@@ -2584,15 +2591,13 @@ define <16 x i8> @buildvec_v16i8_undef_edges(ptr %p) {
; RV64V-ONLY-NEXT: lbu a3, 44(a0)
; RV64V-ONLY-NEXT: lbu a4, 55(a0)
; RV64V-ONLY-NEXT: lbu a5, 75(a0)
-; RV64V-ONLY-NEXT: li a6, 255
-; RV64V-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64V-ONLY-NEXT: vmv.s.x v0, a6
; RV64V-ONLY-NEXT: lbu a6, 82(a0)
; RV64V-ONLY-NEXT: lbu a7, 93(a0)
; RV64V-ONLY-NEXT: lbu t0, 105(a0)
; RV64V-ONLY-NEXT: lbu a0, 161(a0)
-; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu
+; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64V-ONLY-NEXT: vmv.v.x v8, a6
+; RV64V-ONLY-NEXT: li a6, 255
; RV64V-ONLY-NEXT: vmv.v.x v9, a2
; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a7
; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a3
@@ -2602,6 +2607,9 @@ define <16 x i8> @buildvec_v16i8_undef_edges(ptr %p) {
; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a1
; RV64V-ONLY-NEXT: vslidedown.vi v8, v8, 4
; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a5
+; RV64V-ONLY-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64V-ONLY-NEXT: vmv.s.x v0, a6
+; RV64V-ONLY-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64V-ONLY-NEXT: vslidedown.vi v8, v9, 8, v0.t
; RV64V-ONLY-NEXT: ret
;
@@ -2671,15 +2679,13 @@ define <16 x i8> @buildvec_v16i8_undef_edges(ptr %p) {
; RV64ZVE32-NEXT: lbu a3, 44(a0)
; RV64ZVE32-NEXT: lbu a4, 55(a0)
; RV64ZVE32-NEXT: lbu a5, 75(a0)
-; RV64ZVE32-NEXT: li a6, 255
-; RV64ZVE32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32-NEXT: vmv.s.x v0, a6
; RV64ZVE32-NEXT: lbu a6, 82(a0)
; RV64ZVE32-NEXT: lbu a7, 93(a0)
; RV64ZVE32-NEXT: lbu t0, 105(a0)
; RV64ZVE32-NEXT: lbu a0, 161(a0)
-; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
+; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64ZVE32-NEXT: vmv.v.x v8, a6
+; RV64ZVE32-NEXT: li a6, 255
; RV64ZVE32-NEXT: vmv.v.x v9, a2
; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a7
; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a3
@@ -2689,6 +2695,9 @@ define <16 x i8> @buildvec_v16i8_undef_edges(ptr %p) {
; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a1
; RV64ZVE32-NEXT: vslidedown.vi v8, v8, 4
; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a5
+; RV64ZVE32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32-NEXT: vmv.s.x v0, a6
+; RV64ZVE32-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64ZVE32-NEXT: vslidedown.vi v8, v9, 8, v0.t
; RV64ZVE32-NEXT: ret
%p4 = getelementptr i8, ptr %p, i32 31
@@ -2734,13 +2743,11 @@ define <16 x i8> @buildvec_v16i8_loads_undef_scattered(ptr %p) {
; RV32-ONLY-NEXT: lbu a6, 82(a0)
; RV32-ONLY-NEXT: lbu a7, 93(a0)
; RV32-ONLY-NEXT: lbu t0, 124(a0)
-; RV32-ONLY-NEXT: li t1, 255
-; RV32-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV32-ONLY-NEXT: vmv.s.x v0, t1
; RV32-ONLY-NEXT: lbu t1, 144(a0)
; RV32-ONLY-NEXT: lbu a0, 154(a0)
-; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu
+; RV32-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-ONLY-NEXT: vmv.v.x v8, a6
+; RV32-ONLY-NEXT: li a6, 255
; RV32-ONLY-NEXT: vmv.v.x v9, a1
; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a7
; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a2
@@ -2754,6 +2761,9 @@ define <16 x i8> @buildvec_v16i8_loads_undef_scattered(ptr %p) {
; RV32-ONLY-NEXT: vslidedown.vi v9, v9, 1
; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a0
; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a5
+; RV32-ONLY-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV32-ONLY-NEXT: vmv.s.x v0, a6
+; RV32-ONLY-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV32-ONLY-NEXT: vslidedown.vi v8, v9, 8, v0.t
; RV32-ONLY-NEXT: ret
;
@@ -2828,13 +2838,11 @@ define <16 x i8> @buildvec_v16i8_loads_undef_scattered(ptr %p) {
; RV64V-ONLY-NEXT: lbu a6, 82(a0)
; RV64V-ONLY-NEXT: lbu a7, 93(a0)
; RV64V-ONLY-NEXT: lbu t0, 124(a0)
-; RV64V-ONLY-NEXT: li t1, 255
-; RV64V-ONLY-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64V-ONLY-NEXT: vmv.s.x v0, t1
; RV64V-ONLY-NEXT: lbu t1, 144(a0)
; RV64V-ONLY-NEXT: lbu a0, 154(a0)
-; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, mu
+; RV64V-ONLY-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64V-ONLY-NEXT: vmv.v.x v8, a6
+; RV64V-ONLY-NEXT: li a6, 255
; RV64V-ONLY-NEXT: vmv.v.x v9, a1
; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a7
; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a2
@@ -2848,6 +2856,9 @@ define <16 x i8> @buildvec_v16i8_loads_undef_scattered(ptr %p) {
; RV64V-ONLY-NEXT: vslidedown.vi v9, v9, 1
; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a0
; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a5
+; RV64V-ONLY-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64V-ONLY-NEXT: vmv.s.x v0, a6
+; RV64V-ONLY-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64V-ONLY-NEXT: vslidedown.vi v8, v9, 8, v0.t
; RV64V-ONLY-NEXT: ret
;
@@ -2924,13 +2935,11 @@ define <16 x i8> @buildvec_v16i8_loads_undef_scattered(ptr %p) {
; RV64ZVE32-NEXT: lbu a6, 82(a0)
; RV64ZVE32-NEXT: lbu a7, 93(a0)
; RV64ZVE32-NEXT: lbu t0, 124(a0)
-; RV64ZVE32-NEXT: li t1, 255
-; RV64ZVE32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
-; RV64ZVE32-NEXT: vmv.s.x v0, t1
; RV64ZVE32-NEXT: lbu t1, 144(a0)
; RV64ZVE32-NEXT: lbu a0, 154(a0)
-; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
+; RV64ZVE32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64ZVE32-NEXT: vmv.v.x v8, a6
+; RV64ZVE32-NEXT: li a6, 255
; RV64ZVE32-NEXT: vmv.v.x v9, a1
; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a7
; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a2
@@ -2944,6 +2953,9 @@ define <16 x i8> @buildvec_v16i8_loads_undef_scattered(ptr %p) {
; RV64ZVE32-NEXT: vslidedown.vi v9, v9, 1
; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a0
; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a5
+; RV64ZVE32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; RV64ZVE32-NEXT: vmv.s.x v0, a6
+; RV64ZVE32-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64ZVE32-NEXT: vslidedown.vi v8, v9, 8, v0.t
; RV64ZVE32-NEXT: ret
%p2 = getelementptr i8, ptr %p, i32 1
@@ -3004,13 +3016,13 @@ define <8 x i8> @buildvec_v8i8_pack(i8 %e1, i8 %e2, i8 %e3, i8 %e4, i8 %e5, i8 %
; RV32-ONLY-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-ONLY-NEXT: vmv.v.x v8, a4
; RV32-ONLY-NEXT: vmv.v.x v9, a0
-; RV32-ONLY-NEXT: vmv.v.i v0, 15
; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a5
; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a1
; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a6
; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a2
; RV32-ONLY-NEXT: vslide1down.vx v8, v8, a7
; RV32-ONLY-NEXT: vslide1down.vx v9, v9, a3
+; RV32-ONLY-NEXT: vmv.v.i v0, 15
; RV32-ONLY-NEXT: vslidedown.vi v8, v9, 4, v0.t
; RV32-ONLY-NEXT: ret
;
@@ -3057,13 +3069,13 @@ define <8 x i8> @buildvec_v8i8_pack(i8 %e1, i8 %e2, i8 %e3, i8 %e4, i8 %e5, i8 %
; RV64V-ONLY-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64V-ONLY-NEXT: vmv.v.x v8, a4
; RV64V-ONLY-NEXT: vmv.v.x v9, a0
-; RV64V-ONLY-NEXT: vmv.v.i v0, 15
; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a5
; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a1
; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a6
; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a2
; RV64V-ONLY-NEXT: vslide1down.vx v8, v8, a7
; RV64V-ONLY-NEXT: vslide1down.vx v9, v9, a3
+; RV64V-ONLY-NEXT: vmv.v.i v0, 15
; RV64V-ONLY-NEXT: vslidedown.vi v8, v9, 4, v0.t
; RV64V-ONLY-NEXT: ret
;
@@ -3112,13 +3124,13 @@ define <8 x i8> @buildvec_v8i8_pack(i8 %e1, i8 %e2, i8 %e3, i8 %e4, i8 %e5, i8 %
; RV64ZVE32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64ZVE32-NEXT: vmv.v.x v8, a4
; RV64ZVE32-NEXT: vmv.v.x v9, a0
-; RV64ZVE32-NEXT: vmv.v.i v0, 15
; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a5
; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a1
; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a6
; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a2
; RV64ZVE32-NEXT: vslide1down.vx v8, v8, a7
; RV64ZVE32-NEXT: vslide1down.vx v9, v9, a3
+; RV64ZVE32-NEXT: vmv.v.i v0, 15
; RV64ZVE32-NEXT: vslidedown.vi v8, v9, 4, v0.t
; RV64ZVE32-NEXT: ret
%v1 = insertelement <8 x i8> poison, i8 %e1, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
index 7cb00d40e60c0..23e3ce66349a7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
@@ -1059,24 +1059,24 @@ define void @mulhu_v16i8(ptr %x) {
; CHECK-NEXT: lui a1, 1
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vmerge.vxm v11, v9, a2, v0
-; CHECK-NEXT: addi a2, a1, 32
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmv.s.x v0, a2
; CHECK-NEXT: li a2, 513
-; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.i v12, 4
-; CHECK-NEXT: addi a1, a1, 78
-; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vmv.s.x v0, a2
+; CHECK-NEXT: addi a2, a1, 32
+; CHECK-NEXT: addi a1, a1, 78
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; CHECK-NEXT: vsrl.vv v9, v8, v9
; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; CHECK-NEXT: vmv.s.x v0, a2
+; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
+; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmerge.vim v12, v12, 3, v0
+; CHECK-NEXT: vsrl.vv v9, v8, v9
; CHECK-NEXT: vmulhu.vv v9, v9, v10
-; CHECK-NEXT: vmerge.vim v10, v12, 3, v0
; CHECK-NEXT: lui a1, 8
; CHECK-NEXT: addi a1, a1, 304
; CHECK-NEXT: vsub.vv v8, v8, v9
@@ -1085,7 +1085,7 @@ define void @mulhu_v16i8(ptr %x) {
; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vadd.vv v8, v8, v9
-; CHECK-NEXT: vmerge.vim v9, v10, 2, v0
+; CHECK-NEXT: vmerge.vim v9, v12, 2, v0
; CHECK-NEXT: vsrl.vv v8, v8, v9
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
@@ -1103,20 +1103,20 @@ define void @mulhu_v8i16(ptr %x) {
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vsetivli zero, 7, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.i v10, 1
-; CHECK-NEXT: li a1, 33
-; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: lui a1, %hi(.LCPI66_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI66_0)
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v11, 3
-; CHECK-NEXT: vle16.v v12, (a1)
-; CHECK-NEXT: vmerge.vim v11, v11, 2, v0
+; CHECK-NEXT: vle16.v v11, (a1)
+; CHECK-NEXT: li a1, 33
+; CHECK-NEXT: vmv.v.i v12, 3
+; CHECK-NEXT: vmv.s.x v0, a1
+; CHECK-NEXT: vmerge.vim v12, v12, 2, v0
; CHECK-NEXT: vmv1r.v v13, v9
; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vi v9, v10, 6
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vsrl.vv v9, v8, v9
-; CHECK-NEXT: vmulhu.vv v9, v9, v12
+; CHECK-NEXT: vmulhu.vv v9, v9, v11
; CHECK-NEXT: lui a1, 1048568
; CHECK-NEXT: vsetvli zero, zero, e16, m1, tu, ma
; CHECK-NEXT: vmv.s.x v13, a1
@@ -1125,9 +1125,9 @@ define void @mulhu_v8i16(ptr %x) {
; CHECK-NEXT: vmulhu.vv v8, v8, v13
; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, ma
-; CHECK-NEXT: vslideup.vi v11, v10, 6
+; CHECK-NEXT: vslideup.vi v12, v10, 6
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vsrl.vv v8, v8, v11
+; CHECK-NEXT: vsrl.vv v8, v8, v12
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
%a = load <8 x i16>, ptr %x
@@ -1243,9 +1243,9 @@ define void @mulhs_v16i8(ptr %x) {
; CHECK-NEXT: li a1, 57
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vmerge.vxm v9, v9, a1, v0
-; CHECK-NEXT: vmv.v.i v10, 7
; CHECK-NEXT: vmulhu.vv v8, v8, v9
-; CHECK-NEXT: vmerge.vim v9, v10, 1, v0
+; CHECK-NEXT: vmv.v.i v9, 7
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsrl.vv v8, v8, v9
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
@@ -3152,15 +3152,15 @@ define void @mulhu_v32i8(ptr %x) {
; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: lui a1, 66785
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 4
-; CHECK-NEXT: addi a1, a1, 78
; CHECK-NEXT: vsrl.vv v10, v14, v10
-; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
+; CHECK-NEXT: vmulhu.vv v8, v10, v8
+; CHECK-NEXT: vmv.v.i v10, 4
+; CHECK-NEXT: addi a1, a1, 78
+; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmulhu.vv v8, v10, v8
-; CHECK-NEXT: vmerge.vim v10, v16, 3, v0
+; CHECK-NEXT: vmerge.vim v10, v10, 3, v0
; CHECK-NEXT: lui a1, 529160
; CHECK-NEXT: addi a1, a1, 304
; CHECK-NEXT: vsub.vv v14, v14, v8
@@ -3183,40 +3183,36 @@ define void @mulhu_v16i16(ptr %x) {
; RV32-LABEL: mulhu_v16i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; RV32-NEXT: vle16.v v10, (a0)
+; RV32-NEXT: vle16.v v8, (a0)
; RV32-NEXT: li a1, 257
-; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vmv.s.x v0, a1
+; RV32-NEXT: lui a1, %hi(.LCPI182_0)
+; RV32-NEXT: addi a1, a1, %lo(.LCPI182_0)
+; RV32-NEXT: vle16.v v12, (a1)
; RV32-NEXT: lui a1, 1048568
-; RV32-NEXT: vmerge.vxm v12, v8, a1, v0
-; RV32-NEXT: lui a1, 4
-; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; RV32-NEXT: vmv.v.i v9, 0
-; RV32-NEXT: addi a1, a1, 64
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV32-NEXT: vmv.s.x v8, a1
+; RV32-NEXT: vmerge.vxm v10, v10, a1, v0
; RV32-NEXT: lui a1, 2
; RV32-NEXT: addi a1, a1, 289
-; RV32-NEXT: vmv1r.v v0, v8
+; RV32-NEXT: vmv.s.x v0, a1
+; RV32-NEXT: lui a1, 4
; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; RV32-NEXT: vmerge.vim v16, v9, 1, v0
+; RV32-NEXT: vmv.v.i v14, 0
+; RV32-NEXT: vmv.v.i v15, 3
+; RV32-NEXT: addi a1, a1, 64
+; RV32-NEXT: vmerge.vim v15, v15, 2, v0
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV32-NEXT: vmv.s.x v0, a1
-; RV32-NEXT: lui a1, %hi(.LCPI182_0)
-; RV32-NEXT: addi a1, a1, %lo(.LCPI182_0)
; RV32-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; RV32-NEXT: vmv.v.i v9, 3
-; RV32-NEXT: vmerge.vim v9, v9, 2, v0
-; RV32-NEXT: vle16.v v14, (a1)
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vmerge.vim v17, v9, 1, v0
+; RV32-NEXT: vmerge.vim v16, v14, 1, v0
+; RV32-NEXT: vmerge.vim v17, v15, 1, v0
; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV32-NEXT: vsext.vf2 v8, v16
-; RV32-NEXT: vsrl.vv v8, v10, v8
-; RV32-NEXT: vmulhu.vv v8, v8, v14
-; RV32-NEXT: vsub.vv v10, v10, v8
-; RV32-NEXT: vmulhu.vv v10, v10, v12
-; RV32-NEXT: vadd.vv v8, v10, v8
+; RV32-NEXT: vsext.vf2 v14, v16
+; RV32-NEXT: vsrl.vv v14, v8, v14
+; RV32-NEXT: vmulhu.vv v12, v14, v12
+; RV32-NEXT: vsub.vv v8, v8, v12
+; RV32-NEXT: vmulhu.vv v8, v8, v10
+; RV32-NEXT: vadd.vv v8, v8, v12
; RV32-NEXT: vsext.vf2 v10, v17
; RV32-NEXT: vsrl.vv v8, v8, v10
; RV32-NEXT: vse16.v v8, (a0)
@@ -3357,20 +3353,21 @@ define void @mulhs_v32i8(ptr %x) {
; CHECK-LABEL: mulhs_v32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32
-; CHECK-NEXT: lui a2, 304453
-; CHECK-NEXT: addi a2, a2, -1452
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
-; CHECK-NEXT: vmv.s.x v0, a2
; CHECK-NEXT: li a2, -123
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-NEXT: vle8.v v8, (a0)
-; CHECK-NEXT: vmv.v.i v10, 7
-; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
-; CHECK-NEXT: vmv.v.x v12, a2
+; CHECK-NEXT: vmv.v.x v8, a2
+; CHECK-NEXT: lui a1, 304453
+; CHECK-NEXT: vle8.v v10, (a0)
+; CHECK-NEXT: vmv.v.i v12, 7
+; CHECK-NEXT: addi a1, a1, -1452
+; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmv.s.x v0, a1
+; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
; CHECK-NEXT: li a1, 57
-; CHECK-NEXT: vmerge.vxm v12, v12, a1, v0
-; CHECK-NEXT: vmulhu.vv v8, v8, v12
-; CHECK-NEXT: vsrl.vv v8, v8, v10
+; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
+; CHECK-NEXT: vmulhu.vv v8, v10, v8
+; CHECK-NEXT: vsrl.vv v8, v8, v12
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
%a = load <32 x i8>, ptr %x
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
index b65352aed2d52..cb77b1d4f4973 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
@@ -24,38 +24,35 @@ define <4 x i1> @load_large_vector(ptr %p) {
; ZVE32X-NEXT: xor a0, a7, a0
; ZVE32X-NEXT: snez a3, a3
; ZVE32X-NEXT: snez a1, a1
+; ZVE32X-NEXT: snez a2, a2
+; ZVE32X-NEXT: snez a0, a0
; ZVE32X-NEXT: vmv.s.x v10, a3
; ZVE32X-NEXT: vmv.s.x v11, a1
; ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; ZVE32X-NEXT: vand.vi v10, v10, 1
+; ZVE32X-NEXT: vand.vi v11, v11, 1
; ZVE32X-NEXT: vmsne.vi v0, v10, 0
-; ZVE32X-NEXT: vand.vi v10, v11, 1
-; ZVE32X-NEXT: vmerge.vim v11, v8, 1, v0
-; ZVE32X-NEXT: vmsne.vi v0, v10, 0
-; ZVE32X-NEXT: snez a1, a2
-; ZVE32X-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; ZVE32X-NEXT: vmerge.vim v10, v9, 1, v0
-; ZVE32X-NEXT: vsetivli zero, 2, e8, mf4, tu, ma
-; ZVE32X-NEXT: vslideup.vi v10, v11, 1
-; ZVE32X-NEXT: vmv.s.x v11, a1
-; ZVE32X-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; ZVE32X-NEXT: vmsne.vi v0, v10, 0
-; ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
-; ZVE32X-NEXT: vand.vi v10, v11, 1
+; ZVE32X-NEXT: vmerge.vim v10, v8, 1, v0
+; ZVE32X-NEXT: vmsne.vi v0, v11, 0
; ZVE32X-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVE32X-NEXT: vmerge.vim v11, v9, 1, v0
+; ZVE32X-NEXT: vsetivli zero, 2, e8, mf4, tu, ma
+; ZVE32X-NEXT: vslideup.vi v11, v10, 1
+; ZVE32X-NEXT: vmv.s.x v10, a2
; ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
+; ZVE32X-NEXT: vand.vi v10, v10, 1
; ZVE32X-NEXT: vmsne.vi v0, v10, 0
-; ZVE32X-NEXT: snez a0, a0
; ZVE32X-NEXT: vmerge.vim v10, v8, 1, v0
+; ZVE32X-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVE32X-NEXT: vmsne.vi v0, v11, 0
+; ZVE32X-NEXT: vmerge.vim v11, v9, 1, v0
; ZVE32X-NEXT: vsetivli zero, 3, e8, mf4, tu, ma
; ZVE32X-NEXT: vslideup.vi v11, v10, 2
; ZVE32X-NEXT: vmv.s.x v10, a0
-; ZVE32X-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; ZVE32X-NEXT: vmsne.vi v0, v11, 0
; ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; ZVE32X-NEXT: vand.vi v10, v10, 1
; ZVE32X-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVE32X-NEXT: vmsne.vi v0, v11, 0
; ZVE32X-NEXT: vmerge.vim v9, v9, 1, v0
; ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; ZVE32X-NEXT: vmsne.vi v0, v10, 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
index 9b35860904f11..8fde7053e5a50 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
@@ -530,431 +530,307 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 84
+; RV32-NEXT: li a3, 70
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: sub sp, sp, a2
-; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xd4, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 84 * vlenb
-; RV32-NEXT: addi a4, a1, 128
-; RV32-NEXT: addi a5, a1, 256
+; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc6, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 70 * vlenb
+; RV32-NEXT: addi a6, a1, 128
; RV32-NEXT: li a2, 32
-; RV32-NEXT: lui a3, 12
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; RV32-NEXT: vle32.v v24, (a5)
-; RV32-NEXT: lui a5, 12291
-; RV32-NEXT: vmv.s.x v3, a3
-; RV32-NEXT: vle32.v v8, (a1)
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a6, 76
-; RV32-NEXT: mul a1, a1, a6
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vslideup.vi v16, v24, 4
-; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; RV32-NEXT: vslidedown.vi v8, v24, 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a6, 60
-; RV32-NEXT: mul a1, a1, a6
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v3
-; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; RV32-NEXT: vslideup.vi v16, v8, 10, v0.t
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a6, 56
-; RV32-NEXT: mul a1, a1, a6
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
+; RV32-NEXT: lui a4, 12291
+; RV32-NEXT: lui a7, %hi(.LCPI27_0)
+; RV32-NEXT: addi a7, a7, %lo(.LCPI27_0)
+; RV32-NEXT: lui a3, 49164
+; RV32-NEXT: lui a5, 196656
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; RV32-NEXT: vle32.v v8, (a4)
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a4, 68
-; RV32-NEXT: mul a1, a1, a4
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: addi a5, a5, 3
-; RV32-NEXT: vmv.s.x v0, a5
+; RV32-NEXT: vle32.v v16, (a6)
+; RV32-NEXT: lui a6, 786624
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vslideup.vi v28, v24, 2
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a4, 76
-; RV32-NEXT: mul a1, a1, a4
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a4, 68
-; RV32-NEXT: mul a1, a1, a4
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a4, 44
-; RV32-NEXT: mul a1, a1, a4
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v3
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a4, 60
-; RV32-NEXT: mul a1, a1, a4
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; RV32-NEXT: vslideup.vi v28, v8, 8, v0.t
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a4, 52
-; RV32-NEXT: mul a1, a1, a4
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs4r.v v28, (a1) # vscale x 32-byte Folded Spill
-; RV32-NEXT: lui a1, %hi(.LCPI27_0)
-; RV32-NEXT: addi a1, a1, %lo(.LCPI27_0)
-; RV32-NEXT: lui a6, 49164
-; RV32-NEXT: lui t1, 3
-; RV32-NEXT: lui t0, 196656
-; RV32-NEXT: lui a7, 786624
-; RV32-NEXT: li a4, 48
-; RV32-NEXT: lui a5, 768
-; RV32-NEXT: addi a6, a6, 12
-; RV32-NEXT: vmv.s.x v0, a6
-; RV32-NEXT: addi t1, t1, 3
-; RV32-NEXT: csrr a6, vlenb
-; RV32-NEXT: li t2, 76
-; RV32-NEXT: mul a6, a6, t2
-; RV32-NEXT: add a6, sp, a6
-; RV32-NEXT: addi a6, a6, 16
-; RV32-NEXT: vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a6, vlenb
-; RV32-NEXT: li t2, 68
-; RV32-NEXT: mul a6, a6, t2
-; RV32-NEXT: add a6, sp, a6
-; RV32-NEXT: addi a6, a6, 16
-; RV32-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vle16.v v8, (a7)
+; RV32-NEXT: csrr a7, vlenb
+; RV32-NEXT: li t0, 66
+; RV32-NEXT: mul a7, a7, t0
+; RV32-NEXT: add a7, sp, a7
+; RV32-NEXT: addi a7, a7, 16
+; RV32-NEXT: vs2r.v v8, (a7) # vscale x 16-byte Folded Spill
+; RV32-NEXT: lui a7, 768
+; RV32-NEXT: addi a4, a4, 3
+; RV32-NEXT: vmv.s.x v0, a4
+; RV32-NEXT: lui a4, 3073
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
-; RV32-NEXT: csrr a6, vlenb
-; RV32-NEXT: li t2, 28
-; RV32-NEXT: mul a6, a6, t2
-; RV32-NEXT: add a6, sp, a6
-; RV32-NEXT: addi a6, a6, 16
-; RV32-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv.s.x v0, t1
-; RV32-NEXT: addi a6, t0, 48
-; RV32-NEXT: csrr t0, vlenb
-; RV32-NEXT: li t1, 60
-; RV32-NEXT: mul t0, t0, t1
-; RV32-NEXT: add t0, sp, t0
-; RV32-NEXT: addi t0, t0, 16
-; RV32-NEXT: vl8r.v v8, (t0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmerge.vvm v8, v8, v24, v0
-; RV32-NEXT: csrr t0, vlenb
-; RV32-NEXT: li t1, 36
-; RV32-NEXT: mul t0, t0, t1
-; RV32-NEXT: add t0, sp, t0
-; RV32-NEXT: addi t0, t0, 16
-; RV32-NEXT: vs4r.v v8, (t0) # vscale x 32-byte Folded Spill
-; RV32-NEXT: vmv.s.x v0, a6
+; RV32-NEXT: vle32.v v8, (a1)
; RV32-NEXT: addi a3, a3, 12
-; RV32-NEXT: csrr a6, vlenb
-; RV32-NEXT: li t0, 76
-; RV32-NEXT: mul a6, a6, t0
-; RV32-NEXT: add a6, sp, a6
-; RV32-NEXT: addi a6, a6, 16
-; RV32-NEXT: vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a6, vlenb
-; RV32-NEXT: li t0, 68
-; RV32-NEXT: mul a6, a6, t0
-; RV32-NEXT: add a6, sp, a6
-; RV32-NEXT: addi a6, a6, 16
-; RV32-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
-; RV32-NEXT: csrr a6, vlenb
-; RV32-NEXT: li t0, 20
-; RV32-NEXT: mul a6, a6, t0
-; RV32-NEXT: add a6, sp, a6
-; RV32-NEXT: addi a6, a6, 16
-; RV32-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv.s.x v0, a3
-; RV32-NEXT: addi a3, a7, 192
-; RV32-NEXT: csrr a6, vlenb
-; RV32-NEXT: li a7, 60
-; RV32-NEXT: mul a6, a6, a7
-; RV32-NEXT: add a6, sp, a6
-; RV32-NEXT: addi a6, a6, 16
-; RV32-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmerge.vvm v8, v8, v24, v0
-; RV32-NEXT: csrr a6, vlenb
-; RV32-NEXT: li a7, 40
-; RV32-NEXT: mul a6, a6, a7
-; RV32-NEXT: add a6, sp, a6
-; RV32-NEXT: addi a6, a6, 16
-; RV32-NEXT: vs4r.v v8, (a6) # vscale x 32-byte Folded Spill
-; RV32-NEXT: vmv.s.x v0, a3
-; RV32-NEXT: li a3, 192
-; RV32-NEXT: csrr a6, vlenb
-; RV32-NEXT: li a7, 76
-; RV32-NEXT: mul a6, a6, a7
-; RV32-NEXT: add a6, sp, a6
-; RV32-NEXT: addi a6, a6, 16
-; RV32-NEXT: vl8r.v v16, (a6) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a6, vlenb
-; RV32-NEXT: li a7, 68
-; RV32-NEXT: mul a6, a6, a7
-; RV32-NEXT: add a6, sp, a6
-; RV32-NEXT: addi a6, a6, 16
-; RV32-NEXT: vl8r.v v8, (a6) # vscale x 64-byte Folded Reload
+; RV32-NEXT: addi a5, a5, 48
+; RV32-NEXT: addi a6, a6, 192
+; RV32-NEXT: addi a7, a7, 768
+; RV32-NEXT: addi a4, a4, -1024
+; RV32-NEXT: vmv.s.x v25, a3
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li t0, 58
+; RV32-NEXT: mul a3, a3, t0
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs1r.v v25, (a3) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vmv.s.x v7, a5
+; RV32-NEXT: vmv.s.x v6, a6
+; RV32-NEXT: vmv.s.x v5, a7
+; RV32-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a5, 34
+; RV32-NEXT: mul a3, a3, a5
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.s.x v4, a4
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 58
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 1
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 22
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 42
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v5
+; RV32-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 50
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v4
+; RV32-NEXT: vmerge.vvm v8, v16, v8, v0
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 58
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 66
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl2r.v v8, (a3) # vscale x 16-byte Folded Reload
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 34
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV32-NEXT: vrgatherei16.vv v16, v24, v8
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 14
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: addi a1, a1, 256
+; RV32-NEXT: lui a3, 12
+; RV32-NEXT: lui a4, 3
+; RV32-NEXT: li a5, 48
+; RV32-NEXT: li a6, 192
+; RV32-NEXT: addi a4, a4, 3
+; RV32-NEXT: addi a7, a3, 12
+; RV32-NEXT: vmv.s.x v28, a5
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
-; RV32-NEXT: csrr a6, vlenb
-; RV32-NEXT: slli a6, a6, 3
-; RV32-NEXT: add a6, sp, a6
-; RV32-NEXT: addi a6, a6, 16
-; RV32-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv.s.x v0, a4
-; RV32-NEXT: addi a4, a5, 768
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 60
-; RV32-NEXT: mul a5, a5, a6
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmerge.vvm v8, v8, v24, v0
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 4
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs4r.v v8, (a5) # vscale x 32-byte Folded Spill
+; RV32-NEXT: vle32.v v8, (a1)
+; RV32-NEXT: vmv.s.x v7, a6
; RV32-NEXT: vmv.s.x v0, a4
-; RV32-NEXT: vle16.v v2, (a1)
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a4, 76
-; RV32-NEXT: mul a1, a1, a4
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmv.s.x v29, a7
+; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; RV32-NEXT: vslidedown.vi v16, v8, 16
+; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
+; RV32-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV32-NEXT: vmv1r.v v0, v29
+; RV32-NEXT: vmerge.vvm v12, v16, v8, v0
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a4, 68
-; RV32-NEXT: mul a1, a1, a4
+; RV32-NEXT: li a2, 10
+; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv.s.x v0, a3
+; RV32-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v28
+; RV32-NEXT: vmerge.vvm v12, v16, v8, v0
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 60
-; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: li a2, 34
+; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vmerge.vvm v8, v8, v24, v0
+; RV32-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
+; RV32-NEXT: vslideup.vi v12, v8, 4
+; RV32-NEXT: vslideup.vi v28, v8, 2
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vmerge.vvm v8, v16, v8, v0
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 60
-; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: li a2, 30
+; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 44
-; RV32-NEXT: mul a1, a1, a3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32-NEXT: vrgatherei16.vv v24, v8, v2
; RV32-NEXT: lui a1, %hi(.LCPI27_1)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_1)
-; RV32-NEXT: lui a3, 3073
-; RV32-NEXT: addi a3, a3, -1024
; RV32-NEXT: vmv.s.x v0, a3
-; RV32-NEXT: vle16.v v30, (a1)
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 76
-; RV32-NEXT: mul a1, a1, a3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 68
-; RV32-NEXT: mul a1, a1, a3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 76
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vslideup.vi v12, v16, 10, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 66
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs4r.v v12, (a2) # vscale x 32-byte Folded Spill
+; RV32-NEXT: vle16.v v8, (a1)
+; RV32-NEXT: vslideup.vi v28, v16, 8, v0.t
; RV32-NEXT: lui a1, %hi(.LCPI27_3)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_3)
-; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vle16.v v28, (a1)
+; RV32-NEXT: vle16.v v10, (a1)
+; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: vs2r.v v10, (a1) # vscale x 16-byte Folded Spill
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 28
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a1, a1, 1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vrgatherei16.vv v16, v8, v30
+; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32-NEXT: vrgatherei16.vv v16, v0, v8
; RV32-NEXT: lui a1, %hi(.LCPI27_2)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_2)
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vle16.v v20, (a1)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 20
+; RV32-NEXT: li a2, 22
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: vl2r.v v22, (a1) # vscale x 16-byte Folded Reload
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vrgatherei16.vv v8, v0, v28
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vsetivli zero, 12, e32, m4, tu, ma
-; RV32-NEXT: vmv.v.v v12, v24
+; RV32-NEXT: vrgatherei16.vv v8, v0, v22
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: li a2, 14
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
+; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 52
+; RV32-NEXT: li a2, 66
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vmv.v.v v12, v16
+; RV32-NEXT: vsetivli zero, 12, e32, m4, tu, ma
+; RV32-NEXT: vmv.v.v v12, v0
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 52
+; RV32-NEXT: li a2, 66
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
+; RV32-NEXT: vmv.v.v v28, v16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 36
+; RV32-NEXT: li a2, 22
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
+; RV32-NEXT: vs4r.v v28, (a1) # vscale x 32-byte Folded Spill
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vrgatherei16.vv v24, v12, v20
+; RV32-NEXT: vrgatherei16.vv v16, v24, v20
; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
-; RV32-NEXT: vmv.v.v v24, v8
+; RV32-NEXT: vmv.v.v v16, v8
; RV32-NEXT: lui a1, %hi(.LCPI27_4)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_4)
; RV32-NEXT: lui a2, %hi(.LCPI27_5)
; RV32-NEXT: addi a2, a2, %lo(.LCPI27_5)
; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; RV32-NEXT: vle16.v v28, (a2)
+; RV32-NEXT: vle16.v v20, (a2)
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT: vle16.v v1, (a1)
+; RV32-NEXT: vle16.v v7, (a1)
; RV32-NEXT: lui a1, %hi(.LCPI27_7)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_7)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vle16.v v2, (a1)
+; RV32-NEXT: vle16.v v22, (a1)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: li a2, 42
+; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vrgatherei16.vv v8, v16, v28
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vrgatherei16.vv v8, v24, v20
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 40
+; RV32-NEXT: li a2, 10
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vrgatherei16.vv v28, v12, v1
+; RV32-NEXT: vrgatherei16.vv v0, v12, v7
; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
-; RV32-NEXT: vmv.v.v v28, v8
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmv.v.v v0, v8
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 50
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vrgatherei16.vv v16, v8, v2
+; RV32-NEXT: vrgatherei16.vv v8, v24, v22
; RV32-NEXT: lui a1, %hi(.LCPI27_6)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_6)
; RV32-NEXT: lui a2, %hi(.LCPI27_8)
; RV32-NEXT: addi a2, a2, %lo(.LCPI27_8)
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT: vle16.v v8, (a1)
+; RV32-NEXT: vle16.v v12, (a1)
; RV32-NEXT: lui a1, %hi(.LCPI27_9)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_9)
; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; RV32-NEXT: vle16.v v10, (a1)
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 44
-; RV32-NEXT: mul a1, a1, a3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs2r.v v10, (a1) # vscale x 16-byte Folded Spill
+; RV32-NEXT: vle16.v v4, (a1)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vle16.v v9, (a2)
+; RV32-NEXT: vle16.v v7, (a2)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 68
+; RV32-NEXT: li a2, 34
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs1r.v v9, (a1) # vscale x 8-byte Folded Spill
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vrgatherei16.vv v20, v12, v8
+; RV32-NEXT: vl4r.v v24, (a1) # vscale x 32-byte Folded Reload
+; RV32-NEXT: vrgatherei16.vv v20, v24, v12
; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
-; RV32-NEXT: vmv.v.v v20, v16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 76
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmv.v.v v20, v8
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 44
+; RV32-NEXT: li a2, 58
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl2r.v v16, (a1) # vscale x 16-byte Folded Reload
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vrgatherei16.vv v8, v0, v16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 60
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl4r.v v16, (a1) # vscale x 32-byte Folded Reload
+; RV32-NEXT: vrgatherei16.vv v8, v24, v4
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 68
+; RV32-NEXT: li a2, 30
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl1r.v v7, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vl4r.v v24, (a1) # vscale x 32-byte Folded Reload
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vrgatherei16.vv v12, v16, v7
+; RV32-NEXT: vrgatherei16.vv v12, v24, v7
; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
; RV32-NEXT: vmv.v.v v12, v8
; RV32-NEXT: addi a1, a0, 320
@@ -963,26 +839,26 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: addi a1, a0, 256
; RV32-NEXT: vse32.v v20, (a1)
; RV32-NEXT: addi a1, a0, 192
-; RV32-NEXT: vse32.v v28, (a1)
+; RV32-NEXT: vse32.v v0, (a1)
; RV32-NEXT: addi a1, a0, 128
-; RV32-NEXT: vse32.v v24, (a1)
+; RV32-NEXT: vse32.v v16, (a1)
; RV32-NEXT: addi a1, a0, 64
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 52
+; RV32-NEXT: li a3, 22
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: li a2, 66
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 84
+; RV32-NEXT: li a1, 70
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -995,478 +871,388 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 93
+; RV64-NEXT: li a3, 78
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: sub sp, sp, a2
-; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xdd, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 93 * vlenb
+; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xce, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 78 * vlenb
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vle64.v v8, (a1)
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 85
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: addi a2, a1, 128
-; RV64-NEXT: addi a1, a1, 256
-; RV64-NEXT: vle64.v v8, (a1)
-; RV64-NEXT: li a3, 128
-; RV64-NEXT: lui a1, 1
+; RV64-NEXT: vle64.v v24, (a1)
+; RV64-NEXT: addi a3, a1, 128
+; RV64-NEXT: lui a2, 1
+; RV64-NEXT: vle64.v v16, (a3)
+; RV64-NEXT: lui a3, %hi(.LCPI27_0)
+; RV64-NEXT: addi a3, a3, %lo(.LCPI27_0)
+; RV64-NEXT: vle16.v v6, (a3)
+; RV64-NEXT: li a3, 1040
+; RV64-NEXT: vmv.s.x v5, a3
+; RV64-NEXT: addi a3, a2, 65
+; RV64-NEXT: vmv.s.x v0, a3
+; RV64-NEXT: lui a3, 2
+; RV64-NEXT: addi a3, a3, 130
; RV64-NEXT: vmv.s.x v3, a3
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV64-NEXT: vslideup.vi v24, v8, 2
-; RV64-NEXT: vsetivli zero, 8, e64, m8, ta, ma
-; RV64-NEXT: vslidedown.vi v16, v8, 8
-; RV64-NEXT: csrr a3, vlenb
-; RV64-NEXT: li a4, 45
-; RV64-NEXT: mul a3, a3, a4
-; RV64-NEXT: add a3, sp, a3
-; RV64-NEXT: addi a3, a3, 16
-; RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v3
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vslideup.vi v24, v16, 5, v0.t
+; RV64-NEXT: lui a3, 4
+; RV64-NEXT: addi a3, a3, 260
+; RV64-NEXT: vmv.s.x v4, a3
+; RV64-NEXT: lui a3, 8
+; RV64-NEXT: addi a3, a3, 520
+; RV64-NEXT: addi a2, a2, -2016
+; RV64-NEXT: vmv.s.x v1, a3
+; RV64-NEXT: vmerge.vvm v8, v16, v24, v0
; RV64-NEXT: csrr a3, vlenb
-; RV64-NEXT: li a4, 73
+; RV64-NEXT: li a4, 22
; RV64-NEXT: mul a3, a3, a4
; RV64-NEXT: add a3, sp, a3
; RV64-NEXT: addi a3, a3, 16
-; RV64-NEXT: vs4r.v v24, (a3) # vscale x 32-byte Folded Spill
-; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vle64.v v16, (a2)
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 77
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: addi a2, a1, 65
-; RV64-NEXT: vmv.s.x v0, a2
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV64-NEXT: vslideup.vi v12, v8, 1
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 85
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 77
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vmerge.vvm v16, v16, v24, v0
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 37
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv.s.x v2, a2
; RV64-NEXT: vmv1r.v v0, v3
+; RV64-NEXT: vmerge.vvm v8, v16, v24, v0
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 45
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vslideup.vi v12, v16, 4, v0.t
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 69
+; RV64-NEXT: li a3, 70
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs4r.v v12, (a2) # vscale x 32-byte Folded Spill
-; RV64-NEXT: lui a2, 2
-; RV64-NEXT: lui a3, 4
-; RV64-NEXT: li a4, 32
-; RV64-NEXT: addi a2, a2, 130
-; RV64-NEXT: vmv.s.x v0, a2
-; RV64-NEXT: addi a2, a3, 260
-; RV64-NEXT: csrr a3, vlenb
-; RV64-NEXT: li a5, 85
-; RV64-NEXT: mul a3, a3, a5
-; RV64-NEXT: add a3, sp, a3
-; RV64-NEXT: addi a3, a3, 16
-; RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
-; RV64-NEXT: csrr a3, vlenb
-; RV64-NEXT: li a5, 77
-; RV64-NEXT: mul a3, a3, a5
-; RV64-NEXT: add a3, sp, a3
-; RV64-NEXT: addi a3, a3, 16
-; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vmerge.vvm v16, v16, v24, v0
-; RV64-NEXT: csrr a3, vlenb
-; RV64-NEXT: li a5, 21
-; RV64-NEXT: mul a3, a3, a5
-; RV64-NEXT: add a3, sp, a3
-; RV64-NEXT: addi a3, a3, 16
-; RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv.s.x v0, a2
-; RV64-NEXT: vmv.s.x v2, a4
-; RV64-NEXT: vmv4r.v v12, v8
+; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv1r.v v0, v4
+; RV64-NEXT: vmerge.vvm v8, v16, v24, v0
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 85
+; RV64-NEXT: li a3, 62
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv1r.v v0, v1
+; RV64-NEXT: vmerge.vvm v8, v16, v24, v0
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 77
+; RV64-NEXT: li a3, 38
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv.v.v v8, v16
+; RV64-NEXT: vmv1r.v v0, v5
; RV64-NEXT: vmerge.vvm v16, v16, v24, v0
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 29
+; RV64-NEXT: li a3, 46
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64-NEXT: vmv1r.v v0, v2
+; RV64-NEXT: vmerge.vvm v16, v8, v24, v0
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 53
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vslideup.vi v12, v8, 5, v0.t
-; RV64-NEXT: vmv1r.v v0, v3
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 45
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vrgather.vi v12, v16, 4, v0.t
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: slli a3, a2, 6
-; RV64-NEXT: add a2, a3, a2
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs4r.v v12, (a2) # vscale x 32-byte Folded Spill
-; RV64-NEXT: vslidedown.vi v12, v8, 1
-; RV64-NEXT: vmv1r.v v0, v2
-; RV64-NEXT: vslideup.vi v12, v8, 4, v0.t
-; RV64-NEXT: vmv1r.v v0, v3
-; RV64-NEXT: vmv4r.v v8, v16
-; RV64-NEXT: vrgather.vi v12, v16, 5, v0.t
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: slli a3, a2, 4
-; RV64-NEXT: add a2, a3, a2
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs4r.v v12, (a2) # vscale x 32-byte Folded Spill
-; RV64-NEXT: lui a2, 8
-; RV64-NEXT: addi a2, a2, 520
-; RV64-NEXT: vmv.s.x v0, a2
-; RV64-NEXT: vslideup.vi v4, v16, 6
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 85
+; RV64-NEXT: li a3, 54
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 77
+; RV64-NEXT: li a3, 22
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vmerge.vvm v16, v16, v24, v0
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: slli a3, a2, 3
-; RV64-NEXT: add a2, a3, a2
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v3
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vslideup.vi v4, v8, 1, v0.t
-; RV64-NEXT: li a2, 192
-; RV64-NEXT: vmv.s.x v0, a2
+; RV64-NEXT: vrgatherei16.vv v8, v16, v6
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: slli a2, a2, 3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 53
+; RV64-NEXT: li a3, 30
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vrgather.vi v12, v16, 2
-; RV64-NEXT: vmerge.vvm v12, v12, v4, v0
+; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: lui a2, %hi(.LCPI27_1)
+; RV64-NEXT: addi a2, a2, %lo(.LCPI27_1)
+; RV64-NEXT: lui a3, %hi(.LCPI27_2)
+; RV64-NEXT: addi a3, a3, %lo(.LCPI27_2)
+; RV64-NEXT: vle16.v v8, (a2)
+; RV64-NEXT: vle16.v v10, (a3)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 61
+; RV64-NEXT: li a3, 18
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs4r.v v12, (a2) # vscale x 32-byte Folded Spill
-; RV64-NEXT: lui a2, %hi(.LCPI27_0)
-; RV64-NEXT: addi a2, a2, %lo(.LCPI27_0)
-; RV64-NEXT: li a3, 1040
-; RV64-NEXT: vmv.s.x v0, a3
-; RV64-NEXT: addi a1, a1, -2016
-; RV64-NEXT: csrr a3, vlenb
-; RV64-NEXT: li a4, 85
-; RV64-NEXT: mul a3, a3, a4
-; RV64-NEXT: add a3, sp, a3
-; RV64-NEXT: addi a3, a3, 16
-; RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
-; RV64-NEXT: csrr a3, vlenb
-; RV64-NEXT: li a4, 77
-; RV64-NEXT: mul a3, a3, a4
-; RV64-NEXT: add a3, sp, a3
-; RV64-NEXT: addi a3, a3, 16
-; RV64-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vmerge.vvm v16, v16, v24, v0
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv.s.x v0, a1
-; RV64-NEXT: vle16.v v12, (a2)
+; RV64-NEXT: vs2r.v v10, (a2) # vscale x 16-byte Folded Spill
+; RV64-NEXT: addi a1, a1, 256
+; RV64-NEXT: vle64.v v16, (a1)
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 85
+; RV64-NEXT: li a2, 70
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vrgatherei16.vv v0, v24, v8
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 77
+; RV64-NEXT: slli a1, a1, 1
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 62
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v16, v16, v24, v0
+; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 85
+; RV64-NEXT: li a2, 18
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV64-NEXT: lui a1, %hi(.LCPI27_1)
-; RV64-NEXT: addi a1, a1, %lo(.LCPI27_1)
-; RV64-NEXT: vle16.v v24, (a1)
+; RV64-NEXT: vl2r.v v6, (a1) # vscale x 16-byte Folded Reload
+; RV64-NEXT: vrgatherei16.vv v24, v8, v6
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 37
+; RV64-NEXT: li a2, 22
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vrgatherei16.vv v0, v16, v12
+; RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; RV64-NEXT: li a1, 32
+; RV64-NEXT: vmv.s.x v0, a1
+; RV64-NEXT: vmv4r.v v8, v16
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
+; RV64-NEXT: vslideup.vi v8, v16, 5, v0.t
+; RV64-NEXT: vmv.v.v v24, v8
+; RV64-NEXT: vslidedown.vi v8, v16, 1
+; RV64-NEXT: vslideup.vi v8, v16, 4, v0.t
+; RV64-NEXT: vmv.v.v v28, v8
+; RV64-NEXT: li a1, 128
+; RV64-NEXT: vmv.s.x v8, a1
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 77
+; RV64-NEXT: li a2, 70
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
-; RV64-NEXT: lui a1, %hi(.LCPI27_2)
-; RV64-NEXT: addi a1, a1, %lo(.LCPI27_2)
-; RV64-NEXT: vle16.v v12, (a1)
+; RV64-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
+; RV64-NEXT: vslideup.vi v4, v16, 2
+; RV64-NEXT: vsetivli zero, 8, e64, m8, ta, ma
+; RV64-NEXT: vslidedown.vi v8, v16, 8
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 21
+; RV64-NEXT: li a2, 70
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vrgatherei16.vv v0, v16, v24
+; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
+; RV64-NEXT: vslideup.vi v4, v8, 5, v0.t
+; RV64-NEXT: vslideup.vi v12, v16, 1
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 37
+; RV64-NEXT: li a2, 70
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
-; RV64-NEXT: li a1, 64
-; RV64-NEXT: vmv.s.x v0, a1
+; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vslideup.vi v12, v8, 4, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 29
+; RV64-NEXT: li a2, 70
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vrgatherei16.vv v24, v16, v12
-; RV64-NEXT: vmv4r.v v28, v8
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vslideup.vi v28, v8, 5, v0.t
+; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vrgather.vi v24, v8, 4, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 73
+; RV64-NEXT: li a2, 62
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
+; RV64-NEXT: vs4r.v v24, (a1) # vscale x 32-byte Folded Spill
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 77
+; RV64-NEXT: li a2, 70
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
-; RV64-NEXT: vmv.v.v v8, v16
+; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vrgather.vi v28, v8, 5, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 73
+; RV64-NEXT: li a2, 10
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
+; RV64-NEXT: vs4r.v v28, (a1) # vscale x 32-byte Folded Spill
+; RV64-NEXT: vslideup.vi v24, v8, 6
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 69
+; RV64-NEXT: li a2, 70
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
+; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vslideup.vi v24, v8, 1, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 37
+; RV64-NEXT: li a2, 18
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmv.v.v v8, v16
+; RV64-NEXT: vs4r.v v24, (a1) # vscale x 32-byte Folded Spill
+; RV64-NEXT: li a1, 64
+; RV64-NEXT: vmv.s.x v0, a1
+; RV64-NEXT: vmv4r.v v24, v8
+; RV64-NEXT: vslideup.vi v24, v8, 5, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 69
+; RV64-NEXT: li a2, 14
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
+; RV64-NEXT: vs4r.v v24, (a1) # vscale x 32-byte Folded Spill
; RV64-NEXT: lui a1, %hi(.LCPI27_3)
; RV64-NEXT: addi a1, a1, %lo(.LCPI27_3)
; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV64-NEXT: vle16.v v8, (a1)
-; RV64-NEXT: lui a1, %hi(.LCPI27_4)
-; RV64-NEXT: addi a1, a1, %lo(.LCPI27_4)
-; RV64-NEXT: vle16.v v10, (a1)
+; RV64-NEXT: addi a1, sp, 16
+; RV64-NEXT: vs2r.v v8, (a1) # vscale x 16-byte Folded Spill
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 77
+; RV64-NEXT: li a2, 30
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs2r.v v10, (a1) # vscale x 16-byte Folded Spill
+; RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
+; RV64-NEXT: vmv.v.v v4, v24
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 6
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 70
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
+; RV64-NEXT: vs4r.v v4, (a1) # vscale x 32-byte Folded Spill
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a1, a1, 1
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vmv.v.v v12, v24
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 6
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 30
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 3
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 22
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vrgatherei16.vv v0, v16, v8
+; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 4
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 62
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v20, (a1) # vscale x 32-byte Folded Reload
+; RV64-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
-; RV64-NEXT: vmv.v.v v20, v0
-; RV64-NEXT: addi a1, sp, 16
-; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmv.v.v v12, v8
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 77
+; RV64-NEXT: li a2, 62
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl2r.v v16, (a1) # vscale x 16-byte Folded Reload
+; RV64-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 38
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: addi a1, sp, 16
+; RV64-NEXT: vl2r.v v20, (a1) # vscale x 16-byte Folded Reload
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vrgatherei16.vv v0, v8, v16
-; RV64-NEXT: lui a1, %hi(.LCPI27_5)
-; RV64-NEXT: addi a1, a1, %lo(.LCPI27_5)
-; RV64-NEXT: vle16.v v12, (a1)
+; RV64-NEXT: vrgatherei16.vv v0, v8, v20
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 61
+; RV64-NEXT: li a2, 10
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
+; RV64-NEXT: vl4r.v v28, (a1) # vscale x 32-byte Folded Reload
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
-; RV64-NEXT: vmv.v.v v8, v0
+; RV64-NEXT: vmv.v.v v28, v0
+; RV64-NEXT: li a1, 192
+; RV64-NEXT: lui a2, %hi(.LCPI27_4)
+; RV64-NEXT: addi a2, a2, %lo(.LCPI27_4)
+; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; RV64-NEXT: vle16.v v8, (a2)
+; RV64-NEXT: csrr a2, vlenb
+; RV64-NEXT: li a3, 38
+; RV64-NEXT: mul a2, a2, a3
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: addi a2, a2, 16
+; RV64-NEXT: vs2r.v v8, (a2) # vscale x 16-byte Folded Spill
+; RV64-NEXT: vmv.s.x v0, a1
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV64-NEXT: vrgather.vi v8, v16, 2
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 61
+; RV64-NEXT: li a2, 18
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
+; RV64-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
+; RV64-NEXT: vmerge.vvm v20, v8, v12, v0
+; RV64-NEXT: vmv1r.v v26, v0
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 53
+; RV64-NEXT: li a2, 46
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 38
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vl2r.v v24, (a1) # vscale x 16-byte Folded Reload
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: vrgatherei16.vv v8, v0, v24
+; RV64-NEXT: lui a1, %hi(.LCPI27_5)
+; RV64-NEXT: addi a1, a1, %lo(.LCPI27_5)
+; RV64-NEXT: vle16.v v24, (a1)
+; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
+; RV64-NEXT: vmv.v.v v20, v8
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV64-NEXT: vrgather.vi v8, v0, 3
+; RV64-NEXT: vrgather.vi v8, v16, 3
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: li a2, 14
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v8, v8, v28, v0
+; RV64-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
+; RV64-NEXT: vmv1r.v v0, v26
+; RV64-NEXT: vmerge.vvm v16, v8, v12, v0
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 85
+; RV64-NEXT: li a2, 54
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vrgatherei16.vv v24, v0, v12
+; RV64-NEXT: vrgatherei16.vv v8, v0, v24
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
-; RV64-NEXT: vmv.v.v v8, v24
+; RV64-NEXT: vmv.v.v v16, v8
; RV64-NEXT: addi a1, a0, 320
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV64-NEXT: vse64.v v8, (a1)
+; RV64-NEXT: vse64.v v16, (a1)
; RV64-NEXT: addi a1, a0, 256
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 61
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vse64.v v8, (a1)
-; RV64-NEXT: addi a1, a0, 192
; RV64-NEXT: vse64.v v20, (a1)
+; RV64-NEXT: addi a1, a0, 192
+; RV64-NEXT: vse64.v v28, (a1)
; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: slli a3, a2, 6
-; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: li a3, 62
+; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: addi a1, a0, 64
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 69
+; RV64-NEXT: li a3, 30
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 73
+; RV64-NEXT: li a2, 70
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 93
+; RV64-NEXT: li a1, 78
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 16
@@ -2025,65 +1811,63 @@ define {<4 x i32>, <4 x i32>, <4 x i32>} @invalid_vp_mask(ptr %ptr) {
; RV32-LABEL: invalid_vp_mask:
; RV32: # %bb.0:
; RV32-NEXT: li a1, 73
-; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV32-NEXT: vmv.s.x v11, a1
+; RV32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; RV32-NEXT: vmv.s.x v10, a1
; RV32-NEXT: lui a1, 1
-; RV32-NEXT: vmv.v.i v10, 8
; RV32-NEXT: addi a1, a1, -43
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: li a1, 146
; RV32-NEXT: vsetivli zero, 12, e32, m4, ta, ma
; RV32-NEXT: vle32.v v12, (a0), v0.t
; RV32-NEXT: li a0, 36
-; RV32-NEXT: vmv.s.x v20, a1
+; RV32-NEXT: vmv.s.x v11, a1
; RV32-NEXT: lui a1, %hi(.LCPI65_0)
; RV32-NEXT: addi a1, a1, %lo(.LCPI65_0)
+; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vle16.v v21, (a1)
-; RV32-NEXT: vcompress.vm v8, v12, v11
+; RV32-NEXT: vcompress.vm v8, v12, v10
; RV32-NEXT: vsetivli zero, 8, e32, m4, ta, ma
; RV32-NEXT: vslidedown.vi v16, v12, 8
-; RV32-NEXT: vmv1r.v v0, v10
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV32-NEXT: vcompress.vm v14, v12, v11
+; RV32-NEXT: vmerge.vvm v12, v16, v12, v0
+; RV32-NEXT: vle16.v v18, (a1)
+; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; RV32-NEXT: vmv.v.i v0, 8
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32-NEXT: vrgather.vi v8, v16, 1, v0.t
-; RV32-NEXT: vcompress.vm v14, v12, v20
; RV32-NEXT: vrgather.vi v14, v16, 2, v0.t
-; RV32-NEXT: vmv.s.x v0, a0
-; RV32-NEXT: vmerge.vvm v12, v16, v12, v0
-; RV32-NEXT: vrgatherei16.vv v10, v12, v21
+; RV32-NEXT: vrgatherei16.vv v10, v12, v18
; RV32-NEXT: vmv1r.v v9, v14
; RV32-NEXT: ret
;
; RV64-LABEL: invalid_vp_mask:
; RV64: # %bb.0:
-; RV64-NEXT: li a1, 73
-; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64-NEXT: vmv.s.x v11, a1
-; RV64-NEXT: li a1, 146
-; RV64-NEXT: vmv.s.x v20, a1
; RV64-NEXT: lui a1, 1
-; RV64-NEXT: vmv.v.i v10, 8
; RV64-NEXT: addi a1, a1, -43
-; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64-NEXT: vmv.s.x v0, a1
-; RV64-NEXT: li a1, 36
; RV64-NEXT: vsetivli zero, 12, e32, m4, ta, ma
+; RV64-NEXT: vmv.s.x v0, a1
+; RV64-NEXT: li a1, 73
; RV64-NEXT: vle32.v v12, (a0), v0.t
+; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; RV64-NEXT: vmv.v.i v0, 8
+; RV64-NEXT: li a0, 146
+; RV64-NEXT: vmv.s.x v10, a1
+; RV64-NEXT: li a1, 36
+; RV64-NEXT: vmv.s.x v11, a0
; RV64-NEXT: li a0, 3
-; RV64-NEXT: slli a0, a0, 32
-; RV64-NEXT: addi a0, a0, 5
-; RV64-NEXT: slli a0, a0, 16
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64-NEXT: vcompress.vm v8, v12, v11
+; RV64-NEXT: vcompress.vm v8, v12, v10
; RV64-NEXT: vsetivli zero, 8, e32, m4, ta, ma
; RV64-NEXT: vslidedown.vi v16, v12, 8
-; RV64-NEXT: vmv1r.v v0, v10
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
+; RV64-NEXT: vcompress.vm v14, v12, v11
; RV64-NEXT: vrgather.vi v8, v16, 1, v0.t
-; RV64-NEXT: vcompress.vm v14, v12, v20
; RV64-NEXT: vrgather.vi v14, v16, 2, v0.t
; RV64-NEXT: vmv.s.x v0, a1
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: addi a0, a0, 5
+; RV64-NEXT: slli a0, a0, 16
; RV64-NEXT: addi a0, a0, 2
; RV64-NEXT: vmerge.vvm v12, v16, v12, v0
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
@@ -2108,26 +1892,27 @@ define {<4 x i32>, <4 x i32>, <4 x i32>} @invalid_vp_evl(ptr %ptr) {
; RV32-NEXT: vsetivli zero, 10, e32, m4, ta, ma
; RV32-NEXT: vle32.v v12, (a0)
; RV32-NEXT: li a0, 73
-; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; RV32-NEXT: vmv.v.i v0, 8
; RV32-NEXT: vmv.s.x v10, a0
; RV32-NEXT: li a0, 146
; RV32-NEXT: vmv.s.x v11, a0
+; RV32-NEXT: li a0, 36
+; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: lui a0, %hi(.LCPI66_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI66_0)
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vle16.v v20, (a0)
-; RV32-NEXT: li a0, 36
; RV32-NEXT: vcompress.vm v8, v12, v10
; RV32-NEXT: vsetivli zero, 8, e32, m4, ta, ma
; RV32-NEXT: vslidedown.vi v16, v12, 8
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV32-NEXT: vcompress.vm v14, v12, v11
+; RV32-NEXT: vmerge.vvm v12, v16, v12, v0
+; RV32-NEXT: vle16.v v18, (a0)
+; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; RV32-NEXT: vmv.v.i v0, 8
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32-NEXT: vrgather.vi v8, v16, 1, v0.t
-; RV32-NEXT: vcompress.vm v14, v12, v11
; RV32-NEXT: vrgather.vi v14, v16, 2, v0.t
-; RV32-NEXT: vmv.s.x v0, a0
-; RV32-NEXT: vmerge.vvm v12, v16, v12, v0
-; RV32-NEXT: vrgatherei16.vv v10, v12, v20
+; RV32-NEXT: vrgatherei16.vv v10, v12, v18
; RV32-NEXT: vmv1r.v v9, v14
; RV32-NEXT: ret
;
@@ -2147,8 +1932,8 @@ define {<4 x i32>, <4 x i32>, <4 x i32>} @invalid_vp_evl(ptr %ptr) {
; RV64-NEXT: vsetivli zero, 8, e32, m4, ta, ma
; RV64-NEXT: vslidedown.vi v16, v12, 8
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; RV64-NEXT: vrgather.vi v8, v16, 1, v0.t
; RV64-NEXT: vcompress.vm v14, v12, v11
+; RV64-NEXT: vrgather.vi v8, v16, 1, v0.t
; RV64-NEXT: vrgather.vi v14, v16, 2, v0.t
; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: li a0, 3
@@ -2368,65 +2153,63 @@ define {<4 x i32>, <4 x i32>, <4 x i32>} @maskedload_factor3_invalid_skip_field(
; RV32-LABEL: maskedload_factor3_invalid_skip_field:
; RV32: # %bb.0:
; RV32-NEXT: li a1, 73
-; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV32-NEXT: vmv.s.x v11, a1
+; RV32-NEXT: vsetivli zero, 1, e16, m2, ta, ma
+; RV32-NEXT: vmv.s.x v10, a1
; RV32-NEXT: lui a1, 1
-; RV32-NEXT: vmv.v.i v10, 8
; RV32-NEXT: addi a1, a1, -1171
-; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: li a1, 146
; RV32-NEXT: vsetivli zero, 12, e32, m4, ta, ma
; RV32-NEXT: vle32.v v12, (a0), v0.t
; RV32-NEXT: li a0, 36
-; RV32-NEXT: vmv.s.x v20, a1
+; RV32-NEXT: vmv.s.x v11, a1
; RV32-NEXT: lui a1, %hi(.LCPI78_0)
; RV32-NEXT: addi a1, a1, %lo(.LCPI78_0)
+; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT: vle16.v v21, (a1)
-; RV32-NEXT: vcompress.vm v8, v12, v11
+; RV32-NEXT: vcompress.vm v8, v12, v10
; RV32-NEXT: vsetivli zero, 8, e32, m4, ta, ma
; RV32-NEXT: vslidedown.vi v16, v12, 8
-; RV32-NEXT: vmv1r.v v0, v10
+; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; RV32-NEXT: vcompress.vm v14, v12, v11
+; RV32-NEXT: vmerge.vvm v12, v16, v12, v0
+; RV32-NEXT: vle16.v v18, (a1)
+; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; RV32-NEXT: vmv.v.i v0, 8
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; RV32-NEXT: vrgather.vi v8, v16, 1, v0.t
-; RV32-NEXT: vcompress.vm v14, v12, v20
; RV32-NEXT: vrgather.vi v14, v16, 2, v0.t
-; RV32-NEXT: vmv.s.x v0, a0
-; RV32-NEXT: vmerge.vvm v12, v16, v12, v0
-; RV32-NEXT: vrgatherei16.vv v10, v12, v21
+; RV32-NEXT: vrgatherei16.vv v10, v12, v18
; RV32-NEXT: vmv1r.v v9, v14
; RV32-NEXT: ret
;
; RV64-LABEL: maskedload_factor3_invalid_skip_field:
; RV64: # %bb.0:
-; RV64-NEXT: li a1, 73
-; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; RV64-NEXT: vmv.s.x v11, a1
-; RV64-NEXT: li a1, 146
-; RV64-NEXT: vmv.s.x v20, a1
; RV64-NEXT: lui a1, 1
-; RV64-NEXT: vmv.v.i v10, 8
; RV64-NEXT: addi a1, a1, -1171
-; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; RV64-NEXT: vmv.s.x v0, a1
-; RV64-NEXT: li a1, 36
; RV64-NEXT: vsetivli zero, 12, e32, m4, ta, ma
+; RV64-NEXT: vmv.s.x v0, a1
+; RV64-NEXT: li a1, 73
; RV64-NEXT: vle32.v v12, (a0), v0.t
+; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; RV64-NEXT: vmv.v.i v0, 8
+; RV64-NEXT: li a0, 146
+; RV64-NEXT: vmv.s.x v10, a1
+; RV64-NEXT: li a1, 36
+; RV64-NEXT: vmv.s.x v11, a0
; RV64-NEXT: li a0, 3
-; RV64-NEXT: slli a0, a0, 32
-; RV64-NEXT: addi a0, a0, 5
-; RV64-NEXT: slli a0, a0, 16
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RV64-NEXT: vcompress.vm v8, v12, v11
+; RV64-NEXT: vcompress.vm v8, v12, v10
; RV64-NEXT: vsetivli zero, 8, e32, m4, ta, ma
; RV64-NEXT: vslidedown.vi v16, v12, 8
-; RV64-NEXT: vmv1r.v v0, v10
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
+; RV64-NEXT: vcompress.vm v14, v12, v11
; RV64-NEXT: vrgather.vi v8, v16, 1, v0.t
-; RV64-NEXT: vcompress.vm v14, v12, v20
; RV64-NEXT: vrgather.vi v14, v16, 2, v0.t
; RV64-NEXT: vmv.s.x v0, a1
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: addi a0, a0, 5
+; RV64-NEXT: slli a0, a0, 16
; RV64-NEXT: addi a0, a0, 2
; RV64-NEXT: vmerge.vvm v12, v16, v12, v0
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
index 8027b911a0933..9130a1d5eb6db 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
@@ -141,8 +141,8 @@ define <4 x i1> @buildvec_mask_nonconst_v4i1(i1 %x, i1 %y) {
; CHECK-LABEL: buildvec_mask_nonconst_v4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v0, 3
; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: vmv.v.i v0, 3
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
@@ -151,8 +151,8 @@ define <4 x i1> @buildvec_mask_nonconst_v4i1(i1 %x, i1 %y) {
; ZVE32F-LABEL: buildvec_mask_nonconst_v4i1:
; ZVE32F: # %bb.0:
; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; ZVE32F-NEXT: vmv.v.i v0, 3
; ZVE32F-NEXT: vmv.v.x v8, a1
+; ZVE32F-NEXT: vmv.v.i v0, 3
; ZVE32F-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVE32F-NEXT: vand.vi v8, v8, 1
; ZVE32F-NEXT: vmsne.vi v0, v8, 0
@@ -245,10 +245,10 @@ define <8 x i1> @buildvec_mask_v8i1() {
define <8 x i1> @buildvec_mask_nonconst_v8i1(i1 %x, i1 %y) {
; CHECK-LABEL: buildvec_mask_nonconst_v8i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 19
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vmv.s.x v0, a2
; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: li a1, 19
+; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
@@ -256,10 +256,10 @@ define <8 x i1> @buildvec_mask_nonconst_v8i1(i1 %x, i1 %y) {
;
; ZVE32F-LABEL: buildvec_mask_nonconst_v8i1:
; ZVE32F: # %bb.0:
-; ZVE32F-NEXT: li a2, 19
; ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; ZVE32F-NEXT: vmv.s.x v0, a2
; ZVE32F-NEXT: vmv.v.x v8, a1
+; ZVE32F-NEXT: li a1, 19
+; ZVE32F-NEXT: vmv.s.x v0, a1
; ZVE32F-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVE32F-NEXT: vand.vi v8, v8, 1
; ZVE32F-NEXT: vmsne.vi v0, v8, 0
@@ -282,12 +282,12 @@ define <8 x i1> @buildvec_mask_nonconst_v8i1_2(i1 %x, i1 %y, i1 %z, i1 %w) {
; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: vslide1down.vx v9, v8, a3
; CHECK-NEXT: li a3, 1
-; CHECK-NEXT: vmv.v.i v0, 15
; CHECK-NEXT: vslide1down.vx v8, v8, a0
; CHECK-NEXT: vslide1down.vx v9, v9, zero
; CHECK-NEXT: vslide1down.vx v8, v8, a3
; CHECK-NEXT: vslide1down.vx v9, v9, a2
; CHECK-NEXT: vslide1down.vx v8, v8, a1
+; CHECK-NEXT: vmv.v.i v0, 15
; CHECK-NEXT: vslidedown.vi v9, v8, 4, v0.t
; CHECK-NEXT: vand.vi v8, v9, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
@@ -299,12 +299,12 @@ define <8 x i1> @buildvec_mask_nonconst_v8i1_2(i1 %x, i1 %y, i1 %z, i1 %w) {
; ZVE32F-NEXT: vmv.v.x v8, a0
; ZVE32F-NEXT: vslide1down.vx v9, v8, a3
; ZVE32F-NEXT: li a3, 1
-; ZVE32F-NEXT: vmv.v.i v0, 15
; ZVE32F-NEXT: vslide1down.vx v8, v8, a0
; ZVE32F-NEXT: vslide1down.vx v9, v9, zero
; ZVE32F-NEXT: vslide1down.vx v8, v8, a3
; ZVE32F-NEXT: vslide1down.vx v9, v9, a2
; ZVE32F-NEXT: vslide1down.vx v8, v8, a1
+; ZVE32F-NEXT: vmv.v.i v0, 15
; ZVE32F-NEXT: vslidedown.vi v9, v8, 4, v0.t
; ZVE32F-NEXT: vand.vi v8, v9, 1
; ZVE32F-NEXT: vmsne.vi v0, v8, 0
@@ -327,12 +327,12 @@ define <8 x i1> @buildvec_mask_optsize_nonconst_v8i1_2(i1 %x, i1 %y, i1 %z, i1 %
; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: vslide1down.vx v9, v8, a3
; CHECK-NEXT: li a3, 1
-; CHECK-NEXT: vmv.v.i v0, 15
; CHECK-NEXT: vslide1down.vx v8, v8, a0
; CHECK-NEXT: vslide1down.vx v9, v9, zero
; CHECK-NEXT: vslide1down.vx v8, v8, a3
; CHECK-NEXT: vslide1down.vx v9, v9, a2
; CHECK-NEXT: vslide1down.vx v8, v8, a1
+; CHECK-NEXT: vmv.v.i v0, 15
; CHECK-NEXT: vslidedown.vi v9, v8, 4, v0.t
; CHECK-NEXT: vand.vi v8, v9, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
@@ -344,12 +344,12 @@ define <8 x i1> @buildvec_mask_optsize_nonconst_v8i1_2(i1 %x, i1 %y, i1 %z, i1 %
; ZVE32F-NEXT: vmv.v.x v8, a0
; ZVE32F-NEXT: vslide1down.vx v9, v8, a3
; ZVE32F-NEXT: li a3, 1
-; ZVE32F-NEXT: vmv.v.i v0, 15
; ZVE32F-NEXT: vslide1down.vx v8, v8, a0
; ZVE32F-NEXT: vslide1down.vx v9, v9, zero
; ZVE32F-NEXT: vslide1down.vx v8, v8, a3
; ZVE32F-NEXT: vslide1down.vx v9, v9, a2
; ZVE32F-NEXT: vslide1down.vx v8, v8, a1
+; ZVE32F-NEXT: vmv.v.i v0, 15
; ZVE32F-NEXT: vslidedown.vi v9, v8, 4, v0.t
; ZVE32F-NEXT: vand.vi v8, v9, 1
; ZVE32F-NEXT: vmsne.vi v0, v8, 0
@@ -370,13 +370,13 @@ define <8 x i1> @buildvec_mask_optsize_nonconst_v8i1(i1 %x, i1 %y) optsize {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.x v8, a0
-; CHECK-NEXT: vmv.v.i v0, 15
; CHECK-NEXT: vslide1down.vx v9, v8, a1
; CHECK-NEXT: vslide1down.vx v8, v8, a0
; CHECK-NEXT: vslide1down.vx v9, v9, a1
; CHECK-NEXT: vslide1down.vx v8, v8, a1
; CHECK-NEXT: vslide1down.vx v9, v9, a1
; CHECK-NEXT: vslide1down.vx v8, v8, a1
+; CHECK-NEXT: vmv.v.i v0, 15
; CHECK-NEXT: vslidedown.vi v9, v8, 4, v0.t
; CHECK-NEXT: vand.vi v8, v9, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
@@ -386,13 +386,13 @@ define <8 x i1> @buildvec_mask_optsize_nonconst_v8i1(i1 %x, i1 %y) optsize {
; ZVE32F: # %bb.0:
; ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; ZVE32F-NEXT: vmv.v.x v8, a0
-; ZVE32F-NEXT: vmv.v.i v0, 15
; ZVE32F-NEXT: vslide1down.vx v9, v8, a1
; ZVE32F-NEXT: vslide1down.vx v8, v8, a0
; ZVE32F-NEXT: vslide1down.vx v9, v9, a1
; ZVE32F-NEXT: vslide1down.vx v8, v8, a1
; ZVE32F-NEXT: vslide1down.vx v9, v9, a1
; ZVE32F-NEXT: vslide1down.vx v8, v8, a1
+; ZVE32F-NEXT: vmv.v.i v0, 15
; ZVE32F-NEXT: vslidedown.vi v9, v8, 4, v0.t
; ZVE32F-NEXT: vand.vi v8, v9, 1
; ZVE32F-NEXT: vmsne.vi v0, v8, 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
index 979785dd2c024..84486a96873d4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
@@ -24,11 +24,11 @@ define void @splat_zeros_v2i1(ptr %x) {
define void @splat_v1i1(ptr %x, i1 %y) {
; CHECK-LABEL: splat_v1i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: andi a1, a1, 1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.s.x v8, a1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmv.s.x v8, zero
+; CHECK-NEXT: andi a1, a1, 1
+; CHECK-NEXT: vmv.s.x v9, a1
+; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
@@ -48,11 +48,11 @@ define void @splat_v1i1_icmp(ptr %x, i32 signext %y, i32 signext %z) {
; CHECK-LABEL: splat_v1i1_icmp:
; CHECK: # %bb.0:
; CHECK-NEXT: xor a1, a1, a2
-; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.s.x v8, a1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmv.s.x v8, zero
+; CHECK-NEXT: seqz a1, a1
+; CHECK-NEXT: vmv.s.x v9, a1
+; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
@@ -84,9 +84,9 @@ define void @splat_v4i1(ptr %x, i1 %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: andi a1, a1, 1
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.x v8, a1
-; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv.v.x v9, a1
+; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
index f3cea49ce7946..ca637971a046a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
@@ -13424,11 +13424,11 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m
; RV64V-NEXT: vslidedown.vi v8, v8, 16
; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64V-NEXT: vluxei64.v v10, (a0), v16, v0.t
+; RV64V-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64V-NEXT: vsext.vf8 v16, v8
; RV64V-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64V-NEXT: vslidedown.vi v0, v0, 2
-; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64V-NEXT: vsext.vf8 v16, v8
-; RV64V-NEXT: vsetvli zero, zero, e8, m1, ta, mu
+; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t
; RV64V-NEXT: li a0, 32
; RV64V-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -13924,8 +13924,8 @@ define <4 x i32> @mgather_narrow_edge_case(ptr %base) {
; RV32: # %bb.0:
; RV32-NEXT: li a1, -512
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: vmerge.vim v8, v8, 0, v0
; RV32-NEXT: vluxei32.v v8, (a0), v8
; RV32-NEXT: ret
@@ -13933,10 +13933,11 @@ define <4 x i32> @mgather_narrow_edge_case(ptr %base) {
; RV64V-LABEL: mgather_narrow_edge_case:
; RV64V: # %bb.0:
; RV64V-NEXT: li a1, -512
+; RV64V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64V-NEXT: vmv.v.x v8, a1
; RV64V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64V-NEXT: vmv.v.i v0, 5
; RV64V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV64V-NEXT: vmv.v.x v8, a1
; RV64V-NEXT: vmerge.vim v10, v8, 0, v0
; RV64V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV64V-NEXT: vluxei64.v v8, (a0), v10
@@ -13947,8 +13948,8 @@ define <4 x i32> @mgather_narrow_edge_case(ptr %base) {
; RV64ZVE32F-NEXT: lw a1, -512(a0)
; RV64ZVE32F-NEXT: lw a0, 0(a0)
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV64ZVE32F-NEXT: vmv.v.i v0, 5
; RV64ZVE32F-NEXT: vmv.v.x v8, a1
+; RV64ZVE32F-NEXT: vmv.v.i v0, 5
; RV64ZVE32F-NEXT: vmerge.vxm v8, v8, a0, v0
; RV64ZVE32F-NEXT: ret
%ptrs = getelementptr inbounds i32, ptr %base, <4 x i8> <i8 0, i8 128, i8 0, i8 128>
@@ -13984,45 +13985,45 @@ define <8 x i16> @mgather_strided_unaligned(ptr %base) {
; RV32-NEXT: vmv.x.s t0, v8
; RV32-NEXT: lbu t1, 0(a1)
; RV32-NEXT: lbu a1, 1(a1)
+; RV32-NEXT: lbu t2, 0(a2)
+; RV32-NEXT: lbu a2, 1(a2)
; RV32-NEXT: slli a0, a0, 8
; RV32-NEXT: or a0, a0, a6
-; RV32-NEXT: lbu a6, 0(a2)
-; RV32-NEXT: lbu a2, 1(a2)
+; RV32-NEXT: lbu a6, 0(a3)
+; RV32-NEXT: lbu a3, 1(a3)
; RV32-NEXT: slli a1, a1, 8
; RV32-NEXT: or a1, a1, t1
-; RV32-NEXT: lbu t1, 0(a3)
-; RV32-NEXT: lbu a3, 1(a3)
-; RV32-NEXT: slli a2, a2, 8
-; RV32-NEXT: or a2, a2, a6
-; RV32-NEXT: lbu a6, 0(a4)
+; RV32-NEXT: lbu t1, 0(a4)
; RV32-NEXT: lbu a4, 1(a4)
-; RV32-NEXT: slli a3, a3, 8
-; RV32-NEXT: or a3, a3, t1
-; RV32-NEXT: lbu t1, 0(a5)
+; RV32-NEXT: slli a2, a2, 8
+; RV32-NEXT: or a2, a2, t2
+; RV32-NEXT: lbu t2, 0(a5)
; RV32-NEXT: lbu a5, 1(a5)
-; RV32-NEXT: slli a4, a4, 8
-; RV32-NEXT: or a4, a4, a6
+; RV32-NEXT: slli a3, a3, 8
+; RV32-NEXT: or a3, a3, a6
; RV32-NEXT: lbu a6, 0(a7)
; RV32-NEXT: lbu a7, 1(a7)
-; RV32-NEXT: slli a5, a5, 8
-; RV32-NEXT: or a5, a5, t1
+; RV32-NEXT: slli a4, a4, 8
+; RV32-NEXT: or a4, a4, t1
; RV32-NEXT: lbu t1, 0(t0)
; RV32-NEXT: lbu t0, 1(t0)
+; RV32-NEXT: slli a5, a5, 8
+; RV32-NEXT: or a5, a5, t2
; RV32-NEXT: slli a7, a7, 8
; RV32-NEXT: or a6, a7, a6
-; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV32-NEXT: vmv.v.i v0, 15
; RV32-NEXT: slli t0, t0, 8
; RV32-NEXT: or a7, t0, t1
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV32-NEXT: vmv.v.x v8, a0
; RV32-NEXT: vmv.v.x v9, a4
; RV32-NEXT: vslide1down.vx v8, v8, a1
; RV32-NEXT: vslide1down.vx v9, v9, a5
-; RV32-NEXT: vslide1down.vx v10, v8, a2
-; RV32-NEXT: vslide1down.vx v8, v9, a6
-; RV32-NEXT: vslide1down.vx v8, v8, a7
-; RV32-NEXT: vslide1down.vx v9, v10, a3
-; RV32-NEXT: vslidedown.vi v8, v9, 4, v0.t
+; RV32-NEXT: vslide1down.vx v8, v8, a2
+; RV32-NEXT: vslide1down.vx v9, v9, a6
+; RV32-NEXT: vslide1down.vx v10, v8, a3
+; RV32-NEXT: vslide1down.vx v8, v9, a7
+; RV32-NEXT: vmv.v.i v0, 15
+; RV32-NEXT: vslidedown.vi v8, v10, 4, v0.t
; RV32-NEXT: ret
;
; RV64V-LABEL: mgather_strided_unaligned:
@@ -14095,8 +14096,8 @@ define <8 x i16> @mgather_strided_unaligned(ptr %base) {
; RV64V-NEXT: vmv.v.x v8, a3
; RV64V-NEXT: vslide1down.vx v8, v8, a0
; RV64V-NEXT: vslide1down.vx v8, v8, a1
-; RV64V-NEXT: vmv.v.i v0, 15
; RV64V-NEXT: vslide1down.vx v8, v8, a2
+; RV64V-NEXT: vmv.v.i v0, 15
; RV64V-NEXT: vslidedown.vi v8, v9, 4, v0.t
; RV64V-NEXT: addi sp, s0, -128
; RV64V-NEXT: .cfi_def_cfa sp, 128
@@ -14127,31 +14128,31 @@ define <8 x i16> @mgather_strided_unaligned(ptr %base) {
; RV64ZVE32F-NEXT: lbu t1, 20(a0)
; RV64ZVE32F-NEXT: lbu t2, 21(a0)
; RV64ZVE32F-NEXT: slli a6, a6, 8
-; RV64ZVE32F-NEXT: or a5, a6, a5
; RV64ZVE32F-NEXT: slli t0, t0, 8
; RV64ZVE32F-NEXT: slli a4, a4, 8
-; RV64ZVE32F-NEXT: slli t2, t2, 8
+; RV64ZVE32F-NEXT: or a5, a6, a5
; RV64ZVE32F-NEXT: or a6, t0, a7
; RV64ZVE32F-NEXT: or a2, a4, a2
-; RV64ZVE32F-NEXT: or a4, t2, t1
+; RV64ZVE32F-NEXT: lbu a4, 24(a0)
; RV64ZVE32F-NEXT: lbu a7, 25(a0)
-; RV64ZVE32F-NEXT: lbu t0, 24(a0)
-; RV64ZVE32F-NEXT: lbu t1, 28(a0)
+; RV64ZVE32F-NEXT: lbu t0, 28(a0)
; RV64ZVE32F-NEXT: lbu a0, 29(a0)
+; RV64ZVE32F-NEXT: slli t2, t2, 8
+; RV64ZVE32F-NEXT: or t1, t2, t1
; RV64ZVE32F-NEXT: slli a7, a7, 8
-; RV64ZVE32F-NEXT: or a7, a7, t0
-; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV64ZVE32F-NEXT: vmv.v.i v0, 15
+; RV64ZVE32F-NEXT: or a4, a7, a4
; RV64ZVE32F-NEXT: slli a0, a0, 8
-; RV64ZVE32F-NEXT: or a0, a0, t1
+; RV64ZVE32F-NEXT: or a0, a0, t0
+; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; RV64ZVE32F-NEXT: vmv.v.x v8, a2
; RV64ZVE32F-NEXT: vmv.v.x v9, a1
-; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a4
+; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, t1
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a3
-; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a7
+; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a4
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a5
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a0
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a6
+; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t
; RV64ZVE32F-NEXT: ret
%ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
@@ -14186,7 +14187,6 @@ define <8 x i16> @mgather_strided_2xSEW(ptr %base) {
; RV64ZVE32F-NEXT: lh a7, 24(a0)
; RV64ZVE32F-NEXT: lh a0, 26(a0)
; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vmv.v.x v8, a5
; RV64ZVE32F-NEXT: vmv.v.x v9, a1
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6
@@ -14195,6 +14195,7 @@ define <8 x i16> @mgather_strided_2xSEW(ptr %base) {
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a3
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a0
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a4
+; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t
; RV64ZVE32F-NEXT: ret
%ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13>
@@ -14231,7 +14232,6 @@ define <8 x i16> @mgather_strided_2xSEW_with_offset(ptr %base) {
; RV64ZVE32F-NEXT: lh a7, 28(a0)
; RV64ZVE32F-NEXT: lh a0, 30(a0)
; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vmv.v.x v8, a5
; RV64ZVE32F-NEXT: vmv.v.x v9, a1
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6
@@ -14240,6 +14240,7 @@ define <8 x i16> @mgather_strided_2xSEW_with_offset(ptr %base) {
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a3
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a0
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a4
+; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t
; RV64ZVE32F-NEXT: ret
%ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> <i64 2, i64 3, i64 6, i64 7, i64 10, i64 11, i64 14, i64 15>
@@ -14267,24 +14268,24 @@ define <8 x i16> @mgather_reverse_unit_strided_2xSEW(ptr %base) {
;
; RV64ZVE32F-LABEL: mgather_reverse_unit_strided_2xSEW:
; RV64ZVE32F: # %bb.0:
-; RV64ZVE32F-NEXT: lh a1, 24(a0)
-; RV64ZVE32F-NEXT: lh a2, 26(a0)
-; RV64ZVE32F-NEXT: lh a3, 28(a0)
-; RV64ZVE32F-NEXT: lh a4, 30(a0)
-; RV64ZVE32F-NEXT: lh a5, 20(a0)
-; RV64ZVE32F-NEXT: lh a6, 16(a0)
-; RV64ZVE32F-NEXT: lh a7, 18(a0)
-; RV64ZVE32F-NEXT: lh a0, 22(a0)
+; RV64ZVE32F-NEXT: lh a1, 16(a0)
+; RV64ZVE32F-NEXT: lh a2, 18(a0)
+; RV64ZVE32F-NEXT: lh a3, 20(a0)
+; RV64ZVE32F-NEXT: lh a4, 22(a0)
+; RV64ZVE32F-NEXT: lh a5, 28(a0)
+; RV64ZVE32F-NEXT: lh a6, 24(a0)
+; RV64ZVE32F-NEXT: lh a7, 26(a0)
+; RV64ZVE32F-NEXT: lh a0, 30(a0)
; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu
+; RV64ZVE32F-NEXT: vmv.v.x v8, a3
+; RV64ZVE32F-NEXT: vmv.v.x v9, a5
+; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a4
+; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a0
+; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a1
+; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a6
+; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2
+; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a7
; RV64ZVE32F-NEXT: vmv.v.i v0, 15
-; RV64ZVE32F-NEXT: vmv.v.x v8, a5
-; RV64ZVE32F-NEXT: vmv.v.x v9, a3
-; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a0
-; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a4
-; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6
-; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a1
-; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a7
-; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a2
; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t
; RV64ZVE32F-NEXT: ret
%ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> <i64 14, i64 15, i64 12, i64 13, i64 10, i64 11, i64 8, i64 9>
@@ -14312,24 +14313,24 @@ define <8 x i16> @mgather_reverse_strided_2xSEW(ptr %base) {
;
; RV64ZVE32F-LABEL: mgather_reverse_strided_2xSEW:
; RV64ZVE32F: # %bb.0:
-; RV64ZVE32F-NEXT: lh a1, 20(a0)
-; RV64ZVE32F-NEXT: lh a2, 22(a0)
-; RV64ZVE32F-NEXT: lh a3, 28(a0)
-; RV64ZVE32F-NEXT: lh a4, 30(a0)
-; RV64ZVE32F-NEXT: lh a5, 12(a0)
-; RV64ZVE32F-NEXT: lh a6, 4(a0)
-; RV64ZVE32F-NEXT: lh a7, 6(a0)
-; RV64ZVE32F-NEXT: lh a0, 14(a0)
+; RV64ZVE32F-NEXT: lh a1, 4(a0)
+; RV64ZVE32F-NEXT: lh a2, 6(a0)
+; RV64ZVE32F-NEXT: lh a3, 12(a0)
+; RV64ZVE32F-NEXT: lh a4, 14(a0)
+; RV64ZVE32F-NEXT: lh a5, 28(a0)
+; RV64ZVE32F-NEXT: lh a6, 20(a0)
+; RV64ZVE32F-NEXT: lh a7, 22(a0)
+; RV64ZVE32F-NEXT: lh a0, 30(a0)
; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu
+; RV64ZVE32F-NEXT: vmv.v.x v8, a3
+; RV64ZVE32F-NEXT: vmv.v.x v9, a5
+; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a4
+; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a0
+; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a1
+; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a6
+; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2
+; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a7
; RV64ZVE32F-NEXT: vmv.v.i v0, 15
-; RV64ZVE32F-NEXT: vmv.v.x v8, a5
-; RV64ZVE32F-NEXT: vmv.v.x v9, a3
-; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a0
-; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a4
-; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6
-; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a1
-; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a7
-; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a2
; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t
; RV64ZVE32F-NEXT: ret
%ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> <i64 14, i64 15, i64 10, i64 11, i64 6, i64 7, i64 2, i64 3>
@@ -14365,7 +14366,6 @@ define <8 x i16> @mgather_gather_2xSEW(ptr %base) {
; RV64ZVE32F-NEXT: lh a7, 4(a0)
; RV64ZVE32F-NEXT: lh a0, 6(a0)
; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vmv.v.x v8, a1
; RV64ZVE32F-NEXT: vmv.v.x v9, a5
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2
@@ -14374,6 +14374,7 @@ define <8 x i16> @mgather_gather_2xSEW(ptr %base) {
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a3
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a0
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a4
+; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t
; RV64ZVE32F-NEXT: ret
%ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 4, i32 5, i32 2, i32 3>
@@ -14412,7 +14413,6 @@ define <8 x i16> @mgather_gather_2xSEW_unaligned(ptr %base) {
; RV64ZVE32F-NEXT: lh a7, 4(a0)
; RV64ZVE32F-NEXT: lh a0, 6(a0)
; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vmv.v.x v8, a1
; RV64ZVE32F-NEXT: vmv.v.x v9, a5
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2
@@ -14421,6 +14421,7 @@ define <8 x i16> @mgather_gather_2xSEW_unaligned(ptr %base) {
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a3
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a0
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a4
+; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t
; RV64ZVE32F-NEXT: ret
%ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 0, i32 1, i32 9, i32 10, i32 4, i32 5, i32 2, i32 3>
@@ -14459,7 +14460,6 @@ define <8 x i16> @mgather_gather_2xSEW_unaligned2(ptr %base) {
; RV64ZVE32F-NEXT: lh a6, 18(a0)
; RV64ZVE32F-NEXT: lh a0, 20(a0)
; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vmv.v.x v8, a4
; RV64ZVE32F-NEXT: vmv.v.x v9, a1
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a5
@@ -14468,6 +14468,7 @@ define <8 x i16> @mgather_gather_2xSEW_unaligned2(ptr %base) {
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a6
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a3
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a0
+; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t
; RV64ZVE32F-NEXT: ret
%ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 1, i32 2, i32 9, i32 10, i32 4, i32 5, i32 2, i32 3>
@@ -14510,7 +14511,6 @@ define <8 x i16> @mgather_gather_4xSEW(ptr %base) {
; RV64ZVE32F-NEXT: lh a7, 20(a0)
; RV64ZVE32F-NEXT: lh a0, 22(a0)
; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vmv.v.x v8, a5
; RV64ZVE32F-NEXT: vmv.v.x v9, a1
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6
@@ -14519,6 +14519,7 @@ define <8 x i16> @mgather_gather_4xSEW(ptr %base) {
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a3
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a0
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a4
+; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t
; RV64ZVE32F-NEXT: ret
%ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
@@ -14558,7 +14559,6 @@ define <8 x i16> @mgather_gather_4xSEW_partial_align(ptr %base) {
; RV64ZVE32F-NEXT: lh a7, 20(a0)
; RV64ZVE32F-NEXT: lh a0, 22(a0)
; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vmv.v.x v8, a5
; RV64ZVE32F-NEXT: vmv.v.x v9, a1
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6
@@ -14567,6 +14567,7 @@ define <8 x i16> @mgather_gather_4xSEW_partial_align(ptr %base) {
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a3
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a0
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a4
+; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t
; RV64ZVE32F-NEXT: ret
%ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
@@ -14615,7 +14616,6 @@ define <8 x i16> @mgather_shuffle_rotate(ptr %base) {
; RV64ZVE32F-NEXT: lh a7, 4(a0)
; RV64ZVE32F-NEXT: lh a0, 6(a0)
; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vmv.v.x v8, a5
; RV64ZVE32F-NEXT: vmv.v.x v9, a1
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6
@@ -14624,6 +14624,7 @@ define <8 x i16> @mgather_shuffle_rotate(ptr %base) {
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a3
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a0
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a4
+; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t
; RV64ZVE32F-NEXT: ret
%ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> <i64 4, i64 5, i64 6, i64 7, i64 0, i64 1, i64 2, i64 3>
@@ -14663,7 +14664,6 @@ define <8 x i16> @mgather_shuffle_vrgather(ptr %base) {
; RV64ZVE32F-NEXT: lh a7, 12(a0)
; RV64ZVE32F-NEXT: lh a0, 14(a0)
; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vmv.v.x v8, a5
; RV64ZVE32F-NEXT: vmv.v.x v9, a1
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6
@@ -14672,6 +14672,7 @@ define <8 x i16> @mgather_shuffle_vrgather(ptr %base) {
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a4
; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a0
; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a2
+; RV64ZVE32F-NEXT: vmv.v.i v0, 15
; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t
; RV64ZVE32F-NEXT: ret
%ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> <i64 0, i64 2, i64 3, i64 1, i64 4, i64 5, i64 6, i64 7>
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
index 7b0cfc6bc919b..ecda04c81764c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
@@ -242,9 +242,9 @@ define <32 x double> @masked_load_v32f64(ptr %a, <32 x i1> %mask) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0), v0.t
+; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2
-; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a0), v0.t
; CHECK-NEXT: ret
@@ -280,9 +280,9 @@ define <64 x float> @masked_load_v64f32(ptr %a, <64 x i1> %mask) {
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 4
-; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v16, (a0), v0.t
; CHECK-NEXT: ret
@@ -296,9 +296,9 @@ define <128 x bfloat> @masked_load_v128bf16(ptr %a, <128 x i1> %mask) {
; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v8, (a0), v0.t
+; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 8
-; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v16, (a0), v0.t
; CHECK-NEXT: ret
@@ -312,9 +312,9 @@ define <128 x half> @masked_load_v128f16(ptr %a, <128 x i1> %mask) {
; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v8, (a0), v0.t
+; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 8
-; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v16, (a0), v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
index 78cb57749447e..38388b2004b2f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
@@ -240,9 +240,9 @@ define <32 x i64> @masked_load_v32i64(ptr %a, <32 x i1> %mask) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0), v0.t
+; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2
-; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a0), v0.t
; CHECK-NEXT: ret
@@ -278,9 +278,9 @@ define <64 x i32> @masked_load_v64i32(ptr %a, <64 x i1> %mask) {
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v8, (a0), v0.t
+; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 4
-; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vle32.v v16, (a0), v0.t
; CHECK-NEXT: ret
@@ -305,9 +305,9 @@ define <128 x i16> @masked_load_v128i16(ptr %a, <128 x i1> %mask) {
; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v8, (a0), v0.t
+; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 8
-; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v16, (a0), v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
index c5e874a6f8f91..f1a4318c0480f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
@@ -12081,11 +12081,11 @@ define void @mscatter_baseidx_v32i8(<32 x i8> %val, ptr %base, <32 x i8> %idxs,
; RV64V-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64V-NEXT: vslidedown.vi v16, v8, 16
; RV64V-NEXT: vslidedown.vi v18, v10, 16
-; RV64V-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64V-NEXT: vslidedown.vi v0, v0, 2
; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64V-NEXT: vsext.vf8 v8, v18
-; RV64V-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV64V-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64V-NEXT: vslidedown.vi v0, v0, 2
+; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64V-NEXT: vsoxei64.v v16, (a0), v8, v0.t
; RV64V-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
index 5f4a039866d7e..6098bdd7ad22d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
@@ -242,9 +242,9 @@ define void @masked_store_v32f64(<32 x double> %val, ptr %a, <32 x i1> %mask) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vse64.v v8, (a0), v0.t
+; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2
-; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vse64.v v16, (a0), v0.t
; CHECK-NEXT: ret
@@ -280,9 +280,9 @@ define void @masked_store_v64f32(<64 x float> %val, ptr %a, <64 x i1> %mask) {
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vse32.v v8, (a0), v0.t
+; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 4
-; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vse32.v v16, (a0), v0.t
; CHECK-NEXT: ret
@@ -296,9 +296,9 @@ define void @masked_store_v128bf16(<128 x bfloat> %val, ptr %a, <128 x i1> %mask
; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vse16.v v8, (a0), v0.t
+; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 8
-; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vse16.v v16, (a0), v0.t
; CHECK-NEXT: ret
@@ -312,9 +312,9 @@ define void @masked_store_v128f16(<128 x half> %val, ptr %a, <128 x i1> %mask) {
; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vse16.v v8, (a0), v0.t
+; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 8
-; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vse16.v v16, (a0), v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
index 67e19e046f331..a101c5c2cbac1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
@@ -240,9 +240,9 @@ define void @masked_store_v32i64(<32 x i64> %val, ptr %a, <32 x i1> %mask) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vse64.v v8, (a0), v0.t
+; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2
-; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vse64.v v16, (a0), v0.t
; CHECK-NEXT: ret
@@ -278,9 +278,9 @@ define void @masked_store_v64i32(<64 x i32> %val, ptr %a, <64 x i1> %mask) {
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vse32.v v8, (a0), v0.t
+; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 4
-; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vse32.v v16, (a0), v0.t
; CHECK-NEXT: ret
@@ -305,9 +305,9 @@ define void @masked_store_v128i16(<128 x i16> %val, ptr %a, <128 x i1> %mask) {
; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vse16.v v8, (a0), v0.t
+; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 8
-; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vse16.v v16, (a0), v0.t
; CHECK-NEXT: ret
@@ -320,11 +320,11 @@ define void @masked_store_v256i8(<256 x i8> %val, ptr %a, <256 x i1> %mask) {
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v24, (a1)
-; CHECK-NEXT: addi a1, a0, 128
+; CHECK-NEXT: vlm.v v25, (a1)
; CHECK-NEXT: vse8.v v8, (a0), v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vse8.v v16, (a1), v0.t
+; CHECK-NEXT: addi a0, a0, 128
+; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vse8.v v16, (a0), v0.t
; CHECK-NEXT: ret
call void @llvm.masked.store.v256i8.p0(<256 x i8> %val, ptr %a, i32 8, <256 x i1> %mask)
ret void
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
index 10ef72a3e3f9d..45aeccebad0f6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
@@ -728,92 +728,92 @@ define <32 x double> @vp_nearbyint_v32f64(<32 x double> %va, <32 x i1> %m, i32 z
; RV32-LABEL: vp_nearbyint_v32f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v6, v0
+; RV32-NEXT: vmv1r.v v7, v0
; RV32-NEXT: li a2, 16
-; RV32-NEXT: vslidedown.vi v7, v0, 2
+; RV32-NEXT: vslidedown.vi v6, v0, 2
; RV32-NEXT: mv a1, a0
; RV32-NEXT: bltu a0, a2, .LBB26_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB26_2:
-; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vfabs.v v24, v8, v0.t
-; RV32-NEXT: lui a1, %hi(.LCPI26_0)
-; RV32-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
-; RV32-NEXT: addi a1, a0, -16
-; RV32-NEXT: sltu a0, a0, a1
+; RV32-NEXT: lui a2, %hi(.LCPI26_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
+; RV32-NEXT: addi a2, a0, -16
+; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: addi a0, a0, -1
-; RV32-NEXT: and a0, a0, a1
+; RV32-NEXT: and a0, a0, a2
+; RV32-NEXT: frflags a2
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV32-NEXT: frflags a1
+; RV32-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vfabs.v v24, v16, v0.t
+; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV32-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV32-NEXT: fsflags a1
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: fsflags a2
+; RV32-NEXT: frflags a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vfabs.v v24, v16, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV32-NEXT: frflags a0
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32-NEXT: vfcvt.x.f.v v24, v16, v0.t
; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vfsgnj.vv v16, v24, v16, v0.t
-; RV32-NEXT: fsflags a0
+; RV32-NEXT: fsflags a1
; RV32-NEXT: ret
;
; RV64-LABEL: vp_nearbyint_v32f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v6, v0
+; RV64-NEXT: vmv1r.v v7, v0
; RV64-NEXT: li a2, 16
-; RV64-NEXT: vslidedown.vi v7, v0, 2
+; RV64-NEXT: vslidedown.vi v6, v0, 2
; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB26_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB26_2:
-; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vfabs.v v24, v8, v0.t
-; RV64-NEXT: li a1, 1075
-; RV64-NEXT: slli a1, a1, 52
-; RV64-NEXT: fmv.d.x fa5, a1
-; RV64-NEXT: addi a1, a0, -16
-; RV64-NEXT: sltu a0, a0, a1
+; RV64-NEXT: li a2, 1075
+; RV64-NEXT: slli a2, a2, 52
+; RV64-NEXT: fmv.d.x fa5, a2
+; RV64-NEXT: addi a2, a0, -16
+; RV64-NEXT: sltu a0, a0, a2
; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a0, a0, a2
+; RV64-NEXT: frflags a2
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV64-NEXT: and a0, a0, a1
-; RV64-NEXT: frflags a1
+; RV64-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vfabs.v v24, v16, v0.t
+; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV64-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV64-NEXT: fsflags a1
+; RV64-NEXT: fsflags a2
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: frflags a1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vfabs.v v24, v16, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV64-NEXT: frflags a0
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64-NEXT: vfcvt.x.f.v v24, v16, v0.t
; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64-NEXT: vfsgnj.vv v16, v24, v16, v0.t
-; RV64-NEXT: fsflags a0
+; RV64-NEXT: fsflags a1
; RV64-NEXT: ret
%v = call <32 x double> @llvm.vp.nearbyint.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl)
ret <32 x double> %v
@@ -830,31 +830,28 @@ define <32 x double> @vp_nearbyint_v32f64_unmasked(<32 x double> %va, i32 zeroex
; RV32-NEXT: .LBB27_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vfabs.v v24, v8
-; RV32-NEXT: lui a2, %hi(.LCPI27_0)
-; RV32-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
-; RV32-NEXT: addi a2, a0, -16
-; RV32-NEXT: sltu a0, a0, a2
+; RV32-NEXT: lui a1, %hi(.LCPI27_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
+; RV32-NEXT: addi a1, a0, -16
+; RV32-NEXT: sltu a0, a0, a1
; RV32-NEXT: addi a0, a0, -1
-; RV32-NEXT: and a0, a0, a2
-; RV32-NEXT: frflags a2
+; RV32-NEXT: and a0, a0, a1
+; RV32-NEXT: frflags a1
; RV32-NEXT: vmflt.vf v0, v24, fa5
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vfabs.v v24, v16
-; RV32-NEXT: vmflt.vf v7, v24, fa5
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV32-NEXT: fsflags a2
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32-NEXT: frflags a1
-; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vfabs.v v24, v16
+; RV32-NEXT: vmflt.vf v0, v24, fa5
+; RV32-NEXT: fsflags a1
+; RV32-NEXT: frflags a0
; RV32-NEXT: vfcvt.x.f.v v24, v16, v0.t
; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vfsgnj.vv v16, v24, v16, v0.t
-; RV32-NEXT: fsflags a1
+; RV32-NEXT: fsflags a0
; RV32-NEXT: ret
;
; RV64-LABEL: vp_nearbyint_v32f64_unmasked:
@@ -867,32 +864,29 @@ define <32 x double> @vp_nearbyint_v32f64_unmasked(<32 x double> %va, i32 zeroex
; RV64-NEXT: .LBB27_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vfabs.v v24, v8
-; RV64-NEXT: li a2, 1075
-; RV64-NEXT: slli a2, a2, 52
-; RV64-NEXT: fmv.d.x fa5, a2
-; RV64-NEXT: addi a2, a0, -16
-; RV64-NEXT: sltu a0, a0, a2
+; RV64-NEXT: li a1, 1075
+; RV64-NEXT: slli a1, a1, 52
+; RV64-NEXT: fmv.d.x fa5, a1
+; RV64-NEXT: addi a1, a0, -16
+; RV64-NEXT: sltu a0, a0, a1
; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a0, a0, a2
-; RV64-NEXT: frflags a2
+; RV64-NEXT: and a0, a0, a1
+; RV64-NEXT: frflags a1
; RV64-NEXT: vmflt.vf v0, v24, fa5
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vfabs.v v24, v16
-; RV64-NEXT: vmflt.vf v7, v24, fa5
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV64-NEXT: fsflags a2
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64-NEXT: frflags a1
-; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vfabs.v v24, v16
+; RV64-NEXT: fsflags a1
+; RV64-NEXT: vmflt.vf v0, v24, fa5
+; RV64-NEXT: frflags a0
; RV64-NEXT: vfcvt.x.f.v v24, v16, v0.t
; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64-NEXT: vfsgnj.vv v16, v24, v16, v0.t
-; RV64-NEXT: fsflags a1
+; RV64-NEXT: fsflags a0
; RV64-NEXT: ret
%v = call <32 x double> @llvm.vp.nearbyint.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl)
ret <32 x double> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
index ca9b24e60e503..58826b4f67bf1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
@@ -113,24 +113,24 @@ define float @vpreduce_fadd_v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 4
+; CHECK-NEXT: vslidedown.vi v25, v0, 4
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB8_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: .LBB8_2:
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v24, fa0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
+; CHECK-NEXT: vfredusum.vs v24, v8, v24, v0.t
; CHECK-NEXT: addi a1, a0, -32
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfredusum.vs v25, v16, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredusum.vs v24, v16, v24, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v24
; CHECK-NEXT: ret
%r = call reassoc float @llvm.vp.reduce.fadd.v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32 %evl)
ret float %r
@@ -141,24 +141,24 @@ define float @vpreduce_ord_fadd_v64f32(float %s, <64 x float> %v, <64 x i1> %m,
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 4
+; CHECK-NEXT: vslidedown.vi v25, v0, 4
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB9_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: .LBB9_2:
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v24, fa0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
+; CHECK-NEXT: vfredosum.vs v24, v8, v24, v0.t
; CHECK-NEXT: addi a1, a0, -32
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vfredosum.vs v25, v16, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v24, v16, v24, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v24
; CHECK-NEXT: ret
%r = call float @llvm.vp.reduce.fadd.v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32 %evl)
ret float %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
index 1ccc52be36215..52be38834661d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
@@ -1827,14 +1827,13 @@ define float @vreduce_fminimum_v64f32(ptr %x) {
; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; CHECK-NEXT: vle32.v v16, (a0)
-; CHECK-NEXT: vle32.v v24, (a1)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v16, (a1)
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
; CHECK-NEXT: vmfeq.vv v0, v16, v16
-; CHECK-NEXT: vmfeq.vv v7, v24, v24
-; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
-; CHECK-NEXT: vfmin.vv v8, v16, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
+; CHECK-NEXT: vfmin.vv v8, v8, v24
; CHECK-NEXT: vmfne.vv v16, v8, v8
; CHECK-NEXT: vcpop.m a0, v16
; CHECK-NEXT: beqz a0, .LBB119_2
@@ -1883,74 +1882,81 @@ define float @vreduce_fminimum_v128f32(ptr %x) {
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: addi a2, a0, 128
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; CHECK-NEXT: vle32.v v24, (a2)
-; CHECK-NEXT: addi a1, a0, 384
-; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: addi a1, a0, 256
-; CHECK-NEXT: vle32.v v16, (a1)
+; CHECK-NEXT: vle32.v v16, (a2)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v0, v24, v24
-; CHECK-NEXT: vmfeq.vv v7, v8, v8
-; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: addi a1, a0, 384
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: addi a1, a0, 256
+; CHECK-NEXT: vle32.v v24, (a0)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v24, v16, v16
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
+; CHECK-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v7, v8, v8
+; CHECK-NEXT: vle32.v v24, (a1)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfmin.vv v24, v8, v24
-; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v7, v8, v8
+; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vmfeq.vv v7, v24, v24
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmerge.vvm v24, v24, v8, v0
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfmin.vv v16, v16, v8
+; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfmin.vv v8, v0, v8
+; CHECK-NEXT: vfmin.vv v16, v24, v16
; CHECK-NEXT: vmfeq.vv v0, v16, v16
-; CHECK-NEXT: vmfeq.vv v7, v24, v24
-; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
-; CHECK-NEXT: vfmin.vv v8, v16, v8
+; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
+; CHECK-NEXT: vfmin.vv v8, v8, v24
; CHECK-NEXT: vmfne.vv v16, v8, v8
; CHECK-NEXT: vcpop.m a0, v16
; CHECK-NEXT: beqz a0, .LBB121_2
@@ -2209,14 +2215,13 @@ define double @vreduce_fminimum_v32f64(ptr %x) {
; RV32: # %bb.0:
; RV32-NEXT: addi a1, a0, 128
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vle64.v v16, (a0)
-; RV32-NEXT: vle64.v v24, (a1)
+; RV32-NEXT: vle64.v v8, (a0)
+; RV32-NEXT: vle64.v v16, (a1)
+; RV32-NEXT: vmfeq.vv v0, v8, v8
+; RV32-NEXT: vmerge.vvm v24, v8, v16, v0
; RV32-NEXT: vmfeq.vv v0, v16, v16
-; RV32-NEXT: vmfeq.vv v7, v24, v24
-; RV32-NEXT: vmerge.vvm v8, v16, v24, v0
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vmerge.vvm v16, v24, v16, v0
-; RV32-NEXT: vfmin.vv v8, v16, v8
+; RV32-NEXT: vmerge.vvm v8, v16, v8, v0
+; RV32-NEXT: vfmin.vv v8, v8, v24
; RV32-NEXT: vmfne.vv v16, v8, v8
; RV32-NEXT: vcpop.m a0, v16
; RV32-NEXT: beqz a0, .LBB131_2
@@ -2233,14 +2238,13 @@ define double @vreduce_fminimum_v32f64(ptr %x) {
; RV64: # %bb.0:
; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vle64.v v16, (a0)
-; RV64-NEXT: vle64.v v24, (a1)
+; RV64-NEXT: vle64.v v8, (a0)
+; RV64-NEXT: vle64.v v16, (a1)
+; RV64-NEXT: vmfeq.vv v0, v8, v8
+; RV64-NEXT: vmerge.vvm v24, v8, v16, v0
; RV64-NEXT: vmfeq.vv v0, v16, v16
-; RV64-NEXT: vmfeq.vv v7, v24, v24
-; RV64-NEXT: vmerge.vvm v8, v16, v24, v0
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vmerge.vvm v16, v24, v16, v0
-; RV64-NEXT: vfmin.vv v8, v16, v8
+; RV64-NEXT: vmerge.vvm v8, v16, v8, v0
+; RV64-NEXT: vfmin.vv v8, v8, v24
; RV64-NEXT: vmfne.vv v16, v8, v8
; RV64-NEXT: vcpop.m a0, v16
; RV64-NEXT: beqz a0, .LBB131_2
@@ -2288,74 +2292,81 @@ define double @vreduce_fminimum_v64f64(ptr %x) {
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; RV32-NEXT: addi a1, a0, 128
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vle64.v v24, (a1)
+; RV32-NEXT: vle64.v v16, (a1)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: addi a1, a0, 384
; RV32-NEXT: vle64.v v8, (a1)
; RV32-NEXT: addi a1, a0, 256
-; RV32-NEXT: vle64.v v16, (a0)
+; RV32-NEXT: vle64.v v24, (a0)
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmfeq.vv v0, v24, v24
+; RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmfeq.vv v24, v16, v16
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
; RV32-NEXT: vmfeq.vv v7, v8, v8
-; RV32-NEXT: vle64.v v16, (a1)
+; RV32-NEXT: vle64.v v24, (a1)
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vmerge.vvm v16, v16, v8, v0
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmerge.vvm v16, v24, v8, v0
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vmerge.vvm v8, v8, v24, v0
+; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vfmin.vv v24, v8, v24
+; RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vmfeq.vv v0, v8, v8
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmfeq.vv v7, v16, v16
+; RV32-NEXT: vmfeq.vv v7, v24, v24
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmerge.vvm v16, v16, v8, v0
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vmerge.vvm v24, v24, v8, v0
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vfmin.vv v16, v16, v8
+; RV32-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vfmin.vv v8, v0, v8
+; RV32-NEXT: vfmin.vv v16, v24, v16
; RV32-NEXT: vmfeq.vv v0, v16, v16
-; RV32-NEXT: vmfeq.vv v7, v24, v24
-; RV32-NEXT: vmerge.vvm v8, v16, v24, v0
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vmerge.vvm v16, v24, v16, v0
-; RV32-NEXT: vfmin.vv v8, v16, v8
+; RV32-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV32-NEXT: vmfeq.vv v0, v8, v8
+; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
+; RV32-NEXT: vfmin.vv v8, v8, v24
; RV32-NEXT: vmfne.vv v16, v8, v8
; RV32-NEXT: vcpop.m a0, v16
; RV32-NEXT: beqz a0, .LBB133_2
@@ -2391,74 +2402,81 @@ define double @vreduce_fminimum_v64f64(ptr %x) {
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vle64.v v24, (a1)
+; RV64-NEXT: vle64.v v16, (a1)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV64-NEXT: addi a1, a0, 384
; RV64-NEXT: vle64.v v8, (a1)
; RV64-NEXT: addi a1, a0, 256
-; RV64-NEXT: vle64.v v16, (a0)
+; RV64-NEXT: vle64.v v24, (a0)
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmfeq.vv v0, v24, v24
+; RV64-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmfeq.vv v24, v16, v16
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
; RV64-NEXT: vmfeq.vv v7, v8, v8
-; RV64-NEXT: vle64.v v16, (a1)
+; RV64-NEXT: vle64.v v24, (a1)
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vmerge.vvm v16, v16, v8, v0
; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmerge.vvm v16, v24, v8, v0
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vmerge.vvm v8, v8, v24, v0
+; RV64-NEXT: vmerge.vvm v8, v8, v16, v0
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vfmin.vv v24, v8, v24
+; RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: vmfeq.vv v0, v8, v8
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmfeq.vv v7, v16, v16
+; RV64-NEXT: vmfeq.vv v7, v24, v24
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v8, v8, v16, v0
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vmerge.vvm v16, v8, v24, v0
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v16, v16, v8, v0
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vmerge.vvm v24, v24, v8, v0
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vfmin.vv v16, v16, v8
+; RV64-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vfmin.vv v8, v0, v8
+; RV64-NEXT: vfmin.vv v16, v24, v16
; RV64-NEXT: vmfeq.vv v0, v16, v16
-; RV64-NEXT: vmfeq.vv v7, v24, v24
-; RV64-NEXT: vmerge.vvm v8, v16, v24, v0
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vmerge.vvm v16, v24, v16, v0
-; RV64-NEXT: vfmin.vv v8, v16, v8
+; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV64-NEXT: vmfeq.vv v0, v8, v8
+; RV64-NEXT: vmerge.vvm v8, v8, v16, v0
+; RV64-NEXT: vfmin.vv v8, v8, v24
; RV64-NEXT: vmfne.vv v16, v8, v8
; RV64-NEXT: vcpop.m a0, v16
; RV64-NEXT: beqz a0, .LBB133_2
@@ -2724,14 +2742,13 @@ define float @vreduce_fmaximum_v64f32(ptr %x) {
; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; CHECK-NEXT: vle32.v v16, (a0)
-; CHECK-NEXT: vle32.v v24, (a1)
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vle32.v v16, (a1)
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
; CHECK-NEXT: vmfeq.vv v0, v16, v16
-; CHECK-NEXT: vmfeq.vv v7, v24, v24
-; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
-; CHECK-NEXT: vfmax.vv v8, v16, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
+; CHECK-NEXT: vfmax.vv v8, v8, v24
; CHECK-NEXT: vmfne.vv v16, v8, v8
; CHECK-NEXT: vcpop.m a0, v16
; CHECK-NEXT: beqz a0, .LBB147_2
@@ -2780,74 +2797,81 @@ define float @vreduce_fmaximum_v128f32(ptr %x) {
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: addi a2, a0, 128
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; CHECK-NEXT: vle32.v v24, (a2)
-; CHECK-NEXT: addi a1, a0, 384
-; CHECK-NEXT: vle32.v v8, (a1)
-; CHECK-NEXT: addi a1, a0, 256
-; CHECK-NEXT: vle32.v v16, (a1)
+; CHECK-NEXT: vle32.v v16, (a2)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v0, v24, v24
-; CHECK-NEXT: vmfeq.vv v7, v8, v8
-; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: addi a1, a0, 384
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: addi a1, a0, 256
+; CHECK-NEXT: vle32.v v24, (a0)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v24, v16, v16
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
+; CHECK-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v7, v8, v8
+; CHECK-NEXT: vle32.v v24, (a1)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfmax.vv v24, v8, v24
-; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v7, v8, v8
+; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vmfeq.vv v7, v24, v24
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmerge.vvm v24, v24, v8, v0
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfmax.vv v16, v16, v8
+; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfmax.vv v8, v0, v8
+; CHECK-NEXT: vfmax.vv v16, v24, v16
; CHECK-NEXT: vmfeq.vv v0, v16, v16
-; CHECK-NEXT: vmfeq.vv v7, v24, v24
-; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
-; CHECK-NEXT: vfmax.vv v8, v16, v8
+; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
+; CHECK-NEXT: vfmax.vv v8, v8, v24
; CHECK-NEXT: vmfne.vv v16, v8, v8
; CHECK-NEXT: vcpop.m a0, v16
; CHECK-NEXT: beqz a0, .LBB149_2
@@ -3106,14 +3130,13 @@ define double @vreduce_fmaximum_v32f64(ptr %x) {
; RV32: # %bb.0:
; RV32-NEXT: addi a1, a0, 128
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vle64.v v16, (a0)
-; RV32-NEXT: vle64.v v24, (a1)
+; RV32-NEXT: vle64.v v8, (a0)
+; RV32-NEXT: vle64.v v16, (a1)
+; RV32-NEXT: vmfeq.vv v0, v8, v8
+; RV32-NEXT: vmerge.vvm v24, v8, v16, v0
; RV32-NEXT: vmfeq.vv v0, v16, v16
-; RV32-NEXT: vmfeq.vv v7, v24, v24
-; RV32-NEXT: vmerge.vvm v8, v16, v24, v0
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vmerge.vvm v16, v24, v16, v0
-; RV32-NEXT: vfmax.vv v8, v16, v8
+; RV32-NEXT: vmerge.vvm v8, v16, v8, v0
+; RV32-NEXT: vfmax.vv v8, v8, v24
; RV32-NEXT: vmfne.vv v16, v8, v8
; RV32-NEXT: vcpop.m a0, v16
; RV32-NEXT: beqz a0, .LBB159_2
@@ -3130,14 +3153,13 @@ define double @vreduce_fmaximum_v32f64(ptr %x) {
; RV64: # %bb.0:
; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vle64.v v16, (a0)
-; RV64-NEXT: vle64.v v24, (a1)
+; RV64-NEXT: vle64.v v8, (a0)
+; RV64-NEXT: vle64.v v16, (a1)
+; RV64-NEXT: vmfeq.vv v0, v8, v8
+; RV64-NEXT: vmerge.vvm v24, v8, v16, v0
; RV64-NEXT: vmfeq.vv v0, v16, v16
-; RV64-NEXT: vmfeq.vv v7, v24, v24
-; RV64-NEXT: vmerge.vvm v8, v16, v24, v0
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vmerge.vvm v16, v24, v16, v0
-; RV64-NEXT: vfmax.vv v8, v16, v8
+; RV64-NEXT: vmerge.vvm v8, v16, v8, v0
+; RV64-NEXT: vfmax.vv v8, v8, v24
; RV64-NEXT: vmfne.vv v16, v8, v8
; RV64-NEXT: vcpop.m a0, v16
; RV64-NEXT: beqz a0, .LBB159_2
@@ -3185,74 +3207,81 @@ define double @vreduce_fmaximum_v64f64(ptr %x) {
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; RV32-NEXT: addi a1, a0, 128
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vle64.v v24, (a1)
+; RV32-NEXT: vle64.v v16, (a1)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: addi a1, a0, 384
; RV32-NEXT: vle64.v v8, (a1)
; RV32-NEXT: addi a1, a0, 256
-; RV32-NEXT: vle64.v v16, (a0)
+; RV32-NEXT: vle64.v v24, (a0)
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmfeq.vv v0, v24, v24
+; RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmfeq.vv v24, v16, v16
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
; RV32-NEXT: vmfeq.vv v7, v8, v8
-; RV32-NEXT: vle64.v v16, (a1)
+; RV32-NEXT: vle64.v v24, (a1)
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vmerge.vvm v16, v16, v8, v0
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmerge.vvm v16, v24, v8, v0
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vmerge.vvm v8, v8, v24, v0
+; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vfmax.vv v24, v8, v24
+; RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vmfeq.vv v0, v8, v8
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmfeq.vv v7, v16, v16
+; RV32-NEXT: vmfeq.vv v7, v24, v24
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmerge.vvm v16, v16, v8, v0
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vmerge.vvm v24, v24, v8, v0
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vfmax.vv v16, v16, v8
+; RV32-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vfmax.vv v8, v0, v8
+; RV32-NEXT: vfmax.vv v16, v24, v16
; RV32-NEXT: vmfeq.vv v0, v16, v16
-; RV32-NEXT: vmfeq.vv v7, v24, v24
-; RV32-NEXT: vmerge.vvm v8, v16, v24, v0
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vmerge.vvm v16, v24, v16, v0
-; RV32-NEXT: vfmax.vv v8, v16, v8
+; RV32-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV32-NEXT: vmfeq.vv v0, v8, v8
+; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
+; RV32-NEXT: vfmax.vv v8, v8, v24
; RV32-NEXT: vmfne.vv v16, v8, v8
; RV32-NEXT: vcpop.m a0, v16
; RV32-NEXT: beqz a0, .LBB161_2
@@ -3288,74 +3317,81 @@ define double @vreduce_fmaximum_v64f64(ptr %x) {
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vle64.v v24, (a1)
+; RV64-NEXT: vle64.v v16, (a1)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV64-NEXT: addi a1, a0, 384
; RV64-NEXT: vle64.v v8, (a1)
; RV64-NEXT: addi a1, a0, 256
-; RV64-NEXT: vle64.v v16, (a0)
+; RV64-NEXT: vle64.v v24, (a0)
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmfeq.vv v0, v24, v24
+; RV64-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmfeq.vv v24, v16, v16
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
; RV64-NEXT: vmfeq.vv v7, v8, v8
-; RV64-NEXT: vle64.v v16, (a1)
+; RV64-NEXT: vle64.v v24, (a1)
+; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: slli a0, a0, 3
+; RV64-NEXT: add a0, sp, a0
+; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vmerge.vvm v16, v16, v8, v0
; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmerge.vvm v16, v24, v8, v0
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vmerge.vvm v8, v8, v24, v0
+; RV64-NEXT: vmerge.vvm v8, v8, v16, v0
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vfmax.vv v24, v8, v24
+; RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: vmfeq.vv v0, v8, v8
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmfeq.vv v7, v16, v16
+; RV64-NEXT: vmfeq.vv v7, v24, v24
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v8, v8, v16, v0
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vmerge.vvm v16, v8, v24, v0
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v16, v16, v8, v0
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vmerge.vvm v24, v24, v8, v0
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vfmax.vv v16, v16, v8
+; RV64-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vfmax.vv v8, v0, v8
+; RV64-NEXT: vfmax.vv v16, v24, v16
; RV64-NEXT: vmfeq.vv v0, v16, v16
-; RV64-NEXT: vmfeq.vv v7, v24, v24
-; RV64-NEXT: vmerge.vvm v8, v16, v24, v0
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vmerge.vvm v16, v24, v16, v0
-; RV64-NEXT: vfmax.vv v8, v16, v8
+; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV64-NEXT: vmfeq.vv v0, v8, v8
+; RV64-NEXT: vmerge.vvm v8, v8, v16, v0
+; RV64-NEXT: vfmax.vv v8, v8, v24
; RV64-NEXT: vmfne.vv v16, v8, v8
; RV64-NEXT: vcpop.m a0, v16
; RV64-NEXT: beqz a0, .LBB161_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
index 3e77020ed0213..4b5d581e7b668 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
@@ -646,24 +646,24 @@ define signext i32 @vpreduce_xor_v64i32(i32 signext %s, <64 x i32> %v, <64 x i1>
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 4
+; CHECK-NEXT: vslidedown.vi v25, v0, 4
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bltu a1, a3, .LBB49_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: .LBB49_2:
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v24, a0
; CHECK-NEXT: addi a0, a1, -32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; CHECK-NEXT: vredxor.vs v25, v8, v25, v0.t
+; CHECK-NEXT: vredxor.vs v24, v8, v24, v0.t
; CHECK-NEXT: sltu a1, a1, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vredxor.vs v25, v16, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredxor.vs v24, v16, v24, v0.t
+; CHECK-NEXT: vmv.x.s a0, v24
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.xor.v64i32(i32 %s, <64 x i32> %v, <64 x i1> %m, i32 %evl)
ret i32 %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
index 8523ca957a8f5..447367f6a9f29 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
@@ -201,19 +201,16 @@ define zeroext i1 @vpreduce_and_v16i1(i1 zeroext %s, <16 x i1> %v, <16 x i1> %m,
define zeroext i1 @vpreduce_and_v256i1(i1 zeroext %s, <256 x i1> %v, <256 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_v256i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v11, v9
-; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: li a3, 128
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bltu a1, a3, .LBB14_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: .LBB14_2:
-; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; CHECK-NEXT: vmnot.m v9, v9
-; CHECK-NEXT: vcpop.m a2, v9, v0.t
+; CHECK-NEXT: vmnot.m v11, v0
+; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vcpop.m a2, v11, v0.t
; CHECK-NEXT: seqz a2, a2
; CHECK-NEXT: and a0, a2, a0
; CHECK-NEXT: addi a2, a1, -128
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
index 1d9ef739255ff..61543861583b8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
@@ -656,38 +656,38 @@ define <32 x double> @vp_rint_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroex
; RV32-LABEL: vp_rint_v32f64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v6, v0
+; RV32-NEXT: vmv1r.v v7, v0
; RV32-NEXT: li a2, 16
-; RV32-NEXT: vslidedown.vi v7, v0, 2
+; RV32-NEXT: vslidedown.vi v6, v0, 2
; RV32-NEXT: mv a1, a0
; RV32-NEXT: bltu a0, a2, .LBB26_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB26_2:
-; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: lui a2, %hi(.LCPI26_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
+; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vfabs.v v24, v8, v0.t
-; RV32-NEXT: lui a1, %hi(.LCPI26_0)
-; RV32-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
-; RV32-NEXT: addi a1, a0, -16
-; RV32-NEXT: sltu a0, a0, a1
+; RV32-NEXT: addi a2, a0, -16
+; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV32-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: and a0, a0, a2
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vfabs.v v24, v16, v0.t
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV32-NEXT: and a0, a0, a1
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vmv1r.v v0, v6
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vfabs.v v24, v16, v0.t
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32-NEXT: vfcvt.x.f.v v24, v16, v0.t
; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -697,39 +697,39 @@ define <32 x double> @vp_rint_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroex
; RV64-LABEL: vp_rint_v32f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v6, v0
+; RV64-NEXT: vmv1r.v v7, v0
; RV64-NEXT: li a2, 16
-; RV64-NEXT: vslidedown.vi v7, v0, 2
+; RV64-NEXT: vslidedown.vi v6, v0, 2
; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB26_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB26_2:
-; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vfabs.v v24, v8, v0.t
-; RV64-NEXT: li a1, 1075
-; RV64-NEXT: slli a1, a1, 52
-; RV64-NEXT: fmv.d.x fa5, a1
-; RV64-NEXT: addi a1, a0, -16
-; RV64-NEXT: sltu a0, a0, a1
+; RV64-NEXT: li a2, 1075
+; RV64-NEXT: slli a2, a2, 52
+; RV64-NEXT: fmv.d.x fa5, a2
+; RV64-NEXT: addi a2, a0, -16
+; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV64-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: sltu a0, a0, a2
; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a0, a0, a2
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vfabs.v v24, v16, v0.t
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV64-NEXT: and a0, a0, a1
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vmv1r.v v0, v6
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vfabs.v v24, v16, v0.t
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64-NEXT: vfcvt.x.f.v v24, v16, v0.t
; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -750,23 +750,20 @@ define <32 x double> @vp_rint_v32f64_unmasked(<32 x double> %va, i32 zeroext %ev
; RV32-NEXT: .LBB27_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vfabs.v v24, v8
-; RV32-NEXT: lui a2, %hi(.LCPI27_0)
-; RV32-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
-; RV32-NEXT: addi a2, a0, -16
-; RV32-NEXT: sltu a0, a0, a2
+; RV32-NEXT: lui a1, %hi(.LCPI27_0)
+; RV32-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
+; RV32-NEXT: addi a1, a0, -16
+; RV32-NEXT: sltu a0, a0, a1
; RV32-NEXT: addi a0, a0, -1
-; RV32-NEXT: and a0, a0, a2
+; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: vmflt.vf v0, v24, fa5
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vfabs.v v24, v16
-; RV32-NEXT: vmflt.vf v7, v24, fa5
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vfabs.v v24, v16
+; RV32-NEXT: vmflt.vf v0, v24, fa5
; RV32-NEXT: vfcvt.x.f.v v24, v16, v0.t
; RV32-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -783,24 +780,21 @@ define <32 x double> @vp_rint_v32f64_unmasked(<32 x double> %va, i32 zeroext %ev
; RV64-NEXT: .LBB27_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vfabs.v v24, v8
-; RV64-NEXT: li a2, 1075
-; RV64-NEXT: slli a2, a2, 52
-; RV64-NEXT: fmv.d.x fa5, a2
-; RV64-NEXT: addi a2, a0, -16
-; RV64-NEXT: sltu a0, a0, a2
+; RV64-NEXT: li a1, 1075
+; RV64-NEXT: slli a1, a1, 52
+; RV64-NEXT: fmv.d.x fa5, a1
+; RV64-NEXT: addi a1, a0, -16
+; RV64-NEXT: sltu a0, a0, a1
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: vmflt.vf v0, v24, fa5
-; RV64-NEXT: and a0, a0, a2
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vfabs.v v24, v16
-; RV64-NEXT: vmflt.vf v7, v24, fa5
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vfabs.v v24, v16
+; RV64-NEXT: vmflt.vf v0, v24, fa5
; RV64-NEXT: vfcvt.x.f.v v24, v16, v0.t
; RV64-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
index ebac7656be29a..dcb2fde553d58 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
@@ -16,9 +16,9 @@ define <2 x half> @vp_round_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl)
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -30,26 +30,24 @@ define <2 x half> @vp_round_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl)
; ZVFHMIN-LABEL: vp_round_v2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 4
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <2 x half> @llvm.vp.round.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl)
ret <2 x half> %v
@@ -63,8 +61,8 @@ define <2 x half> @vp_round_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -77,11 +75,11 @@ define <2 x half> @vp_round_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) {
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -102,9 +100,9 @@ define <4 x half> @vp_round_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl)
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -116,26 +114,24 @@ define <4 x half> @vp_round_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl)
; ZVFHMIN-LABEL: vp_round_v4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 4
-; ZVFHMIN-NEXT: vmv.v.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <4 x half> @llvm.vp.round.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)
ret <4 x half> %v
@@ -149,8 +145,8 @@ define <4 x half> @vp_round_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -163,11 +159,11 @@ define <4 x half> @vp_round_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -188,9 +184,9 @@ define <8 x half> @vp_round_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl)
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -205,21 +201,21 @@ define <8 x half> @vp_round_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl)
; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v13, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: fsrmi a0, 4
-; ZVFHMIN-NEXT: vmv1r.v v0, v13
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
+; ZVFHMIN-NEXT: vmv1r.v v0, v13
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: ret
@@ -235,8 +231,8 @@ define <8 x half> @vp_round_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -249,11 +245,11 @@ define <8 x half> @vp_round_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) {
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -293,21 +289,21 @@ define <16 x half> @vp_round_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %
; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: fsrmi a0, 4
-; ZVFHMIN-NEXT: vmv1r.v v0, v17
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vmv1r.v v0, v17
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
@@ -323,8 +319,8 @@ define <16 x half> @vp_round_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl)
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -337,11 +333,11 @@ define <16 x half> @vp_round_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl)
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -361,9 +357,9 @@ define <2 x float> @vp_round_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroext %ev
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -382,8 +378,8 @@ define <2 x float> @vp_round_v2f32_unmasked(<2 x float> %va, i32 zeroext %evl) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -401,9 +397,9 @@ define <4 x float> @vp_round_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %ev
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -422,8 +418,8 @@ define <4 x float> @vp_round_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -464,8 +460,8 @@ define <8 x float> @vp_round_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) {
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -506,8 +502,8 @@ define <16 x float> @vp_round_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -525,9 +521,9 @@ define <2 x double> @vp_round_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI16_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZVFH-NEXT: fsrmi a0, 4
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a0, 4
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
@@ -543,9 +539,9 @@ define <2 x double> @vp_round_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
+; RV64ZVFH-NEXT: fsrmi a0, 4
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZVFH-NEXT: fsrmi a0, 4
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
@@ -560,9 +556,9 @@ define <2 x double> @vp_round_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI16_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZVFHMIN-NEXT: fsrmi a0, 4
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a0, 4
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
@@ -578,9 +574,9 @@ define <2 x double> @vp_round_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
+; RV64ZVFHMIN-NEXT: fsrmi a0, 4
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a0, 4
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
@@ -599,8 +595,8 @@ define <2 x double> @vp_round_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl)
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI17_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -615,8 +611,8 @@ define <2 x double> @vp_round_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl)
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -630,8 +626,8 @@ define <2 x double> @vp_round_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl)
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI17_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -646,8 +642,8 @@ define <2 x double> @vp_round_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl)
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -747,8 +743,8 @@ define <4 x double> @vp_round_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl)
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI19_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZVFH-NEXT: vfabs.v v10, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -763,8 +759,8 @@ define <4 x double> @vp_round_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl)
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -778,8 +774,8 @@ define <4 x double> @vp_round_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl)
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI19_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v10, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -794,8 +790,8 @@ define <4 x double> @vp_round_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl)
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -895,8 +891,8 @@ define <8 x double> @vp_round_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI21_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZVFH-NEXT: vfabs.v v12, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -911,8 +907,8 @@ define <8 x double> @vp_round_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -926,8 +922,8 @@ define <8 x double> @vp_round_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI21_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v12, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -942,8 +938,8 @@ define <8 x double> @vp_round_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl)
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1043,8 +1039,8 @@ define <15 x double> @vp_round_v15f64_unmasked(<15 x double> %va, i32 zeroext %e
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI23_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1059,8 +1055,8 @@ define <15 x double> @vp_round_v15f64_unmasked(<15 x double> %va, i32 zeroext %e
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1074,8 +1070,8 @@ define <15 x double> @vp_round_v15f64_unmasked(<15 x double> %va, i32 zeroext %e
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI23_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1090,8 +1086,8 @@ define <15 x double> @vp_round_v15f64_unmasked(<15 x double> %va, i32 zeroext %e
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1191,8 +1187,8 @@ define <16 x double> @vp_round_v16f64_unmasked(<16 x double> %va, i32 zeroext %e
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1207,8 +1203,8 @@ define <16 x double> @vp_round_v16f64_unmasked(<16 x double> %va, i32 zeroext %e
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1222,8 +1218,8 @@ define <16 x double> @vp_round_v16f64_unmasked(<16 x double> %va, i32 zeroext %e
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1238,8 +1234,8 @@ define <16 x double> @vp_round_v16f64_unmasked(<16 x double> %va, i32 zeroext %e
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1254,43 +1250,43 @@ define <32 x double> @vp_round_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; RV32ZVFH-LABEL: vp_round_v32f64:
; RV32ZVFH: # %bb.0:
; RV32ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32ZVFH-NEXT: vmv1r.v v6, v0
+; RV32ZVFH-NEXT: vmv1r.v v7, v0
; RV32ZVFH-NEXT: li a2, 16
-; RV32ZVFH-NEXT: vslidedown.vi v7, v0, 2
+; RV32ZVFH-NEXT: vslidedown.vi v6, v0, 2
; RV32ZVFH-NEXT: mv a1, a0
; RV32ZVFH-NEXT: bltu a0, a2, .LBB26_2
; RV32ZVFH-NEXT: # %bb.1:
; RV32ZVFH-NEXT: li a1, 16
; RV32ZVFH-NEXT: .LBB26_2:
-; RV32ZVFH-NEXT: vmv1r.v v0, v6
+; RV32ZVFH-NEXT: vmv1r.v v0, v7
; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v8, v0.t
-; RV32ZVFH-NEXT: lui a1, %hi(.LCPI26_0)
-; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
-; RV32ZVFH-NEXT: addi a1, a0, -16
-; RV32ZVFH-NEXT: sltu a0, a0, a1
+; RV32ZVFH-NEXT: lui a2, %hi(.LCPI26_0)
+; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
+; RV32ZVFH-NEXT: addi a2, a0, -16
+; RV32ZVFH-NEXT: sltu a0, a0, a2
; RV32ZVFH-NEXT: addi a0, a0, -1
-; RV32ZVFH-NEXT: and a0, a0, a1
+; RV32ZVFH-NEXT: and a0, a0, a2
+; RV32ZVFH-NEXT: fsrmi a2, 4
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a1, 4
+; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV32ZVFH-NEXT: vmv1r.v v0, v6
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t
+; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV32ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV32ZVFH-NEXT: vmv1r.v v0, v7
+; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFH-NEXT: fsrm a1
+; RV32ZVFH-NEXT: fsrm a2
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFH-NEXT: vmv1r.v v0, v7
+; RV32ZVFH-NEXT: vmv1r.v v0, v6
+; RV32ZVFH-NEXT: fsrmi a1, 4
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a0, 4
-; RV32ZVFH-NEXT: vmv1r.v v0, v7
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFH-NEXT: fsrm a0
+; RV32ZVFH-NEXT: fsrm a1
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1299,44 +1295,44 @@ define <32 x double> @vp_round_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; RV64ZVFH-LABEL: vp_round_v32f64:
; RV64ZVFH: # %bb.0:
; RV64ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVFH-NEXT: vmv1r.v v6, v0
+; RV64ZVFH-NEXT: vmv1r.v v7, v0
; RV64ZVFH-NEXT: li a2, 16
-; RV64ZVFH-NEXT: vslidedown.vi v7, v0, 2
+; RV64ZVFH-NEXT: vslidedown.vi v6, v0, 2
; RV64ZVFH-NEXT: mv a1, a0
; RV64ZVFH-NEXT: bltu a0, a2, .LBB26_2
; RV64ZVFH-NEXT: # %bb.1:
; RV64ZVFH-NEXT: li a1, 16
; RV64ZVFH-NEXT: .LBB26_2:
-; RV64ZVFH-NEXT: vmv1r.v v0, v6
+; RV64ZVFH-NEXT: vmv1r.v v0, v7
; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v8, v0.t
-; RV64ZVFH-NEXT: li a1, 1075
-; RV64ZVFH-NEXT: slli a1, a1, 52
-; RV64ZVFH-NEXT: fmv.d.x fa5, a1
-; RV64ZVFH-NEXT: addi a1, a0, -16
-; RV64ZVFH-NEXT: sltu a0, a0, a1
+; RV64ZVFH-NEXT: li a2, 1075
+; RV64ZVFH-NEXT: slli a2, a2, 52
+; RV64ZVFH-NEXT: fmv.d.x fa5, a2
+; RV64ZVFH-NEXT: addi a2, a0, -16
+; RV64ZVFH-NEXT: sltu a0, a0, a2
; RV64ZVFH-NEXT: addi a0, a0, -1
+; RV64ZVFH-NEXT: and a0, a0, a2
+; RV64ZVFH-NEXT: fsrmi a2, 4
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV64ZVFH-NEXT: and a0, a0, a1
-; RV64ZVFH-NEXT: fsrmi a1, 4
+; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV64ZVFH-NEXT: vmv1r.v v0, v6
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t
+; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV64ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV64ZVFH-NEXT: vmv1r.v v0, v7
+; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFH-NEXT: fsrm a1
+; RV64ZVFH-NEXT: fsrm a2
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
+; RV64ZVFH-NEXT: fsrmi a1, 4
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFH-NEXT: vmv1r.v v0, v7
+; RV64ZVFH-NEXT: vmv1r.v v0, v6
; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV64ZVFH-NEXT: fsrmi a0, 4
-; RV64ZVFH-NEXT: vmv1r.v v0, v7
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFH-NEXT: fsrm a0
+; RV64ZVFH-NEXT: fsrm a1
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1345,43 +1341,43 @@ define <32 x double> @vp_round_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; RV32ZVFHMIN-LABEL: vp_round_v32f64:
; RV32ZVFHMIN: # %bb.0:
; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32ZVFHMIN-NEXT: vmv1r.v v6, v0
+; RV32ZVFHMIN-NEXT: vmv1r.v v7, v0
; RV32ZVFHMIN-NEXT: li a2, 16
-; RV32ZVFHMIN-NEXT: vslidedown.vi v7, v0, 2
+; RV32ZVFHMIN-NEXT: vslidedown.vi v6, v0, 2
; RV32ZVFHMIN-NEXT: mv a1, a0
; RV32ZVFHMIN-NEXT: bltu a0, a2, .LBB26_2
; RV32ZVFHMIN-NEXT: # %bb.1:
; RV32ZVFHMIN-NEXT: li a1, 16
; RV32ZVFHMIN-NEXT: .LBB26_2:
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI26_0)
-; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
-; RV32ZVFHMIN-NEXT: addi a1, a0, -16
-; RV32ZVFHMIN-NEXT: sltu a0, a0, a1
+; RV32ZVFHMIN-NEXT: lui a2, %hi(.LCPI26_0)
+; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
+; RV32ZVFHMIN-NEXT: addi a2, a0, -16
+; RV32ZVFHMIN-NEXT: sltu a0, a0, a2
; RV32ZVFHMIN-NEXT: addi a0, a0, -1
-; RV32ZVFHMIN-NEXT: and a0, a0, a1
+; RV32ZVFHMIN-NEXT: and a0, a0, a2
+; RV32ZVFHMIN-NEXT: fsrmi a2, 4
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a1, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
+; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV32ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a1
+; RV32ZVFHMIN-NEXT: fsrm a2
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV32ZVFHMIN-NEXT: fsrmi a1, 4
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a0, 4
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a0
+; RV32ZVFHMIN-NEXT: fsrm a1
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1390,44 +1386,44 @@ define <32 x double> @vp_round_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; RV64ZVFHMIN-LABEL: vp_round_v32f64:
; RV64ZVFHMIN: # %bb.0:
; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVFHMIN-NEXT: vmv1r.v v6, v0
+; RV64ZVFHMIN-NEXT: vmv1r.v v7, v0
; RV64ZVFHMIN-NEXT: li a2, 16
-; RV64ZVFHMIN-NEXT: vslidedown.vi v7, v0, 2
+; RV64ZVFHMIN-NEXT: vslidedown.vi v6, v0, 2
; RV64ZVFHMIN-NEXT: mv a1, a0
; RV64ZVFHMIN-NEXT: bltu a0, a2, .LBB26_2
; RV64ZVFHMIN-NEXT: # %bb.1:
; RV64ZVFHMIN-NEXT: li a1, 16
; RV64ZVFHMIN-NEXT: .LBB26_2:
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: li a1, 1075
-; RV64ZVFHMIN-NEXT: slli a1, a1, 52
-; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a1
-; RV64ZVFHMIN-NEXT: addi a1, a0, -16
-; RV64ZVFHMIN-NEXT: sltu a0, a0, a1
+; RV64ZVFHMIN-NEXT: li a2, 1075
+; RV64ZVFHMIN-NEXT: slli a2, a2, 52
+; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a2
+; RV64ZVFHMIN-NEXT: addi a2, a0, -16
+; RV64ZVFHMIN-NEXT: sltu a0, a0, a2
; RV64ZVFHMIN-NEXT: addi a0, a0, -1
+; RV64ZVFHMIN-NEXT: and a0, a0, a2
+; RV64ZVFHMIN-NEXT: fsrmi a2, 4
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV64ZVFHMIN-NEXT: and a0, a0, a1
-; RV64ZVFHMIN-NEXT: fsrmi a1, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
+; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV64ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a1
+; RV64ZVFHMIN-NEXT: fsrm a2
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
+; RV64ZVFHMIN-NEXT: fsrmi a1, 4
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a0, 4
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a0
+; RV64ZVFHMIN-NEXT: fsrm a1
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1447,28 +1443,25 @@ define <32 x double> @vp_round_v32f64_unmasked(<32 x double> %va, i32 zeroext %e
; RV32ZVFH-NEXT: .LBB27_2:
; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v8
-; RV32ZVFH-NEXT: lui a2, %hi(.LCPI27_0)
-; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
-; RV32ZVFH-NEXT: addi a2, a0, -16
-; RV32ZVFH-NEXT: sltu a0, a0, a2
+; RV32ZVFH-NEXT: lui a1, %hi(.LCPI27_0)
+; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
+; RV32ZVFH-NEXT: addi a1, a0, -16
+; RV32ZVFH-NEXT: sltu a0, a0, a1
; RV32ZVFH-NEXT: addi a0, a0, -1
-; RV32ZVFH-NEXT: and a0, a0, a2
-; RV32ZVFH-NEXT: fsrmi a2, 4
+; RV32ZVFH-NEXT: and a0, a0, a1
+; RV32ZVFH-NEXT: fsrmi a1, 4
; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFH-NEXT: vfabs.v v24, v16
-; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5
-; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFH-NEXT: fsrm a2
+; RV32ZVFH-NEXT: fsrm a1
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV32ZVFH-NEXT: fsrmi a1, 4
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFH-NEXT: vmv1r.v v0, v7
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFH-NEXT: vfabs.v v24, v16
+; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
+; RV32ZVFH-NEXT: fsrmi a0, 4
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFH-NEXT: fsrm a1
+; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1484,29 +1477,26 @@ define <32 x double> @vp_round_v32f64_unmasked(<32 x double> %va, i32 zeroext %e
; RV64ZVFH-NEXT: .LBB27_2:
; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v8
-; RV64ZVFH-NEXT: li a2, 1075
-; RV64ZVFH-NEXT: slli a2, a2, 52
-; RV64ZVFH-NEXT: fmv.d.x fa5, a2
-; RV64ZVFH-NEXT: addi a2, a0, -16
-; RV64ZVFH-NEXT: sltu a0, a0, a2
+; RV64ZVFH-NEXT: li a1, 1075
+; RV64ZVFH-NEXT: slli a1, a1, 52
+; RV64ZVFH-NEXT: fmv.d.x fa5, a1
+; RV64ZVFH-NEXT: addi a1, a0, -16
+; RV64ZVFH-NEXT: sltu a0, a0, a1
; RV64ZVFH-NEXT: addi a0, a0, -1
-; RV64ZVFH-NEXT: and a0, a0, a2
-; RV64ZVFH-NEXT: fsrmi a2, 4
+; RV64ZVFH-NEXT: and a0, a0, a1
+; RV64ZVFH-NEXT: fsrmi a1, 4
; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFH-NEXT: vfabs.v v24, v16
-; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5
-; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFH-NEXT: fsrm a2
+; RV64ZVFH-NEXT: fsrm a1
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV64ZVFH-NEXT: fsrmi a1, 4
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFH-NEXT: vmv1r.v v0, v7
; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFH-NEXT: vfabs.v v24, v16
+; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
+; RV64ZVFH-NEXT: fsrmi a0, 4
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFH-NEXT: fsrm a1
+; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1522,28 +1512,25 @@ define <32 x double> @vp_round_v32f64_unmasked(<32 x double> %va, i32 zeroext %e
; RV32ZVFHMIN-NEXT: .LBB27_2:
; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v8
-; RV32ZVFHMIN-NEXT: lui a2, %hi(.LCPI27_0)
-; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
-; RV32ZVFHMIN-NEXT: addi a2, a0, -16
-; RV32ZVFHMIN-NEXT: sltu a0, a0, a2
+; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI27_0)
+; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
+; RV32ZVFHMIN-NEXT: addi a1, a0, -16
+; RV32ZVFHMIN-NEXT: sltu a0, a0, a1
; RV32ZVFHMIN-NEXT: addi a0, a0, -1
-; RV32ZVFHMIN-NEXT: and a0, a0, a2
-; RV32ZVFHMIN-NEXT: fsrmi a2, 4
+; RV32ZVFHMIN-NEXT: and a0, a0, a1
+; RV32ZVFHMIN-NEXT: fsrmi a1, 4
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFHMIN-NEXT: vfabs.v v24, v16
-; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5
-; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a2
+; RV32ZVFHMIN-NEXT: fsrm a1
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a1, 4
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFHMIN-NEXT: vfabs.v v24, v16
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
+; RV32ZVFHMIN-NEXT: fsrmi a0, 4
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a1
+; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1559,29 +1546,26 @@ define <32 x double> @vp_round_v32f64_unmasked(<32 x double> %va, i32 zeroext %e
; RV64ZVFHMIN-NEXT: .LBB27_2:
; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v8
-; RV64ZVFHMIN-NEXT: li a2, 1075
-; RV64ZVFHMIN-NEXT: slli a2, a2, 52
-; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a2
-; RV64ZVFHMIN-NEXT: addi a2, a0, -16
-; RV64ZVFHMIN-NEXT: sltu a0, a0, a2
+; RV64ZVFHMIN-NEXT: li a1, 1075
+; RV64ZVFHMIN-NEXT: slli a1, a1, 52
+; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a1
+; RV64ZVFHMIN-NEXT: addi a1, a0, -16
+; RV64ZVFHMIN-NEXT: sltu a0, a0, a1
; RV64ZVFHMIN-NEXT: addi a0, a0, -1
-; RV64ZVFHMIN-NEXT: and a0, a0, a2
-; RV64ZVFHMIN-NEXT: fsrmi a2, 4
+; RV64ZVFHMIN-NEXT: and a0, a0, a1
+; RV64ZVFHMIN-NEXT: fsrmi a1, 4
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFHMIN-NEXT: vfabs.v v24, v16
-; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5
-; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a2
+; RV64ZVFHMIN-NEXT: fsrm a1
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a1, 4
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFHMIN-NEXT: vfabs.v v24, v16
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
+; RV64ZVFHMIN-NEXT: fsrmi a0, 4
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a1
+; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
index 43566185a200b..f398cb306559b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
@@ -16,9 +16,9 @@ define <2 x half> @vp_roundeven_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -30,26 +30,24 @@ define <2 x half> @vp_roundeven_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %
; ZVFHMIN-LABEL: vp_roundeven_v2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 0
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <2 x half> @llvm.vp.roundeven.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl)
ret <2 x half> %v
@@ -63,8 +61,8 @@ define <2 x half> @vp_roundeven_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl)
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -77,11 +75,11 @@ define <2 x half> @vp_roundeven_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl)
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -102,9 +100,9 @@ define <4 x half> @vp_roundeven_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -116,26 +114,24 @@ define <4 x half> @vp_roundeven_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %
; ZVFHMIN-LABEL: vp_roundeven_v4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 0
-; ZVFHMIN-NEXT: vmv.v.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <4 x half> @llvm.vp.roundeven.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)
ret <4 x half> %v
@@ -149,8 +145,8 @@ define <4 x half> @vp_roundeven_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl)
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -163,11 +159,11 @@ define <4 x half> @vp_roundeven_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl)
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -188,9 +184,9 @@ define <8 x half> @vp_roundeven_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -205,21 +201,21 @@ define <8 x half> @vp_roundeven_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %
; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v13, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: fsrmi a0, 0
-; ZVFHMIN-NEXT: vmv1r.v v0, v13
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
+; ZVFHMIN-NEXT: vmv1r.v v0, v13
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: ret
@@ -235,8 +231,8 @@ define <8 x half> @vp_roundeven_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl)
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -249,11 +245,11 @@ define <8 x half> @vp_roundeven_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl)
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -293,21 +289,21 @@ define <16 x half> @vp_roundeven_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroe
; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: fsrmi a0, 0
-; ZVFHMIN-NEXT: vmv1r.v v0, v17
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vmv1r.v v0, v17
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
@@ -323,8 +319,8 @@ define <16 x half> @vp_roundeven_v16f16_unmasked(<16 x half> %va, i32 zeroext %e
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -337,11 +333,11 @@ define <16 x half> @vp_roundeven_v16f16_unmasked(<16 x half> %va, i32 zeroext %e
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -361,9 +357,9 @@ define <2 x float> @vp_roundeven_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroext
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -382,8 +378,8 @@ define <2 x float> @vp_roundeven_v2f32_unmasked(<2 x float> %va, i32 zeroext %ev
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -401,9 +397,9 @@ define <4 x float> @vp_roundeven_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -422,8 +418,8 @@ define <4 x float> @vp_roundeven_v4f32_unmasked(<4 x float> %va, i32 zeroext %ev
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -464,8 +460,8 @@ define <8 x float> @vp_roundeven_v8f32_unmasked(<8 x float> %va, i32 zeroext %ev
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -506,8 +502,8 @@ define <16 x float> @vp_roundeven_v16f32_unmasked(<16 x float> %va, i32 zeroext
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -525,9 +521,9 @@ define <2 x double> @vp_roundeven_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroe
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI16_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZVFH-NEXT: fsrmi a0, 0
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a0, 0
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
@@ -543,9 +539,9 @@ define <2 x double> @vp_roundeven_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroe
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
+; RV64ZVFH-NEXT: fsrmi a0, 0
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZVFH-NEXT: fsrmi a0, 0
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
@@ -560,9 +556,9 @@ define <2 x double> @vp_roundeven_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroe
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI16_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZVFHMIN-NEXT: fsrmi a0, 0
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a0, 0
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
@@ -578,9 +574,9 @@ define <2 x double> @vp_roundeven_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroe
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
+; RV64ZVFHMIN-NEXT: fsrmi a0, 0
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a0, 0
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
@@ -599,8 +595,8 @@ define <2 x double> @vp_roundeven_v2f64_unmasked(<2 x double> %va, i32 zeroext %
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI17_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -615,8 +611,8 @@ define <2 x double> @vp_roundeven_v2f64_unmasked(<2 x double> %va, i32 zeroext %
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -630,8 +626,8 @@ define <2 x double> @vp_roundeven_v2f64_unmasked(<2 x double> %va, i32 zeroext %
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI17_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -646,8 +642,8 @@ define <2 x double> @vp_roundeven_v2f64_unmasked(<2 x double> %va, i32 zeroext %
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -747,8 +743,8 @@ define <4 x double> @vp_roundeven_v4f64_unmasked(<4 x double> %va, i32 zeroext %
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI19_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZVFH-NEXT: vfabs.v v10, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -763,8 +759,8 @@ define <4 x double> @vp_roundeven_v4f64_unmasked(<4 x double> %va, i32 zeroext %
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -778,8 +774,8 @@ define <4 x double> @vp_roundeven_v4f64_unmasked(<4 x double> %va, i32 zeroext %
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI19_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v10, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -794,8 +790,8 @@ define <4 x double> @vp_roundeven_v4f64_unmasked(<4 x double> %va, i32 zeroext %
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -895,8 +891,8 @@ define <8 x double> @vp_roundeven_v8f64_unmasked(<8 x double> %va, i32 zeroext %
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI21_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZVFH-NEXT: vfabs.v v12, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -911,8 +907,8 @@ define <8 x double> @vp_roundeven_v8f64_unmasked(<8 x double> %va, i32 zeroext %
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -926,8 +922,8 @@ define <8 x double> @vp_roundeven_v8f64_unmasked(<8 x double> %va, i32 zeroext %
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI21_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v12, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -942,8 +938,8 @@ define <8 x double> @vp_roundeven_v8f64_unmasked(<8 x double> %va, i32 zeroext %
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1043,8 +1039,8 @@ define <15 x double> @vp_roundeven_v15f64_unmasked(<15 x double> %va, i32 zeroex
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI23_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1059,8 +1055,8 @@ define <15 x double> @vp_roundeven_v15f64_unmasked(<15 x double> %va, i32 zeroex
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1074,8 +1070,8 @@ define <15 x double> @vp_roundeven_v15f64_unmasked(<15 x double> %va, i32 zeroex
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI23_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1090,8 +1086,8 @@ define <15 x double> @vp_roundeven_v15f64_unmasked(<15 x double> %va, i32 zeroex
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1191,8 +1187,8 @@ define <16 x double> @vp_roundeven_v16f64_unmasked(<16 x double> %va, i32 zeroex
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1207,8 +1203,8 @@ define <16 x double> @vp_roundeven_v16f64_unmasked(<16 x double> %va, i32 zeroex
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1222,8 +1218,8 @@ define <16 x double> @vp_roundeven_v16f64_unmasked(<16 x double> %va, i32 zeroex
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1238,8 +1234,8 @@ define <16 x double> @vp_roundeven_v16f64_unmasked(<16 x double> %va, i32 zeroex
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1254,43 +1250,43 @@ define <32 x double> @vp_roundeven_v32f64(<32 x double> %va, <32 x i1> %m, i32 z
; RV32ZVFH-LABEL: vp_roundeven_v32f64:
; RV32ZVFH: # %bb.0:
; RV32ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32ZVFH-NEXT: vmv1r.v v6, v0
+; RV32ZVFH-NEXT: vmv1r.v v7, v0
; RV32ZVFH-NEXT: li a2, 16
-; RV32ZVFH-NEXT: vslidedown.vi v7, v0, 2
+; RV32ZVFH-NEXT: vslidedown.vi v6, v0, 2
; RV32ZVFH-NEXT: mv a1, a0
; RV32ZVFH-NEXT: bltu a0, a2, .LBB26_2
; RV32ZVFH-NEXT: # %bb.1:
; RV32ZVFH-NEXT: li a1, 16
; RV32ZVFH-NEXT: .LBB26_2:
-; RV32ZVFH-NEXT: vmv1r.v v0, v6
+; RV32ZVFH-NEXT: vmv1r.v v0, v7
; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v8, v0.t
-; RV32ZVFH-NEXT: lui a1, %hi(.LCPI26_0)
-; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
-; RV32ZVFH-NEXT: addi a1, a0, -16
-; RV32ZVFH-NEXT: sltu a0, a0, a1
+; RV32ZVFH-NEXT: lui a2, %hi(.LCPI26_0)
+; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
+; RV32ZVFH-NEXT: addi a2, a0, -16
+; RV32ZVFH-NEXT: sltu a0, a0, a2
; RV32ZVFH-NEXT: addi a0, a0, -1
-; RV32ZVFH-NEXT: and a0, a0, a1
+; RV32ZVFH-NEXT: and a0, a0, a2
+; RV32ZVFH-NEXT: fsrmi a2, 0
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a1, 0
+; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV32ZVFH-NEXT: vmv1r.v v0, v6
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t
+; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV32ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV32ZVFH-NEXT: vmv1r.v v0, v7
+; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFH-NEXT: fsrm a1
+; RV32ZVFH-NEXT: fsrm a2
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFH-NEXT: vmv1r.v v0, v7
+; RV32ZVFH-NEXT: vmv1r.v v0, v6
+; RV32ZVFH-NEXT: fsrmi a1, 0
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a0, 0
-; RV32ZVFH-NEXT: vmv1r.v v0, v7
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFH-NEXT: fsrm a0
+; RV32ZVFH-NEXT: fsrm a1
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1299,44 +1295,44 @@ define <32 x double> @vp_roundeven_v32f64(<32 x double> %va, <32 x i1> %m, i32 z
; RV64ZVFH-LABEL: vp_roundeven_v32f64:
; RV64ZVFH: # %bb.0:
; RV64ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVFH-NEXT: vmv1r.v v6, v0
+; RV64ZVFH-NEXT: vmv1r.v v7, v0
; RV64ZVFH-NEXT: li a2, 16
-; RV64ZVFH-NEXT: vslidedown.vi v7, v0, 2
+; RV64ZVFH-NEXT: vslidedown.vi v6, v0, 2
; RV64ZVFH-NEXT: mv a1, a0
; RV64ZVFH-NEXT: bltu a0, a2, .LBB26_2
; RV64ZVFH-NEXT: # %bb.1:
; RV64ZVFH-NEXT: li a1, 16
; RV64ZVFH-NEXT: .LBB26_2:
-; RV64ZVFH-NEXT: vmv1r.v v0, v6
+; RV64ZVFH-NEXT: vmv1r.v v0, v7
; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v8, v0.t
-; RV64ZVFH-NEXT: li a1, 1075
-; RV64ZVFH-NEXT: slli a1, a1, 52
-; RV64ZVFH-NEXT: fmv.d.x fa5, a1
-; RV64ZVFH-NEXT: addi a1, a0, -16
-; RV64ZVFH-NEXT: sltu a0, a0, a1
+; RV64ZVFH-NEXT: li a2, 1075
+; RV64ZVFH-NEXT: slli a2, a2, 52
+; RV64ZVFH-NEXT: fmv.d.x fa5, a2
+; RV64ZVFH-NEXT: addi a2, a0, -16
+; RV64ZVFH-NEXT: sltu a0, a0, a2
; RV64ZVFH-NEXT: addi a0, a0, -1
+; RV64ZVFH-NEXT: and a0, a0, a2
+; RV64ZVFH-NEXT: fsrmi a2, 0
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV64ZVFH-NEXT: and a0, a0, a1
-; RV64ZVFH-NEXT: fsrmi a1, 0
+; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV64ZVFH-NEXT: vmv1r.v v0, v6
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t
+; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV64ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV64ZVFH-NEXT: vmv1r.v v0, v7
+; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFH-NEXT: fsrm a1
+; RV64ZVFH-NEXT: fsrm a2
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
+; RV64ZVFH-NEXT: fsrmi a1, 0
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFH-NEXT: vmv1r.v v0, v7
+; RV64ZVFH-NEXT: vmv1r.v v0, v6
; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV64ZVFH-NEXT: fsrmi a0, 0
-; RV64ZVFH-NEXT: vmv1r.v v0, v7
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFH-NEXT: fsrm a0
+; RV64ZVFH-NEXT: fsrm a1
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1345,43 +1341,43 @@ define <32 x double> @vp_roundeven_v32f64(<32 x double> %va, <32 x i1> %m, i32 z
; RV32ZVFHMIN-LABEL: vp_roundeven_v32f64:
; RV32ZVFHMIN: # %bb.0:
; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32ZVFHMIN-NEXT: vmv1r.v v6, v0
+; RV32ZVFHMIN-NEXT: vmv1r.v v7, v0
; RV32ZVFHMIN-NEXT: li a2, 16
-; RV32ZVFHMIN-NEXT: vslidedown.vi v7, v0, 2
+; RV32ZVFHMIN-NEXT: vslidedown.vi v6, v0, 2
; RV32ZVFHMIN-NEXT: mv a1, a0
; RV32ZVFHMIN-NEXT: bltu a0, a2, .LBB26_2
; RV32ZVFHMIN-NEXT: # %bb.1:
; RV32ZVFHMIN-NEXT: li a1, 16
; RV32ZVFHMIN-NEXT: .LBB26_2:
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI26_0)
-; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
-; RV32ZVFHMIN-NEXT: addi a1, a0, -16
-; RV32ZVFHMIN-NEXT: sltu a0, a0, a1
+; RV32ZVFHMIN-NEXT: lui a2, %hi(.LCPI26_0)
+; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
+; RV32ZVFHMIN-NEXT: addi a2, a0, -16
+; RV32ZVFHMIN-NEXT: sltu a0, a0, a2
; RV32ZVFHMIN-NEXT: addi a0, a0, -1
-; RV32ZVFHMIN-NEXT: and a0, a0, a1
+; RV32ZVFHMIN-NEXT: and a0, a0, a2
+; RV32ZVFHMIN-NEXT: fsrmi a2, 0
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a1, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
+; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV32ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a1
+; RV32ZVFHMIN-NEXT: fsrm a2
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV32ZVFHMIN-NEXT: fsrmi a1, 0
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a0, 0
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a0
+; RV32ZVFHMIN-NEXT: fsrm a1
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1390,44 +1386,44 @@ define <32 x double> @vp_roundeven_v32f64(<32 x double> %va, <32 x i1> %m, i32 z
; RV64ZVFHMIN-LABEL: vp_roundeven_v32f64:
; RV64ZVFHMIN: # %bb.0:
; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVFHMIN-NEXT: vmv1r.v v6, v0
+; RV64ZVFHMIN-NEXT: vmv1r.v v7, v0
; RV64ZVFHMIN-NEXT: li a2, 16
-; RV64ZVFHMIN-NEXT: vslidedown.vi v7, v0, 2
+; RV64ZVFHMIN-NEXT: vslidedown.vi v6, v0, 2
; RV64ZVFHMIN-NEXT: mv a1, a0
; RV64ZVFHMIN-NEXT: bltu a0, a2, .LBB26_2
; RV64ZVFHMIN-NEXT: # %bb.1:
; RV64ZVFHMIN-NEXT: li a1, 16
; RV64ZVFHMIN-NEXT: .LBB26_2:
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: li a1, 1075
-; RV64ZVFHMIN-NEXT: slli a1, a1, 52
-; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a1
-; RV64ZVFHMIN-NEXT: addi a1, a0, -16
-; RV64ZVFHMIN-NEXT: sltu a0, a0, a1
+; RV64ZVFHMIN-NEXT: li a2, 1075
+; RV64ZVFHMIN-NEXT: slli a2, a2, 52
+; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a2
+; RV64ZVFHMIN-NEXT: addi a2, a0, -16
+; RV64ZVFHMIN-NEXT: sltu a0, a0, a2
; RV64ZVFHMIN-NEXT: addi a0, a0, -1
+; RV64ZVFHMIN-NEXT: and a0, a0, a2
+; RV64ZVFHMIN-NEXT: fsrmi a2, 0
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV64ZVFHMIN-NEXT: and a0, a0, a1
-; RV64ZVFHMIN-NEXT: fsrmi a1, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
+; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV64ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a1
+; RV64ZVFHMIN-NEXT: fsrm a2
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
+; RV64ZVFHMIN-NEXT: fsrmi a1, 0
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a0, 0
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a0
+; RV64ZVFHMIN-NEXT: fsrm a1
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1447,28 +1443,25 @@ define <32 x double> @vp_roundeven_v32f64_unmasked(<32 x double> %va, i32 zeroex
; RV32ZVFH-NEXT: .LBB27_2:
; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v8
-; RV32ZVFH-NEXT: lui a2, %hi(.LCPI27_0)
-; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
-; RV32ZVFH-NEXT: addi a2, a0, -16
-; RV32ZVFH-NEXT: sltu a0, a0, a2
+; RV32ZVFH-NEXT: lui a1, %hi(.LCPI27_0)
+; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
+; RV32ZVFH-NEXT: addi a1, a0, -16
+; RV32ZVFH-NEXT: sltu a0, a0, a1
; RV32ZVFH-NEXT: addi a0, a0, -1
-; RV32ZVFH-NEXT: and a0, a0, a2
-; RV32ZVFH-NEXT: fsrmi a2, 0
+; RV32ZVFH-NEXT: and a0, a0, a1
+; RV32ZVFH-NEXT: fsrmi a1, 0
; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFH-NEXT: vfabs.v v24, v16
-; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5
-; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFH-NEXT: fsrm a2
+; RV32ZVFH-NEXT: fsrm a1
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV32ZVFH-NEXT: fsrmi a1, 0
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFH-NEXT: vmv1r.v v0, v7
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFH-NEXT: vfabs.v v24, v16
+; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
+; RV32ZVFH-NEXT: fsrmi a0, 0
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFH-NEXT: fsrm a1
+; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1484,29 +1477,26 @@ define <32 x double> @vp_roundeven_v32f64_unmasked(<32 x double> %va, i32 zeroex
; RV64ZVFH-NEXT: .LBB27_2:
; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v8
-; RV64ZVFH-NEXT: li a2, 1075
-; RV64ZVFH-NEXT: slli a2, a2, 52
-; RV64ZVFH-NEXT: fmv.d.x fa5, a2
-; RV64ZVFH-NEXT: addi a2, a0, -16
-; RV64ZVFH-NEXT: sltu a0, a0, a2
+; RV64ZVFH-NEXT: li a1, 1075
+; RV64ZVFH-NEXT: slli a1, a1, 52
+; RV64ZVFH-NEXT: fmv.d.x fa5, a1
+; RV64ZVFH-NEXT: addi a1, a0, -16
+; RV64ZVFH-NEXT: sltu a0, a0, a1
; RV64ZVFH-NEXT: addi a0, a0, -1
-; RV64ZVFH-NEXT: and a0, a0, a2
-; RV64ZVFH-NEXT: fsrmi a2, 0
+; RV64ZVFH-NEXT: and a0, a0, a1
+; RV64ZVFH-NEXT: fsrmi a1, 0
; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFH-NEXT: vfabs.v v24, v16
-; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5
-; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFH-NEXT: fsrm a2
+; RV64ZVFH-NEXT: fsrm a1
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV64ZVFH-NEXT: fsrmi a1, 0
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFH-NEXT: vmv1r.v v0, v7
; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFH-NEXT: vfabs.v v24, v16
+; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
+; RV64ZVFH-NEXT: fsrmi a0, 0
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFH-NEXT: fsrm a1
+; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1522,28 +1512,25 @@ define <32 x double> @vp_roundeven_v32f64_unmasked(<32 x double> %va, i32 zeroex
; RV32ZVFHMIN-NEXT: .LBB27_2:
; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v8
-; RV32ZVFHMIN-NEXT: lui a2, %hi(.LCPI27_0)
-; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
-; RV32ZVFHMIN-NEXT: addi a2, a0, -16
-; RV32ZVFHMIN-NEXT: sltu a0, a0, a2
+; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI27_0)
+; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
+; RV32ZVFHMIN-NEXT: addi a1, a0, -16
+; RV32ZVFHMIN-NEXT: sltu a0, a0, a1
; RV32ZVFHMIN-NEXT: addi a0, a0, -1
-; RV32ZVFHMIN-NEXT: and a0, a0, a2
-; RV32ZVFHMIN-NEXT: fsrmi a2, 0
+; RV32ZVFHMIN-NEXT: and a0, a0, a1
+; RV32ZVFHMIN-NEXT: fsrmi a1, 0
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFHMIN-NEXT: vfabs.v v24, v16
-; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5
-; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a2
+; RV32ZVFHMIN-NEXT: fsrm a1
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a1, 0
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFHMIN-NEXT: vfabs.v v24, v16
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
+; RV32ZVFHMIN-NEXT: fsrmi a0, 0
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a1
+; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1559,29 +1546,26 @@ define <32 x double> @vp_roundeven_v32f64_unmasked(<32 x double> %va, i32 zeroex
; RV64ZVFHMIN-NEXT: .LBB27_2:
; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v8
-; RV64ZVFHMIN-NEXT: li a2, 1075
-; RV64ZVFHMIN-NEXT: slli a2, a2, 52
-; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a2
-; RV64ZVFHMIN-NEXT: addi a2, a0, -16
-; RV64ZVFHMIN-NEXT: sltu a0, a0, a2
+; RV64ZVFHMIN-NEXT: li a1, 1075
+; RV64ZVFHMIN-NEXT: slli a1, a1, 52
+; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a1
+; RV64ZVFHMIN-NEXT: addi a1, a0, -16
+; RV64ZVFHMIN-NEXT: sltu a0, a0, a1
; RV64ZVFHMIN-NEXT: addi a0, a0, -1
-; RV64ZVFHMIN-NEXT: and a0, a0, a2
-; RV64ZVFHMIN-NEXT: fsrmi a2, 0
+; RV64ZVFHMIN-NEXT: and a0, a0, a1
+; RV64ZVFHMIN-NEXT: fsrmi a1, 0
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFHMIN-NEXT: vfabs.v v24, v16
-; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5
-; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a2
+; RV64ZVFHMIN-NEXT: fsrm a1
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a1, 0
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFHMIN-NEXT: vfabs.v v24, v16
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
+; RV64ZVFHMIN-NEXT: fsrmi a0, 0
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a1
+; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
index 7cae17e8e1ec7..bfbf6c8371a4e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
@@ -16,9 +16,9 @@ define <2 x half> @vp_roundtozero_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 1
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 1
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -30,26 +30,24 @@ define <2 x half> @vp_roundtozero_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext
; ZVFHMIN-LABEL: vp_roundtozero_v2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 1
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <2 x half> @llvm.vp.roundtozero.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl)
ret <2 x half> %v
@@ -63,8 +61,8 @@ define <2 x half> @vp_roundtozero_v2f16_unmasked(<2 x half> %va, i32 zeroext %ev
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 1
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -77,11 +75,11 @@ define <2 x half> @vp_roundtozero_v2f16_unmasked(<2 x half> %va, i32 zeroext %ev
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -102,9 +100,9 @@ define <4 x half> @vp_roundtozero_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 1
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 1
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -116,26 +114,24 @@ define <4 x half> @vp_roundtozero_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext
; ZVFHMIN-LABEL: vp_roundtozero_v4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 1
-; ZVFHMIN-NEXT: vmv.v.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <4 x half> @llvm.vp.roundtozero.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)
ret <4 x half> %v
@@ -149,8 +145,8 @@ define <4 x half> @vp_roundtozero_v4f16_unmasked(<4 x half> %va, i32 zeroext %ev
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 1
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -163,11 +159,11 @@ define <4 x half> @vp_roundtozero_v4f16_unmasked(<4 x half> %va, i32 zeroext %ev
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -188,9 +184,9 @@ define <8 x half> @vp_roundtozero_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 1
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 1
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -205,21 +201,21 @@ define <8 x half> @vp_roundtozero_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext
; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v13, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: fsrmi a0, 1
-; ZVFHMIN-NEXT: vmv1r.v v0, v13
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
+; ZVFHMIN-NEXT: vmv1r.v v0, v13
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: ret
@@ -235,8 +231,8 @@ define <8 x half> @vp_roundtozero_v8f16_unmasked(<8 x half> %va, i32 zeroext %ev
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 1
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -249,11 +245,11 @@ define <8 x half> @vp_roundtozero_v8f16_unmasked(<8 x half> %va, i32 zeroext %ev
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -293,21 +289,21 @@ define <16 x half> @vp_roundtozero_v16f16(<16 x half> %va, <16 x i1> %m, i32 zer
; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: fsrmi a0, 1
-; ZVFHMIN-NEXT: vmv1r.v v0, v17
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vmv1r.v v0, v17
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
@@ -323,8 +319,8 @@ define <16 x half> @vp_roundtozero_v16f16_unmasked(<16 x half> %va, i32 zeroext
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 1
+; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -337,11 +333,11 @@ define <16 x half> @vp_roundtozero_v16f16_unmasked(<16 x half> %va, i32 zeroext
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -361,9 +357,9 @@ define <2 x float> @vp_roundtozero_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroe
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -382,8 +378,8 @@ define <2 x float> @vp_roundtozero_v2f32_unmasked(<2 x float> %va, i32 zeroext %
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 1
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -401,9 +397,9 @@ define <4 x float> @vp_roundtozero_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroe
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -422,8 +418,8 @@ define <4 x float> @vp_roundtozero_v4f32_unmasked(<4 x float> %va, i32 zeroext %
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 1
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -464,8 +460,8 @@ define <8 x float> @vp_roundtozero_v8f32_unmasked(<8 x float> %va, i32 zeroext %
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 1
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -506,8 +502,8 @@ define <16 x float> @vp_roundtozero_v16f32_unmasked(<16 x float> %va, i32 zeroex
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 1
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -525,9 +521,9 @@ define <2 x double> @vp_roundtozero_v2f64(<2 x double> %va, <2 x i1> %m, i32 zer
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI16_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZVFH-NEXT: fsrmi a0, 1
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a0, 1
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
@@ -543,9 +539,9 @@ define <2 x double> @vp_roundtozero_v2f64(<2 x double> %va, <2 x i1> %m, i32 zer
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
+; RV64ZVFH-NEXT: fsrmi a0, 1
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZVFH-NEXT: fsrmi a0, 1
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
@@ -560,9 +556,9 @@ define <2 x double> @vp_roundtozero_v2f64(<2 x double> %va, <2 x i1> %m, i32 zer
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI16_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZVFHMIN-NEXT: fsrmi a0, 1
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a0, 1
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
@@ -578,9 +574,9 @@ define <2 x double> @vp_roundtozero_v2f64(<2 x double> %va, <2 x i1> %m, i32 zer
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
+; RV64ZVFHMIN-NEXT: fsrmi a0, 1
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a0, 1
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
@@ -599,8 +595,8 @@ define <2 x double> @vp_roundtozero_v2f64_unmasked(<2 x double> %va, i32 zeroext
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI17_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: fsrmi a0, 1
+; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -615,8 +611,8 @@ define <2 x double> @vp_roundtozero_v2f64_unmasked(<2 x double> %va, i32 zeroext
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: fsrmi a0, 1
+; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -630,8 +626,8 @@ define <2 x double> @vp_roundtozero_v2f64_unmasked(<2 x double> %va, i32 zeroext
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI17_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 1
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -646,8 +642,8 @@ define <2 x double> @vp_roundtozero_v2f64_unmasked(<2 x double> %va, i32 zeroext
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 1
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -747,8 +743,8 @@ define <4 x double> @vp_roundtozero_v4f64_unmasked(<4 x double> %va, i32 zeroext
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI19_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZVFH-NEXT: vfabs.v v10, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: fsrmi a0, 1
+; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -763,8 +759,8 @@ define <4 x double> @vp_roundtozero_v4f64_unmasked(<4 x double> %va, i32 zeroext
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: fsrmi a0, 1
+; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -778,8 +774,8 @@ define <4 x double> @vp_roundtozero_v4f64_unmasked(<4 x double> %va, i32 zeroext
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI19_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v10, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 1
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -794,8 +790,8 @@ define <4 x double> @vp_roundtozero_v4f64_unmasked(<4 x double> %va, i32 zeroext
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 1
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -895,8 +891,8 @@ define <8 x double> @vp_roundtozero_v8f64_unmasked(<8 x double> %va, i32 zeroext
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI21_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZVFH-NEXT: vfabs.v v12, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: fsrmi a0, 1
+; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -911,8 +907,8 @@ define <8 x double> @vp_roundtozero_v8f64_unmasked(<8 x double> %va, i32 zeroext
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: fsrmi a0, 1
+; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -926,8 +922,8 @@ define <8 x double> @vp_roundtozero_v8f64_unmasked(<8 x double> %va, i32 zeroext
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI21_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v12, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 1
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -942,8 +938,8 @@ define <8 x double> @vp_roundtozero_v8f64_unmasked(<8 x double> %va, i32 zeroext
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 1
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1043,8 +1039,8 @@ define <15 x double> @vp_roundtozero_v15f64_unmasked(<15 x double> %va, i32 zero
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI23_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 1
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1059,8 +1055,8 @@ define <15 x double> @vp_roundtozero_v15f64_unmasked(<15 x double> %va, i32 zero
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 1
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1074,8 +1070,8 @@ define <15 x double> @vp_roundtozero_v15f64_unmasked(<15 x double> %va, i32 zero
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI23_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 1
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1090,8 +1086,8 @@ define <15 x double> @vp_roundtozero_v15f64_unmasked(<15 x double> %va, i32 zero
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 1
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1191,8 +1187,8 @@ define <16 x double> @vp_roundtozero_v16f64_unmasked(<16 x double> %va, i32 zero
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 1
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1207,8 +1203,8 @@ define <16 x double> @vp_roundtozero_v16f64_unmasked(<16 x double> %va, i32 zero
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 1
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1222,8 +1218,8 @@ define <16 x double> @vp_roundtozero_v16f64_unmasked(<16 x double> %va, i32 zero
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI25_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 1
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1238,8 +1234,8 @@ define <16 x double> @vp_roundtozero_v16f64_unmasked(<16 x double> %va, i32 zero
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 1
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1254,43 +1250,43 @@ define <32 x double> @vp_roundtozero_v32f64(<32 x double> %va, <32 x i1> %m, i32
; RV32ZVFH-LABEL: vp_roundtozero_v32f64:
; RV32ZVFH: # %bb.0:
; RV32ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32ZVFH-NEXT: vmv1r.v v6, v0
+; RV32ZVFH-NEXT: vmv1r.v v7, v0
; RV32ZVFH-NEXT: li a2, 16
-; RV32ZVFH-NEXT: vslidedown.vi v7, v0, 2
+; RV32ZVFH-NEXT: vslidedown.vi v6, v0, 2
; RV32ZVFH-NEXT: mv a1, a0
; RV32ZVFH-NEXT: bltu a0, a2, .LBB26_2
; RV32ZVFH-NEXT: # %bb.1:
; RV32ZVFH-NEXT: li a1, 16
; RV32ZVFH-NEXT: .LBB26_2:
-; RV32ZVFH-NEXT: vmv1r.v v0, v6
+; RV32ZVFH-NEXT: vmv1r.v v0, v7
; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v8, v0.t
-; RV32ZVFH-NEXT: lui a1, %hi(.LCPI26_0)
-; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
-; RV32ZVFH-NEXT: addi a1, a0, -16
-; RV32ZVFH-NEXT: sltu a0, a0, a1
+; RV32ZVFH-NEXT: lui a2, %hi(.LCPI26_0)
+; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
+; RV32ZVFH-NEXT: addi a2, a0, -16
+; RV32ZVFH-NEXT: sltu a0, a0, a2
; RV32ZVFH-NEXT: addi a0, a0, -1
-; RV32ZVFH-NEXT: and a0, a0, a1
+; RV32ZVFH-NEXT: and a0, a0, a2
+; RV32ZVFH-NEXT: fsrmi a2, 1
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a1, 1
+; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV32ZVFH-NEXT: vmv1r.v v0, v6
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t
+; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV32ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV32ZVFH-NEXT: vmv1r.v v0, v7
+; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFH-NEXT: fsrm a1
+; RV32ZVFH-NEXT: fsrm a2
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFH-NEXT: vmv1r.v v0, v7
+; RV32ZVFH-NEXT: vmv1r.v v0, v6
+; RV32ZVFH-NEXT: fsrmi a1, 1
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a0, 1
-; RV32ZVFH-NEXT: vmv1r.v v0, v7
-; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFH-NEXT: fsrm a0
+; RV32ZVFH-NEXT: fsrm a1
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1299,44 +1295,44 @@ define <32 x double> @vp_roundtozero_v32f64(<32 x double> %va, <32 x i1> %m, i32
; RV64ZVFH-LABEL: vp_roundtozero_v32f64:
; RV64ZVFH: # %bb.0:
; RV64ZVFH-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVFH-NEXT: vmv1r.v v6, v0
+; RV64ZVFH-NEXT: vmv1r.v v7, v0
; RV64ZVFH-NEXT: li a2, 16
-; RV64ZVFH-NEXT: vslidedown.vi v7, v0, 2
+; RV64ZVFH-NEXT: vslidedown.vi v6, v0, 2
; RV64ZVFH-NEXT: mv a1, a0
; RV64ZVFH-NEXT: bltu a0, a2, .LBB26_2
; RV64ZVFH-NEXT: # %bb.1:
; RV64ZVFH-NEXT: li a1, 16
; RV64ZVFH-NEXT: .LBB26_2:
-; RV64ZVFH-NEXT: vmv1r.v v0, v6
+; RV64ZVFH-NEXT: vmv1r.v v0, v7
; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v8, v0.t
-; RV64ZVFH-NEXT: li a1, 1075
-; RV64ZVFH-NEXT: slli a1, a1, 52
-; RV64ZVFH-NEXT: fmv.d.x fa5, a1
-; RV64ZVFH-NEXT: addi a1, a0, -16
-; RV64ZVFH-NEXT: sltu a0, a0, a1
+; RV64ZVFH-NEXT: li a2, 1075
+; RV64ZVFH-NEXT: slli a2, a2, 52
+; RV64ZVFH-NEXT: fmv.d.x fa5, a2
+; RV64ZVFH-NEXT: addi a2, a0, -16
+; RV64ZVFH-NEXT: sltu a0, a0, a2
; RV64ZVFH-NEXT: addi a0, a0, -1
+; RV64ZVFH-NEXT: and a0, a0, a2
+; RV64ZVFH-NEXT: fsrmi a2, 1
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV64ZVFH-NEXT: and a0, a0, a1
-; RV64ZVFH-NEXT: fsrmi a1, 1
+; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV64ZVFH-NEXT: vmv1r.v v0, v6
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t
+; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV64ZVFH-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV64ZVFH-NEXT: vmv1r.v v0, v7
+; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFH-NEXT: fsrm a1
+; RV64ZVFH-NEXT: fsrm a2
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
+; RV64ZVFH-NEXT: fsrmi a1, 1
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFH-NEXT: vmv1r.v v0, v7
+; RV64ZVFH-NEXT: vmv1r.v v0, v6
; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV64ZVFH-NEXT: fsrmi a0, 1
-; RV64ZVFH-NEXT: vmv1r.v v0, v7
-; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFH-NEXT: fsrm a0
+; RV64ZVFH-NEXT: fsrm a1
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1345,43 +1341,43 @@ define <32 x double> @vp_roundtozero_v32f64(<32 x double> %va, <32 x i1> %m, i32
; RV32ZVFHMIN-LABEL: vp_roundtozero_v32f64:
; RV32ZVFHMIN: # %bb.0:
; RV32ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32ZVFHMIN-NEXT: vmv1r.v v6, v0
+; RV32ZVFHMIN-NEXT: vmv1r.v v7, v0
; RV32ZVFHMIN-NEXT: li a2, 16
-; RV32ZVFHMIN-NEXT: vslidedown.vi v7, v0, 2
+; RV32ZVFHMIN-NEXT: vslidedown.vi v6, v0, 2
; RV32ZVFHMIN-NEXT: mv a1, a0
; RV32ZVFHMIN-NEXT: bltu a0, a2, .LBB26_2
; RV32ZVFHMIN-NEXT: # %bb.1:
; RV32ZVFHMIN-NEXT: li a1, 16
; RV32ZVFHMIN-NEXT: .LBB26_2:
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI26_0)
-; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI26_0)(a1)
-; RV32ZVFHMIN-NEXT: addi a1, a0, -16
-; RV32ZVFHMIN-NEXT: sltu a0, a0, a1
+; RV32ZVFHMIN-NEXT: lui a2, %hi(.LCPI26_0)
+; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI26_0)(a2)
+; RV32ZVFHMIN-NEXT: addi a2, a0, -16
+; RV32ZVFHMIN-NEXT: sltu a0, a0, a2
; RV32ZVFHMIN-NEXT: addi a0, a0, -1
-; RV32ZVFHMIN-NEXT: and a0, a0, a1
+; RV32ZVFHMIN-NEXT: and a0, a0, a2
+; RV32ZVFHMIN-NEXT: fsrmi a2, 1
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a1, 1
+; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
+; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV32ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a1
+; RV32ZVFHMIN-NEXT: fsrm a2
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV32ZVFHMIN-NEXT: fsrmi a1, 1
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a0, 1
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a0
+; RV32ZVFHMIN-NEXT: fsrm a1
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1390,44 +1386,44 @@ define <32 x double> @vp_roundtozero_v32f64(<32 x double> %va, <32 x i1> %m, i32
; RV64ZVFHMIN-LABEL: vp_roundtozero_v32f64:
; RV64ZVFHMIN: # %bb.0:
; RV64ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64ZVFHMIN-NEXT: vmv1r.v v6, v0
+; RV64ZVFHMIN-NEXT: vmv1r.v v7, v0
; RV64ZVFHMIN-NEXT: li a2, 16
-; RV64ZVFHMIN-NEXT: vslidedown.vi v7, v0, 2
+; RV64ZVFHMIN-NEXT: vslidedown.vi v6, v0, 2
; RV64ZVFHMIN-NEXT: mv a1, a0
; RV64ZVFHMIN-NEXT: bltu a0, a2, .LBB26_2
; RV64ZVFHMIN-NEXT: # %bb.1:
; RV64ZVFHMIN-NEXT: li a1, 16
; RV64ZVFHMIN-NEXT: .LBB26_2:
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: li a1, 1075
-; RV64ZVFHMIN-NEXT: slli a1, a1, 52
-; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a1
-; RV64ZVFHMIN-NEXT: addi a1, a0, -16
-; RV64ZVFHMIN-NEXT: sltu a0, a0, a1
+; RV64ZVFHMIN-NEXT: li a2, 1075
+; RV64ZVFHMIN-NEXT: slli a2, a2, 52
+; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a2
+; RV64ZVFHMIN-NEXT: addi a2, a0, -16
+; RV64ZVFHMIN-NEXT: sltu a0, a0, a2
; RV64ZVFHMIN-NEXT: addi a0, a0, -1
+; RV64ZVFHMIN-NEXT: and a0, a0, a2
+; RV64ZVFHMIN-NEXT: fsrmi a2, 1
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
-; RV64ZVFHMIN-NEXT: and a0, a0, a1
-; RV64ZVFHMIN-NEXT: fsrmi a1, 1
+; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
+; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
+; RV64ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a1
+; RV64ZVFHMIN-NEXT: fsrm a2
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
+; RV64ZVFHMIN-NEXT: fsrmi a1, 1
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
+; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
-; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a0, 1
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a0
+; RV64ZVFHMIN-NEXT: fsrm a1
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1447,28 +1443,25 @@ define <32 x double> @vp_roundtozero_v32f64_unmasked(<32 x double> %va, i32 zero
; RV32ZVFH-NEXT: .LBB27_2:
; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v8
-; RV32ZVFH-NEXT: lui a2, %hi(.LCPI27_0)
-; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
-; RV32ZVFH-NEXT: addi a2, a0, -16
-; RV32ZVFH-NEXT: sltu a0, a0, a2
+; RV32ZVFH-NEXT: lui a1, %hi(.LCPI27_0)
+; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
+; RV32ZVFH-NEXT: addi a1, a0, -16
+; RV32ZVFH-NEXT: sltu a0, a0, a1
; RV32ZVFH-NEXT: addi a0, a0, -1
-; RV32ZVFH-NEXT: and a0, a0, a2
-; RV32ZVFH-NEXT: fsrmi a2, 1
+; RV32ZVFH-NEXT: and a0, a0, a1
+; RV32ZVFH-NEXT: fsrmi a1, 1
; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFH-NEXT: vfabs.v v24, v16
-; RV32ZVFH-NEXT: vmflt.vf v7, v24, fa5
-; RV32ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFH-NEXT: fsrm a2
+; RV32ZVFH-NEXT: fsrm a1
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV32ZVFH-NEXT: fsrmi a1, 1
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFH-NEXT: vmv1r.v v0, v7
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFH-NEXT: vfabs.v v24, v16
+; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
+; RV32ZVFH-NEXT: fsrmi a0, 1
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFH-NEXT: fsrm a1
+; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1484,29 +1477,26 @@ define <32 x double> @vp_roundtozero_v32f64_unmasked(<32 x double> %va, i32 zero
; RV64ZVFH-NEXT: .LBB27_2:
; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v8
-; RV64ZVFH-NEXT: li a2, 1075
-; RV64ZVFH-NEXT: slli a2, a2, 52
-; RV64ZVFH-NEXT: fmv.d.x fa5, a2
-; RV64ZVFH-NEXT: addi a2, a0, -16
-; RV64ZVFH-NEXT: sltu a0, a0, a2
+; RV64ZVFH-NEXT: li a1, 1075
+; RV64ZVFH-NEXT: slli a1, a1, 52
+; RV64ZVFH-NEXT: fmv.d.x fa5, a1
+; RV64ZVFH-NEXT: addi a1, a0, -16
+; RV64ZVFH-NEXT: sltu a0, a0, a1
; RV64ZVFH-NEXT: addi a0, a0, -1
-; RV64ZVFH-NEXT: and a0, a0, a2
-; RV64ZVFH-NEXT: fsrmi a2, 1
+; RV64ZVFH-NEXT: and a0, a0, a1
+; RV64ZVFH-NEXT: fsrmi a1, 1
; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFH-NEXT: vfabs.v v24, v16
-; RV64ZVFH-NEXT: vmflt.vf v7, v24, fa5
-; RV64ZVFH-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFH-NEXT: fsrm a2
+; RV64ZVFH-NEXT: fsrm a1
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV64ZVFH-NEXT: fsrmi a1, 1
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFH-NEXT: vmv1r.v v0, v7
; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFH-NEXT: vfabs.v v24, v16
+; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
+; RV64ZVFH-NEXT: fsrmi a0, 1
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFH-NEXT: fsrm a1
+; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1522,28 +1512,25 @@ define <32 x double> @vp_roundtozero_v32f64_unmasked(<32 x double> %va, i32 zero
; RV32ZVFHMIN-NEXT: .LBB27_2:
; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v8
-; RV32ZVFHMIN-NEXT: lui a2, %hi(.LCPI27_0)
-; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI27_0)(a2)
-; RV32ZVFHMIN-NEXT: addi a2, a0, -16
-; RV32ZVFHMIN-NEXT: sltu a0, a0, a2
+; RV32ZVFHMIN-NEXT: lui a1, %hi(.LCPI27_0)
+; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI27_0)(a1)
+; RV32ZVFHMIN-NEXT: addi a1, a0, -16
+; RV32ZVFHMIN-NEXT: sltu a0, a0, a1
; RV32ZVFHMIN-NEXT: addi a0, a0, -1
-; RV32ZVFHMIN-NEXT: and a0, a0, a2
-; RV32ZVFHMIN-NEXT: fsrmi a2, 1
+; RV32ZVFHMIN-NEXT: and a0, a0, a1
+; RV32ZVFHMIN-NEXT: fsrmi a1, 1
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32ZVFHMIN-NEXT: vfabs.v v24, v16
-; RV32ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5
-; RV32ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a2
+; RV32ZVFHMIN-NEXT: fsrm a1
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a1, 1
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV32ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32ZVFHMIN-NEXT: vfabs.v v24, v16
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
+; RV32ZVFHMIN-NEXT: fsrmi a0, 1
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a1
+; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -1559,29 +1546,26 @@ define <32 x double> @vp_roundtozero_v32f64_unmasked(<32 x double> %va, i32 zero
; RV64ZVFHMIN-NEXT: .LBB27_2:
; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v8
-; RV64ZVFHMIN-NEXT: li a2, 1075
-; RV64ZVFHMIN-NEXT: slli a2, a2, 52
-; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a2
-; RV64ZVFHMIN-NEXT: addi a2, a0, -16
-; RV64ZVFHMIN-NEXT: sltu a0, a0, a2
+; RV64ZVFHMIN-NEXT: li a1, 1075
+; RV64ZVFHMIN-NEXT: slli a1, a1, 52
+; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a1
+; RV64ZVFHMIN-NEXT: addi a1, a0, -16
+; RV64ZVFHMIN-NEXT: sltu a0, a0, a1
; RV64ZVFHMIN-NEXT: addi a0, a0, -1
-; RV64ZVFHMIN-NEXT: and a0, a0, a2
-; RV64ZVFHMIN-NEXT: fsrmi a2, 1
+; RV64ZVFHMIN-NEXT: and a0, a0, a1
+; RV64ZVFHMIN-NEXT: fsrmi a1, 1
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64ZVFHMIN-NEXT: vfabs.v v24, v16
-; RV64ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5
-; RV64ZVFHMIN-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a2
+; RV64ZVFHMIN-NEXT: fsrm a1
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a1, 1
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v8, v24, v8, v0.t
-; RV64ZVFHMIN-NEXT: vmv1r.v v0, v7
; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64ZVFHMIN-NEXT: vfabs.v v24, v16
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
+; RV64ZVFHMIN-NEXT: fsrmi a0, 1
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a1
+; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-addsub.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-addsub.ll
index 9d3fe3a90b463..6f29d8287081d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-addsub.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-addsub.ll
@@ -157,10 +157,10 @@ define <64 x i32> @select_addsub_v64i32(<64 x i1> %cc, <64 x i32> %a, <64 x i32>
; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vrsub.vi v8, v8, 0, v0.t
+; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 4
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vrsub.vi v24, v24, 0, v0.t
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
index db2cbc82a017b..c1385800a41cc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
@@ -1057,9 +1057,10 @@ define <128 x i1> @fcmp_oeq_vv_v128f16(<128 x half> %va, <128 x half> %vb, <128
; ZVFH-NEXT: addi sp, sp, -16
; ZVFH-NEXT: .cfi_def_cfa_offset 16
; ZVFH-NEXT: csrr a1, vlenb
-; ZVFH-NEXT: slli a1, a1, 3
+; ZVFH-NEXT: slli a3, a1, 3
+; ZVFH-NEXT: add a1, a3, a1
; ZVFH-NEXT: sub sp, sp, a1
-; ZVFH-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFH-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
; ZVFH-NEXT: addi a1, sp, 16
; ZVFH-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; ZVFH-NEXT: addi a1, a0, 128
@@ -1068,28 +1069,39 @@ define <128 x i1> @fcmp_oeq_vv_v128f16(<128 x half> %va, <128 x half> %vb, <128
; ZVFH-NEXT: vle16.v v16, (a1)
; ZVFH-NEXT: vle16.v v24, (a0)
; ZVFH-NEXT: mv a0, a2
+; ZVFH-NEXT: csrr a1, vlenb
+; ZVFH-NEXT: slli a1, a1, 3
+; ZVFH-NEXT: add a1, sp, a1
+; ZVFH-NEXT: addi a1, a1, 16
+; ZVFH-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
; ZVFH-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; ZVFH-NEXT: vslidedown.vi v7, v0, 8
; ZVFH-NEXT: bltu a2, a3, .LBB43_2
; ZVFH-NEXT: # %bb.1:
; ZVFH-NEXT: li a0, 64
; ZVFH-NEXT: .LBB43_2:
+; ZVFH-NEXT: csrr a1, vlenb
+; ZVFH-NEXT: slli a1, a1, 3
+; ZVFH-NEXT: add a1, sp, a1
+; ZVFH-NEXT: addi a1, a1, 16
+; ZVFH-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; ZVFH-NEXT: vmfeq.vv v6, v8, v24, v0.t
; ZVFH-NEXT: addi a0, a2, -64
; ZVFH-NEXT: sltu a1, a2, a0
; ZVFH-NEXT: addi a1, a1, -1
; ZVFH-NEXT: and a0, a1, a0
-; ZVFH-NEXT: vmv1r.v v0, v7
; ZVFH-NEXT: addi a1, sp, 16
; ZVFH-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFH-NEXT: vmv1r.v v0, v7
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; ZVFH-NEXT: vmfeq.vv v8, v24, v16, v0.t
; ZVFH-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; ZVFH-NEXT: vslideup.vi v6, v8, 8
; ZVFH-NEXT: vmv.v.v v0, v6
; ZVFH-NEXT: csrr a0, vlenb
-; ZVFH-NEXT: slli a0, a0, 3
+; ZVFH-NEXT: slli a1, a0, 3
+; ZVFH-NEXT: add a0, a1, a0
; ZVFH-NEXT: add sp, sp, a0
; ZVFH-NEXT: .cfi_def_cfa sp, 16
; ZVFH-NEXT: addi sp, sp, 16
@@ -3910,9 +3922,10 @@ define <32 x i1> @fcmp_oeq_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a3, a1, 3
+; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a1, a0, 128
@@ -3921,28 +3934,39 @@ define <32 x i1> @fcmp_oeq_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v7, v0, 2
; CHECK-NEXT: bltu a2, a1, .LBB87_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB87_2:
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v6, v8, v24, v0.t
; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v8, v24, v16, v0.t
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v6, v8, 2
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
index 5777d76072d80..f9b97da6d02aa 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
@@ -591,7 +591,7 @@ define <256 x i1> @icmp_eq_vv_v256i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1>
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vmv1r.v v6, v0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: li a1, 128
@@ -605,18 +605,18 @@ define <256 x i1> @icmp_eq_vv_v256i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1>
; CHECK-NEXT: addi a4, a4, -1
; CHECK-NEXT: and a2, a4, a2
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; CHECK-NEXT: vmseq.vv v6, v16, v24, v0.t
+; CHECK-NEXT: vmseq.vv v7, v16, v24, v0.t
; CHECK-NEXT: bltu a3, a1, .LBB51_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a3, 128
; CHECK-NEXT: .LBB51_2:
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vv v16, v24, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vmv1r.v v8, v6
+; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -632,7 +632,7 @@ define <256 x i1> @icmp_eq_vx_v256i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 z
; CHECK-LABEL: icmp_eq_vx_v256i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
@@ -641,16 +641,16 @@ define <256 x i1> @icmp_eq_vx_v256i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 z
; CHECK-NEXT: addi a4, a4, -1
; CHECK-NEXT: and a1, a4, a1
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vmseq.vx v25, v16, a0, v0.t
+; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB52_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: .LBB52_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vx v16, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vmv1r.v v8, v24
; CHECK-NEXT: ret
%elt.head = insertelement <256 x i8> poison, i8 %b, i32 0
%vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer
@@ -662,7 +662,7 @@ define <256 x i1> @icmp_eq_vx_swap_v256i8(<256 x i8> %va, i8 %b, <256 x i1> %m,
; CHECK-LABEL: icmp_eq_vx_swap_v256i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
@@ -671,16 +671,16 @@ define <256 x i1> @icmp_eq_vx_swap_v256i8(<256 x i8> %va, i8 %b, <256 x i1> %m,
; CHECK-NEXT: addi a4, a4, -1
; CHECK-NEXT: and a1, a4, a1
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vmseq.vx v25, v16, a0, v0.t
+; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB53_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: .LBB53_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vx v16, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vmv1r.v v8, v24
; CHECK-NEXT: ret
%elt.head = insertelement <256 x i8> poison, i8 %b, i32 0
%vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer
@@ -1231,9 +1231,10 @@ define <64 x i1> @icmp_eq_vv_v64i32(<64 x i32> %va, <64 x i32> %vb, <64 x i1> %m
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a3, a1, 3
+; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a1, a0, 128
@@ -1242,28 +1243,39 @@ define <64 x i1> @icmp_eq_vv_v64i32(<64 x i32> %va, <64 x i32> %vb, <64 x i1> %m
; CHECK-NEXT: vle32.v v16, (a1)
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v7, v0, 4
; CHECK-NEXT: bltu a2, a3, .LBB99_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: .LBB99_2:
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vmseq.vv v6, v8, v24, v0.t
; CHECK-NEXT: addi a0, a2, -32
; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vmseq.vv v8, v24, v16, v0.t
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v6, v8, 4
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -1278,24 +1290,24 @@ define <64 x i1> @icmp_eq_vx_v64i32(<64 x i32> %va, i32 %b, <64 x i1> %m, i32 ze
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 4
+; CHECK-NEXT: vslidedown.vi v25, v0, 4
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bltu a1, a3, .LBB100_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: .LBB100_2:
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
+; CHECK-NEXT: vmseq.vx v24, v8, a0, v0.t
; CHECK-NEXT: addi a2, a1, -32
; CHECK-NEXT: sltu a1, a1, a2
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a1, a1, a2
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vmseq.vx v8, v16, a0, v0.t
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vi v25, v8, 4
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vslideup.vi v24, v8, 4
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: ret
%elt.head = insertelement <64 x i32> poison, i32 %b, i32 0
%vb = shufflevector <64 x i32> %elt.head, <64 x i32> poison, <64 x i32> zeroinitializer
@@ -1308,24 +1320,24 @@ define <64 x i1> @icmp_eq_vx_swap_v64i32(<64 x i32> %va, i32 %b, <64 x i1> %m, i
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 4
+; CHECK-NEXT: vslidedown.vi v25, v0, 4
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bltu a1, a3, .LBB101_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: .LBB101_2:
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t
+; CHECK-NEXT: vmseq.vx v24, v8, a0, v0.t
; CHECK-NEXT: addi a2, a1, -32
; CHECK-NEXT: sltu a1, a1, a2
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a1, a1, a2
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vmseq.vx v8, v16, a0, v0.t
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vi v25, v8, 4
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vslideup.vi v24, v8, 4
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: ret
%elt.head = insertelement <64 x i32> poison, i32 %b, i32 0
%vb = shufflevector <64 x i32> %elt.head, <64 x i32> poison, <64 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
index a452e5a9ffbb8..b03415e1a8550 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
@@ -139,25 +139,24 @@ define <32 x i64> @vsext_v32i64_v32i32(<32 x i32> %va, <32 x i1> %m, i32 zeroext
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: vslidedown.vi v16, v0, 2
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB12_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB12_2:
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vsext.vf2 v16, v8, v0.t
+; CHECK-NEXT: vsext.vf2 v24, v8, v0.t
; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 16
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vsext.vf2 v24, v8, v0.t
-; CHECK-NEXT: vmv8r.v v8, v16
-; CHECK-NEXT: vmv.v.v v16, v24
+; CHECK-NEXT: vsext.vf2 v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.sext.v32i64.v32i32(<32 x i32> %va, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
index c05f306424519..deeba241e212c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll
@@ -31,8 +31,8 @@ define <8 x i1> @v8i1_v16i1(<16 x i1>) {
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: vslide1down.vx v8, v8, a1
; RV32-NEXT: vslide1down.vx v9, v9, a2
-; RV32-NEXT: vmv.v.i v0, 15
; RV32-NEXT: vslide1down.vx v9, v9, a0
+; RV32-NEXT: vmv.v.i v0, 15
; RV32-NEXT: vslidedown.vi v8, v9, 4, v0.t
; RV32-NEXT: vand.vi v8, v8, 1
; RV32-NEXT: vmsne.vi v0, v8, 0
@@ -65,8 +65,8 @@ define <8 x i1> @v8i1_v16i1(<16 x i1>) {
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: vslide1down.vx v8, v8, a1
; RV64-NEXT: vslide1down.vx v9, v9, a2
-; RV64-NEXT: vmv.v.i v0, 15
; RV64-NEXT: vslide1down.vx v9, v9, a0
+; RV64-NEXT: vmv.v.i v0, 15
; RV64-NEXT: vslidedown.vi v8, v9, 4, v0.t
; RV64-NEXT: vand.vi v8, v8, 1
; RV64-NEXT: vmsne.vi v0, v8, 0
@@ -79,8 +79,8 @@ define <4 x i32> @v4i32_v8i32(<8 x i32>) {
; CHECK-LABEL: v4i32_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.i v0, 8
; CHECK-NEXT: vslidedown.vi v10, v8, 2
+; CHECK-NEXT: vmv.v.i v0, 8
; CHECK-NEXT: vslideup.vi v10, v8, 1, v0.t
; CHECK-NEXT: vmv.v.i v0, 5
; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
@@ -104,8 +104,8 @@ define <4 x i32> @v4i32_v16i32(<16 x i32>) {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vslidedown.vi v12, v12, 3, v0.t
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v0, 10
; CHECK-NEXT: vnsrl.wx v10, v8, a0
+; CHECK-NEXT: vmv.v.i v0, 10
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
; CHECK-NEXT: ret
@@ -246,11 +246,11 @@ define <16 x i32> @v16i32_v4i32(<4 x i32>) {
; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: addi a0, a0, -1856
+; CHECK-NEXT: srli a1, a1, 2
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: srli a1, a1, 2
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
index 63b96a96a284a..03bde17b1230a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
@@ -145,11 +145,12 @@ define void @deinterleave6_0_i8(ptr %in, ptr %out) {
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.v.i v0, 2
+; CHECK-NEXT: vmv.v.i v10, 4
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 8
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 5, v0.t
-; CHECK-NEXT: vmv.v.i v0, 4
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vrgather.vi v8, v9, 4, v0.t
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -189,11 +190,12 @@ define void @deinterleave7_0_i8(ptr %in, ptr %out) {
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.v.i v0, 2
+; CHECK-NEXT: vmv.v.i v10, 4
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 8
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 6, v0.t
-; CHECK-NEXT: vmv.v.i v0, 4
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vrgather.vi v8, v9, 6, v0.t
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -275,18 +277,17 @@ define void @deinterleave7_0_i64(ptr %in, ptr %out) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vsetivli zero, 8, e64, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v8, 8
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 2
-; CHECK-NEXT: vmv4r.v v16, v8
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vslidedown.vi v16, v8, 6, v0.t
+; CHECK-NEXT: vslidedown.vi v8, v8, 6, v0.t
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 4
-; CHECK-NEXT: vsetivli zero, 8, e64, m8, ta, ma
-; CHECK-NEXT: vslidedown.vi v8, v8, 8
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vrgather.vi v16, v8, 6, v0.t
-; CHECK-NEXT: vse64.v v16, (a1)
+; CHECK-NEXT: vrgather.vi v8, v16, 6, v0.t
+; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
entry:
%0 = load <16 x i64>, ptr %in
@@ -320,19 +321,18 @@ define void @deinterleave7_0_i32_subvec(ptr %in, ptr %out) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v8, 8
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 2
-; CHECK-NEXT: vmv2r.v v12, v8
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vslidedown.vi v12, v8, 6, v0.t
+; CHECK-NEXT: vslidedown.vi v8, v8, 6, v0.t
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 4
-; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
-; CHECK-NEXT: vslidedown.vi v8, v8, 8
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vrgather.vi v12, v8, 6, v0.t
+; CHECK-NEXT: vrgather.vi v8, v12, 6, v0.t
; CHECK-NEXT: vsetivli zero, 3, e32, m1, ta, ma
-; CHECK-NEXT: vse32.v v12, (a1)
+; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret
entry:
%0 = load <16 x i32>, ptr %in
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
index f80b7bd94490e..aa86624440754 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
@@ -227,9 +227,9 @@ define void @vnsrl_32_i32(ptr %in, ptr %out) {
; ZVE32F: # %bb.0: # %entry
; ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVE32F-NEXT: vle32.v v8, (a0)
-; ZVE32F-NEXT: vmv.v.i v0, 1
; ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; ZVE32F-NEXT: vmv.v.i v0, 1
; ZVE32F-NEXT: vslidedown.vi v9, v8, 1, v0.t
; ZVE32F-NEXT: vse32.v v9, (a1)
; ZVE32F-NEXT: ret
@@ -300,9 +300,9 @@ define void @vnsrl_32_float(ptr %in, ptr %out) {
; ZVE32F: # %bb.0: # %entry
; ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVE32F-NEXT: vle32.v v8, (a0)
-; ZVE32F-NEXT: vmv.v.i v0, 1
; ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, mu
; ZVE32F-NEXT: vslidedown.vi v9, v8, 2
+; ZVE32F-NEXT: vmv.v.i v0, 1
; ZVE32F-NEXT: vslidedown.vi v9, v8, 1, v0.t
; ZVE32F-NEXT: vse32.v v9, (a1)
; ZVE32F-NEXT: ret
@@ -362,9 +362,9 @@ define void @vnsrl_64_i64(ptr %in, ptr %out) {
; V: # %bb.0: # %entry
; V-NEXT: vsetivli zero, 4, e64, m1, ta, ma
; V-NEXT: vle64.v v8, (a0)
-; V-NEXT: vmv.v.i v0, 1
; V-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; V-NEXT: vslidedown.vi v9, v8, 2
+; V-NEXT: vmv.v.i v0, 1
; V-NEXT: vslidedown.vi v9, v8, 1, v0.t
; V-NEXT: vse64.v v9, (a1)
; V-NEXT: ret
@@ -431,9 +431,9 @@ define void @vnsrl_64_double(ptr %in, ptr %out) {
; V: # %bb.0: # %entry
; V-NEXT: vsetivli zero, 4, e64, m1, ta, ma
; V-NEXT: vle64.v v8, (a0)
-; V-NEXT: vmv.v.i v0, 1
; V-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; V-NEXT: vslidedown.vi v9, v8, 2
+; V-NEXT: vmv.v.i v0, 1
; V-NEXT: vslidedown.vi v9, v8, 1, v0.t
; V-NEXT: vse64.v v9, (a1)
; V-NEXT: ret
@@ -515,21 +515,21 @@ define void @vnsrl_0_i8_undef_negative(ptr %in, ptr %out) {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e8, mf2, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
-; CHECK-NEXT: li a0, 32
-; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: lui a0, %hi(.LCPI17_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI17_0)
; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
; CHECK-NEXT: vle8.v v9, (a0)
+; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: li a0, 48
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 8
; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, mu
-; CHECK-NEXT: vslideup.vi v11, v10, 4
-; CHECK-NEXT: vslideup.vi v11, v10, 3, v0.t
-; CHECK-NEXT: li a0, 48
+; CHECK-NEXT: vrgather.vv v11, v8, v9
+; CHECK-NEXT: vslideup.vi v8, v10, 4
+; CHECK-NEXT: vslideup.vi v8, v10, 3, v0.t
; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vrgather.vv v10, v8, v9
-; CHECK-NEXT: vmerge.vvm v8, v10, v11, v0
+; CHECK-NEXT: vmerge.vvm v8, v11, v8, v0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
entry:
@@ -1329,8 +1329,8 @@ define <4 x i64> @unzip2a_dual_v4i64(<4 x i64> %a, <4 x i64> %b) {
; V-LABEL: unzip2a_dual_v4i64:
; V: # %bb.0: # %entry
; V-NEXT: vsetivli zero, 4, e64, m1, ta, mu
-; V-NEXT: vmv.v.i v0, 8
; V-NEXT: vslideup.vi v10, v9, 2
+; V-NEXT: vmv.v.i v0, 8
; V-NEXT: vslideup.vi v10, v9, 1, v0.t
; V-NEXT: vmv.v.i v0, 2
; V-NEXT: vslidedown.vi v8, v8, 1, v0.t
@@ -1340,24 +1340,24 @@ define <4 x i64> @unzip2a_dual_v4i64(<4 x i64> %a, <4 x i64> %b) {
;
; ZVE32F-LABEL: unzip2a_dual_v4i64:
; ZVE32F: # %bb.0: # %entry
-; ZVE32F-NEXT: ld a3, 0(a1)
-; ZVE32F-NEXT: ld a1, 16(a1)
-; ZVE32F-NEXT: ld a4, 0(a2)
-; ZVE32F-NEXT: ld a2, 16(a2)
+; ZVE32F-NEXT: ld a3, 16(a1)
+; ZVE32F-NEXT: ld a1, 0(a1)
+; ZVE32F-NEXT: ld a4, 16(a2)
+; ZVE32F-NEXT: ld a2, 0(a2)
+; ZVE32F-NEXT: srli a5, a3, 32
+; ZVE32F-NEXT: srli a6, a1, 32
+; ZVE32F-NEXT: srli a7, a4, 32
+; ZVE32F-NEXT: srli t0, a2, 32
; ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, mu
-; ZVE32F-NEXT: vmv.v.i v0, 15
-; ZVE32F-NEXT: srli a5, a1, 32
-; ZVE32F-NEXT: srli a6, a3, 32
-; ZVE32F-NEXT: srli a7, a2, 32
-; ZVE32F-NEXT: srli t0, a4, 32
-; ZVE32F-NEXT: vmv.v.x v8, a4
-; ZVE32F-NEXT: vmv.v.x v9, a3
+; ZVE32F-NEXT: vmv.v.x v8, a2
+; ZVE32F-NEXT: vmv.v.x v9, a1
; ZVE32F-NEXT: vslide1down.vx v8, v8, t0
; ZVE32F-NEXT: vslide1down.vx v9, v9, a6
-; ZVE32F-NEXT: vslide1down.vx v8, v8, a2
-; ZVE32F-NEXT: vslide1down.vx v9, v9, a1
+; ZVE32F-NEXT: vslide1down.vx v8, v8, a4
+; ZVE32F-NEXT: vslide1down.vx v9, v9, a3
; ZVE32F-NEXT: vslide1down.vx v8, v8, a7
; ZVE32F-NEXT: vslide1down.vx v9, v9, a5
+; ZVE32F-NEXT: vmv.v.i v0, 15
; ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t
; ZVE32F-NEXT: vse32.v v8, (a0)
; ZVE32F-NEXT: ret
@@ -1384,14 +1384,12 @@ define <16 x i64> @unzip2a_dual_v16i64(<16 x i64> %a, <16 x i64> %b) {
; V-NEXT: addi a0, a0, 1365
; V-NEXT: vmv.s.x v20, a0
; V-NEXT: li a0, -256
-; V-NEXT: vadd.vv v21, v16, v16
-; V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; V-NEXT: vadd.vv v16, v16, v16
+; V-NEXT: vadd.vi v21, v16, -16
+; V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; V-NEXT: vcompress.vm v16, v8, v20
; V-NEXT: vmv.s.x v0, a0
-; V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; V-NEXT: vadd.vi v8, v21, -16
-; V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; V-NEXT: vrgatherei16.vv v16, v12, v8, v0.t
+; V-NEXT: vrgatherei16.vv v16, v12, v21, v0.t
; V-NEXT: vmv.v.v v8, v16
; V-NEXT: ret
;
@@ -1515,8 +1513,8 @@ define <4 x i64> @unzip2a_dual_v4i64_exact(<4 x i64> %a, <4 x i64> %b) vscale_ra
; V-LABEL: unzip2a_dual_v4i64_exact:
; V: # %bb.0: # %entry
; V-NEXT: vsetivli zero, 4, e64, m1, ta, mu
-; V-NEXT: vmv.v.i v0, 8
; V-NEXT: vslideup.vi v10, v9, 2
+; V-NEXT: vmv.v.i v0, 8
; V-NEXT: vslideup.vi v10, v9, 1, v0.t
; V-NEXT: vmv.v.i v0, 2
; V-NEXT: vslidedown.vi v8, v8, 1, v0.t
@@ -1526,24 +1524,24 @@ define <4 x i64> @unzip2a_dual_v4i64_exact(<4 x i64> %a, <4 x i64> %b) vscale_ra
;
; ZVE32F-LABEL: unzip2a_dual_v4i64_exact:
; ZVE32F: # %bb.0: # %entry
-; ZVE32F-NEXT: ld a3, 0(a1)
-; ZVE32F-NEXT: ld a1, 16(a1)
-; ZVE32F-NEXT: ld a4, 0(a2)
-; ZVE32F-NEXT: ld a2, 16(a2)
+; ZVE32F-NEXT: ld a3, 16(a1)
+; ZVE32F-NEXT: ld a1, 0(a1)
+; ZVE32F-NEXT: ld a4, 16(a2)
+; ZVE32F-NEXT: ld a2, 0(a2)
+; ZVE32F-NEXT: srli a5, a3, 32
+; ZVE32F-NEXT: srli a6, a1, 32
+; ZVE32F-NEXT: srli a7, a4, 32
+; ZVE32F-NEXT: srli t0, a2, 32
; ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, mu
-; ZVE32F-NEXT: vmv.v.i v0, 15
-; ZVE32F-NEXT: srli a5, a1, 32
-; ZVE32F-NEXT: srli a6, a3, 32
-; ZVE32F-NEXT: srli a7, a2, 32
-; ZVE32F-NEXT: srli t0, a4, 32
-; ZVE32F-NEXT: vmv.v.x v8, a4
-; ZVE32F-NEXT: vmv.v.x v9, a3
+; ZVE32F-NEXT: vmv.v.x v8, a2
+; ZVE32F-NEXT: vmv.v.x v9, a1
; ZVE32F-NEXT: vslide1down.vx v8, v8, t0
; ZVE32F-NEXT: vslide1down.vx v9, v9, a6
-; ZVE32F-NEXT: vslide1down.vx v8, v8, a2
-; ZVE32F-NEXT: vslide1down.vx v9, v9, a1
+; ZVE32F-NEXT: vslide1down.vx v8, v8, a4
+; ZVE32F-NEXT: vslide1down.vx v9, v9, a3
; ZVE32F-NEXT: vslide1down.vx v8, v8, a7
; ZVE32F-NEXT: vslide1down.vx v9, v9, a5
+; ZVE32F-NEXT: vmv.v.i v0, 15
; ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t
; ZVE32F-NEXT: vs1r.v v8, (a0)
; ZVE32F-NEXT: ret
@@ -1563,8 +1561,8 @@ define <4 x i64> @unzip2a_dual_v4i64_exact_nf2(<4 x i64> %a, <4 x i64> %b) vscal
; V-LABEL: unzip2a_dual_v4i64_exact_nf2:
; V: # %bb.0: # %entry
; V-NEXT: vsetivli zero, 4, e64, m1, ta, mu
-; V-NEXT: vmv.v.i v0, 8
; V-NEXT: vslideup.vi v10, v9, 2
+; V-NEXT: vmv.v.i v0, 8
; V-NEXT: vslideup.vi v10, v9, 1, v0.t
; V-NEXT: vmv.v.i v0, 2
; V-NEXT: vslidedown.vi v8, v8, 1, v0.t
@@ -1574,24 +1572,24 @@ define <4 x i64> @unzip2a_dual_v4i64_exact_nf2(<4 x i64> %a, <4 x i64> %b) vscal
;
; ZVE32F-LABEL: unzip2a_dual_v4i64_exact_nf2:
; ZVE32F: # %bb.0: # %entry
-; ZVE32F-NEXT: ld a3, 0(a1)
-; ZVE32F-NEXT: ld a1, 16(a1)
-; ZVE32F-NEXT: ld a4, 0(a2)
-; ZVE32F-NEXT: ld a2, 16(a2)
+; ZVE32F-NEXT: ld a3, 16(a1)
+; ZVE32F-NEXT: ld a1, 0(a1)
+; ZVE32F-NEXT: ld a4, 16(a2)
+; ZVE32F-NEXT: ld a2, 0(a2)
+; ZVE32F-NEXT: srli a5, a3, 32
+; ZVE32F-NEXT: srli a6, a1, 32
+; ZVE32F-NEXT: srli a7, a4, 32
+; ZVE32F-NEXT: srli t0, a2, 32
; ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, mu
-; ZVE32F-NEXT: vmv.v.i v0, 15
-; ZVE32F-NEXT: srli a5, a1, 32
-; ZVE32F-NEXT: srli a6, a3, 32
-; ZVE32F-NEXT: srli a7, a2, 32
-; ZVE32F-NEXT: srli t0, a4, 32
-; ZVE32F-NEXT: vmv.v.x v8, a4
-; ZVE32F-NEXT: vmv.v.x v9, a3
+; ZVE32F-NEXT: vmv.v.x v8, a2
+; ZVE32F-NEXT: vmv.v.x v9, a1
; ZVE32F-NEXT: vslide1down.vx v8, v8, t0
; ZVE32F-NEXT: vslide1down.vx v9, v9, a6
-; ZVE32F-NEXT: vslide1down.vx v8, v8, a2
-; ZVE32F-NEXT: vslide1down.vx v9, v9, a1
+; ZVE32F-NEXT: vslide1down.vx v8, v8, a4
+; ZVE32F-NEXT: vslide1down.vx v9, v9, a3
; ZVE32F-NEXT: vslide1down.vx v8, v8, a7
; ZVE32F-NEXT: vslide1down.vx v9, v9, a5
+; ZVE32F-NEXT: vmv.v.i v0, 15
; ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t
; ZVE32F-NEXT: vse32.v v8, (a0)
; ZVE32F-NEXT: ret
@@ -1612,35 +1610,35 @@ define <16 x i64> @unzip2a_dual_v16i64_exact(<16 x i64> %a, <16 x i64> %b) vscal
; V-LABEL: unzip2a_dual_v16i64_exact:
; V: # %bb.0: # %entry
; V-NEXT: vsetivli zero, 4, e64, m1, ta, mu
-; V-NEXT: vslideup.vi v19, v15, 2
-; V-NEXT: vmv.v.i v16, 8
-; V-NEXT: vmv.v.i v17, 2
+; V-NEXT: vslideup.vi v16, v15, 2
+; V-NEXT: vmv.v.i v17, 8
+; V-NEXT: vmv.v.i v19, 2
; V-NEXT: vmv.v.i v18, 12
-; V-NEXT: vmv.v.v v0, v16
-; V-NEXT: vslideup.vi v19, v15, 1, v0.t
; V-NEXT: vmv.v.v v0, v17
+; V-NEXT: vslideup.vi v16, v15, 1, v0.t
+; V-NEXT: vmv.v.v v0, v19
; V-NEXT: vslidedown.vi v14, v14, 1, v0.t
; V-NEXT: vmv.v.v v0, v18
-; V-NEXT: vmerge.vvm v15, v14, v19, v0
+; V-NEXT: vmerge.vvm v15, v14, v16, v0
; V-NEXT: vslideup.vi v14, v13, 2
-; V-NEXT: vmv.v.v v0, v16
-; V-NEXT: vslideup.vi v14, v13, 1, v0.t
; V-NEXT: vmv.v.v v0, v17
+; V-NEXT: vslideup.vi v14, v13, 1, v0.t
+; V-NEXT: vmv.v.v v0, v19
; V-NEXT: vslidedown.vi v12, v12, 1, v0.t
; V-NEXT: vmv.v.v v0, v18
; V-NEXT: vmerge.vvm v14, v12, v14, v0
; V-NEXT: vslideup.vi v12, v11, 2
; V-NEXT: li a0, -256
-; V-NEXT: vmv.v.v v0, v16
-; V-NEXT: vslideup.vi v12, v11, 1, v0.t
; V-NEXT: vmv.v.v v0, v17
+; V-NEXT: vslideup.vi v12, v11, 1, v0.t
+; V-NEXT: vmv.v.v v0, v19
; V-NEXT: vslidedown.vi v10, v10, 1, v0.t
; V-NEXT: vmv.v.v v0, v18
; V-NEXT: vmerge.vvm v13, v10, v12, v0
; V-NEXT: vslideup.vi v10, v9, 2
-; V-NEXT: vmv.v.v v0, v16
-; V-NEXT: vslideup.vi v10, v9, 1, v0.t
; V-NEXT: vmv.v.v v0, v17
+; V-NEXT: vslideup.vi v10, v9, 1, v0.t
+; V-NEXT: vmv.v.v v0, v19
; V-NEXT: vslidedown.vi v8, v8, 1, v0.t
; V-NEXT: vmv.v.v v0, v18
; V-NEXT: vmerge.vvm v12, v8, v10, v0
@@ -1651,75 +1649,75 @@ define <16 x i64> @unzip2a_dual_v16i64_exact(<16 x i64> %a, <16 x i64> %b) vscal
;
; ZVE32F-LABEL: unzip2a_dual_v16i64_exact:
; ZVE32F: # %bb.0: # %entry
-; ZVE32F-NEXT: ld a5, 96(a2)
-; ZVE32F-NEXT: ld a7, 0(a1)
-; ZVE32F-NEXT: ld a4, 16(a1)
-; ZVE32F-NEXT: ld t0, 32(a1)
-; ZVE32F-NEXT: ld a3, 48(a1)
-; ZVE32F-NEXT: ld t1, 64(a1)
-; ZVE32F-NEXT: ld a6, 80(a1)
-; ZVE32F-NEXT: ld t2, 96(a1)
-; ZVE32F-NEXT: ld a1, 112(a1)
+; ZVE32F-NEXT: ld a3, 96(a1)
+; ZVE32F-NEXT: ld a4, 64(a1)
+; ZVE32F-NEXT: ld a5, 112(a1)
; ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, mu
-; ZVE32F-NEXT: vmv.v.x v8, a7
-; ZVE32F-NEXT: srli a7, a7, 32
-; ZVE32F-NEXT: vmv.v.x v9, t0
-; ZVE32F-NEXT: srli t0, t0, 32
-; ZVE32F-NEXT: vmv.v.x v10, t1
-; ZVE32F-NEXT: srli t1, t1, 32
-; ZVE32F-NEXT: vmv.v.x v11, t2
-; ZVE32F-NEXT: srli t2, t2, 32
-; ZVE32F-NEXT: vslide1down.vx v11, v11, t2
-; ZVE32F-NEXT: vslide1down.vx v10, v10, t1
-; ZVE32F-NEXT: vslide1down.vx v12, v9, t0
-; ZVE32F-NEXT: vslide1down.vx v8, v8, a7
-; ZVE32F-NEXT: ld t0, 0(a2)
-; ZVE32F-NEXT: ld t1, 16(a2)
-; ZVE32F-NEXT: ld t2, 32(a2)
-; ZVE32F-NEXT: ld a7, 48(a2)
-; ZVE32F-NEXT: vmv.v.x v9, t0
-; ZVE32F-NEXT: srli t0, t0, 32
-; ZVE32F-NEXT: vmv.v.x v13, t2
-; ZVE32F-NEXT: srli t2, t2, 32
-; ZVE32F-NEXT: vslide1down.vx v13, v13, t2
-; ZVE32F-NEXT: vslide1down.vx v14, v9, t0
-; ZVE32F-NEXT: ld t0, 64(a2)
-; ZVE32F-NEXT: ld t2, 112(a2)
-; ZVE32F-NEXT: vmv.v.x v9, a5
-; ZVE32F-NEXT: srli a5, a5, 32
-; ZVE32F-NEXT: vslide1down.vx v15, v9, a5
-; ZVE32F-NEXT: ld a2, 80(a2)
-; ZVE32F-NEXT: vmv.v.x v9, t0
-; ZVE32F-NEXT: srli a5, t0, 32
-; ZVE32F-NEXT: vslide1down.vx v16, v9, a5
-; ZVE32F-NEXT: vslide1down.vx v9, v11, a1
-; ZVE32F-NEXT: srli a1, a1, 32
-; ZVE32F-NEXT: vslide1down.vx v9, v9, a1
-; ZVE32F-NEXT: vslide1down.vx v10, v10, a6
-; ZVE32F-NEXT: srli a1, a6, 32
-; ZVE32F-NEXT: vslide1down.vx v10, v10, a1
-; ZVE32F-NEXT: vslide1down.vx v8, v8, a4
+; ZVE32F-NEXT: vmv.v.x v8, a3
+; ZVE32F-NEXT: srli a3, a3, 32
+; ZVE32F-NEXT: vslide1down.vx v8, v8, a3
+; ZVE32F-NEXT: ld a3, 80(a1)
+; ZVE32F-NEXT: vmv.v.x v9, a4
; ZVE32F-NEXT: srli a4, a4, 32
-; ZVE32F-NEXT: vslide1down.vx v11, v8, a4
+; ZVE32F-NEXT: vslide1down.vx v9, v9, a4
+; ZVE32F-NEXT: vslide1down.vx v10, v9, a3
+; ZVE32F-NEXT: srli a3, a3, 32
+; ZVE32F-NEXT: vslide1down.vx v8, v8, a5
+; ZVE32F-NEXT: srli a5, a5, 32
+; ZVE32F-NEXT: vslide1down.vx v9, v8, a5
+; ZVE32F-NEXT: vslide1down.vx v8, v10, a3
+; ZVE32F-NEXT: ld a3, 32(a1)
+; ZVE32F-NEXT: ld a4, 48(a1)
; ZVE32F-NEXT: vmv.v.i v0, 15
-; ZVE32F-NEXT: vslide1down.vx v8, v14, t1
-; ZVE32F-NEXT: srli a1, t1, 32
-; ZVE32F-NEXT: vslide1down.vx v14, v8, a1
-; ZVE32F-NEXT: vslidedown.vi v9, v10, 4, v0.t
-; ZVE32F-NEXT: vslide1down.vx v8, v12, a3
+; ZVE32F-NEXT: vslidedown.vi v9, v8, 4, v0.t
+; ZVE32F-NEXT: vmv.v.x v8, a3
; ZVE32F-NEXT: srli a3, a3, 32
; ZVE32F-NEXT: vslide1down.vx v8, v8, a3
-; ZVE32F-NEXT: vslidedown.vi v8, v11, 4, v0.t
-; ZVE32F-NEXT: vslide1down.vx v10, v13, a7
-; ZVE32F-NEXT: srli a1, a7, 32
+; ZVE32F-NEXT: ld a3, 0(a1)
+; ZVE32F-NEXT: vslide1down.vx v8, v8, a4
+; ZVE32F-NEXT: srli a4, a4, 32
+; ZVE32F-NEXT: vslide1down.vx v8, v8, a4
+; ZVE32F-NEXT: ld a1, 16(a1)
+; ZVE32F-NEXT: vmv.v.x v10, a3
+; ZVE32F-NEXT: srli a3, a3, 32
+; ZVE32F-NEXT: vslide1down.vx v10, v10, a3
+; ZVE32F-NEXT: ld a3, 32(a2)
; ZVE32F-NEXT: vslide1down.vx v10, v10, a1
-; ZVE32F-NEXT: vslidedown.vi v10, v14, 4, v0.t
-; ZVE32F-NEXT: vslide1down.vx v11, v15, t2
-; ZVE32F-NEXT: srli a1, t2, 32
+; ZVE32F-NEXT: srli a1, a1, 32
+; ZVE32F-NEXT: vslide1down.vx v10, v10, a1
+; ZVE32F-NEXT: ld a1, 48(a2)
+; ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t
+; ZVE32F-NEXT: vmv.v.x v10, a3
+; ZVE32F-NEXT: srli a3, a3, 32
+; ZVE32F-NEXT: vslide1down.vx v10, v10, a3
+; ZVE32F-NEXT: ld a3, 0(a2)
+; ZVE32F-NEXT: vslide1down.vx v10, v10, a1
+; ZVE32F-NEXT: srli a1, a1, 32
+; ZVE32F-NEXT: vslide1down.vx v10, v10, a1
+; ZVE32F-NEXT: ld a1, 16(a2)
+; ZVE32F-NEXT: vmv.v.x v11, a3
+; ZVE32F-NEXT: srli a3, a3, 32
+; ZVE32F-NEXT: vslide1down.vx v11, v11, a3
+; ZVE32F-NEXT: ld a3, 96(a2)
+; ZVE32F-NEXT: vslide1down.vx v11, v11, a1
+; ZVE32F-NEXT: srli a1, a1, 32
+; ZVE32F-NEXT: vslide1down.vx v11, v11, a1
+; ZVE32F-NEXT: ld a1, 112(a2)
+; ZVE32F-NEXT: vslidedown.vi v10, v11, 4, v0.t
+; ZVE32F-NEXT: vmv.v.x v11, a3
+; ZVE32F-NEXT: srli a3, a3, 32
+; ZVE32F-NEXT: vslide1down.vx v11, v11, a3
+; ZVE32F-NEXT: ld a3, 64(a2)
; ZVE32F-NEXT: vslide1down.vx v11, v11, a1
-; ZVE32F-NEXT: vslide1down.vx v12, v16, a2
-; ZVE32F-NEXT: srli a2, a2, 32
-; ZVE32F-NEXT: vslide1down.vx v12, v12, a2
+; ZVE32F-NEXT: srli a1, a1, 32
+; ZVE32F-NEXT: vslide1down.vx v11, v11, a1
+; ZVE32F-NEXT: ld a1, 80(a2)
+; ZVE32F-NEXT: vmv.v.x v12, a3
+; ZVE32F-NEXT: srli a3, a3, 32
+; ZVE32F-NEXT: vslide1down.vx v12, v12, a3
+; ZVE32F-NEXT: vslide1down.vx v12, v12, a1
+; ZVE32F-NEXT: srli a1, a1, 32
+; ZVE32F-NEXT: vslide1down.vx v12, v12, a1
; ZVE32F-NEXT: vslidedown.vi v11, v12, 4, v0.t
; ZVE32F-NEXT: vs4r.v v8, (a0)
; ZVE32F-NEXT: ret
@@ -1739,8 +1737,8 @@ define <4 x i64> @unzip2b_dual_v4i64(<4 x i64> %a, <4 x i64> %b) {
; V-LABEL: unzip2b_dual_v4i64:
; V: # %bb.0: # %entry
; V-NEXT: vsetivli zero, 4, e64, m1, ta, mu
-; V-NEXT: vmv.v.i v0, 2
; V-NEXT: vslidedown.vi v10, v8, 1
+; V-NEXT: vmv.v.i v0, 2
; V-NEXT: vslidedown.vi v10, v8, 2, v0.t
; V-NEXT: vmv.v.i v0, 4
; V-NEXT: vmv1r.v v8, v9
@@ -1751,24 +1749,24 @@ define <4 x i64> @unzip2b_dual_v4i64(<4 x i64> %a, <4 x i64> %b) {
;
; ZVE32F-LABEL: unzip2b_dual_v4i64:
; ZVE32F: # %bb.0: # %entry
-; ZVE32F-NEXT: ld a3, 8(a1)
-; ZVE32F-NEXT: ld a1, 24(a1)
-; ZVE32F-NEXT: ld a4, 8(a2)
-; ZVE32F-NEXT: ld a2, 24(a2)
+; ZVE32F-NEXT: ld a3, 24(a1)
+; ZVE32F-NEXT: ld a1, 8(a1)
+; ZVE32F-NEXT: ld a4, 24(a2)
+; ZVE32F-NEXT: ld a2, 8(a2)
+; ZVE32F-NEXT: srli a5, a3, 32
+; ZVE32F-NEXT: srli a6, a1, 32
+; ZVE32F-NEXT: srli a7, a4, 32
+; ZVE32F-NEXT: srli t0, a2, 32
; ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, mu
-; ZVE32F-NEXT: vmv.v.i v0, 15
-; ZVE32F-NEXT: srli a5, a1, 32
-; ZVE32F-NEXT: srli a6, a3, 32
-; ZVE32F-NEXT: srli a7, a2, 32
-; ZVE32F-NEXT: srli t0, a4, 32
-; ZVE32F-NEXT: vmv.v.x v8, a4
-; ZVE32F-NEXT: vmv.v.x v9, a3
+; ZVE32F-NEXT: vmv.v.x v8, a2
+; ZVE32F-NEXT: vmv.v.x v9, a1
; ZVE32F-NEXT: vslide1down.vx v8, v8, t0
; ZVE32F-NEXT: vslide1down.vx v9, v9, a6
-; ZVE32F-NEXT: vslide1down.vx v8, v8, a2
-; ZVE32F-NEXT: vslide1down.vx v9, v9, a1
+; ZVE32F-NEXT: vslide1down.vx v8, v8, a4
+; ZVE32F-NEXT: vslide1down.vx v9, v9, a3
; ZVE32F-NEXT: vslide1down.vx v8, v8, a7
; ZVE32F-NEXT: vslide1down.vx v9, v9, a5
+; ZVE32F-NEXT: vmv.v.i v0, 15
; ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t
; ZVE32F-NEXT: vse32.v v8, (a0)
; ZVE32F-NEXT: ret
@@ -1790,8 +1788,8 @@ define <4 x i64> @unzip2b_dual_v4i64_exact(<4 x i64> %a, <4 x i64> %b) vscale_ra
; V-LABEL: unzip2b_dual_v4i64_exact:
; V: # %bb.0: # %entry
; V-NEXT: vsetivli zero, 4, e64, m1, ta, mu
-; V-NEXT: vmv.v.i v0, 2
; V-NEXT: vslidedown.vi v10, v8, 1
+; V-NEXT: vmv.v.i v0, 2
; V-NEXT: vslidedown.vi v10, v8, 2, v0.t
; V-NEXT: vmv.v.i v0, 4
; V-NEXT: vmv1r.v v8, v9
@@ -1802,24 +1800,24 @@ define <4 x i64> @unzip2b_dual_v4i64_exact(<4 x i64> %a, <4 x i64> %b) vscale_ra
;
; ZVE32F-LABEL: unzip2b_dual_v4i64_exact:
; ZVE32F: # %bb.0: # %entry
-; ZVE32F-NEXT: ld a3, 8(a1)
-; ZVE32F-NEXT: ld a1, 24(a1)
-; ZVE32F-NEXT: ld a4, 8(a2)
-; ZVE32F-NEXT: ld a2, 24(a2)
+; ZVE32F-NEXT: ld a3, 24(a1)
+; ZVE32F-NEXT: ld a1, 8(a1)
+; ZVE32F-NEXT: ld a4, 24(a2)
+; ZVE32F-NEXT: ld a2, 8(a2)
+; ZVE32F-NEXT: srli a5, a3, 32
+; ZVE32F-NEXT: srli a6, a1, 32
+; ZVE32F-NEXT: srli a7, a4, 32
+; ZVE32F-NEXT: srli t0, a2, 32
; ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, mu
-; ZVE32F-NEXT: vmv.v.i v0, 15
-; ZVE32F-NEXT: srli a5, a1, 32
-; ZVE32F-NEXT: srli a6, a3, 32
-; ZVE32F-NEXT: srli a7, a2, 32
-; ZVE32F-NEXT: srli t0, a4, 32
-; ZVE32F-NEXT: vmv.v.x v8, a4
-; ZVE32F-NEXT: vmv.v.x v9, a3
+; ZVE32F-NEXT: vmv.v.x v8, a2
+; ZVE32F-NEXT: vmv.v.x v9, a1
; ZVE32F-NEXT: vslide1down.vx v8, v8, t0
; ZVE32F-NEXT: vslide1down.vx v9, v9, a6
-; ZVE32F-NEXT: vslide1down.vx v8, v8, a2
-; ZVE32F-NEXT: vslide1down.vx v9, v9, a1
+; ZVE32F-NEXT: vslide1down.vx v8, v8, a4
+; ZVE32F-NEXT: vslide1down.vx v9, v9, a3
; ZVE32F-NEXT: vslide1down.vx v8, v8, a7
; ZVE32F-NEXT: vslide1down.vx v9, v9, a5
+; ZVE32F-NEXT: vmv.v.i v0, 15
; ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t
; ZVE32F-NEXT: vs1r.v v8, (a0)
; ZVE32F-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
index 3250821a92534..e32410dcf109d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
@@ -185,12 +185,11 @@ define void @shuffle1(ptr %explicit_0, ptr %explicit_1) vscale_range(2,2) {
; CHECK-NEXT: vsetivli zero, 12, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v10, (a0)
; CHECK-NEXT: vmv.v.i v0, 1
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v10, v10, 1, v0.t
; CHECK-NEXT: vmv.v.i v0, 5
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0
; CHECK-NEXT: addi a0, a1, 672
; CHECK-NEXT: vs2r.v v8, (a0)
@@ -209,13 +208,14 @@ define <16 x float> @shuffle2(<4 x float> %a) vscale_range(2,2) {
; CHECK-LABEL: shuffle2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v12, v8, 1
-; CHECK-NEXT: vmv.v.i v0, 6
-; CHECK-NEXT: vslideup.vi v12, v8, 2
+; CHECK-NEXT: vmv1r.v v12, v8
+; CHECK-NEXT: vslidedown.vi v13, v8, 1
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v9, v9, v12, v0
+; CHECK-NEXT: vslideup.vi v13, v12, 2
+; CHECK-NEXT: vmv.v.i v0, 6
+; CHECK-NEXT: vmerge.vvm v9, v9, v13, v0
; CHECK-NEXT: ret
%b = extractelement <4 x float> %a, i32 2
%c = insertelement <16 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float poison, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %b, i32 5
@@ -253,11 +253,10 @@ define i64 @extract_any_extend_vector_inreg_v16i64(<16 x i64> %a0, i32 %a1) vsca
; RV64-NEXT: addi s0, sp, 256
; RV64-NEXT: .cfi_def_cfa s0, 0
; RV64-NEXT: andi sp, sp, -128
-; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; RV64-NEXT: vmv.v.i v0, 1
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
+; RV64-NEXT: vmv.v.i v0, 1
; RV64-NEXT: vslidedown.vi v18, v15, 1, v0.t
; RV64-NEXT: mv s2, sp
; RV64-NEXT: vs8r.v v16, (s2)
@@ -344,17 +343,19 @@ define i64 @multi_chunks_shuffle(<32 x i32> %0) vscale_range(8,8) {
; RV32-NEXT: vwsubu.vx v10, v12, a0
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV32-NEXT: vmv.v.x v12, a0
-; RV32-NEXT: lui a0, 61681
-; RV32-NEXT: addi a0, a0, -241
; RV32-NEXT: vand.vx v10, v10, a1
; RV32-NEXT: vand.vx v12, v12, a1
; RV32-NEXT: vsrl.vv v10, v8, v10
; RV32-NEXT: vsll.vv v8, v8, v12
-; RV32-NEXT: vmv.s.x v0, a0
+; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; RV32-NEXT: vmv.v.i v12, 0
+; RV32-NEXT: lui a0, 61681
+; RV32-NEXT: addi a0, a0, -241
+; RV32-NEXT: vsetivli zero, 16, e64, m2, ta, ma
; RV32-NEXT: vor.vv v8, v8, v10
+; RV32-NEXT: vmv.s.x v0, a0
; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV32-NEXT: vmv.v.i v10, 0
-; RV32-NEXT: vmerge.vvm v8, v10, v8, v0
+; RV32-NEXT: vmerge.vvm v8, v12, v8, v0
; RV32-NEXT: vrgather.vi v10, v8, 2
; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
@@ -369,12 +370,12 @@ define i64 @multi_chunks_shuffle(<32 x i32> %0) vscale_range(8,8) {
; RV64-NEXT: vsetivli zero, 16, e64, m2, ta, ma
; RV64-NEXT: vsrl.vx v10, v8, a0
; RV64-NEXT: vsll.vx v8, v8, a0
-; RV64-NEXT: lui a0, 61681
-; RV64-NEXT: addi a0, a0, -241
; RV64-NEXT: vor.vv v8, v8, v10
-; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; RV64-NEXT: vmv.v.i v10, 0
+; RV64-NEXT: lui a0, 61681
+; RV64-NEXT: addi a0, a0, -241
+; RV64-NEXT: vmv.s.x v0, a0
; RV64-NEXT: vmerge.vvm v8, v10, v8, v0
; RV64-NEXT: vrgather.vi v10, v8, 2
; RV64-NEXT: vor.vv v8, v8, v10
@@ -433,11 +434,9 @@ define void @shuffle_3_input_vectors() vscale_range(4,4) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 1
-; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v0, 6
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetivli zero, 4, e64, m1, ta, mu
+; CHECK-NEXT: vmv.v.i v0, 6
; CHECK-NEXT: vslidedown.vi v20, v8, 1, v0.t
; CHECK-NEXT: vslideup.vi v20, v9, 3
; CHECK-NEXT: vslidedown.vi v21, v9, 1
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp-interleave.ll
index bc8cdf8832d41..99bdeabeadccb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp-interleave.ll
@@ -53,11 +53,11 @@ define <4 x double> @interleave_v2f64(<2 x double> %x, <2 x double> %y) {
; V512: # %bb.0:
; V512-NEXT: vsetivli zero, 4, e64, m1, ta, ma
; V512-NEXT: vslideup.vi v10, v9, 1
-; V512-NEXT: vmv1r.v v11, v8
; V512-NEXT: vslideup.vi v10, v9, 2
+; V512-NEXT: vmv1r.v v9, v8
+; V512-NEXT: vslideup.vi v9, v8, 1
; V512-NEXT: vmv.v.i v0, 10
-; V512-NEXT: vslideup.vi v11, v8, 1
-; V512-NEXT: vmerge.vvm v8, v11, v10, v0
+; V512-NEXT: vmerge.vvm v8, v9, v10, v0
; V512-NEXT: ret
%a = shufflevector <2 x double> %x, <2 x double> %y, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
ret <4 x double> %a
@@ -251,8 +251,8 @@ define <64 x float> @interleave_v32f32(<32 x float> %x, <32 x float> %y) {
; V128-NEXT: vzext.vf2 v8, v24
; V128-NEXT: addi a1, a1, -1366
; V128-NEXT: vzext.vf2 v24, v0
-; V128-NEXT: vmv.s.x v0, a1
; V128-NEXT: vsll.vx v8, v8, a0
+; V128-NEXT: vmv.s.x v0, a1
; V128-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; V128-NEXT: vmerge.vvm v24, v24, v8, v0
; V128-NEXT: addi a0, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll
index 965d0b0fe0f9b..07f5eca03b2d7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll
@@ -126,9 +126,9 @@ define <8 x float> @vmerge_vxm(<8 x float> %v, float %s) {
; CHECK-LABEL: vmerge_vxm:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 25
-; CHECK-NEXT: vsetivli zero, 1, e32, m4, tu, ma
-; CHECK-NEXT: vmv.s.x v0, a0
+; CHECK-NEXT: vsetivli zero, 8, e32, m1, tu, ma
; CHECK-NEXT: vfmv.s.f v8, fa0
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT: ret
@@ -179,10 +179,10 @@ define <4 x double> @vrgather_shuffle_vv_v4f64(<4 x double> %x, <4 x double> %y)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v12, v8, 1
+; CHECK-NEXT: vslideup.vi v12, v8, 2
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 8
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; CHECK-NEXT: vslideup.vi v12, v8, 2
; CHECK-NEXT: vrgather.vi v12, v10, 1, v0.t
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
@@ -193,17 +193,17 @@ define <4 x double> @vrgather_shuffle_vv_v4f64(<4 x double> %x, <4 x double> %y)
define <4 x double> @vrgather_shuffle_xv_v4f64(<4 x double> %x) {
; RV32-LABEL: vrgather_shuffle_xv_v4f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; RV32-NEXT: vmv.v.i v0, 8
; RV32-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
+; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; RV32-NEXT: vmv.v.i v0, 8
; RV32-NEXT: vmv2r.v v10, v8
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vslideup.vi v10, v8, 2, v0.t
+; RV32-NEXT: vfmv.v.f v8, fa5
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.i v0, 12
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32-NEXT: vfmv.v.f v8, fa5
; RV32-NEXT: vmerge.vvm v8, v8, v10, v0
; RV32-NEXT: ret
;
@@ -216,10 +216,10 @@ define <4 x double> @vrgather_shuffle_xv_v4f64(<4 x double> %x) {
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vslideup.vi v10, v8, 2, v0.t
; RV64-NEXT: slli a0, a0, 62
+; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.i v0, 12
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: vmerge.vvm v8, v8, v10, v0
; RV64-NEXT: ret
%s = shufflevector <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x double> %x, <4 x i32> <i32 0, i32 3, i32 6, i32 5>
@@ -229,16 +229,16 @@ define <4 x double> @vrgather_shuffle_xv_v4f64(<4 x double> %x) {
define <4 x double> @vrgather_shuffle_vx_v4f64(<4 x double> %x) {
; RV32-LABEL: vrgather_shuffle_vx_v4f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; RV32-NEXT: vmv.v.i v0, 2
; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
+; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; RV32-NEXT: vmv.v.i v0, 2
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV32-NEXT: vslidedown.vi v8, v8, 2, v0.t
+; RV32-NEXT: vfmv.v.f v10, fa5
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.i v0, 3
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32-NEXT: vfmv.v.f v10, fa5
; RV32-NEXT: vmerge.vvm v8, v10, v8, v0
; RV32-NEXT: ret
;
@@ -250,10 +250,10 @@ define <4 x double> @vrgather_shuffle_vx_v4f64(<4 x double> %x) {
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vslidedown.vi v8, v8, 2, v0.t
; RV64-NEXT: slli a0, a0, 62
+; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.i v0, 3
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV64-NEXT: vmv.v.x v10, a0
; RV64-NEXT: vmerge.vvm v8, v10, v8, v0
; RV64-NEXT: ret
%s = shufflevector <4 x double> %x, <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x i32> <i32 0, i32 3, i32 6, i32 5>
@@ -431,8 +431,8 @@ define <4 x bfloat> @vrgather_shuffle_vv_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v10, v8, 1
-; CHECK-NEXT: vmv.v.i v0, 8
; CHECK-NEXT: vslideup.vi v10, v8, 2
+; CHECK-NEXT: vmv.v.i v0, 8
; CHECK-NEXT: vrgather.vi v10, v9, 1, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
@@ -469,8 +469,8 @@ define <4 x half> @vrgather_shuffle_vv_v4f16(<4 x half> %x, <4 x half> %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v10, v8, 1
-; CHECK-NEXT: vmv.v.i v0, 8
; CHECK-NEXT: vslideup.vi v10, v8, 2
+; CHECK-NEXT: vmv.v.i v0, 8
; CHECK-NEXT: vrgather.vi v10, v9, 1, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
@@ -532,10 +532,10 @@ define <16 x float> @shuffle_disjoint_lanes_one_broadcast(<16 x float> %v, <16 x
; CHECK-NEXT: addi a0, a0, %lo(.LCPI36_0)
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vle16.v v20, (a0)
+; CHECK-NEXT: vrgather.vi v16, v8, 7
; CHECK-NEXT: lui a0, 15
; CHECK-NEXT: addi a0, a0, 240
; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vrgather.vi v16, v8, 7
; CHECK-NEXT: vrgatherei16.vv v16, v12, v20, v0.t
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
@@ -546,14 +546,14 @@ define <16 x float> @shuffle_disjoint_lanes_one_broadcast(<16 x float> %v, <16 x
define <16 x float> @shuffle_disjoint_lanes_one_splat(float %v, <16 x float> %w) {
; CHECK-LABEL: shuffle_disjoint_lanes_one_splat:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
+; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: lui a0, %hi(.LCPI37_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI37_0)
-; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: lui a0, 15
; CHECK-NEXT: addi a0, a0, 240
; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vrgatherei16.vv v12, v8, v16, v0.t
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
index 9bbfad4f32ffa..ae55d7c2e64fd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
@@ -89,11 +89,11 @@ define <4 x i64> @interleave_v2i64(<2 x i64> %x, <2 x i64> %y) {
; V512: # %bb.0:
; V512-NEXT: vsetivli zero, 4, e64, m1, ta, ma
; V512-NEXT: vslideup.vi v10, v9, 1
-; V512-NEXT: vmv1r.v v11, v8
; V512-NEXT: vslideup.vi v10, v9, 2
+; V512-NEXT: vmv1r.v v9, v8
+; V512-NEXT: vslideup.vi v9, v8, 1
; V512-NEXT: vmv.v.i v0, 10
-; V512-NEXT: vslideup.vi v11, v8, 1
-; V512-NEXT: vmerge.vvm v8, v11, v10, v0
+; V512-NEXT: vmerge.vvm v8, v9, v10, v0
; V512-NEXT: ret
;
; ZIP-LABEL: interleave_v2i64:
@@ -265,11 +265,11 @@ define <4 x i32> @interleave_v4i32_offset_1(<4 x i32> %x, <4 x i32> %y) {
; ZIP: # %bb.0:
; ZIP-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; ZIP-NEXT: vmv.v.i v0, 8
-; ZIP-NEXT: vmv1r.v v10, v9
-; ZIP-NEXT: vslideup.vi v10, v9, 1, v0.t
+; ZIP-NEXT: ri.vzip2a.vv v11, v8, v10
+; ZIP-NEXT: vmv1r.v v8, v9
+; ZIP-NEXT: vslideup.vi v8, v9, 1, v0.t
; ZIP-NEXT: vmv.v.i v0, 10
-; ZIP-NEXT: ri.vzip2a.vv v11, v8, v9
-; ZIP-NEXT: vmerge.vvm v8, v11, v10, v0
+; ZIP-NEXT: vmerge.vvm v8, v11, v8, v0
; ZIP-NEXT: ret
%a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 5, i32 1, i32 6>
ret <4 x i32> %a
@@ -561,8 +561,8 @@ define <64 x i32> @interleave_v32i32(<32 x i32> %x, <32 x i32> %y) {
; V128-NEXT: vzext.vf2 v8, v24
; V128-NEXT: addi a1, a1, -1366
; V128-NEXT: vzext.vf2 v24, v0
-; V128-NEXT: vmv.s.x v0, a1
; V128-NEXT: vsll.vx v8, v8, a0
+; V128-NEXT: vmv.s.x v0, a1
; V128-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; V128-NEXT: vmerge.vvm v24, v24, v8, v0
; V128-NEXT: addi a0, sp, 16
@@ -598,12 +598,13 @@ define <64 x i32> @interleave_v32i32(<32 x i32> %x, <32 x i32> %y) {
; ZIP-NEXT: addi sp, sp, -16
; ZIP-NEXT: .cfi_def_cfa_offset 16
; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 40
+; ZIP-NEXT: li a1, 25
; ZIP-NEXT: mul a0, a0, a1
; ZIP-NEXT: sub sp, sp, a0
-; ZIP-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
+; ZIP-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
+; ZIP-NEXT: slli a1, a0, 4
+; ZIP-NEXT: add a0, a1, a0
; ZIP-NEXT: add a0, sp, a0
; ZIP-NEXT: addi a0, a0, 16
; ZIP-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
@@ -611,43 +612,34 @@ define <64 x i32> @interleave_v32i32(<32 x i32> %x, <32 x i32> %y) {
; ZIP-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZIP-NEXT: li a0, 32
; ZIP-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; ZIP-NEXT: vslidedown.vi v16, v8, 16
+; ZIP-NEXT: vslidedown.vi v8, v8, 16
; ZIP-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; ZIP-NEXT: ri.vzip2a.vv v8, v16, v0
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a1, a1, 3
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 16
-; ZIP-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZIP-NEXT: ri.vzip2a.vv v16, v8, v0
; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a1, a1, 5
+; ZIP-NEXT: slli a2, a1, 4
+; ZIP-NEXT: add a1, a2, a1
; ZIP-NEXT: add a1, sp, a1
; ZIP-NEXT: addi a1, a1, 16
-; ZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; ZIP-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; ZIP-NEXT: vslidedown.vi v16, v16, 16
+; ZIP-NEXT: vslidedown.vi v24, v24, 16
; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: li a2, 24
-; ZIP-NEXT: mul a1, a1, a2
+; ZIP-NEXT: slli a2, a1, 3
+; ZIP-NEXT: add a1, a2, a1
; ZIP-NEXT: add a1, sp, a1
; ZIP-NEXT: addi a1, a1, 16
-; ZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZIP-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; ZIP-NEXT: lui a1, 699051
; ZIP-NEXT: addi a1, a1, -1366
-; ZIP-NEXT: vmv.s.x v0, a1
+; ZIP-NEXT: vmv.s.x v24, a1
; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a1, a1, 4
-; ZIP-NEXT: add a1, sp, a1
-; ZIP-NEXT: addi a1, a1, 16
-; ZIP-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: li a2, 24
-; ZIP-NEXT: mul a1, a1, a2
+; ZIP-NEXT: slli a1, a1, 3
; ZIP-NEXT: add a1, sp, a1
; ZIP-NEXT: addi a1, a1, 16
-; ZIP-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZIP-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
; ZIP-NEXT: csrr a1, vlenb
-; ZIP-NEXT: slli a1, a1, 4
+; ZIP-NEXT: slli a2, a1, 3
+; ZIP-NEXT: add a1, a2, a1
; ZIP-NEXT: add a1, sp, a1
; ZIP-NEXT: addi a1, a1, 16
; ZIP-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
@@ -655,22 +647,21 @@ define <64 x i32> @interleave_v32i32(<32 x i32> %x, <32 x i32> %y) {
; ZIP-NEXT: slli a1, a1, 3
; ZIP-NEXT: add a1, sp, a1
; ZIP-NEXT: addi a1, a1, 16
-; ZIP-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZIP-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZIP-NEXT: vsetvli zero, a0, e32, m8, ta, mu
-; ZIP-NEXT: ri.vzip2a.vv v8, v24, v16, v0.t
-; ZIP-NEXT: vmv.v.v v24, v8
+; ZIP-NEXT: ri.vzip2a.vv v16, v8, v24, v0.t
; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: slli a0, a0, 5
+; ZIP-NEXT: slli a1, a0, 4
+; ZIP-NEXT: add a0, a1, a0
; ZIP-NEXT: add a0, sp, a0
; ZIP-NEXT: addi a0, a0, 16
-; ZIP-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZIP-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZIP-NEXT: addi a0, sp, 16
; ZIP-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZIP-NEXT: ri.vzip2a.vv v0, v8, v16
+; ZIP-NEXT: ri.vzip2a.vv v0, v8, v24
; ZIP-NEXT: vmv.v.v v8, v0
-; ZIP-NEXT: vmv.v.v v16, v24
; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: li a1, 40
+; ZIP-NEXT: li a1, 25
; ZIP-NEXT: mul a0, a0, a1
; ZIP-NEXT: add sp, sp, a0
; ZIP-NEXT: .cfi_def_cfa sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
index 5683476852683..1117a177ac3a2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
@@ -76,8 +76,8 @@ define <4 x i16> @vrgather_shuffle_vv_v4i16(<4 x i16> %x, <4 x i16> %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v10, v8, 1
-; CHECK-NEXT: vmv.v.i v0, 8
; CHECK-NEXT: vslideup.vi v10, v8, 2
+; CHECK-NEXT: vmv.v.i v0, 8
; CHECK-NEXT: vrgather.vi v10, v9, 1, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
@@ -145,44 +145,40 @@ define <8 x i64> @vrgather_permute_shuffle_uv_v8i64(<8 x i64> %x) {
define <8 x i64> @vrgather_shuffle_vv_v8i64(<8 x i64> %x, <8 x i64> %y) {
; RV32-LABEL: vrgather_shuffle_vv_v8i64:
; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV32-NEXT: vmv.v.i v16, 2
; RV32-NEXT: lui a0, %hi(.LCPI11_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI11_0)
-; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vle16.v v20, (a0)
-; RV32-NEXT: vmv.v.i v21, 2
+; RV32-NEXT: li a0, 5
+; RV32-NEXT: vslide1down.vx v21, v16, a0
; RV32-NEXT: li a0, 164
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV32-NEXT: vrgatherei16.vv v16, v8, v20
; RV32-NEXT: vmv.s.x v0, a0
-; RV32-NEXT: li a0, 5
-; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; RV32-NEXT: vslide1down.vx v8, v21, a0
-; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; RV32-NEXT: vrgatherei16.vv v16, v12, v8, v0.t
+; RV32-NEXT: vrgatherei16.vv v16, v12, v21, v0.t
; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret
;
; RV64-LABEL: vrgather_shuffle_vv_v8i64:
; RV64: # %bb.0:
-; RV64-NEXT: li a0, 164
+; RV64-NEXT: lui a0, 163841
+; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: addi a0, a0, 1
+; RV64-NEXT: slli a0, a0, 17
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV64-NEXT: vmv.s.x v0, a0
+; RV64-NEXT: vmv.v.x v20, a0
; RV64-NEXT: lui a0, 327683
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: addi a0, a0, 1
; RV64-NEXT: slli a0, a0, 17
; RV64-NEXT: addi a0, a0, 1
-; RV64-NEXT: vmv.v.x v20, a0
-; RV64-NEXT: lui a0, 163841
-; RV64-NEXT: slli a0, a0, 4
-; RV64-NEXT: addi a0, a0, 1
-; RV64-NEXT: slli a0, a0, 17
-; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV64-NEXT: vrgatherei16.vv v16, v8, v20
-; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV64-NEXT: vmv.v.x v8, a0
+; RV64-NEXT: vmv.v.x v21, a0
+; RV64-NEXT: li a0, 164
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vrgatherei16.vv v16, v12, v8, v0.t
+; RV64-NEXT: vrgatherei16.vv v16, v8, v21
+; RV64-NEXT: vmv.s.x v0, a0
+; RV64-NEXT: vrgatherei16.vv v16, v12, v20, v0.t
; RV64-NEXT: vmv.v.v v8, v16
; RV64-NEXT: ret
%s = shufflevector <8 x i64> %x, <8 x i64> %y, <8 x i32> <i32 1, i32 2, i32 10, i32 5, i32 1, i32 10, i32 3, i32 13>
@@ -192,18 +188,18 @@ define <8 x i64> @vrgather_shuffle_vv_v8i64(<8 x i64> %x, <8 x i64> %y) {
define <8 x i64> @vrgather_shuffle_xv_v8i64(<8 x i64> %x) {
; RV32-LABEL: vrgather_shuffle_xv_v8i64:
; RV32: # %bb.0:
-; RV32-NEXT: lui a0, %hi(.LCPI12_0)
-; RV32-NEXT: addi a0, a0, %lo(.LCPI12_0)
-; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vle16.v v20, (a0)
; RV32-NEXT: lui a0, %hi(.LCPI12_1)
; RV32-NEXT: addi a0, a0, %lo(.LCPI12_1)
-; RV32-NEXT: vle16.v v21, (a0)
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
+; RV32-NEXT: vle16.v v20, (a0)
+; RV32-NEXT: lui a0, %hi(.LCPI12_0)
+; RV32-NEXT: addi a0, a0, %lo(.LCPI12_0)
; RV32-NEXT: vmv.v.i v16, -1
+; RV32-NEXT: vle16.v v21, (a0)
; RV32-NEXT: li a0, 113
+; RV32-NEXT: vrgatherei16.vv v12, v16, v20
; RV32-NEXT: vmv.s.x v0, a0
-; RV32-NEXT: vrgatherei16.vv v12, v16, v21
-; RV32-NEXT: vrgatherei16.vv v12, v8, v20, v0.t
+; RV32-NEXT: vrgatherei16.vv v12, v8, v21, v0.t
; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret
;
@@ -230,15 +226,15 @@ define <8 x i64> @vrgather_shuffle_vx_v8i64(<8 x i64> %x) {
; RV32-NEXT: lui a0, %hi(.LCPI13_1)
; RV32-NEXT: addi a0, a0, %lo(.LCPI13_1)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV32-NEXT: vle16.v v16, (a0)
+; RV32-NEXT: vle16.v v20, (a0)
; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI13_0)
-; RV32-NEXT: vle16.v v17, (a0)
+; RV32-NEXT: vmv.v.i v16, 5
+; RV32-NEXT: vle16.v v21, (a0)
; RV32-NEXT: li a0, 140
+; RV32-NEXT: vrgatherei16.vv v12, v8, v20
; RV32-NEXT: vmv.s.x v0, a0
-; RV32-NEXT: vrgatherei16.vv v12, v8, v16
-; RV32-NEXT: vmv.v.i v8, 5
-; RV32-NEXT: vrgatherei16.vv v12, v8, v17, v0.t
+; RV32-NEXT: vrgatherei16.vv v12, v16, v21, v0.t
; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret
;
@@ -355,10 +351,10 @@ define <8 x i8> @splat_ve4_ins_i1ve3(<8 x i8> %v) {
define <8 x i8> @splat_ve2_we0(<8 x i8> %v, <8 x i8> %w) {
; CHECK-LABEL: splat_ve2_we0:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, 66
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgather.vi v10, v8, 2
+; CHECK-NEXT: li a0, 66
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgather.vi v10, v9, 0, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
@@ -375,9 +371,9 @@ define <8 x i8> @splat_ve2_we0_ins_i0ve4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, tu, ma
; CHECK-NEXT: vmv.s.x v11, a0
; CHECK-NEXT: li a0, 66
-; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vv v10, v8, v11
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgather.vi v10, v9, 0, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
@@ -390,10 +386,10 @@ define <8 x i8> @splat_ve2_we0_ins_i0we4(<8 x i8> %v, <8 x i8> %w) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v11, 4
-; CHECK-NEXT: li a0, 67
-; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vi v10, v8, 2
+; CHECK-NEXT: li a0, 67
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
@@ -409,9 +405,9 @@ define <8 x i8> @splat_ve2_we0_ins_i2ve4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v11, a0
; CHECK-NEXT: li a0, 66
-; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vv v10, v8, v11
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgather.vi v10, v9, 0, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
@@ -423,16 +419,16 @@ define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-LABEL: splat_ve2_we0_ins_i2we4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 4
+; CHECK-NEXT: vmv.v.i v11, 4
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v11, 0
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vrgather.vi v10, v8, 2
; CHECK-NEXT: li a0, 70
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, ma
-; CHECK-NEXT: vslideup.vi v11, v10, 2
+; CHECK-NEXT: vslideup.vi v12, v11, 2
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vrgather.vi v10, v8, 2
-; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t
+; CHECK-NEXT: vrgather.vv v10, v9, v12, v0.t
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 12, i32 2, i32 2, i32 2, i32 8, i32 2>
@@ -659,10 +655,10 @@ define <8 x i8> @merge_slidedown(<8 x i8> %v, <8 x i8> %w) {
define <8 x i8> @merge_non_contiguous_slideup_slidedown(<8 x i8> %v, <8 x i8> %w) {
; CHECK-LABEL: merge_non_contiguous_slideup_slidedown:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, -22
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: li a0, -22
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vslideup.vi v8, v9, 1, v0.t
; CHECK-NEXT: ret
%res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 10, i32 6, i32 12, i32 13, i32 14>
@@ -1044,10 +1040,10 @@ define <16 x i32> @shuffle_disjoint_lanes_one_broadcast(<16 x i32> %v, <16 x i32
; CHECK-NEXT: addi a0, a0, %lo(.LCPI72_0)
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vle16.v v20, (a0)
+; CHECK-NEXT: vrgather.vi v16, v8, 7
; CHECK-NEXT: lui a0, 15
; CHECK-NEXT: addi a0, a0, 240
; CHECK-NEXT: vmv.s.x v0, a0
-; CHECK-NEXT: vrgather.vi v16, v8, 7
; CHECK-NEXT: vrgatherei16.vv v16, v12, v20, v0.t
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret
@@ -1058,14 +1054,14 @@ define <16 x i32> @shuffle_disjoint_lanes_one_broadcast(<16 x i32> %v, <16 x i32
define <16 x i32> @shuffle_disjoint_lanes_one_splat(i32 %v, <16 x i32> %w) {
; CHECK-LABEL: shuffle_disjoint_lanes_one_splat:
; CHECK: # %bb.0:
-; CHECK-NEXT: lui a1, %hi(.LCPI73_0)
-; CHECK-NEXT: addi a1, a1, %lo(.LCPI73_0)
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vle16.v v16, (a1)
-; CHECK-NEXT: lui a1, 15
-; CHECK-NEXT: addi a1, a1, 240
-; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: vmv.v.x v12, a0
+; CHECK-NEXT: lui a0, %hi(.LCPI73_0)
+; CHECK-NEXT: addi a0, a0, %lo(.LCPI73_0)
+; CHECK-NEXT: vle16.v v16, (a0)
+; CHECK-NEXT: lui a0, 15
+; CHECK-NEXT: addi a0, a0, 240
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgatherei16.vv v12, v8, v16, v0.t
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
@@ -1292,10 +1288,11 @@ define void @shuffle_i256_splat(ptr %p) nounwind {
define <16 x i32> @shuffle_m1_prefix(<16 x i32> %a) {
; CHECK-LABEL: shuffle_m1_prefix:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v8, 2
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v0, 12
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; CHECK-NEXT: vslidedown.vi v12, v8, 2
; CHECK-NEXT: vslideup.vi v12, v8, 1, v0.t
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
@@ -1445,9 +1442,9 @@ define <8 x i8> @vmerge_vxm(<8 x i8> %v, i8 %s) {
; CHECK-LABEL: vmerge_vxm:
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 25
-; CHECK-NEXT: vsetivli zero, 1, e8, m1, tu, ma
-; CHECK-NEXT: vmv.s.x v0, a1
+; CHECK-NEXT: vsetivli zero, 8, e8, m1, tu, ma
; CHECK-NEXT: vmv.s.x v8, a0
+; CHECK-NEXT: vmv.s.x v0, a1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
index 5c17283cacd1b..2795ea55292bd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
@@ -510,10 +510,10 @@ define <8 x i16> @shuffle_v8i16_as_i64_16(<8 x i16> %v) {
;
; ZVKB-ZVE32X-LABEL: shuffle_v8i16_as_i64_16:
; ZVKB-ZVE32X: # %bb.0:
-; ZVKB-ZVE32X-NEXT: li a0, 136
; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e16, m2, ta, mu
-; ZVKB-ZVE32X-NEXT: vmv.s.x v0, a0
; ZVKB-ZVE32X-NEXT: vslidedown.vi v10, v8, 1
+; ZVKB-ZVE32X-NEXT: li a0, 136
+; ZVKB-ZVE32X-NEXT: vmv.s.x v0, a0
; ZVKB-ZVE32X-NEXT: vslideup.vi v10, v8, 3, v0.t
; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v10
; ZVKB-ZVE32X-NEXT: ret
@@ -555,10 +555,10 @@ define <8 x i16> @shuffle_v8i16_as_i64_32(<8 x i16> %v) {
;
; ZVKB-ZVE32X-LABEL: shuffle_v8i16_as_i64_32:
; ZVKB-ZVE32X: # %bb.0:
-; ZVKB-ZVE32X-NEXT: li a0, 204
; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e16, m2, ta, mu
-; ZVKB-ZVE32X-NEXT: vmv.s.x v0, a0
; ZVKB-ZVE32X-NEXT: vslidedown.vi v10, v8, 2
+; ZVKB-ZVE32X-NEXT: li a0, 204
+; ZVKB-ZVE32X-NEXT: vmv.s.x v0, a0
; ZVKB-ZVE32X-NEXT: vslideup.vi v10, v8, 2, v0.t
; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v10
; ZVKB-ZVE32X-NEXT: ret
@@ -600,10 +600,10 @@ define <8 x i16> @shuffle_v8i16_as_i64_48(<8 x i16> %v) {
;
; ZVKB-ZVE32X-LABEL: shuffle_v8i16_as_i64_48:
; ZVKB-ZVE32X: # %bb.0:
-; ZVKB-ZVE32X-NEXT: li a0, -18
; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e16, m2, ta, mu
-; ZVKB-ZVE32X-NEXT: vmv.s.x v0, a0
; ZVKB-ZVE32X-NEXT: vslidedown.vi v10, v8, 3
+; ZVKB-ZVE32X-NEXT: li a0, -18
+; ZVKB-ZVE32X-NEXT: vmv.s.x v0, a0
; ZVKB-ZVE32X-NEXT: vslideup.vi v10, v8, 1, v0.t
; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v10
; ZVKB-ZVE32X-NEXT: ret
@@ -645,10 +645,10 @@ define <8 x i32> @shuffle_v8i32_as_i64(<8 x i32> %v) {
;
; ZVKB-ZVE32X-LABEL: shuffle_v8i32_as_i64:
; ZVKB-ZVE32X: # %bb.0:
-; ZVKB-ZVE32X-NEXT: li a0, 170
; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e32, m4, ta, mu
-; ZVKB-ZVE32X-NEXT: vmv.s.x v0, a0
; ZVKB-ZVE32X-NEXT: vslidedown.vi v12, v8, 1
+; ZVKB-ZVE32X-NEXT: li a0, 170
+; ZVKB-ZVE32X-NEXT: vmv.s.x v0, a0
; ZVKB-ZVE32X-NEXT: vslideup.vi v12, v8, 1, v0.t
; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v12
; ZVKB-ZVE32X-NEXT: ret
@@ -714,10 +714,10 @@ define <8 x half> @shuffle_v8f16_as_i64_16(<8 x half> %v) {
;
; ZVKB-ZVE32X-LABEL: shuffle_v8f16_as_i64_16:
; ZVKB-ZVE32X: # %bb.0:
-; ZVKB-ZVE32X-NEXT: li a0, 136
; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e16, m2, ta, mu
-; ZVKB-ZVE32X-NEXT: vmv.s.x v0, a0
; ZVKB-ZVE32X-NEXT: vslidedown.vi v10, v8, 1
+; ZVKB-ZVE32X-NEXT: li a0, 136
+; ZVKB-ZVE32X-NEXT: vmv.s.x v0, a0
; ZVKB-ZVE32X-NEXT: vslideup.vi v10, v8, 3, v0.t
; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v10
; ZVKB-ZVE32X-NEXT: ret
@@ -759,10 +759,10 @@ define <8 x half> @shuffle_v8f16_as_i64_32(<8 x half> %v) {
;
; ZVKB-ZVE32X-LABEL: shuffle_v8f16_as_i64_32:
; ZVKB-ZVE32X: # %bb.0:
-; ZVKB-ZVE32X-NEXT: li a0, 204
; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e16, m2, ta, mu
-; ZVKB-ZVE32X-NEXT: vmv.s.x v0, a0
; ZVKB-ZVE32X-NEXT: vslidedown.vi v10, v8, 2
+; ZVKB-ZVE32X-NEXT: li a0, 204
+; ZVKB-ZVE32X-NEXT: vmv.s.x v0, a0
; ZVKB-ZVE32X-NEXT: vslideup.vi v10, v8, 2, v0.t
; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v10
; ZVKB-ZVE32X-NEXT: ret
@@ -804,10 +804,10 @@ define <8 x half> @shuffle_v8f16_as_i64_48(<8 x half> %v) {
;
; ZVKB-ZVE32X-LABEL: shuffle_v8f16_as_i64_48:
; ZVKB-ZVE32X: # %bb.0:
-; ZVKB-ZVE32X-NEXT: li a0, -18
; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e16, m2, ta, mu
-; ZVKB-ZVE32X-NEXT: vmv.s.x v0, a0
; ZVKB-ZVE32X-NEXT: vslidedown.vi v10, v8, 3
+; ZVKB-ZVE32X-NEXT: li a0, -18
+; ZVKB-ZVE32X-NEXT: vmv.s.x v0, a0
; ZVKB-ZVE32X-NEXT: vslideup.vi v10, v8, 1, v0.t
; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v10
; ZVKB-ZVE32X-NEXT: ret
@@ -849,10 +849,10 @@ define <8 x float> @shuffle_v8f32_as_i64(<8 x float> %v) {
;
; ZVKB-ZVE32X-LABEL: shuffle_v8f32_as_i64:
; ZVKB-ZVE32X: # %bb.0:
-; ZVKB-ZVE32X-NEXT: li a0, 170
; ZVKB-ZVE32X-NEXT: vsetivli zero, 8, e32, m4, ta, mu
-; ZVKB-ZVE32X-NEXT: vmv.s.x v0, a0
; ZVKB-ZVE32X-NEXT: vslidedown.vi v12, v8, 1
+; ZVKB-ZVE32X-NEXT: li a0, 170
+; ZVKB-ZVE32X-NEXT: vmv.s.x v0, a0
; ZVKB-ZVE32X-NEXT: vslideup.vi v12, v8, 1, v0.t
; ZVKB-ZVE32X-NEXT: vmv.v.v v8, v12
; ZVKB-ZVE32X-NEXT: ret
@@ -895,8 +895,8 @@ define <8 x float> @shuffle_v8f32_as_i64_exact(<8 x float> %v) vscale_range(2,2)
; ZVKB-ZVE32X-LABEL: shuffle_v8f32_as_i64_exact:
; ZVKB-ZVE32X: # %bb.0:
; ZVKB-ZVE32X-NEXT: vsetivli zero, 4, e32, m1, ta, mu
-; ZVKB-ZVE32X-NEXT: vmv.v.i v0, 10
; ZVKB-ZVE32X-NEXT: vslidedown.vi v11, v9, 1
+; ZVKB-ZVE32X-NEXT: vmv.v.i v0, 10
; ZVKB-ZVE32X-NEXT: vslideup.vi v11, v9, 1, v0.t
; ZVKB-ZVE32X-NEXT: vslidedown.vi v10, v8, 1
; ZVKB-ZVE32X-NEXT: vslideup.vi v10, v8, 1, v0.t
@@ -909,20 +909,20 @@ define <8 x float> @shuffle_v8f32_as_i64_exact(<8 x float> %v) vscale_range(2,2)
define <8 x i64> @shuffle_v8i64_as_i128(<8 x i64> %v) {
; CHECK-LABEL: shuffle_v8i64_as_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, 170
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vslidedown.vi v12, v8, 1
+; CHECK-NEXT: li a0, 170
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vslideup.vi v12, v8, 1, v0.t
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
;
; ZVKB-V-LABEL: shuffle_v8i64_as_i128:
; ZVKB-V: # %bb.0:
-; ZVKB-V-NEXT: li a0, 170
; ZVKB-V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; ZVKB-V-NEXT: vmv.s.x v0, a0
; ZVKB-V-NEXT: vslidedown.vi v12, v8, 1
+; ZVKB-V-NEXT: li a0, 170
+; ZVKB-V-NEXT: vmv.s.x v0, a0
; ZVKB-V-NEXT: vslideup.vi v12, v8, 1, v0.t
; ZVKB-V-NEXT: vmv.v.v v8, v12
; ZVKB-V-NEXT: ret
@@ -1064,20 +1064,20 @@ define <8 x i64> @shuffle_v8i64_as_i128(<8 x i64> %v) {
define <8 x i64> @shuffle_v8i64_as_i128_2(<8 x i64> %v) {
; CHECK-LABEL: shuffle_v8i64_as_i128_2:
; CHECK: # %bb.0:
-; CHECK-NEXT: li a0, 168
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vslidedown.vi v12, v8, 1
+; CHECK-NEXT: li a0, 168
+; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vslideup.vi v12, v8, 1, v0.t
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
;
; ZVKB-V-LABEL: shuffle_v8i64_as_i128_2:
; ZVKB-V: # %bb.0:
-; ZVKB-V-NEXT: li a0, 168
; ZVKB-V-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; ZVKB-V-NEXT: vmv.s.x v0, a0
; ZVKB-V-NEXT: vslidedown.vi v12, v8, 1
+; ZVKB-V-NEXT: li a0, 168
+; ZVKB-V-NEXT: vmv.s.x v0, a0
; ZVKB-V-NEXT: vslideup.vi v12, v8, 1, v0.t
; ZVKB-V-NEXT: vmv.v.v v8, v12
; ZVKB-V-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
index 6cbf32151e748..998357e223727 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
@@ -64,8 +64,8 @@ define void @gather_masked(ptr noalias nocapture %A, ptr noalias nocapture reado
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a3, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v9, v8
-; CHECK-NEXT: vlse8.v v9, (a1), a4, v0.t
; CHECK-NEXT: vle8.v v10, (a0)
+; CHECK-NEXT: vlse8.v v9, (a1), a4, v0.t
; CHECK-NEXT: vadd.vv v9, v10, v9
; CHECK-NEXT: vse8.v v9, (a0)
; CHECK-NEXT: addi a0, a0, 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
index 8af4ced77be39..f44f90085eabd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
@@ -485,8 +485,6 @@ define <3 x double> @strided_vpload_v3f64_allones_mask(ptr %ptr, i32 signext %st
define <32 x double> @strided_vpload_v32f64(ptr %ptr, i32 signext %stride, <32 x i1> %m, i32 zeroext %evl) nounwind {
; CHECK-LABEL: strided_vpload_v32f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: li a4, 16
; CHECK-NEXT: mv a3, a2
; CHECK-NEXT: bltu a2, a4, .LBB45_2
@@ -496,7 +494,8 @@ define <32 x double> @strided_vpload_v32f64(ptr %ptr, i32 signext %stride, <32 x
; CHECK-NEXT: mul a4, a3, a1
; CHECK-NEXT: addi a5, a2, -16
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v8, v9, 2
+; CHECK-NEXT: vslidedown.vi v8, v0, 2
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: add a4, a0, a4
; CHECK-NEXT: sltu a2, a2, a5
; CHECK-NEXT: addi a2, a2, -1
@@ -541,7 +540,7 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
; CHECK-RV32-LABEL: strided_load_v33f64:
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-RV32-NEXT: vmv1r.v v8, v0
+; CHECK-RV32-NEXT: vmv1r.v v16, v0
; CHECK-RV32-NEXT: li a5, 32
; CHECK-RV32-NEXT: mv a3, a4
; CHECK-RV32-NEXT: bltu a4, a5, .LBB47_2
@@ -560,9 +559,9 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
; CHECK-RV32-NEXT: li a7, 16
; CHECK-RV32-NEXT: .LBB47_4:
; CHECK-RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v0, v8, 4
+; CHECK-RV32-NEXT: vslidedown.vi v0, v16, 4
; CHECK-RV32-NEXT: vsetvli zero, a7, e64, m8, ta, ma
-; CHECK-RV32-NEXT: vlse64.v v16, (a6), a2, v0.t
+; CHECK-RV32-NEXT: vlse64.v v8, (a6), a2, v0.t
; CHECK-RV32-NEXT: addi a6, a3, -16
; CHECK-RV32-NEXT: sltu a3, a3, a6
; CHECK-RV32-NEXT: addi a3, a3, -1
@@ -572,27 +571,28 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
; CHECK-RV32-NEXT: li a4, 16
; CHECK-RV32-NEXT: .LBB47_6:
; CHECK-RV32-NEXT: mul a5, a4, a2
+; CHECK-RV32-NEXT: vmv1r.v v0, v16
; CHECK-RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v0, v8, 2
-; CHECK-RV32-NEXT: add a5, a1, a5
-; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; CHECK-RV32-NEXT: vlse64.v v24, (a5), a2, v0.t
-; CHECK-RV32-NEXT: vmv1r.v v0, v8
+; CHECK-RV32-NEXT: vslidedown.vi v9, v16, 2
; CHECK-RV32-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; CHECK-RV32-NEXT: vlse64.v v8, (a1), a2, v0.t
+; CHECK-RV32-NEXT: vlse64.v v16, (a1), a2, v0.t
+; CHECK-RV32-NEXT: add a1, a1, a5
+; CHECK-RV32-NEXT: vmv1r.v v0, v9
+; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; CHECK-RV32-NEXT: vlse64.v v24, (a1), a2, v0.t
; CHECK-RV32-NEXT: addi a1, a0, 128
; CHECK-RV32-NEXT: addi a2, a0, 256
; CHECK-RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; CHECK-RV32-NEXT: vse64.v v8, (a0)
+; CHECK-RV32-NEXT: vse64.v v16, (a0)
; CHECK-RV32-NEXT: vse64.v v24, (a1)
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vse64.v v16, (a2)
+; CHECK-RV32-NEXT: vse64.v v8, (a2)
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: strided_load_v33f64:
; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-RV64-NEXT: vmv1r.v v8, v0
+; CHECK-RV64-NEXT: vmv1r.v v16, v0
; CHECK-RV64-NEXT: li a5, 32
; CHECK-RV64-NEXT: mv a4, a3
; CHECK-RV64-NEXT: bltu a3, a5, .LBB47_2
@@ -611,9 +611,9 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
; CHECK-RV64-NEXT: li a7, 16
; CHECK-RV64-NEXT: .LBB47_4:
; CHECK-RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v0, v8, 4
+; CHECK-RV64-NEXT: vslidedown.vi v0, v16, 4
; CHECK-RV64-NEXT: vsetvli zero, a7, e64, m8, ta, ma
-; CHECK-RV64-NEXT: vlse64.v v16, (a6), a2, v0.t
+; CHECK-RV64-NEXT: vlse64.v v8, (a6), a2, v0.t
; CHECK-RV64-NEXT: addi a6, a4, -16
; CHECK-RV64-NEXT: sltu a4, a4, a6
; CHECK-RV64-NEXT: addi a4, a4, -1
@@ -623,21 +623,22 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
; CHECK-RV64-NEXT: li a3, 16
; CHECK-RV64-NEXT: .LBB47_6:
; CHECK-RV64-NEXT: mul a5, a3, a2
+; CHECK-RV64-NEXT: vmv1r.v v0, v16
; CHECK-RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v0, v8, 2
-; CHECK-RV64-NEXT: add a5, a1, a5
-; CHECK-RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; CHECK-RV64-NEXT: vlse64.v v24, (a5), a2, v0.t
-; CHECK-RV64-NEXT: vmv1r.v v0, v8
+; CHECK-RV64-NEXT: vslidedown.vi v9, v16, 2
; CHECK-RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; CHECK-RV64-NEXT: vlse64.v v8, (a1), a2, v0.t
+; CHECK-RV64-NEXT: vlse64.v v16, (a1), a2, v0.t
+; CHECK-RV64-NEXT: add a1, a1, a5
+; CHECK-RV64-NEXT: vmv1r.v v0, v9
+; CHECK-RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; CHECK-RV64-NEXT: vlse64.v v24, (a1), a2, v0.t
; CHECK-RV64-NEXT: addi a1, a0, 128
; CHECK-RV64-NEXT: addi a2, a0, 256
; CHECK-RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; CHECK-RV64-NEXT: vse64.v v8, (a0)
+; CHECK-RV64-NEXT: vse64.v v16, (a0)
; CHECK-RV64-NEXT: vse64.v v24, (a1)
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vse64.v v16, (a2)
+; CHECK-RV64-NEXT: vse64.v v8, (a2)
; CHECK-RV64-NEXT: ret
%v = call <33 x double> @llvm.experimental.vp.strided.load.v33f64.p0.i64(ptr %ptr, i64 %stride, <33 x i1> %mask, i32 %evl)
ret <33 x double> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
index 25624ea0fcf6c..6aeac9150820c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll
@@ -416,9 +416,9 @@ define void @strided_store_v32f64(<32 x double> %v, ptr %ptr, i32 signext %strid
; CHECK-NEXT: addi a3, a2, -16
; CHECK-NEXT: sltu a2, a2, a3
; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2
-; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vsse64.v v16, (a0), a1, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
index f992d1f8f7eee..17a76735dfdb1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
@@ -207,28 +207,35 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: sw s0, 28(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset s0, -4
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 72
+; RV32-NEXT: li a3, 82
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: sub sp, sp, a2
-; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0xc8, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 72 * vlenb
-; RV32-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; RV32-NEXT: vmv1r.v v7, v0
+; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0xd2, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 82 * vlenb
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 5
+; RV32-NEXT: li a3, 41
+; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 40
+; RV32-NEXT: li a3, 49
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vslidedown.vi v5, v0, 8
+; RV32-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; RV32-NEXT: vslidedown.vi v8, v0, 8
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 57
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV32-NEXT: vslidedown.vi v4, v0, 4
+; RV32-NEXT: vslidedown.vi v9, v0, 4
; RV32-NEXT: addi a2, a7, -64
-; RV32-NEXT: vslidedown.vi v3, v5, 4
+; RV32-NEXT: vmv1r.v v28, v8
+; RV32-NEXT: vslidedown.vi v8, v8, 4
; RV32-NEXT: sltu a3, a7, a2
; RV32-NEXT: addi a3, a3, -1
; RV32-NEXT: and a4, a3, a2
@@ -251,21 +258,28 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: li a6, 64
; RV32-NEXT: .LBB16_4:
; RV32-NEXT: addi t2, a1, 128
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li t3, 24
+; RV32-NEXT: mul a3, a3, t3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs1r.v v9, (a3) # vscale x 8-byte Folded Spill
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v6, v4, 2
+; RV32-NEXT: vslidedown.vi v29, v9, 2
; RV32-NEXT: addi t6, a1, 512
-; RV32-NEXT: addi t5, a1, 640
-; RV32-NEXT: vslidedown.vi v0, v3, 2
+; RV32-NEXT: addi t4, a1, 640
+; RV32-NEXT: vmv1r.v v30, v8
+; RV32-NEXT: vslidedown.vi v0, v8, 2
; RV32-NEXT: addi t1, t1, -1
; RV32-NEXT: addi t3, a1, 384
-; RV32-NEXT: vslidedown.vi v2, v5, 2
+; RV32-NEXT: vslidedown.vi v31, v28, 2
; RV32-NEXT: li a3, 32
-; RV32-NEXT: addi t4, a6, -32
-; RV32-NEXT: sltu a6, a6, t4
+; RV32-NEXT: addi t5, a6, -32
+; RV32-NEXT: sltu a6, a6, t5
; RV32-NEXT: addi a6, a6, -1
-; RV32-NEXT: and a6, a6, t4
-; RV32-NEXT: addi t4, a6, -16
-; RV32-NEXT: sltu s0, a6, t4
+; RV32-NEXT: and a6, a6, t5
+; RV32-NEXT: addi t5, a6, -16
+; RV32-NEXT: sltu s0, a6, t5
; RV32-NEXT: addi s0, s0, -1
; RV32-NEXT: bltu a6, a2, .LBB16_6
; RV32-NEXT: # %bb.5:
@@ -275,29 +289,35 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: vle64.v v8, (t6)
; RV32-NEXT: csrr t6, vlenb
; RV32-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
-; RV32-NEXT: li a0, 56
+; RV32-NEXT: li a0, 66
; RV32-NEXT: mul t6, t6, a0
; RV32-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
; RV32-NEXT: add t6, sp, t6
; RV32-NEXT: addi t6, t6, 16
; RV32-NEXT: vs8r.v v8, (t6) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vle64.v v8, (t5)
-; RV32-NEXT: vle64.v v16, (t2)
-; RV32-NEXT: vle64.v v24, (a1)
+; RV32-NEXT: vle64.v v16, (t4)
+; RV32-NEXT: vle64.v v8, (t2)
+; RV32-NEXT: csrr t2, vlenb
+; RV32-NEXT: li t4, 25
+; RV32-NEXT: mul t2, t2, t4
+; RV32-NEXT: add t2, sp, t2
+; RV32-NEXT: addi t2, t2, 16
+; RV32-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vle64.v v8, (a1)
; RV32-NEXT: csrr t2, vlenb
-; RV32-NEXT: li t5, 48
-; RV32-NEXT: mul t2, t2, t5
+; RV32-NEXT: li t4, 58
+; RV32-NEXT: mul t2, t2, t4
; RV32-NEXT: add t2, sp, t2
; RV32-NEXT: addi t2, t2, 16
-; RV32-NEXT: vs8r.v v24, (t2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vle64.v v24, (t3)
+; RV32-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vle64.v v8, (t3)
; RV32-NEXT: csrr t2, vlenb
-; RV32-NEXT: slli t2, t2, 3
+; RV32-NEXT: slli t2, t2, 4
; RV32-NEXT: add t2, sp, t2
; RV32-NEXT: addi t2, t2, 16
-; RV32-NEXT: vs8r.v v24, (t2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
; RV32-NEXT: and t2, t1, t0
-; RV32-NEXT: and t1, s0, t4
+; RV32-NEXT: and t1, s0, t5
; RV32-NEXT: addi a1, a1, 256
; RV32-NEXT: mv t0, a4
; RV32-NEXT: bltu a4, a3, .LBB16_8
@@ -305,32 +325,36 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: li t0, 32
; RV32-NEXT: .LBB16_8:
; RV32-NEXT: vsetvli zero, t2, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v24, v8, 0, v0.t
-; RV32-NEXT: csrr t2, vlenb
-; RV32-NEXT: li t3, 24
-; RV32-NEXT: mul t2, t2, t3
-; RV32-NEXT: add t2, sp, t2
-; RV32-NEXT: addi t2, t2, 16
-; RV32-NEXT: vs8r.v v24, (t2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v3
+; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; RV32-NEXT: addi t2, sp, 16
+; RV32-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v30
; RV32-NEXT: csrr t2, vlenb
-; RV32-NEXT: li t3, 56
+; RV32-NEXT: li t3, 66
; RV32-NEXT: mul t2, t2, t3
; RV32-NEXT: add t2, sp, t2
; RV32-NEXT: addi t2, t2, 16
-; RV32-NEXT: vl8r.v v24, (t2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a5, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v8, v24, 0, v0.t
+; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 6
+; RV32-NEXT: li t2, 74
+; RV32-NEXT: mul a5, a5, t2
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vmv1r.v v0, v29
+; RV32-NEXT: csrr a5, vlenb
+; RV32-NEXT: li t2, 25
+; RV32-NEXT: mul a5, a5, t2
+; RV32-NEXT: add a5, sp, a5
+; RV32-NEXT: addi a5, a5, 16
+; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, t1, e32, m4, ta, ma
; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 4
+; RV32-NEXT: slli t1, a5, 5
+; RV32-NEXT: add a5, t1, a5
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
@@ -340,112 +364,122 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: and a5, t0, a5
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vle64.v v8, (a1)
-; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li t0, 57
+; RV32-NEXT: mul a1, a1, t0
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v8, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v30, v7, 2
-; RV32-NEXT: vmv1r.v v0, v4
+; RV32-NEXT: vslidedown.vi v8, v8, 2
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li t0, 48
+; RV32-NEXT: li t0, 25
+; RV32-NEXT: mul a1, a1, t0
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li t0, 58
; RV32-NEXT: mul a1, a1, t0
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li t0, 24
+; RV32-NEXT: mul a1, a1, t0
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsetvli zero, a6, e32, m4, ta, ma
; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a6, 56
+; RV32-NEXT: li a6, 66
; RV32-NEXT: mul a1, a1, a6
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v2
+; RV32-NEXT: vmv1r.v v0, v31
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a5, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v16, v8, 0, v0.t
+; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
; RV32-NEXT: bltu a4, a2, .LBB16_10
; RV32-NEXT: # %bb.9:
; RV32-NEXT: li a4, 16
; RV32-NEXT: .LBB16_10:
-; RV32-NEXT: vmv1r.v v0, v5
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmv1r.v v0, v28
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a4, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v24, v8, 0, v0.t
+; RV32-NEXT: vnsrl.wi v16, v24, 0, v0.t
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a4, 48
+; RV32-NEXT: li a4, 58
; RV32-NEXT: mul a1, a1, a4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: mv a1, a7
; RV32-NEXT: bltu a7, a3, .LBB16_12
; RV32-NEXT: # %bb.11:
; RV32-NEXT: li a1, 32
; RV32-NEXT: .LBB16_12:
-; RV32-NEXT: vmv1r.v v0, v30
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: li a5, 24
-; RV32-NEXT: mul a4, a4, a5
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
+; RV32-NEXT: addi a4, sp, 16
+; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmv4r.v v24, v16
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a4, a4, 4
+; RV32-NEXT: slli a5, a4, 5
+; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: li a5, 24
+; RV32-NEXT: li a5, 74
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a4, a4, 6
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; RV32-NEXT: vslideup.vi v16, v8, 16
+; RV32-NEXT: vslideup.vi v16, v24, 16
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a4, a4, 6
+; RV32-NEXT: li a5, 74
+; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32-NEXT: addi a4, a1, -16
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 56
+; RV32-NEXT: li a6, 66
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vslideup.vi v16, v24, 16
+; RV32-NEXT: vslideup.vi v16, v0, 16
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 56
+; RV32-NEXT: li a6, 66
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 48
+; RV32-NEXT: li a6, 58
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 24
-; RV32-NEXT: mul a5, a5, a6
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
; RV32-NEXT: vslideup.vi v16, v8, 16
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 48
+; RV32-NEXT: li a6, 58
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
@@ -454,19 +488,31 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a4
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a4, a4, 5
+; RV32-NEXT: li a5, 41
+; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: li a5, 25
+; RV32-NEXT: mul a4, a4, a5
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, ma
; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
; RV32-NEXT: bltu a7, a2, .LBB16_14
; RV32-NEXT: # %bb.13:
; RV32-NEXT: li a7, 16
; RV32-NEXT: .LBB16_14:
-; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 40
+; RV32-NEXT: li a2, 57
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 49
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
@@ -478,7 +524,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: vse32.v v24, (a0)
; RV32-NEXT: addi a1, a0, 256
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 48
+; RV32-NEXT: li a3, 58
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
@@ -486,7 +532,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: addi a1, a0, 128
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 56
+; RV32-NEXT: li a3, 66
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
@@ -494,13 +540,14 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: addi a0, a0, 384
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 6
+; RV32-NEXT: li a2, 74
+; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 72
+; RV32-NEXT: li a1, 82
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 32
@@ -517,28 +564,35 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: sd s0, 40(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset s0, -8
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 72
+; RV64-NEXT: li a3, 82
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: sub sp, sp, a2
-; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0xc8, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 72 * vlenb
-; RV64-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; RV64-NEXT: vmv1r.v v7, v0
+; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0xd2, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 82 * vlenb
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: slli a2, a2, 5
+; RV64-NEXT: li a3, 41
+; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 32
; RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 40
+; RV64-NEXT: li a3, 49
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 32
; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vslidedown.vi v5, v0, 8
+; RV64-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; RV64-NEXT: vslidedown.vi v8, v0, 8
+; RV64-NEXT: csrr a2, vlenb
+; RV64-NEXT: li a3, 57
+; RV64-NEXT: mul a2, a2, a3
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: addi a2, a2, 32
+; RV64-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; RV64-NEXT: vslidedown.vi v4, v0, 4
+; RV64-NEXT: vslidedown.vi v9, v0, 4
; RV64-NEXT: addi a2, a7, -64
-; RV64-NEXT: vslidedown.vi v3, v5, 4
+; RV64-NEXT: vmv1r.v v28, v8
+; RV64-NEXT: vslidedown.vi v8, v8, 4
; RV64-NEXT: sltu a3, a7, a2
; RV64-NEXT: addi a3, a3, -1
; RV64-NEXT: and a4, a3, a2
@@ -561,21 +615,28 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: li a6, 64
; RV64-NEXT: .LBB16_4:
; RV64-NEXT: addi t2, a1, 128
+; RV64-NEXT: csrr a3, vlenb
+; RV64-NEXT: li t3, 24
+; RV64-NEXT: mul a3, a3, t3
+; RV64-NEXT: add a3, sp, a3
+; RV64-NEXT: addi a3, a3, 32
+; RV64-NEXT: vs1r.v v9, (a3) # vscale x 8-byte Folded Spill
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vi v6, v4, 2
+; RV64-NEXT: vslidedown.vi v29, v9, 2
; RV64-NEXT: addi t6, a1, 512
-; RV64-NEXT: addi t5, a1, 640
-; RV64-NEXT: vslidedown.vi v0, v3, 2
+; RV64-NEXT: addi t4, a1, 640
+; RV64-NEXT: vmv1r.v v30, v8
+; RV64-NEXT: vslidedown.vi v0, v8, 2
; RV64-NEXT: addi t1, t1, -1
; RV64-NEXT: addi t3, a1, 384
-; RV64-NEXT: vslidedown.vi v2, v5, 2
+; RV64-NEXT: vslidedown.vi v31, v28, 2
; RV64-NEXT: li a3, 32
-; RV64-NEXT: addi t4, a6, -32
-; RV64-NEXT: sltu a6, a6, t4
+; RV64-NEXT: addi t5, a6, -32
+; RV64-NEXT: sltu a6, a6, t5
; RV64-NEXT: addi a6, a6, -1
-; RV64-NEXT: and a6, a6, t4
-; RV64-NEXT: addi t4, a6, -16
-; RV64-NEXT: sltu s0, a6, t4
+; RV64-NEXT: and a6, a6, t5
+; RV64-NEXT: addi t5, a6, -16
+; RV64-NEXT: sltu s0, a6, t5
; RV64-NEXT: addi s0, s0, -1
; RV64-NEXT: bltu a6, a2, .LBB16_6
; RV64-NEXT: # %bb.5:
@@ -585,29 +646,35 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: vle64.v v8, (t6)
; RV64-NEXT: csrr t6, vlenb
; RV64-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT: li a0, 56
+; RV64-NEXT: li a0, 66
; RV64-NEXT: mul t6, t6, a0
; RV64-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: add t6, sp, t6
; RV64-NEXT: addi t6, t6, 32
; RV64-NEXT: vs8r.v v8, (t6) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vle64.v v8, (t5)
-; RV64-NEXT: vle64.v v16, (t2)
-; RV64-NEXT: vle64.v v24, (a1)
+; RV64-NEXT: vle64.v v16, (t4)
+; RV64-NEXT: vle64.v v8, (t2)
+; RV64-NEXT: csrr t2, vlenb
+; RV64-NEXT: li t4, 25
+; RV64-NEXT: mul t2, t2, t4
+; RV64-NEXT: add t2, sp, t2
+; RV64-NEXT: addi t2, t2, 32
+; RV64-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vle64.v v8, (a1)
; RV64-NEXT: csrr t2, vlenb
-; RV64-NEXT: li t5, 48
-; RV64-NEXT: mul t2, t2, t5
+; RV64-NEXT: li t4, 58
+; RV64-NEXT: mul t2, t2, t4
; RV64-NEXT: add t2, sp, t2
; RV64-NEXT: addi t2, t2, 32
-; RV64-NEXT: vs8r.v v24, (t2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vle64.v v24, (t3)
+; RV64-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vle64.v v8, (t3)
; RV64-NEXT: csrr t2, vlenb
-; RV64-NEXT: slli t2, t2, 3
+; RV64-NEXT: slli t2, t2, 4
; RV64-NEXT: add t2, sp, t2
; RV64-NEXT: addi t2, t2, 32
-; RV64-NEXT: vs8r.v v24, (t2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
; RV64-NEXT: and t2, t1, t0
-; RV64-NEXT: and t1, s0, t4
+; RV64-NEXT: and t1, s0, t5
; RV64-NEXT: addi a1, a1, 256
; RV64-NEXT: mv t0, a4
; RV64-NEXT: bltu a4, a3, .LBB16_8
@@ -615,32 +682,36 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: li t0, 32
; RV64-NEXT: .LBB16_8:
; RV64-NEXT: vsetvli zero, t2, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v24, v8, 0, v0.t
-; RV64-NEXT: csrr t2, vlenb
-; RV64-NEXT: li t3, 24
-; RV64-NEXT: mul t2, t2, t3
-; RV64-NEXT: add t2, sp, t2
-; RV64-NEXT: addi t2, t2, 32
-; RV64-NEXT: vs8r.v v24, (t2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v3
+; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; RV64-NEXT: addi t2, sp, 32
+; RV64-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv1r.v v0, v30
; RV64-NEXT: csrr t2, vlenb
-; RV64-NEXT: li t3, 56
+; RV64-NEXT: li t3, 66
; RV64-NEXT: mul t2, t2, t3
; RV64-NEXT: add t2, sp, t2
; RV64-NEXT: addi t2, t2, 32
-; RV64-NEXT: vl8r.v v24, (t2) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, a5, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v8, v24, 0, v0.t
+; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: slli a5, a5, 6
+; RV64-NEXT: li t2, 74
+; RV64-NEXT: mul a5, a5, t2
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vmv1r.v v0, v29
+; RV64-NEXT: csrr a5, vlenb
+; RV64-NEXT: li t2, 25
+; RV64-NEXT: mul a5, a5, t2
+; RV64-NEXT: add a5, sp, a5
+; RV64-NEXT: addi a5, a5, 32
+; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, t1, e32, m4, ta, ma
; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: slli a5, a5, 4
+; RV64-NEXT: slli t1, a5, 5
+; RV64-NEXT: add a5, t1, a5
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
@@ -650,112 +721,122 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: and a5, t0, a5
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vle64.v v8, (a1)
-; RV64-NEXT: addi a1, sp, 32
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 32
; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li t0, 57
+; RV64-NEXT: mul a1, a1, t0
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 32
+; RV64-NEXT: vl1r.v v8, (a1) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vi v30, v7, 2
-; RV64-NEXT: vmv1r.v v0, v4
+; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li t0, 48
+; RV64-NEXT: li t0, 25
+; RV64-NEXT: mul a1, a1, t0
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 32
+; RV64-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li t0, 58
; RV64-NEXT: mul a1, a1, t0
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li t0, 24
+; RV64-NEXT: mul a1, a1, t0
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 32
+; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsetvli zero, a6, e32, m4, ta, ma
; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a6, 56
+; RV64-NEXT: li a6, 66
; RV64-NEXT: mul a1, a1, a6
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v2
+; RV64-NEXT: vmv1r.v v0, v31
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: slli a1, a1, 4
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, a5, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v16, v8, 0, v0.t
+; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
; RV64-NEXT: bltu a4, a2, .LBB16_10
; RV64-NEXT: # %bb.9:
; RV64-NEXT: li a4, 16
; RV64-NEXT: .LBB16_10:
-; RV64-NEXT: vmv1r.v v0, v5
-; RV64-NEXT: addi a1, sp, 32
-; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmv1r.v v0, v28
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 32
+; RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, a4, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v24, v8, 0, v0.t
+; RV64-NEXT: vnsrl.wi v16, v24, 0, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a4, 48
+; RV64-NEXT: li a4, 58
; RV64-NEXT: mul a1, a1, a4
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; RV64-NEXT: mv a1, a7
; RV64-NEXT: bltu a7, a3, .LBB16_12
; RV64-NEXT: # %bb.11:
; RV64-NEXT: li a1, 32
; RV64-NEXT: .LBB16_12:
-; RV64-NEXT: vmv1r.v v0, v30
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: li a5, 24
-; RV64-NEXT: mul a4, a4, a5
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 32
-; RV64-NEXT: vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
+; RV64-NEXT: addi a4, sp, 32
+; RV64-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmv4r.v v24, v16
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 4
+; RV64-NEXT: slli a5, a4, 5
+; RV64-NEXT: add a4, a5, a4
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: li a5, 24
+; RV64-NEXT: li a5, 74
; RV64-NEXT: mul a4, a4, a5
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
-; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 6
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 32
; RV64-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; RV64-NEXT: vslideup.vi v16, v8, 16
+; RV64-NEXT: vslideup.vi v16, v24, 16
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 6
+; RV64-NEXT: li a5, 74
+; RV64-NEXT: mul a4, a4, a5
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64-NEXT: addi a4, a1, -16
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 56
+; RV64-NEXT: li a6, 66
; RV64-NEXT: mul a5, a5, a6
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vslideup.vi v16, v24, 16
+; RV64-NEXT: vslideup.vi v16, v0, 16
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 56
+; RV64-NEXT: li a6, 66
; RV64-NEXT: mul a5, a5, a6
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
; RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 48
+; RV64-NEXT: li a6, 58
; RV64-NEXT: mul a5, a5, a6
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 24
-; RV64-NEXT: mul a5, a5, a6
-; RV64-NEXT: add a5, sp, a5
-; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
; RV64-NEXT: vslideup.vi v16, v8, 16
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 48
+; RV64-NEXT: li a6, 58
; RV64-NEXT: mul a5, a5, a6
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
@@ -764,19 +845,31 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: and a1, a1, a4
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 5
+; RV64-NEXT: li a5, 41
+; RV64-NEXT: mul a4, a4, a5
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
; RV64-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
+; RV64-NEXT: csrr a4, vlenb
+; RV64-NEXT: li a5, 25
+; RV64-NEXT: mul a4, a4, a5
+; RV64-NEXT: add a4, sp, a4
+; RV64-NEXT: addi a4, a4, 32
+; RV64-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsetvli zero, a1, e32, m4, ta, ma
; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
; RV64-NEXT: bltu a7, a2, .LBB16_14
; RV64-NEXT: # %bb.13:
; RV64-NEXT: li a7, 16
; RV64-NEXT: .LBB16_14:
-; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 40
+; RV64-NEXT: li a2, 57
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 32
+; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 49
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
@@ -788,7 +881,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: vse32.v v24, (a0)
; RV64-NEXT: addi a1, a0, 256
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 48
+; RV64-NEXT: li a3, 58
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 32
@@ -796,7 +889,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: vse32.v v8, (a1)
; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 56
+; RV64-NEXT: li a3, 66
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 32
@@ -804,13 +897,14 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: vse32.v v8, (a1)
; RV64-NEXT: addi a0, a0, 384
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 6
+; RV64-NEXT: li a2, 74
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 72
+; RV64-NEXT: li a1, 82
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 48
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll
index dc432efbd5c47..b742f8ac94188 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll
@@ -163,12 +163,12 @@ define <8 x i1> @vaaddu_vv_v8i1_floor(<8 x i1> %x, <8 x i1> %y) {
; CHECK-LABEL: vaaddu_vv_v8i1_floor:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v9, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: csrwi vxrm, 2
-; CHECK-NEXT: vaaddu.vv v8, v10, v8
+; CHECK-NEXT: vaaddu.vv v8, v9, v8
; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
@@ -406,12 +406,12 @@ define <8 x i1> @vaaddu_vv_v8i1_ceil(<8 x i1> %x, <8 x i1> %y) {
; CHECK-LABEL: vaaddu_vv_v8i1_ceil:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v9, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: csrwi vxrm, 0
-; CHECK-NEXT: vaaddu.vv v8, v10, v8
+; CHECK-NEXT: vaaddu.vv v8, v9, v8
; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
index 96dff2464e501..1fc4283795075 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
@@ -350,7 +350,7 @@ define <256 x i8> @vadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %ev
; CHECK-LABEL: vadd_vi_v258i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
@@ -364,7 +364,7 @@ define <256 x i8> @vadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %ev
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 128
; CHECK-NEXT: .LBB32_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
@@ -400,11 +400,11 @@ define <256 x i8> @vadd_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vadd_vi_v258i8_evl129:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v24, (a0)
+; CHECK-NEXT: vlm.v v25, (a0)
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
index da26c63b61e34..c916cff268a14 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll
@@ -434,9 +434,10 @@ define <32 x double> @vfsgnj_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a3, a1, 3
+; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a1, a0, 128
@@ -445,25 +446,36 @@ define <32 x double> @vfsgnj_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v7, v0, 2
; CHECK-NEXT: bltu a2, a1, .LBB34_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB34_2:
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vfsgnj.vv v8, v8, v24, v0.t
; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
index 6bea222ffb90e..71116cdf160f5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
@@ -9,8 +9,8 @@ define <8 x i7> @vdiv_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t
-; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
+; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
index dbc714f50946d..91067b6aa9917 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll
@@ -56,8 +56,8 @@ define <1 x i1> @fcmp_ogt_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -72,8 +72,8 @@ define <1 x i1> @fcmp_ogt_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -101,8 +101,8 @@ define <1 x i1> @fcmp_oge_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -117,8 +117,8 @@ define <1 x i1> @fcmp_oge_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -146,8 +146,8 @@ define <1 x i1> @fcmp_olt_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -162,8 +162,8 @@ define <1 x i1> @fcmp_olt_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -191,8 +191,8 @@ define <1 x i1> @fcmp_ole_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -207,8 +207,8 @@ define <1 x i1> @fcmp_ole_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -387,8 +387,8 @@ define <1 x i1> @fcmp_ugt_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -404,8 +404,8 @@ define <1 x i1> @fcmp_ugt_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -435,8 +435,8 @@ define <1 x i1> @fcmp_uge_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -452,8 +452,8 @@ define <1 x i1> @fcmp_uge_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -483,8 +483,8 @@ define <1 x i1> @fcmp_ult_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -500,8 +500,8 @@ define <1 x i1> @fcmp_ult_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -531,8 +531,8 @@ define <1 x i1> @fcmp_ule_vf_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -548,8 +548,8 @@ define <1 x i1> @fcmp_ule_fv_v1f16(<1 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -688,8 +688,8 @@ define <2 x i1> @fcmp_ogt_vf_v2f16(<2 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -704,8 +704,8 @@ define <2 x i1> @fcmp_ogt_fv_v2f16(<2 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -733,8 +733,8 @@ define <2 x i1> @fcmp_oge_vf_v2f16(<2 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -749,8 +749,8 @@ define <2 x i1> @fcmp_oge_fv_v2f16(<2 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -778,8 +778,8 @@ define <2 x i1> @fcmp_olt_vf_v2f16(<2 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -794,8 +794,8 @@ define <2 x i1> @fcmp_olt_fv_v2f16(<2 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -823,8 +823,8 @@ define <2 x i1> @fcmp_ole_vf_v2f16(<2 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -839,8 +839,8 @@ define <2 x i1> @fcmp_ole_fv_v2f16(<2 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1019,8 +1019,8 @@ define <2 x i1> @fcmp_ugt_vf_v2f16(<2 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1036,8 +1036,8 @@ define <2 x i1> @fcmp_ugt_fv_v2f16(<2 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1067,8 +1067,8 @@ define <2 x i1> @fcmp_uge_vf_v2f16(<2 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1084,8 +1084,8 @@ define <2 x i1> @fcmp_uge_fv_v2f16(<2 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1115,8 +1115,8 @@ define <2 x i1> @fcmp_ult_vf_v2f16(<2 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1132,8 +1132,8 @@ define <2 x i1> @fcmp_ult_fv_v2f16(<2 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1163,8 +1163,8 @@ define <2 x i1> @fcmp_ule_vf_v2f16(<2 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1180,8 +1180,8 @@ define <2 x i1> @fcmp_ule_fv_v2f16(<2 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1320,8 +1320,8 @@ define <4 x i1> @fcmp_ogt_vf_v4f16(<4 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1336,8 +1336,8 @@ define <4 x i1> @fcmp_ogt_fv_v4f16(<4 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1365,8 +1365,8 @@ define <4 x i1> @fcmp_oge_vf_v4f16(<4 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1381,8 +1381,8 @@ define <4 x i1> @fcmp_oge_fv_v4f16(<4 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1410,8 +1410,8 @@ define <4 x i1> @fcmp_olt_vf_v4f16(<4 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1426,8 +1426,8 @@ define <4 x i1> @fcmp_olt_fv_v4f16(<4 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1455,8 +1455,8 @@ define <4 x i1> @fcmp_ole_vf_v4f16(<4 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1471,8 +1471,8 @@ define <4 x i1> @fcmp_ole_fv_v4f16(<4 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1651,8 +1651,8 @@ define <4 x i1> @fcmp_ugt_vf_v4f16(<4 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1668,8 +1668,8 @@ define <4 x i1> @fcmp_ugt_fv_v4f16(<4 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1699,8 +1699,8 @@ define <4 x i1> @fcmp_uge_vf_v4f16(<4 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1716,8 +1716,8 @@ define <4 x i1> @fcmp_uge_fv_v4f16(<4 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1747,8 +1747,8 @@ define <4 x i1> @fcmp_ult_vf_v4f16(<4 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1764,8 +1764,8 @@ define <4 x i1> @fcmp_ult_fv_v4f16(<4 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1795,8 +1795,8 @@ define <4 x i1> @fcmp_ule_vf_v4f16(<4 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1812,8 +1812,8 @@ define <4 x i1> @fcmp_ule_fv_v4f16(<4 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1952,8 +1952,8 @@ define <8 x i1> @fcmp_ogt_vf_v8f16(<8 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1968,8 +1968,8 @@ define <8 x i1> @fcmp_ogt_fv_v8f16(<8 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1997,8 +1997,8 @@ define <8 x i1> @fcmp_oge_vf_v8f16(<8 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -2013,8 +2013,8 @@ define <8 x i1> @fcmp_oge_fv_v8f16(<8 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -2042,8 +2042,8 @@ define <8 x i1> @fcmp_olt_vf_v8f16(<8 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -2058,8 +2058,8 @@ define <8 x i1> @fcmp_olt_fv_v8f16(<8 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -2087,8 +2087,8 @@ define <8 x i1> @fcmp_ole_vf_v8f16(<8 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -2103,8 +2103,8 @@ define <8 x i1> @fcmp_ole_fv_v8f16(<8 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -2283,8 +2283,8 @@ define <8 x i1> @fcmp_ugt_vf_v8f16(<8 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -2300,8 +2300,8 @@ define <8 x i1> @fcmp_ugt_fv_v8f16(<8 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -2331,8 +2331,8 @@ define <8 x i1> @fcmp_uge_vf_v8f16(<8 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -2348,8 +2348,8 @@ define <8 x i1> @fcmp_uge_fv_v8f16(<8 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -2379,8 +2379,8 @@ define <8 x i1> @fcmp_ult_vf_v8f16(<8 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -2396,8 +2396,8 @@ define <8 x i1> @fcmp_ult_fv_v8f16(<8 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -2427,8 +2427,8 @@ define <8 x i1> @fcmp_ule_vf_v8f16(<8 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -2444,8 +2444,8 @@ define <8 x i1> @fcmp_ule_fv_v8f16(<8 x half> %va, half %b) nounwind strictfp {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -2777,8 +2777,8 @@ define <16 x i1> @fcmp_one_vv_v16f16(<16 x half> %va, <16 x half> %vb) nounwind
; CHECK-NEXT: vmfeq.vv v12, v10, v10
; CHECK-NEXT: vmfeq.vv v13, v8, v8
; CHECK-NEXT: vmand.mm v12, v13, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vv v13, v8, v10, v0.t
; CHECK-NEXT: vmflt.vv v12, v10, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v13
@@ -2795,8 +2795,8 @@ define <16 x i1> @fcmp_one_vf_v16f16(<16 x half> %va, half %b) nounwind strictfp
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v12, v13
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v10, v11
@@ -2815,8 +2815,8 @@ define <16 x i1> @fcmp_one_fv_v16f16(<16 x half> %va, half %b) nounwind strictfp
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v13, v12
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v10, v11
@@ -2876,8 +2876,8 @@ define <16 x i1> @fcmp_ueq_vv_v16f16(<16 x half> %va, <16 x half> %vb) nounwind
; CHECK-NEXT: vmfeq.vv v12, v10, v10
; CHECK-NEXT: vmfeq.vv v13, v8, v8
; CHECK-NEXT: vmand.mm v12, v13, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vv v13, v8, v10, v0.t
; CHECK-NEXT: vmflt.vv v12, v10, v8, v0.t
; CHECK-NEXT: vmnor.mm v0, v12, v13
@@ -2894,8 +2894,8 @@ define <16 x i1> @fcmp_ueq_vf_v16f16(<16 x half> %va, half %b) nounwind strictfp
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v12, v13
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v10, v11
@@ -2914,8 +2914,8 @@ define <16 x i1> @fcmp_ueq_fv_v16f16(<16 x half> %va, half %b) nounwind strictfp
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v13, v12
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v10, v11
@@ -3467,8 +3467,8 @@ define <32 x i1> @fcmp_one_vv_v32f16(<32 x half> %va, <32 x half> %vb) nounwind
; CHECK-NEXT: vmfeq.vv v16, v12, v12
; CHECK-NEXT: vmfeq.vv v17, v8, v8
; CHECK-NEXT: vmand.mm v16, v17, v16
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vv v17, v8, v12, v0.t
; CHECK-NEXT: vmflt.vv v16, v12, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v16, v17
@@ -3486,8 +3486,8 @@ define <32 x i1> @fcmp_one_vf_v32f16(<32 x half> %va, half %b) nounwind strictfp
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v12, v16
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v13
@@ -3507,8 +3507,8 @@ define <32 x i1> @fcmp_one_fv_v32f16(<32 x half> %va, half %b) nounwind strictfp
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v16, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v13
@@ -3572,8 +3572,8 @@ define <32 x i1> @fcmp_ueq_vv_v32f16(<32 x half> %va, <32 x half> %vb) nounwind
; CHECK-NEXT: vmfeq.vv v16, v12, v12
; CHECK-NEXT: vmfeq.vv v17, v8, v8
; CHECK-NEXT: vmand.mm v16, v17, v16
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vv v17, v8, v12, v0.t
; CHECK-NEXT: vmflt.vv v16, v12, v8, v0.t
; CHECK-NEXT: vmnor.mm v0, v16, v17
@@ -3591,8 +3591,8 @@ define <32 x i1> @fcmp_ueq_vf_v32f16(<32 x half> %va, half %b) nounwind strictfp
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v12, v16
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v12, v13
@@ -3612,8 +3612,8 @@ define <32 x i1> @fcmp_ueq_fv_v32f16(<32 x half> %va, half %b) nounwind strictfp
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v16, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v12, v13
@@ -3974,8 +3974,8 @@ define <1 x i1> @fcmp_ogt_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -3990,8 +3990,8 @@ define <1 x i1> @fcmp_ogt_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4019,8 +4019,8 @@ define <1 x i1> @fcmp_oge_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4035,8 +4035,8 @@ define <1 x i1> @fcmp_oge_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4064,8 +4064,8 @@ define <1 x i1> @fcmp_olt_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4080,8 +4080,8 @@ define <1 x i1> @fcmp_olt_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4109,8 +4109,8 @@ define <1 x i1> @fcmp_ole_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4125,8 +4125,8 @@ define <1 x i1> @fcmp_ole_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4305,8 +4305,8 @@ define <1 x i1> @fcmp_ugt_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4322,8 +4322,8 @@ define <1 x i1> @fcmp_ugt_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4353,8 +4353,8 @@ define <1 x i1> @fcmp_uge_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4370,8 +4370,8 @@ define <1 x i1> @fcmp_uge_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4401,8 +4401,8 @@ define <1 x i1> @fcmp_ult_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4418,8 +4418,8 @@ define <1 x i1> @fcmp_ult_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4449,8 +4449,8 @@ define <1 x i1> @fcmp_ule_vf_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4466,8 +4466,8 @@ define <1 x i1> @fcmp_ule_fv_v1f32(<1 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4606,8 +4606,8 @@ define <2 x i1> @fcmp_ogt_vf_v2f32(<2 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4622,8 +4622,8 @@ define <2 x i1> @fcmp_ogt_fv_v2f32(<2 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4651,8 +4651,8 @@ define <2 x i1> @fcmp_oge_vf_v2f32(<2 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4667,8 +4667,8 @@ define <2 x i1> @fcmp_oge_fv_v2f32(<2 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4696,8 +4696,8 @@ define <2 x i1> @fcmp_olt_vf_v2f32(<2 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4712,8 +4712,8 @@ define <2 x i1> @fcmp_olt_fv_v2f32(<2 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4741,8 +4741,8 @@ define <2 x i1> @fcmp_ole_vf_v2f32(<2 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4757,8 +4757,8 @@ define <2 x i1> @fcmp_ole_fv_v2f32(<2 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4937,8 +4937,8 @@ define <2 x i1> @fcmp_ugt_vf_v2f32(<2 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4954,8 +4954,8 @@ define <2 x i1> @fcmp_ugt_fv_v2f32(<2 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4985,8 +4985,8 @@ define <2 x i1> @fcmp_uge_vf_v2f32(<2 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5002,8 +5002,8 @@ define <2 x i1> @fcmp_uge_fv_v2f32(<2 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5033,8 +5033,8 @@ define <2 x i1> @fcmp_ult_vf_v2f32(<2 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5050,8 +5050,8 @@ define <2 x i1> @fcmp_ult_fv_v2f32(<2 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5081,8 +5081,8 @@ define <2 x i1> @fcmp_ule_vf_v2f32(<2 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5098,8 +5098,8 @@ define <2 x i1> @fcmp_ule_fv_v2f32(<2 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5238,8 +5238,8 @@ define <4 x i1> @fcmp_ogt_vf_v4f32(<4 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -5254,8 +5254,8 @@ define <4 x i1> @fcmp_ogt_fv_v4f32(<4 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -5283,8 +5283,8 @@ define <4 x i1> @fcmp_oge_vf_v4f32(<4 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -5299,8 +5299,8 @@ define <4 x i1> @fcmp_oge_fv_v4f32(<4 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -5328,8 +5328,8 @@ define <4 x i1> @fcmp_olt_vf_v4f32(<4 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -5344,8 +5344,8 @@ define <4 x i1> @fcmp_olt_fv_v4f32(<4 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -5373,8 +5373,8 @@ define <4 x i1> @fcmp_ole_vf_v4f32(<4 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -5389,8 +5389,8 @@ define <4 x i1> @fcmp_ole_fv_v4f32(<4 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -5569,8 +5569,8 @@ define <4 x i1> @fcmp_ugt_vf_v4f32(<4 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5586,8 +5586,8 @@ define <4 x i1> @fcmp_ugt_fv_v4f32(<4 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5617,8 +5617,8 @@ define <4 x i1> @fcmp_uge_vf_v4f32(<4 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5634,8 +5634,8 @@ define <4 x i1> @fcmp_uge_fv_v4f32(<4 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5665,8 +5665,8 @@ define <4 x i1> @fcmp_ult_vf_v4f32(<4 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5682,8 +5682,8 @@ define <4 x i1> @fcmp_ult_fv_v4f32(<4 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5713,8 +5713,8 @@ define <4 x i1> @fcmp_ule_vf_v4f32(<4 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5730,8 +5730,8 @@ define <4 x i1> @fcmp_ule_fv_v4f32(<4 x float> %va, float %b) nounwind strictfp
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -6063,8 +6063,8 @@ define <8 x i1> @fcmp_one_vv_v8f32(<8 x float> %va, <8 x float> %vb) nounwind st
; CHECK-NEXT: vmfeq.vv v12, v10, v10
; CHECK-NEXT: vmfeq.vv v13, v8, v8
; CHECK-NEXT: vmand.mm v12, v13, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vv v13, v8, v10, v0.t
; CHECK-NEXT: vmflt.vv v12, v10, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v13
@@ -6081,8 +6081,8 @@ define <8 x i1> @fcmp_one_vf_v8f32(<8 x float> %va, float %b) nounwind strictfp
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v12, v13
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v10, v11
@@ -6101,8 +6101,8 @@ define <8 x i1> @fcmp_one_fv_v8f32(<8 x float> %va, float %b) nounwind strictfp
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v13, v12
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v10, v11
@@ -6162,8 +6162,8 @@ define <8 x i1> @fcmp_ueq_vv_v8f32(<8 x float> %va, <8 x float> %vb) nounwind st
; CHECK-NEXT: vmfeq.vv v12, v10, v10
; CHECK-NEXT: vmfeq.vv v13, v8, v8
; CHECK-NEXT: vmand.mm v12, v13, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vv v13, v8, v10, v0.t
; CHECK-NEXT: vmflt.vv v12, v10, v8, v0.t
; CHECK-NEXT: vmnor.mm v0, v12, v13
@@ -6180,8 +6180,8 @@ define <8 x i1> @fcmp_ueq_vf_v8f32(<8 x float> %va, float %b) nounwind strictfp
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v12, v13
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v10, v11
@@ -6200,8 +6200,8 @@ define <8 x i1> @fcmp_ueq_fv_v8f32(<8 x float> %va, float %b) nounwind strictfp
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v13, v12
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v10, v11
@@ -6737,8 +6737,8 @@ define <16 x i1> @fcmp_one_vv_v16f32(<16 x float> %va, <16 x float> %vb) nounwin
; CHECK-NEXT: vmfeq.vv v16, v12, v12
; CHECK-NEXT: vmfeq.vv v17, v8, v8
; CHECK-NEXT: vmand.mm v16, v17, v16
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vv v17, v8, v12, v0.t
; CHECK-NEXT: vmflt.vv v16, v12, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v16, v17
@@ -6755,8 +6755,8 @@ define <16 x i1> @fcmp_one_vf_v16f32(<16 x float> %va, float %b) nounwind strict
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v12, v16
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v13
@@ -6775,8 +6775,8 @@ define <16 x i1> @fcmp_one_fv_v16f32(<16 x float> %va, float %b) nounwind strict
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v16, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v13
@@ -6836,8 +6836,8 @@ define <16 x i1> @fcmp_ueq_vv_v16f32(<16 x float> %va, <16 x float> %vb) nounwin
; CHECK-NEXT: vmfeq.vv v16, v12, v12
; CHECK-NEXT: vmfeq.vv v17, v8, v8
; CHECK-NEXT: vmand.mm v16, v17, v16
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vv v17, v8, v12, v0.t
; CHECK-NEXT: vmflt.vv v16, v12, v8, v0.t
; CHECK-NEXT: vmnor.mm v0, v16, v17
@@ -6854,8 +6854,8 @@ define <16 x i1> @fcmp_ueq_vf_v16f32(<16 x float> %va, float %b) nounwind strict
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v12, v16
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v12, v13
@@ -6874,8 +6874,8 @@ define <16 x i1> @fcmp_ueq_fv_v16f32(<16 x float> %va, float %b) nounwind strict
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v16, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v12, v13
@@ -7218,8 +7218,8 @@ define <1 x i1> @fcmp_ogt_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7234,8 +7234,8 @@ define <1 x i1> @fcmp_ogt_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7263,8 +7263,8 @@ define <1 x i1> @fcmp_oge_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7279,8 +7279,8 @@ define <1 x i1> @fcmp_oge_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7308,8 +7308,8 @@ define <1 x i1> @fcmp_olt_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7324,8 +7324,8 @@ define <1 x i1> @fcmp_olt_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7353,8 +7353,8 @@ define <1 x i1> @fcmp_ole_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7369,8 +7369,8 @@ define <1 x i1> @fcmp_ole_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7549,8 +7549,8 @@ define <1 x i1> @fcmp_ugt_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -7566,8 +7566,8 @@ define <1 x i1> @fcmp_ugt_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -7597,8 +7597,8 @@ define <1 x i1> @fcmp_uge_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -7614,8 +7614,8 @@ define <1 x i1> @fcmp_uge_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -7645,8 +7645,8 @@ define <1 x i1> @fcmp_ult_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -7662,8 +7662,8 @@ define <1 x i1> @fcmp_ult_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -7693,8 +7693,8 @@ define <1 x i1> @fcmp_ule_vf_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -7710,8 +7710,8 @@ define <1 x i1> @fcmp_ule_fv_v1f64(<1 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
; CHECK-NEXT: vfmv.s.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -7850,8 +7850,8 @@ define <2 x i1> @fcmp_ogt_vf_v2f64(<2 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7866,8 +7866,8 @@ define <2 x i1> @fcmp_ogt_fv_v2f64(<2 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7895,8 +7895,8 @@ define <2 x i1> @fcmp_oge_vf_v2f64(<2 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7911,8 +7911,8 @@ define <2 x i1> @fcmp_oge_fv_v2f64(<2 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7940,8 +7940,8 @@ define <2 x i1> @fcmp_olt_vf_v2f64(<2 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7956,8 +7956,8 @@ define <2 x i1> @fcmp_olt_fv_v2f64(<2 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7985,8 +7985,8 @@ define <2 x i1> @fcmp_ole_vf_v2f64(<2 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -8001,8 +8001,8 @@ define <2 x i1> @fcmp_ole_fv_v2f64(<2 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -8181,8 +8181,8 @@ define <2 x i1> @fcmp_ugt_vf_v2f64(<2 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -8198,8 +8198,8 @@ define <2 x i1> @fcmp_ugt_fv_v2f64(<2 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -8229,8 +8229,8 @@ define <2 x i1> @fcmp_uge_vf_v2f64(<2 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -8246,8 +8246,8 @@ define <2 x i1> @fcmp_uge_fv_v2f64(<2 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -8277,8 +8277,8 @@ define <2 x i1> @fcmp_ult_vf_v2f64(<2 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -8294,8 +8294,8 @@ define <2 x i1> @fcmp_ult_fv_v2f64(<2 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -8325,8 +8325,8 @@ define <2 x i1> @fcmp_ule_vf_v2f64(<2 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -8342,8 +8342,8 @@ define <2 x i1> @fcmp_ule_fv_v2f64(<2 x double> %va, double %b) nounwind strictf
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -8675,8 +8675,8 @@ define <4 x i1> @fcmp_one_vv_v4f64(<4 x double> %va, <4 x double> %vb) nounwind
; CHECK-NEXT: vmfeq.vv v12, v10, v10
; CHECK-NEXT: vmfeq.vv v13, v8, v8
; CHECK-NEXT: vmand.mm v12, v13, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vv v13, v8, v10, v0.t
; CHECK-NEXT: vmflt.vv v12, v10, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v13
@@ -8693,8 +8693,8 @@ define <4 x i1> @fcmp_one_vf_v4f64(<4 x double> %va, double %b) nounwind strictf
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v12, v13
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v10, v11
@@ -8713,8 +8713,8 @@ define <4 x i1> @fcmp_one_fv_v4f64(<4 x double> %va, double %b) nounwind strictf
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v13, v12
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v10, v11
@@ -8774,8 +8774,8 @@ define <4 x i1> @fcmp_ueq_vv_v4f64(<4 x double> %va, <4 x double> %vb) nounwind
; CHECK-NEXT: vmfeq.vv v12, v10, v10
; CHECK-NEXT: vmfeq.vv v13, v8, v8
; CHECK-NEXT: vmand.mm v12, v13, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vv v13, v8, v10, v0.t
; CHECK-NEXT: vmflt.vv v12, v10, v8, v0.t
; CHECK-NEXT: vmnor.mm v0, v12, v13
@@ -8792,8 +8792,8 @@ define <4 x i1> @fcmp_ueq_vf_v4f64(<4 x double> %va, double %b) nounwind strictf
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v12, v13
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v10, v11
@@ -8812,8 +8812,8 @@ define <4 x i1> @fcmp_ueq_fv_v4f64(<4 x double> %va, double %b) nounwind strictf
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v13, v12
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v10, v11
@@ -9349,8 +9349,8 @@ define <8 x i1> @fcmp_one_vv_v8f64(<8 x double> %va, <8 x double> %vb) nounwind
; CHECK-NEXT: vmfeq.vv v16, v12, v12
; CHECK-NEXT: vmfeq.vv v17, v8, v8
; CHECK-NEXT: vmand.mm v16, v17, v16
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vv v17, v8, v12, v0.t
; CHECK-NEXT: vmflt.vv v16, v12, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v16, v17
@@ -9367,8 +9367,8 @@ define <8 x i1> @fcmp_one_vf_v8f64(<8 x double> %va, double %b) nounwind strictf
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v12, v16
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v13
@@ -9387,8 +9387,8 @@ define <8 x i1> @fcmp_one_fv_v8f64(<8 x double> %va, double %b) nounwind strictf
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v16, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v13
@@ -9448,8 +9448,8 @@ define <8 x i1> @fcmp_ueq_vv_v8f64(<8 x double> %va, <8 x double> %vb) nounwind
; CHECK-NEXT: vmfeq.vv v16, v12, v12
; CHECK-NEXT: vmfeq.vv v17, v8, v8
; CHECK-NEXT: vmand.mm v16, v17, v16
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vv v17, v8, v12, v0.t
; CHECK-NEXT: vmflt.vv v16, v12, v8, v0.t
; CHECK-NEXT: vmnor.mm v0, v16, v17
@@ -9466,8 +9466,8 @@ define <8 x i1> @fcmp_ueq_vf_v8f64(<8 x double> %va, double %b) nounwind strictf
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v12, v16
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v12, v13
@@ -9486,8 +9486,8 @@ define <8 x i1> @fcmp_ueq_fv_v8f64(<8 x double> %va, double %b) nounwind strictf
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v16, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v12, v13
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
index f28b970f48ff7..1d3df7a95b826 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
@@ -807,51 +807,84 @@ define <32 x double> @vfma_vv_v32f64(<32 x double> %va, <32 x double> %b, <32 x
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 5
+; CHECK-NEXT: li a3, 49
+; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: li a3, 41
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: li a3, 25
+; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a1, a2, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; CHECK-NEXT: vle64.v v24, (a2)
+; CHECK-NEXT: vle64.v v8, (a2)
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a2, a0, 128
; CHECK-NEXT: vle64.v v8, (a1)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a3, a1, 4
+; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vle64.v v8, (a2)
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: mv a0, a4
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v7, v0, 2
+; CHECK-NEXT: vslidedown.vi v16, v0, 2
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vs1r.v v16, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: bltu a4, a1, .LBB50_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a2, a1, 5
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: li a2, 25
+; CHECK-NEXT: mul a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a2, a1, 3
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vfmadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a1, a0, 5
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
@@ -859,30 +892,36 @@ define <32 x double> @vfma_vv_v32f64(<32 x double> %va, <32 x double> %b, <32 x
; CHECK-NEXT: sltu a1, a4, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a2, 24
+; CHECK-NEXT: li a2, 41
; CHECK-NEXT: mul a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a2, a1, 4
+; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vfmadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: vmv.v.v v16, v8
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a1, a0, 5
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: li a1, 49
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
index 403d0b8d57940..8dffc6d2baa8a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll
@@ -362,9 +362,10 @@ define <32 x double> @vfmax_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a3, a1, 3
+; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a1, a0, 128
@@ -373,25 +374,36 @@ define <32 x double> @vfmax_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v7, v0, 2
; CHECK-NEXT: bltu a2, a1, .LBB26_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB26_2:
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vfmax.vv v8, v8, v24, v0.t
; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vfmax.vv v16, v24, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
index 56f7a8d48c5a1..1712ba34c84af 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll
@@ -362,9 +362,10 @@ define <32 x double> @vfmin_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a3, a1, 3
+; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a1, a0, 128
@@ -373,25 +374,36 @@ define <32 x double> @vfmin_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v7, v0, 2
; CHECK-NEXT: bltu a2, a1, .LBB26_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB26_2:
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vfmin.vv v8, v8, v24, v0.t
; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vfmin.vv v16, v24, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
index a9857880b5942..b7507131007c1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
@@ -579,51 +579,84 @@ define <32 x double> @vfma_vv_v32f64(<32 x double> %va, <32 x double> %b, <32 x
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 5
+; CHECK-NEXT: li a3, 49
+; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: li a3, 41
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: li a3, 25
+; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a1, a2, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; CHECK-NEXT: vle64.v v24, (a2)
+; CHECK-NEXT: vle64.v v8, (a2)
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a2, a0, 128
; CHECK-NEXT: vle64.v v8, (a1)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a3, a1, 4
+; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vle64.v v8, (a2)
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: mv a0, a4
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v7, v0, 2
+; CHECK-NEXT: vslidedown.vi v16, v0, 2
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vs1r.v v16, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: bltu a4, a1, .LBB50_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a2, a1, 5
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: li a2, 25
+; CHECK-NEXT: mul a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a2, a1, 3
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vfmadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a1, a0, 5
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
@@ -631,30 +664,36 @@ define <32 x double> @vfma_vv_v32f64(<32 x double> %va, <32 x double> %b, <32 x
; CHECK-NEXT: sltu a1, a4, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a2, 24
+; CHECK-NEXT: li a2, 41
; CHECK-NEXT: mul a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a2, a1, 4
+; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vfmadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: vmv.v.v v16, v8
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a1, a0, 5
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: li a1, 49
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
index f5978de080082..eafb52c1c006a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
@@ -9,8 +9,8 @@ define <8 x i7> @vmax_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t
-; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
+; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -254,7 +254,7 @@ define <256 x i8> @vmax_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zero
; CHECK-LABEL: vmax_vx_v258i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
@@ -268,7 +268,7 @@ define <256 x i8> @vmax_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zero
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: .LBB22_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vmax.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
@@ -308,11 +308,11 @@ define <256 x i8> @vmax_vx_v258i8_evl129(<256 x i8> %va, i8 %b, <256 x i1> %m) {
; CHECK-LABEL: vmax_vx_v258i8_evl129:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v24, (a1)
+; CHECK-NEXT: vlm.v v25, (a1)
; CHECK-NEXT: li a1, 128
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmax.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
; CHECK-NEXT: vmax.vx v16, v16, a0, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
index 7450a70df66ba..dd234cb203873 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
@@ -253,7 +253,7 @@ define <256 x i8> @vmaxu_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zer
; CHECK-LABEL: vmaxu_vx_v258i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
@@ -267,7 +267,7 @@ define <256 x i8> @vmaxu_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zer
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: .LBB22_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vmaxu.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
@@ -307,11 +307,11 @@ define <256 x i8> @vmaxu_vx_v258i8_evl129(<256 x i8> %va, i8 %b, <256 x i1> %m)
; CHECK-LABEL: vmaxu_vx_v258i8_evl129:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v24, (a1)
+; CHECK-NEXT: vlm.v v25, (a1)
; CHECK-NEXT: li a1, 128
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmaxu.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
; CHECK-NEXT: vmaxu.vx v16, v16, a0, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
index 31d19304c2909..609d1df976dde 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
@@ -9,8 +9,8 @@ define <8 x i7> @vmin_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t
-; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
+; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -254,7 +254,7 @@ define <256 x i8> @vmin_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zero
; CHECK-LABEL: vmin_vx_v258i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
@@ -268,7 +268,7 @@ define <256 x i8> @vmin_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zero
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: .LBB22_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
@@ -308,11 +308,11 @@ define <256 x i8> @vmin_vx_v258i8_evl129(<256 x i8> %va, i8 %b, <256 x i1> %m) {
; CHECK-LABEL: vmin_vx_v258i8_evl129:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v24, (a1)
+; CHECK-NEXT: vlm.v v25, (a1)
; CHECK-NEXT: li a1, 128
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
; CHECK-NEXT: vmin.vx v16, v16, a0, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
index dda69ec8a7d2e..7c4efb760393e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
@@ -253,7 +253,7 @@ define <256 x i8> @vminu_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zer
; CHECK-LABEL: vminu_vx_v258i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
@@ -267,7 +267,7 @@ define <256 x i8> @vminu_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zer
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: .LBB22_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
@@ -307,11 +307,11 @@ define <256 x i8> @vminu_vx_v258i8_evl129(<256 x i8> %va, i8 %b, <256 x i1> %m)
; CHECK-LABEL: vminu_vx_v258i8_evl129:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v24, (a1)
+; CHECK-NEXT: vlm.v v25, (a1)
; CHECK-NEXT: li a1, 128
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
; CHECK-NEXT: vminu.vx v16, v16, a0, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
index 3f5751aaa2cad..23a5f247ed204 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
@@ -288,11 +288,11 @@ define <32 x i8> @vpgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %
; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 16
+; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v8
-; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
@@ -1998,13 +1998,13 @@ define <32 x double> @vpgather_v32f64(<32 x ptr> %ptrs, <32 x i1> %m, i32 zeroex
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v24, (zero), v8, v0.t
; RV32-NEXT: addi a1, a0, -16
-; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v0, v0, 2
+; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; RV32-NEXT: vslidedown.vi v8, v8, 16
; RV32-NEXT: sltu a0, a0, a1
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a1
-; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; RV32-NEXT: vslidedown.vi v8, v8, 16
+; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (zero), v8, v0.t
; RV32-NEXT: vmv8r.v v8, v24
@@ -2023,9 +2023,9 @@ define <32 x double> @vpgather_v32f64(<32 x ptr> %ptrs, <32 x i1> %m, i32 zeroex
; RV64-NEXT: addi a1, a0, -16
; RV64-NEXT: sltu a0, a0, a1
; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
-; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (zero), v16, v0.t
; RV64-NEXT: ret
@@ -2049,13 +2049,13 @@ define <32 x double> @vpgather_baseidx_v32i8_v32f64(ptr %base, <32 x i8> %idxs,
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: addi a2, a1, -16
-; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v0, v0, 2
+; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2
-; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; RV32-NEXT: vslidedown.vi v24, v16, 16
+; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret
@@ -2080,9 +2080,9 @@ define <32 x double> @vpgather_baseidx_v32i8_v32f64(ptr %base, <32 x i8> %idxs,
; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a1, a1, -1
+; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
-; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: ret
@@ -2107,13 +2107,13 @@ define <32 x double> @vpgather_baseidx_sext_v32i8_v32f64(ptr %base, <32 x i8> %i
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: addi a2, a1, -16
-; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v0, v0, 2
+; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2
-; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; RV32-NEXT: vslidedown.vi v24, v16, 16
+; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret
@@ -2139,9 +2139,9 @@ define <32 x double> @vpgather_baseidx_sext_v32i8_v32f64(ptr %base, <32 x i8> %i
; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a1, a1, -1
+; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
-; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: ret
@@ -2171,9 +2171,9 @@ define <32 x double> @vpgather_baseidx_zext_v32i8_v32f64(ptr %base, <32 x i8> %i
; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1
+; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2
-; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei16.v v16, (a0), v24, v0.t
; RV32-NEXT: ret
@@ -2197,9 +2197,9 @@ define <32 x double> @vpgather_baseidx_zext_v32i8_v32f64(ptr %base, <32 x i8> %i
; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a1, a1, -1
+; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
-; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vluxei16.v v16, (a0), v24, v0.t
; RV64-NEXT: ret
@@ -2229,9 +2229,9 @@ define <32 x double> @vpgather_baseidx_v32i16_v32f64(ptr %base, <32 x i16> %idxs
; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1
+; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2
-; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret
@@ -2256,9 +2256,9 @@ define <32 x double> @vpgather_baseidx_v32i16_v32f64(ptr %base, <32 x i16> %idxs
; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a1, a1, -1
+; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
-; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: ret
@@ -2287,9 +2287,9 @@ define <32 x double> @vpgather_baseidx_sext_v32i16_v32f64(ptr %base, <32 x i16>
; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1
+; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2
-; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret
@@ -2315,9 +2315,9 @@ define <32 x double> @vpgather_baseidx_sext_v32i16_v32f64(ptr %base, <32 x i16>
; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a1, a1, -1
+; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
-; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: ret
@@ -2347,9 +2347,9 @@ define <32 x double> @vpgather_baseidx_zext_v32i16_v32f64(ptr %base, <32 x i16>
; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1
+; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2
-; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret
@@ -2373,9 +2373,9 @@ define <32 x double> @vpgather_baseidx_zext_v32i16_v32f64(ptr %base, <32 x i16>
; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a1, a1, -1
+; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
-; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV64-NEXT: ret
@@ -2400,13 +2400,13 @@ define <32 x double> @vpgather_baseidx_v32i32_v32f64(ptr %base, <32 x i32> %idxs
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: addi a2, a1, -16
-; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v0, v0, 2
+; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2
-; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; RV32-NEXT: vslidedown.vi v24, v16, 16
+; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret
@@ -2430,9 +2430,9 @@ define <32 x double> @vpgather_baseidx_v32i32_v32f64(ptr %base, <32 x i32> %idxs
; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a1, a1, -1
+; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
-; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: ret
@@ -2456,13 +2456,13 @@ define <32 x double> @vpgather_baseidx_sext_v32i32_v32f64(ptr %base, <32 x i32>
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: addi a2, a1, -16
-; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v0, v0, 2
+; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2
-; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; RV32-NEXT: vslidedown.vi v24, v16, 16
+; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret
@@ -2486,9 +2486,9 @@ define <32 x double> @vpgather_baseidx_sext_v32i32_v32f64(ptr %base, <32 x i32>
; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a1, a1, -1
+; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
-; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: ret
@@ -2513,13 +2513,13 @@ define <32 x double> @vpgather_baseidx_zext_v32i32_v32f64(ptr %base, <32 x i32>
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: addi a2, a1, -16
-; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v0, v0, 2
+; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2
-; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; RV32-NEXT: vslidedown.vi v24, v16, 16
+; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret
@@ -2543,9 +2543,9 @@ define <32 x double> @vpgather_baseidx_zext_v32i32_v32f64(ptr %base, <32 x i32>
; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a1, a1, -1
+; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
-; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: ret
@@ -2578,9 +2578,9 @@ define <32 x double> @vpgather_baseidx_v32f64(ptr %base, <32 x i64> %idxs, <32 x
; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1
+; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2
-; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret
@@ -2601,9 +2601,9 @@ define <32 x double> @vpgather_baseidx_v32f64(ptr %base, <32 x i64> %idxs, <32 x
; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a1, a1, -1
+; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
-; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
index d058669c103f3..d8cac111c37ba 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
@@ -326,12 +326,12 @@ define <32 x double> @vpload_v32f64(ptr %ptr, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0), v0.t
; CHECK-NEXT: addi a2, a1, -16
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v0, 2
+; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: sltu a1, a1, a2
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a1, a1, a2
-; CHECK-NEXT: addi a0, a0, 128
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a0), v0.t
; CHECK-NEXT: ret
@@ -345,7 +345,7 @@ define <33 x double> @vpload_v33f64(ptr %ptr, <33 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpload_v33f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: li a4, 32
; CHECK-NEXT: mv a3, a2
; CHECK-NEXT: bltu a2, a4, .LBB32_2
@@ -363,32 +363,32 @@ define <33 x double> @vpload_v33f64(ptr %ptr, <33 x i1> %m, i32 zeroext %evl) {
; CHECK-NEXT: and a5, a3, a7
; CHECK-NEXT: li a3, 16
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v8, 2
+; CHECK-NEXT: vslidedown.vi v0, v24, 2
; CHECK-NEXT: bltu a5, a3, .LBB32_4
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: li a5, 16
; CHECK-NEXT: .LBB32_4:
; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma
-; CHECK-NEXT: vle64.v v16, (a4), v0.t
-; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v8, 4
+; CHECK-NEXT: vle64.v v8, (a4), v0.t
; CHECK-NEXT: addi a4, a1, 256
+; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v24, 4
; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma
-; CHECK-NEXT: vle64.v v24, (a4), v0.t
+; CHECK-NEXT: vle64.v v16, (a4), v0.t
; CHECK-NEXT: bltu a2, a3, .LBB32_6
; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: li a2, 16
; CHECK-NEXT: .LBB32_6:
-; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vle64.v v8, (a1), v0.t
+; CHECK-NEXT: vle64.v v24, (a1), v0.t
; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: addi a2, a0, 256
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; CHECK-NEXT: vse64.v v8, (a0)
-; CHECK-NEXT: vse64.v v16, (a1)
+; CHECK-NEXT: vse64.v v24, (a0)
+; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-NEXT: vse64.v v24, (a2)
+; CHECK-NEXT: vse64.v v16, (a2)
; CHECK-NEXT: ret
%load = call <33 x double> @llvm.vp.load.v33f64.p0(ptr %ptr, <33 x i1> %m, i32 %evl)
ret <33 x double> %load
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
index 0bacb5c26cb4a..b1593f6a30646 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
@@ -168,17 +168,17 @@ define <32 x i1> @vpmerge_vv_v32i1(<32 x i1> %va, <32 x i1> %vb, <32 x i1> %m, i
; RV64-LABEL: vpmerge_vv_v32i1:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; RV64-NEXT: vmv.v.i v10, 0
+; RV64-NEXT: vmv.v.i v12, 0
; RV64-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; RV64-NEXT: vmerge.vim v12, v10, 1, v0
+; RV64-NEXT: vmerge.vim v10, v12, 1, v0
; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; RV64-NEXT: vmerge.vim v10, v10, 1, v0
+; RV64-NEXT: vmerge.vim v12, v12, 1, v0
; RV64-NEXT: vmv1r.v v0, v9
; RV64-NEXT: vsetvli zero, a0, e8, m2, tu, ma
-; RV64-NEXT: vmerge.vvm v10, v10, v12, v0
+; RV64-NEXT: vmerge.vvm v12, v12, v10, v0
; RV64-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; RV64-NEXT: vmsne.vi v0, v10, 0
+; RV64-NEXT: vmsne.vi v0, v12, 0
; RV64-NEXT: ret
;
; RV32ZVFHMIN-LABEL: vpmerge_vv_v32i1:
@@ -196,17 +196,17 @@ define <32 x i1> @vpmerge_vv_v32i1(<32 x i1> %va, <32 x i1> %vb, <32 x i1> %m, i
; RV64ZVFHMIN-LABEL: vpmerge_vv_v32i1:
; RV64ZVFHMIN: # %bb.0:
; RV64ZVFHMIN-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; RV64ZVFHMIN-NEXT: vmv.v.i v10, 0
+; RV64ZVFHMIN-NEXT: vmv.v.i v12, 0
; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; RV64ZVFHMIN-NEXT: vmerge.vim v12, v10, 1, v0
+; RV64ZVFHMIN-NEXT: vmerge.vim v10, v12, 1, v0
; RV64ZVFHMIN-NEXT: vmv1r.v v0, v8
; RV64ZVFHMIN-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; RV64ZVFHMIN-NEXT: vmerge.vim v10, v10, 1, v0
+; RV64ZVFHMIN-NEXT: vmerge.vim v12, v12, 1, v0
; RV64ZVFHMIN-NEXT: vmv1r.v v0, v9
; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e8, m2, tu, ma
-; RV64ZVFHMIN-NEXT: vmerge.vvm v10, v10, v12, v0
+; RV64ZVFHMIN-NEXT: vmerge.vvm v12, v12, v10, v0
; RV64ZVFHMIN-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; RV64ZVFHMIN-NEXT: vmsne.vi v0, v10, 0
+; RV64ZVFHMIN-NEXT: vmsne.vi v0, v12, 0
; RV64ZVFHMIN-NEXT: ret
%v = call <32 x i1> @llvm.vp.merge.v32i1(<32 x i1> %m, <32 x i1> %va, <32 x i1> %vb, i32 %evl)
ret <32 x i1> %v
@@ -216,17 +216,17 @@ define <64 x i1> @vpmerge_vv_v64i1(<64 x i1> %va, <64 x i1> %vb, <64 x i1> %m, i
; CHECK-LABEL: vpmerge_vv_v64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v12, 1, v0
+; CHECK-NEXT: vmerge.vim v12, v16, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
+; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma
-; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0
+; CHECK-NEXT: vmerge.vvm v16, v16, v12, v0
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; CHECK-NEXT: vmsne.vi v0, v12, 0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: ret
%v = call <64 x i1> @llvm.vp.merge.v64i1(<64 x i1> %m, <64 x i1> %va, <64 x i1> %vb, i32 %evl)
ret <64 x i1> %v
@@ -1309,9 +1309,9 @@ define <32 x double> @vpmerge_vv_v32f64(<32 x double> %va, <32 x double> %vb, <3
; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2
-; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma
@@ -1342,9 +1342,9 @@ define <32 x double> @vpmerge_vf_v32f64(double %a, <32 x double> %vb, <32 x i1>
; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2
-; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma
; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
index b4d20d93f2a1c..df6c3b2ffc7e5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
@@ -1704,13 +1704,13 @@ define void @vpscatter_v32f64(<32 x double> %val, <32 x ptr> %ptrs, <32 x i1> %m
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v8, (zero), v24, v0.t
; RV32-NEXT: addi a0, a1, -16
-; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v0, v0, 2
+; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: sltu a1, a1, a0
; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a0, a1, a0
-; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; RV32-NEXT: vslidedown.vi v8, v24, 16
+; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v16, (zero), v8, v0.t
; RV32-NEXT: ret
@@ -1740,9 +1740,9 @@ define void @vpscatter_v32f64(<32 x double> %val, <32 x ptr> %ptrs, <32 x i1> %m
; RV64-NEXT: addi a0, a2, -16
; RV64-NEXT: sltu a1, a2, a0
; RV64-NEXT: addi a1, a1, -1
+; RV64-NEXT: and a0, a1, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
-; RV64-NEXT: and a0, a1, a0
; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -1774,13 +1774,13 @@ define void @vpscatter_baseidx_v32i32_v32f64(<32 x double> %val, ptr %base, <32
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: addi a1, a2, -16
-; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v0, v0, 2
+; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: sltu a2, a2, a1
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a1, a2, a1
-; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; RV32-NEXT: vslidedown.vi v8, v24, 16
+; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: ret
@@ -1790,50 +1790,63 @@ define void @vpscatter_baseidx_v32i32_v32f64(<32 x double> %val, ptr %base, <32
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a3, vlenb
-; RV64-NEXT: slli a3, a3, 4
+; RV64-NEXT: slli a4, a3, 4
+; RV64-NEXT: add a3, a4, a3
; RV64-NEXT: sub sp, sp, a3
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
+; RV64-NEXT: csrr a3, vlenb
+; RV64-NEXT: slli a3, a3, 4
+; RV64-NEXT: add a3, sp, a3
+; RV64-NEXT: addi a3, a3, 16
+; RV64-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
; RV64-NEXT: csrr a3, vlenb
; RV64-NEXT: slli a3, a3, 3
; RV64-NEXT: add a3, sp, a3
; RV64-NEXT: addi a3, a3, 16
; RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; RV64-NEXT: li a3, 32
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vle32.v v24, (a1)
; RV64-NEXT: li a1, 8
; RV64-NEXT: li a3, 16
; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; RV64-NEXT: vslidedown.vi v16, v24, 16
+; RV64-NEXT: vslidedown.vi v0, v24, 16
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV64-NEXT: vwmulsu.vx v8, v16, a1
+; RV64-NEXT: vwmulsu.vx v16, v0, a1
+; RV64-NEXT: addi a4, sp, 16
+; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64-NEXT: vwmulsu.vx v16, v24, a1
; RV64-NEXT: mv a1, a2
; RV64-NEXT: bltu a2, a3, .LBB84_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB84_2:
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; RV64-NEXT: csrr a3, vlenb
+; RV64-NEXT: slli a3, a3, 4
+; RV64-NEXT: add a3, sp, a3
+; RV64-NEXT: addi a3, a3, 16
+; RV64-NEXT: vl1r.v v24, (a3) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vmv1r.v v0, v24
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsoxei64.v v24, (a0), v16, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: addi a1, a2, -16
; RV64-NEXT: sltu a2, a2, a1
; RV64-NEXT: addi a2, a2, -1
-; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: and a1, a2, a1
+; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vi v0, v24, 2
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
+; RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV64-NEXT: addi a2, sp, 16
; RV64-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsoxei64.v v16, (a0), v8, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: slli a1, a0, 4
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 16
; RV64-NEXT: addi sp, sp, 16
@@ -1860,13 +1873,13 @@ define void @vpscatter_baseidx_sext_v32i32_v32f64(<32 x double> %val, ptr %base,
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: addi a1, a2, -16
-; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v0, v0, 2
+; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: sltu a2, a2, a1
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a1, a2, a1
-; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; RV32-NEXT: vslidedown.vi v8, v24, 16
+; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: ret
@@ -1876,50 +1889,63 @@ define void @vpscatter_baseidx_sext_v32i32_v32f64(<32 x double> %val, ptr %base,
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a3, vlenb
-; RV64-NEXT: slli a3, a3, 4
+; RV64-NEXT: slli a4, a3, 4
+; RV64-NEXT: add a3, a4, a3
; RV64-NEXT: sub sp, sp, a3
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
+; RV64-NEXT: csrr a3, vlenb
+; RV64-NEXT: slli a3, a3, 4
+; RV64-NEXT: add a3, sp, a3
+; RV64-NEXT: addi a3, a3, 16
+; RV64-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
; RV64-NEXT: csrr a3, vlenb
; RV64-NEXT: slli a3, a3, 3
; RV64-NEXT: add a3, sp, a3
; RV64-NEXT: addi a3, a3, 16
; RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; RV64-NEXT: li a3, 32
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vle32.v v24, (a1)
; RV64-NEXT: li a1, 8
; RV64-NEXT: li a3, 16
; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; RV64-NEXT: vslidedown.vi v16, v24, 16
+; RV64-NEXT: vslidedown.vi v0, v24, 16
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV64-NEXT: vwmulsu.vx v8, v16, a1
+; RV64-NEXT: vwmulsu.vx v16, v0, a1
+; RV64-NEXT: addi a4, sp, 16
+; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64-NEXT: vwmulsu.vx v16, v24, a1
; RV64-NEXT: mv a1, a2
; RV64-NEXT: bltu a2, a3, .LBB85_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB85_2:
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; RV64-NEXT: csrr a3, vlenb
+; RV64-NEXT: slli a3, a3, 4
+; RV64-NEXT: add a3, sp, a3
+; RV64-NEXT: addi a3, a3, 16
+; RV64-NEXT: vl1r.v v24, (a3) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vmv1r.v v0, v24
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsoxei64.v v24, (a0), v16, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: addi a1, a2, -16
; RV64-NEXT: sltu a2, a2, a1
; RV64-NEXT: addi a2, a2, -1
-; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: and a1, a2, a1
+; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vi v0, v24, 2
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
+; RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV64-NEXT: addi a2, sp, 16
; RV64-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsoxei64.v v16, (a0), v8, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: slli a1, a0, 4
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 16
; RV64-NEXT: addi sp, sp, 16
@@ -1947,13 +1973,13 @@ define void @vpscatter_baseidx_zext_v32i32_v32f64(<32 x double> %val, ptr %base,
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: addi a1, a2, -16
-; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v0, v0, 2
+; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: sltu a2, a2, a1
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a1, a2, a1
-; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; RV32-NEXT: vslidedown.vi v8, v24, 16
+; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: ret
@@ -1963,50 +1989,63 @@ define void @vpscatter_baseidx_zext_v32i32_v32f64(<32 x double> %val, ptr %base,
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a3, vlenb
-; RV64-NEXT: slli a3, a3, 4
+; RV64-NEXT: slli a4, a3, 4
+; RV64-NEXT: add a3, a4, a3
; RV64-NEXT: sub sp, sp, a3
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
+; RV64-NEXT: csrr a3, vlenb
+; RV64-NEXT: slli a3, a3, 4
+; RV64-NEXT: add a3, sp, a3
+; RV64-NEXT: addi a3, a3, 16
+; RV64-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
; RV64-NEXT: csrr a3, vlenb
; RV64-NEXT: slli a3, a3, 3
; RV64-NEXT: add a3, sp, a3
; RV64-NEXT: addi a3, a3, 16
; RV64-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; RV64-NEXT: li a3, 32
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vle32.v v24, (a1)
; RV64-NEXT: li a1, 8
; RV64-NEXT: li a3, 16
; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; RV64-NEXT: vslidedown.vi v16, v24, 16
+; RV64-NEXT: vslidedown.vi v0, v24, 16
; RV64-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV64-NEXT: vwmulu.vx v8, v16, a1
+; RV64-NEXT: vwmulu.vx v16, v0, a1
+; RV64-NEXT: addi a4, sp, 16
+; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64-NEXT: vwmulu.vx v16, v24, a1
; RV64-NEXT: mv a1, a2
; RV64-NEXT: bltu a2, a3, .LBB86_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB86_2:
-; RV64-NEXT: addi a3, sp, 16
-; RV64-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; RV64-NEXT: csrr a3, vlenb
+; RV64-NEXT: slli a3, a3, 4
+; RV64-NEXT: add a3, sp, a3
+; RV64-NEXT: addi a3, a3, 16
+; RV64-NEXT: vl1r.v v24, (a3) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vmv1r.v v0, v24
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsoxei64.v v24, (a0), v16, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: addi a1, a2, -16
; RV64-NEXT: sltu a2, a2, a1
; RV64-NEXT: addi a2, a2, -1
-; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: and a1, a2, a1
+; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vi v0, v24, 2
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
+; RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV64-NEXT: addi a2, sp, 16
; RV64-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsoxei64.v v16, (a0), v8, v0.t
+; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: slli a1, a0, 4
+; RV64-NEXT: add a0, a1, a0
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 16
; RV64-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
index 855a87d21b7dc..209fd6664f9a9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
@@ -256,12 +256,12 @@ define void @vpstore_v32f64(<32 x double> %val, ptr %ptr, <32 x i1> %m, i32 zero
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vse64.v v8, (a0), v0.t
; CHECK-NEXT: addi a2, a1, -16
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v0, 2
+; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: sltu a1, a1, a2
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a1, a1, a2
-; CHECK-NEXT: addi a0, a0, 128
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vse64.v v16, (a0), v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
index 78eabfec4153e..c7c8443325afc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
@@ -9,8 +9,8 @@ define <8 x i7> @vrem_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsll.vi v9, v9, 1, v0.t
-; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
+; CHECK-NEXT: vsra.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
; CHECK-NEXT: vrem.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
index acaa1e6fa002d..a72ae512b2019 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
@@ -359,7 +359,7 @@ define <256 x i8> @vsadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %e
; CHECK-LABEL: vsadd_vi_v258i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
@@ -373,7 +373,7 @@ define <256 x i8> @vsadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %e
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 128
; CHECK-NEXT: .LBB32_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
@@ -409,11 +409,11 @@ define <256 x i8> @vsadd_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vsadd_vi_v258i8_evl129:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v24, (a0)
+; CHECK-NEXT: vlm.v v25, (a0)
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
index 9b3b8348d9b30..51bab9bcf2997 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
@@ -355,7 +355,7 @@ define <256 x i8> @vsaddu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %
; CHECK-LABEL: vsaddu_vi_v258i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
@@ -369,7 +369,7 @@ define <256 x i8> @vsaddu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 128
; CHECK-NEXT: .LBB32_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
@@ -405,11 +405,11 @@ define <256 x i8> @vsaddu_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vsaddu_vi_v258i8_evl129:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v24, (a0)
+; CHECK-NEXT: vlm.v v25, (a0)
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
index f2f9f90f386c0..2db96dca3123d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
@@ -140,8 +140,8 @@ define <256 x i8> @select_v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c, i3
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v6, v8
-; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vmv1r.v v7, v8
+; CHECK-NEXT: vmv1r.v v6, v0
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: addi a4, a1, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -152,16 +152,16 @@ define <256 x i8> @select_v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c, i3
; CHECK-NEXT: vle8.v v16, (a1)
; CHECK-NEXT: addi a4, a4, -1
; CHECK-NEXT: and a0, a4, a0
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vmerge.vvm v24, v8, v24, v0
; CHECK-NEXT: bltu a3, a2, .LBB11_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a3, 128
; CHECK-NEXT: .LBB11_2:
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: vmv8r.v v16, v24
@@ -345,9 +345,9 @@ define <32 x i64> @select_v32i64(<32 x i1> %a, <32 x i64> %b, <32 x i64> %c, i32
; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2
-; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -369,36 +369,26 @@ define <32 x i64> @select_evl_v32i64(<32 x i1> %a, <32 x i64> %b, <32 x i64> %c)
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, ma
-; CHECK-NEXT: vle64.v v24, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vle64.v v16, (a0)
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
+; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, ma
-; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
+; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -514,9 +504,9 @@ define <64 x float> @select_v64f32(<64 x i1> %a, <64 x float> %b, <64 x float> %
; CHECK-NEXT: addi a0, a2, -32
; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 4
-; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
index b97fa1d3a51ec..c946e8c0b1a0f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
@@ -19,11 +19,11 @@ define void @vselect_vv_v6i32(ptr %a, ptr %b, ptr %cc, ptr %z) {
; RV32-NEXT: srli a4, a4, 31
; RV32-NEXT: vslide1down.vx v10, v10, a4
; RV32-NEXT: slli a4, a2, 27
-; RV32-NEXT: srli a2, a2, 5
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: srli a4, a4, 31
; RV32-NEXT: vslide1down.vx v10, v10, a1
; RV32-NEXT: vslide1down.vx v10, v10, a4
+; RV32-NEXT: srli a2, a2, 5
; RV32-NEXT: vslide1down.vx v10, v10, a2
; RV32-NEXT: vsetivli zero, 6, e8, mf2, ta, ma
; RV32-NEXT: vslidedown.vi v10, v10, 2
@@ -50,11 +50,11 @@ define void @vselect_vv_v6i32(ptr %a, ptr %b, ptr %cc, ptr %z) {
; RV64-NEXT: srli a4, a4, 63
; RV64-NEXT: vslide1down.vx v10, v10, a4
; RV64-NEXT: slli a4, a2, 59
-; RV64-NEXT: srli a2, a2, 5
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: srli a4, a4, 63
; RV64-NEXT: vslide1down.vx v10, v10, a1
; RV64-NEXT: vslide1down.vx v10, v10, a4
+; RV64-NEXT: srli a2, a2, 5
; RV64-NEXT: vslide1down.vx v10, v10, a2
; RV64-NEXT: vsetivli zero, 6, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vi v10, v10, 2
@@ -89,11 +89,11 @@ define void @vselect_vx_v6i32(i32 %a, ptr %b, ptr %cc, ptr %z) {
; RV32-NEXT: srli a4, a4, 31
; RV32-NEXT: vslide1down.vx v10, v10, a4
; RV32-NEXT: slli a4, a2, 27
-; RV32-NEXT: srli a2, a2, 5
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: srli a4, a4, 31
; RV32-NEXT: vslide1down.vx v10, v10, a1
; RV32-NEXT: vslide1down.vx v10, v10, a4
+; RV32-NEXT: srli a2, a2, 5
; RV32-NEXT: vslide1down.vx v10, v10, a2
; RV32-NEXT: vsetivli zero, 6, e8, mf2, ta, ma
; RV32-NEXT: vslidedown.vi v10, v10, 2
@@ -120,11 +120,11 @@ define void @vselect_vx_v6i32(i32 %a, ptr %b, ptr %cc, ptr %z) {
; RV64-NEXT: srli a4, a4, 63
; RV64-NEXT: vslide1down.vx v10, v10, a4
; RV64-NEXT: slli a4, a2, 59
-; RV64-NEXT: srli a2, a2, 5
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: srli a4, a4, 63
; RV64-NEXT: vslide1down.vx v10, v10, a1
; RV64-NEXT: vslide1down.vx v10, v10, a4
+; RV64-NEXT: srli a2, a2, 5
; RV64-NEXT: vslide1down.vx v10, v10, a2
; RV64-NEXT: vsetivli zero, 6, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vi v10, v10, 2
@@ -160,11 +160,11 @@ define void @vselect_vi_v6i32(ptr %b, ptr %cc, ptr %z) {
; RV32-NEXT: srli a3, a3, 31
; RV32-NEXT: vslide1down.vx v10, v10, a3
; RV32-NEXT: slli a3, a1, 27
-; RV32-NEXT: srli a1, a1, 5
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: srli a3, a3, 31
; RV32-NEXT: vslide1down.vx v10, v10, a0
; RV32-NEXT: vslide1down.vx v10, v10, a3
+; RV32-NEXT: srli a1, a1, 5
; RV32-NEXT: vslide1down.vx v10, v10, a1
; RV32-NEXT: vsetivli zero, 6, e8, mf2, ta, ma
; RV32-NEXT: vslidedown.vi v10, v10, 2
@@ -191,11 +191,11 @@ define void @vselect_vi_v6i32(ptr %b, ptr %cc, ptr %z) {
; RV64-NEXT: srli a3, a3, 63
; RV64-NEXT: vslide1down.vx v10, v10, a3
; RV64-NEXT: slli a3, a1, 59
-; RV64-NEXT: srli a1, a1, 5
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: srli a3, a3, 63
; RV64-NEXT: vslide1down.vx v10, v10, a0
; RV64-NEXT: vslide1down.vx v10, v10, a3
+; RV64-NEXT: srli a1, a1, 5
; RV64-NEXT: vslide1down.vx v10, v10, a1
; RV64-NEXT: vsetivli zero, 6, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vi v10, v10, 2
@@ -230,11 +230,11 @@ define void @vselect_vv_v6f32(ptr %a, ptr %b, ptr %cc, ptr %z) {
; RV32-NEXT: srli a4, a4, 31
; RV32-NEXT: vslide1down.vx v10, v10, a4
; RV32-NEXT: slli a4, a2, 27
-; RV32-NEXT: srli a2, a2, 5
; RV32-NEXT: srli a1, a1, 31
; RV32-NEXT: srli a4, a4, 31
; RV32-NEXT: vslide1down.vx v10, v10, a1
; RV32-NEXT: vslide1down.vx v10, v10, a4
+; RV32-NEXT: srli a2, a2, 5
; RV32-NEXT: vslide1down.vx v10, v10, a2
; RV32-NEXT: vsetivli zero, 6, e8, mf2, ta, ma
; RV32-NEXT: vslidedown.vi v10, v10, 2
@@ -261,11 +261,11 @@ define void @vselect_vv_v6f32(ptr %a, ptr %b, ptr %cc, ptr %z) {
; RV64-NEXT: srli a4, a4, 63
; RV64-NEXT: vslide1down.vx v10, v10, a4
; RV64-NEXT: slli a4, a2, 59
-; RV64-NEXT: srli a2, a2, 5
; RV64-NEXT: srli a1, a1, 63
; RV64-NEXT: srli a4, a4, 63
; RV64-NEXT: vslide1down.vx v10, v10, a1
; RV64-NEXT: vslide1down.vx v10, v10, a4
+; RV64-NEXT: srli a2, a2, 5
; RV64-NEXT: vslide1down.vx v10, v10, a2
; RV64-NEXT: vsetivli zero, 6, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vi v10, v10, 2
@@ -300,11 +300,11 @@ define void @vselect_vx_v6f32(float %a, ptr %b, ptr %cc, ptr %z) {
; RV32-NEXT: srli a3, a3, 31
; RV32-NEXT: vslide1down.vx v10, v10, a3
; RV32-NEXT: slli a3, a1, 27
-; RV32-NEXT: srli a1, a1, 5
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: srli a3, a3, 31
; RV32-NEXT: vslide1down.vx v10, v10, a0
; RV32-NEXT: vslide1down.vx v10, v10, a3
+; RV32-NEXT: srli a1, a1, 5
; RV32-NEXT: vslide1down.vx v10, v10, a1
; RV32-NEXT: vsetivli zero, 6, e8, mf2, ta, ma
; RV32-NEXT: vslidedown.vi v10, v10, 2
@@ -331,11 +331,11 @@ define void @vselect_vx_v6f32(float %a, ptr %b, ptr %cc, ptr %z) {
; RV64-NEXT: srli a3, a3, 63
; RV64-NEXT: vslide1down.vx v10, v10, a3
; RV64-NEXT: slli a3, a1, 59
-; RV64-NEXT: srli a1, a1, 5
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: srli a3, a3, 63
; RV64-NEXT: vslide1down.vx v10, v10, a0
; RV64-NEXT: vslide1down.vx v10, v10, a3
+; RV64-NEXT: srli a1, a1, 5
; RV64-NEXT: vslide1down.vx v10, v10, a1
; RV64-NEXT: vsetivli zero, 6, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vi v10, v10, 2
@@ -371,11 +371,11 @@ define void @vselect_vfpzero_v6f32(ptr %b, ptr %cc, ptr %z) {
; RV32-NEXT: srli a3, a3, 31
; RV32-NEXT: vslide1down.vx v10, v10, a3
; RV32-NEXT: slli a3, a1, 27
-; RV32-NEXT: srli a1, a1, 5
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: srli a3, a3, 31
; RV32-NEXT: vslide1down.vx v10, v10, a0
; RV32-NEXT: vslide1down.vx v10, v10, a3
+; RV32-NEXT: srli a1, a1, 5
; RV32-NEXT: vslide1down.vx v10, v10, a1
; RV32-NEXT: vsetivli zero, 6, e8, mf2, ta, ma
; RV32-NEXT: vslidedown.vi v10, v10, 2
@@ -402,11 +402,11 @@ define void @vselect_vfpzero_v6f32(ptr %b, ptr %cc, ptr %z) {
; RV64-NEXT: srli a3, a3, 63
; RV64-NEXT: vslide1down.vx v10, v10, a3
; RV64-NEXT: slli a3, a1, 59
-; RV64-NEXT: srli a1, a1, 5
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: srli a3, a3, 63
; RV64-NEXT: vslide1down.vx v10, v10, a0
; RV64-NEXT: vslide1down.vx v10, v10, a3
+; RV64-NEXT: srli a1, a1, 5
; RV64-NEXT: vslide1down.vx v10, v10, a1
; RV64-NEXT: vsetivli zero, 6, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vi v10, v10, 2
@@ -427,8 +427,8 @@ define void @vselect_vv_v8i32(ptr %a, ptr %b, ptr %cc, ptr %z) {
; CHECK-LABEL: vselect_vv_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vle32.v v8, (a0), v0.t
; CHECK-NEXT: vse32.v v8, (a3)
; CHECK-NEXT: ret
@@ -444,8 +444,8 @@ define void @vselect_vx_v8i32(i32 %a, ptr %b, ptr %cc, ptr %z) {
; CHECK-LABEL: vselect_vx_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: vse32.v v8, (a3)
; CHECK-NEXT: ret
@@ -462,8 +462,8 @@ define void @vselect_vi_v8i32(ptr %b, ptr %cc, ptr %z) {
; CHECK-LABEL: vselect_vi_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
@@ -478,8 +478,8 @@ define void @vselect_vv_v8f32(ptr %a, ptr %b, ptr %cc, ptr %z) {
; CHECK-LABEL: vselect_vv_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vle32.v v8, (a0), v0.t
; CHECK-NEXT: vse32.v v8, (a3)
; CHECK-NEXT: ret
@@ -495,8 +495,8 @@ define void @vselect_vx_v8f32(float %a, ptr %b, ptr %cc, ptr %z) {
; CHECK-LABEL: vselect_vx_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
@@ -513,8 +513,8 @@ define void @vselect_vfpzero_v8f32(ptr %b, ptr %cc, ptr %z) {
; CHECK-LABEL: vselect_vfpzero_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
; CHECK-NEXT: vse32.v v8, (a2)
; CHECK-NEXT: ret
@@ -529,8 +529,8 @@ define void @vselect_vv_v16i16(ptr %a, ptr %b, ptr %cc, ptr %z) {
; CHECK-LABEL: vselect_vv_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vle16.v v8, (a1)
+; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vle16.v v8, (a0), v0.t
; CHECK-NEXT: vse16.v v8, (a3)
; CHECK-NEXT: ret
@@ -546,8 +546,8 @@ define void @vselect_vx_v16i16(i16 signext %a, ptr %b, ptr %cc, ptr %z) {
; CHECK-LABEL: vselect_vx_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vle16.v v8, (a1)
+; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: vse16.v v8, (a3)
; CHECK-NEXT: ret
@@ -564,8 +564,8 @@ define void @vselect_vi_v16i16(ptr %b, ptr %cc, ptr %z) {
; CHECK-LABEL: vselect_vi_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: vmerge.vim v8, v8, 4, v0
; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
@@ -581,8 +581,8 @@ define void @vselect_vv_v32f16(ptr %a, ptr %b, ptr %cc, ptr %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: li a4, 32
; CHECK-NEXT: vsetvli zero, a4, e16, m4, ta, mu
-; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vle16.v v8, (a1)
+; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vle16.v v8, (a0), v0.t
; CHECK-NEXT: vse16.v v8, (a3)
; CHECK-NEXT: ret
@@ -599,8 +599,8 @@ define void @vselect_vx_v32f16(half %a, ptr %b, ptr %cc, ptr %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
@@ -618,8 +618,8 @@ define void @vselect_vfpzero_v32f16(ptr %b, ptr %cc, ptr %z) {
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: vle16.v v8, (a0)
+; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
; CHECK-NEXT: vse16.v v8, (a2)
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
index 1d0c3a6937b54..b6e99c7af8685 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
@@ -9,8 +9,8 @@ define <8 x i7> @vsra_vv_v8i7(<8 x i7> %va, <8 x i7> %b, <8 x i1> %m, i32 zeroex
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 127
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vand.vx v9, v9, a1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
+; CHECK-NEXT: vand.vx v9, v9, a1, v0.t
; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
index 4c7d312e8e785..f5aba6885efcc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
@@ -371,7 +371,7 @@ define <256 x i8> @vssub_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %e
; CHECK-LABEL: vssub_vi_v258i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: addi a3, a1, -128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -386,7 +386,7 @@ define <256 x i8> @vssub_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %e
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 128
; CHECK-NEXT: .LBB32_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
@@ -423,12 +423,12 @@ define <256 x i8> @vssub_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vssub_vi_v258i8_evl129:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v24, (a0)
+; CHECK-NEXT: vlm.v v25, (a0)
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: li a1, -1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
; CHECK-NEXT: vssub.vx v16, v16, a1, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
index f9000a1b88a6d..1d74d1f5a6ead 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
@@ -366,7 +366,7 @@ define <256 x i8> @vssubu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %
; CHECK-LABEL: vssubu_vi_v258i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: addi a3, a1, -128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -381,7 +381,7 @@ define <256 x i8> @vssubu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 128
; CHECK-NEXT: .LBB32_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
@@ -418,12 +418,12 @@ define <256 x i8> @vssubu_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
; CHECK-LABEL: vssubu_vi_v258i8_evl129:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v24, (a0)
+; CHECK-NEXT: vlm.v v25, (a0)
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: li a1, -1
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, ma
; CHECK-NEXT: vssubu.vx v16, v16, a1, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd-mask.ll
index 7bac239cfffea..47afc8b073563 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd-mask.ll
@@ -5,13 +5,12 @@
define <8 x i64> @vwadd_wv_mask_v8i32(<8 x i32> %x, <8 x i64> %y) {
; CHECK-LABEL: vwadd_wv_mask_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vmv2r.v v16, v8
; CHECK-NEXT: li a0, 42
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vmslt.vx v0, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, mu
-; CHECK-NEXT: vwadd.wv v8, v8, v16, v0.t
+; CHECK-NEXT: vwadd.wv v12, v12, v8, v0.t
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%mask = icmp slt <8 x i32> %x, <i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42>
%a = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> zeroinitializer
@@ -23,13 +22,12 @@ define <8 x i64> @vwadd_wv_mask_v8i32(<8 x i32> %x, <8 x i64> %y) {
define <8 x i64> @vwaddu_wv_mask_v8i32(<8 x i32> %x, <8 x i64> %y) {
; CHECK-LABEL: vwaddu_wv_mask_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vmv2r.v v16, v8
; CHECK-NEXT: li a0, 42
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vmslt.vx v0, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, mu
-; CHECK-NEXT: vwaddu.wv v8, v8, v16, v0.t
+; CHECK-NEXT: vwaddu.wv v12, v12, v8, v0.t
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%mask = icmp slt <8 x i32> %x, <i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42>
%a = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> zeroinitializer
@@ -60,13 +58,12 @@ define <8 x i64> @vwaddu_vv_mask_v8i32(<8 x i32> %x, <8 x i32> %y) {
define <8 x i64> @vwadd_wv_mask_v8i32_commutative(<8 x i32> %x, <8 x i64> %y) {
; CHECK-LABEL: vwadd_wv_mask_v8i32_commutative:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vmv2r.v v16, v8
; CHECK-NEXT: li a0, 42
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vmslt.vx v0, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, mu
-; CHECK-NEXT: vwadd.wv v8, v8, v16, v0.t
+; CHECK-NEXT: vwadd.wv v12, v12, v8, v0.t
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%mask = icmp slt <8 x i32> %x, <i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42>
%a = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub-mask.ll
index eafea7292a54b..446a24b973e27 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub-mask.ll
@@ -5,13 +5,12 @@
define <8 x i64> @vwsub_wv_mask_v8i32(<8 x i32> %x, <8 x i64> %y) {
; CHECK-LABEL: vwsub_wv_mask_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vmv2r.v v16, v8
; CHECK-NEXT: li a0, 42
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vmslt.vx v0, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, mu
-; CHECK-NEXT: vwsub.wv v8, v8, v16, v0.t
+; CHECK-NEXT: vwsub.wv v12, v12, v8, v0.t
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%mask = icmp slt <8 x i32> %x, <i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42>
%a = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> zeroinitializer
@@ -23,13 +22,12 @@ define <8 x i64> @vwsub_wv_mask_v8i32(<8 x i32> %x, <8 x i64> %y) {
define <8 x i64> @vwsubu_wv_mask_v8i32(<8 x i32> %x, <8 x i64> %y) {
; CHECK-LABEL: vwsubu_wv_mask_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT: vmv2r.v v16, v8
; CHECK-NEXT: li a0, 42
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vmslt.vx v0, v8, a0
-; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m2, tu, mu
-; CHECK-NEXT: vwsubu.wv v8, v8, v16, v0.t
+; CHECK-NEXT: vwsubu.wv v12, v12, v8, v0.t
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%mask = icmp slt <8 x i32> %x, <i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42, i32 42>
%a = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
index e2d9e0ac2deea..714c027fbfa0b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
@@ -139,25 +139,24 @@ define <32 x i64> @vzext_v32i64_v32i32(<32 x i32> %va, <32 x i1> %m, i32 zeroext
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: vslidedown.vi v16, v0, 2
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB12_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB12_2:
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vzext.vf2 v16, v8, v0.t
+; CHECK-NEXT: vzext.vf2 v24, v8, v0.t
; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 16
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vzext.vf2 v24, v8, v0.t
-; CHECK-NEXT: vmv8r.v v8, v16
-; CHECK-NEXT: vmv.v.v v16, v24
+; CHECK-NEXT: vzext.vf2 v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.zext.v32i64.v32i32(<32 x i32> %va, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll b/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
index 17c2244001082..4191a0f4d5d55 100644
--- a/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
@@ -399,8 +399,8 @@ define <vscale x 1 x i8> @ceil_nxv1f32_to_si8(<vscale x 1 x float> %x) {
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: lui a0, 307200
; RV32-NEXT: fmv.w.x fa5, a0
-; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: fsrmi a0, 3
+; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -418,8 +418,8 @@ define <vscale x 1 x i8> @ceil_nxv1f32_to_si8(<vscale x 1 x float> %x) {
; RV64-NEXT: vfabs.v v9, v8
; RV64-NEXT: lui a0, 307200
; RV64-NEXT: fmv.w.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -442,8 +442,8 @@ define <vscale x 1 x i8> @ceil_nxv1f32_to_ui8(<vscale x 1 x float> %x) {
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: lui a0, 307200
; RV32-NEXT: fmv.w.x fa5, a0
-; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: fsrmi a0, 3
+; RV32-NEXT: vmflt.vf v0, v9, fa5
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -461,8 +461,8 @@ define <vscale x 1 x i8> @ceil_nxv1f32_to_ui8(<vscale x 1 x float> %x) {
; RV64-NEXT: vfabs.v v9, v8
; RV64-NEXT: lui a0, 307200
; RV64-NEXT: fmv.w.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -623,8 +623,8 @@ define <vscale x 4 x i8> @ceil_nxv4f32_to_si8(<vscale x 4 x float> %x) {
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: lui a0, 307200
; RV32-NEXT: fmv.w.x fa5, a0
-; RV32-NEXT: vmflt.vf v0, v10, fa5
; RV32-NEXT: fsrmi a0, 3
+; RV32-NEXT: vmflt.vf v0, v10, fa5
; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -642,8 +642,8 @@ define <vscale x 4 x i8> @ceil_nxv4f32_to_si8(<vscale x 4 x float> %x) {
; RV64-NEXT: vfabs.v v10, v8
; RV64-NEXT: lui a0, 307200
; RV64-NEXT: fmv.w.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -666,8 +666,8 @@ define <vscale x 4 x i8> @ceil_nxv4f32_to_ui8(<vscale x 4 x float> %x) {
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: lui a0, 307200
; RV32-NEXT: fmv.w.x fa5, a0
-; RV32-NEXT: vmflt.vf v0, v10, fa5
; RV32-NEXT: fsrmi a0, 3
+; RV32-NEXT: vmflt.vf v0, v10, fa5
; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32-NEXT: fsrm a0
; RV32-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -685,8 +685,8 @@ define <vscale x 4 x i8> @ceil_nxv4f32_to_ui8(<vscale x 4 x float> %x) {
; RV64-NEXT: vfabs.v v10, v8
; RV64-NEXT: lui a0, 307200
; RV64-NEXT: fmv.w.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: fsrmi a0, 3
+; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64-NEXT: fsrm a0
; RV64-NEXT: vfcvt.f.x.v v10, v10, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
index a107cb82964eb..fe41552c4c984 100644
--- a/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
@@ -16,26 +16,24 @@ define <vscale x 1 x bfloat> @vp_floor_nxv1bf16(<vscale x 1 x bfloat> %va, <vsca
; CHECK-LABEL: vp_floor_nxv1bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfabs.v v11, v10, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 2
-; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
-; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 1 x bfloat> @llvm.vp.floor.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x bfloat> %v
@@ -47,11 +45,11 @@ define <vscale x 1 x bfloat> @vp_floor_nxv1bf16_unmasked(<vscale x 1 x bfloat> %
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -68,26 +66,24 @@ define <vscale x 2 x bfloat> @vp_floor_nxv2bf16(<vscale x 2 x bfloat> %va, <vsca
; CHECK-LABEL: vp_floor_nxv2bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfabs.v v11, v10, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 2
-; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
-; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 2 x bfloat> @llvm.vp.floor.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x bfloat> %v
@@ -99,11 +95,11 @@ define <vscale x 2 x bfloat> @vp_floor_nxv2bf16_unmasked(<vscale x 2 x bfloat> %
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -123,21 +119,21 @@ define <vscale x 4 x bfloat> @vp_floor_nxv4bf16(<vscale x 4 x bfloat> %va, <vsca
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v8, v10, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v13, v8, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fsrmi a0, 2
-; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
; CHECK-NEXT: ret
@@ -151,11 +147,11 @@ define <vscale x 4 x bfloat> @vp_floor_nxv4bf16_unmasked(<vscale x 4 x bfloat> %
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v8, v10
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -175,21 +171,21 @@ define <vscale x 8 x bfloat> @vp_floor_nxv8bf16(<vscale x 8 x bfloat> %va, <vsca
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v17, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfabs.v v8, v12, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v17, v8, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v17, v0
; CHECK-NEXT: fsrmi a0, 2
-; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
; CHECK-NEXT: ret
@@ -203,11 +199,11 @@ define <vscale x 8 x bfloat> @vp_floor_nxv8bf16_unmasked(<vscale x 8 x bfloat> %
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfabs.v v8, v12
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -227,21 +223,21 @@ define <vscale x 16 x bfloat> @vp_floor_nxv16bf16(<vscale x 16 x bfloat> %va, <v
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v8, v16, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v24, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fsrmi a0, 2
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vfsgnj.vv v16, v8, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: ret
@@ -255,11 +251,11 @@ define <vscale x 16 x bfloat> @vp_floor_nxv16bf16_unmasked(<vscale x 16 x bfloat
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v8, v16
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -285,50 +281,50 @@ define <vscale x 32 x bfloat> @vp_floor_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vslidedown.vx v6, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: vmv1r.v v5, v6
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v5, v16, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: fsrmi a2, 2
-; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a2
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB10_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB10_2:
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t
-; CHECK-NEXT: vmv1r.v v8, v7
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v16, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: fsrmi a0, 2
-; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a0
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 32 x bfloat> @llvm.vp.floor.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x bfloat> %v
@@ -348,37 +344,37 @@ define <vscale x 32 x bfloat> @vp_floor_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v7, v16, a2
; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: vmv1r.v v6, v7
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v6, v16, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: fsrmi a2, 2
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a2
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB11_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB11_2:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v24, v16
; CHECK-NEXT: vmflt.vf v0, v24, fa5
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -399,9 +395,9 @@ define <vscale x 1 x half> @vp_floor_nxv1f16(<vscale x 1 x half> %va, <vscale x
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 2
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 2
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -413,26 +409,24 @@ define <vscale x 1 x half> @vp_floor_nxv1f16(<vscale x 1 x half> %va, <vscale x
; ZVFHMIN-LABEL: vp_floor_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 2
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x half> @llvm.vp.floor.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x half> %v
@@ -446,8 +440,8 @@ define <vscale x 1 x half> @vp_floor_nxv1f16_unmasked(<vscale x 1 x half> %va, i
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 2
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -460,11 +454,11 @@ define <vscale x 1 x half> @vp_floor_nxv1f16_unmasked(<vscale x 1 x half> %va, i
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -485,9 +479,9 @@ define <vscale x 2 x half> @vp_floor_nxv2f16(<vscale x 2 x half> %va, <vscale x
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 2
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 2
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -499,26 +493,24 @@ define <vscale x 2 x half> @vp_floor_nxv2f16(<vscale x 2 x half> %va, <vscale x
; ZVFHMIN-LABEL: vp_floor_nxv2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 2
-; ZVFHMIN-NEXT: vmv.v.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 2 x half> @llvm.vp.floor.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x half> %v
@@ -532,8 +524,8 @@ define <vscale x 2 x half> @vp_floor_nxv2f16_unmasked(<vscale x 2 x half> %va, i
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 2
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -546,11 +538,11 @@ define <vscale x 2 x half> @vp_floor_nxv2f16_unmasked(<vscale x 2 x half> %va, i
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -571,9 +563,9 @@ define <vscale x 4 x half> @vp_floor_nxv4f16(<vscale x 4 x half> %va, <vscale x
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 2
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 2
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -588,21 +580,21 @@ define <vscale x 4 x half> @vp_floor_nxv4f16(<vscale x 4 x half> %va, <vscale x
; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v13, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: fsrmi a0, 2
-; ZVFHMIN-NEXT: vmv1r.v v0, v13
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
+; ZVFHMIN-NEXT: vmv1r.v v0, v13
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: ret
@@ -618,8 +610,8 @@ define <vscale x 4 x half> @vp_floor_nxv4f16_unmasked(<vscale x 4 x half> %va, i
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 2
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -632,11 +624,11 @@ define <vscale x 4 x half> @vp_floor_nxv4f16_unmasked(<vscale x 4 x half> %va, i
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -676,21 +668,21 @@ define <vscale x 8 x half> @vp_floor_nxv8f16(<vscale x 8 x half> %va, <vscale x
; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: fsrmi a0, 2
-; ZVFHMIN-NEXT: vmv1r.v v0, v17
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vmv1r.v v0, v17
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
@@ -706,8 +698,8 @@ define <vscale x 8 x half> @vp_floor_nxv8f16_unmasked(<vscale x 8 x half> %va, i
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 2
+; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -720,11 +712,11 @@ define <vscale x 8 x half> @vp_floor_nxv8f16_unmasked(<vscale x 8 x half> %va, i
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -764,21 +756,21 @@ define <vscale x 16 x half> @vp_floor_nxv16f16(<vscale x 16 x half> %va, <vscale
; ZVFHMIN-NEXT: vmv1r.v v24, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v25, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v16, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v25, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v24, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v25, v0
; ZVFHMIN-NEXT: fsrmi a0, 2
-; ZVFHMIN-NEXT: vmv1r.v v0, v25
+; ZVFHMIN-NEXT: vmv1r.v v0, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v24
+; ZVFHMIN-NEXT: vmv1r.v v0, v25
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
@@ -794,8 +786,8 @@ define <vscale x 16 x half> @vp_floor_nxv16f16_unmasked(<vscale x 16 x half> %va
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: fsrmi a0, 2
+; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -808,11 +800,11 @@ define <vscale x 16 x half> @vp_floor_nxv16f16_unmasked(<vscale x 16 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v16
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -858,50 +850,50 @@ define <vscale x 32 x half> @vp_floor_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: vmv1r.v v5, v6
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v5, v16, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: fsrmi a2, 2
-; ZVFHMIN-NEXT: vmv1r.v v0, v5
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a2
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB22_2:
; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v8, v7
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v16, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v8, v0
; ZVFHMIN-NEXT: fsrmi a0, 2
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 32 x half> @llvm.vp.floor.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x half> %v
@@ -915,8 +907,8 @@ define <vscale x 32 x half> @vp_floor_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: fsrmi a0, 2
+; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -937,37 +929,37 @@ define <vscale x 32 x half> @vp_floor_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v7, v16, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: vmv1r.v v6, v7
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v6, v16, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: fsrmi a2, 2
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a2
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB23_2:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v24, v16
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -987,9 +979,9 @@ define <vscale x 1 x float> @vp_floor_nxv1f32(<vscale x 1 x float> %va, <vscale
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -1008,8 +1000,8 @@ define <vscale x 1 x float> @vp_floor_nxv1f32_unmasked(<vscale x 1 x float> %va,
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1027,9 +1019,9 @@ define <vscale x 2 x float> @vp_floor_nxv2f32(<vscale x 2 x float> %va, <vscale
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -1048,8 +1040,8 @@ define <vscale x 2 x float> @vp_floor_nxv2f32_unmasked(<vscale x 2 x float> %va,
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1090,8 +1082,8 @@ define <vscale x 4 x float> @vp_floor_nxv4f32_unmasked(<vscale x 4 x float> %va,
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1132,8 +1124,8 @@ define <vscale x 8 x float> @vp_floor_nxv8f32_unmasked(<vscale x 8 x float> %va,
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1174,8 +1166,8 @@ define <vscale x 16 x float> @vp_floor_nxv16f32_unmasked(<vscale x 16 x float> %
; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 2
+; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1193,9 +1185,9 @@ define <vscale x 1 x double> @vp_floor_nxv1f64(<vscale x 1 x double> %va, <vscal
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI34_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZVFH-NEXT: fsrmi a0, 2
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a0, 2
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
@@ -1211,9 +1203,9 @@ define <vscale x 1 x double> @vp_floor_nxv1f64(<vscale x 1 x double> %va, <vscal
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
+; RV64ZVFH-NEXT: fsrmi a0, 2
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZVFH-NEXT: fsrmi a0, 2
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
@@ -1228,9 +1220,9 @@ define <vscale x 1 x double> @vp_floor_nxv1f64(<vscale x 1 x double> %va, <vscal
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI34_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZVFHMIN-NEXT: fsrmi a0, 2
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a0, 2
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
@@ -1246,9 +1238,9 @@ define <vscale x 1 x double> @vp_floor_nxv1f64(<vscale x 1 x double> %va, <vscal
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
+; RV64ZVFHMIN-NEXT: fsrmi a0, 2
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a0, 2
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
@@ -1267,8 +1259,8 @@ define <vscale x 1 x double> @vp_floor_nxv1f64_unmasked(<vscale x 1 x double> %v
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI35_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: fsrmi a0, 2
+; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1283,8 +1275,8 @@ define <vscale x 1 x double> @vp_floor_nxv1f64_unmasked(<vscale x 1 x double> %v
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: fsrmi a0, 2
+; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1298,8 +1290,8 @@ define <vscale x 1 x double> @vp_floor_nxv1f64_unmasked(<vscale x 1 x double> %v
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI35_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1314,8 +1306,8 @@ define <vscale x 1 x double> @vp_floor_nxv1f64_unmasked(<vscale x 1 x double> %v
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1415,8 +1407,8 @@ define <vscale x 2 x double> @vp_floor_nxv2f64_unmasked(<vscale x 2 x double> %v
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI37_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZVFH-NEXT: vfabs.v v10, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: fsrmi a0, 2
+; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1431,8 +1423,8 @@ define <vscale x 2 x double> @vp_floor_nxv2f64_unmasked(<vscale x 2 x double> %v
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: fsrmi a0, 2
+; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1446,8 +1438,8 @@ define <vscale x 2 x double> @vp_floor_nxv2f64_unmasked(<vscale x 2 x double> %v
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI37_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v10, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1462,8 +1454,8 @@ define <vscale x 2 x double> @vp_floor_nxv2f64_unmasked(<vscale x 2 x double> %v
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1563,8 +1555,8 @@ define <vscale x 4 x double> @vp_floor_nxv4f64_unmasked(<vscale x 4 x double> %v
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI39_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZVFH-NEXT: vfabs.v v12, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: fsrmi a0, 2
+; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1579,8 +1571,8 @@ define <vscale x 4 x double> @vp_floor_nxv4f64_unmasked(<vscale x 4 x double> %v
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: fsrmi a0, 2
+; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1594,8 +1586,8 @@ define <vscale x 4 x double> @vp_floor_nxv4f64_unmasked(<vscale x 4 x double> %v
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI39_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v12, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1610,8 +1602,8 @@ define <vscale x 4 x double> @vp_floor_nxv4f64_unmasked(<vscale x 4 x double> %v
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1711,8 +1703,8 @@ define <vscale x 7 x double> @vp_floor_nxv7f64_unmasked(<vscale x 7 x double> %v
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI41_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 2
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1727,8 +1719,8 @@ define <vscale x 7 x double> @vp_floor_nxv7f64_unmasked(<vscale x 7 x double> %v
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 2
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1742,8 +1734,8 @@ define <vscale x 7 x double> @vp_floor_nxv7f64_unmasked(<vscale x 7 x double> %v
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI41_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1758,8 +1750,8 @@ define <vscale x 7 x double> @vp_floor_nxv7f64_unmasked(<vscale x 7 x double> %v
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1859,8 +1851,8 @@ define <vscale x 8 x double> @vp_floor_nxv8f64_unmasked(<vscale x 8 x double> %v
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI43_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 2
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1875,8 +1867,8 @@ define <vscale x 8 x double> @vp_floor_nxv8f64_unmasked(<vscale x 8 x double> %v
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 2
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1890,8 +1882,8 @@ define <vscale x 8 x double> @vp_floor_nxv8f64_unmasked(<vscale x 8 x double> %v
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI43_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1906,8 +1898,8 @@ define <vscale x 8 x double> @vp_floor_nxv8f64_unmasked(<vscale x 8 x double> %v
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1933,8 +1925,8 @@ define <vscale x 16 x double> @vp_floor_nxv16f64(<vscale x 16 x double> %va, <vs
; RV32ZVFH-NEXT: vslidedown.vx v6, v0, a3
; RV32ZVFH-NEXT: sltu a3, a0, a2
; RV32ZVFH-NEXT: addi a3, a3, -1
-; RV32ZVFH-NEXT: and a2, a3, a2
; RV32ZVFH-NEXT: vmv1r.v v0, v6
+; RV32ZVFH-NEXT: and a2, a3, a2
; RV32ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -1979,8 +1971,8 @@ define <vscale x 16 x double> @vp_floor_nxv16f64(<vscale x 16 x double> %va, <vs
; RV64ZVFH-NEXT: fmv.d.x fa5, a2
; RV64ZVFH-NEXT: sltu a2, a0, a3
; RV64ZVFH-NEXT: addi a2, a2, -1
-; RV64ZVFH-NEXT: and a2, a2, a3
; RV64ZVFH-NEXT: vmv1r.v v0, v6
+; RV64ZVFH-NEXT: and a2, a2, a3
; RV64ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -2024,8 +2016,8 @@ define <vscale x 16 x double> @vp_floor_nxv16f64(<vscale x 16 x double> %va, <vs
; RV32ZVFHMIN-NEXT: vslidedown.vx v6, v0, a3
; RV32ZVFHMIN-NEXT: sltu a3, a0, a2
; RV32ZVFHMIN-NEXT: addi a3, a3, -1
-; RV32ZVFHMIN-NEXT: and a2, a3, a2
; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV32ZVFHMIN-NEXT: and a2, a3, a2
; RV32ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -2070,8 +2062,8 @@ define <vscale x 16 x double> @vp_floor_nxv16f64(<vscale x 16 x double> %va, <vs
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a2
; RV64ZVFHMIN-NEXT: sltu a2, a0, a3
; RV64ZVFHMIN-NEXT: addi a2, a2, -1
-; RV64ZVFHMIN-NEXT: and a2, a2, a3
; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV64ZVFHMIN-NEXT: and a2, a2, a3
; RV64ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -2116,12 +2108,12 @@ define <vscale x 16 x double> @vp_floor_nxv16f64_unmasked(<vscale x 16 x double>
; RV32ZVFH-NEXT: sltu a2, a0, a3
; RV32ZVFH-NEXT: addi a2, a2, -1
; RV32ZVFH-NEXT: and a2, a2, a3
+; RV32ZVFH-NEXT: fsrmi a3, 2
; RV32ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v16
; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFH-NEXT: fsrmi a2, 2
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFH-NEXT: fsrm a2
+; RV32ZVFH-NEXT: fsrm a3
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -2131,8 +2123,8 @@ define <vscale x 16 x double> @vp_floor_nxv16f64_unmasked(<vscale x 16 x double>
; RV32ZVFH-NEXT: .LBB45_2:
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
; RV32ZVFH-NEXT: fsrmi a0, 2
+; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -2150,12 +2142,12 @@ define <vscale x 16 x double> @vp_floor_nxv16f64_unmasked(<vscale x 16 x double>
; RV64ZVFH-NEXT: sltu a2, a0, a3
; RV64ZVFH-NEXT: addi a2, a2, -1
; RV64ZVFH-NEXT: and a2, a2, a3
+; RV64ZVFH-NEXT: fsrmi a3, 2
; RV64ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v16
; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFH-NEXT: fsrmi a2, 2
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFH-NEXT: fsrm a2
+; RV64ZVFH-NEXT: fsrm a3
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -2165,8 +2157,8 @@ define <vscale x 16 x double> @vp_floor_nxv16f64_unmasked(<vscale x 16 x double>
; RV64ZVFH-NEXT: .LBB45_2:
; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v8
-; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
; RV64ZVFH-NEXT: fsrmi a0, 2
+; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -2183,12 +2175,12 @@ define <vscale x 16 x double> @vp_floor_nxv16f64_unmasked(<vscale x 16 x double>
; RV32ZVFHMIN-NEXT: sltu a2, a0, a3
; RV32ZVFHMIN-NEXT: addi a2, a2, -1
; RV32ZVFHMIN-NEXT: and a2, a2, a3
+; RV32ZVFHMIN-NEXT: fsrmi a3, 2
; RV32ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v16
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFHMIN-NEXT: fsrmi a2, 2
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a2
+; RV32ZVFHMIN-NEXT: fsrm a3
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -2198,8 +2190,8 @@ define <vscale x 16 x double> @vp_floor_nxv16f64_unmasked(<vscale x 16 x double>
; RV32ZVFHMIN-NEXT: .LBB45_2:
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 2
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -2217,12 +2209,12 @@ define <vscale x 16 x double> @vp_floor_nxv16f64_unmasked(<vscale x 16 x double>
; RV64ZVFHMIN-NEXT: sltu a2, a0, a3
; RV64ZVFHMIN-NEXT: addi a2, a2, -1
; RV64ZVFHMIN-NEXT: and a2, a2, a3
+; RV64ZVFHMIN-NEXT: fsrmi a3, 2
; RV64ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v16
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFHMIN-NEXT: fsrmi a2, 2
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a2
+; RV64ZVFHMIN-NEXT: fsrm a3
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -2232,8 +2224,8 @@ define <vscale x 16 x double> @vp_floor_nxv16f64_unmasked(<vscale x 16 x double>
; RV64ZVFHMIN-NEXT: .LBB45_2:
; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v8
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 2
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
index c9a210c054244..c0ddb812f833e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
@@ -20,16 +20,14 @@ define <vscale x 1 x bfloat> @vfmax_nxv1bf16_vv(<vscale x 1 x bfloat> %a, <vscal
; ZVFBFMIN-LABEL: vfmax_nxv1bf16_vv:
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v9
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v9
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFBFMIN-NEXT: vfmax.vv v9, v8, v9
+; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFBFMIN-NEXT: vfmax.vv v9, v9, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
; ZVFBFMIN-NEXT: ret
@@ -51,16 +49,14 @@ define <vscale x 2 x bfloat> @vfmax_nxv2bf16_vv(<vscale x 2 x bfloat> %a, <vscal
; ZVFBFMIN-LABEL: vfmax_nxv2bf16_vv:
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v9
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v9
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFBFMIN-NEXT: vfmax.vv v9, v8, v9
+; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFBFMIN-NEXT: vfmax.vv v9, v9, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
; ZVFBFMIN-NEXT: ret
@@ -82,15 +78,13 @@ define <vscale x 4 x bfloat> @vfmax_nxv4bf16_vv(<vscale x 4 x bfloat> %a, <vscal
; ZVFBFMIN-LABEL: vfmax_nxv4bf16_vv:
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v9
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v9
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v10, v12, v0
; ZVFBFMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFBFMIN-NEXT: vmerge.vvm v10, v12, v10, v0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v12, v10, v0
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
+; ZVFBFMIN-NEXT: vmerge.vvm v10, v10, v12, v0
; ZVFBFMIN-NEXT: vfmax.vv v10, v10, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
@@ -113,15 +107,13 @@ define <vscale x 8 x bfloat> @vfmax_nxv8bf16_vv(<vscale x 8 x bfloat> %a, <vscal
; ZVFBFMIN-LABEL: vfmax_nxv8bf16_vv:
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v10
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v12, v16, v0
; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
-; ZVFBFMIN-NEXT: vmerge.vvm v12, v16, v12, v0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v12, v0
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v12, v12
+; ZVFBFMIN-NEXT: vmerge.vvm v12, v12, v16, v0
; ZVFBFMIN-NEXT: vfmax.vv v12, v12, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
@@ -148,9 +140,8 @@ define <vscale x 16 x bfloat> @vfmax_nxv16bf16_vv(<vscale x 16 x bfloat> %a, <vs
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v24, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT: vmfeq.vv v0, v24, v24
-; ZVFBFMIN-NEXT: vmfeq.vv v7, v16, v16
; ZVFBFMIN-NEXT: vmerge.vvm v8, v24, v16, v0
-; ZVFBFMIN-NEXT: vmv1r.v v0, v7
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
; ZVFBFMIN-NEXT: vmerge.vvm v16, v16, v24, v0
; ZVFBFMIN-NEXT: vfmax.vv v16, v16, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -215,9 +206,8 @@ define <vscale x 32 x bfloat> @vfmax_nxv32bf16_vv(<vscale x 32 x bfloat> %a, <vs
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v20
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmfeq.vv v7, v24, v24
; ZVFBFMIN-NEXT: vmerge.vvm v16, v8, v24, v0
-; ZVFBFMIN-NEXT: vmv1r.v v0, v7
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v24, v24
; ZVFBFMIN-NEXT: vmerge.vvm v8, v24, v8, v0
; ZVFBFMIN-NEXT: vfmax.vv v16, v8, v16
; ZVFBFMIN-NEXT: csrr a0, vlenb
@@ -238,9 +228,8 @@ define <vscale x 32 x bfloat> @vfmax_nxv32bf16_vv(<vscale x 32 x bfloat> %a, <vs
; ZVFBFA: # %bb.0:
; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m8, ta, ma
; ZVFBFA-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFA-NEXT: vmfeq.vv v7, v16, v16
; ZVFBFA-NEXT: vmerge.vvm v24, v8, v16, v0
-; ZVFBFA-NEXT: vmv1r.v v0, v7
+; ZVFBFA-NEXT: vmfeq.vv v0, v16, v16
; ZVFBFA-NEXT: vmerge.vvm v8, v16, v8, v0
; ZVFBFA-NEXT: vfmax.vv v8, v8, v24
; ZVFBFA-NEXT: ret
@@ -262,16 +251,14 @@ define <vscale x 1 x half> @vfmax_nxv1f16_vv(<vscale x 1 x half> %a, <vscale x 1
; ZVFHMIN-LABEL: vfmax_nxv1f16_vv:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFHMIN-NEXT: vfmax.vv v9, v8, v9
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
@@ -293,16 +280,14 @@ define <vscale x 2 x half> @vfmax_nxv2f16_vv(<vscale x 2 x half> %a, <vscale x 2
; ZVFHMIN-LABEL: vfmax_nxv2f16_vv:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFHMIN-NEXT: vfmax.vv v9, v8, v9
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
@@ -324,15 +309,13 @@ define <vscale x 4 x half> @vfmax_nxv4f16_vv(<vscale x 4 x half> %a, <vscale x 4
; ZVFHMIN-LABEL: vfmax_nxv4f16_vv:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v10, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
+; ZVFHMIN-NEXT: vmerge.vvm v10, v10, v12, v0
; ZVFHMIN-NEXT: vfmax.vv v10, v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
@@ -355,15 +338,13 @@ define <vscale x 8 x half> @vfmax_nxv8f16_vv(<vscale x 8 x half> %a, <vscale x 8
; ZVFHMIN-LABEL: vfmax_nxv8f16_vv:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
-; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v12, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
+; ZVFHMIN-NEXT: vmerge.vvm v12, v12, v16, v0
; ZVFHMIN-NEXT: vfmax.vv v12, v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
@@ -390,9 +371,8 @@ define <vscale x 16 x half> @vfmax_nxv16f16_vv(<vscale x 16 x half> %a, <vscale
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24
-; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0
; ZVFHMIN-NEXT: vfmax.vv v16, v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -407,9 +387,8 @@ define <vscale x 32 x half> @vfmax_nxv32f16_vv(<vscale x 32 x half> %a, <vscale
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
-; ZVFH-NEXT: vmfeq.vv v7, v16, v16
; ZVFH-NEXT: vmerge.vvm v24, v8, v16, v0
-; ZVFH-NEXT: vmv1r.v v0, v7
+; ZVFH-NEXT: vmfeq.vv v0, v16, v16
; ZVFH-NEXT: vmerge.vvm v8, v16, v8, v0
; ZVFH-NEXT: vfmax.vv v8, v8, v24
; ZVFH-NEXT: ret
@@ -458,9 +437,8 @@ define <vscale x 32 x half> @vfmax_nxv32f16_vv(<vscale x 32 x half> %a, <vscale
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmfeq.vv v7, v24, v24
; ZVFHMIN-NEXT: vmerge.vvm v16, v8, v24, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24
; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v8, v0
; ZVFHMIN-NEXT: vfmax.vv v16, v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
@@ -541,9 +519,8 @@ define <vscale x 16 x float> @vfmax_nxv16f32_vv(<vscale x 16 x float> %a, <vscal
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v16, v16
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: vfmax.vv v8, v8, v24
; CHECK-NEXT: ret
@@ -598,9 +575,8 @@ define <vscale x 8 x double> @vfmax_nxv8f64_vv(<vscale x 8 x double> %a, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v16, v16
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: vfmax.vv v8, v8, v24
; CHECK-NEXT: ret
@@ -646,10 +622,12 @@ define <vscale x 1 x half> @vfmax_nxv1f16_vv_nnana(<vscale x 1 x half> %a, <vsca
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v9, v10, v10
-; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
; ZVFHMIN-NEXT: vmv1r.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8
@@ -678,10 +656,12 @@ define <vscale x 1 x half> @vfmax_nxv1f16_vv_nnanb(<vscale x 1 x half> %a, <vsca
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v8, v10, v10
-; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
; ZVFHMIN-NEXT: vmv1r.v v8, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
index c432204b078f5..4fe3faadf0fb8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
@@ -18,16 +18,16 @@ define <vscale x 1 x bfloat> @vfmax_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vsca
; CHECK-LABEL: vfmax_vv_nxv1bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v11, v9, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9, v0.t
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t
-; CHECK-NEXT: vmerge.vvm v8, v9, v11, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfeq.vv v0, v11, v11, v0.t
-; CHECK-NEXT: vmerge.vvm v9, v11, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vmfeq.vv v0, v10, v10, v0.t
+; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vfmax.vv v9, v9, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
@@ -40,16 +40,14 @@ define <vscale x 1 x bfloat> @vfmax_vv_nxv1bf16_unmasked(<vscale x 1 x bfloat> %
; CHECK-LABEL: vfmax_vv_nxv1bf16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v9, v9
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
; CHECK-NEXT: vmfeq.vv v0, v10, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vmerge.vvm v9, v10, v8, v0
-; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
-; CHECK-NEXT: vfmax.vv v9, v8, v9
+; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
; CHECK-NEXT: ret
@@ -61,16 +59,16 @@ define <vscale x 2 x bfloat> @vfmax_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vsca
; CHECK-LABEL: vfmax_vv_nxv2bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v11, v9, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9, v0.t
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t
-; CHECK-NEXT: vmerge.vvm v8, v9, v11, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfeq.vv v0, v11, v11, v0.t
-; CHECK-NEXT: vmerge.vvm v9, v11, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vmfeq.vv v0, v10, v10, v0.t
+; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vfmax.vv v9, v9, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
@@ -83,16 +81,14 @@ define <vscale x 2 x bfloat> @vfmax_vv_nxv2bf16_unmasked(<vscale x 2 x bfloat> %
; CHECK-LABEL: vfmax_vv_nxv2bf16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v9, v9
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
; CHECK-NEXT: vmfeq.vv v0, v10, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v9, v10, v8, v0
-; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
-; CHECK-NEXT: vfmax.vv v9, v8, v9
+; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
; CHECK-NEXT: ret
@@ -104,21 +100,20 @@ define <vscale x 4 x bfloat> @vfmax_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vsca
; CHECK-LABEL: vfmax_vv_nxv4bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v14, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vmfeq.vv v8, v14, v14, v0.t
+; CHECK-NEXT: vmfeq.vv v8, v12, v12, v0.t
+; CHECK-NEXT: vmfeq.vv v14, v10, v10, v0.t
+; CHECK-NEXT: vmv1r.v v15, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vvm v8, v14, v12, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfeq.vv v11, v12, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: vmerge.vvm v12, v12, v14, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vfmax.vv v12, v12, v8, v0.t
+; CHECK-NEXT: vmerge.vvm v8, v12, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v15
+; CHECK-NEXT: vfmax.vv v10, v10, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 4 x bfloat> @llvm.vp.maximum.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x bfloat> %v
@@ -128,15 +123,13 @@ define <vscale x 4 x bfloat> @vfmax_vv_nxv4bf16_unmasked(<vscale x 4 x bfloat> %
; CHECK-LABEL: vfmax_vv_nxv4bf16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vmfeq.vv v0, v10, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9
+; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
; CHECK-NEXT: vmfeq.vv v0, v12, v12
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
+; CHECK-NEXT: vmerge.vvm v8, v12, v10, v0
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0
; CHECK-NEXT: vfmax.vv v10, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
@@ -149,21 +142,20 @@ define <vscale x 8 x bfloat> @vfmax_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vsca
; CHECK-LABEL: vfmax_vv_nxv8bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v12, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v10, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v20, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v10, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmfeq.vv v8, v20, v20, v0.t
+; CHECK-NEXT: vmfeq.vv v8, v16, v16, v0.t
+; CHECK-NEXT: vmfeq.vv v20, v12, v12, v0.t
+; CHECK-NEXT: vmv1r.v v21, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vvm v8, v20, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vv v13, v16, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: vmerge.vvm v16, v16, v20, v0
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vfmax.vv v16, v16, v8, v0.t
+; CHECK-NEXT: vmerge.vvm v8, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v21
+; CHECK-NEXT: vfmax.vv v12, v12, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 8 x bfloat> @llvm.vp.maximum.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x bfloat> %v
@@ -173,15 +165,13 @@ define <vscale x 8 x bfloat> @vfmax_vv_nxv8bf16_unmasked(<vscale x 8 x bfloat> %
; CHECK-LABEL: vfmax_vv_nxv8bf16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmfeq.vv v0, v12, v12
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v10
+; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v10
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
; CHECK-NEXT: vmfeq.vv v0, v16, v16
-; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vmerge.vvm v8, v16, v12, v0
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0
; CHECK-NEXT: vfmax.vv v12, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
@@ -194,18 +184,17 @@ define <vscale x 16 x bfloat> @vfmax_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <v
; CHECK-LABEL: vfmax_vv_nxv16bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v8, v16, v16, v0.t
+; CHECK-NEXT: vmfeq.vv v8, v24, v24, v0.t
+; CHECK-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; CHECK-NEXT: vmv1r.v v6, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmfeq.vv v6, v24, v24, v0.t
+; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vfmax.vv v16, v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
@@ -222,9 +211,8 @@ define <vscale x 16 x bfloat> @vfmax_vv_nxv16bf16_unmasked(<vscale x 16 x bfloat
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v24, v24
-; CHECK-NEXT: vmfeq.vv v7, v16, v16
; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vfmax.vv v16, v16, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -240,101 +228,120 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a2, 24
+; CHECK-NEXT: li a2, 26
; CHECK-NEXT: mul a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: vslidedown.vx v6, v0, a2
+; CHECK-NEXT: csrr a4, vlenb
+; CHECK-NEXT: slli a4, a4, 4
+; CHECK-NEXT: add a4, sp, a4
+; CHECK-NEXT: addi a4, a4, 16
+; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vslidedown.vx v24, v0, a2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a4, 25
+; CHECK-NEXT: mul a2, a2, a4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: addi a3, sp, 16
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: li a4, 25
+; CHECK-NEXT: mul a3, a3, a4
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a3, 25
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v5, v24, v24, v0.t
+; CHECK-NEXT: vmfeq.vv v8, v24, v24, v0.t
+; CHECK-NEXT: vmv8r.v v0, v16
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a3, a2, 4
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a3, 25
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
-; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v4, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmfeq.vv v5, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v5
-; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
+; CHECK-NEXT: vmfeq.vv v9, v16, v16, v0.t
+; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmv1r.v v6, v9
+; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0
; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vfmax.vv v16, v8, v16, v0.t
+; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vfmax.vv v16, v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: bltu a0, a1, .LBB10_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB10_2:
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16, v0.t
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v8, v24, v24, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v16, v0.t
+; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 4
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vvm v24, v24, v16, v0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmfeq.vv v8, v16, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
+; CHECK-NEXT: vmfeq.vv v24, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v25, v16, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v6, v25
+; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vfmax.vv v16, v16, v24, v0.t
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 24
+; CHECK-NEXT: li a1, 26
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
@@ -351,48 +358,92 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a2, 24
-; CHECK-NEXT: mul a1, a1, a2
+; CHECK-NEXT: slli a1, a1, 5
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; CHECK-NEXT: vmset.m v24
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: vmset.m v8
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v7, v24, a2
+; CHECK-NEXT: vslidedown.vx v8, v8, a2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a4, 24
+; CHECK-NEXT: mul a2, a2, a4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: li a4, 24
+; CHECK-NEXT: mul a3, a3, a4
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a3, a3, 3
; CHECK-NEXT: add a3, sp, a3
; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v6, v24, v24, v0.t
-; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: vmfeq.vv v7, v24, v24, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0
+; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmfeq.vv v6, v16, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
+; CHECK-NEXT: vmv1r.v v7, v17
+; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vfmax.vv v16, v16, v8, v0.t
+; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vfmax.vv v16, v8, v16, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: addi a2, sp, 16
@@ -405,28 +456,29 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v16
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v0
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v16, v16
-; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: li a1, 24
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: li a1, 24
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
@@ -436,8 +488,7 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 24
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -451,29 +502,29 @@ define <vscale x 1 x half> @vfmax_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x
; ZVFH-LABEL: vfmax_vv_nxv1f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT: vmv1r.v v10, v0
+; ZVFH-NEXT: vmv1r.v v11, v0
; ZVFH-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0
+; ZVFH-NEXT: vmv1r.v v0, v11
; ZVFH-NEXT: vmfeq.vv v0, v9, v9, v0.t
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
-; ZVFH-NEXT: vfmax.vv v8, v8, v11, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v11
+; ZVFH-NEXT: vfmax.vv v8, v8, v10, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfmax_vv_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v11, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9, v0.t
-; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v11, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
-; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t
-; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v9, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v11
+; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v11
; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
@@ -496,16 +547,14 @@ define <vscale x 1 x half> @vfmax_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, <
; ZVFHMIN-LABEL: vfmax_vv_nxv1f16_unmasked:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFHMIN-NEXT: vfmax.vv v9, v8, v9
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
@@ -517,29 +566,29 @@ define <vscale x 2 x half> @vfmax_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x
; ZVFH-LABEL: vfmax_vv_nxv2f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vmv1r.v v10, v0
+; ZVFH-NEXT: vmv1r.v v11, v0
; ZVFH-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0
+; ZVFH-NEXT: vmv1r.v v0, v11
; ZVFH-NEXT: vmfeq.vv v0, v9, v9, v0.t
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
-; ZVFH-NEXT: vfmax.vv v8, v8, v11, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v11
+; ZVFH-NEXT: vfmax.vv v8, v8, v10, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfmax_vv_nxv2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v11, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9, v0.t
-; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v11, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
-; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t
-; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v9, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v11
+; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v11
; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
@@ -562,16 +611,14 @@ define <vscale x 2 x half> @vfmax_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, <
; ZVFHMIN-LABEL: vfmax_vv_nxv2f16_unmasked:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFHMIN-NEXT: vfmax.vv v9, v8, v9
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vfmax.vv v9, v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
@@ -583,34 +630,33 @@ define <vscale x 4 x half> @vfmax_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x
; ZVFH-LABEL: vfmax_vv_nxv4f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFH-NEXT: vmv1r.v v10, v0
+; ZVFH-NEXT: vmv1r.v v11, v0
; ZVFH-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0
+; ZVFH-NEXT: vmv1r.v v0, v11
; ZVFH-NEXT: vmfeq.vv v0, v9, v9, v0.t
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
-; ZVFH-NEXT: vfmax.vv v8, v8, v11, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v11
+; ZVFH-NEXT: vfmax.vv v8, v8, v10, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfmax_vv_nxv4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v8, v14, v14, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v14, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v15, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v14, v12, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
-; ZVFHMIN-NEXT: vmfeq.vv v11, v12, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v11
-; ZVFHMIN-NEXT: vmerge.vvm v12, v12, v14, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
-; ZVFHMIN-NEXT: vfmax.vv v12, v12, v8, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v10, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v14
+; ZVFHMIN-NEXT: vmerge.vvm v10, v10, v12, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v15
+; ZVFHMIN-NEXT: vfmax.vv v10, v10, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 4 x half> @llvm.vp.maximum.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x half> %v
@@ -630,15 +676,13 @@ define <vscale x 4 x half> @vfmax_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, <
; ZVFHMIN-LABEL: vfmax_vv_nxv4f16_unmasked:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v10, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
+; ZVFHMIN-NEXT: vmerge.vvm v10, v10, v12, v0
; ZVFHMIN-NEXT: vfmax.vv v10, v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
@@ -651,36 +695,34 @@ define <vscale x 8 x half> @vfmax_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; ZVFH-LABEL: vfmax_vv_nxv8f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vmv1r.v v12, v0
-; ZVFH-NEXT: vmfeq.vv v13, v8, v8, v0.t
-; ZVFH-NEXT: vmv1r.v v0, v13
-; ZVFH-NEXT: vmerge.vvm v14, v8, v10, v0
+; ZVFH-NEXT: vmfeq.vv v12, v8, v8, v0.t
+; ZVFH-NEXT: vmfeq.vv v14, v10, v10, v0.t
+; ZVFH-NEXT: vmv1r.v v15, v0
; ZVFH-NEXT: vmv1r.v v0, v12
-; ZVFH-NEXT: vmfeq.vv v13, v10, v10, v0.t
-; ZVFH-NEXT: vmv1r.v v0, v13
+; ZVFH-NEXT: vmerge.vvm v12, v8, v10, v0
+; ZVFH-NEXT: vmv1r.v v0, v14
; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v12
-; ZVFH-NEXT: vfmax.vv v8, v8, v14, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v15
+; ZVFH-NEXT: vfmax.vv v8, v8, v12, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfmax_vv_nxv8f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v12, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v8, v20, v20, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v16, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v20, v12, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v21, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v20, v16, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
-; ZVFHMIN-NEXT: vmfeq.vv v13, v16, v16, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v13
-; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v20, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
-; ZVFHMIN-NEXT: vfmax.vv v16, v16, v8, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v12, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v20
+; ZVFHMIN-NEXT: vmerge.vvm v12, v12, v16, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v21
+; ZVFHMIN-NEXT: vfmax.vv v12, v12, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 8 x half> @llvm.vp.maximum.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x half> %v
@@ -700,15 +742,13 @@ define <vscale x 8 x half> @vfmax_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, <
; ZVFHMIN-LABEL: vfmax_vv_nxv8f16_unmasked:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
-; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v12, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
+; ZVFHMIN-NEXT: vmerge.vvm v12, v12, v16, v0
; ZVFHMIN-NEXT: vfmax.vv v12, v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
@@ -721,33 +761,31 @@ define <vscale x 16 x half> @vfmax_vv_nxv16f16(<vscale x 16 x half> %va, <vscale
; ZVFH-LABEL: vfmax_vv_nxv16f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vmv1r.v v16, v0
-; ZVFH-NEXT: vmfeq.vv v17, v8, v8, v0.t
-; ZVFH-NEXT: vmv1r.v v0, v17
-; ZVFH-NEXT: vmerge.vvm v20, v8, v12, v0
+; ZVFH-NEXT: vmfeq.vv v16, v8, v8, v0.t
+; ZVFH-NEXT: vmfeq.vv v20, v12, v12, v0.t
+; ZVFH-NEXT: vmv1r.v v21, v0
; ZVFH-NEXT: vmv1r.v v0, v16
-; ZVFH-NEXT: vmfeq.vv v17, v12, v12, v0.t
-; ZVFH-NEXT: vmv1r.v v0, v17
+; ZVFH-NEXT: vmerge.vvm v16, v8, v12, v0
+; ZVFH-NEXT: vmv1r.v v0, v20
; ZVFH-NEXT: vmerge.vvm v8, v12, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v16
-; ZVFH-NEXT: vfmax.vv v8, v8, v20, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v21
+; ZVFH-NEXT: vfmax.vv v8, v8, v16, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfmax_vv_nxv16f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v16, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v6, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v24, v0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: vmfeq.vv v6, v24, v24, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vmerge.vvm v16, v24, v16, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vfmax.vv v16, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
@@ -774,9 +812,8 @@ define <vscale x 16 x half> @vfmax_vv_nxv16f16_unmasked(<vscale x 16 x half> %va
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24
-; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0
; ZVFHMIN-NEXT: vfmax.vv v16, v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -790,15 +827,14 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFH-LABEL: vfmax_vv_nxv32f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vmv1r.v v7, v0
; ZVFH-NEXT: vmfeq.vv v24, v8, v8, v0.t
+; ZVFH-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; ZVFH-NEXT: vmv1r.v v6, v0
; ZVFH-NEXT: vmv1r.v v0, v24
; ZVFH-NEXT: vmerge.vvm v24, v8, v16, v0
; ZVFH-NEXT: vmv1r.v v0, v7
-; ZVFH-NEXT: vmfeq.vv v6, v16, v16, v0.t
-; ZVFH-NEXT: vmv1r.v v0, v6
; ZVFH-NEXT: vmerge.vvm v8, v16, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v7
+; ZVFH-NEXT: vmv1r.v v0, v6
; ZVFH-NEXT: vfmax.vv v8, v8, v24, v0.t
; ZVFH-NEXT: ret
;
@@ -807,101 +843,120 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: li a2, 24
+; ZVFHMIN-NEXT: li a2, 26
; ZVFHMIN-NEXT: mul a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 4
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vslidedown.vx v24, v0, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: li a4, 25
+; ZVFHMIN-NEXT: mul a2, a2, a4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: addi a3, sp, 16
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: li a4, 25
+; ZVFHMIN-NEXT: mul a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: li a3, 25
+; ZVFHMIN-NEXT: mul a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v5, v24, v24, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t
+; ZVFHMIN-NEXT: vmv8r.v v0, v16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: slli a3, a2, 4
+; ZVFHMIN-NEXT: add a2, a3, a2
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: li a3, 25
+; ZVFHMIN-NEXT: mul a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v5
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v16, v24, v8, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vmfeq.vv v5, v8, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v5
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v24, v0
+; ZVFHMIN-NEXT: vmfeq.vv v9, v16, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v7, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: vmv1r.v v6, v9
+; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vfmax.vv v16, v8, v16, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vfmax.vv v16, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB22_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: addi a1, sp, 16
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v24, v24, v16, v0
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v16, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0
+; ZVFHMIN-NEXT: vmfeq.vv v24, v8, v8, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v25, v16, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v24
+; ZVFHMIN-NEXT: vmv1r.v v6, v25
+; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v8, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfmax.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: li a1, 24
+; ZVFHMIN-NEXT: li a1, 26
; ZVFHMIN-NEXT: mul a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
@@ -917,9 +972,8 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
-; ZVFH-NEXT: vmfeq.vv v7, v16, v16
; ZVFH-NEXT: vmerge.vvm v24, v8, v16, v0
-; ZVFH-NEXT: vmv1r.v v0, v7
+; ZVFH-NEXT: vmfeq.vv v0, v16, v16
; ZVFH-NEXT: vmerge.vvm v8, v16, v8, v0
; ZVFH-NEXT: vfmax.vv v8, v8, v24
; ZVFH-NEXT: ret
@@ -929,48 +983,92 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: li a2, 24
-; ZVFHMIN-NEXT: mul a1, a1, a2
+; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; ZVFHMIN-NEXT: vmset.m v24
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: vmset.m v8
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v7, v24, a2
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: li a4, 24
+; ZVFHMIN-NEXT: mul a2, a2, a4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: li a4, 24
+; ZVFHMIN-NEXT: mul a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: li a3, 24
+; ZVFHMIN-NEXT: mul a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v6, v24, v24, v0.t
-; ZVFHMIN-NEXT: vmv8r.v v8, v16
+; ZVFHMIN-NEXT: vmfeq.vv v7, v24, v24, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: li a3, 24
+; ZVFHMIN-NEXT: mul a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: li a3, 24
+; ZVFHMIN-NEXT: mul a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0
+; ZVFHMIN-NEXT: vmfeq.vv v17, v8, v8, v0.t
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: vmfeq.vv v6, v16, v16, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0
+; ZVFHMIN-NEXT: vmv1r.v v7, v17
+; ZVFHMIN-NEXT: vmerge.vvm v16, v24, v8, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: vfmax.vv v16, v16, v8, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v24, v0
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: li a3, 24
+; ZVFHMIN-NEXT: mul a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfmax.vv v16, v8, v16, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: li a3, 24
+; ZVFHMIN-NEXT: mul a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
@@ -983,28 +1081,29 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16
-; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
+; ZVFHMIN-NEXT: vmerge.vvm v16, v8, v24, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: li a1, 24
+; ZVFHMIN-NEXT: mul a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v8, v0
+; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24
+; ZVFHMIN-NEXT: vmerge.vvm v16, v24, v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: li a1, 24
+; ZVFHMIN-NEXT: mul a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
@@ -1014,8 +1113,7 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: li a1, 24
-; ZVFHMIN-NEXT: mul a0, a0, a1
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -1029,14 +1127,14 @@ define <vscale x 1 x float> @vfmax_vv_nxv1f32(<vscale x 1 x float> %va, <vscale
; CHECK-LABEL: vfmax_vv_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; CHECK-NEXT: vmerge.vvm v11, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vfmax.vv v8, v8, v11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vfmax.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 1 x float> @llvm.vp.maximum.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x float> %v
@@ -1060,14 +1158,14 @@ define <vscale x 2 x float> @vfmax_vv_nxv2f32(<vscale x 2 x float> %va, <vscale
; CHECK-LABEL: vfmax_vv_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; CHECK-NEXT: vmerge.vvm v11, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vfmax.vv v8, v8, v11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vfmax.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 2 x float> @llvm.vp.maximum.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x float> %v
@@ -1091,16 +1189,15 @@ define <vscale x 4 x float> @vfmax_vv_nxv4f32(<vscale x 4 x float> %va, <vscale
; CHECK-LABEL: vfmax_vv_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v12, v0
-; CHECK-NEXT: vmfeq.vv v13, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: vmerge.vvm v14, v8, v10, v0
+; CHECK-NEXT: vmfeq.vv v12, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v14, v10, v10, v0.t
+; CHECK-NEXT: vmv1r.v v15, v0
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vv v13, v10, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmerge.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vfmax.vv v8, v8, v14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v15
+; CHECK-NEXT: vfmax.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 4 x float> @llvm.vp.maximum.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x float> %v
@@ -1124,16 +1221,15 @@ define <vscale x 8 x float> @vfmax_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: vfmax_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vmv1r.v v16, v0
-; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v17
-; CHECK-NEXT: vmerge.vvm v20, v8, v12, v0
+; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v20, v12, v12, v0.t
+; CHECK-NEXT: vmv1r.v v21, v0
; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vmfeq.vv v17, v12, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmerge.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vfmax.vv v8, v8, v20, v0.t
+; CHECK-NEXT: vmv1r.v v0, v21
+; CHECK-NEXT: vfmax.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 8 x float> @llvm.vp.maximum.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x float> %v
@@ -1157,14 +1253,14 @@ define <vscale x 1 x double> @vfmax_vv_nxv1f64(<vscale x 1 x double> %va, <vscal
; CHECK-LABEL: vfmax_vv_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; CHECK-NEXT: vmerge.vvm v11, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vfmax.vv v8, v8, v11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vfmax.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 1 x double> @llvm.vp.maximum.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x double> %v
@@ -1188,16 +1284,15 @@ define <vscale x 2 x double> @vfmax_vv_nxv2f64(<vscale x 2 x double> %va, <vscal
; CHECK-LABEL: vfmax_vv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v12, v0
-; CHECK-NEXT: vmfeq.vv v13, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: vmerge.vvm v14, v8, v10, v0
+; CHECK-NEXT: vmfeq.vv v12, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v14, v10, v10, v0.t
+; CHECK-NEXT: vmv1r.v v15, v0
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vv v13, v10, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmerge.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vfmax.vv v8, v8, v14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v15
+; CHECK-NEXT: vfmax.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 2 x double> @llvm.vp.maximum.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x double> %v
@@ -1221,16 +1316,15 @@ define <vscale x 4 x double> @vfmax_vv_nxv4f64(<vscale x 4 x double> %va, <vscal
; CHECK-LABEL: vfmax_vv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vmv1r.v v16, v0
-; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v17
-; CHECK-NEXT: vmerge.vvm v20, v8, v12, v0
+; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v20, v12, v12, v0.t
+; CHECK-NEXT: vmv1r.v v21, v0
; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vmfeq.vv v17, v12, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmerge.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vfmax.vv v8, v8, v20, v0.t
+; CHECK-NEXT: vmv1r.v v0, v21
+; CHECK-NEXT: vfmax.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 4 x double> @llvm.vp.maximum.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x double> %v
@@ -1254,15 +1348,14 @@ define <vscale x 8 x double> @vfmax_vv_nxv8f64(<vscale x 8 x double> %va, <vscal
; CHECK-LABEL: vfmax_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vmfeq.vv v24, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; CHECK-NEXT: vmv1r.v v6, v0
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmfeq.vv v6, v16, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vfmax.vv v8, v8, v24, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 8 x double> @llvm.vp.maximum.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 %evl)
@@ -1274,9 +1367,8 @@ define <vscale x 8 x double> @vfmax_vv_nxv8f64_unmasked(<vscale x 8 x double> %v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v16, v16
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: vfmax.vv v8, v8, v24
; CHECK-NEXT: ret
@@ -1290,68 +1382,142 @@ define <vscale x 16 x double> @vfmax_vv_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: li a3, 27
+; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1b, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 27 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a3, a1, 3
; CHECK-NEXT: srli a4, a1, 3
-; CHECK-NEXT: vslidedown.vx v6, v0, a4
+; CHECK-NEXT: csrr a5, vlenb
+; CHECK-NEXT: li a6, 26
+; CHECK-NEXT: mul a5, a5, a6
+; CHECK-NEXT: add a5, sp, a5
+; CHECK-NEXT: addi a5, a5, 16
+; CHECK-NEXT: vs1r.v v0, (a5) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vslidedown.vx v24, v0, a4
+; CHECK-NEXT: csrr a4, vlenb
+; CHECK-NEXT: li a5, 18
+; CHECK-NEXT: mul a4, a4, a5
+; CHECK-NEXT: add a4, sp, a4
+; CHECK-NEXT: addi a4, a4, 16
+; CHECK-NEXT: vs1r.v v24, (a4) # vscale x 8-byte Folded Spill
; CHECK-NEXT: sub a4, a2, a1
; CHECK-NEXT: add a3, a0, a3
; CHECK-NEXT: vl8re64.v v24, (a3)
; CHECK-NEXT: sltu a3, a2, a4
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a3, a3, a4
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: csrr a4, vlenb
+; CHECK-NEXT: li a5, 18
+; CHECK-NEXT: mul a4, a4, a5
+; CHECK-NEXT: add a4, sp, a4
+; CHECK-NEXT: addi a4, a4, 16
+; CHECK-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v8, v16, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv8r.v v8, v16
-; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
-; CHECK-NEXT: addi a3, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmfeq.vv v5, v24, v24, v0.t
-; CHECK-NEXT: vl8re64.v v16, (a0)
-; CHECK-NEXT: vmv1r.v v0, v5
-; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfmax.vv v8, v8, v24, v0.t
+; CHECK-NEXT: vmfeq.vv v5, v16, v16, v0.t
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: li a4, 18
+; CHECK-NEXT: mul a3, a3, a4
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmfeq.vv v4, v24, v24, v0.t
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a4, a3, 3
+; CHECK-NEXT: add a3, a4, a3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs1r.v v5, (a3) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs1r.v v4, (a3) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vl8re64.v v0, (a0)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a3, 10
+; CHECK-NEXT: mul a0, a0, a3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a3, a0, 3
+; CHECK-NEXT: add a0, a3, a0
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a3, 18
+; CHECK-NEXT: mul a0, a0, a3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vfmax.vv v8, v16, v8, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a3, 18
+; CHECK-NEXT: mul a0, a0, a3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: bltu a2, a1, .LBB40_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB40_2:
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: li a1, 26
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v24, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmfeq.vv v6, v16, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
+; CHECK-NEXT: vmfeq.vv v16, v24, v24, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 10
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 26
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v7, v17
+; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vfmax.vv v8, v8, v24, v0.t
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 26
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vfmax.vv v8, v8, v16, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 18
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: li a1, 27
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -1371,10 +1537,7 @@ define <vscale x 16 x double> @vfmax_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a3, a1, 3
@@ -1385,42 +1548,54 @@ define <vscale x 16 x double> @vfmax_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a3, a3, a4
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vmfeq.vv v7, v24, v24
; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: vfmax.vv v8, v16, v8
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: bltu a2, a1, .LBB41_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB41_2:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v7, v8, v8
; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: vfmax.vv v8, v8, v24
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
index dc4d0beb417c2..02ae0b8032776 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
@@ -20,16 +20,14 @@ define <vscale x 1 x bfloat> @vfmin_nxv1bf16_vv(<vscale x 1 x bfloat> %a, <vscal
; ZVFBFMIN-LABEL: vfmin_nxv1bf16_vv:
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v9
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v9
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFBFMIN-NEXT: vfmin.vv v9, v8, v9
+; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFBFMIN-NEXT: vfmin.vv v9, v9, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
; ZVFBFMIN-NEXT: ret
@@ -51,16 +49,14 @@ define <vscale x 2 x bfloat> @vfmin_nxv2bf16_vv(<vscale x 2 x bfloat> %a, <vscal
; ZVFBFMIN-LABEL: vfmin_nxv2bf16_vv:
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v9
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v9, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v9
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFBFMIN-NEXT: vfmin.vv v9, v8, v9
+; ZVFBFMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFBFMIN-NEXT: vfmin.vv v9, v9, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v9
; ZVFBFMIN-NEXT: ret
@@ -82,15 +78,13 @@ define <vscale x 4 x bfloat> @vfmin_nxv4bf16_vv(<vscale x 4 x bfloat> %a, <vscal
; ZVFBFMIN-LABEL: vfmin_nxv4bf16_vv:
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v8
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v9
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v10, v9
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v10, v12, v0
; ZVFBFMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFBFMIN-NEXT: vmerge.vvm v10, v12, v10, v0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v12, v10, v0
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v10, v10
+; ZVFBFMIN-NEXT: vmerge.vvm v10, v10, v12, v0
; ZVFBFMIN-NEXT: vfmin.vv v10, v10, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v10
@@ -113,15 +107,13 @@ define <vscale x 8 x bfloat> @vfmin_nxv8bf16_vv(<vscale x 8 x bfloat> %a, <vscal
; ZVFBFMIN-LABEL: vfmin_nxv8bf16_vv:
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v8
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v12, v10
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v10
-; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v12, v16, v0
; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
-; ZVFBFMIN-NEXT: vmerge.vvm v12, v16, v12, v0
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v12, v0
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v12, v12
+; ZVFBFMIN-NEXT: vmerge.vvm v12, v12, v16, v0
; ZVFBFMIN-NEXT: vfmin.vv v12, v12, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFBFMIN-NEXT: vfncvtbf16.f.f.w v8, v12
@@ -148,9 +140,8 @@ define <vscale x 16 x bfloat> @vfmin_nxv16bf16_vv(<vscale x 16 x bfloat> %a, <vs
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v24, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT: vmfeq.vv v0, v24, v24
-; ZVFBFMIN-NEXT: vmfeq.vv v7, v16, v16
; ZVFBFMIN-NEXT: vmerge.vvm v8, v24, v16, v0
-; ZVFBFMIN-NEXT: vmv1r.v v0, v7
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
; ZVFBFMIN-NEXT: vmerge.vvm v16, v16, v24, v0
; ZVFBFMIN-NEXT: vfmin.vv v16, v16, v8
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -215,9 +206,8 @@ define <vscale x 32 x bfloat> @vfmin_nxv32bf16_vv(<vscale x 32 x bfloat> %a, <vs
; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v20
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmfeq.vv v7, v24, v24
; ZVFBFMIN-NEXT: vmerge.vvm v16, v8, v24, v0
-; ZVFBFMIN-NEXT: vmv1r.v v0, v7
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v24, v24
; ZVFBFMIN-NEXT: vmerge.vvm v8, v24, v8, v0
; ZVFBFMIN-NEXT: vfmin.vv v16, v8, v16
; ZVFBFMIN-NEXT: csrr a0, vlenb
@@ -238,9 +228,8 @@ define <vscale x 32 x bfloat> @vfmin_nxv32bf16_vv(<vscale x 32 x bfloat> %a, <vs
; ZVFBFA: # %bb.0:
; ZVFBFA-NEXT: vsetvli a0, zero, e16alt, m8, ta, ma
; ZVFBFA-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFA-NEXT: vmfeq.vv v7, v16, v16
; ZVFBFA-NEXT: vmerge.vvm v24, v8, v16, v0
-; ZVFBFA-NEXT: vmv1r.v v0, v7
+; ZVFBFA-NEXT: vmfeq.vv v0, v16, v16
; ZVFBFA-NEXT: vmerge.vvm v8, v16, v8, v0
; ZVFBFA-NEXT: vfmin.vv v8, v8, v24
; ZVFBFA-NEXT: ret
@@ -262,16 +251,14 @@ define <vscale x 1 x half> @vfmin_nxv1f16_vv(<vscale x 1 x half> %a, <vscale x 1
; ZVFHMIN-LABEL: vfmin_nxv1f16_vv:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFHMIN-NEXT: vfmin.vv v9, v8, v9
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
@@ -293,16 +280,14 @@ define <vscale x 2 x half> @vfmin_nxv2f16_vv(<vscale x 2 x half> %a, <vscale x 2
; ZVFHMIN-LABEL: vfmin_nxv2f16_vv:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFHMIN-NEXT: vfmin.vv v9, v8, v9
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
@@ -324,15 +309,13 @@ define <vscale x 4 x half> @vfmin_nxv4f16_vv(<vscale x 4 x half> %a, <vscale x 4
; ZVFHMIN-LABEL: vfmin_nxv4f16_vv:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v10, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
+; ZVFHMIN-NEXT: vmerge.vvm v10, v10, v12, v0
; ZVFHMIN-NEXT: vfmin.vv v10, v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
@@ -355,15 +338,13 @@ define <vscale x 8 x half> @vfmin_nxv8f16_vv(<vscale x 8 x half> %a, <vscale x 8
; ZVFHMIN-LABEL: vfmin_nxv8f16_vv:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
-; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v12, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
+; ZVFHMIN-NEXT: vmerge.vvm v12, v12, v16, v0
; ZVFHMIN-NEXT: vfmin.vv v12, v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
@@ -390,9 +371,8 @@ define <vscale x 16 x half> @vfmin_nxv16f16_vv(<vscale x 16 x half> %a, <vscale
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24
-; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0
; ZVFHMIN-NEXT: vfmin.vv v16, v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -407,9 +387,8 @@ define <vscale x 32 x half> @vfmin_nxv32f16_vv(<vscale x 32 x half> %a, <vscale
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
-; ZVFH-NEXT: vmfeq.vv v7, v16, v16
; ZVFH-NEXT: vmerge.vvm v24, v8, v16, v0
-; ZVFH-NEXT: vmv1r.v v0, v7
+; ZVFH-NEXT: vmfeq.vv v0, v16, v16
; ZVFH-NEXT: vmerge.vvm v8, v16, v8, v0
; ZVFH-NEXT: vfmin.vv v8, v8, v24
; ZVFH-NEXT: ret
@@ -458,9 +437,8 @@ define <vscale x 32 x half> @vfmin_nxv32f16_vv(<vscale x 32 x half> %a, <vscale
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmfeq.vv v7, v24, v24
; ZVFHMIN-NEXT: vmerge.vvm v16, v8, v24, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24
; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v8, v0
; ZVFHMIN-NEXT: vfmin.vv v16, v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
@@ -541,9 +519,8 @@ define <vscale x 16 x float> @vfmin_nxv16f32_vv(<vscale x 16 x float> %a, <vscal
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v16, v16
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: vfmin.vv v8, v8, v24
; CHECK-NEXT: ret
@@ -598,9 +575,8 @@ define <vscale x 8 x double> @vfmin_nxv8f64_vv(<vscale x 8 x double> %a, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v16, v16
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: vfmin.vv v8, v8, v24
; CHECK-NEXT: ret
@@ -646,10 +622,12 @@ define <vscale x 1 x half> @vfmin_nxv1f16_vv_nnana(<vscale x 1 x half> %a, <vsca
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v9, v10, v10
-; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
; ZVFHMIN-NEXT: vmv1r.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8
@@ -678,10 +656,12 @@ define <vscale x 1 x half> @vfmin_nxv1f16_vv_nnanb(<vscale x 1 x half> %a, <vsca
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v8, v10, v10
-; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
; ZVFHMIN-NEXT: vmv1r.v v8, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
index 27816a862cc1b..e8b708fb84aad 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
@@ -18,16 +18,16 @@ define <vscale x 1 x bfloat> @vfmin_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vsca
; CHECK-LABEL: vfmin_vv_nxv1bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v11, v9, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9, v0.t
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t
-; CHECK-NEXT: vmerge.vvm v8, v9, v11, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfeq.vv v0, v11, v11, v0.t
-; CHECK-NEXT: vmerge.vvm v9, v11, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vmfeq.vv v0, v10, v10, v0.t
+; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vfmin.vv v9, v9, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
@@ -40,16 +40,14 @@ define <vscale x 1 x bfloat> @vfmin_vv_nxv1bf16_unmasked(<vscale x 1 x bfloat> %
; CHECK-LABEL: vfmin_vv_nxv1bf16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v9, v9
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
; CHECK-NEXT: vmfeq.vv v0, v10, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vmerge.vvm v9, v10, v8, v0
-; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
-; CHECK-NEXT: vfmin.vv v9, v8, v9
+; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
; CHECK-NEXT: ret
@@ -61,16 +59,16 @@ define <vscale x 2 x bfloat> @vfmin_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vsca
; CHECK-LABEL: vfmin_vv_nxv2bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v11, v9, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9, v0.t
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t
-; CHECK-NEXT: vmerge.vvm v8, v9, v11, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfeq.vv v0, v11, v11, v0.t
-; CHECK-NEXT: vmerge.vvm v9, v11, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vmfeq.vv v0, v10, v10, v0.t
+; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vfmin.vv v9, v9, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
@@ -83,16 +81,14 @@ define <vscale x 2 x bfloat> @vfmin_vv_nxv2bf16_unmasked(<vscale x 2 x bfloat> %
; CHECK-LABEL: vfmin_vv_nxv2bf16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v9, v9
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
; CHECK-NEXT: vmfeq.vv v0, v10, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vmerge.vvm v9, v10, v8, v0
-; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
-; CHECK-NEXT: vfmin.vv v9, v8, v9
+; CHECK-NEXT: vmerge.vvm v9, v10, v9, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
; CHECK-NEXT: ret
@@ -104,21 +100,20 @@ define <vscale x 4 x bfloat> @vfmin_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vsca
; CHECK-LABEL: vfmin_vv_nxv4bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v14, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vmfeq.vv v8, v14, v14, v0.t
+; CHECK-NEXT: vmfeq.vv v8, v12, v12, v0.t
+; CHECK-NEXT: vmfeq.vv v14, v10, v10, v0.t
+; CHECK-NEXT: vmv1r.v v15, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vvm v8, v14, v12, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmfeq.vv v11, v12, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: vmerge.vvm v12, v12, v14, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vfmin.vv v12, v12, v8, v0.t
+; CHECK-NEXT: vmerge.vvm v8, v12, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v15
+; CHECK-NEXT: vfmin.vv v10, v10, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 4 x bfloat> @llvm.vp.minimum.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x bfloat> %v
@@ -128,15 +123,13 @@ define <vscale x 4 x bfloat> @vfmin_vv_nxv4bf16_unmasked(<vscale x 4 x bfloat> %
; CHECK-LABEL: vfmin_vv_nxv4bf16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vmfeq.vv v0, v10, v10
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
+; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9
+; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
; CHECK-NEXT: vmfeq.vv v0, v12, v12
-; CHECK-NEXT: vmerge.vvm v10, v12, v10, v0
+; CHECK-NEXT: vmerge.vvm v8, v12, v10, v0
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmerge.vvm v10, v10, v12, v0
; CHECK-NEXT: vfmin.vv v10, v10, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
@@ -149,21 +142,20 @@ define <vscale x 8 x bfloat> @vfmin_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vsca
; CHECK-LABEL: vfmin_vv_nxv8bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v12, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v10, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v20, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v10, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmfeq.vv v8, v20, v20, v0.t
+; CHECK-NEXT: vmfeq.vv v8, v16, v16, v0.t
+; CHECK-NEXT: vmfeq.vv v20, v12, v12, v0.t
+; CHECK-NEXT: vmv1r.v v21, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vvm v8, v20, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vv v13, v16, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: vmerge.vvm v16, v16, v20, v0
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vfmin.vv v16, v16, v8, v0.t
+; CHECK-NEXT: vmerge.vvm v8, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v20
+; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v21
+; CHECK-NEXT: vfmin.vv v12, v12, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 8 x bfloat> @llvm.vp.minimum.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x bfloat> %v
@@ -173,15 +165,13 @@ define <vscale x 8 x bfloat> @vfmin_vv_nxv8bf16_unmasked(<vscale x 8 x bfloat> %
; CHECK-LABEL: vfmin_vv_nxv8bf16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
-; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmfeq.vv v0, v12, v12
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v10
+; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v10
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
; CHECK-NEXT: vmfeq.vv v0, v16, v16
-; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
+; CHECK-NEXT: vmerge.vvm v8, v16, v12, v0
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0
; CHECK-NEXT: vfmin.vv v12, v12, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
@@ -194,18 +184,17 @@ define <vscale x 16 x bfloat> @vfmin_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <v
; CHECK-LABEL: vfmin_vv_nxv16bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v8, v16, v16, v0.t
+; CHECK-NEXT: vmfeq.vv v8, v24, v24, v0.t
+; CHECK-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; CHECK-NEXT: vmv1r.v v6, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmfeq.vv v6, v24, v24, v0.t
+; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vfmin.vv v16, v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
@@ -222,9 +211,8 @@ define <vscale x 16 x bfloat> @vfmin_vv_nxv16bf16_unmasked(<vscale x 16 x bfloat
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v24, v24
-; CHECK-NEXT: vmfeq.vv v7, v16, v16
; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vfmin.vv v16, v16, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -240,101 +228,120 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a2, 24
+; CHECK-NEXT: li a2, 26
; CHECK-NEXT: mul a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: vslidedown.vx v6, v0, a2
+; CHECK-NEXT: csrr a4, vlenb
+; CHECK-NEXT: slli a4, a4, 4
+; CHECK-NEXT: add a4, sp, a4
+; CHECK-NEXT: addi a4, a4, 16
+; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vslidedown.vx v24, v0, a2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a4, 25
+; CHECK-NEXT: mul a2, a2, a4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: addi a3, sp, 16
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: li a4, 25
+; CHECK-NEXT: mul a3, a3, a4
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a3, 25
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v5, v24, v24, v0.t
+; CHECK-NEXT: vmfeq.vv v8, v24, v24, v0.t
+; CHECK-NEXT: vmv8r.v v0, v16
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a3, a2, 4
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a3, 25
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
-; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v4, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmfeq.vv v5, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v5
-; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
+; CHECK-NEXT: vmfeq.vv v9, v16, v16, v0.t
+; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmv1r.v v6, v9
+; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0
; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vfmin.vv v16, v8, v16, v0.t
+; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vfmin.vv v16, v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: bltu a0, a1, .LBB10_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB10_2:
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16, v0.t
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v8, v24, v24, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v16, v0.t
+; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 4
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vvm v24, v24, v16, v0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmfeq.vv v8, v16, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
+; CHECK-NEXT: vmfeq.vv v24, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v25, v16, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v6, v25
+; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vfmin.vv v16, v16, v24, v0.t
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 24
+; CHECK-NEXT: li a1, 26
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
@@ -351,48 +358,92 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a2, 24
-; CHECK-NEXT: mul a1, a1, a2
+; CHECK-NEXT: slli a1, a1, 5
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; CHECK-NEXT: vmset.m v24
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: vmset.m v8
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v7, v24, a2
+; CHECK-NEXT: vslidedown.vx v8, v8, a2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a4, 24
+; CHECK-NEXT: mul a2, a2, a4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: li a4, 24
+; CHECK-NEXT: mul a3, a3, a4
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a3, a3, 3
; CHECK-NEXT: add a3, sp, a3
; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v6, v24, v24, v0.t
-; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: vmfeq.vv v7, v24, v24, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0
+; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmfeq.vv v6, v16, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
+; CHECK-NEXT: vmv1r.v v7, v17
+; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vfmin.vv v16, v16, v8, v0.t
+; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vfmin.vv v16, v8, v16, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: li a3, 24
+; CHECK-NEXT: mul a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: addi a2, sp, 16
@@ -405,28 +456,29 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v16
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v0
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v16, v16
-; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: li a1, 24
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: li a1, 24
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
@@ -436,8 +488,7 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 24
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -451,29 +502,29 @@ define <vscale x 1 x half> @vfmin_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x
; ZVFH-LABEL: vfmin_vv_nxv1f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT: vmv1r.v v10, v0
+; ZVFH-NEXT: vmv1r.v v11, v0
; ZVFH-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0
+; ZVFH-NEXT: vmv1r.v v0, v11
; ZVFH-NEXT: vmfeq.vv v0, v9, v9, v0.t
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
-; ZVFH-NEXT: vfmin.vv v8, v8, v11, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v11
+; ZVFH-NEXT: vfmin.vv v8, v8, v10, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfmin_vv_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v11, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9, v0.t
-; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v11, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
-; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t
-; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v9, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v11
+; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v11
; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
@@ -496,16 +547,14 @@ define <vscale x 1 x half> @vfmin_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, <
; ZVFHMIN-LABEL: vfmin_vv_nxv1f16_unmasked:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFHMIN-NEXT: vfmin.vv v9, v8, v9
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
@@ -517,29 +566,29 @@ define <vscale x 2 x half> @vfmin_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x
; ZVFH-LABEL: vfmin_vv_nxv2f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vmv1r.v v10, v0
+; ZVFH-NEXT: vmv1r.v v11, v0
; ZVFH-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0
+; ZVFH-NEXT: vmv1r.v v0, v11
; ZVFH-NEXT: vmfeq.vv v0, v9, v9, v0.t
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
-; ZVFH-NEXT: vfmin.vv v8, v8, v11, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v11
+; ZVFH-NEXT: vfmin.vv v8, v8, v10, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfmin_vv_nxv2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v11, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9, v0.t
-; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v11, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
-; ZVFHMIN-NEXT: vmfeq.vv v0, v11, v11, v0.t
-; ZVFHMIN-NEXT: vmerge.vvm v9, v11, v9, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v11
+; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v11
; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
@@ -562,16 +611,14 @@ define <vscale x 2 x half> @vfmin_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, <
; ZVFHMIN-LABEL: vfmin_vv_nxv2f16_unmasked:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
+; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v10, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v8, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; ZVFHMIN-NEXT: vfmin.vv v9, v8, v9
+; ZVFHMIN-NEXT: vmerge.vvm v9, v10, v9, v0
+; ZVFHMIN-NEXT: vfmin.vv v9, v9, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
; ZVFHMIN-NEXT: ret
@@ -583,34 +630,33 @@ define <vscale x 4 x half> @vfmin_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x
; ZVFH-LABEL: vfmin_vv_nxv4f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFH-NEXT: vmv1r.v v10, v0
+; ZVFH-NEXT: vmv1r.v v11, v0
; ZVFH-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; ZVFH-NEXT: vmerge.vvm v11, v8, v9, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: vmerge.vvm v10, v8, v9, v0
+; ZVFH-NEXT: vmv1r.v v0, v11
; ZVFH-NEXT: vmfeq.vv v0, v9, v9, v0.t
; ZVFH-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v10
-; ZVFH-NEXT: vfmin.vv v8, v8, v11, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v11
+; ZVFH-NEXT: vfmin.vv v8, v8, v10, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfmin_vv_nxv4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v8, v14, v14, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v14, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v15, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v14, v12, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
-; ZVFHMIN-NEXT: vmfeq.vv v11, v12, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v11
-; ZVFHMIN-NEXT: vmerge.vvm v12, v12, v14, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v10
-; ZVFHMIN-NEXT: vfmin.vv v12, v12, v8, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v10, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v14
+; ZVFHMIN-NEXT: vmerge.vvm v10, v10, v12, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v15
+; ZVFHMIN-NEXT: vfmin.vv v10, v10, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 4 x half> @llvm.vp.minimum.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x half> %v
@@ -630,15 +676,13 @@ define <vscale x 4 x half> @vfmin_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, <
; ZVFHMIN-LABEL: vfmin_vv_nxv4f16_unmasked:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v12, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFHMIN-NEXT: vmerge.vvm v10, v12, v10, v0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v10, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v10, v10
+; ZVFHMIN-NEXT: vmerge.vvm v10, v10, v12, v0
; ZVFHMIN-NEXT: vfmin.vv v10, v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
@@ -651,36 +695,34 @@ define <vscale x 8 x half> @vfmin_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; ZVFH-LABEL: vfmin_vv_nxv8f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFH-NEXT: vmv1r.v v12, v0
-; ZVFH-NEXT: vmfeq.vv v13, v8, v8, v0.t
-; ZVFH-NEXT: vmv1r.v v0, v13
-; ZVFH-NEXT: vmerge.vvm v14, v8, v10, v0
+; ZVFH-NEXT: vmfeq.vv v12, v8, v8, v0.t
+; ZVFH-NEXT: vmfeq.vv v14, v10, v10, v0.t
+; ZVFH-NEXT: vmv1r.v v15, v0
; ZVFH-NEXT: vmv1r.v v0, v12
-; ZVFH-NEXT: vmfeq.vv v13, v10, v10, v0.t
-; ZVFH-NEXT: vmv1r.v v0, v13
+; ZVFH-NEXT: vmerge.vvm v12, v8, v10, v0
+; ZVFH-NEXT: vmv1r.v v0, v14
; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v12
-; ZVFH-NEXT: vfmin.vv v8, v8, v14, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v15
+; ZVFH-NEXT: vfmin.vv v8, v8, v12, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfmin_vv_nxv8f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v12, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v8, v20, v20, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v16, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v20, v12, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v21, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v20, v16, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
-; ZVFHMIN-NEXT: vmfeq.vv v13, v16, v16, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v13
-; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v20, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
-; ZVFHMIN-NEXT: vfmin.vv v16, v16, v8, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v12, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v20
+; ZVFHMIN-NEXT: vmerge.vvm v12, v12, v16, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v21
+; ZVFHMIN-NEXT: vfmin.vv v12, v12, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 8 x half> @llvm.vp.minimum.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x half> %v
@@ -700,15 +742,13 @@ define <vscale x 8 x half> @vfmin_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, <
; ZVFHMIN-LABEL: vfmin_vv_nxv8f16_unmasked:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v16, v0
; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
-; ZVFHMIN-NEXT: vmerge.vvm v12, v16, v12, v0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v12, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v12
+; ZVFHMIN-NEXT: vmerge.vvm v12, v12, v16, v0
; ZVFHMIN-NEXT: vfmin.vv v12, v12, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
@@ -721,33 +761,31 @@ define <vscale x 16 x half> @vfmin_vv_nxv16f16(<vscale x 16 x half> %va, <vscale
; ZVFH-LABEL: vfmin_vv_nxv16f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vmv1r.v v16, v0
-; ZVFH-NEXT: vmfeq.vv v17, v8, v8, v0.t
-; ZVFH-NEXT: vmv1r.v v0, v17
-; ZVFH-NEXT: vmerge.vvm v20, v8, v12, v0
+; ZVFH-NEXT: vmfeq.vv v16, v8, v8, v0.t
+; ZVFH-NEXT: vmfeq.vv v20, v12, v12, v0.t
+; ZVFH-NEXT: vmv1r.v v21, v0
; ZVFH-NEXT: vmv1r.v v0, v16
-; ZVFH-NEXT: vmfeq.vv v17, v12, v12, v0.t
-; ZVFH-NEXT: vmv1r.v v0, v17
+; ZVFH-NEXT: vmerge.vvm v16, v8, v12, v0
+; ZVFH-NEXT: vmv1r.v v0, v20
; ZVFH-NEXT: vmerge.vvm v8, v12, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v16
-; ZVFH-NEXT: vfmin.vv v8, v8, v20, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v21
+; ZVFH-NEXT: vfmin.vv v8, v8, v16, v0.t
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfmin_vv_nxv16f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v16, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v6, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v24, v0
+; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: vmfeq.vv v6, v24, v24, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vmerge.vvm v16, v24, v16, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vfmin.vv v16, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
@@ -774,9 +812,8 @@ define <vscale x 16 x half> @vfmin_vv_nxv16f16_unmasked(<vscale x 16 x half> %va
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24
-; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0
; ZVFHMIN-NEXT: vfmin.vv v16, v16, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -790,15 +827,14 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFH-LABEL: vfmin_vv_nxv32f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFH-NEXT: vmv1r.v v7, v0
; ZVFH-NEXT: vmfeq.vv v24, v8, v8, v0.t
+; ZVFH-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; ZVFH-NEXT: vmv1r.v v6, v0
; ZVFH-NEXT: vmv1r.v v0, v24
; ZVFH-NEXT: vmerge.vvm v24, v8, v16, v0
; ZVFH-NEXT: vmv1r.v v0, v7
-; ZVFH-NEXT: vmfeq.vv v6, v16, v16, v0.t
-; ZVFH-NEXT: vmv1r.v v0, v6
; ZVFH-NEXT: vmerge.vvm v8, v16, v8, v0
-; ZVFH-NEXT: vmv1r.v v0, v7
+; ZVFH-NEXT: vmv1r.v v0, v6
; ZVFH-NEXT: vfmin.vv v8, v8, v24, v0.t
; ZVFH-NEXT: ret
;
@@ -807,101 +843,120 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: li a2, 24
+; ZVFHMIN-NEXT: li a2, 26
; ZVFHMIN-NEXT: mul a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 4
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vslidedown.vx v24, v0, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: li a4, 25
+; ZVFHMIN-NEXT: mul a2, a2, a4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: addi a3, sp, 16
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: li a4, 25
+; ZVFHMIN-NEXT: mul a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: li a3, 25
+; ZVFHMIN-NEXT: mul a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v5, v24, v24, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t
+; ZVFHMIN-NEXT: vmv8r.v v0, v16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: slli a3, a2, 4
+; ZVFHMIN-NEXT: add a2, a3, a2
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: li a3, 25
+; ZVFHMIN-NEXT: mul a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v5
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v16, v24, v8, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vmfeq.vv v5, v8, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v5
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v24, v0
+; ZVFHMIN-NEXT: vmfeq.vv v9, v16, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v7, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: vmv1r.v v6, v9
+; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vfmin.vv v16, v8, v16, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vfmin.vv v16, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB22_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: addi a1, sp, 16
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v24, v24, v16, v0
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v16, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0
+; ZVFHMIN-NEXT: vmfeq.vv v24, v8, v8, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v25, v16, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v24
+; ZVFHMIN-NEXT: vmv1r.v v6, v25
+; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v8, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfmin.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: li a1, 24
+; ZVFHMIN-NEXT: li a1, 26
; ZVFHMIN-NEXT: mul a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
@@ -917,9 +972,8 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; ZVFH-NEXT: vmfeq.vv v0, v8, v8
-; ZVFH-NEXT: vmfeq.vv v7, v16, v16
; ZVFH-NEXT: vmerge.vvm v24, v8, v16, v0
-; ZVFH-NEXT: vmv1r.v v0, v7
+; ZVFH-NEXT: vmfeq.vv v0, v16, v16
; ZVFH-NEXT: vmerge.vvm v8, v16, v8, v0
; ZVFH-NEXT: vfmin.vv v8, v8, v24
; ZVFH-NEXT: ret
@@ -929,48 +983,92 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: li a2, 24
-; ZVFHMIN-NEXT: mul a1, a1, a2
+; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; ZVFHMIN-NEXT: vmset.m v24
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: vmset.m v8
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v7, v24, a2
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: li a4, 24
+; ZVFHMIN-NEXT: mul a2, a2, a4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: li a4, 24
+; ZVFHMIN-NEXT: mul a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: li a3, 24
+; ZVFHMIN-NEXT: mul a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v6, v24, v24, v0.t
-; ZVFHMIN-NEXT: vmv8r.v v8, v16
+; ZVFHMIN-NEXT: vmfeq.vv v7, v24, v24, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: li a3, 24
+; ZVFHMIN-NEXT: mul a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: li a3, 24
+; ZVFHMIN-NEXT: mul a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0
+; ZVFHMIN-NEXT: vmfeq.vv v17, v8, v8, v0.t
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: vmfeq.vv v6, v16, v16, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0
+; ZVFHMIN-NEXT: vmv1r.v v7, v17
+; ZVFHMIN-NEXT: vmerge.vvm v16, v24, v8, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: vfmin.vv v16, v16, v8, v0.t
+; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v24, v0
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: li a3, 24
+; ZVFHMIN-NEXT: mul a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfmin.vv v16, v8, v16, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: li a3, 24
+; ZVFHMIN-NEXT: mul a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
@@ -983,28 +1081,29 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16
-; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
+; ZVFHMIN-NEXT: vmerge.vvm v16, v8, v24, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: li a1, 24
+; ZVFHMIN-NEXT: mul a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v8, v0
+; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24
+; ZVFHMIN-NEXT: vmerge.vvm v16, v24, v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: li a1, 24
+; ZVFHMIN-NEXT: mul a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
@@ -1014,8 +1113,7 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: li a1, 24
-; ZVFHMIN-NEXT: mul a0, a0, a1
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -1029,14 +1127,14 @@ define <vscale x 1 x float> @vfmin_vv_nxv1f32(<vscale x 1 x float> %va, <vscale
; CHECK-LABEL: vfmin_vv_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; CHECK-NEXT: vmerge.vvm v11, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vfmin.vv v8, v8, v11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vfmin.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 1 x float> @llvm.vp.minimum.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x float> %v
@@ -1060,14 +1158,14 @@ define <vscale x 2 x float> @vfmin_vv_nxv2f32(<vscale x 2 x float> %va, <vscale
; CHECK-LABEL: vfmin_vv_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; CHECK-NEXT: vmerge.vvm v11, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vfmin.vv v8, v8, v11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vfmin.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 2 x float> @llvm.vp.minimum.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x float> %v
@@ -1091,16 +1189,15 @@ define <vscale x 4 x float> @vfmin_vv_nxv4f32(<vscale x 4 x float> %va, <vscale
; CHECK-LABEL: vfmin_vv_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v12, v0
-; CHECK-NEXT: vmfeq.vv v13, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: vmerge.vvm v14, v8, v10, v0
+; CHECK-NEXT: vmfeq.vv v12, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v14, v10, v10, v0.t
+; CHECK-NEXT: vmv1r.v v15, v0
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vv v13, v10, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmerge.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vfmin.vv v8, v8, v14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v15
+; CHECK-NEXT: vfmin.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 4 x float> @llvm.vp.minimum.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x float> %v
@@ -1124,16 +1221,15 @@ define <vscale x 8 x float> @vfmin_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-LABEL: vfmin_vv_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vmv1r.v v16, v0
-; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v17
-; CHECK-NEXT: vmerge.vvm v20, v8, v12, v0
+; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v20, v12, v12, v0.t
+; CHECK-NEXT: vmv1r.v v21, v0
; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vmfeq.vv v17, v12, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmerge.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vfmin.vv v8, v8, v20, v0.t
+; CHECK-NEXT: vmv1r.v v0, v21
+; CHECK-NEXT: vfmin.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 8 x float> @llvm.vp.minimum.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x float> %v
@@ -1157,14 +1253,14 @@ define <vscale x 1 x double> @vfmin_vv_nxv1f64(<vscale x 1 x double> %va, <vscal
; CHECK-LABEL: vfmin_vv_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmfeq.vv v0, v8, v8, v0.t
-; CHECK-NEXT: vmerge.vvm v11, v8, v9, v0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vvm v10, v8, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmfeq.vv v0, v9, v9, v0.t
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vfmin.vv v8, v8, v11, v0.t
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vfmin.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 1 x double> @llvm.vp.minimum.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x double> %v
@@ -1188,16 +1284,15 @@ define <vscale x 2 x double> @vfmin_vv_nxv2f64(<vscale x 2 x double> %va, <vscal
; CHECK-LABEL: vfmin_vv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v12, v0
-; CHECK-NEXT: vmfeq.vv v13, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: vmerge.vvm v14, v8, v10, v0
+; CHECK-NEXT: vmfeq.vv v12, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v14, v10, v10, v0.t
+; CHECK-NEXT: vmv1r.v v15, v0
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmfeq.vv v13, v10, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmerge.vvm v12, v8, v10, v0
+; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vfmin.vv v8, v8, v14, v0.t
+; CHECK-NEXT: vmv1r.v v0, v15
+; CHECK-NEXT: vfmin.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 2 x double> @llvm.vp.minimum.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x double> %v
@@ -1221,16 +1316,15 @@ define <vscale x 4 x double> @vfmin_vv_nxv4f64(<vscale x 4 x double> %va, <vscal
; CHECK-LABEL: vfmin_vv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vmv1r.v v16, v0
-; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v17
-; CHECK-NEXT: vmerge.vvm v20, v8, v12, v0
+; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v20, v12, v12, v0.t
+; CHECK-NEXT: vmv1r.v v21, v0
; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vmfeq.vv v17, v12, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmerge.vvm v16, v8, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vfmin.vv v8, v8, v20, v0.t
+; CHECK-NEXT: vmv1r.v v0, v21
+; CHECK-NEXT: vfmin.vv v8, v8, v16, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 4 x double> @llvm.vp.minimum.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x i1> %m, i32 %evl)
ret <vscale x 4 x double> %v
@@ -1254,15 +1348,14 @@ define <vscale x 8 x double> @vfmin_vv_nxv8f64(<vscale x 8 x double> %va, <vscal
; CHECK-LABEL: vfmin_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vmfeq.vv v24, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; CHECK-NEXT: vmv1r.v v6, v0
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmfeq.vv v6, v16, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vfmin.vv v8, v8, v24, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 8 x double> @llvm.vp.minimum.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 %evl)
@@ -1274,9 +1367,8 @@ define <vscale x 8 x double> @vfmin_vv_nxv8f64_unmasked(<vscale x 8 x double> %v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v16, v16
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
; CHECK-NEXT: vfmin.vv v8, v8, v24
; CHECK-NEXT: ret
@@ -1290,68 +1382,142 @@ define <vscale x 16 x double> @vfmin_vv_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: li a3, 27
+; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1b, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 27 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a3, a1, 3
; CHECK-NEXT: srli a4, a1, 3
-; CHECK-NEXT: vslidedown.vx v6, v0, a4
+; CHECK-NEXT: csrr a5, vlenb
+; CHECK-NEXT: li a6, 26
+; CHECK-NEXT: mul a5, a5, a6
+; CHECK-NEXT: add a5, sp, a5
+; CHECK-NEXT: addi a5, a5, 16
+; CHECK-NEXT: vs1r.v v0, (a5) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vslidedown.vx v24, v0, a4
+; CHECK-NEXT: csrr a4, vlenb
+; CHECK-NEXT: li a5, 18
+; CHECK-NEXT: mul a4, a4, a5
+; CHECK-NEXT: add a4, sp, a4
+; CHECK-NEXT: addi a4, a4, 16
+; CHECK-NEXT: vs1r.v v24, (a4) # vscale x 8-byte Folded Spill
; CHECK-NEXT: sub a4, a2, a1
; CHECK-NEXT: add a3, a0, a3
; CHECK-NEXT: vl8re64.v v24, (a3)
; CHECK-NEXT: sltu a3, a2, a4
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a3, a3, a4
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: csrr a4, vlenb
+; CHECK-NEXT: li a5, 18
+; CHECK-NEXT: mul a4, a4, a5
+; CHECK-NEXT: add a4, sp, a4
+; CHECK-NEXT: addi a4, a4, 16
+; CHECK-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v8, v16, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv8r.v v8, v16
-; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
-; CHECK-NEXT: addi a3, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmfeq.vv v5, v24, v24, v0.t
-; CHECK-NEXT: vl8re64.v v16, (a0)
-; CHECK-NEXT: vmv1r.v v0, v5
-; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfmin.vv v8, v8, v24, v0.t
+; CHECK-NEXT: vmfeq.vv v5, v16, v16, v0.t
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: li a4, 18
+; CHECK-NEXT: mul a3, a3, a4
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmfeq.vv v4, v24, v24, v0.t
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a4, a3, 3
+; CHECK-NEXT: add a3, a4, a3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs1r.v v5, (a3) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs1r.v v4, (a3) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vl8re64.v v0, (a0)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a3, 10
+; CHECK-NEXT: mul a0, a0, a3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a3, a0, 3
+; CHECK-NEXT: add a0, a3, a0
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a3, 18
+; CHECK-NEXT: mul a0, a0, a3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vfmin.vv v8, v16, v8, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a3, 18
+; CHECK-NEXT: mul a0, a0, a3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: bltu a2, a1, .LBB40_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB40_2:
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: li a1, 26
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v24, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmfeq.vv v6, v16, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
+; CHECK-NEXT: vmfeq.vv v16, v24, v24, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 10
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 26
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v7, v17
+; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vfmin.vv v8, v8, v24, v0.t
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 26
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vfmin.vv v8, v8, v16, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 18
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: li a1, 27
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -1371,10 +1537,7 @@ define <vscale x 16 x double> @vfmin_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a3, a1, 3
@@ -1385,42 +1548,54 @@ define <vscale x 16 x double> @vfmin_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a3, a3, a4
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vmfeq.vv v7, v24, v24
; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: vfmin.vv v8, v16, v8
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: bltu a2, a1, .LBB41_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB41_2:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v7, v8, v8
; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: vfmin.vv v8, v8, v24
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
index 6c5b6ff31a24b..d2fda775d4741 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
@@ -255,10 +255,10 @@ define <vscale x 16 x float> @nearbyint_nxv16f32(<vscale x 16 x float> %v) stric
define <vscale x 1 x double> @nearbyint_nxv1f64(<vscale x 1 x double> %v) strictfp {
; RV32-LABEL: nearbyint_nxv1f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: lui a0, %hi(.LCPI11_0)
; RV32-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
+; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
@@ -296,10 +296,10 @@ define <vscale x 1 x double> @nearbyint_nxv1f64(<vscale x 1 x double> %v) strict
define <vscale x 2 x double> @nearbyint_nxv2f64(<vscale x 2 x double> %v) strictfp {
; RV32-LABEL: nearbyint_nxv2f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
+; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
+; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: vmflt.vf v0, v10, fa5
@@ -337,10 +337,10 @@ define <vscale x 2 x double> @nearbyint_nxv2f64(<vscale x 2 x double> %v) strict
define <vscale x 4 x double> @nearbyint_nxv4f64(<vscale x 4 x double> %v) strictfp {
; RV32-LABEL: nearbyint_nxv4f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
+; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
+; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v12, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
@@ -378,10 +378,10 @@ define <vscale x 4 x double> @nearbyint_nxv4f64(<vscale x 4 x double> %v) strict
define <vscale x 8 x double> @nearbyint_nxv8f64(<vscale x 8 x double> %v) strictfp {
; RV32-LABEL: nearbyint_nxv8f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: lui a0, %hi(.LCPI14_0)
; RV32-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v16, v8
; RV32-NEXT: vmflt.vf v0, v16, fa5
diff --git a/llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
index 8bfc002fa629b..f5c2395d8bda4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
@@ -133,11 +133,11 @@ define <vscale x 32 x bfloat> @nearbyint_nxv32bf16(<vscale x 32 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: frflags a0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v24, v16
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v24, fa5
-; CHECK-NEXT: frflags a0
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
@@ -381,11 +381,11 @@ define <vscale x 32 x half> @nearbyint_nxv32f16(<vscale x 32 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: frflags a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v24, v16
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; ZVFHMIN-NEXT: frflags a0
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
diff --git a/llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
index 91897ef7fbac3..2580aae5f3337 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll
@@ -14,10 +14,10 @@ define <vscale x 1 x half> @round_nxv1f16(<vscale x 1 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -37,10 +37,10 @@ define <vscale x 2 x half> @round_nxv2f16(<vscale x 2 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -60,10 +60,10 @@ define <vscale x 4 x half> @round_nxv4f16(<vscale x 4 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -83,10 +83,10 @@ define <vscale x 8 x half> @round_nxv8f16(<vscale x 8 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -106,10 +106,10 @@ define <vscale x 16 x half> @round_nxv16f16(<vscale x 16 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -129,10 +129,10 @@ define <vscale x 32 x half> @round_nxv32f16(<vscale x 32 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -152,9 +152,9 @@ define <vscale x 1 x float> @round_nxv1f32(<vscale x 1 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -174,9 +174,9 @@ define <vscale x 2 x float> @round_nxv2f32(<vscale x 2 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -196,9 +196,9 @@ define <vscale x 4 x float> @round_nxv4f32(<vscale x 4 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -218,9 +218,9 @@ define <vscale x 8 x float> @round_nxv8f32(<vscale x 8 x float> %x) strictfp {
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -240,9 +240,9 @@ define <vscale x 16 x float> @round_nxv16f32(<vscale x 16 x float> %x) strictfp
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -262,9 +262,9 @@ define <vscale x 1 x double> @round_nxv1f64(<vscale x 1 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI11_0)
; RV32-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 4
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: fsrmi a0, 4
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -280,10 +280,10 @@ define <vscale x 1 x double> @round_nxv1f64(<vscale x 1 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v9, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 4
+; RV64-NEXT: vfabs.v v9, v8
+; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -303,9 +303,9 @@ define <vscale x 2 x double> @round_nxv2f64(<vscale x 2 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 4
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: vmflt.vf v0, v10, fa5
-; RV32-NEXT: fsrmi a0, 4
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -321,10 +321,10 @@ define <vscale x 2 x double> @round_nxv2f64(<vscale x 2 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v10, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: fsrmi a0, 4
+; RV64-NEXT: vfabs.v v10, v8
+; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -344,9 +344,9 @@ define <vscale x 4 x double> @round_nxv4f64(<vscale x 4 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 4
; RV32-NEXT: vfabs.v v12, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
-; RV32-NEXT: fsrmi a0, 4
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -362,10 +362,10 @@ define <vscale x 4 x double> @round_nxv4f64(<vscale x 4 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v12, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 4
+; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -385,9 +385,9 @@ define <vscale x 8 x double> @round_nxv8f64(<vscale x 8 x double> %x) strictfp {
; RV32-NEXT: lui a0, %hi(.LCPI14_0)
; RV32-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 4
; RV32-NEXT: vfabs.v v16, v8
; RV32-NEXT: vmflt.vf v0, v16, fa5
-; RV32-NEXT: fsrmi a0, 4
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -403,10 +403,10 @@ define <vscale x 8 x double> @round_nxv8f64(<vscale x 8 x double> %x) strictfp {
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v16, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v16, fa5
; RV64-NEXT: fsrmi a0, 4
+; RV64-NEXT: vfabs.v v16, v8
+; RV64-NEXT: vmflt.vf v0, v16, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64-NEXT: fsrm a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
index 0ebc2a82bd828..e57de37a54b73 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
@@ -20,11 +20,11 @@ define <vscale x 1 x bfloat> @round_nxv1bf16(<vscale x 1 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -43,11 +43,11 @@ define <vscale x 2 x bfloat> @round_nxv2bf16(<vscale x 2 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -66,11 +66,11 @@ define <vscale x 4 x bfloat> @round_nxv4bf16(<vscale x 4 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v8, v10
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -89,11 +89,11 @@ define <vscale x 8 x bfloat> @round_nxv8bf16(<vscale x 8 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfabs.v v8, v12
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -112,11 +112,11 @@ define <vscale x 16 x bfloat> @round_nxv16bf16(<vscale x 16 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v8, v16
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -135,11 +135,11 @@ define <vscale x 32 x bfloat> @round_nxv32bf16(<vscale x 32 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v24, v16
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v24, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -174,8 +174,8 @@ define <vscale x 1 x half> @round_nxv1f16(<vscale x 1 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -188,11 +188,11 @@ define <vscale x 1 x half> @round_nxv1f16(<vscale x 1 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -213,8 +213,8 @@ define <vscale x 2 x half> @round_nxv2f16(<vscale x 2 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -227,11 +227,11 @@ define <vscale x 2 x half> @round_nxv2f16(<vscale x 2 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -252,8 +252,8 @@ define <vscale x 4 x half> @round_nxv4f16(<vscale x 4 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -266,11 +266,11 @@ define <vscale x 4 x half> @round_nxv4f16(<vscale x 4 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -291,8 +291,8 @@ define <vscale x 8 x half> @round_nxv8f16(<vscale x 8 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -305,11 +305,11 @@ define <vscale x 8 x half> @round_nxv8f16(<vscale x 8 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -330,8 +330,8 @@ define <vscale x 16 x half> @round_nxv16f16(<vscale x 16 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -344,11 +344,11 @@ define <vscale x 16 x half> @round_nxv16f16(<vscale x 16 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v16
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -369,8 +369,8 @@ define <vscale x 32 x half> @round_nxv32f16(<vscale x 32 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -383,11 +383,11 @@ define <vscale x 32 x half> @round_nxv32f16(<vscale x 32 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v24, v16
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -421,8 +421,8 @@ define <vscale x 1 x float> @round_nxv1f32(<vscale x 1 x float> %x) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -440,8 +440,8 @@ define <vscale x 2 x float> @round_nxv2f32(<vscale x 2 x float> %x) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -459,8 +459,8 @@ define <vscale x 4 x float> @round_nxv4f32(<vscale x 4 x float> %x) {
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -478,8 +478,8 @@ define <vscale x 8 x float> @round_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -497,8 +497,8 @@ define <vscale x 16 x float> @round_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -516,8 +516,8 @@ define <vscale x 1 x double> @round_nxv1f64(<vscale x 1 x double> %x) {
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI17_0)(a0)
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -532,8 +532,8 @@ define <vscale x 1 x double> @round_nxv1f64(<vscale x 1 x double> %x) {
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -547,8 +547,8 @@ define <vscale x 1 x double> @round_nxv1f64(<vscale x 1 x double> %x) {
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI17_0)(a0)
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -563,8 +563,8 @@ define <vscale x 1 x double> @round_nxv1f64(<vscale x 1 x double> %x) {
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -582,8 +582,8 @@ define <vscale x 2 x double> @round_nxv2f64(<vscale x 2 x double> %x) {
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI18_0)(a0)
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV32ZVFH-NEXT: vfabs.v v10, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -598,8 +598,8 @@ define <vscale x 2 x double> @round_nxv2f64(<vscale x 2 x double> %x) {
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -613,8 +613,8 @@ define <vscale x 2 x double> @round_nxv2f64(<vscale x 2 x double> %x) {
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI18_0)(a0)
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v10, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -629,8 +629,8 @@ define <vscale x 2 x double> @round_nxv2f64(<vscale x 2 x double> %x) {
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -648,8 +648,8 @@ define <vscale x 4 x double> @round_nxv4f64(<vscale x 4 x double> %x) {
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI19_0)(a0)
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32ZVFH-NEXT: vfabs.v v12, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -664,8 +664,8 @@ define <vscale x 4 x double> @round_nxv4f64(<vscale x 4 x double> %x) {
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -679,8 +679,8 @@ define <vscale x 4 x double> @round_nxv4f64(<vscale x 4 x double> %x) {
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI19_0)(a0)
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v12, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -695,8 +695,8 @@ define <vscale x 4 x double> @round_nxv4f64(<vscale x 4 x double> %x) {
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -714,8 +714,8 @@ define <vscale x 8 x double> @round_nxv8f64(<vscale x 8 x double> %x) {
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI20_0)(a0)
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -730,8 +730,8 @@ define <vscale x 8 x double> @round_nxv8f64(<vscale x 8 x double> %x) {
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -745,8 +745,8 @@ define <vscale x 8 x double> @round_nxv8f64(<vscale x 8 x double> %x) {
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI20_0)(a0)
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -761,8 +761,8 @@ define <vscale x 8 x double> @round_nxv8f64(<vscale x 8 x double> %x) {
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
index cd9d124e4b08c..0b4072e4c909d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
@@ -14,10 +14,10 @@ define <vscale x 1 x half> @roundeven_nxv1f16(<vscale x 1 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -37,10 +37,10 @@ define <vscale x 2 x half> @roundeven_nxv2f16(<vscale x 2 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -60,10 +60,10 @@ define <vscale x 4 x half> @roundeven_nxv4f16(<vscale x 4 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -83,10 +83,10 @@ define <vscale x 8 x half> @roundeven_nxv8f16(<vscale x 8 x half> %x) strictfp {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -106,10 +106,10 @@ define <vscale x 16 x half> @roundeven_nxv16f16(<vscale x 16 x half> %x) strictf
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -129,10 +129,10 @@ define <vscale x 32 x half> @roundeven_nxv32f16(<vscale x 32 x half> %x) strictf
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: slli a0, a0, 10
-; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -152,9 +152,9 @@ define <vscale x 1 x float> @roundeven_nxv1f32(<vscale x 1 x float> %x) strictfp
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -174,9 +174,9 @@ define <vscale x 2 x float> @roundeven_nxv2f32(<vscale x 2 x float> %x) strictfp
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -196,9 +196,9 @@ define <vscale x 4 x float> @roundeven_nxv4f32(<vscale x 4 x float> %x) strictfp
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -218,9 +218,9 @@ define <vscale x 8 x float> @roundeven_nxv8f32(<vscale x 8 x float> %x) strictfp
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -240,9 +240,9 @@ define <vscale x 16 x float> @roundeven_nxv16f32(<vscale x 16 x float> %x) stric
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: vmflt.vf v0, v16, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -262,9 +262,9 @@ define <vscale x 1 x double> @roundeven_nxv1f64(<vscale x 1 x double> %x) strict
; RV32-NEXT: lui a0, %hi(.LCPI11_0)
; RV32-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 0
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
-; RV32-NEXT: fsrmi a0, 0
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -280,10 +280,10 @@ define <vscale x 1 x double> @roundeven_nxv1f64(<vscale x 1 x double> %x) strict
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v9, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: fsrmi a0, 0
+; RV64-NEXT: vfabs.v v9, v8
+; RV64-NEXT: vmflt.vf v0, v9, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -303,9 +303,9 @@ define <vscale x 2 x double> @roundeven_nxv2f64(<vscale x 2 x double> %x) strict
; RV32-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 0
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: vmflt.vf v0, v10, fa5
-; RV32-NEXT: fsrmi a0, 0
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV32-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -321,10 +321,10 @@ define <vscale x 2 x double> @roundeven_nxv2f64(<vscale x 2 x double> %x) strict
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v10, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: fsrmi a0, 0
+; RV64-NEXT: vfabs.v v10, v8
+; RV64-NEXT: vmflt.vf v0, v10, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -344,9 +344,9 @@ define <vscale x 4 x double> @roundeven_nxv4f64(<vscale x 4 x double> %x) strict
; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 0
; RV32-NEXT: vfabs.v v12, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
-; RV32-NEXT: fsrmi a0, 0
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV32-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -362,10 +362,10 @@ define <vscale x 4 x double> @roundeven_nxv4f64(<vscale x 4 x double> %x) strict
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v12, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: fsrmi a0, 0
+; RV64-NEXT: vfabs.v v12, v8
+; RV64-NEXT: vmflt.vf v0, v12, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV64-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64-NEXT: fsrm a0
@@ -385,9 +385,9 @@ define <vscale x 8 x double> @roundeven_nxv8f64(<vscale x 8 x double> %x) strict
; RV32-NEXT: lui a0, %hi(.LCPI14_0)
; RV32-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
+; RV32-NEXT: fsrmi a0, 0
; RV32-NEXT: vfabs.v v16, v8
; RV32-NEXT: vmflt.vf v0, v16, fa5
-; RV32-NEXT: fsrmi a0, 0
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32-NEXT: fsrm a0
@@ -403,10 +403,10 @@ define <vscale x 8 x double> @roundeven_nxv8f64(<vscale x 8 x double> %x) strict
; RV64-NEXT: li a0, 1075
; RV64-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV64-NEXT: slli a0, a0, 52
-; RV64-NEXT: vfabs.v v16, v8
; RV64-NEXT: fmv.d.x fa5, a0
-; RV64-NEXT: vmflt.vf v0, v16, fa5
; RV64-NEXT: fsrmi a0, 0
+; RV64-NEXT: vfabs.v v16, v8
+; RV64-NEXT: vmflt.vf v0, v16, fa5
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64-NEXT: fsrm a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
index 5991f1a5cecfa..8e041aa95c49b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
@@ -19,11 +19,11 @@ define <vscale x 1 x bfloat> @roundeven_nxv1bf16(<vscale x 1 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -42,11 +42,11 @@ define <vscale x 2 x bfloat> @roundeven_nxv2bf16(<vscale x 2 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -65,11 +65,11 @@ define <vscale x 4 x bfloat> @roundeven_nxv4bf16(<vscale x 4 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v8, v10
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -88,11 +88,11 @@ define <vscale x 8 x bfloat> @roundeven_nxv8bf16(<vscale x 8 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfabs.v v8, v12
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -111,11 +111,11 @@ define <vscale x 16 x bfloat> @roundeven_nxv16bf16(<vscale x 16 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v8, v16
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -134,11 +134,11 @@ define <vscale x 32 x bfloat> @roundeven_nxv32bf16(<vscale x 32 x bfloat> %x) {
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v24, v16
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v24, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -173,8 +173,8 @@ define <vscale x 1 x half> @roundeven_nxv1f16(<vscale x 1 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -187,11 +187,11 @@ define <vscale x 1 x half> @roundeven_nxv1f16(<vscale x 1 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -212,8 +212,8 @@ define <vscale x 2 x half> @roundeven_nxv2f16(<vscale x 2 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -226,11 +226,11 @@ define <vscale x 2 x half> @roundeven_nxv2f16(<vscale x 2 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -251,8 +251,8 @@ define <vscale x 4 x half> @roundeven_nxv4f16(<vscale x 4 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -265,11 +265,11 @@ define <vscale x 4 x half> @roundeven_nxv4f16(<vscale x 4 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -290,8 +290,8 @@ define <vscale x 8 x half> @roundeven_nxv8f16(<vscale x 8 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -304,11 +304,11 @@ define <vscale x 8 x half> @roundeven_nxv8f16(<vscale x 8 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -329,8 +329,8 @@ define <vscale x 16 x half> @roundeven_nxv16f16(<vscale x 16 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -343,11 +343,11 @@ define <vscale x 16 x half> @roundeven_nxv16f16(<vscale x 16 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v16
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -368,8 +368,8 @@ define <vscale x 32 x half> @roundeven_nxv32f16(<vscale x 32 x half> %x) {
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -382,11 +382,11 @@ define <vscale x 32 x half> @roundeven_nxv32f16(<vscale x 32 x half> %x) {
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v24, v16
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -420,8 +420,8 @@ define <vscale x 1 x float> @roundeven_nxv1f32(<vscale x 1 x float> %x) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -439,8 +439,8 @@ define <vscale x 2 x float> @roundeven_nxv2f32(<vscale x 2 x float> %x) {
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -458,8 +458,8 @@ define <vscale x 4 x float> @roundeven_nxv4f32(<vscale x 4 x float> %x) {
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -477,8 +477,8 @@ define <vscale x 8 x float> @roundeven_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -496,8 +496,8 @@ define <vscale x 16 x float> @roundeven_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -515,8 +515,8 @@ define <vscale x 1 x double> @roundeven_nxv1f64(<vscale x 1 x double> %x) {
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI17_0)(a0)
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -531,8 +531,8 @@ define <vscale x 1 x double> @roundeven_nxv1f64(<vscale x 1 x double> %x) {
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -546,8 +546,8 @@ define <vscale x 1 x double> @roundeven_nxv1f64(<vscale x 1 x double> %x) {
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI17_0)(a0)
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -562,8 +562,8 @@ define <vscale x 1 x double> @roundeven_nxv1f64(<vscale x 1 x double> %x) {
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -581,8 +581,8 @@ define <vscale x 2 x double> @roundeven_nxv2f64(<vscale x 2 x double> %x) {
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI18_0)(a0)
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV32ZVFH-NEXT: vfabs.v v10, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -597,8 +597,8 @@ define <vscale x 2 x double> @roundeven_nxv2f64(<vscale x 2 x double> %x) {
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -612,8 +612,8 @@ define <vscale x 2 x double> @roundeven_nxv2f64(<vscale x 2 x double> %x) {
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI18_0)(a0)
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v10, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -628,8 +628,8 @@ define <vscale x 2 x double> @roundeven_nxv2f64(<vscale x 2 x double> %x) {
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -647,8 +647,8 @@ define <vscale x 4 x double> @roundeven_nxv4f64(<vscale x 4 x double> %x) {
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI19_0)(a0)
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32ZVFH-NEXT: vfabs.v v12, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -663,8 +663,8 @@ define <vscale x 4 x double> @roundeven_nxv4f64(<vscale x 4 x double> %x) {
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -678,8 +678,8 @@ define <vscale x 4 x double> @roundeven_nxv4f64(<vscale x 4 x double> %x) {
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI19_0)(a0)
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v12, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -694,8 +694,8 @@ define <vscale x 4 x double> @roundeven_nxv4f64(<vscale x 4 x double> %x) {
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -713,8 +713,8 @@ define <vscale x 8 x double> @roundeven_nxv8f64(<vscale x 8 x double> %x) {
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI20_0)(a0)
; RV32ZVFH-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -729,8 +729,8 @@ define <vscale x 8 x double> @roundeven_nxv8f64(<vscale x 8 x double> %x) {
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -744,8 +744,8 @@ define <vscale x 8 x double> @roundeven_nxv8f64(<vscale x 8 x double> %x) {
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI20_0)(a0)
; RV32ZVFHMIN-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -760,8 +760,8 @@ define <vscale x 8 x double> @roundeven_nxv8f64(<vscale x 8 x double> %x) {
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
index 736dd1225da88..5d00204f903fe 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
@@ -8,9 +8,9 @@ define <vscale x 1 x i8> @fshr_v1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b,
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vand.vi v11, v11, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -24,9 +24,9 @@ define <vscale x 1 x i8> @fshl_v1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b,
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vand.vi v11, v11, 7, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -40,9 +40,9 @@ define <vscale x 2 x i8> @fshr_v2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b,
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vand.vi v11, v11, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -56,9 +56,9 @@ define <vscale x 2 x i8> @fshl_v2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b,
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vand.vi v11, v11, 7, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -72,9 +72,9 @@ define <vscale x 4 x i8> @fshr_v4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b,
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vand.vi v11, v11, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -88,9 +88,9 @@ define <vscale x 4 x i8> @fshl_v4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b,
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vand.vi v11, v11, 7, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -104,9 +104,9 @@ define <vscale x 8 x i8> @fshr_v8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b,
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vand.vi v11, v11, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -120,9 +120,9 @@ define <vscale x 8 x i8> @fshl_v8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b,
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vand.vi v11, v11, 7, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -136,9 +136,9 @@ define <vscale x 16 x i8> @fshr_v16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8>
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v14, v12, v0.t
+; CHECK-NEXT: vand.vi v12, v12, 7, v0.t
; CHECK-NEXT: vand.vi v14, v14, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
-; CHECK-NEXT: vand.vi v12, v12, 7, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
@@ -152,9 +152,9 @@ define <vscale x 16 x i8> @fshl_v16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8>
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t
; CHECK-NEXT: vnot.v v14, v12, v0.t
+; CHECK-NEXT: vand.vi v12, v12, 7, v0.t
; CHECK-NEXT: vand.vi v14, v14, 7, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
-; CHECK-NEXT: vand.vi v12, v12, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
@@ -168,9 +168,9 @@ define <vscale x 32 x i8> @fshr_v32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8>
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v20, v16, v0.t
+; CHECK-NEXT: vand.vi v16, v16, 7, v0.t
; CHECK-NEXT: vand.vi v20, v20, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
-; CHECK-NEXT: vand.vi v16, v16, 7, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
@@ -184,9 +184,9 @@ define <vscale x 32 x i8> @fshl_v32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8>
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t
; CHECK-NEXT: vnot.v v20, v16, v0.t
+; CHECK-NEXT: vand.vi v16, v16, 7, v0.t
; CHECK-NEXT: vand.vi v20, v20, 7, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
-; CHECK-NEXT: vand.vi v16, v16, 7, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
@@ -200,24 +200,66 @@ define <vscale x 64 x i8> @fshr_v64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8>
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: sub sp, sp, a2
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vl8r.v v24, (a0)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vsll.vi v16, v8, 1, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vnot.v v8, v24, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vand.vi v8, v8, 7, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vand.vi v16, v24, 7, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsrl.vv v16, v24, v16, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -233,24 +275,66 @@ define <vscale x 64 x i8> @fshl_v64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8>
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: sub sp, sp, a2
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vl8r.v v24, (a0)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v16, v16, 1, v0.t
-; CHECK-NEXT: vnot.v v8, v24, v0.t
-; CHECK-NEXT: vand.vi v8, v8, 7, v0.t
-; CHECK-NEXT: vsrl.vv v8, v16, v8, v0.t
+; CHECK-NEXT: vsrl.vi v8, v16, 1, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vnot.v v16, v24, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vand.vi v16, v16, 7, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsrl.vv v8, v8, v16, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vand.vi v16, v24, 7, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsll.vv v16, v24, v16, v0.t
-; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -266,9 +350,9 @@ define <vscale x 1 x i16> @fshr_v1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16>
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vand.vi v11, v11, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -282,9 +366,9 @@ define <vscale x 1 x i16> @fshl_v1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16>
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vand.vi v11, v11, 15, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -298,9 +382,9 @@ define <vscale x 2 x i16> @fshr_v2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16>
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vand.vi v11, v11, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -314,9 +398,9 @@ define <vscale x 2 x i16> @fshl_v2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16>
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vand.vi v11, v11, 15, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -330,9 +414,9 @@ define <vscale x 4 x i16> @fshr_v4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16>
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vand.vi v11, v11, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -346,9 +430,9 @@ define <vscale x 4 x i16> @fshl_v4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16>
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
; CHECK-NEXT: vnot.v v11, v10, v0.t
+; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vand.vi v11, v11, 15, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
@@ -362,9 +446,9 @@ define <vscale x 8 x i16> @fshr_v8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16>
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v14, v12, v0.t
+; CHECK-NEXT: vand.vi v12, v12, 15, v0.t
; CHECK-NEXT: vand.vi v14, v14, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
-; CHECK-NEXT: vand.vi v12, v12, 15, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
@@ -378,9 +462,9 @@ define <vscale x 8 x i16> @fshl_v8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16>
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t
; CHECK-NEXT: vnot.v v14, v12, v0.t
+; CHECK-NEXT: vand.vi v12, v12, 15, v0.t
; CHECK-NEXT: vand.vi v14, v14, 15, v0.t
; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
-; CHECK-NEXT: vand.vi v12, v12, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
@@ -394,9 +478,9 @@ define <vscale x 16 x i16> @fshr_v16i16(<vscale x 16 x i16> %a, <vscale x 16 x i
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vnot.v v20, v16, v0.t
+; CHECK-NEXT: vand.vi v16, v16, 15, v0.t
; CHECK-NEXT: vand.vi v20, v20, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
-; CHECK-NEXT: vand.vi v16, v16, 15, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
@@ -410,9 +494,9 @@ define <vscale x 16 x i16> @fshl_v16i16(<vscale x 16 x i16> %a, <vscale x 16 x i
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t
; CHECK-NEXT: vnot.v v20, v16, v0.t
+; CHECK-NEXT: vand.vi v16, v16, 15, v0.t
; CHECK-NEXT: vand.vi v20, v20, 15, v0.t
; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
-; CHECK-NEXT: vand.vi v16, v16, 15, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
@@ -426,24 +510,66 @@ define <vscale x 32 x i16> @fshr_v32i16(<vscale x 32 x i16> %a, <vscale x 32 x i
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: sub sp, sp, a2
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vl8re16.v v24, (a0)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vsll.vi v16, v8, 1, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vnot.v v8, v24, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vand.vi v16, v24, 15, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsrl.vv v16, v24, v16, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -459,24 +585,66 @@ define <vscale x 32 x i16> @fshl_v32i16(<vscale x 32 x i16> %a, <vscale x 32 x i
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: sub sp, sp, a2
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vl8re16.v v24, (a0)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v16, v16, 1, v0.t
-; CHECK-NEXT: vnot.v v8, v24, v0.t
-; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
-; CHECK-NEXT: vsrl.vv v8, v16, v8, v0.t
+; CHECK-NEXT: vsrl.vi v8, v16, 1, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vnot.v v16, v24, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vand.vi v16, v16, 15, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsrl.vv v8, v8, v16, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vand.vi v16, v24, 15, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsll.vv v16, v24, v16, v0.t
-; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -491,12 +659,12 @@ define <vscale x 1 x i32> @fshr_v1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 31
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vand.vx v11, v10, a1, v0.t
-; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vnot.v v10, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vnot.v v11, v10, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vand.vx v11, v11, a1, v0.t
+; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 1 x i32> @llvm.vp.fshr.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c, <vscale x 1 x i1> %m, i32 %evl)
@@ -508,12 +676,12 @@ define <vscale x 1 x i32> @fshl_v1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 31
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
-; CHECK-NEXT: vand.vx v11, v10, a1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vnot.v v10, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vnot.v v11, v10, v0.t
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
-; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vand.vx v11, v11, a1, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 1 x i32> @llvm.vp.fshl.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c, <vscale x 1 x i1> %m, i32 %evl)
@@ -525,12 +693,12 @@ define <vscale x 2 x i32> @fshr_v2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 31
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vand.vx v11, v10, a1, v0.t
-; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vnot.v v10, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vnot.v v11, v10, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vand.vx v11, v11, a1, v0.t
+; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 2 x i32> @llvm.vp.fshr.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i1> %m, i32 %evl)
@@ -542,12 +710,12 @@ define <vscale x 2 x i32> @fshl_v2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 31
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vand.vx v11, v10, a1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vnot.v v10, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vnot.v v11, v10, v0.t
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
-; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vand.vx v11, v11, a1, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 2 x i32> @llvm.vp.fshl.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, <vscale x 2 x i1> %m, i32 %evl)
@@ -559,12 +727,12 @@ define <vscale x 4 x i32> @fshr_v4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 31
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vand.vx v14, v12, a1, v0.t
-; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
-; CHECK-NEXT: vnot.v v12, v12, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
+; CHECK-NEXT: vnot.v v14, v12, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
+; CHECK-NEXT: vand.vx v14, v14, a1, v0.t
+; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.vp.fshr.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i1> %m, i32 %evl)
@@ -576,12 +744,12 @@ define <vscale x 4 x i32> @fshl_v4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 31
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
-; CHECK-NEXT: vand.vx v14, v12, a1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
-; CHECK-NEXT: vnot.v v12, v12, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
+; CHECK-NEXT: vnot.v v14, v12, v0.t
; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t
-; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
+; CHECK-NEXT: vand.vx v14, v14, a1, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.vp.fshl.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i1> %m, i32 %evl)
@@ -593,12 +761,12 @@ define <vscale x 8 x i32> @fshr_v8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 31
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
-; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vnot.v v20, v16, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vand.vx v20, v20, a1, v0.t
+; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.vp.fshr.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, <vscale x 8 x i32> %c, <vscale x 8 x i1> %m, i32 %evl)
@@ -610,12 +778,12 @@ define <vscale x 8 x i32> @fshl_v8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 31
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
-; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vnot.v v20, v16, v0.t
; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t
-; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vand.vx v20, v20, a1, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.vp.fshl.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, <vscale x 8 x i32> %c, <vscale x 8 x i1> %m, i32 %evl)
@@ -628,25 +796,62 @@ define <vscale x 16 x i32> @fshr_v16i32(<vscale x 16 x i32> %a, <vscale x 16 x i
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: sub sp, sp, a2
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vl8re32.v v24, (a0)
+; CHECK-NEXT: vl8re32.v v8, (a0)
; CHECK-NEXT: li a0, 31
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
-; CHECK-NEXT: vsrl.vv v16, v16, v8, v0.t
-; CHECK-NEXT: vnot.v v8, v24, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsll.vi v24, v24, 1, v0.t
-; CHECK-NEXT: vsll.vv v8, v24, v8, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vand.vx v24, v8, a0, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsrl.vv v16, v16, v24, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsll.vi v24, v24, 1, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsll.vv v8, v24, v8, v0.t
+; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -662,26 +867,63 @@ define <vscale x 16 x i32> @fshl_v16i32(<vscale x 16 x i32> %a, <vscale x 16 x i
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: sub sp, sp, a2
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vmv8r.v v16, v8
-; CHECK-NEXT: vl8re32.v v24, (a0)
+; CHECK-NEXT: vl8re32.v v8, (a0)
; CHECK-NEXT: li a0, 31
-; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
-; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t
-; CHECK-NEXT: vnot.v v16, v24, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vand.vx v24, v8, a0, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsll.vv v16, v16, v24, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsrl.vi v24, v24, 1, v0.t
-; CHECK-NEXT: vsrl.vv v16, v24, v16, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsrl.vv v8, v24, v8, v0.t
+; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -696,12 +938,12 @@ define <vscale x 1 x i64> @fshr_v1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 63
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vand.vx v11, v10, a1, v0.t
-; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
-; CHECK-NEXT: vnot.v v10, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vnot.v v11, v10, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vand.vx v11, v11, a1, v0.t
+; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 1 x i64> @llvm.vp.fshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, <vscale x 1 x i64> %c, <vscale x 1 x i1> %m, i32 %evl)
@@ -713,12 +955,12 @@ define <vscale x 1 x i64> @fshl_v1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 63
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; CHECK-NEXT: vand.vx v11, v10, a1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
-; CHECK-NEXT: vnot.v v10, v10, v0.t
-; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vnot.v v11, v10, v0.t
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
-; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
+; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
+; CHECK-NEXT: vand.vx v11, v11, a1, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
+; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 1 x i64> @llvm.vp.fshl.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b, <vscale x 1 x i64> %c, <vscale x 1 x i1> %m, i32 %evl)
@@ -730,12 +972,12 @@ define <vscale x 2 x i64> @fshr_v2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 63
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vand.vx v14, v12, a1, v0.t
-; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
-; CHECK-NEXT: vnot.v v12, v12, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
+; CHECK-NEXT: vnot.v v14, v12, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
+; CHECK-NEXT: vand.vx v14, v14, a1, v0.t
+; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.vp.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i1> %m, i32 %evl)
@@ -747,12 +989,12 @@ define <vscale x 2 x i64> @fshl_v2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 63
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vand.vx v14, v12, a1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v14, v0.t
-; CHECK-NEXT: vnot.v v12, v12, v0.t
-; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
+; CHECK-NEXT: vnot.v v14, v12, v0.t
; CHECK-NEXT: vsrl.vi v10, v10, 1, v0.t
-; CHECK-NEXT: vsrl.vv v10, v10, v12, v0.t
+; CHECK-NEXT: vand.vx v12, v12, a1, v0.t
+; CHECK-NEXT: vand.vx v14, v14, a1, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t
+; CHECK-NEXT: vsrl.vv v10, v10, v14, v0.t
; CHECK-NEXT: vor.vv v8, v8, v10, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.vp.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i1> %m, i32 %evl)
@@ -764,12 +1006,12 @@ define <vscale x 4 x i64> @fshr_v4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 63
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
-; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vnot.v v20, v16, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vand.vx v20, v20, a1, v0.t
+; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 4 x i64> @llvm.vp.fshr.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c, <vscale x 4 x i1> %m, i32 %evl)
@@ -781,12 +1023,12 @@ define <vscale x 4 x i64> @fshl_v4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64>
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 63
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
-; CHECK-NEXT: vand.vx v20, v16, a1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v20, v0.t
-; CHECK-NEXT: vnot.v v16, v16, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vnot.v v20, v16, v0.t
; CHECK-NEXT: vsrl.vi v12, v12, 1, v0.t
-; CHECK-NEXT: vsrl.vv v12, v12, v16, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vand.vx v20, v20, a1, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vsrl.vv v12, v12, v20, v0.t
; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 4 x i64> @llvm.vp.fshl.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c, <vscale x 4 x i1> %m, i32 %evl)
@@ -799,25 +1041,62 @@ define <vscale x 7 x i64> @fshr_v7i64(<vscale x 7 x i64> %a, <vscale x 7 x i64>
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: sub sp, sp, a2
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vl8re64.v v24, (a0)
+; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: li a0, 63
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
-; CHECK-NEXT: vsrl.vv v16, v16, v8, v0.t
-; CHECK-NEXT: vnot.v v8, v24, v0.t
+; CHECK-NEXT: vand.vx v24, v8, a0, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsrl.vv v16, v16, v24, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsll.vi v24, v24, 1, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsll.vv v8, v24, v8, v0.t
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -833,26 +1112,63 @@ define <vscale x 7 x i64> @fshl_v7i64(<vscale x 7 x i64> %a, <vscale x 7 x i64>
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: sub sp, sp, a2
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vmv8r.v v16, v8
-; CHECK-NEXT: vl8re64.v v24, (a0)
+; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: li a0, 63
-; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
-; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t
-; CHECK-NEXT: vnot.v v16, v24, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vand.vx v24, v8, a0, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsll.vv v16, v16, v24, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsrl.vi v24, v24, 1, v0.t
-; CHECK-NEXT: vsrl.vv v16, v24, v16, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsrl.vv v8, v24, v8, v0.t
+; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -868,25 +1184,62 @@ define <vscale x 8 x i64> @fshr_v8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64>
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: sub sp, sp, a2
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vl8re64.v v24, (a0)
+; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: li a0, 63
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
-; CHECK-NEXT: vsrl.vv v16, v16, v8, v0.t
-; CHECK-NEXT: vnot.v v8, v24, v0.t
+; CHECK-NEXT: vand.vx v24, v8, a0, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsrl.vv v16, v16, v24, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsll.vi v24, v24, 1, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsll.vv v8, v24, v8, v0.t
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -902,26 +1255,63 @@ define <vscale x 8 x i64> @fshl_v8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64>
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: sub sp, sp, a2
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x09, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 9 * vlenb
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vmv8r.v v16, v8
-; CHECK-NEXT: vl8re64.v v24, (a0)
+; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: li a0, 63
-; CHECK-NEXT: vand.vx v8, v24, a0, v0.t
-; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t
-; CHECK-NEXT: vnot.v v16, v24, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vand.vx v24, v8, a0, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsll.vv v16, v16, v24, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsrl.vi v24, v24, 1, v0.t
-; CHECK-NEXT: vsrl.vv v16, v24, v16, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsrl.vv v8, v24, v8, v0.t
+; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -937,15 +1327,17 @@ define <vscale x 16 x i64> @fshr_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 5
+; CHECK-NEXT: li a3, 41
+; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: li a3, 40
+; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 24
@@ -953,79 +1345,152 @@ define <vscale x 16 x i64> @fshr_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a3, a1, 3
-; CHECK-NEXT: sub a5, a4, a1
-; CHECK-NEXT: add a6, a2, a3
-; CHECK-NEXT: vl8re64.v v8, (a6)
-; CHECK-NEXT: sltu a6, a4, a5
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a5, a3, 3
+; CHECK-NEXT: sub a1, a4, a3
+; CHECK-NEXT: add a6, a2, a5
+; CHECK-NEXT: vl8re64.v v24, (a6)
+; CHECK-NEXT: sltu a6, a4, a1
; CHECK-NEXT: addi a6, a6, -1
-; CHECK-NEXT: and a5, a6, a5
-; CHECK-NEXT: srli a6, a1, 3
-; CHECK-NEXT: add a3, a0, a3
-; CHECK-NEXT: vl8re64.v v16, (a3)
-; CHECK-NEXT: vslidedown.vx v0, v0, a6
-; CHECK-NEXT: li a3, 63
-; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma
-; CHECK-NEXT: vand.vx v24, v8, a3, v0.t
-; CHECK-NEXT: vsrl.vv v16, v16, v24, v0.t
-; CHECK-NEXT: addi a5, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vnot.v v8, v8, v0.t
-; CHECK-NEXT: vand.vx v16, v8, a3, v0.t
-; CHECK-NEXT: vl8re64.v v8, (a0)
+; CHECK-NEXT: and a6, a6, a1
+; CHECK-NEXT: li a1, 63
+; CHECK-NEXT: add a5, a0, a5
+; CHECK-NEXT: vl8re64.v v16, (a5)
+; CHECK-NEXT: srli a5, a3, 3
+; CHECK-NEXT: csrr a7, vlenb
+; CHECK-NEXT: li t0, 40
+; CHECK-NEXT: mul a7, a7, t0
+; CHECK-NEXT: add a7, sp, a7
+; CHECK-NEXT: addi a7, a7, 16
+; CHECK-NEXT: vl1r.v v8, (a7) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vx v8, v8, a5
+; CHECK-NEXT: csrr a5, vlenb
+; CHECK-NEXT: slli a5, a5, 5
+; CHECK-NEXT: add a5, sp, a5
+; CHECK-NEXT: addi a5, a5, 16
+; CHECK-NEXT: vs1r.v v8, (a5) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: csrr a5, vlenb
+; CHECK-NEXT: slli a5, a5, 5
+; CHECK-NEXT: add a5, sp, a5
+; CHECK-NEXT: addi a5, a5, 16
+; CHECK-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma
+; CHECK-NEXT: vand.vx v8, v24, a1, v0.t
+; CHECK-NEXT: csrr a5, vlenb
+; CHECK-NEXT: slli a5, a5, 5
+; CHECK-NEXT: add a5, sp, a5
+; CHECK-NEXT: addi a5, a5, 16
+; CHECK-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsrl.vv v8, v16, v8, v0.t
+; CHECK-NEXT: csrr a5, vlenb
+; CHECK-NEXT: slli a5, a5, 3
+; CHECK-NEXT: add a5, sp, a5
+; CHECK-NEXT: addi a5, a5, 16
+; CHECK-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a5, vlenb
+; CHECK-NEXT: slli a5, a5, 5
+; CHECK-NEXT: add a5, sp, a5
+; CHECK-NEXT: addi a5, a5, 16
+; CHECK-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vnot.v v24, v24, v0.t
+; CHECK-NEXT: vand.vx v8, v24, a1, v0.t
+; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vl8re64.v v24, (a2)
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsll.vi v16, v16, 1, v0.t
+; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
-; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: bltu a4, a1, .LBB46_2
+; CHECK-NEXT: bltu a4, a3, .LBB46_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a4, a1
+; CHECK-NEXT: mv a4, a3
; CHECK-NEXT: .LBB46_2:
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a2, 24
+; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a2, 40
+; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; CHECK-NEXT: vand.vx v8, v24, a3, v0.t
+; CHECK-NEXT: vsll.vi v16, v8, 1, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: li a2, 40
+; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsrl.vv v16, v16, v8, v0.t
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: vnot.v v24, v24, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a3, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 24
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: li a2, 40
+; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v24, v0.t
-; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a2, 40
+; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsll.vv v16, v16, v24, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a2, 40
+; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vand.vx v24, v8, a1, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 40
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsrl.vv v24, v8, v24, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 40
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vor.vv v8, v16, v24, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 41
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -1041,37 +1506,71 @@ define <vscale x 16 x i64> @fshl_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a3, 24
-; CHECK-NEXT: mul a1, a1, a3
+; CHECK-NEXT: slli a3, a1, 5
+; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a5, a3, 3
+; CHECK-NEXT: srli a1, a3, 3
+; CHECK-NEXT: sub a6, a4, a3
+; CHECK-NEXT: csrr a7, vlenb
+; CHECK-NEXT: slli a7, a7, 5
+; CHECK-NEXT: add a7, sp, a7
+; CHECK-NEXT: addi a7, a7, 16
+; CHECK-NEXT: vs1r.v v0, (a7) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vx v8, v0, a1
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a5, a1, 3
-; CHECK-NEXT: srli a3, a1, 3
-; CHECK-NEXT: sub a6, a4, a1
-; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: add a3, a2, a5
-; CHECK-NEXT: vl8re64.v v8, (a3)
-; CHECK-NEXT: sltu a3, a4, a6
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a6, a3, a6
-; CHECK-NEXT: li a3, 63
+; CHECK-NEXT: li a7, 24
+; CHECK-NEXT: mul a1, a1, a7
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: add a1, a2, a5
+; CHECK-NEXT: vl8re64.v v8, (a1)
+; CHECK-NEXT: sltu a1, a4, a6
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a6, a1, a6
+; CHECK-NEXT: li a1, 63
+; CHECK-NEXT: csrr a7, vlenb
+; CHECK-NEXT: li t0, 24
+; CHECK-NEXT: mul a7, a7, t0
+; CHECK-NEXT: add a7, sp, a7
+; CHECK-NEXT: addi a7, a7, 16
+; CHECK-NEXT: vl1r.v v0, (a7) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma
-; CHECK-NEXT: vand.vx v24, v8, a3, v0.t
+; CHECK-NEXT: vand.vx v24, v8, a1, v0.t
+; CHECK-NEXT: csrr a6, vlenb
+; CHECK-NEXT: li a7, 24
+; CHECK-NEXT: mul a6, a6, a7
+; CHECK-NEXT: add a6, sp, a6
+; CHECK-NEXT: addi a6, a6, 16
+; CHECK-NEXT: vl1r.v v0, (a6) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsll.vv v16, v16, v24, v0.t
; CHECK-NEXT: addi a6, sp, 16
; CHECK-NEXT: vs8r.v v16, (a6) # vscale x 64-byte Folded Spill
; CHECK-NEXT: add a5, a0, a5
-; CHECK-NEXT: vnot.v v8, v8, v0.t
+; CHECK-NEXT: csrr a6, vlenb
+; CHECK-NEXT: li a7, 24
+; CHECK-NEXT: mul a6, a6, a7
+; CHECK-NEXT: add a6, sp, a6
+; CHECK-NEXT: addi a6, a6, 16
+; CHECK-NEXT: vl1r.v v0, (a6) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vnot.v v24, v8, v0.t
; CHECK-NEXT: vl8re64.v v16, (a5)
-; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
+; CHECK-NEXT: csrr a5, vlenb
+; CHECK-NEXT: li a6, 24
+; CHECK-NEXT: mul a5, a5, a6
+; CHECK-NEXT: add a5, sp, a5
+; CHECK-NEXT: addi a5, a5, 16
+; CHECK-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vand.vx v8, v24, a1, v0.t
; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
@@ -1079,40 +1578,102 @@ define <vscale x 16 x i64> @fshl_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vl8re64.v v24, (a2)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a2, 24
+; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsrl.vi v16, v16, 1, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a2, 24
+; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsrl.vv v8, v16, v8, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a2, 24
+; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a2, 24
+; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: bltu a4, a1, .LBB47_2
+; CHECK-NEXT: bltu a4, a3, .LBB47_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a4, a1
+; CHECK-NEXT: mv a4, a3
; CHECK-NEXT: .LBB47_2:
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; CHECK-NEXT: vand.vx v8, v24, a3, v0.t
+; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
+; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsll.vv v16, v16, v8, v0.t
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vnot.v v24, v24, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a3, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsrl.vv v16, v16, v24, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vand.vx v24, v8, a1, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsrl.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsrl.vv v8, v8, v24, v0.t
-; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsll.vv v24, v8, v24, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vor.vv v8, v24, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24
; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 5
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -1131,11 +1692,11 @@ define <vscale x 1 x i9> @fshr_v1i9(<vscale x 1 x i9> %a, <vscale x 1 x i9> %b,
; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
; CHECK-NEXT: li a0, 9
; CHECK-NEXT: vremu.vx v10, v10, a0, v0.t
+; CHECK-NEXT: vsll.vi v9, v9, 7, v0.t
; CHECK-NEXT: vadd.vi v10, v10, 7, v0.t
; CHECK-NEXT: vand.vi v11, v10, 15, v0.t
-; CHECK-NEXT: vsll.vi v9, v9, 7, v0.t
-; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
; CHECK-NEXT: vnot.v v10, v10, v0.t
+; CHECK-NEXT: vsrl.vv v9, v9, v11, v0.t
; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
@@ -1153,11 +1714,11 @@ define <vscale x 1 x i9> @fshl_v1i9(<vscale x 1 x i9> %a, <vscale x 1 x i9> %b,
; CHECK-NEXT: vand.vx v10, v10, a1, v0.t
; CHECK-NEXT: li a0, 9
; CHECK-NEXT: vremu.vx v10, v10, a0, v0.t
+; CHECK-NEXT: vsll.vi v9, v9, 7, v0.t
; CHECK-NEXT: vand.vi v11, v10, 15, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
; CHECK-NEXT: vnot.v v10, v10, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v11, v0.t
; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
-; CHECK-NEXT: vsll.vi v9, v9, 7, v0.t
; CHECK-NEXT: vsrl.vi v9, v9, 1, v0.t
; CHECK-NEXT: vsrl.vv v9, v9, v10, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
@@ -1172,11 +1733,11 @@ define <vscale x 1 x i8> @fshr_v1i4(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b,
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: li a0, 4
+; CHECK-NEXT: vremu.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vi v9, v9, 15, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vremu.vx v9, v10, a0, v0.t
-; CHECK-NEXT: vsrl.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsrl.vv v8, v8, v10, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret
%trunca = call <vscale x 1 x i4> @llvm.vp.trunc.nxv1i4.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i1> %m, i32 zeroext %evl)
@@ -1193,11 +1754,11 @@ define <vscale x 1 x i8> @fshl_v1i4(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b,
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vand.vi v10, v10, 15, v0.t
; CHECK-NEXT: li a0, 4
+; CHECK-NEXT: vremu.vx v10, v10, a0, v0.t
; CHECK-NEXT: vand.vi v9, v9, 15, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vremu.vx v9, v10, a0, v0.t
-; CHECK-NEXT: vsll.vv v8, v8, v9, v0.t
+; CHECK-NEXT: vsll.vv v8, v8, v10, v0.t
; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t
; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
index adeee2bd82b57..fd9e77b94fb15 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
@@ -137,8 +137,8 @@ define <vscale x 1 x float> @trunc_nxv1f32(<vscale x 1 x float> %x) strictfp {
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
@@ -157,8 +157,8 @@ define <vscale x 2 x float> @trunc_nxv2f32(<vscale x 2 x float> %x) strictfp {
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vfabs.v v9, v8
+; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
@@ -177,8 +177,8 @@ define <vscale x 4 x float> @trunc_nxv4f32(<vscale x 4 x float> %x) strictfp {
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vfabs.v v10, v8
+; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
@@ -197,8 +197,8 @@ define <vscale x 8 x float> @trunc_nxv8f32(<vscale x 8 x float> %x) strictfp {
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vfabs.v v12, v8
+; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
@@ -217,8 +217,8 @@ define <vscale x 16 x float> @trunc_nxv16f32(<vscale x 16 x float> %x) strictfp
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vfabs.v v16, v8
+; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8, v0.t
@@ -233,10 +233,10 @@ define <vscale x 16 x float> @trunc_nxv16f32(<vscale x 16 x float> %x) strictfp
define <vscale x 1 x double> @trunc_nxv1f64(<vscale x 1 x double> %x) strictfp {
; RV32-LABEL: trunc_nxv1f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: lui a0, %hi(.LCPI11_0)
; RV32-NEXT: fld fa5, %lo(.LCPI11_0)(a0)
+; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v9, v8
; RV32-NEXT: vmflt.vf v0, v9, fa5
@@ -270,10 +270,10 @@ define <vscale x 1 x double> @trunc_nxv1f64(<vscale x 1 x double> %x) strictfp {
define <vscale x 2 x double> @trunc_nxv2f64(<vscale x 2 x double> %x) strictfp {
; RV32-LABEL: trunc_nxv2f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
+; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
+; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v10, v8
; RV32-NEXT: vmflt.vf v0, v10, fa5
@@ -307,10 +307,10 @@ define <vscale x 2 x double> @trunc_nxv2f64(<vscale x 2 x double> %x) strictfp {
define <vscale x 4 x double> @trunc_nxv4f64(<vscale x 4 x double> %x) strictfp {
; RV32-LABEL: trunc_nxv4f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
+; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
+; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v12, v8
; RV32-NEXT: vmflt.vf v0, v12, fa5
@@ -344,10 +344,10 @@ define <vscale x 4 x double> @trunc_nxv4f64(<vscale x 4 x double> %x) strictfp {
define <vscale x 8 x double> @trunc_nxv8f64(<vscale x 8 x double> %x) strictfp {
; RV32-LABEL: trunc_nxv8f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: lui a0, %hi(.LCPI14_0)
; RV32-NEXT: fld fa5, %lo(.LCPI14_0)(a0)
+; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV32-NEXT: vmfne.vv v0, v8, v8
; RV32-NEXT: vfadd.vv v8, v8, v8, v0.t
; RV32-NEXT: vfabs.v v16, v8
; RV32-NEXT: vmflt.vf v0, v16, fa5
diff --git a/llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll b/llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
index 6413b914b6440..4654b2e223edf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
@@ -334,8 +334,8 @@ define <vscale x 1 x i64> @ceil_nxv1f16_to_si64(<vscale x 1 x half> %x) {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: slli a0, a0, 10
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -392,8 +392,8 @@ define <vscale x 1 x i64> @ceil_nxv1f16_to_ui64(<vscale x 1 x half> %x) {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: slli a0, a0, 10
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -536,8 +536,8 @@ define <vscale x 4 x i64> @ceil_nxv4f16_to_si64(<vscale x 4 x half> %x) {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: slli a0, a0, 10
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -594,8 +594,8 @@ define <vscale x 4 x i64> @ceil_nxv4f16_to_ui64(<vscale x 4 x half> %x) {
; CHECK-NEXT: li a0, 25
; CHECK-NEXT: slli a0, a0, 10
; CHECK-NEXT: fmv.h.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 3
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
index 962fa729722cd..0d6d09e8dfa08 100644
--- a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
@@ -432,17 +432,17 @@ define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_0(<vscale x 4 x i1> %v, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
+; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
-; CHECK-NEXT: vmv.v.v v9, v8
+; CHECK-NEXT: vmv.v.v v10, v9
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmsne.vi v0, v9, 0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: ret
%vec = call <vscale x 4 x i1> @llvm.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv, i64 0)
ret <vscale x 4 x i1> %vec
@@ -454,18 +454,18 @@ define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_2(<vscale x 4 x i1> %v, <vscale x
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
+; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma
-; CHECK-NEXT: vslideup.vx v9, v8, a0
+; CHECK-NEXT: vslideup.vx v10, v9, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmsne.vi v0, v9, 0
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: ret
%vec = call <vscale x 4 x i1> @llvm.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv, i64 2)
ret <vscale x 4 x i1> %vec
diff --git a/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
index c0a794afac3ae..d3c3349919ec9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
@@ -51,11 +51,11 @@ define <vscale x 8 x i64> @llrint_nxv8i64_nxv8f32(<vscale x 8 x float> %x, <vsca
define <vscale x 16 x i64> @llrint_nxv16i64_nxv16f32(<vscale x 16 x float> %x, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: llrint_nxv16i64_nxv16f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
diff --git a/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
index c09df1a60d2ae..e672a3a554962 100644
--- a/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
@@ -113,11 +113,11 @@ define <vscale x 16 x iXLen> @lrint_nxv16f32(<vscale x 16 x float> %x, <vscale x
;
; RV64-i64-LABEL: lrint_nxv16f32:
; RV64-i64: # %bb.0:
-; RV64-i64-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; RV64-i64-NEXT: vmv1r.v v24, v0
; RV64-i64-NEXT: csrr a1, vlenb
; RV64-i64-NEXT: srli a2, a1, 3
; RV64-i64-NEXT: sub a3, a0, a1
+; RV64-i64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; RV64-i64-NEXT: vmv1r.v v24, v0
; RV64-i64-NEXT: vslidedown.vx v0, v0, a2
; RV64-i64-NEXT: sltu a2, a0, a3
; RV64-i64-NEXT: addi a2, a2, -1
diff --git a/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir b/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
index ba5a05e89c506..60d7b50be053e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
@@ -17,9 +17,9 @@ body: |
; CHECK: liveins: $v0, $v1, $v2, $v3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 192 /* e8, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
- ; CHECK-NEXT: renamable $v8 = PseudoVMERGE_VIM_M1 undef renamable $v8, killed renamable $v2, 1, $v0, 1, 3 /* e8 */, implicit $vl, implicit $vtype
- ; CHECK-NEXT: renamable $v0 = COPY $v1, implicit $vtype
- ; CHECK-NEXT: renamable $v9 = PseudoVMERGE_VIM_M1 undef renamable $v9, killed renamable $v3, 1, $v0, 1, 3 /* e8 */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: renamable $v8 = PseudoVMERGE_VIM_M1 undef renamable $v8, killed renamable $v2, 1, killed renamable $v0, 1, 3 /* e8 */, implicit $vl, implicit $vtype
+ ; CHECK-NEXT: renamable $v0 = COPY killed renamable $v1, implicit $vtype
+ ; CHECK-NEXT: renamable $v9 = PseudoVMERGE_VIM_M1 undef renamable $v9, killed renamable $v3, 1, killed renamable $v0, 1, 3 /* e8 */, implicit $vl, implicit $vtype
; CHECK-NEXT: renamable $v0 = PseudoVADD_VV_M1 undef renamable $v0, killed renamable $v8, killed renamable $v9, 1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: PseudoRET implicit $v0
%0:vr = COPY $v0
diff --git a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
index ae3b9db74080c..75b8aa515a717 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
@@ -1182,15 +1182,16 @@ define <vscale x 8 x i64> @mgather_baseidx_nxv8i64(ptr %base, <vscale x 8 x i64>
define void @mgather_nxv16i64(<vscale x 8 x ptr> %ptrs0, <vscale x 8 x ptr> %ptrs1, <vscale x 16 x i1> %m, <vscale x 8 x i64> %passthru0, <vscale x 8 x i64> %passthru1, ptr %out) {
; RV32-LABEL: mgather_nxv16i64:
; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
+; RV32-NEXT: vmv1r.v v7, v0
; RV32-NEXT: vl8re64.v v24, (a0)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
-; RV32-NEXT: vluxei32.v v16, (zero), v8, v0.t
; RV32-NEXT: srli a2, a0, 3
-; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vx v0, v0, a2
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV32-NEXT: vluxei32.v v24, (zero), v12, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vluxei32.v v16, (zero), v8, v0.t
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: vs8r.v v24, (a0)
@@ -1199,20 +1200,37 @@ define void @mgather_nxv16i64(<vscale x 8 x ptr> %ptrs0, <vscale x 8 x ptr> %ptr
;
; RV64-LABEL: mgather_nxv16i64:
; RV64: # %bb.0:
-; RV64-NEXT: vl8re64.v v24, (a0)
-; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; RV64-NEXT: vluxei64.v v24, (zero), v8, v0.t
-; RV64-NEXT: vl8re64.v v8, (a1)
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: srli a1, a0, 3
+; RV64-NEXT: addi sp, sp, -16
+; RV64-NEXT: .cfi_def_cfa_offset 16
+; RV64-NEXT: csrr a3, vlenb
+; RV64-NEXT: slli a3, a3, 3
+; RV64-NEXT: sub sp, sp, a3
+; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v0, v0, a1
-; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; RV64-NEXT: vmv1r.v v7, v0
+; RV64-NEXT: addi a3, sp, 16
+; RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vl8re64.v v24, (a1)
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: vl8re64.v v8, (a0)
+; RV64-NEXT: srli a0, a1, 3
+; RV64-NEXT: vslidedown.vx v0, v0, a0
+; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; RV64-NEXT: vluxei64.v v24, (zero), v16, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: vluxei64.v v8, (zero), v16, v0.t
+; RV64-NEXT: slli a1, a1, 3
+; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: vs8r.v v24, (a1)
+; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a0, a2, a0
-; RV64-NEXT: vs8r.v v8, (a0)
-; RV64-NEXT: vs8r.v v24, (a2)
+; RV64-NEXT: add sp, sp, a0
+; RV64-NEXT: .cfi_def_cfa sp, 16
+; RV64-NEXT: addi sp, sp, 16
+; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
%p0 = call <vscale x 16 x ptr> @llvm.vector.insert.nxv8p0.nxv16p0(<vscale x 16 x ptr> poison, <vscale x 8 x ptr> %ptrs0, i64 0)
%p1 = call <vscale x 16 x ptr> @llvm.vector.insert.nxv8p0.nxv16p0(<vscale x 16 x ptr> %p0, <vscale x 8 x ptr> %ptrs1, i64 8)
@@ -2252,30 +2270,30 @@ define <vscale x 32 x i8> @mgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8>
; RV64-LABEL: mgather_baseidx_nxv32i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
-; RV64-NEXT: vmv1r.v v16, v0
-; RV64-NEXT: vsext.vf8 v24, v8
+; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; RV64-NEXT: vluxei64.v v12, (a0), v24, v0.t
+; RV64-NEXT: vluxei64.v v12, (a0), v16, v0.t
+; RV64-NEXT: vmv1r.v v8, v0
+; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV64-NEXT: vsext.vf8 v16, v9
; RV64-NEXT: srli a2, a1, 3
; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vx v0, v0, a2
-; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, ma
-; RV64-NEXT: vsext.vf8 v24, v9
-; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; RV64-NEXT: vluxei64.v v13, (a0), v24, v0.t
+; RV64-NEXT: vsetvli a3, zero, e8, m1, ta, mu
+; RV64-NEXT: vluxei64.v v13, (a0), v16, v0.t
; RV64-NEXT: srli a1, a1, 2
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vslidedown.vx v8, v16, a1
+; RV64-NEXT: vslidedown.vx v9, v8, a1
; RV64-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v0, v8, a2
+; RV64-NEXT: vslidedown.vx v0, v9, a2
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v11
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v15, (a0), v16, v0.t
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v10
-; RV64-NEXT: vmv1r.v v0, v8
+; RV64-NEXT: vmv1r.v v0, v9
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v14, (a0), v16, v0.t
; RV64-NEXT: vmv4r.v v8, v12
diff --git a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
index 5eb6553aaba79..639a91535f191 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
@@ -1835,35 +1835,25 @@ define void @mscatter_nxv16f64(<vscale x 8 x double> %val0, <vscale x 8 x double
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: slli a2, a2, 4
+; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: sub sp, sp, a2
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV64-NEXT: addi a2, sp, 16
-; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vl8re64.v v8, (a0)
-; RV64-NEXT: vl8re64.v v24, (a1)
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vl8re64.v v24, (a0)
+; RV64-NEXT: vl8re64.v v16, (a1)
; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; RV64-NEXT: vsoxei64.v v24, (zero), v8, v0.t
+; RV64-NEXT: vsoxei64.v v8, (zero), v24, v0.t
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: srli a0, a0, 3
; RV64-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vx v0, v0, a0
-; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 3
-; RV64-NEXT: add a0, sp, a0
-; RV64-NEXT: addi a0, a0, 16
+; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; RV64-NEXT: vsoxei64.v v16, (zero), v8, v0.t
+; RV64-NEXT: vsoxei64.v v8, (zero), v16, v0.t
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: slli a0, a0, 4
+; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 16
; RV64-NEXT: addi sp, sp, 16
@@ -1903,10 +1893,10 @@ define void @mscatter_baseidx_nxv16i8_nxv16f64(<vscale x 8 x double> %val0, <vsc
; RV64-NEXT: vsoxei64.v v8, (a0), v24, v0.t
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: srli a1, a1, 3
-; RV64-NEXT: vsext.vf8 v8, v7
; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vx v0, v0, a1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
+; RV64-NEXT: vsext.vf8 v8, v7
; RV64-NEXT: vsll.vi v8, v8, 3
; RV64-NEXT: vsoxei64.v v16, (a0), v8, v0.t
; RV64-NEXT: ret
@@ -1943,10 +1933,10 @@ define void @mscatter_baseidx_nxv16i16_nxv16f64(<vscale x 8 x double> %val0, <vs
; RV64-NEXT: vsoxei64.v v8, (a0), v24, v0.t
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: srli a1, a1, 3
-; RV64-NEXT: vsext.vf4 v8, v6
; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vx v0, v0, a1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
+; RV64-NEXT: vsext.vf4 v8, v6
; RV64-NEXT: vsll.vi v8, v8, 3
; RV64-NEXT: vsoxei64.v v16, (a0), v8, v0.t
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll b/llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll
index 11305d9efbea1..b85b1163e0726 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/mutate-prior-vsetvli-avl.ll
@@ -17,9 +17,9 @@ define dso_local void @test(ptr nocapture noundef %var_99) {
; CHECK-NEXT: csrwi vxrm, 0
; CHECK-NEXT: vmul.vx v16, v8, a1
; CHECK-NEXT: vmv.x.s a1, v16
+; CHECK-NEXT: vssra.vv v12, v12, v8
; CHECK-NEXT: vmsleu.vx v0, v8, a1
-; CHECK-NEXT: vssra.vv v8, v12, v8
-; CHECK-NEXT: vmerge.vvm v8, v8, v8, v0
+; CHECK-NEXT: vmerge.vvm v8, v12, v12, v0
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
index 3a4591d47e5e4..f7b68ce1f64b8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
@@ -16,25 +16,23 @@ define <vscale x 1 x bfloat> @vp_nearbyint_nxv1bf16(<vscale x 1 x bfloat> %va, <
; CHECK-LABEL: vp_nearbyint_nxv1bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfabs.v v11, v10, v0.t
+; CHECK-NEXT: vfabs.v v8, v9, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: frflags a0
-; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t
-; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
; CHECK-NEXT: fsflags a0
; CHECK-NEXT: ret
%v = call <vscale x 1 x bfloat> @llvm.vp.nearbyint.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 %evl)
@@ -68,25 +66,23 @@ define <vscale x 2 x bfloat> @vp_nearbyint_nxv2bf16(<vscale x 2 x bfloat> %va, <
; CHECK-LABEL: vp_nearbyint_nxv2bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfabs.v v11, v10, v0.t
+; CHECK-NEXT: vfabs.v v8, v9, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: frflags a0
-; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t
-; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
; CHECK-NEXT: fsflags a0
; CHECK-NEXT: ret
%v = call <vscale x 2 x bfloat> @llvm.vp.nearbyint.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 %evl)
@@ -123,20 +119,20 @@ define <vscale x 4 x bfloat> @vp_nearbyint_nxv4bf16(<vscale x 4 x bfloat> %va, <
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v8, v10, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v13, v8, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: frflags a0
-; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
; CHECK-NEXT: fsflags a0
@@ -175,20 +171,20 @@ define <vscale x 8 x bfloat> @vp_nearbyint_nxv8bf16(<vscale x 8 x bfloat> %va, <
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v17, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfabs.v v8, v12, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v17, v8, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v17, v0
; CHECK-NEXT: frflags a0
-; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
; CHECK-NEXT: fsflags a0
@@ -227,20 +223,20 @@ define <vscale x 16 x bfloat> @vp_nearbyint_nxv16bf16(<vscale x 16 x bfloat> %va
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v8, v16, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v24, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: frflags a0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vfsgnj.vv v16, v8, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: fsflags a0
@@ -285,49 +281,49 @@ define <vscale x 32 x bfloat> @vp_nearbyint_nxv32bf16(<vscale x 32 x bfloat> %va
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vslidedown.vx v6, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: vmv1r.v v5, v6
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v5, v16, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: frflags a2
-; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: fsflags a2
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB10_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB10_2:
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t
-; CHECK-NEXT: vmv1r.v v8, v7
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v16, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: frflags a0
-; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: fsflags a0
; CHECK-NEXT: ret
%v = call <vscale x 32 x bfloat> @llvm.vp.nearbyint.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 %evl)
@@ -348,27 +344,27 @@ define <vscale x 32 x bfloat> @vp_nearbyint_nxv32bf16_unmasked(<vscale x 32 x bf
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v7, v16, a2
; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: vmv1r.v v6, v7
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v6, v16, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: frflags a2
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: fsflags a2
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB11_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -413,25 +409,23 @@ define <vscale x 1 x half> @vp_nearbyint_nxv1f16(<vscale x 1 x half> %va, <vscal
; ZVFHMIN-LABEL: vp_nearbyint_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: frflags a0
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: fsflags a0
; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x half> @llvm.vp.nearbyint.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 %evl)
@@ -499,25 +493,23 @@ define <vscale x 2 x half> @vp_nearbyint_nxv2f16(<vscale x 2 x half> %va, <vscal
; ZVFHMIN-LABEL: vp_nearbyint_nxv2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: frflags a0
-; ZVFHMIN-NEXT: vmv.v.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: fsflags a0
; ZVFHMIN-NEXT: ret
%v = call <vscale x 2 x half> @llvm.vp.nearbyint.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)
@@ -588,20 +580,20 @@ define <vscale x 4 x half> @vp_nearbyint_nxv4f16(<vscale x 4 x half> %va, <vscal
; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v13, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: frflags a0
-; ZVFHMIN-NEXT: vmv1r.v v0, v13
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
+; ZVFHMIN-NEXT: vmv1r.v v0, v13
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: fsflags a0
@@ -676,20 +668,20 @@ define <vscale x 8 x half> @vp_nearbyint_nxv8f16(<vscale x 8 x half> %va, <vscal
; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: frflags a0
-; ZVFHMIN-NEXT: vmv1r.v v0, v17
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vmv1r.v v0, v17
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: fsflags a0
@@ -764,20 +756,20 @@ define <vscale x 16 x half> @vp_nearbyint_nxv16f16(<vscale x 16 x half> %va, <vs
; ZVFHMIN-NEXT: vmv1r.v v24, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v25, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v16, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v25, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v24, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v25, v0
; ZVFHMIN-NEXT: frflags a0
-; ZVFHMIN-NEXT: vmv1r.v v0, v25
+; ZVFHMIN-NEXT: vmv1r.v v0, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v24
+; ZVFHMIN-NEXT: vmv1r.v v0, v25
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: fsflags a0
@@ -858,49 +850,49 @@ define <vscale x 32 x half> @vp_nearbyint_nxv32f16(<vscale x 32 x half> %va, <vs
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: vmv1r.v v5, v6
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v5, v16, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: frflags a2
-; ZVFHMIN-NEXT: vmv1r.v v0, v5
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: fsflags a2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB22_2:
; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v8, v7
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v16, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v8, v0
; ZVFHMIN-NEXT: frflags a0
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: fsflags a0
; ZVFHMIN-NEXT: ret
%v = call <vscale x 32 x half> @llvm.vp.nearbyint.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 %evl)
@@ -937,27 +929,27 @@ define <vscale x 32 x half> @vp_nearbyint_nxv32f16_unmasked(<vscale x 32 x half>
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v7, v16, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: vmv1r.v v6, v7
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v6, v16, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: frflags a2
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: fsflags a2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
@@ -1933,8 +1925,8 @@ define <vscale x 16 x double> @vp_nearbyint_nxv16f64(<vscale x 16 x double> %va,
; RV32ZVFH-NEXT: vslidedown.vx v6, v0, a3
; RV32ZVFH-NEXT: sltu a3, a0, a2
; RV32ZVFH-NEXT: addi a3, a3, -1
-; RV32ZVFH-NEXT: and a2, a3, a2
; RV32ZVFH-NEXT: vmv1r.v v0, v6
+; RV32ZVFH-NEXT: and a2, a3, a2
; RV32ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -1979,8 +1971,8 @@ define <vscale x 16 x double> @vp_nearbyint_nxv16f64(<vscale x 16 x double> %va,
; RV64ZVFH-NEXT: fmv.d.x fa5, a2
; RV64ZVFH-NEXT: sltu a2, a0, a3
; RV64ZVFH-NEXT: addi a2, a2, -1
-; RV64ZVFH-NEXT: and a2, a2, a3
; RV64ZVFH-NEXT: vmv1r.v v0, v6
+; RV64ZVFH-NEXT: and a2, a2, a3
; RV64ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -2024,8 +2016,8 @@ define <vscale x 16 x double> @vp_nearbyint_nxv16f64(<vscale x 16 x double> %va,
; RV32ZVFHMIN-NEXT: vslidedown.vx v6, v0, a3
; RV32ZVFHMIN-NEXT: sltu a3, a0, a2
; RV32ZVFHMIN-NEXT: addi a3, a3, -1
-; RV32ZVFHMIN-NEXT: and a2, a3, a2
; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV32ZVFHMIN-NEXT: and a2, a3, a2
; RV32ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -2070,8 +2062,8 @@ define <vscale x 16 x double> @vp_nearbyint_nxv16f64(<vscale x 16 x double> %va,
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a2
; RV64ZVFHMIN-NEXT: sltu a2, a0, a3
; RV64ZVFHMIN-NEXT: addi a2, a2, -1
-; RV64ZVFHMIN-NEXT: and a2, a2, a3
; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV64ZVFHMIN-NEXT: and a2, a2, a3
; RV64ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -2116,13 +2108,13 @@ define <vscale x 16 x double> @vp_nearbyint_nxv16f64_unmasked(<vscale x 16 x dou
; RV32ZVFH-NEXT: sltu a2, a0, a3
; RV32ZVFH-NEXT: addi a2, a2, -1
; RV32ZVFH-NEXT: and a2, a2, a3
+; RV32ZVFH-NEXT: frflags a3
; RV32ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v16
; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFH-NEXT: frflags a2
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV32ZVFH-NEXT: fsflags a2
+; RV32ZVFH-NEXT: fsflags a3
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
; RV32ZVFH-NEXT: bltu a0, a1, .LBB45_2
@@ -2150,13 +2142,13 @@ define <vscale x 16 x double> @vp_nearbyint_nxv16f64_unmasked(<vscale x 16 x dou
; RV64ZVFH-NEXT: sltu a2, a0, a3
; RV64ZVFH-NEXT: addi a2, a2, -1
; RV64ZVFH-NEXT: and a2, a2, a3
+; RV64ZVFH-NEXT: frflags a3
; RV64ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v16
; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFH-NEXT: frflags a2
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV64ZVFH-NEXT: fsflags a2
+; RV64ZVFH-NEXT: fsflags a3
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
; RV64ZVFH-NEXT: bltu a0, a1, .LBB45_2
@@ -2183,13 +2175,13 @@ define <vscale x 16 x double> @vp_nearbyint_nxv16f64_unmasked(<vscale x 16 x dou
; RV32ZVFHMIN-NEXT: sltu a2, a0, a3
; RV32ZVFHMIN-NEXT: addi a2, a2, -1
; RV32ZVFHMIN-NEXT: and a2, a2, a3
+; RV32ZVFHMIN-NEXT: frflags a3
; RV32ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v16
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFHMIN-NEXT: frflags a2
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV32ZVFHMIN-NEXT: fsflags a2
+; RV32ZVFHMIN-NEXT: fsflags a3
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
; RV32ZVFHMIN-NEXT: bltu a0, a1, .LBB45_2
@@ -2217,13 +2209,13 @@ define <vscale x 16 x double> @vp_nearbyint_nxv16f64_unmasked(<vscale x 16 x dou
; RV64ZVFHMIN-NEXT: sltu a2, a0, a3
; RV64ZVFHMIN-NEXT: addi a2, a2, -1
; RV64ZVFHMIN-NEXT: and a2, a2, a3
+; RV64ZVFHMIN-NEXT: frflags a3
; RV64ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v16
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFHMIN-NEXT: frflags a2
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; RV64ZVFHMIN-NEXT: fsflags a2
+; RV64ZVFHMIN-NEXT: fsflags a3
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
; RV64ZVFHMIN-NEXT: bltu a0, a1, .LBB45_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr165232.ll b/llvm/test/CodeGen/RISCV/rvv/pr165232.ll
index 95f54bc29511b..39a1b3b6e4559 100644
--- a/llvm/test/CodeGen/RISCV/rvv/pr165232.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/pr165232.ll
@@ -10,171 +10,225 @@ define i1 @main(ptr %var_117, ptr %arrayinit.element3045, ptr %arrayinit.element
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr t0, vlenb
-; CHECK-NEXT: slli t0, t0, 3
+; CHECK-NEXT: slli t0, t0, 1
; CHECK-NEXT: mv t1, t0
+; CHECK-NEXT: slli t0, t0, 2
+; CHECK-NEXT: add t1, t1, t0
; CHECK-NEXT: slli t0, t0, 1
; CHECK-NEXT: add t0, t0, t1
; CHECK-NEXT: sub sp, sp, t0
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
; CHECK-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd a2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: csrr t0, vlenb
-; CHECK-NEXT: slli t0, t0, 2
-; CHECK-NEXT: add a1, a1, t0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: mv t0, a1
; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, t0
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: mv t0, a1
; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, t0
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: ld t0, 56(a1)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: mv t1, a1
; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, t1
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: ld t1, 48(a1)
; CHECK-NEXT: vsetvli t2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: mv t2, a1
; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, t2
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: ld t2, 40(a1)
-; CHECK-NEXT: # kill: def $v10 killed $v9 killed $vtype
+; CHECK-NEXT: # kill: def $v13 killed $v12 killed $vtype
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: mv t3, a1
; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, t3
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: ld t3, 32(a1)
-; CHECK-NEXT: vmv.v.i v11, 0
+; CHECK-NEXT: vmv.v.i v14, 0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: mv t4, a1
; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, t4
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: ld t4, 16(a1)
-; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmv.v.i v15, 0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: mv t5, a1
; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, t5
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: ld t5, 24(a1)
-; CHECK-NEXT: vmv.v.i v13, 0
-; CHECK-NEXT: vsetvli t6, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: vmv1r.v v14, v9
+; CHECK-NEXT: vsetvli t6, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmv.v.i v20, 0
+; CHECK-NEXT: vmv1r.v v17, v12
; CHECK-NEXT: sd zero, 0(a0)
-; CHECK-NEXT: vmv.v.i v18, 0
-; CHECK-NEXT: vmv1r.v v15, v9
-; CHECK-NEXT: vmv1r.v v28, v9
+; CHECK-NEXT: vmv.v.i v22, 0
+; CHECK-NEXT: vmv1r.v v18, v12
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: li t6, 1023
-; CHECK-NEXT: vmv.v.i v20, 0
-; CHECK-NEXT: vmv1r.v v29, v9
+; CHECK-NEXT: vmv.v.i v24, 0
+; CHECK-NEXT: vmv1r.v v9, v12
; CHECK-NEXT: slli t6, t6, 52
-; CHECK-NEXT: vmv.v.i v22, 0
+; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs4r.v v20, (a1) # vscale x 32-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: ld a2, 0(sp) # 8-byte Folded Reload
+; CHECK-NEXT: vs4r.v v24, (a1) # vscale x 32-byte Folded Spill
; CHECK-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
-; CHECK-NEXT: vmv1r.v v30, v9
+; CHECK-NEXT: vmv1r.v v10, v12
; CHECK-NEXT: sd t6, 0(t5)
-; CHECK-NEXT: vmv1r.v v21, v9
-; CHECK-NEXT: vmv2r.v v22, v10
-; CHECK-NEXT: vmv4r.v v24, v12
-; CHECK-NEXT: vmv1r.v v31, v9
+; CHECK-NEXT: vmv1r.v v19, v12
+; CHECK-NEXT: vmv1r.v v20, v13
+; CHECK-NEXT: vmv1r.v v21, v14
+; CHECK-NEXT: vmv1r.v v22, v15
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vmv1r.v v24, v17
+; CHECK-NEXT: vmv1r.v v25, v18
+; CHECK-NEXT: vmv1r.v v11, v12
+; CHECK-NEXT: csrr t5, vlenb
+; CHECK-NEXT: slli t5, t5, 1
+; CHECK-NEXT: mv t6, t5
+; CHECK-NEXT: slli t5, t5, 2
+; CHECK-NEXT: add t5, t5, t6
+; CHECK-NEXT: add t5, sp, t5
+; CHECK-NEXT: addi t5, t5, 16
+; CHECK-NEXT: vs4r.v v8, (t5) # vscale x 32-byte Folded Spill
+; CHECK-NEXT: vsetivli zero, 0, e64, m2, ta, ma
+; CHECK-NEXT: vmclr.m v8
+; CHECK-NEXT: csrr t5, vlenb
+; CHECK-NEXT: slli t6, t5, 3
+; CHECK-NEXT: add t5, t6, t5
+; CHECK-NEXT: add t5, sp, t5
+; CHECK-NEXT: addi t5, t5, 16
+; CHECK-NEXT: vs1r.v v8, (t5) # vscale x 8-byte Folded Spill
; CHECK-NEXT: csrr t5, vlenb
; CHECK-NEXT: slli t5, t5, 3
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
-; CHECK-NEXT: vs4r.v v28, (t5) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v13, 0
-; CHECK-NEXT: vmclr.m v14
+; CHECK-NEXT: vs1r.v v8, (t5) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: .LBB0_1: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vsetivli zero, 0, e64, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmv1r.v v17, v13
-; CHECK-NEXT: vmv1r.v v15, v13
-; CHECK-NEXT: vmv1r.v v9, v13
-; CHECK-NEXT: vmv1r.v v16, v13
-; CHECK-NEXT: vmv1r.v v19, v13
-; CHECK-NEXT: vmv1r.v v28, v13
-; CHECK-NEXT: vmv1r.v v12, v13
-; CHECK-NEXT: vmv1r.v v2, v21
-; CHECK-NEXT: vmv1r.v v4, v23
-; CHECK-NEXT: vmv1r.v v5, v24
-; CHECK-NEXT: vmv1r.v v6, v25
-; CHECK-NEXT: vmv1r.v v7, v26
-; CHECK-NEXT: vmv1r.v v8, v27
-; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmv.v.i v30, 0
-; CHECK-NEXT: vmv1r.v v29, v13
-; CHECK-NEXT: vmv1r.v v18, v14
+; CHECK-NEXT: vmv.v.i v31, 0
+; CHECK-NEXT: vmv.v.i v13, 0
+; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmv.v.i v11, 0
+; CHECK-NEXT: vmv.v.i v18, 0
+; CHECK-NEXT: vmv2r.v v0, v18
+; CHECK-NEXT: vmv2r.v v2, v20
+; CHECK-NEXT: vmv2r.v v4, v22
+; CHECK-NEXT: vmv2r.v v6, v24
+; CHECK-NEXT: vmv2r.v v14, v16
+; CHECK-NEXT: vmv2r.v v28, v16
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: csrr t5, vlenb
+; CHECK-NEXT: slli t6, t5, 3
+; CHECK-NEXT: add t5, t6, t5
+; CHECK-NEXT: add t5, sp, t5
+; CHECK-NEXT: addi t5, t5, 16
+; CHECK-NEXT: vl1r.v v8, (t5) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
-; CHECK-NEXT: vle32.v v17, (t4)
-; CHECK-NEXT: vle32.v v15, (t1)
-; CHECK-NEXT: vle32.v v28, (a7)
-; CHECK-NEXT: vle64.v v30, (a4)
-; CHECK-NEXT: vle32.v v9, (t2)
-; CHECK-NEXT: vle32.v v16, (t3)
-; CHECK-NEXT: vle32.v v19, (a6)
-; CHECK-NEXT: vmv1r.v v3, v28
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v18, v30, v10, v0.t
-; CHECK-NEXT: vmv1r.v v19, v13
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu
-; CHECK-NEXT: vle32.v v29, (a2)
-; CHECK-NEXT: vle32.v v19, (a3)
-; CHECK-NEXT: vle32.v v12, (a5)
-; CHECK-NEXT: vmv1r.v v1, v17
+; CHECK-NEXT: vle32.v v30, (t4)
+; CHECK-NEXT: vle32.v v31, (t1)
+; CHECK-NEXT: vle32.v v11, (a7)
+; CHECK-NEXT: vle64.v v28, (a4)
+; CHECK-NEXT: vle32.v v13, (t2)
+; CHECK-NEXT: vle32.v v26, (t3)
+; CHECK-NEXT: vle32.v v10, (a6)
+; CHECK-NEXT: vmv1r.v v2, v11
; CHECK-NEXT: csrr t5, vlenb
; CHECK-NEXT: slli t5, t5, 3
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
-; CHECK-NEXT: vl1r.v v9, (t5) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: csrr t6, vlenb
-; CHECK-NEXT: add t5, t5, t6
-; CHECK-NEXT: vl2r.v v10, (t5) # vscale x 16-byte Folded Reload
-; CHECK-NEXT: slli t6, t6, 1
-; CHECK-NEXT: add t5, t5, t6
-; CHECK-NEXT: vl1r.v v12, (t5) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsseg4e32.v v9, (zero)
-; CHECK-NEXT: vsseg8e32.v v1, (a1)
-; CHECK-NEXT: vmv1r.v v0, v18
-; CHECK-NEXT: vssub.vv v19, v13, v29, v0.t
+; CHECK-NEXT: vl1r.v v0, (t5) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
+; CHECK-NEXT: vmflt.vv v8, v28, v16, v0.t
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu
+; CHECK-NEXT: vle32.v v12, (a2)
+; CHECK-NEXT: vle32.v v10, (a3)
+; CHECK-NEXT: vle32.v v18, (a5)
+; CHECK-NEXT: vmv1r.v v0, v30
; CHECK-NEXT: csrr t5, vlenb
+; CHECK-NEXT: slli t5, t5, 1
+; CHECK-NEXT: mv t6, t5
; CHECK-NEXT: slli t5, t5, 2
+; CHECK-NEXT: add t5, t5, t6
+; CHECK-NEXT: add t5, sp, t5
+; CHECK-NEXT: addi t5, t5, 16
+; CHECK-NEXT: vl4r.v v28, (t5) # vscale x 32-byte Folded Reload
+; CHECK-NEXT: vsseg4e32.v v28, (zero)
+; CHECK-NEXT: vsseg8e32.v v0, (a1)
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vssub.vv v10, v9, v12, v0.t
+; CHECK-NEXT: csrr t5, vlenb
+; CHECK-NEXT: slli t5, t5, 1
; CHECK-NEXT: mv t6, t5
; CHECK-NEXT: slli t5, t5, 1
+; CHECK-NEXT: add t6, t6, t5
+; CHECK-NEXT: slli t5, t5, 1
; CHECK-NEXT: add t5, t5, t6
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
-; CHECK-NEXT: vl4r.v v28, (t5) # vscale x 32-byte Folded Reload
+; CHECK-NEXT: vl2r.v v2, (t5) # vscale x 16-byte Folded Reload
+; CHECK-NEXT: csrr t6, vlenb
+; CHECK-NEXT: slli t6, t6, 1
+; CHECK-NEXT: add t5, t5, t6
+; CHECK-NEXT: vl2r.v v4, (t5) # vscale x 16-byte Folded Reload
; CHECK-NEXT: vsetvli zero, t0, e64, m2, ta, ma
-; CHECK-NEXT: vsseg2e64.v v28, (zero)
-; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vsseg2e64.v v2, (zero)
; CHECK-NEXT: addi t5, sp, 16
; CHECK-NEXT: vl2r.v v2, (t5) # vscale x 16-byte Folded Reload
; CHECK-NEXT: csrr t6, vlenb
@@ -184,17 +238,28 @@ define i1 @main(ptr %var_117, ptr %arrayinit.element3045, ptr %arrayinit.element
; CHECK-NEXT: slli t6, t6, 1
; CHECK-NEXT: add t5, t5, t6
; CHECK-NEXT: vl2r.v v8, (t5) # vscale x 16-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vsetivli zero, 0, e64, m2, ta, ma
; CHECK-NEXT: vsseg4e64.v v2, (zero), v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vsseg8e32.v v19, (a0)
+; CHECK-NEXT: vsseg8e32.v v10, (a0)
; CHECK-NEXT: csrr t5, vlenb
-; CHECK-NEXT: slli t5, t5, 4
+; CHECK-NEXT: slli t5, t5, 1
+; CHECK-NEXT: mv t6, t5
+; CHECK-NEXT: slli t5, t5, 3
+; CHECK-NEXT: add t5, t5, t6
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
-; CHECK-NEXT: vl8r.v v0, (t5) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl2r.v v2, (t5) # vscale x 16-byte Folded Reload
+; CHECK-NEXT: csrr t6, vlenb
+; CHECK-NEXT: slli t6, t6, 1
+; CHECK-NEXT: add t5, t5, t6
+; CHECK-NEXT: vl4r.v v4, (t5) # vscale x 32-byte Folded Reload
+; CHECK-NEXT: slli t6, t6, 1
+; CHECK-NEXT: add t5, t5, t6
+; CHECK-NEXT: vl2r.v v8, (t5) # vscale x 16-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; CHECK-NEXT: vsseg4e64.v v0, (zero)
+; CHECK-NEXT: vsseg4e64.v v2, (zero)
; CHECK-NEXT: j .LBB0_1
entry:
store double 0.000000e+00, ptr %var_117, align 8
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr88576.ll b/llvm/test/CodeGen/RISCV/rvv/pr88576.ll
index a094e35ffde97..0d025d06b0da4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/pr88576.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/pr88576.ll
@@ -7,6 +7,8 @@ define i1 @foo(<vscale x 16 x i8> %x, i64 %y) {
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a2, a1, 4
; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv2r.v v0, v8
; CHECK-NEXT: bltu a0, a2, .LBB0_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
@@ -20,20 +22,29 @@ define i1 @foo(<vscale x 16 x i8> %x, i64 %y) {
; CHECK-NEXT: addi s0, sp, 80
; CHECK-NEXT: .cfi_def_cfa s0, 0
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: andi sp, sp, -64
-; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: addi a2, sp, 64
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 64
; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: add a0, a2, a0
; CHECK-NEXT: add a1, a2, a1
-; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
-; CHECK-NEXT: vs8r.v v24, (a1)
+; CHECK-NEXT: addi a3, sp, 64
+; CHECK-NEXT: vs2r.v v0, (a3) # vscale x 16-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v1
+; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT: addi a3, sp, 64
+; CHECK-NEXT: vl2r.v v0, (a3) # vscale x 16-byte Folded Reload
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vs8r.v v8, (a2)
; CHECK-NEXT: lbu a0, 0(a0)
; CHECK-NEXT: addi sp, s0, -80
diff --git a/llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll b/llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
index c574bd758bd2d..bfff09bc35c8e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
@@ -7,24 +7,23 @@ define i32 @_ZN4Mesh12rezone_countESt6vectorIiSaIiEERiS3_(<vscale x 4 x i32> %wi
; CHECK-LABEL: _ZN4Mesh12rezone_countESt6vectorIiSaIiEERiS3_:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 0, e32, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v17, v0
; CHECK-NEXT: li a0, 0
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vmv.v.i v14, 0
; CHECK-NEXT: .LBB0_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vsetivli zero, 0, e32, m2, ta, mu
-; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: vmv2r.v v16, v10
-; CHECK-NEXT: vle32.v v16, (a0), v0.t
-; CHECK-NEXT: vand.vi v16, v16, 1
-; CHECK-NEXT: vmsne.vi v9, v16, 0
-; CHECK-NEXT: vmand.mm v0, v8, v9
-; CHECK-NEXT: vmerge.vim v12, v12, -1, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vor.vi v14, v14, 1, v0.t
+; CHECK-NEXT: vsetivli zero, 0, e32, m2, ta, mu
+; CHECK-NEXT: vmv2r.v v14, v8
+; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vle32.v v14, (a0), v0.t
+; CHECK-NEXT: vor.vi v12, v12, 1, v0.t
+; CHECK-NEXT: vand.vi v14, v14, 1
+; CHECK-NEXT: vmsne.vi v16, v14, 0
+; CHECK-NEXT: vmand.mm v0, v17, v16
+; CHECK-NEXT: vmerge.vim v10, v10, -1, v0
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: j .LBB0_1
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
index 82235f08b5226..b36c80a05f407 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
@@ -16,24 +16,22 @@ define <vscale x 1 x bfloat> @vp_rint_nxv1bf16(<vscale x 1 x bfloat> %va, <vscal
; CHECK-LABEL: vp_rint_nxv1bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfabs.v v11, v10, v0.t
+; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t
-; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 1 x bfloat> @llvm.vp.rint.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x bfloat> %v
@@ -64,24 +62,22 @@ define <vscale x 2 x bfloat> @vp_rint_nxv2bf16(<vscale x 2 x bfloat> %va, <vscal
; CHECK-LABEL: vp_rint_nxv2bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfabs.v v11, v10, v0.t
+; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t
-; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t
-; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 2 x bfloat> @llvm.vp.rint.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x bfloat> %v
@@ -115,19 +111,19 @@ define <vscale x 4 x bfloat> @vp_rint_nxv4bf16(<vscale x 4 x bfloat> %va, <vscal
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v8, v10, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v13, v8, fa5, v0.t
-; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v13, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
; CHECK-NEXT: ret
@@ -163,19 +159,19 @@ define <vscale x 8 x bfloat> @vp_rint_nxv8bf16(<vscale x 8 x bfloat> %va, <vscal
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v17, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfabs.v v8, v12, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v17, v8, fa5, v0.t
-; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v17, v0
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
; CHECK-NEXT: ret
@@ -211,19 +207,19 @@ define <vscale x 16 x bfloat> @vp_rint_nxv16bf16(<vscale x 16 x bfloat> %va, <vs
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v8, v16, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa5, v0.t
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmflt.vf v24, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vfsgnj.vv v16, v8, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: ret
@@ -265,46 +261,46 @@ define <vscale x 32 x bfloat> @vp_rint_nxv32bf16(<vscale x 32 x bfloat> %va, <vs
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vslidedown.vx v6, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: vmv1r.v v5, v6
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v5, v16, fa5, v0.t
-; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v12, v0
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB10_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB10_2:
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t
-; CHECK-NEXT: vmv1r.v v8, v7
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v16, fa5, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 32 x bfloat> @llvm.vp.rint.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x bfloat> %v
@@ -324,25 +320,25 @@ define <vscale x 32 x bfloat> @vp_rint_nxv32bf16_unmasked(<vscale x 32 x bfloat>
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v7, v16, a2
; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: vmv1r.v v6, v7
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v6, v16, fa5, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v12, v0
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB11_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -383,24 +379,22 @@ define <vscale x 1 x half> @vp_rint_nxv1f16(<vscale x 1 x half> %va, <vscale x 1
; ZVFHMIN-LABEL: vp_rint_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x half> @llvm.vp.rint.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x half> %v
@@ -461,24 +455,22 @@ define <vscale x 2 x half> @vp_rint_nxv2f16(<vscale x 2 x half> %va, <vscale x 2
; ZVFHMIN-LABEL: vp_rint_nxv2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
-; ZVFHMIN-NEXT: vmv.v.v v0, v8
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 2 x half> @llvm.vp.rint.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x half> %v
@@ -542,19 +534,19 @@ define <vscale x 4 x half> @vp_rint_nxv4f16(<vscale x 4 x half> %va, <vscale x 4
; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v13, v8, fa5, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v13
+; ZVFHMIN-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v13, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
+; ZVFHMIN-NEXT: vmv1r.v v0, v13
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: ret
@@ -622,19 +614,19 @@ define <vscale x 8 x half> @vp_rint_nxv8f16(<vscale x 8 x half> %va, <vscale x 8
; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v17
+; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v17, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vmv1r.v v0, v17
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
@@ -702,19 +694,19 @@ define <vscale x 16 x half> @vp_rint_nxv16f16(<vscale x 16 x half> %va, <vscale
; ZVFHMIN-NEXT: vmv1r.v v24, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v25, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v16, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v25, v8, fa5, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v25
+; ZVFHMIN-NEXT: vmflt.vf v24, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v25, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v24
+; ZVFHMIN-NEXT: vmv1r.v v0, v25
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
@@ -788,46 +780,46 @@ define <vscale x 32 x half> @vp_rint_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: vmv1r.v v5, v6
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v5, v16, fa5, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v5
+; ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v12, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB22_2:
; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v8, v7
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v16, fa5, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v8, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 32 x half> @llvm.vp.rint.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x half> %v
@@ -861,25 +853,25 @@ define <vscale x 32 x half> @vp_rint_nxv32f16_unmasked(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v7, v16, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: vmv1r.v v6, v7
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v6, v16, fa5, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v12, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
@@ -1753,8 +1745,8 @@ define <vscale x 16 x double> @vp_rint_nxv16f64(<vscale x 16 x double> %va, <vsc
; RV32ZVFH-NEXT: vslidedown.vx v6, v0, a3
; RV32ZVFH-NEXT: sltu a3, a0, a2
; RV32ZVFH-NEXT: addi a3, a3, -1
-; RV32ZVFH-NEXT: and a2, a3, a2
; RV32ZVFH-NEXT: vmv1r.v v0, v6
+; RV32ZVFH-NEXT: and a2, a3, a2
; RV32ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -1795,8 +1787,8 @@ define <vscale x 16 x double> @vp_rint_nxv16f64(<vscale x 16 x double> %va, <vsc
; RV64ZVFH-NEXT: fmv.d.x fa5, a2
; RV64ZVFH-NEXT: sltu a2, a0, a3
; RV64ZVFH-NEXT: addi a2, a2, -1
-; RV64ZVFH-NEXT: and a2, a2, a3
; RV64ZVFH-NEXT: vmv1r.v v0, v6
+; RV64ZVFH-NEXT: and a2, a2, a3
; RV64ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -1836,8 +1828,8 @@ define <vscale x 16 x double> @vp_rint_nxv16f64(<vscale x 16 x double> %va, <vsc
; RV32ZVFMIN-NEXT: vslidedown.vx v6, v0, a3
; RV32ZVFMIN-NEXT: sltu a3, a0, a2
; RV32ZVFMIN-NEXT: addi a3, a3, -1
-; RV32ZVFMIN-NEXT: and a2, a3, a2
; RV32ZVFMIN-NEXT: vmv1r.v v0, v6
+; RV32ZVFMIN-NEXT: and a2, a3, a2
; RV32ZVFMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFMIN-NEXT: vfabs.v v24, v16, v0.t
; RV32ZVFMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -1878,8 +1870,8 @@ define <vscale x 16 x double> @vp_rint_nxv16f64(<vscale x 16 x double> %va, <vsc
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a2
; RV64ZVFHMIN-NEXT: sltu a2, a0, a3
; RV64ZVFHMIN-NEXT: addi a2, a2, -1
-; RV64ZVFHMIN-NEXT: and a2, a2, a3
; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV64ZVFHMIN-NEXT: and a2, a2, a3
; RV64ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -1943,15 +1935,15 @@ define <vscale x 16 x double> @vp_rint_nxv16f64_unmasked(<vscale x 16 x double>
; RV64ZVFH-LABEL: vp_rint_nxv16f64_unmasked:
; RV64ZVFH: # %bb.0:
; RV64ZVFH-NEXT: csrr a1, vlenb
-; RV64ZVFH-NEXT: li a2, 1075
-; RV64ZVFH-NEXT: sub a3, a0, a1
-; RV64ZVFH-NEXT: slli a2, a2, 52
-; RV64ZVFH-NEXT: fmv.d.x fa5, a2
-; RV64ZVFH-NEXT: sltu a2, a0, a3
-; RV64ZVFH-NEXT: addi a2, a2, -1
-; RV64ZVFH-NEXT: and a2, a2, a3
+; RV64ZVFH-NEXT: sub a2, a0, a1
+; RV64ZVFH-NEXT: sltu a3, a0, a2
+; RV64ZVFH-NEXT: addi a3, a3, -1
+; RV64ZVFH-NEXT: and a2, a3, a2
+; RV64ZVFH-NEXT: li a3, 1075
+; RV64ZVFH-NEXT: slli a3, a3, 52
; RV64ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v16
+; RV64ZVFH-NEXT: fmv.d.x fa5, a3
; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -2002,15 +1994,15 @@ define <vscale x 16 x double> @vp_rint_nxv16f64_unmasked(<vscale x 16 x double>
; RV64ZVFHMIN-LABEL: vp_rint_nxv16f64_unmasked:
; RV64ZVFHMIN: # %bb.0:
; RV64ZVFHMIN-NEXT: csrr a1, vlenb
-; RV64ZVFHMIN-NEXT: li a2, 1075
-; RV64ZVFHMIN-NEXT: sub a3, a0, a1
-; RV64ZVFHMIN-NEXT: slli a2, a2, 52
-; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a2
-; RV64ZVFHMIN-NEXT: sltu a2, a0, a3
-; RV64ZVFHMIN-NEXT: addi a2, a2, -1
-; RV64ZVFHMIN-NEXT: and a2, a2, a3
+; RV64ZVFHMIN-NEXT: sub a2, a0, a1
+; RV64ZVFHMIN-NEXT: sltu a3, a0, a2
+; RV64ZVFHMIN-NEXT: addi a3, a3, -1
+; RV64ZVFHMIN-NEXT: and a2, a3, a2
+; RV64ZVFHMIN-NEXT: li a3, 1075
+; RV64ZVFHMIN-NEXT: slli a3, a3, 52
; RV64ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v16
+; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a3
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll
index eae28fafb4300..c5a3b2252de19 100644
--- a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll
@@ -16,26 +16,24 @@ define <vscale x 1 x bfloat> @vp_round_nxv1bf16(<vscale x 1 x bfloat> %va, <vsca
; CHECK-LABEL: vp_round_nxv1bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfabs.v v11, v10, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 4
-; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
-; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 1 x bfloat> @llvm.vp.round.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x bfloat> %v
@@ -47,11 +45,11 @@ define <vscale x 1 x bfloat> @vp_round_nxv1bf16_unmasked(<vscale x 1 x bfloat> %
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -68,26 +66,24 @@ define <vscale x 2 x bfloat> @vp_round_nxv2bf16(<vscale x 2 x bfloat> %va, <vsca
; CHECK-LABEL: vp_round_nxv2bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfabs.v v11, v10, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 4
-; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
-; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 2 x bfloat> @llvm.vp.round.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x bfloat> %v
@@ -99,11 +95,11 @@ define <vscale x 2 x bfloat> @vp_round_nxv2bf16_unmasked(<vscale x 2 x bfloat> %
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -123,21 +119,21 @@ define <vscale x 4 x bfloat> @vp_round_nxv4bf16(<vscale x 4 x bfloat> %va, <vsca
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v8, v10, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v13, v8, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fsrmi a0, 4
-; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
; CHECK-NEXT: ret
@@ -151,11 +147,11 @@ define <vscale x 4 x bfloat> @vp_round_nxv4bf16_unmasked(<vscale x 4 x bfloat> %
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v8, v10
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -175,21 +171,21 @@ define <vscale x 8 x bfloat> @vp_round_nxv8bf16(<vscale x 8 x bfloat> %va, <vsca
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v17, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfabs.v v8, v12, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v17, v8, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v17, v0
; CHECK-NEXT: fsrmi a0, 4
-; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
; CHECK-NEXT: ret
@@ -203,11 +199,11 @@ define <vscale x 8 x bfloat> @vp_round_nxv8bf16_unmasked(<vscale x 8 x bfloat> %
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfabs.v v8, v12
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -227,21 +223,21 @@ define <vscale x 16 x bfloat> @vp_round_nxv16bf16(<vscale x 16 x bfloat> %va, <v
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v8, v16, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v24, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fsrmi a0, 4
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vfsgnj.vv v16, v8, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: ret
@@ -255,11 +251,11 @@ define <vscale x 16 x bfloat> @vp_round_nxv16bf16_unmasked(<vscale x 16 x bfloat
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v8, v16
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -285,50 +281,50 @@ define <vscale x 32 x bfloat> @vp_round_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vslidedown.vx v6, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: vmv1r.v v5, v6
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v5, v16, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: fsrmi a2, 4
-; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a2
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB10_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB10_2:
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t
-; CHECK-NEXT: vmv1r.v v8, v7
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v16, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: fsrmi a0, 4
-; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a0
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 32 x bfloat> @llvm.vp.round.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x bfloat> %v
@@ -348,37 +344,37 @@ define <vscale x 32 x bfloat> @vp_round_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v7, v16, a2
; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: vmv1r.v v6, v7
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v6, v16, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: fsrmi a2, 4
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a2
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB11_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB11_2:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v24, v16
; CHECK-NEXT: vmflt.vf v0, v24, fa5
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -399,9 +395,9 @@ define <vscale x 1 x half> @vp_round_nxv1f16(<vscale x 1 x half> %va, <vscale x
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -413,26 +409,24 @@ define <vscale x 1 x half> @vp_round_nxv1f16(<vscale x 1 x half> %va, <vscale x
; ZVFHMIN-LABEL: vp_round_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 4
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x half> @llvm.vp.round.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x half> %v
@@ -446,8 +440,8 @@ define <vscale x 1 x half> @vp_round_nxv1f16_unmasked(<vscale x 1 x half> %va, i
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -460,11 +454,11 @@ define <vscale x 1 x half> @vp_round_nxv1f16_unmasked(<vscale x 1 x half> %va, i
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -485,9 +479,9 @@ define <vscale x 2 x half> @vp_round_nxv2f16(<vscale x 2 x half> %va, <vscale x
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -499,26 +493,24 @@ define <vscale x 2 x half> @vp_round_nxv2f16(<vscale x 2 x half> %va, <vscale x
; ZVFHMIN-LABEL: vp_round_nxv2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 4
-; ZVFHMIN-NEXT: vmv.v.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 2 x half> @llvm.vp.round.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x half> %v
@@ -532,8 +524,8 @@ define <vscale x 2 x half> @vp_round_nxv2f16_unmasked(<vscale x 2 x half> %va, i
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -546,11 +538,11 @@ define <vscale x 2 x half> @vp_round_nxv2f16_unmasked(<vscale x 2 x half> %va, i
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -571,9 +563,9 @@ define <vscale x 4 x half> @vp_round_nxv4f16(<vscale x 4 x half> %va, <vscale x
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 4
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -588,21 +580,21 @@ define <vscale x 4 x half> @vp_round_nxv4f16(<vscale x 4 x half> %va, <vscale x
; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v13, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: fsrmi a0, 4
-; ZVFHMIN-NEXT: vmv1r.v v0, v13
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
+; ZVFHMIN-NEXT: vmv1r.v v0, v13
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: ret
@@ -618,8 +610,8 @@ define <vscale x 4 x half> @vp_round_nxv4f16_unmasked(<vscale x 4 x half> %va, i
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -632,11 +624,11 @@ define <vscale x 4 x half> @vp_round_nxv4f16_unmasked(<vscale x 4 x half> %va, i
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -676,21 +668,21 @@ define <vscale x 8 x half> @vp_round_nxv8f16(<vscale x 8 x half> %va, <vscale x
; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: fsrmi a0, 4
-; ZVFHMIN-NEXT: vmv1r.v v0, v17
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vmv1r.v v0, v17
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
@@ -706,8 +698,8 @@ define <vscale x 8 x half> @vp_round_nxv8f16_unmasked(<vscale x 8 x half> %va, i
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -720,11 +712,11 @@ define <vscale x 8 x half> @vp_round_nxv8f16_unmasked(<vscale x 8 x half> %va, i
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -764,21 +756,21 @@ define <vscale x 16 x half> @vp_round_nxv16f16(<vscale x 16 x half> %va, <vscale
; ZVFHMIN-NEXT: vmv1r.v v24, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v25, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v16, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v25, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v24, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v25, v0
; ZVFHMIN-NEXT: fsrmi a0, 4
-; ZVFHMIN-NEXT: vmv1r.v v0, v25
+; ZVFHMIN-NEXT: vmv1r.v v0, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v24
+; ZVFHMIN-NEXT: vmv1r.v v0, v25
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
@@ -794,8 +786,8 @@ define <vscale x 16 x half> @vp_round_nxv16f16_unmasked(<vscale x 16 x half> %va
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -808,11 +800,11 @@ define <vscale x 16 x half> @vp_round_nxv16f16_unmasked(<vscale x 16 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v16
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -858,50 +850,50 @@ define <vscale x 32 x half> @vp_round_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: vmv1r.v v5, v6
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v5, v16, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: fsrmi a2, 4
-; ZVFHMIN-NEXT: vmv1r.v v0, v5
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a2
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB22_2:
; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v8, v7
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v16, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v8, v0
; ZVFHMIN-NEXT: fsrmi a0, 4
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 32 x half> @llvm.vp.round.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x half> %v
@@ -915,8 +907,8 @@ define <vscale x 32 x half> @vp_round_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: fsrmi a0, 4
+; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -937,37 +929,37 @@ define <vscale x 32 x half> @vp_round_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v7, v16, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: vmv1r.v v6, v7
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v6, v16, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: fsrmi a2, 4
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a2
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB23_2:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v24, v16
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -987,9 +979,9 @@ define <vscale x 1 x float> @vp_round_nxv1f32(<vscale x 1 x float> %va, <vscale
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -1008,8 +1000,8 @@ define <vscale x 1 x float> @vp_round_nxv1f32_unmasked(<vscale x 1 x float> %va,
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1027,9 +1019,9 @@ define <vscale x 2 x float> @vp_round_nxv2f32(<vscale x 2 x float> %va, <vscale
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -1048,8 +1040,8 @@ define <vscale x 2 x float> @vp_round_nxv2f32_unmasked(<vscale x 2 x float> %va,
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1090,8 +1082,8 @@ define <vscale x 4 x float> @vp_round_nxv4f32_unmasked(<vscale x 4 x float> %va,
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1132,8 +1124,8 @@ define <vscale x 8 x float> @vp_round_nxv8f32_unmasked(<vscale x 8 x float> %va,
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1174,8 +1166,8 @@ define <vscale x 16 x float> @vp_round_nxv16f32_unmasked(<vscale x 16 x float> %
; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 4
+; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1193,9 +1185,9 @@ define <vscale x 1 x double> @vp_round_nxv1f64(<vscale x 1 x double> %va, <vscal
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI34_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZVFH-NEXT: fsrmi a0, 4
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a0, 4
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
@@ -1211,9 +1203,9 @@ define <vscale x 1 x double> @vp_round_nxv1f64(<vscale x 1 x double> %va, <vscal
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
+; RV64ZVFH-NEXT: fsrmi a0, 4
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZVFH-NEXT: fsrmi a0, 4
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
@@ -1228,9 +1220,9 @@ define <vscale x 1 x double> @vp_round_nxv1f64(<vscale x 1 x double> %va, <vscal
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI34_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZVFHMIN-NEXT: fsrmi a0, 4
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a0, 4
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
@@ -1246,9 +1238,9 @@ define <vscale x 1 x double> @vp_round_nxv1f64(<vscale x 1 x double> %va, <vscal
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
+; RV64ZVFHMIN-NEXT: fsrmi a0, 4
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a0, 4
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
@@ -1267,8 +1259,8 @@ define <vscale x 1 x double> @vp_round_nxv1f64_unmasked(<vscale x 1 x double> %v
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI35_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1283,8 +1275,8 @@ define <vscale x 1 x double> @vp_round_nxv1f64_unmasked(<vscale x 1 x double> %v
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1298,8 +1290,8 @@ define <vscale x 1 x double> @vp_round_nxv1f64_unmasked(<vscale x 1 x double> %v
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI35_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1314,8 +1306,8 @@ define <vscale x 1 x double> @vp_round_nxv1f64_unmasked(<vscale x 1 x double> %v
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1415,8 +1407,8 @@ define <vscale x 2 x double> @vp_round_nxv2f64_unmasked(<vscale x 2 x double> %v
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI37_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZVFH-NEXT: vfabs.v v10, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1431,8 +1423,8 @@ define <vscale x 2 x double> @vp_round_nxv2f64_unmasked(<vscale x 2 x double> %v
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1446,8 +1438,8 @@ define <vscale x 2 x double> @vp_round_nxv2f64_unmasked(<vscale x 2 x double> %v
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI37_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v10, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1462,8 +1454,8 @@ define <vscale x 2 x double> @vp_round_nxv2f64_unmasked(<vscale x 2 x double> %v
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1563,8 +1555,8 @@ define <vscale x 4 x double> @vp_round_nxv4f64_unmasked(<vscale x 4 x double> %v
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI39_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZVFH-NEXT: vfabs.v v12, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1579,8 +1571,8 @@ define <vscale x 4 x double> @vp_round_nxv4f64_unmasked(<vscale x 4 x double> %v
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1594,8 +1586,8 @@ define <vscale x 4 x double> @vp_round_nxv4f64_unmasked(<vscale x 4 x double> %v
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI39_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v12, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1610,8 +1602,8 @@ define <vscale x 4 x double> @vp_round_nxv4f64_unmasked(<vscale x 4 x double> %v
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1711,8 +1703,8 @@ define <vscale x 7 x double> @vp_round_nxv7f64_unmasked(<vscale x 7 x double> %v
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI41_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1727,8 +1719,8 @@ define <vscale x 7 x double> @vp_round_nxv7f64_unmasked(<vscale x 7 x double> %v
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1742,8 +1734,8 @@ define <vscale x 7 x double> @vp_round_nxv7f64_unmasked(<vscale x 7 x double> %v
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI41_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1758,8 +1750,8 @@ define <vscale x 7 x double> @vp_round_nxv7f64_unmasked(<vscale x 7 x double> %v
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1859,8 +1851,8 @@ define <vscale x 8 x double> @vp_round_nxv8f64_unmasked(<vscale x 8 x double> %v
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI43_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1875,8 +1867,8 @@ define <vscale x 8 x double> @vp_round_nxv8f64_unmasked(<vscale x 8 x double> %v
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1890,8 +1882,8 @@ define <vscale x 8 x double> @vp_round_nxv8f64_unmasked(<vscale x 8 x double> %v
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI43_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1906,8 +1898,8 @@ define <vscale x 8 x double> @vp_round_nxv8f64_unmasked(<vscale x 8 x double> %v
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1933,8 +1925,8 @@ define <vscale x 16 x double> @vp_round_nxv16f64(<vscale x 16 x double> %va, <vs
; RV32ZVFH-NEXT: vslidedown.vx v6, v0, a3
; RV32ZVFH-NEXT: sltu a3, a0, a2
; RV32ZVFH-NEXT: addi a3, a3, -1
-; RV32ZVFH-NEXT: and a2, a3, a2
; RV32ZVFH-NEXT: vmv1r.v v0, v6
+; RV32ZVFH-NEXT: and a2, a3, a2
; RV32ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -1979,8 +1971,8 @@ define <vscale x 16 x double> @vp_round_nxv16f64(<vscale x 16 x double> %va, <vs
; RV64ZVFH-NEXT: fmv.d.x fa5, a2
; RV64ZVFH-NEXT: sltu a2, a0, a3
; RV64ZVFH-NEXT: addi a2, a2, -1
-; RV64ZVFH-NEXT: and a2, a2, a3
; RV64ZVFH-NEXT: vmv1r.v v0, v6
+; RV64ZVFH-NEXT: and a2, a2, a3
; RV64ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -2024,8 +2016,8 @@ define <vscale x 16 x double> @vp_round_nxv16f64(<vscale x 16 x double> %va, <vs
; RV32ZVFHMIN-NEXT: vslidedown.vx v6, v0, a3
; RV32ZVFHMIN-NEXT: sltu a3, a0, a2
; RV32ZVFHMIN-NEXT: addi a3, a3, -1
-; RV32ZVFHMIN-NEXT: and a2, a3, a2
; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV32ZVFHMIN-NEXT: and a2, a3, a2
; RV32ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -2070,8 +2062,8 @@ define <vscale x 16 x double> @vp_round_nxv16f64(<vscale x 16 x double> %va, <vs
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a2
; RV64ZVFHMIN-NEXT: sltu a2, a0, a3
; RV64ZVFHMIN-NEXT: addi a2, a2, -1
-; RV64ZVFHMIN-NEXT: and a2, a2, a3
; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV64ZVFHMIN-NEXT: and a2, a2, a3
; RV64ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -2116,12 +2108,12 @@ define <vscale x 16 x double> @vp_round_nxv16f64_unmasked(<vscale x 16 x double>
; RV32ZVFH-NEXT: sltu a2, a0, a3
; RV32ZVFH-NEXT: addi a2, a2, -1
; RV32ZVFH-NEXT: and a2, a2, a3
+; RV32ZVFH-NEXT: fsrmi a3, 4
; RV32ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v16
; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFH-NEXT: fsrmi a2, 4
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFH-NEXT: fsrm a2
+; RV32ZVFH-NEXT: fsrm a3
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -2131,8 +2123,8 @@ define <vscale x 16 x double> @vp_round_nxv16f64_unmasked(<vscale x 16 x double>
; RV32ZVFH-NEXT: .LBB45_2:
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
; RV32ZVFH-NEXT: fsrmi a0, 4
+; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -2150,12 +2142,12 @@ define <vscale x 16 x double> @vp_round_nxv16f64_unmasked(<vscale x 16 x double>
; RV64ZVFH-NEXT: sltu a2, a0, a3
; RV64ZVFH-NEXT: addi a2, a2, -1
; RV64ZVFH-NEXT: and a2, a2, a3
+; RV64ZVFH-NEXT: fsrmi a3, 4
; RV64ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v16
; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFH-NEXT: fsrmi a2, 4
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFH-NEXT: fsrm a2
+; RV64ZVFH-NEXT: fsrm a3
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -2165,8 +2157,8 @@ define <vscale x 16 x double> @vp_round_nxv16f64_unmasked(<vscale x 16 x double>
; RV64ZVFH-NEXT: .LBB45_2:
; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v8
-; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
; RV64ZVFH-NEXT: fsrmi a0, 4
+; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -2183,12 +2175,12 @@ define <vscale x 16 x double> @vp_round_nxv16f64_unmasked(<vscale x 16 x double>
; RV32ZVFHMIN-NEXT: sltu a2, a0, a3
; RV32ZVFHMIN-NEXT: addi a2, a2, -1
; RV32ZVFHMIN-NEXT: and a2, a2, a3
+; RV32ZVFHMIN-NEXT: fsrmi a3, 4
; RV32ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v16
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFHMIN-NEXT: fsrmi a2, 4
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a2
+; RV32ZVFHMIN-NEXT: fsrm a3
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -2198,8 +2190,8 @@ define <vscale x 16 x double> @vp_round_nxv16f64_unmasked(<vscale x 16 x double>
; RV32ZVFHMIN-NEXT: .LBB45_2:
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 4
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -2217,12 +2209,12 @@ define <vscale x 16 x double> @vp_round_nxv16f64_unmasked(<vscale x 16 x double>
; RV64ZVFHMIN-NEXT: sltu a2, a0, a3
; RV64ZVFHMIN-NEXT: addi a2, a2, -1
; RV64ZVFHMIN-NEXT: and a2, a2, a3
+; RV64ZVFHMIN-NEXT: fsrmi a3, 4
; RV64ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v16
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFHMIN-NEXT: fsrmi a2, 4
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a2
+; RV64ZVFHMIN-NEXT: fsrm a3
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -2232,8 +2224,8 @@ define <vscale x 16 x double> @vp_round_nxv16f64_unmasked(<vscale x 16 x double>
; RV64ZVFHMIN-NEXT: .LBB45_2:
; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v8
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 4
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll b/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
index b9c435b7fb8d8..443909ba2cc25 100644
--- a/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
@@ -16,26 +16,24 @@ define <vscale x 1 x bfloat> @vp_roundeven_nxv1bf16(<vscale x 1 x bfloat> %va, <
; CHECK-LABEL: vp_roundeven_nxv1bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfabs.v v11, v10, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 0
-; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
-; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 1 x bfloat> @llvm.vp.roundeven.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x bfloat> %v
@@ -47,11 +45,11 @@ define <vscale x 1 x bfloat> @vp_roundeven_nxv1bf16_unmasked(<vscale x 1 x bfloa
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -68,26 +66,24 @@ define <vscale x 2 x bfloat> @vp_roundeven_nxv2bf16(<vscale x 2 x bfloat> %va, <
; CHECK-LABEL: vp_roundeven_nxv2bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfabs.v v11, v10, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 0
-; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
-; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 2 x bfloat> @llvm.vp.roundeven.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x bfloat> %v
@@ -99,11 +95,11 @@ define <vscale x 2 x bfloat> @vp_roundeven_nxv2bf16_unmasked(<vscale x 2 x bfloa
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -123,21 +119,21 @@ define <vscale x 4 x bfloat> @vp_roundeven_nxv4bf16(<vscale x 4 x bfloat> %va, <
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v8, v10, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v13, v8, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fsrmi a0, 0
-; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
; CHECK-NEXT: ret
@@ -151,11 +147,11 @@ define <vscale x 4 x bfloat> @vp_roundeven_nxv4bf16_unmasked(<vscale x 4 x bfloa
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v8, v10
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -175,21 +171,21 @@ define <vscale x 8 x bfloat> @vp_roundeven_nxv8bf16(<vscale x 8 x bfloat> %va, <
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v17, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfabs.v v8, v12, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v17, v8, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v17, v0
; CHECK-NEXT: fsrmi a0, 0
-; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
; CHECK-NEXT: ret
@@ -203,11 +199,11 @@ define <vscale x 8 x bfloat> @vp_roundeven_nxv8bf16_unmasked(<vscale x 8 x bfloa
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfabs.v v8, v12
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -227,21 +223,21 @@ define <vscale x 16 x bfloat> @vp_roundeven_nxv16bf16(<vscale x 16 x bfloat> %va
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v8, v16, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v24, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fsrmi a0, 0
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vfsgnj.vv v16, v8, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: ret
@@ -255,11 +251,11 @@ define <vscale x 16 x bfloat> @vp_roundeven_nxv16bf16_unmasked(<vscale x 16 x bf
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v8, v16
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -285,50 +281,50 @@ define <vscale x 32 x bfloat> @vp_roundeven_nxv32bf16(<vscale x 32 x bfloat> %va
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vslidedown.vx v6, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: vmv1r.v v5, v6
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v5, v16, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: fsrmi a2, 0
-; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a2
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB10_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB10_2:
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t
-; CHECK-NEXT: vmv1r.v v8, v7
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v16, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: fsrmi a0, 0
-; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a0
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 32 x bfloat> @llvm.vp.roundeven.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x bfloat> %v
@@ -348,37 +344,37 @@ define <vscale x 32 x bfloat> @vp_roundeven_nxv32bf16_unmasked(<vscale x 32 x bf
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v7, v16, a2
; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: vmv1r.v v6, v7
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v6, v16, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: fsrmi a2, 0
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a2
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB11_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB11_2:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v24, v16
; CHECK-NEXT: vmflt.vf v0, v24, fa5
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -399,9 +395,9 @@ define <vscale x 1 x half> @vp_roundeven_nxv1f16(<vscale x 1 x half> %va, <vscal
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -413,26 +409,24 @@ define <vscale x 1 x half> @vp_roundeven_nxv1f16(<vscale x 1 x half> %va, <vscal
; ZVFHMIN-LABEL: vp_roundeven_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 0
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x half> @llvm.vp.roundeven.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x half> %v
@@ -446,8 +440,8 @@ define <vscale x 1 x half> @vp_roundeven_nxv1f16_unmasked(<vscale x 1 x half> %v
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -460,11 +454,11 @@ define <vscale x 1 x half> @vp_roundeven_nxv1f16_unmasked(<vscale x 1 x half> %v
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -485,9 +479,9 @@ define <vscale x 2 x half> @vp_roundeven_nxv2f16(<vscale x 2 x half> %va, <vscal
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -499,26 +493,24 @@ define <vscale x 2 x half> @vp_roundeven_nxv2f16(<vscale x 2 x half> %va, <vscal
; ZVFHMIN-LABEL: vp_roundeven_nxv2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 0
-; ZVFHMIN-NEXT: vmv.v.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 2 x half> @llvm.vp.roundeven.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x half> %v
@@ -532,8 +524,8 @@ define <vscale x 2 x half> @vp_roundeven_nxv2f16_unmasked(<vscale x 2 x half> %v
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -546,11 +538,11 @@ define <vscale x 2 x half> @vp_roundeven_nxv2f16_unmasked(<vscale x 2 x half> %v
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -571,9 +563,9 @@ define <vscale x 4 x half> @vp_roundeven_nxv4f16(<vscale x 4 x half> %va, <vscal
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 0
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -588,21 +580,21 @@ define <vscale x 4 x half> @vp_roundeven_nxv4f16(<vscale x 4 x half> %va, <vscal
; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v13, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: fsrmi a0, 0
-; ZVFHMIN-NEXT: vmv1r.v v0, v13
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
+; ZVFHMIN-NEXT: vmv1r.v v0, v13
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: ret
@@ -618,8 +610,8 @@ define <vscale x 4 x half> @vp_roundeven_nxv4f16_unmasked(<vscale x 4 x half> %v
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -632,11 +624,11 @@ define <vscale x 4 x half> @vp_roundeven_nxv4f16_unmasked(<vscale x 4 x half> %v
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -676,21 +668,21 @@ define <vscale x 8 x half> @vp_roundeven_nxv8f16(<vscale x 8 x half> %va, <vscal
; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: fsrmi a0, 0
-; ZVFHMIN-NEXT: vmv1r.v v0, v17
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vmv1r.v v0, v17
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
@@ -706,8 +698,8 @@ define <vscale x 8 x half> @vp_roundeven_nxv8f16_unmasked(<vscale x 8 x half> %v
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -720,11 +712,11 @@ define <vscale x 8 x half> @vp_roundeven_nxv8f16_unmasked(<vscale x 8 x half> %v
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -764,21 +756,21 @@ define <vscale x 16 x half> @vp_roundeven_nxv16f16(<vscale x 16 x half> %va, <vs
; ZVFHMIN-NEXT: vmv1r.v v24, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v25, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v16, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v25, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v24, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v25, v0
; ZVFHMIN-NEXT: fsrmi a0, 0
-; ZVFHMIN-NEXT: vmv1r.v v0, v25
+; ZVFHMIN-NEXT: vmv1r.v v0, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v24
+; ZVFHMIN-NEXT: vmv1r.v v0, v25
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
@@ -794,8 +786,8 @@ define <vscale x 16 x half> @vp_roundeven_nxv16f16_unmasked(<vscale x 16 x half>
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -808,11 +800,11 @@ define <vscale x 16 x half> @vp_roundeven_nxv16f16_unmasked(<vscale x 16 x half>
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v16
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -858,50 +850,50 @@ define <vscale x 32 x half> @vp_roundeven_nxv32f16(<vscale x 32 x half> %va, <vs
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: vmv1r.v v5, v6
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v5, v16, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: fsrmi a2, 0
-; ZVFHMIN-NEXT: vmv1r.v v0, v5
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a2
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB22_2:
; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v8, v7
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v16, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v8, v0
; ZVFHMIN-NEXT: fsrmi a0, 0
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 32 x half> @llvm.vp.roundeven.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x half> %v
@@ -915,8 +907,8 @@ define <vscale x 32 x half> @vp_roundeven_nxv32f16_unmasked(<vscale x 32 x half>
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: fsrmi a0, 0
+; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -937,37 +929,37 @@ define <vscale x 32 x half> @vp_roundeven_nxv32f16_unmasked(<vscale x 32 x half>
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v7, v16, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: vmv1r.v v6, v7
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v6, v16, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: fsrmi a2, 0
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a2
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB23_2:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v24, v16
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -987,9 +979,9 @@ define <vscale x 1 x float> @vp_roundeven_nxv1f32(<vscale x 1 x float> %va, <vsc
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -1008,8 +1000,8 @@ define <vscale x 1 x float> @vp_roundeven_nxv1f32_unmasked(<vscale x 1 x float>
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1027,9 +1019,9 @@ define <vscale x 2 x float> @vp_roundeven_nxv2f32(<vscale x 2 x float> %va, <vsc
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -1048,8 +1040,8 @@ define <vscale x 2 x float> @vp_roundeven_nxv2f32_unmasked(<vscale x 2 x float>
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1090,8 +1082,8 @@ define <vscale x 4 x float> @vp_roundeven_nxv4f32_unmasked(<vscale x 4 x float>
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1132,8 +1124,8 @@ define <vscale x 8 x float> @vp_roundeven_nxv8f32_unmasked(<vscale x 8 x float>
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1174,8 +1166,8 @@ define <vscale x 16 x float> @vp_roundeven_nxv16f32_unmasked(<vscale x 16 x floa
; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 0
+; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1193,9 +1185,9 @@ define <vscale x 1 x double> @vp_roundeven_nxv1f64(<vscale x 1 x double> %va, <v
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI34_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZVFH-NEXT: fsrmi a0, 0
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a0, 0
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
@@ -1211,9 +1203,9 @@ define <vscale x 1 x double> @vp_roundeven_nxv1f64(<vscale x 1 x double> %va, <v
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
+; RV64ZVFH-NEXT: fsrmi a0, 0
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZVFH-NEXT: fsrmi a0, 0
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
@@ -1228,9 +1220,9 @@ define <vscale x 1 x double> @vp_roundeven_nxv1f64(<vscale x 1 x double> %va, <v
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI34_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZVFHMIN-NEXT: fsrmi a0, 0
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a0, 0
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
@@ -1246,9 +1238,9 @@ define <vscale x 1 x double> @vp_roundeven_nxv1f64(<vscale x 1 x double> %va, <v
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
+; RV64ZVFHMIN-NEXT: fsrmi a0, 0
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a0, 0
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
@@ -1267,8 +1259,8 @@ define <vscale x 1 x double> @vp_roundeven_nxv1f64_unmasked(<vscale x 1 x double
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI35_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1283,8 +1275,8 @@ define <vscale x 1 x double> @vp_roundeven_nxv1f64_unmasked(<vscale x 1 x double
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1298,8 +1290,8 @@ define <vscale x 1 x double> @vp_roundeven_nxv1f64_unmasked(<vscale x 1 x double
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI35_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1314,8 +1306,8 @@ define <vscale x 1 x double> @vp_roundeven_nxv1f64_unmasked(<vscale x 1 x double
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1415,8 +1407,8 @@ define <vscale x 2 x double> @vp_roundeven_nxv2f64_unmasked(<vscale x 2 x double
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI37_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZVFH-NEXT: vfabs.v v10, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1431,8 +1423,8 @@ define <vscale x 2 x double> @vp_roundeven_nxv2f64_unmasked(<vscale x 2 x double
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1446,8 +1438,8 @@ define <vscale x 2 x double> @vp_roundeven_nxv2f64_unmasked(<vscale x 2 x double
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI37_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v10, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1462,8 +1454,8 @@ define <vscale x 2 x double> @vp_roundeven_nxv2f64_unmasked(<vscale x 2 x double
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1563,8 +1555,8 @@ define <vscale x 4 x double> @vp_roundeven_nxv4f64_unmasked(<vscale x 4 x double
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI39_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZVFH-NEXT: vfabs.v v12, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1579,8 +1571,8 @@ define <vscale x 4 x double> @vp_roundeven_nxv4f64_unmasked(<vscale x 4 x double
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1594,8 +1586,8 @@ define <vscale x 4 x double> @vp_roundeven_nxv4f64_unmasked(<vscale x 4 x double
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI39_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v12, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1610,8 +1602,8 @@ define <vscale x 4 x double> @vp_roundeven_nxv4f64_unmasked(<vscale x 4 x double
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1711,8 +1703,8 @@ define <vscale x 7 x double> @vp_roundeven_nxv7f64_unmasked(<vscale x 7 x double
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI41_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1727,8 +1719,8 @@ define <vscale x 7 x double> @vp_roundeven_nxv7f64_unmasked(<vscale x 7 x double
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1742,8 +1734,8 @@ define <vscale x 7 x double> @vp_roundeven_nxv7f64_unmasked(<vscale x 7 x double
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI41_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1758,8 +1750,8 @@ define <vscale x 7 x double> @vp_roundeven_nxv7f64_unmasked(<vscale x 7 x double
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1859,8 +1851,8 @@ define <vscale x 8 x double> @vp_roundeven_nxv8f64_unmasked(<vscale x 8 x double
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI43_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1875,8 +1867,8 @@ define <vscale x 8 x double> @vp_roundeven_nxv8f64_unmasked(<vscale x 8 x double
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1890,8 +1882,8 @@ define <vscale x 8 x double> @vp_roundeven_nxv8f64_unmasked(<vscale x 8 x double
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI43_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1906,8 +1898,8 @@ define <vscale x 8 x double> @vp_roundeven_nxv8f64_unmasked(<vscale x 8 x double
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1933,8 +1925,8 @@ define <vscale x 16 x double> @vp_roundeven_nxv16f64(<vscale x 16 x double> %va,
; RV32ZVFH-NEXT: vslidedown.vx v6, v0, a3
; RV32ZVFH-NEXT: sltu a3, a0, a2
; RV32ZVFH-NEXT: addi a3, a3, -1
-; RV32ZVFH-NEXT: and a2, a3, a2
; RV32ZVFH-NEXT: vmv1r.v v0, v6
+; RV32ZVFH-NEXT: and a2, a3, a2
; RV32ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -1979,8 +1971,8 @@ define <vscale x 16 x double> @vp_roundeven_nxv16f64(<vscale x 16 x double> %va,
; RV64ZVFH-NEXT: fmv.d.x fa5, a2
; RV64ZVFH-NEXT: sltu a2, a0, a3
; RV64ZVFH-NEXT: addi a2, a2, -1
-; RV64ZVFH-NEXT: and a2, a2, a3
; RV64ZVFH-NEXT: vmv1r.v v0, v6
+; RV64ZVFH-NEXT: and a2, a2, a3
; RV64ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -2024,8 +2016,8 @@ define <vscale x 16 x double> @vp_roundeven_nxv16f64(<vscale x 16 x double> %va,
; RV32ZVFHMIN-NEXT: vslidedown.vx v6, v0, a3
; RV32ZVFHMIN-NEXT: sltu a3, a0, a2
; RV32ZVFHMIN-NEXT: addi a3, a3, -1
-; RV32ZVFHMIN-NEXT: and a2, a3, a2
; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV32ZVFHMIN-NEXT: and a2, a3, a2
; RV32ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -2070,8 +2062,8 @@ define <vscale x 16 x double> @vp_roundeven_nxv16f64(<vscale x 16 x double> %va,
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a2
; RV64ZVFHMIN-NEXT: sltu a2, a0, a3
; RV64ZVFHMIN-NEXT: addi a2, a2, -1
-; RV64ZVFHMIN-NEXT: and a2, a2, a3
; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV64ZVFHMIN-NEXT: and a2, a2, a3
; RV64ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -2116,12 +2108,12 @@ define <vscale x 16 x double> @vp_roundeven_nxv16f64_unmasked(<vscale x 16 x dou
; RV32ZVFH-NEXT: sltu a2, a0, a3
; RV32ZVFH-NEXT: addi a2, a2, -1
; RV32ZVFH-NEXT: and a2, a2, a3
+; RV32ZVFH-NEXT: fsrmi a3, 0
; RV32ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v16
; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFH-NEXT: fsrmi a2, 0
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFH-NEXT: fsrm a2
+; RV32ZVFH-NEXT: fsrm a3
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -2131,8 +2123,8 @@ define <vscale x 16 x double> @vp_roundeven_nxv16f64_unmasked(<vscale x 16 x dou
; RV32ZVFH-NEXT: .LBB45_2:
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
; RV32ZVFH-NEXT: fsrmi a0, 0
+; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -2150,12 +2142,12 @@ define <vscale x 16 x double> @vp_roundeven_nxv16f64_unmasked(<vscale x 16 x dou
; RV64ZVFH-NEXT: sltu a2, a0, a3
; RV64ZVFH-NEXT: addi a2, a2, -1
; RV64ZVFH-NEXT: and a2, a2, a3
+; RV64ZVFH-NEXT: fsrmi a3, 0
; RV64ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v16
; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFH-NEXT: fsrmi a2, 0
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFH-NEXT: fsrm a2
+; RV64ZVFH-NEXT: fsrm a3
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -2165,8 +2157,8 @@ define <vscale x 16 x double> @vp_roundeven_nxv16f64_unmasked(<vscale x 16 x dou
; RV64ZVFH-NEXT: .LBB45_2:
; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v8
-; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
; RV64ZVFH-NEXT: fsrmi a0, 0
+; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -2183,12 +2175,12 @@ define <vscale x 16 x double> @vp_roundeven_nxv16f64_unmasked(<vscale x 16 x dou
; RV32ZVFHMIN-NEXT: sltu a2, a0, a3
; RV32ZVFHMIN-NEXT: addi a2, a2, -1
; RV32ZVFHMIN-NEXT: and a2, a2, a3
+; RV32ZVFHMIN-NEXT: fsrmi a3, 0
; RV32ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v16
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFHMIN-NEXT: fsrmi a2, 0
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a2
+; RV32ZVFHMIN-NEXT: fsrm a3
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -2198,8 +2190,8 @@ define <vscale x 16 x double> @vp_roundeven_nxv16f64_unmasked(<vscale x 16 x dou
; RV32ZVFHMIN-NEXT: .LBB45_2:
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 0
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -2217,12 +2209,12 @@ define <vscale x 16 x double> @vp_roundeven_nxv16f64_unmasked(<vscale x 16 x dou
; RV64ZVFHMIN-NEXT: sltu a2, a0, a3
; RV64ZVFHMIN-NEXT: addi a2, a2, -1
; RV64ZVFHMIN-NEXT: and a2, a2, a3
+; RV64ZVFHMIN-NEXT: fsrmi a3, 0
; RV64ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v16
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFHMIN-NEXT: fsrmi a2, 0
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a2
+; RV64ZVFHMIN-NEXT: fsrm a3
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -2232,8 +2224,8 @@ define <vscale x 16 x double> @vp_roundeven_nxv16f64_unmasked(<vscale x 16 x dou
; RV64ZVFHMIN-NEXT: .LBB45_2:
; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v8
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 0
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
index 7f4aaff7f8635..b81e2d7568ceb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
@@ -16,26 +16,24 @@ define <vscale x 1 x bfloat> @vp_roundtozero_nxv1bf16(<vscale x 1 x bfloat> %va,
; CHECK-LABEL: vp_roundtozero_nxv1bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfabs.v v11, v10, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 1
-; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
-; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 1 x bfloat> @llvm.vp.roundtozero.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x bfloat> %v
@@ -47,11 +45,11 @@ define <vscale x 1 x bfloat> @vp_roundtozero_nxv1bf16_unmasked(<vscale x 1 x bfl
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -68,26 +66,24 @@ define <vscale x 2 x bfloat> @vp_roundtozero_nxv2bf16(<vscale x 2 x bfloat> %va,
; CHECK-LABEL: vp_roundtozero_nxv2bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfabs.v v11, v10, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v11, fa5, v0.t
; CHECK-NEXT: fsrmi a0, 1
-; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
-; CHECK-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 2 x bfloat> @llvm.vp.roundtozero.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x bfloat> %v
@@ -99,11 +95,11 @@ define <vscale x 2 x bfloat> @vp_roundtozero_nxv2bf16_unmasked(<vscale x 2 x bfl
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -123,21 +119,21 @@ define <vscale x 4 x bfloat> @vp_roundtozero_nxv4bf16(<vscale x 4 x bfloat> %va,
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v8, v10, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; CHECK-NEXT: vmflt.vf v13, v8, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: fsrmi a0, 1
-; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10, v0.t
; CHECK-NEXT: ret
@@ -151,11 +147,11 @@ define <vscale x 4 x bfloat> @vp_roundtozero_nxv4bf16_unmasked(<vscale x 4 x bfl
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfabs.v v8, v10
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -175,21 +171,21 @@ define <vscale x 8 x bfloat> @vp_roundtozero_nxv8bf16(<vscale x 8 x bfloat> %va,
; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v17, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfabs.v v8, v12, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; CHECK-NEXT: vmflt.vf v17, v8, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v17, v0
; CHECK-NEXT: fsrmi a0, 1
-; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12, v0.t
; CHECK-NEXT: ret
@@ -203,11 +199,11 @@ define <vscale x 8 x bfloat> @vp_roundtozero_nxv8bf16_unmasked(<vscale x 8 x bfl
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfabs.v v8, v12
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -227,21 +223,21 @@ define <vscale x 16 x bfloat> @vp_roundtozero_nxv16bf16(<vscale x 16 x bfloat> %
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: lui a0, 307200
-; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v8, v16, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v25, v8, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v24, v8, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fsrmi a0, 1
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vfsgnj.vv v16, v8, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: ret
@@ -255,11 +251,11 @@ define <vscale x 16 x bfloat> @vp_roundtozero_nxv16bf16_unmasked(<vscale x 16 x
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v8, v16
-; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vmflt.vf v0, v8, fa5
-; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -285,50 +281,50 @@ define <vscale x 32 x bfloat> @vp_roundtozero_nxv32bf16(<vscale x 32 x bfloat> %
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vslidedown.vx v6, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: vmv1r.v v5, v6
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v5, v16, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: fsrmi a2, 1
-; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a2
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB10_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB10_2:
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t
-; CHECK-NEXT: vmv1r.v v8, v7
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v8, v16, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: fsrmi a0, 1
-; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a0
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 32 x bfloat> @llvm.vp.roundtozero.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x bfloat> %v
@@ -348,37 +344,37 @@ define <vscale x 32 x bfloat> @vp_roundtozero_nxv32bf16_unmasked(<vscale x 32 x
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v7, v16, a2
; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: vmv1r.v v6, v7
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfabs.v v16, v24, v0.t
+; CHECK-NEXT: vfabs.v v24, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmflt.vf v6, v16, fa5, v0.t
+; CHECK-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: fsrmi a2, 1
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a2
-; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; CHECK-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB11_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB11_2:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
+; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfabs.v v24, v16
; CHECK-NEXT: vmflt.vf v0, v24, fa5
-; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -399,9 +395,9 @@ define <vscale x 1 x half> @vp_roundtozero_nxv1f16(<vscale x 1 x half> %va, <vsc
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 1
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 1
; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -413,26 +409,24 @@ define <vscale x 1 x half> @vp_roundtozero_nxv1f16(<vscale x 1 x half> %va, <vsc
; ZVFHMIN-LABEL: vp_roundtozero_nxv1f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 1
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x half> @llvm.vp.roundtozero.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x half> %v
@@ -446,8 +440,8 @@ define <vscale x 1 x half> @vp_roundtozero_nxv1f16_unmasked(<vscale x 1 x half>
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 1
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -460,11 +454,11 @@ define <vscale x 1 x half> @vp_roundtozero_nxv1f16_unmasked(<vscale x 1 x half>
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -485,9 +479,9 @@ define <vscale x 2 x half> @vp_roundtozero_nxv2f16(<vscale x 2 x half> %va, <vsc
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 1
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 1
; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -499,26 +493,24 @@ define <vscale x 2 x half> @vp_roundtozero_nxv2f16(<vscale x 2 x half> %va, <vsc
; ZVFHMIN-LABEL: vp_roundtozero_nxv2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v9, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v8, v0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v11, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v11, fa5, v0.t
; ZVFHMIN-NEXT: fsrmi a0, 1
-; ZVFHMIN-NEXT: vmv.v.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v11, v11, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v10, v11, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v9
+; ZVFHMIN-NEXT: vfsgnj.vv v9, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v10
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 2 x half> @llvm.vp.roundtozero.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x half> %v
@@ -532,8 +524,8 @@ define <vscale x 2 x half> @vp_roundtozero_nxv2f16_unmasked(<vscale x 2 x half>
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 1
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -546,11 +538,11 @@ define <vscale x 2 x half> @vp_roundtozero_nxv2f16_unmasked(<vscale x 2 x half>
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -571,9 +563,9 @@ define <vscale x 4 x half> @vp_roundtozero_nxv4f16(<vscale x 4 x half> %va, <vsc
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
+; ZVFH-NEXT: fsrmi a0, 1
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu
; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; ZVFH-NEXT: fsrmi a0, 1
; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
@@ -588,21 +580,21 @@ define <vscale x 4 x half> @vp_roundtozero_nxv4f16(<vscale x 4 x half> %va, <vsc
; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v13, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v12, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v13, v0
; ZVFHMIN-NEXT: fsrmi a0, 1
-; ZVFHMIN-NEXT: vmv1r.v v0, v13
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v10, v8, v10, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v12
+; ZVFHMIN-NEXT: vmv1r.v v0, v13
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: ret
@@ -618,8 +610,8 @@ define <vscale x 4 x half> @vp_roundtozero_nxv4f16_unmasked(<vscale x 4 x half>
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: fsrmi a0, 1
+; ZVFH-NEXT: vmflt.vf v0, v9, fa5
; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -632,11 +624,11 @@ define <vscale x 4 x half> @vp_roundtozero_nxv4f16_unmasked(<vscale x 4 x half>
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v10
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -676,21 +668,21 @@ define <vscale x 8 x half> @vp_roundtozero_nxv8f16(<vscale x 8 x half> %va, <vsc
; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v17, v0
; ZVFHMIN-NEXT: fsrmi a0, 1
-; ZVFHMIN-NEXT: vmv1r.v v0, v17
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v12, v8, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vmv1r.v v0, v17
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
@@ -706,8 +698,8 @@ define <vscale x 8 x half> @vp_roundtozero_nxv8f16_unmasked(<vscale x 8 x half>
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: fsrmi a0, 1
+; ZVFH-NEXT: vmflt.vf v0, v10, fa5
; ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -720,11 +712,11 @@ define <vscale x 8 x half> @vp_roundtozero_nxv8f16_unmasked(<vscale x 8 x half>
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v12
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v12, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -764,21 +756,21 @@ define <vscale x 16 x half> @vp_roundtozero_nxv16f16(<vscale x 16 x half> %va, <
; ZVFHMIN-NEXT: vmv1r.v v24, v0
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: lui a0, 307200
-; ZVFHMIN-NEXT: vmv1r.v v25, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v16, v0.t
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v25, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v24, v8, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v25, v0
; ZVFHMIN-NEXT: fsrmi a0, 1
-; ZVFHMIN-NEXT: vmv1r.v v0, v25
+; ZVFHMIN-NEXT: vmv1r.v v0, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v16, v8, v16, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v24
+; ZVFHMIN-NEXT: vmv1r.v v0, v25
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
@@ -794,8 +786,8 @@ define <vscale x 16 x half> @vp_roundtozero_nxv16f16_unmasked(<vscale x 16 x hal
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: fsrmi a0, 1
+; ZVFH-NEXT: vmflt.vf v0, v12, fa5
; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -808,11 +800,11 @@ define <vscale x 16 x half> @vp_roundtozero_nxv16f16_unmasked(<vscale x 16 x hal
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: lui a0, 307200
+; ZVFHMIN-NEXT: fmv.w.x fa5, a0
+; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v16
-; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
@@ -858,50 +850,50 @@ define <vscale x 32 x half> @vp_roundtozero_nxv32f16(<vscale x 32 x half> %va, <
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: vmv1r.v v5, v6
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v5, v16, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v6, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: fsrmi a2, 1
-; ZVFHMIN-NEXT: vmv1r.v v0, v5
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a2
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB22_2:
; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v8, v7
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v8, v16, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v8, v0
; ZVFHMIN-NEXT: fsrmi a0, 1
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 32 x half> @llvm.vp.roundtozero.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x half> %v
@@ -915,8 +907,8 @@ define <vscale x 32 x half> @vp_roundtozero_nxv32f16_unmasked(<vscale x 32 x hal
; ZVFH-NEXT: li a0, 25
; ZVFH-NEXT: slli a0, a0, 10
; ZVFH-NEXT: fmv.h.x fa5, a0
-; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: fsrmi a0, 1
+; ZVFH-NEXT: vmflt.vf v0, v16, fa5
; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; ZVFH-NEXT: fsrm a0
; ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -937,37 +929,37 @@ define <vscale x 32 x half> @vp_roundtozero_nxv32f16_unmasked(<vscale x 32 x hal
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v7, v16, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: vmv1r.v v6, v7
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vmflt.vf v6, v16, fa5, v0.t
+; ZVFHMIN-NEXT: vmflt.vf v7, v24, fa5, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v12, v0
; ZVFHMIN-NEXT: fsrmi a2, 1
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a2
-; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
+; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
-; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB23_2:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfabs.v v24, v16
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: fsrm a0
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -987,9 +979,9 @@ define <vscale x 1 x float> @vp_roundtozero_nxv1f32(<vscale x 1 x float> %va, <v
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -1008,8 +1000,8 @@ define <vscale x 1 x float> @vp_roundtozero_nxv1f32_unmasked(<vscale x 1 x float
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 1
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1027,9 +1019,9 @@ define <vscale x 2 x float> @vp_roundtozero_nxv2f32(<vscale x 2 x float> %va, <v
; CHECK-NEXT: vfabs.v v9, v8, v0.t
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
@@ -1048,8 +1040,8 @@ define <vscale x 2 x float> @vp_roundtozero_nxv2f32_unmasked(<vscale x 2 x float
; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: fsrmi a0, 1
+; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1090,8 +1082,8 @@ define <vscale x 4 x float> @vp_roundtozero_nxv4f32_unmasked(<vscale x 4 x float
; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: fsrmi a0, 1
+; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1132,8 +1124,8 @@ define <vscale x 8 x float> @vp_roundtozero_nxv8f32_unmasked(<vscale x 8 x float
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: fsrmi a0, 1
+; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1174,8 +1166,8 @@ define <vscale x 16 x float> @vp_roundtozero_nxv16f32_unmasked(<vscale x 16 x fl
; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
-; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: fsrmi a0, 1
+; CHECK-NEXT: vmflt.vf v0, v16, fa5
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1193,9 +1185,9 @@ define <vscale x 1 x double> @vp_roundtozero_nxv1f64(<vscale x 1 x double> %va,
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI34_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZVFH-NEXT: fsrmi a0, 1
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZVFH-NEXT: fsrmi a0, 1
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
@@ -1211,9 +1203,9 @@ define <vscale x 1 x double> @vp_roundtozero_nxv1f64(<vscale x 1 x double> %va,
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
+; RV64ZVFH-NEXT: fsrmi a0, 1
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZVFH-NEXT: fsrmi a0, 1
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
@@ -1228,9 +1220,9 @@ define <vscale x 1 x double> @vp_roundtozero_nxv1f64(<vscale x 1 x double> %va,
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI34_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8, v0.t
+; RV32ZVFHMIN-NEXT: fsrmi a0, 1
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV32ZVFHMIN-NEXT: fsrmi a0, 1
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
@@ -1246,9 +1238,9 @@ define <vscale x 1 x double> @vp_roundtozero_nxv1f64(<vscale x 1 x double> %va,
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
+; RV64ZVFHMIN-NEXT: fsrmi a0, 1
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, mu
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5, v0.t
-; RV64ZVFHMIN-NEXT: fsrmi a0, 1
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
@@ -1267,8 +1259,8 @@ define <vscale x 1 x double> @vp_roundtozero_nxv1f64_unmasked(<vscale x 1 x doub
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI35_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFH-NEXT: vfabs.v v9, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: fsrmi a0, 1
+; RV32ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1283,8 +1275,8 @@ define <vscale x 1 x double> @vp_roundtozero_nxv1f64_unmasked(<vscale x 1 x doub
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: fsrmi a0, 1
+; RV64ZVFH-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1298,8 +1290,8 @@ define <vscale x 1 x double> @vp_roundtozero_nxv1f64_unmasked(<vscale x 1 x doub
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI35_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v9, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 1
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1314,8 +1306,8 @@ define <vscale x 1 x double> @vp_roundtozero_nxv1f64_unmasked(<vscale x 1 x doub
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 1
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v9, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v9, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v9, v9, v0.t
@@ -1415,8 +1407,8 @@ define <vscale x 2 x double> @vp_roundtozero_nxv2f64_unmasked(<vscale x 2 x doub
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI37_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZVFH-NEXT: vfabs.v v10, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: fsrmi a0, 1
+; RV32ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1431,8 +1423,8 @@ define <vscale x 2 x double> @vp_roundtozero_nxv2f64_unmasked(<vscale x 2 x doub
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: fsrmi a0, 1
+; RV64ZVFH-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1446,8 +1438,8 @@ define <vscale x 2 x double> @vp_roundtozero_nxv2f64_unmasked(<vscale x 2 x doub
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI37_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v10, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 1
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1462,8 +1454,8 @@ define <vscale x 2 x double> @vp_roundtozero_nxv2f64_unmasked(<vscale x 2 x doub
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 1
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v10, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v10, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v10, v10, v0.t
@@ -1563,8 +1555,8 @@ define <vscale x 4 x double> @vp_roundtozero_nxv4f64_unmasked(<vscale x 4 x doub
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI39_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZVFH-NEXT: vfabs.v v12, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: fsrmi a0, 1
+; RV32ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1579,8 +1571,8 @@ define <vscale x 4 x double> @vp_roundtozero_nxv4f64_unmasked(<vscale x 4 x doub
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: fsrmi a0, 1
+; RV64ZVFH-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1594,8 +1586,8 @@ define <vscale x 4 x double> @vp_roundtozero_nxv4f64_unmasked(<vscale x 4 x doub
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI39_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v12, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 1
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1610,8 +1602,8 @@ define <vscale x 4 x double> @vp_roundtozero_nxv4f64_unmasked(<vscale x 4 x doub
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 1
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v12, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v12, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v12, v12, v0.t
@@ -1711,8 +1703,8 @@ define <vscale x 7 x double> @vp_roundtozero_nxv7f64_unmasked(<vscale x 7 x doub
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI41_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 1
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1727,8 +1719,8 @@ define <vscale x 7 x double> @vp_roundtozero_nxv7f64_unmasked(<vscale x 7 x doub
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 1
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1742,8 +1734,8 @@ define <vscale x 7 x double> @vp_roundtozero_nxv7f64_unmasked(<vscale x 7 x doub
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI41_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 1
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1758,8 +1750,8 @@ define <vscale x 7 x double> @vp_roundtozero_nxv7f64_unmasked(<vscale x 7 x doub
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 1
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1859,8 +1851,8 @@ define <vscale x 8 x double> @vp_roundtozero_nxv8f64_unmasked(<vscale x 8 x doub
; RV32ZVFH-NEXT: fld fa5, %lo(.LCPI43_0)(a1)
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v16, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: fsrmi a0, 1
+; RV32ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1875,8 +1867,8 @@ define <vscale x 8 x double> @vp_roundtozero_nxv8f64_unmasked(<vscale x 8 x doub
; RV64ZVFH-NEXT: li a0, 1075
; RV64ZVFH-NEXT: slli a0, a0, 52
; RV64ZVFH-NEXT: fmv.d.x fa5, a0
-; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: fsrmi a0, 1
+; RV64ZVFH-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1890,8 +1882,8 @@ define <vscale x 8 x double> @vp_roundtozero_nxv8f64_unmasked(<vscale x 8 x doub
; RV32ZVFHMIN-NEXT: fld fa5, %lo(.LCPI43_0)(a1)
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v16, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 1
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1906,8 +1898,8 @@ define <vscale x 8 x double> @vp_roundtozero_nxv8f64_unmasked(<vscale x 8 x doub
; RV64ZVFHMIN-NEXT: li a0, 1075
; RV64ZVFHMIN-NEXT: slli a0, a0, 52
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a0
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 1
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v16, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v16, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
@@ -1933,8 +1925,8 @@ define <vscale x 16 x double> @vp_roundtozero_nxv16f64(<vscale x 16 x double> %v
; RV32ZVFH-NEXT: vslidedown.vx v6, v0, a3
; RV32ZVFH-NEXT: sltu a3, a0, a2
; RV32ZVFH-NEXT: addi a3, a3, -1
-; RV32ZVFH-NEXT: and a2, a3, a2
; RV32ZVFH-NEXT: vmv1r.v v0, v6
+; RV32ZVFH-NEXT: and a2, a3, a2
; RV32ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v16, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -1979,8 +1971,8 @@ define <vscale x 16 x double> @vp_roundtozero_nxv16f64(<vscale x 16 x double> %v
; RV64ZVFH-NEXT: fmv.d.x fa5, a2
; RV64ZVFH-NEXT: sltu a2, a0, a3
; RV64ZVFH-NEXT: addi a2, a2, -1
-; RV64ZVFH-NEXT: and a2, a2, a3
; RV64ZVFH-NEXT: vmv1r.v v0, v6
+; RV64ZVFH-NEXT: and a2, a2, a3
; RV64ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v16, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -2024,8 +2016,8 @@ define <vscale x 16 x double> @vp_roundtozero_nxv16f64(<vscale x 16 x double> %v
; RV32ZVFHMIN-NEXT: vslidedown.vx v6, v0, a3
; RV32ZVFHMIN-NEXT: sltu a3, a0, a2
; RV32ZVFHMIN-NEXT: addi a3, a3, -1
-; RV32ZVFHMIN-NEXT: and a2, a3, a2
; RV32ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV32ZVFHMIN-NEXT: and a2, a3, a2
; RV32ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -2070,8 +2062,8 @@ define <vscale x 16 x double> @vp_roundtozero_nxv16f64(<vscale x 16 x double> %v
; RV64ZVFHMIN-NEXT: fmv.d.x fa5, a2
; RV64ZVFHMIN-NEXT: sltu a2, a0, a3
; RV64ZVFHMIN-NEXT: addi a2, a2, -1
-; RV64ZVFHMIN-NEXT: and a2, a2, a3
; RV64ZVFHMIN-NEXT: vmv1r.v v0, v6
+; RV64ZVFHMIN-NEXT: and a2, a2, a3
; RV64ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v16, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
@@ -2116,12 +2108,12 @@ define <vscale x 16 x double> @vp_roundtozero_nxv16f64_unmasked(<vscale x 16 x d
; RV32ZVFH-NEXT: sltu a2, a0, a3
; RV32ZVFH-NEXT: addi a2, a2, -1
; RV32ZVFH-NEXT: and a2, a2, a3
+; RV32ZVFH-NEXT: fsrmi a3, 1
; RV32ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v16
; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFH-NEXT: fsrmi a2, 1
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFH-NEXT: fsrm a2
+; RV32ZVFH-NEXT: fsrm a3
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -2131,8 +2123,8 @@ define <vscale x 16 x double> @vp_roundtozero_nxv16f64_unmasked(<vscale x 16 x d
; RV32ZVFH-NEXT: .LBB45_2:
; RV32ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFH-NEXT: vfabs.v v24, v8
-; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
; RV32ZVFH-NEXT: fsrmi a0, 1
+; RV32ZVFH-NEXT: vmflt.vf v0, v24, fa5
; RV32ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV32ZVFH-NEXT: fsrm a0
; RV32ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -2150,12 +2142,12 @@ define <vscale x 16 x double> @vp_roundtozero_nxv16f64_unmasked(<vscale x 16 x d
; RV64ZVFH-NEXT: sltu a2, a0, a3
; RV64ZVFH-NEXT: addi a2, a2, -1
; RV64ZVFH-NEXT: and a2, a2, a3
+; RV64ZVFH-NEXT: fsrmi a3, 1
; RV64ZVFH-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v16
; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFH-NEXT: fsrmi a2, 1
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFH-NEXT: fsrm a2
+; RV64ZVFH-NEXT: fsrm a3
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFH-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFH-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -2165,8 +2157,8 @@ define <vscale x 16 x double> @vp_roundtozero_nxv16f64_unmasked(<vscale x 16 x d
; RV64ZVFH-NEXT: .LBB45_2:
; RV64ZVFH-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64ZVFH-NEXT: vfabs.v v24, v8
-; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
; RV64ZVFH-NEXT: fsrmi a0, 1
+; RV64ZVFH-NEXT: vmflt.vf v0, v24, fa5
; RV64ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV64ZVFH-NEXT: fsrm a0
; RV64ZVFH-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -2183,12 +2175,12 @@ define <vscale x 16 x double> @vp_roundtozero_nxv16f64_unmasked(<vscale x 16 x d
; RV32ZVFHMIN-NEXT: sltu a2, a0, a3
; RV32ZVFHMIN-NEXT: addi a2, a2, -1
; RV32ZVFHMIN-NEXT: and a2, a2, a3
+; RV32ZVFHMIN-NEXT: fsrmi a3, 1
; RV32ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v16
; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV32ZVFHMIN-NEXT: fsrmi a2, 1
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV32ZVFHMIN-NEXT: fsrm a2
+; RV32ZVFHMIN-NEXT: fsrm a3
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV32ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -2198,8 +2190,8 @@ define <vscale x 16 x double> @vp_roundtozero_nxv16f64_unmasked(<vscale x 16 x d
; RV32ZVFHMIN-NEXT: .LBB45_2:
; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32ZVFHMIN-NEXT: vfabs.v v24, v8
-; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; RV32ZVFHMIN-NEXT: fsrmi a0, 1
+; RV32ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; RV32ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV32ZVFHMIN-NEXT: fsrm a0
; RV32ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
@@ -2217,12 +2209,12 @@ define <vscale x 16 x double> @vp_roundtozero_nxv16f64_unmasked(<vscale x 16 x d
; RV64ZVFHMIN-NEXT: sltu a2, a0, a3
; RV64ZVFHMIN-NEXT: addi a2, a2, -1
; RV64ZVFHMIN-NEXT: and a2, a2, a3
+; RV64ZVFHMIN-NEXT: fsrmi a3, 1
; RV64ZVFHMIN-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v16
; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
-; RV64ZVFHMIN-NEXT: fsrmi a2, 1
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
-; RV64ZVFHMIN-NEXT: fsrm a2
+; RV64ZVFHMIN-NEXT: fsrm a3
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e64, m8, ta, mu
; RV64ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
@@ -2232,8 +2224,8 @@ define <vscale x 16 x double> @vp_roundtozero_nxv16f64_unmasked(<vscale x 16 x d
; RV64ZVFHMIN-NEXT: .LBB45_2:
; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64ZVFHMIN-NEXT: vfabs.v v24, v8
-; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; RV64ZVFHMIN-NEXT: fsrmi a0, 1
+; RV64ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
; RV64ZVFHMIN-NEXT: vfcvt.x.f.v v24, v8, v0.t
; RV64ZVFHMIN-NEXT: fsrm a0
; RV64ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
index acd9519bb5a8e..5a2fd164f2eab 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
@@ -858,8 +858,8 @@ define void @test_dag_loop() {
; CHECK-LABEL: test_dag_loop:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 0, e8, m4, ta, ma
-; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli zero, zero, e8, m4, tu, mu
; CHECK-NEXT: vssubu.vx v12, v8, zero, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
index 9e0842c83f9ad..92f665477d24f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
@@ -1351,21 +1351,13 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64bf16(<vscale x 64 x bfloat> %va, <vs
; CHECK-NEXT: add a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1b, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 27 * vlenb
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a3, a1
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vmv8r.v v0, v16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: mv a3, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a3, a3, a1
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, a1, a3
; CHECK-NEXT: add a1, sp, a1
@@ -1377,7 +1369,7 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64bf16(<vscale x 64 x bfloat> %va, <vs
; CHECK-NEXT: slli a4, a3, 1
; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: sub a6, a2, a5
-; CHECK-NEXT: vl8re16.v v24, (a1)
+; CHECK-NEXT: vl8re16.v v16, (a1)
; CHECK-NEXT: sltu a1, a2, a6
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a6, a1, a6
@@ -1390,14 +1382,12 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64bf16(<vscale x 64 x bfloat> %va, <vs
; CHECK-NEXT: csrr t0, vlenb
; CHECK-NEXT: slli t0, t0, 1
; CHECK-NEXT: mv t1, t0
-; CHECK-NEXT: slli t0, t0, 2
-; CHECK-NEXT: add t1, t1, t0
-; CHECK-NEXT: slli t0, t0, 1
+; CHECK-NEXT: slli t0, t0, 3
; CHECK-NEXT: add t0, t0, t1
; CHECK-NEXT: add t0, sp, t0
; CHECK-NEXT: addi t0, t0, 16
-; CHECK-NEXT: vl1r.v v8, (t0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vslidedown.vx v16, v8, a1
+; CHECK-NEXT: vs1r.v v24, (t0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vslidedown.vx v24, v24, a1
; CHECK-NEXT: vl8re16.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
@@ -1408,43 +1398,47 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64bf16(<vscale x 64 x bfloat> %va, <vs
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli t0, a0, 3
+; CHECK-NEXT: add a0, t0, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs1r.v v16, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v16, a3
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a7, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v28
+; CHECK-NEXT: vslidedown.vx v8, v24, a3
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a7, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v4
; CHECK-NEXT: bltu a6, a4, .LBB85_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a6, a4
; CHECK-NEXT: .LBB85_2:
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v5, v8, v16, v0.t
-; CHECK-NEXT: vsetvli zero, a6, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmfeq.vv v20, v8, v24, v0.t
+; CHECK-NEXT: vsetvli zero, a6, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v0
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a6, a0, 3
+; CHECK-NEXT: add a0, a6, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v7, v24, v16, v0.t
+; CHECK-NEXT: vmfeq.vv v16, v8, v24, v0.t
; CHECK-NEXT: bltu a2, a5, .LBB85_4
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a2, a5
@@ -1453,28 +1447,27 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64bf16(<vscale x 64 x bfloat> %va, <vs
; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: slli a5, a5, 1
; CHECK-NEXT: mv a6, a5
-; CHECK-NEXT: slli a5, a5, 2
-; CHECK-NEXT: add a6, a6, a5
-; CHECK-NEXT: slli a5, a5, 1
+; CHECK-NEXT: slli a5, a5, 3
; CHECK-NEXT: add a5, a5, a6
; CHECK-NEXT: add a5, sp, a5
; CHECK-NEXT: addi a5, a5, 16
; CHECK-NEXT: vl1r.v v8, (a5) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a3
+; CHECK-NEXT: vslidedown.vx v17, v8, a3
; CHECK-NEXT: sltu a5, a2, a0
; CHECK-NEXT: addi a5, a5, -1
; CHECK-NEXT: and a0, a5, a0
; CHECK-NEXT: csrr a5, vlenb
-; CHECK-NEXT: slli a5, a5, 1
; CHECK-NEXT: mv a6, a5
+; CHECK-NEXT: slli a5, a5, 1
+; CHECK-NEXT: add a6, a6, a5
; CHECK-NEXT: slli a5, a5, 3
; CHECK-NEXT: add a5, a5, a6
; CHECK-NEXT: add a5, sp, a5
; CHECK-NEXT: addi a5, a5, 16
-; CHECK-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v28
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: mv a5, a0
@@ -1482,27 +1475,28 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64bf16(<vscale x 64 x bfloat> %va, <vs
; CHECK-NEXT: add a0, a0, a5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12
+; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v4
+; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v9, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v8, v7
+; CHECK-NEXT: vmfeq.vv v17, v24, v8, v0.t
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v5, a3
+; CHECK-NEXT: vslideup.vx v16, v20, a3
; CHECK-NEXT: bltu a2, a4, .LBB85_6
; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: mv a2, a4
; CHECK-NEXT: .LBB85_6:
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: mv a4, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a4, a4, a0
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, a0, a4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: mv a2, a0
@@ -1515,20 +1509,18 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64bf16(<vscale x 64 x bfloat> %va, <vs
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: mv a2, a0
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: add a2, a2, a0
-; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v10, v16, v24, v0.t
+; CHECK-NEXT: vmfeq.vv v18, v8, v24, v0.t
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v10, v9, a3
+; CHECK-NEXT: vslideup.vx v18, v17, a3
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v10, v8, a1
-; CHECK-NEXT: vmv.v.v v0, v10
+; CHECK-NEXT: vslideup.vx v18, v16, a1
+; CHECK-NEXT: vmv.v.v v0, v18
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: slli a0, a0, 1
@@ -3487,8 +3479,6 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFH-NEXT: slli a1, a1, 3
; ZVFH-NEXT: sub sp, sp, a1
; ZVFH-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; ZVFH-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; ZVFH-NEXT: vmv1r.v v7, v0
; ZVFH-NEXT: addi a1, sp, 16
; ZVFH-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; ZVFH-NEXT: csrr a3, vlenb
@@ -3501,21 +3491,23 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFH-NEXT: sltu a4, a2, a5
; ZVFH-NEXT: addi a4, a4, -1
; ZVFH-NEXT: vl8re16.v v8, (a0)
-; ZVFH-NEXT: vslidedown.vx v0, v0, a1
; ZVFH-NEXT: and a4, a4, a5
+; ZVFH-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVFH-NEXT: vmv1r.v v6, v0
+; ZVFH-NEXT: vslidedown.vx v0, v0, a1
; ZVFH-NEXT: vsetvli zero, a4, e16, m8, ta, ma
-; ZVFH-NEXT: vmfeq.vv v6, v16, v24, v0.t
+; ZVFH-NEXT: vmfeq.vv v7, v16, v24, v0.t
; ZVFH-NEXT: bltu a2, a3, .LBB171_2
; ZVFH-NEXT: # %bb.1:
; ZVFH-NEXT: mv a2, a3
; ZVFH-NEXT: .LBB171_2:
-; ZVFH-NEXT: vmv1r.v v0, v7
+; ZVFH-NEXT: vmv1r.v v0, v6
; ZVFH-NEXT: addi a0, sp, 16
; ZVFH-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFH-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; ZVFH-NEXT: vmfeq.vv v16, v24, v8, v0.t
; ZVFH-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZVFH-NEXT: vslideup.vx v16, v6, a1
+; ZVFH-NEXT: vslideup.vx v16, v7, a1
; ZVFH-NEXT: vmv.v.v v0, v16
; ZVFH-NEXT: csrr a0, vlenb
; ZVFH-NEXT: slli a0, a0, 3
@@ -3539,21 +3531,13 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFHMIN-NEXT: add a1, a1, a3
; ZVFHMIN-NEXT: sub sp, sp, a1
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1b, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 27 * vlenb
-; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 1
-; ZVFHMIN-NEXT: mv a3, a1
-; ZVFHMIN-NEXT: slli a1, a1, 2
-; ZVFHMIN-NEXT: add a3, a3, a1
-; ZVFHMIN-NEXT: slli a1, a1, 1
-; ZVFHMIN-NEXT: add a1, a1, a3
-; ZVFHMIN-NEXT: add a1, sp, a1
-; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; ZVFHMIN-NEXT: vmv1r.v v24, v0
; ZVFHMIN-NEXT: vmv8r.v v0, v16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 1
; ZVFHMIN-NEXT: mv a3, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a3, a3, a1
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: add a1, a1, a3
; ZVFHMIN-NEXT: add a1, sp, a1
@@ -3565,7 +3549,7 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFHMIN-NEXT: slli a4, a3, 1
; ZVFHMIN-NEXT: add a1, a0, a1
; ZVFHMIN-NEXT: sub a6, a2, a5
-; ZVFHMIN-NEXT: vl8re16.v v24, (a1)
+; ZVFHMIN-NEXT: vl8re16.v v16, (a1)
; ZVFHMIN-NEXT: sltu a1, a2, a6
; ZVFHMIN-NEXT: addi a1, a1, -1
; ZVFHMIN-NEXT: and a6, a1, a6
@@ -3578,14 +3562,12 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFHMIN-NEXT: csrr t0, vlenb
; ZVFHMIN-NEXT: slli t0, t0, 1
; ZVFHMIN-NEXT: mv t1, t0
-; ZVFHMIN-NEXT: slli t0, t0, 2
-; ZVFHMIN-NEXT: add t1, t1, t0
-; ZVFHMIN-NEXT: slli t0, t0, 1
+; ZVFHMIN-NEXT: slli t0, t0, 3
; ZVFHMIN-NEXT: add t0, t0, t1
; ZVFHMIN-NEXT: add t0, sp, t0
; ZVFHMIN-NEXT: addi t0, t0, 16
-; ZVFHMIN-NEXT: vl1r.v v8, (t0) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vslidedown.vx v16, v8, a1
+; ZVFHMIN-NEXT: vs1r.v v24, (t0) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vslidedown.vx v24, v24, a1
; ZVFHMIN-NEXT: vl8re16.v v8, (a0)
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 1
@@ -3596,43 +3578,47 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli t0, a0, 3
+; ZVFHMIN-NEXT: add a0, t0, a0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs1r.v v16, (a0) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v8, v16, a3
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a7, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28
+; ZVFHMIN-NEXT: vslidedown.vx v8, v24, a3
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a7, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20
+; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4
; ZVFHMIN-NEXT: bltu a6, a4, .LBB171_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a6, a4
; ZVFHMIN-NEXT: .LBB171_2:
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v5, v8, v16, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, a6, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v20, v8, v24, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, a6, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a6, a0, 3
+; ZVFHMIN-NEXT: add a0, a6, a0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v7, v24, v16, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v16, v8, v24, v0.t
; ZVFHMIN-NEXT: bltu a2, a5, .LBB171_4
; ZVFHMIN-NEXT: # %bb.3:
; ZVFHMIN-NEXT: mv a2, a5
@@ -3641,28 +3627,27 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFHMIN-NEXT: csrr a5, vlenb
; ZVFHMIN-NEXT: slli a5, a5, 1
; ZVFHMIN-NEXT: mv a6, a5
-; ZVFHMIN-NEXT: slli a5, a5, 2
-; ZVFHMIN-NEXT: add a6, a6, a5
-; ZVFHMIN-NEXT: slli a5, a5, 1
+; ZVFHMIN-NEXT: slli a5, a5, 3
; ZVFHMIN-NEXT: add a5, a5, a6
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
; ZVFHMIN-NEXT: vl1r.v v8, (a5) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
+; ZVFHMIN-NEXT: vslidedown.vx v17, v8, a3
; ZVFHMIN-NEXT: sltu a5, a2, a0
; ZVFHMIN-NEXT: addi a5, a5, -1
; ZVFHMIN-NEXT: and a0, a5, a0
; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 1
; ZVFHMIN-NEXT: mv a6, a5
+; ZVFHMIN-NEXT: slli a5, a5, 1
+; ZVFHMIN-NEXT: add a6, a6, a5
; ZVFHMIN-NEXT: slli a5, a5, 3
; ZVFHMIN-NEXT: add a5, a5, a6
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 1
; ZVFHMIN-NEXT: mv a5, a0
@@ -3670,27 +3655,28 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFHMIN-NEXT: add a0, a0, a5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
+; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4
+; ZVFHMIN-NEXT: vmv1r.v v0, v17
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v9, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v8, v7
+; ZVFHMIN-NEXT: vmfeq.vv v17, v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslideup.vx v8, v5, a3
+; ZVFHMIN-NEXT: vslideup.vx v16, v20, a3
; ZVFHMIN-NEXT: bltu a2, a4, .LBB171_6
; ZVFHMIN-NEXT: # %bb.5:
; ZVFHMIN-NEXT: mv a2, a4
; ZVFHMIN-NEXT: .LBB171_6:
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 1
; ZVFHMIN-NEXT: mv a4, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a4, a4, a0
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, a0, a4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 1
; ZVFHMIN-NEXT: mv a2, a0
@@ -3703,20 +3689,18 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 1
; ZVFHMIN-NEXT: mv a2, a0
-; ZVFHMIN-NEXT: slli a0, a0, 2
-; ZVFHMIN-NEXT: add a2, a2, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, a0, a2
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v10, v16, v24, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v18, v8, v24, v0.t
; ZVFHMIN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslideup.vx v10, v9, a3
+; ZVFHMIN-NEXT: vslideup.vx v18, v17, a3
; ZVFHMIN-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZVFHMIN-NEXT: vslideup.vx v10, v8, a1
-; ZVFHMIN-NEXT: vmv.v.v v0, v10
+; ZVFHMIN-NEXT: vslideup.vx v18, v16, a1
+; ZVFHMIN-NEXT: vmv.v.v v0, v18
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: slli a0, a0, 1
@@ -4835,10 +4819,8 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK32-NEXT: addi a0, a0, 16
; CHECK32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; CHECK32-NEXT: csrr a0, vlenb
-; CHECK32-NEXT: slli a0, a0, 1
-; CHECK32-NEXT: mv a1, a0
-; CHECK32-NEXT: slli a0, a0, 3
-; CHECK32-NEXT: add a0, a0, a1
+; CHECK32-NEXT: slli a1, a0, 4
+; CHECK32-NEXT: add a0, a1, a0
; CHECK32-NEXT: add a0, sp, a0
; CHECK32-NEXT: addi a0, a0, 16
; CHECK32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
@@ -4846,22 +4828,24 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK32-NEXT: li a1, 24
; CHECK32-NEXT: mv a0, s0
; CHECK32-NEXT: call __mulsi3
-; CHECK32-NEXT: csrr a1, vlenb
-; CHECK32-NEXT: add a1, sp, a1
-; CHECK32-NEXT: addi a1, a1, 16
-; CHECK32-NEXT: vl1r.v v6, (a1) # vscale x 8-byte Folded Reload
; CHECK32-NEXT: mv a1, a0
; CHECK32-NEXT: slli a4, s0, 3
; CHECK32-NEXT: srli s4, s0, 2
; CHECK32-NEXT: srli a0, s0, 3
+; CHECK32-NEXT: csrr a2, vlenb
+; CHECK32-NEXT: add a2, sp, a2
+; CHECK32-NEXT: addi a2, a2, 16
+; CHECK32-NEXT: vl1r.v v8, (a2) # vscale x 8-byte Folded Reload
; CHECK32-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK32-NEXT: vslidedown.vx v7, v6, s4
+; CHECK32-NEXT: vslidedown.vx v25, v8, s4
+; CHECK32-NEXT: vmv1r.v v7, v25
; CHECK32-NEXT: add a2, s3, a4
-; CHECK32-NEXT: vl8re64.v v16, (a2)
+; CHECK32-NEXT: vl8re64.v v24, (a2)
; CHECK32-NEXT: slli a6, s0, 4
; CHECK32-NEXT: slli a2, s0, 1
+; CHECK32-NEXT: vmv1r.v v6, v8
; CHECK32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; CHECK32-NEXT: vslidedown.vx v0, v6, a0
+; CHECK32-NEXT: vslidedown.vx v0, v8, a0
; CHECK32-NEXT: mv a3, s1
; CHECK32-NEXT: bltu s1, a2, .LBB257_2
; CHECK32-NEXT: # %bb.1:
@@ -4869,15 +4853,18 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK32-NEXT: .LBB257_2:
; CHECK32-NEXT: add a5, s3, a1
; CHECK32-NEXT: add a1, s2, a4
-; CHECK32-NEXT: vslidedown.vx v9, v7, a0
+; CHECK32-NEXT: vslidedown.vx v16, v7, a0
; CHECK32-NEXT: csrr a4, vlenb
-; CHECK32-NEXT: slli a7, a4, 4
-; CHECK32-NEXT: add a4, a7, a4
+; CHECK32-NEXT: mv a7, a4
+; CHECK32-NEXT: slli a4, a4, 3
+; CHECK32-NEXT: add a7, a7, a4
+; CHECK32-NEXT: slli a4, a4, 1
+; CHECK32-NEXT: add a4, a4, a7
; CHECK32-NEXT: add a4, sp, a4
; CHECK32-NEXT: addi a4, a4, 16
-; CHECK32-NEXT: vs1r.v v9, (a4) # vscale x 8-byte Folded Spill
+; CHECK32-NEXT: vs1r.v v16, (a4) # vscale x 8-byte Folded Spill
; CHECK32-NEXT: add a4, s3, a6
-; CHECK32-NEXT: vl8re64.v v24, (s3)
+; CHECK32-NEXT: vl8re64.v v16, (s3)
; CHECK32-NEXT: sub a6, a3, s0
; CHECK32-NEXT: sltu a7, a3, a6
; CHECK32-NEXT: addi a7, a7, -1
@@ -4889,12 +4876,11 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK32-NEXT: addi a7, a7, 16
; CHECK32-NEXT: vl8r.v v8, (a7) # vscale x 64-byte Folded Reload
; CHECK32-NEXT: vsetvli zero, a6, e64, m8, ta, ma
-; CHECK32-NEXT: vmfeq.vv v5, v8, v16, v0.t
+; CHECK32-NEXT: vmfeq.vv v5, v8, v24, v0.t
; CHECK32-NEXT: bltu a3, s0, .LBB257_4
; CHECK32-NEXT: # %bb.3:
; CHECK32-NEXT: mv a3, s0
; CHECK32-NEXT: .LBB257_4:
-; CHECK32-NEXT: vmv1r.v v0, v6
; CHECK32-NEXT: vl8re64.v v8, (a5)
; CHECK32-NEXT: csrr a5, vlenb
; CHECK32-NEXT: slli a6, a5, 3
@@ -4902,37 +4888,34 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK32-NEXT: add a5, sp, a5
; CHECK32-NEXT: addi a5, a5, 16
; CHECK32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK32-NEXT: vmv1r.v v0, v6
; CHECK32-NEXT: csrr a5, vlenb
-; CHECK32-NEXT: slli a5, a5, 1
-; CHECK32-NEXT: mv a6, a5
-; CHECK32-NEXT: slli a5, a5, 3
-; CHECK32-NEXT: add a5, a5, a6
+; CHECK32-NEXT: slli a6, a5, 4
+; CHECK32-NEXT: add a5, a6, a5
; CHECK32-NEXT: add a5, sp, a5
; CHECK32-NEXT: addi a5, a5, 16
-; CHECK32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
+; CHECK32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
; CHECK32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; CHECK32-NEXT: vmfeq.vv v8, v16, v24, v0.t
-; CHECK32-NEXT: vl8re64.v v16, (a1)
+; CHECK32-NEXT: vmfeq.vv v24, v8, v16, v0.t
+; CHECK32-NEXT: vl8re64.v v8, (a1)
; CHECK32-NEXT: csrr a1, vlenb
; CHECK32-NEXT: add a1, sp, a1
; CHECK32-NEXT: addi a1, a1, 16
-; CHECK32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK32-NEXT: vl8re64.v v16, (a4)
+; CHECK32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; CHECK32-NEXT: vl8re64.v v8, (a4)
; CHECK32-NEXT: sub a1, s1, a2
; CHECK32-NEXT: sltu a2, s1, a1
-; CHECK32-NEXT: vl8re64.v v24, (s2)
+; CHECK32-NEXT: vl8re64.v v16, (s2)
; CHECK32-NEXT: addi a2, a2, -1
; CHECK32-NEXT: and s1, a2, a1
; CHECK32-NEXT: vsetvli zero, s4, e8, mf2, tu, ma
-; CHECK32-NEXT: vslideup.vx v8, v5, a0
+; CHECK32-NEXT: vslideup.vx v24, v5, a0
; CHECK32-NEXT: csrr a1, vlenb
-; CHECK32-NEXT: slli a1, a1, 1
-; CHECK32-NEXT: mv a2, a1
-; CHECK32-NEXT: slli a1, a1, 3
-; CHECK32-NEXT: add a1, a1, a2
+; CHECK32-NEXT: slli a2, a1, 4
+; CHECK32-NEXT: add a1, a2, a1
; CHECK32-NEXT: add a1, sp, a1
; CHECK32-NEXT: addi a1, a1, 16
-; CHECK32-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
+; CHECK32-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
; CHECK32-NEXT: mv a1, s1
; CHECK32-NEXT: bltu s1, s0, .LBB257_6
; CHECK32-NEXT: # %bb.5:
@@ -4940,9 +4923,9 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK32-NEXT: .LBB257_6:
; CHECK32-NEXT: vmv1r.v v0, v7
; CHECK32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK32-NEXT: vmfeq.vv v8, v24, v16, v0.t
+; CHECK32-NEXT: vmfeq.vv v24, v16, v8, v0.t
; CHECK32-NEXT: addi a1, sp, 16
-; CHECK32-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
+; CHECK32-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
; CHECK32-NEXT: li a1, 3
; CHECK32-NEXT: call __mulsi3
; CHECK32-NEXT: csrr a1, vlenb
@@ -4950,14 +4933,6 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK32-NEXT: add a1, a2, a1
; CHECK32-NEXT: add a1, sp, a1
; CHECK32-NEXT: addi a1, a1, 16
-; CHECK32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; CHECK32-NEXT: csrr a1, vlenb
-; CHECK32-NEXT: slli a1, a1, 1
-; CHECK32-NEXT: mv a2, a1
-; CHECK32-NEXT: slli a1, a1, 3
-; CHECK32-NEXT: add a1, a1, a2
-; CHECK32-NEXT: add a1, sp, a1
-; CHECK32-NEXT: addi a1, a1, 16
; CHECK32-NEXT: vl1r.v v9, (a1) # vscale x 8-byte Folded Reload
; CHECK32-NEXT: addi a1, sp, 16
; CHECK32-NEXT: vl1r.v v8, (a1) # vscale x 8-byte Folded Reload
@@ -4968,6 +4943,15 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK32-NEXT: addi a2, a2, -1
; CHECK32-NEXT: and a1, a2, a1
; CHECK32-NEXT: csrr a2, vlenb
+; CHECK32-NEXT: mv a3, a2
+; CHECK32-NEXT: slli a2, a2, 3
+; CHECK32-NEXT: add a3, a3, a2
+; CHECK32-NEXT: slli a2, a2, 1
+; CHECK32-NEXT: add a2, a2, a3
+; CHECK32-NEXT: add a2, sp, a2
+; CHECK32-NEXT: addi a2, a2, 16
+; CHECK32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK32-NEXT: csrr a2, vlenb
; CHECK32-NEXT: slli a3, a2, 3
; CHECK32-NEXT: add a2, a3, a2
; CHECK32-NEXT: add a2, sp, a2
@@ -5046,10 +5030,8 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK64-NEXT: addi a0, a0, 16
; CHECK64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; CHECK64-NEXT: csrr a0, vlenb
-; CHECK64-NEXT: slli a0, a0, 1
-; CHECK64-NEXT: mv a1, a0
-; CHECK64-NEXT: slli a0, a0, 3
-; CHECK64-NEXT: add a0, a0, a1
+; CHECK64-NEXT: slli a1, a0, 4
+; CHECK64-NEXT: add a0, a1, a0
; CHECK64-NEXT: add a0, sp, a0
; CHECK64-NEXT: addi a0, a0, 16
; CHECK64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
@@ -5057,22 +5039,24 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK64-NEXT: li a1, 24
; CHECK64-NEXT: mv a0, s0
; CHECK64-NEXT: call __muldi3
-; CHECK64-NEXT: csrr a1, vlenb
-; CHECK64-NEXT: add a1, sp, a1
-; CHECK64-NEXT: addi a1, a1, 16
-; CHECK64-NEXT: vl1r.v v6, (a1) # vscale x 8-byte Folded Reload
; CHECK64-NEXT: mv a1, a0
; CHECK64-NEXT: slli a4, s0, 3
; CHECK64-NEXT: srli s4, s0, 2
; CHECK64-NEXT: srli a0, s0, 3
+; CHECK64-NEXT: csrr a2, vlenb
+; CHECK64-NEXT: add a2, sp, a2
+; CHECK64-NEXT: addi a2, a2, 16
+; CHECK64-NEXT: vl1r.v v8, (a2) # vscale x 8-byte Folded Reload
; CHECK64-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK64-NEXT: vslidedown.vx v7, v6, s4
+; CHECK64-NEXT: vslidedown.vx v25, v8, s4
+; CHECK64-NEXT: vmv1r.v v7, v25
; CHECK64-NEXT: add a2, s3, a4
-; CHECK64-NEXT: vl8re64.v v16, (a2)
+; CHECK64-NEXT: vl8re64.v v24, (a2)
; CHECK64-NEXT: slli a6, s0, 4
; CHECK64-NEXT: slli a2, s0, 1
+; CHECK64-NEXT: vmv1r.v v6, v8
; CHECK64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; CHECK64-NEXT: vslidedown.vx v0, v6, a0
+; CHECK64-NEXT: vslidedown.vx v0, v8, a0
; CHECK64-NEXT: mv a3, s1
; CHECK64-NEXT: bltu s1, a2, .LBB257_2
; CHECK64-NEXT: # %bb.1:
@@ -5080,15 +5064,18 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK64-NEXT: .LBB257_2:
; CHECK64-NEXT: add a5, s3, a1
; CHECK64-NEXT: add a1, s2, a4
-; CHECK64-NEXT: vslidedown.vx v9, v7, a0
+; CHECK64-NEXT: vslidedown.vx v16, v7, a0
; CHECK64-NEXT: csrr a4, vlenb
-; CHECK64-NEXT: slli a7, a4, 4
-; CHECK64-NEXT: add a4, a7, a4
+; CHECK64-NEXT: mv a7, a4
+; CHECK64-NEXT: slli a4, a4, 3
+; CHECK64-NEXT: add a7, a7, a4
+; CHECK64-NEXT: slli a4, a4, 1
+; CHECK64-NEXT: add a4, a4, a7
; CHECK64-NEXT: add a4, sp, a4
; CHECK64-NEXT: addi a4, a4, 16
-; CHECK64-NEXT: vs1r.v v9, (a4) # vscale x 8-byte Folded Spill
+; CHECK64-NEXT: vs1r.v v16, (a4) # vscale x 8-byte Folded Spill
; CHECK64-NEXT: add a4, s3, a6
-; CHECK64-NEXT: vl8re64.v v24, (s3)
+; CHECK64-NEXT: vl8re64.v v16, (s3)
; CHECK64-NEXT: sub a6, a3, s0
; CHECK64-NEXT: sltu a7, a3, a6
; CHECK64-NEXT: addi a7, a7, -1
@@ -5100,12 +5087,11 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK64-NEXT: addi a7, a7, 16
; CHECK64-NEXT: vl8r.v v8, (a7) # vscale x 64-byte Folded Reload
; CHECK64-NEXT: vsetvli zero, a6, e64, m8, ta, ma
-; CHECK64-NEXT: vmfeq.vv v5, v8, v16, v0.t
+; CHECK64-NEXT: vmfeq.vv v5, v8, v24, v0.t
; CHECK64-NEXT: bltu a3, s0, .LBB257_4
; CHECK64-NEXT: # %bb.3:
; CHECK64-NEXT: mv a3, s0
; CHECK64-NEXT: .LBB257_4:
-; CHECK64-NEXT: vmv1r.v v0, v6
; CHECK64-NEXT: vl8re64.v v8, (a5)
; CHECK64-NEXT: csrr a5, vlenb
; CHECK64-NEXT: slli a6, a5, 3
@@ -5113,37 +5099,34 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK64-NEXT: add a5, sp, a5
; CHECK64-NEXT: addi a5, a5, 16
; CHECK64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK64-NEXT: vmv1r.v v0, v6
; CHECK64-NEXT: csrr a5, vlenb
-; CHECK64-NEXT: slli a5, a5, 1
-; CHECK64-NEXT: mv a6, a5
-; CHECK64-NEXT: slli a5, a5, 3
-; CHECK64-NEXT: add a5, a5, a6
+; CHECK64-NEXT: slli a6, a5, 4
+; CHECK64-NEXT: add a5, a6, a5
; CHECK64-NEXT: add a5, sp, a5
; CHECK64-NEXT: addi a5, a5, 16
-; CHECK64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
+; CHECK64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
; CHECK64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; CHECK64-NEXT: vmfeq.vv v8, v16, v24, v0.t
-; CHECK64-NEXT: vl8re64.v v16, (a1)
+; CHECK64-NEXT: vmfeq.vv v24, v8, v16, v0.t
+; CHECK64-NEXT: vl8re64.v v8, (a1)
; CHECK64-NEXT: csrr a1, vlenb
; CHECK64-NEXT: add a1, sp, a1
; CHECK64-NEXT: addi a1, a1, 16
-; CHECK64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK64-NEXT: vl8re64.v v16, (a4)
+; CHECK64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; CHECK64-NEXT: vl8re64.v v8, (a4)
; CHECK64-NEXT: sub a1, s1, a2
; CHECK64-NEXT: sltu a2, s1, a1
-; CHECK64-NEXT: vl8re64.v v24, (s2)
+; CHECK64-NEXT: vl8re64.v v16, (s2)
; CHECK64-NEXT: addi a2, a2, -1
; CHECK64-NEXT: and s1, a2, a1
; CHECK64-NEXT: vsetvli zero, s4, e8, mf2, tu, ma
-; CHECK64-NEXT: vslideup.vx v8, v5, a0
+; CHECK64-NEXT: vslideup.vx v24, v5, a0
; CHECK64-NEXT: csrr a1, vlenb
-; CHECK64-NEXT: slli a1, a1, 1
-; CHECK64-NEXT: mv a2, a1
-; CHECK64-NEXT: slli a1, a1, 3
-; CHECK64-NEXT: add a1, a1, a2
+; CHECK64-NEXT: slli a2, a1, 4
+; CHECK64-NEXT: add a1, a2, a1
; CHECK64-NEXT: add a1, sp, a1
; CHECK64-NEXT: addi a1, a1, 16
-; CHECK64-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
+; CHECK64-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
; CHECK64-NEXT: mv a1, s1
; CHECK64-NEXT: bltu s1, s0, .LBB257_6
; CHECK64-NEXT: # %bb.5:
@@ -5151,9 +5134,9 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK64-NEXT: .LBB257_6:
; CHECK64-NEXT: vmv1r.v v0, v7
; CHECK64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK64-NEXT: vmfeq.vv v8, v24, v16, v0.t
+; CHECK64-NEXT: vmfeq.vv v24, v16, v8, v0.t
; CHECK64-NEXT: addi a1, sp, 16
-; CHECK64-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
+; CHECK64-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
; CHECK64-NEXT: li a1, 3
; CHECK64-NEXT: call __muldi3
; CHECK64-NEXT: csrr a1, vlenb
@@ -5161,14 +5144,6 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK64-NEXT: add a1, a2, a1
; CHECK64-NEXT: add a1, sp, a1
; CHECK64-NEXT: addi a1, a1, 16
-; CHECK64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; CHECK64-NEXT: csrr a1, vlenb
-; CHECK64-NEXT: slli a1, a1, 1
-; CHECK64-NEXT: mv a2, a1
-; CHECK64-NEXT: slli a1, a1, 3
-; CHECK64-NEXT: add a1, a1, a2
-; CHECK64-NEXT: add a1, sp, a1
-; CHECK64-NEXT: addi a1, a1, 16
; CHECK64-NEXT: vl1r.v v9, (a1) # vscale x 8-byte Folded Reload
; CHECK64-NEXT: addi a1, sp, 16
; CHECK64-NEXT: vl1r.v v8, (a1) # vscale x 8-byte Folded Reload
@@ -5179,6 +5154,15 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK64-NEXT: addi a2, a2, -1
; CHECK64-NEXT: and a1, a2, a1
; CHECK64-NEXT: csrr a2, vlenb
+; CHECK64-NEXT: mv a3, a2
+; CHECK64-NEXT: slli a2, a2, 3
+; CHECK64-NEXT: add a3, a3, a2
+; CHECK64-NEXT: slli a2, a2, 1
+; CHECK64-NEXT: add a2, a2, a3
+; CHECK64-NEXT: add a2, sp, a2
+; CHECK64-NEXT: addi a2, a2, 16
+; CHECK64-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK64-NEXT: csrr a2, vlenb
; CHECK64-NEXT: slli a3, a2, 3
; CHECK64-NEXT: add a2, a3, a2
; CHECK64-NEXT: add a2, sp, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
index ceeeba466014c..5de9b5550035f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
@@ -1074,7 +1074,7 @@ define <vscale x 128 x i1> @icmp_eq_vv_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vmv1r.v v6, v0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
@@ -1088,18 +1088,18 @@ define <vscale x 128 x i1> @icmp_eq_vv_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a4
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; CHECK-NEXT: vmseq.vv v6, v16, v24, v0.t
+; CHECK-NEXT: vmseq.vv v7, v16, v24, v0.t
; CHECK-NEXT: bltu a3, a1, .LBB96_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: .LBB96_2:
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vv v16, v24, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vmv1r.v v8, v6
+; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -1115,7 +1115,7 @@ define <vscale x 128 x i1> @icmp_eq_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b,
; CHECK-LABEL: icmp_eq_vx_nxv128i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
@@ -1124,16 +1124,16 @@ define <vscale x 128 x i1> @icmp_eq_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b,
; CHECK-NEXT: addi a4, a4, -1
; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-NEXT: vmseq.vx v25, v16, a0, v0.t
+; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a1, .LBB97_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB97_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vx v16, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vmv1r.v v8, v24
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 128 x i8> poison, i8 %b, i8 0
%vb = shufflevector <vscale x 128 x i8> %elt.head, <vscale x 128 x i8> poison, <vscale x 128 x i32> zeroinitializer
@@ -1145,7 +1145,7 @@ define <vscale x 128 x i1> @icmp_eq_vx_swap_nxv128i8(<vscale x 128 x i8> %va, i8
; CHECK-LABEL: icmp_eq_vx_swap_nxv128i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
@@ -1154,16 +1154,16 @@ define <vscale x 128 x i1> @icmp_eq_vx_swap_nxv128i8(<vscale x 128 x i8> %va, i8
; CHECK-NEXT: addi a4, a4, -1
; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-NEXT: vmseq.vx v25, v16, a0, v0.t
+; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a1, .LBB98_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB98_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vx v16, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vmv1r.v v8, v25
+; CHECK-NEXT: vmv1r.v v8, v24
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 128 x i8> poison, i8 %b, i8 0
%vb = shufflevector <vscale x 128 x i8> %elt.head, <vscale x 128 x i8> poison, <vscale x 128 x i32> zeroinitializer
@@ -2203,8 +2203,6 @@ define <vscale x 32 x i1> @icmp_eq_vv_nxv32i32(<vscale x 32 x i32> %va, <vscale
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a3, vlenb
@@ -2217,21 +2215,23 @@ define <vscale x 32 x i1> @icmp_eq_vv_nxv32i32(<vscale x 32 x i32> %va, <vscale
; CHECK-NEXT: sltu a4, a2, a5
; CHECK-NEXT: addi a4, a4, -1
; CHECK-NEXT: vl8re32.v v8, (a0)
-; CHECK-NEXT: vslidedown.vx v0, v0, a1
; CHECK-NEXT: and a4, a4, a5
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v6, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a1
; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
-; CHECK-NEXT: vmseq.vv v6, v16, v24, v0.t
+; CHECK-NEXT: vmseq.vv v7, v16, v24, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB189_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB189_2:
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vmseq.vv v16, v24, v8, v0.t
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v16, v6, a1
+; CHECK-NEXT: vslideup.vx v16, v7, a1
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
@@ -2247,27 +2247,27 @@ define <vscale x 32 x i1> @icmp_eq_vv_nxv32i32(<vscale x 32 x i32> %va, <vscale
define <vscale x 32 x i1> @icmp_eq_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_eq_vx_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: srli a2, a3, 2
; CHECK-NEXT: slli a3, a3, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a4, a1, a3
; CHECK-NEXT: sltu a5, a1, a4
; CHECK-NEXT: addi a5, a5, -1
; CHECK-NEXT: and a4, a5, a4
; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
-; CHECK-NEXT: vmseq.vx v25, v16, a0, v0.t
+; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a3, .LBB190_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, a3
; CHECK-NEXT: .LBB190_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vmseq.vx v16, v8, a0, v0.t
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v16, v25, a2
+; CHECK-NEXT: vslideup.vx v16, v24, a2
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i32> poison, i32 %b, i32 0
@@ -2279,27 +2279,27 @@ define <vscale x 32 x i1> @icmp_eq_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b,
define <vscale x 32 x i1> @icmp_eq_vx_swap_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: icmp_eq_vx_swap_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: srli a2, a3, 2
; CHECK-NEXT: slli a3, a3, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a4, a1, a3
; CHECK-NEXT: sltu a5, a1, a4
; CHECK-NEXT: addi a5, a5, -1
; CHECK-NEXT: and a4, a5, a4
; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
-; CHECK-NEXT: vmseq.vx v25, v16, a0, v0.t
+; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a3, .LBB191_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, a3
; CHECK-NEXT: .LBB191_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; CHECK-NEXT: vmseq.vx v16, v8, a0, v0.t
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v16, v25, a2
+; CHECK-NEXT: vslideup.vx v16, v24, a2
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i32> poison, i32 %b, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
index 24e859d82a249..5bb46c3c3627c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
@@ -4808,18 +4808,18 @@ define void @sink_splat_vp_icmp(ptr nocapture %x, i32 signext %y, <4 x i1> %m, i
; CHECK-LABEL: sink_splat_vp_icmp:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a3, 1
; CHECK-NEXT: add a3, a0, a3
-; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: .LBB102_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vle32.v v10, (a0)
-; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma
-; CHECK-NEXT: vmseq.vx v0, v10, a1, v0.t
+; CHECK-NEXT: vmseq.vx v0, v9, a1, v0.t
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vse32.v v9, (a0), v0.t
+; CHECK-NEXT: vse32.v v8, (a0), v0.t
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bne a0, a3, .LBB102_1
; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
@@ -4847,18 +4847,18 @@ define void @sink_splat_vp_fcmp(ptr nocapture %x, float %y, <4 x i1> %m, i32 zer
; CHECK-LABEL: sink_splat_vp_fcmp:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a2, 1
; CHECK-NEXT: add a2, a0, a2
-; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: .LBB103_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vle32.v v10, (a0)
-; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; CHECK-NEXT: vmfeq.vf v0, v10, fa0, v0.t
+; CHECK-NEXT: vmfeq.vf v0, v9, fa0, v0.t
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vse32.v v9, (a0), v0.t
+; CHECK-NEXT: vse32.v v8, (a0), v0.t
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: bne a0, a2, .LBB103_1
; CHECK-NEXT: # %bb.2: # %for.cond.cleanup
diff --git a/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll b/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
index 6381887a1a2f9..16f373e148bbf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
@@ -591,8 +591,6 @@ define <vscale x 3 x double> @strided_vpload_nxv3f64_allones_mask(ptr %ptr, i32
define <vscale x 16 x double> @strided_load_nxv16f64(ptr %ptr, i64 %stride, <vscale x 16 x i1> %mask, i32 zeroext %evl) {
; CHECK-RV32-LABEL: strided_load_nxv16f64:
; CHECK-RV32: # %bb.0:
-; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-RV32-NEXT: vmv1r.v v9, v0
; CHECK-RV32-NEXT: csrr a4, vlenb
; CHECK-RV32-NEXT: sub a2, a3, a4
; CHECK-RV32-NEXT: sltu a5, a3, a2
@@ -604,21 +602,19 @@ define <vscale x 16 x double> @strided_load_nxv16f64(ptr %ptr, i64 %stride, <vsc
; CHECK-RV32-NEXT: .LBB55_2:
; CHECK-RV32-NEXT: mul a5, a3, a1
; CHECK-RV32-NEXT: srli a4, a4, 3
-; CHECK-RV32-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vx v8, v9, a4
; CHECK-RV32-NEXT: add a5, a0, a5
-; CHECK-RV32-NEXT: vmv1r.v v0, v8
+; CHECK-RV32-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
+; CHECK-RV32-NEXT: vmv1r.v v8, v0
+; CHECK-RV32-NEXT: vslidedown.vx v0, v0, a4
; CHECK-RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v16, (a5), a1, v0.t
-; CHECK-RV32-NEXT: vmv1r.v v0, v9
+; CHECK-RV32-NEXT: vmv1r.v v0, v8
; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v8, (a0), a1, v0.t
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: strided_load_nxv16f64:
; CHECK-RV64: # %bb.0:
-; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-RV64-NEXT: vmv1r.v v9, v0
; CHECK-RV64-NEXT: csrr a4, vlenb
; CHECK-RV64-NEXT: sub a3, a2, a4
; CHECK-RV64-NEXT: sltu a5, a2, a3
@@ -630,13 +626,13 @@ define <vscale x 16 x double> @strided_load_nxv16f64(ptr %ptr, i64 %stride, <vsc
; CHECK-RV64-NEXT: .LBB55_2:
; CHECK-RV64-NEXT: mul a5, a2, a1
; CHECK-RV64-NEXT: srli a4, a4, 3
-; CHECK-RV64-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vx v8, v9, a4
; CHECK-RV64-NEXT: add a5, a0, a5
-; CHECK-RV64-NEXT: vmv1r.v v0, v8
+; CHECK-RV64-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
+; CHECK-RV64-NEXT: vmv1r.v v8, v0
+; CHECK-RV64-NEXT: vslidedown.vx v0, v0, a4
; CHECK-RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v16, (a5), a1, v0.t
-; CHECK-RV64-NEXT: vmv1r.v v0, v9
+; CHECK-RV64-NEXT: vmv1r.v v0, v8
; CHECK-RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v8, (a0), a1, v0.t
; CHECK-RV64-NEXT: ret
@@ -694,7 +690,7 @@ define <vscale x 16 x double> @strided_load_nxv17f64(ptr %ptr, i64 %stride, <vsc
; CHECK-RV32-LABEL: strided_load_nxv17f64:
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-RV32-NEXT: vmv1r.v v8, v0
+; CHECK-RV32-NEXT: vmv1r.v v9, v0
; CHECK-RV32-NEXT: csrr a2, vlenb
; CHECK-RV32-NEXT: slli a7, a2, 1
; CHECK-RV32-NEXT: mv a6, a3
@@ -714,9 +710,9 @@ define <vscale x 16 x double> @strided_load_nxv17f64(ptr %ptr, i64 %stride, <vsc
; CHECK-RV32-NEXT: mul t1, a5, a1
; CHECK-RV32-NEXT: srli t2, a2, 3
; CHECK-RV32-NEXT: sub a7, a3, a7
-; CHECK-RV32-NEXT: vsetvli t3, zero, e8, mf4, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vx v0, v8, t2
; CHECK-RV32-NEXT: add t1, a0, t1
+; CHECK-RV32-NEXT: vsetvli t3, zero, e8, mf4, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v0, v9, t2
; CHECK-RV32-NEXT: vsetvli zero, t0, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v16, (t1), a1, v0.t
; CHECK-RV32-NEXT: sltu a3, a3, a7
@@ -728,12 +724,12 @@ define <vscale x 16 x double> @strided_load_nxv17f64(ptr %ptr, i64 %stride, <vsc
; CHECK-RV32-NEXT: .LBB57_6:
; CHECK-RV32-NEXT: mul a6, a6, a1
; CHECK-RV32-NEXT: srli a2, a2, 2
-; CHECK-RV32-NEXT: vsetvli a7, zero, e8, mf2, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vx v0, v8, a2
; CHECK-RV32-NEXT: add a6, a0, a6
+; CHECK-RV32-NEXT: vsetvli a7, zero, e8, mf2, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vx v0, v9, a2
; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v24, (a6), a1, v0.t
-; CHECK-RV32-NEXT: vmv1r.v v0, v8
+; CHECK-RV32-NEXT: vmv1r.v v0, v9
; CHECK-RV32-NEXT: vsetvli zero, a5, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v8, (a0), a1, v0.t
; CHECK-RV32-NEXT: vs1r.v v24, (a4)
@@ -742,7 +738,7 @@ define <vscale x 16 x double> @strided_load_nxv17f64(ptr %ptr, i64 %stride, <vsc
; CHECK-RV64-LABEL: strided_load_nxv17f64:
; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-RV64-NEXT: vmv1r.v v8, v0
+; CHECK-RV64-NEXT: vmv1r.v v9, v0
; CHECK-RV64-NEXT: csrr a4, vlenb
; CHECK-RV64-NEXT: slli a7, a4, 1
; CHECK-RV64-NEXT: mv a6, a2
@@ -762,9 +758,9 @@ define <vscale x 16 x double> @strided_load_nxv17f64(ptr %ptr, i64 %stride, <vsc
; CHECK-RV64-NEXT: mul t1, a5, a1
; CHECK-RV64-NEXT: srli t2, a4, 3
; CHECK-RV64-NEXT: sub a7, a2, a7
-; CHECK-RV64-NEXT: vsetvli t3, zero, e8, mf4, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vx v0, v8, t2
; CHECK-RV64-NEXT: add t1, a0, t1
+; CHECK-RV64-NEXT: vsetvli t3, zero, e8, mf4, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v0, v9, t2
; CHECK-RV64-NEXT: vsetvli zero, t0, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v16, (t1), a1, v0.t
; CHECK-RV64-NEXT: sltu a2, a2, a7
@@ -776,12 +772,12 @@ define <vscale x 16 x double> @strided_load_nxv17f64(ptr %ptr, i64 %stride, <vsc
; CHECK-RV64-NEXT: .LBB57_6:
; CHECK-RV64-NEXT: mul a6, a6, a1
; CHECK-RV64-NEXT: srli a4, a4, 2
-; CHECK-RV64-NEXT: vsetvli a7, zero, e8, mf2, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vx v0, v8, a4
; CHECK-RV64-NEXT: add a6, a0, a6
+; CHECK-RV64-NEXT: vsetvli a7, zero, e8, mf2, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vx v0, v9, a4
; CHECK-RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v24, (a6), a1, v0.t
-; CHECK-RV64-NEXT: vmv1r.v v0, v8
+; CHECK-RV64-NEXT: vmv1r.v v0, v9
; CHECK-RV64-NEXT: vsetvli zero, a5, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v8, (a0), a1, v0.t
; CHECK-RV64-NEXT: vs1r.v v24, (a3)
diff --git a/llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll b/llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
index 2ec89888af077..dc42753476d16 100644
--- a/llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
@@ -495,11 +495,11 @@ define void @strided_store_nxv16f64(<vscale x 16 x double> %v, ptr %ptr, i32 sig
; CHECK-NEXT: mul a4, a4, a1
; CHECK-NEXT: srli a3, a3, 3
; CHECK-NEXT: sltu a2, a2, a5
-; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-NEXT: add a0, a0, a4
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a5
-; CHECK-NEXT: add a0, a0, a4
+; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vsse64.v v16, (a0), a1, v0.t
; CHECK-NEXT: ret
@@ -535,8 +535,6 @@ define void @strided_store_nxv16f64_allones_mask(<vscale x 16 x double> %v, ptr
define void @strided_store_nxv17f64(<vscale x 17 x double> %v, ptr %ptr, i32 signext %stride, <vscale x 17 x i1> %mask, i32 zeroext %evl) {
; CHECK-LABEL: strided_store_nxv17f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a6, a4, 1
; CHECK-NEXT: mv a5, a3
@@ -549,7 +547,6 @@ define void @strided_store_nxv17f64(<vscale x 17 x double> %v, ptr %ptr, i32 sig
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a7, a4
; CHECK-NEXT: .LBB48_4:
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a7, e64, m8, ta, ma
; CHECK-NEXT: vsse64.v v8, (a1), a2, v0.t
@@ -557,8 +554,9 @@ define void @strided_store_nxv17f64(<vscale x 17 x double> %v, ptr %ptr, i32 sig
; CHECK-NEXT: mul a7, a7, a2
; CHECK-NEXT: srli t0, a4, 3
; CHECK-NEXT: sub a6, a3, a6
+; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vsetvli t1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v7, t0
+; CHECK-NEXT: vslidedown.vx v0, v0, t0
; CHECK-NEXT: sltu t0, a5, a0
; CHECK-NEXT: add a7, a1, a7
; CHECK-NEXT: sltu a3, a3, a6
@@ -574,9 +572,9 @@ define void @strided_store_nxv17f64(<vscale x 17 x double> %v, ptr %ptr, i32 sig
; CHECK-NEXT: .LBB48_6:
; CHECK-NEXT: mul a3, a5, a2
; CHECK-NEXT: srli a4, a4, 2
-; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v7, a4
; CHECK-NEXT: add a1, a1, a3
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v8, a4
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vsse64.v v24, (a1), a2, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll
index 4ac59b412b45c..bb5417c5ed9c6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/umulo-sdnode.ll
@@ -5,10 +5,10 @@ define <vscale x 1 x i8> @umulo_nxv1i8(<vscale x 1 x i8> %x, <vscale x 1 x i8> %
; CHECK-LABEL: umulo_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vmulhu.vv v10, v8, v9
-; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v10, v8, v9
+; CHECK-NEXT: vmulhu.vv v8, v8, v9
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 1 x i8>, <vscale x 1 x i1> } @llvm.umul.with.overflow.nxv1i8(<vscale x 1 x i8> %x, <vscale x 1 x i8> %y)
%b = extractvalue { <vscale x 1 x i8>, <vscale x 1 x i1> } %a, 0
@@ -21,10 +21,10 @@ define <vscale x 2 x i8> @umulo_nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %
; CHECK-LABEL: umulo_nxv2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmulhu.vv v10, v8, v9
-; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v10, v8, v9
+; CHECK-NEXT: vmulhu.vv v8, v8, v9
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 2 x i8>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y)
%b = extractvalue { <vscale x 2 x i8>, <vscale x 2 x i1> } %a, 0
@@ -37,10 +37,10 @@ define <vscale x 4 x i8> @umulo_nxv4i8(<vscale x 4 x i8> %x, <vscale x 4 x i8> %
; CHECK-LABEL: umulo_nxv4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmulhu.vv v10, v8, v9
-; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v10, v8, v9
+; CHECK-NEXT: vmulhu.vv v8, v8, v9
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 4 x i8>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i8(<vscale x 4 x i8> %x, <vscale x 4 x i8> %y)
%b = extractvalue { <vscale x 4 x i8>, <vscale x 4 x i1> } %a, 0
@@ -53,10 +53,10 @@ define <vscale x 8 x i8> @umulo_nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %
; CHECK-LABEL: umulo_nxv8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vmulhu.vv v10, v8, v9
-; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v10, v8, v9
+; CHECK-NEXT: vmulhu.vv v8, v8, v9
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 8 x i8>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y)
%b = extractvalue { <vscale x 8 x i8>, <vscale x 8 x i1> } %a, 0
@@ -69,10 +69,10 @@ define <vscale x 16 x i8> @umulo_nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i
; CHECK-LABEL: umulo_nxv16i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmulhu.vv v12, v8, v10
-; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vmul.vv v8, v8, v10
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v12, v8, v10
+; CHECK-NEXT: vmulhu.vv v8, v8, v10
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 16 x i8>, <vscale x 16 x i1> } @llvm.umul.with.overflow.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)
%b = extractvalue { <vscale x 16 x i8>, <vscale x 16 x i1> } %a, 0
@@ -85,10 +85,10 @@ define <vscale x 32 x i8> @umulo_nxv32i8(<vscale x 32 x i8> %x, <vscale x 32 x i
; CHECK-LABEL: umulo_nxv32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; CHECK-NEXT: vmulhu.vv v16, v8, v12
-; CHECK-NEXT: vmsne.vi v0, v16, 0
-; CHECK-NEXT: vmul.vv v8, v8, v12
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v16, v8, v12
+; CHECK-NEXT: vmulhu.vv v8, v8, v12
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v16, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 32 x i8>, <vscale x 32 x i1> } @llvm.umul.with.overflow.nxv32i8(<vscale x 32 x i8> %x, <vscale x 32 x i8> %y)
%b = extractvalue { <vscale x 32 x i8>, <vscale x 32 x i1> } %a, 0
@@ -101,10 +101,10 @@ define <vscale x 64 x i8> @umulo_nxv64i8(<vscale x 64 x i8> %x, <vscale x 64 x i
; CHECK-LABEL: umulo_nxv64i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmulhu.vv v24, v8, v16
-; CHECK-NEXT: vmsne.vi v0, v24, 0
-; CHECK-NEXT: vmul.vv v8, v8, v16
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v24, v8, v16
+; CHECK-NEXT: vmulhu.vv v8, v8, v16
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v24, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 64 x i8>, <vscale x 64 x i1> } @llvm.umul.with.overflow.nxv64i8(<vscale x 64 x i8> %x, <vscale x 64 x i8> %y)
%b = extractvalue { <vscale x 64 x i8>, <vscale x 64 x i1> } %a, 0
@@ -117,10 +117,10 @@ define <vscale x 1 x i16> @umulo_nxv1i16(<vscale x 1 x i16> %x, <vscale x 1 x i1
; CHECK-LABEL: umulo_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vmulhu.vv v10, v8, v9
-; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v10, v8, v9
+; CHECK-NEXT: vmulhu.vv v8, v8, v9
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 1 x i16>, <vscale x 1 x i1> } @llvm.umul.with.overflow.nxv1i16(<vscale x 1 x i16> %x, <vscale x 1 x i16> %y)
%b = extractvalue { <vscale x 1 x i16>, <vscale x 1 x i1> } %a, 0
@@ -133,10 +133,10 @@ define <vscale x 2 x i16> @umulo_nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i1
; CHECK-LABEL: umulo_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vmulhu.vv v10, v8, v9
-; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v10, v8, v9
+; CHECK-NEXT: vmulhu.vv v8, v8, v9
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 2 x i16>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y)
%b = extractvalue { <vscale x 2 x i16>, <vscale x 2 x i1> } %a, 0
@@ -149,10 +149,10 @@ define <vscale x 4 x i16> @umulo_nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i1
; CHECK-LABEL: umulo_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT: vmulhu.vv v10, v8, v9
-; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v10, v8, v9
+; CHECK-NEXT: vmulhu.vv v8, v8, v9
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 4 x i16>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y)
%b = extractvalue { <vscale x 4 x i16>, <vscale x 4 x i1> } %a, 0
@@ -165,10 +165,10 @@ define <vscale x 8 x i16> @umulo_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i1
; CHECK-LABEL: umulo_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmulhu.vv v12, v8, v10
-; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vmul.vv v8, v8, v10
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v12, v8, v10
+; CHECK-NEXT: vmulhu.vv v8, v8, v10
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 8 x i16>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)
%b = extractvalue { <vscale x 8 x i16>, <vscale x 8 x i1> } %a, 0
@@ -181,10 +181,10 @@ define <vscale x 16 x i16> @umulo_nxv16i16(<vscale x 16 x i16> %x, <vscale x 16
; CHECK-LABEL: umulo_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT: vmulhu.vv v16, v8, v12
-; CHECK-NEXT: vmsne.vi v0, v16, 0
-; CHECK-NEXT: vmul.vv v8, v8, v12
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v16, v8, v12
+; CHECK-NEXT: vmulhu.vv v8, v8, v12
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v16, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 16 x i16>, <vscale x 16 x i1> } @llvm.umul.with.overflow.nxv16i16(<vscale x 16 x i16> %x, <vscale x 16 x i16> %y)
%b = extractvalue { <vscale x 16 x i16>, <vscale x 16 x i1> } %a, 0
@@ -197,10 +197,10 @@ define <vscale x 32 x i16> @umulo_nxv32i16(<vscale x 32 x i16> %x, <vscale x 32
; CHECK-LABEL: umulo_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; CHECK-NEXT: vmulhu.vv v24, v8, v16
-; CHECK-NEXT: vmsne.vi v0, v24, 0
-; CHECK-NEXT: vmul.vv v8, v8, v16
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v24, v8, v16
+; CHECK-NEXT: vmulhu.vv v8, v8, v16
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v24, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 32 x i16>, <vscale x 32 x i1> } @llvm.umul.with.overflow.nxv32i16(<vscale x 32 x i16> %x, <vscale x 32 x i16> %y)
%b = extractvalue { <vscale x 32 x i16>, <vscale x 32 x i1> } %a, 0
@@ -213,10 +213,10 @@ define <vscale x 1 x i32> @umulo_nxv1i32(<vscale x 1 x i32> %x, <vscale x 1 x i3
; CHECK-LABEL: umulo_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vmulhu.vv v10, v8, v9
-; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v10, v8, v9
+; CHECK-NEXT: vmulhu.vv v8, v8, v9
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 1 x i32>, <vscale x 1 x i1> } @llvm.umul.with.overflow.nxv1i32(<vscale x 1 x i32> %x, <vscale x 1 x i32> %y)
%b = extractvalue { <vscale x 1 x i32>, <vscale x 1 x i1> } %a, 0
@@ -229,10 +229,10 @@ define <vscale x 2 x i32> @umulo_nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i3
; CHECK-LABEL: umulo_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT: vmulhu.vv v10, v8, v9
-; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v10, v8, v9
+; CHECK-NEXT: vmulhu.vv v8, v8, v9
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y)
%b = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 0
@@ -245,10 +245,10 @@ define <vscale x 4 x i32> @umulo_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i3
; CHECK-LABEL: umulo_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT: vmulhu.vv v12, v8, v10
-; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vmul.vv v8, v8, v10
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v12, v8, v10
+; CHECK-NEXT: vmulhu.vv v8, v8, v10
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 4 x i32>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)
%b = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i1> } %a, 0
@@ -261,10 +261,10 @@ define <vscale x 8 x i32> @umulo_nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i3
; CHECK-LABEL: umulo_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmulhu.vv v16, v8, v12
-; CHECK-NEXT: vmsne.vi v0, v16, 0
-; CHECK-NEXT: vmul.vv v8, v8, v12
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v16, v8, v12
+; CHECK-NEXT: vmulhu.vv v8, v8, v12
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v16, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 8 x i32>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y)
%b = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i1> } %a, 0
@@ -277,10 +277,10 @@ define <vscale x 16 x i32> @umulo_nxv16i32(<vscale x 16 x i32> %x, <vscale x 16
; CHECK-LABEL: umulo_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmulhu.vv v24, v8, v16
-; CHECK-NEXT: vmsne.vi v0, v24, 0
-; CHECK-NEXT: vmul.vv v8, v8, v16
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v24, v8, v16
+; CHECK-NEXT: vmulhu.vv v8, v8, v16
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v24, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 16 x i32>, <vscale x 16 x i1> } @llvm.umul.with.overflow.nxv16i32(<vscale x 16 x i32> %x, <vscale x 16 x i32> %y)
%b = extractvalue { <vscale x 16 x i32>, <vscale x 16 x i1> } %a, 0
@@ -293,10 +293,10 @@ define <vscale x 1 x i64> @umulo_nxv1i64(<vscale x 1 x i64> %x, <vscale x 1 x i6
; CHECK-LABEL: umulo_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; CHECK-NEXT: vmulhu.vv v10, v8, v9
-; CHECK-NEXT: vmsne.vi v0, v10, 0
-; CHECK-NEXT: vmul.vv v8, v8, v9
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v10, v8, v9
+; CHECK-NEXT: vmulhu.vv v8, v8, v9
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 1 x i64>, <vscale x 1 x i1> } @llvm.umul.with.overflow.nxv1i64(<vscale x 1 x i64> %x, <vscale x 1 x i64> %y)
%b = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i1> } %a, 0
@@ -309,10 +309,10 @@ define <vscale x 2 x i64> @umulo_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i6
; CHECK-LABEL: umulo_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-NEXT: vmulhu.vv v12, v8, v10
-; CHECK-NEXT: vmsne.vi v0, v12, 0
-; CHECK-NEXT: vmul.vv v8, v8, v10
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v12, v8, v10
+; CHECK-NEXT: vmulhu.vv v8, v8, v10
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 2 x i64>, <vscale x 2 x i1> } @llvm.umul.with.overflow.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y)
%b = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i1> } %a, 0
@@ -325,10 +325,10 @@ define <vscale x 4 x i64> @umulo_nxv4i64(<vscale x 4 x i64> %x, <vscale x 4 x i6
; CHECK-LABEL: umulo_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-NEXT: vmulhu.vv v16, v8, v12
-; CHECK-NEXT: vmsne.vi v0, v16, 0
-; CHECK-NEXT: vmul.vv v8, v8, v12
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v16, v8, v12
+; CHECK-NEXT: vmulhu.vv v8, v8, v12
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v16, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 4 x i64>, <vscale x 4 x i1> } @llvm.umul.with.overflow.nxv4i64(<vscale x 4 x i64> %x, <vscale x 4 x i64> %y)
%b = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i1> } %a, 0
@@ -341,10 +341,10 @@ define <vscale x 8 x i64> @umulo_nxv8i64(<vscale x 8 x i64> %x, <vscale x 8 x i6
; CHECK-LABEL: umulo_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-NEXT: vmulhu.vv v24, v8, v16
-; CHECK-NEXT: vmsne.vi v0, v24, 0
-; CHECK-NEXT: vmul.vv v8, v8, v16
-; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: vmul.vv v24, v8, v16
+; CHECK-NEXT: vmulhu.vv v8, v8, v16
+; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vmerge.vim v8, v24, 0, v0
; CHECK-NEXT: ret
%a = call { <vscale x 8 x i64>, <vscale x 8 x i1> } @llvm.umul.with.overflow.nxv8i64(<vscale x 8 x i64> %x, <vscale x 8 x i64> %y)
%b = extractvalue { <vscale x 8 x i64>, <vscale x 8 x i1> } %a, 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
index c64b755051898..f850fb822507c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
@@ -546,7 +546,7 @@ define <vscale x 128 x i8> @vadd_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
; CHECK-LABEL: vadd_vi_nxv128i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
@@ -560,7 +560,7 @@ define <vscale x 128 x i8> @vadd_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: .LBB50_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
@@ -1299,11 +1299,11 @@ define <vscale x 16 x i32> @vadd_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va, i
define <vscale x 32 x i32> @vadd_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vadd_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2
@@ -1367,11 +1367,11 @@ define <vscale x 32 x i32> @vadd_vi_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, <v
;
; RV64-LABEL: vadd_vi_nxv32i32_evl_nx8:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: srli a2, a0, 2
; RV64-NEXT: slli a1, a0, 1
+; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: vslidedown.vx v0, v0, a2
; RV64-NEXT: sub a2, a0, a1
; RV64-NEXT: sltu a3, a0, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
index 5c04a09c9953b..93a626e355a6b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
@@ -13,13 +13,12 @@ define {<16 x i1>, <16 x i1>} @vector_deinterleave_v16i1_v32i1(<32 x i1> %vec) {
; CHECK-NEXT: vmerge.vim v9, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v10, v9, 0
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vnsrl.wi v9, v9, 8
+; CHECK-NEXT: vnsrl.wi v10, v9, 0
; CHECK-NEXT: vnsrl.wi v11, v8, 0
+; CHECK-NEXT: vnsrl.wi v9, v9, 8
; CHECK-NEXT: vnsrl.wi v8, v8, 8
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vslideup.vi v10, v11, 8
@@ -101,29 +100,27 @@ define {<4 x i64>, <4 x i64>} @vector_deinterleave_v4i64_v8i64(<8 x i64> %vec) {
; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; V-NEXT: vmv.v.i v0, 8
; V-NEXT: vsetivli zero, 4, e64, m4, ta, ma
-; V-NEXT: vslidedown.vi v16, v8, 4
+; V-NEXT: vslidedown.vi v12, v8, 4
; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; V-NEXT: vmv.v.i v10, 2
-; V-NEXT: vmv2r.v v12, v8
-; V-NEXT: vmv.v.i v11, 12
+; V-NEXT: vmv.v.i v17, 2
+; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
+; V-NEXT: vslideup.vi v10, v12, 2
+; V-NEXT: vslideup.vi v10, v12, 1, v0.t
+; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; V-NEXT: vmv.v.i v18, 12
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; V-NEXT: vslideup.vi v14, v16, 2
-; V-NEXT: vslideup.vi v14, v16, 1, v0.t
-; V-NEXT: vmv1r.v v0, v10
-; V-NEXT: vslidedown.vi v12, v8, 1, v0.t
-; V-NEXT: vmv1r.v v0, v11
-; V-NEXT: vmerge.vvm v12, v12, v14, v0
; V-NEXT: vslidedown.vi v14, v8, 1
-; V-NEXT: vmv1r.v v0, v10
+; V-NEXT: vmv1r.v v0, v17
; V-NEXT: vslidedown.vi v14, v8, 2, v0.t
+; V-NEXT: vslidedown.vi v8, v8, 1, v0.t
; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; V-NEXT: vmv.v.i v0, 4
-; V-NEXT: vmv2r.v v8, v16
+; V-NEXT: vmv2r.v v16, v12
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; V-NEXT: vslideup.vi v8, v16, 1, v0.t
-; V-NEXT: vmv1r.v v0, v11
-; V-NEXT: vmerge.vvm v10, v14, v8, v0
-; V-NEXT: vmv2r.v v8, v12
+; V-NEXT: vslideup.vi v16, v12, 1, v0.t
+; V-NEXT: vmv1r.v v0, v18
+; V-NEXT: vmerge.vvm v8, v8, v10, v0
+; V-NEXT: vmerge.vvm v10, v14, v16, v0
; V-NEXT: ret
;
; ZIP-LABEL: vector_deinterleave_v4i64_v8i64:
@@ -150,17 +147,17 @@ define {<8 x i64>, <8 x i64>} @vector_deinterleave_v8i64_v16i64(<16 x i64> %vec)
; V-NEXT: vmv.v.i v0, -16
; V-NEXT: vmv.s.x v12, a0
; V-NEXT: li a0, 170
-; V-NEXT: vadd.vv v13, v16, v16
-; V-NEXT: vmv.s.x v20, a0
-; V-NEXT: vadd.vi v21, v13, -8
+; V-NEXT: vadd.vv v20, v16, v16
+; V-NEXT: vmv.s.x v21, a0
; V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; V-NEXT: vcompress.vm v16, v8, v12
+; V-NEXT: vcompress.vm v12, v8, v21
; V-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; V-NEXT: vadd.vi v22, v13, -7
+; V-NEXT: vadd.vi v8, v20, -8
+; V-NEXT: vadd.vi v9, v20, -7
; V-NEXT: vsetvli zero, zero, e64, m4, ta, mu
-; V-NEXT: vcompress.vm v12, v8, v20
-; V-NEXT: vrgatherei16.vv v16, v24, v21, v0.t
-; V-NEXT: vrgatherei16.vv v12, v24, v22, v0.t
+; V-NEXT: vrgatherei16.vv v16, v24, v8, v0.t
+; V-NEXT: vrgatherei16.vv v12, v24, v9, v0.t
; V-NEXT: vmv.v.v v8, v16
; V-NEXT: ret
;
@@ -485,29 +482,27 @@ define {<4 x double>, <4 x double>} @vector_deinterleave_v4f64_v8f64(<8 x double
; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; V-NEXT: vmv.v.i v0, 8
; V-NEXT: vsetivli zero, 4, e64, m4, ta, ma
-; V-NEXT: vslidedown.vi v16, v8, 4
+; V-NEXT: vslidedown.vi v12, v8, 4
+; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; V-NEXT: vmv.v.i v17, 2
+; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
+; V-NEXT: vslideup.vi v10, v12, 2
+; V-NEXT: vslideup.vi v10, v12, 1, v0.t
; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; V-NEXT: vmv.v.i v10, 2
-; V-NEXT: vmv2r.v v12, v8
-; V-NEXT: vmv.v.i v11, 12
+; V-NEXT: vmv.v.i v18, 12
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; V-NEXT: vslideup.vi v14, v16, 2
-; V-NEXT: vslideup.vi v14, v16, 1, v0.t
-; V-NEXT: vmv1r.v v0, v10
-; V-NEXT: vslidedown.vi v12, v8, 1, v0.t
-; V-NEXT: vmv1r.v v0, v11
-; V-NEXT: vmerge.vvm v12, v12, v14, v0
; V-NEXT: vslidedown.vi v14, v8, 1
-; V-NEXT: vmv1r.v v0, v10
+; V-NEXT: vmv1r.v v0, v17
; V-NEXT: vslidedown.vi v14, v8, 2, v0.t
+; V-NEXT: vslidedown.vi v8, v8, 1, v0.t
; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; V-NEXT: vmv.v.i v0, 4
-; V-NEXT: vmv2r.v v8, v16
+; V-NEXT: vmv2r.v v16, v12
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
-; V-NEXT: vslideup.vi v8, v16, 1, v0.t
-; V-NEXT: vmv1r.v v0, v11
-; V-NEXT: vmerge.vvm v10, v14, v8, v0
-; V-NEXT: vmv2r.v v8, v12
+; V-NEXT: vslideup.vi v16, v12, 1, v0.t
+; V-NEXT: vmv1r.v v0, v18
+; V-NEXT: vmerge.vvm v8, v8, v10, v0
+; V-NEXT: vmerge.vvm v10, v14, v16, v0
; V-NEXT: ret
;
; ZIP-LABEL: vector_deinterleave_v4f64_v8f64:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
index bd1a3f8e316bb..27587f3738c43 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll
@@ -10,16 +10,17 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_load_nxv16i
; CHECK-LABEL: vector_deinterleave_load_nxv16i1_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; CHECK-NEXT: vlm.v v8, (a0)
+; CHECK-NEXT: vlm.v v12, (a0)
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a0
+; CHECK-NEXT: vslidedown.vx v0, v12, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vmerge.vim v10, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v8, v12, 1, v0
+; CHECK-NEXT: vmerge.vim v10, v8, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vnsrl.wi v12, v8, 0
; CHECK-NEXT: vnsrl.wi v14, v8, 8
; CHECK-NEXT: vmsne.vi v0, v12, 0
@@ -609,13 +610,14 @@ define {<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i
; CHECK-NEXT: vmsne.vi v13, v13, 0
; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vmsne.vi v12, v14, 0
-; CHECK-NEXT: vmsne.vi v14, v15, 0
; CHECK-NEXT: vsetvli zero, a4, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vx v0, v13, a5
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vx v0, v12, a4
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmsne.vi v12, v15, 0
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v0, v14, a1
+; CHECK-NEXT: vslideup.vx v0, v12, a1
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
; CHECK-NEXT: vle8.v v8, (a0), v0.t
; CHECK-NEXT: csrr a0, vlenb
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
index ac9f26314a9ab..5d39739d8d1f6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
@@ -187,21 +187,21 @@ define {<vscale x 64 x i1>, <vscale x 64 x i1>} @vector_deinterleave_nxv64i1_nxv
; ZIP-LABEL: vector_deinterleave_nxv64i1_nxv128i1:
; ZIP: # %bb.0:
; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; ZIP-NEXT: vmv1r.v v9, v0
+; ZIP-NEXT: vmv1r.v v24, v0
+; ZIP-NEXT: vmv.v.i v16, 0
; ZIP-NEXT: vmv1r.v v0, v8
-; ZIP-NEXT: vmv.v.i v24, 0
-; ZIP-NEXT: vmerge.vim v16, v24, 1, v0
-; ZIP-NEXT: vmv1r.v v0, v9
-; ZIP-NEXT: vmerge.vim v24, v24, 1, v0
+; ZIP-NEXT: vmerge.vim v8, v16, 1, v0
+; ZIP-NEXT: vmv1r.v v0, v24
+; ZIP-NEXT: vmerge.vim v24, v16, 1, v0
; ZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; ZIP-NEXT: ri.vunzip2a.vv v12, v16, v20
-; ZIP-NEXT: ri.vunzip2b.vv v4, v16, v20
-; ZIP-NEXT: ri.vunzip2a.vv v8, v24, v28
+; ZIP-NEXT: ri.vunzip2a.vv v20, v8, v12
+; ZIP-NEXT: ri.vunzip2b.vv v4, v8, v12
+; ZIP-NEXT: ri.vunzip2a.vv v16, v24, v28
; ZIP-NEXT: ri.vunzip2b.vv v0, v24, v28
; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; ZIP-NEXT: vmsne.vi v16, v8, 0
+; ZIP-NEXT: vmsne.vi v9, v16, 0
; ZIP-NEXT: vmsne.vi v8, v0, 0
-; ZIP-NEXT: vmv1r.v v0, v16
+; ZIP-NEXT: vmv1r.v v0, v9
; ZIP-NEXT: ret
%retval = call {<vscale x 64 x i1>, <vscale x 64 x i1>} @llvm.vector.deinterleave2.nxv128i1(<vscale x 128 x i1> %vec)
ret {<vscale x 64 x i1>, <vscale x 64 x i1>} %retval
@@ -355,23 +355,24 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} @vector_dein
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v16, v10, 1, v0
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a1
+; CHECK-NEXT: vslidedown.vx v10, v0, a1
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v8, v12, 1, v0
; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v18, v10, 1, v0
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v20, v10, 1, v0
-; CHECK-NEXT: vs8r.v v16, (a0)
-; CHECK-NEXT: vlseg3e8.v v8, (a0)
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v14, v0, a0
+; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v10, v12, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
+; CHECK-NEXT: vs8r.v v8, (a1)
+; CHECK-NEXT: vlseg3e8.v v8, (a1)
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmsne.vi v8, v10, 0
; CHECK-NEXT: vmsne.vi v9, v12, 0
@@ -475,30 +476,32 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: vslidedown.vx v9, v0, a2
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v22, v10, 1, v0
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.v.v v0, v9
+; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v14, v10, 1, v0
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v20, v10, 1, v0
+; CHECK-NEXT: vmerge.vim v12, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v16, v10, 1, v0
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a1
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v18, v10, 1, v0
-; CHECK-NEXT: vs8r.v v16, (a0)
-; CHECK-NEXT: vlseg4e8.v v8, (a0)
+; CHECK-NEXT: vslidedown.vx v16, v8, a1
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
+; CHECK-NEXT: vs8r.v v8, (a2)
+; CHECK-NEXT: vlseg4e8.v v8, (a2)
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmsne.vi v8, v10, 0
; CHECK-NEXT: vmsne.vi v9, v12, 0
@@ -600,39 +603,38 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v16, v12, 1, v0
+; CHECK-NEXT: vmerge.vim v24, v12, 1, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a1
; CHECK-NEXT: srli a2, a0, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v18, v12, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vim v14, v12, 1, v0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v9, a2
+; CHECK-NEXT: vslidedown.vx v10, v9, a1
+; CHECK-NEXT: vslidedown.vx v9, v9, a2
; CHECK-NEXT: sub a0, a0, a1
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v20, v12, 1, v0
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v9, a0
+; CHECK-NEXT: vslidedown.vx v0, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v14, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v10, v15
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v11, v12
+; CHECK-NEXT: vmerge.vim v20, v12, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vim v26, v12, 1, v0
+; CHECK-NEXT: vmv1r.v v18, v21
+; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vmerge.vim v28, v12, 1, v0
+; CHECK-NEXT: vmv1r.v v19, v14
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vmv1r.v v8, v21
+; CHECK-NEXT: vmv1r.v v16, v29
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vmv1r.v v9, v14
-; CHECK-NEXT: vs8r.v v16, (a0)
-; CHECK-NEXT: vmv1r.v v12, v13
-; CHECK-NEXT: vs8r.v v8, (a1)
+; CHECK-NEXT: vmv1r.v v17, v20
+; CHECK-NEXT: vs8r.v v24, (a0)
+; CHECK-NEXT: vmv1r.v v20, v15
+; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vlseg5e8.v v8, (a0)
; CHECK-NEXT: vlseg5e8.v v14, (a1)
@@ -830,41 +832,42 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmv.v.i v14, 0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v16, v10, 1, v0
+; CHECK-NEXT: vmerge.vim v16, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a1
; CHECK-NEXT: srli a2, a0, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a1
; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v18, v10, 1, v0
+; CHECK-NEXT: vmerge.vim v18, v14, 1, v0
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v9, a2
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: sub a0, a0, a1
; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v20, v10, 1, v0
+; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v26, v10, 1, v0
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v9, a0
+; CHECK-NEXT: vslidedown.vx v12, v8, a1
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a2)
+; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v10, v14, 1, v0
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v9, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v24, v10, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmerge.vim v12, v14, 1, v0
+; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a1
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v28, v10, 1, v0
-; CHECK-NEXT: vs8r.v v24, (a0)
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vlseg6e8.v v16, (a2)
-; CHECK-NEXT: vlseg6e8.v v10, (a0)
+; CHECK-NEXT: vlseg6e8.v v10, (a1)
; CHECK-NEXT: vmv2r.v v8, v16
; CHECK-NEXT: vmv2r.v v22, v18
; CHECK-NEXT: vmv2r.v v24, v20
@@ -1062,53 +1065,55 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: vmv1r.v v17, v8
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: vmv.v.i v20, 0
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: srli a0, a1, 1
+; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmerge.vim v22, v20, 1, v0
+; CHECK-NEXT: sub a1, a1, a2
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v22, v12, 1, v0
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v9, a0
-; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v20, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v16, v12, 1, v0
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v9, a1
-; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v18, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v14, v12, 1, v0
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, a1
-; CHECK-NEXT: vmv1r.v v10, v15
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v24, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v11, v24
+; CHECK-NEXT: vmerge.vim v14, v20, 1, v0
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, a0
-; CHECK-NEXT: vmv1r.v v8, v23
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vmv1r.v v9, v14
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v14, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v12, v25
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vmv1r.v v13, v14
-; CHECK-NEXT: vs8r.v v16, (a0)
-; CHECK-NEXT: vmv1r.v v14, v15
+; CHECK-NEXT: vmerge.vim v12, v20, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v10, v8, a2
+; CHECK-NEXT: vmv1r.v v18, v23
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v8, v20, 1, v0
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v17, a2
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v24, v20, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vim v10, v20, 1, v0
+; CHECK-NEXT: vmv1r.v v19, v24
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vmv1r.v v16, v15
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v17, a0
+; CHECK-NEXT: vmv1r.v v17, v22
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v22, v20, 1, v0
+; CHECK-NEXT: vmv1r.v v20, v25
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vmv1r.v v21, v22
; CHECK-NEXT: vs8r.v v8, (a1)
+; CHECK-NEXT: vmv1r.v v22, v23
+; CHECK-NEXT: vs8r.v v16, (a0)
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vlseg7e8.v v8, (a0)
-; CHECK-NEXT: vlseg7e8.v v16, (a1)
+; CHECK-NEXT: vlseg7e8.v v8, (a1)
+; CHECK-NEXT: vlseg7e8.v v16, (a0)
; CHECK-NEXT: vmv2r.v v24, v8
; CHECK-NEXT: vmv2r.v v26, v10
; CHECK-NEXT: vmv2r.v v28, v12
@@ -1333,49 +1338,51 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v22, v10, 1, v0
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v9, a0
-; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v20, v10, 1, v0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: srli a3, a1, 1
+; CHECK-NEXT: sub a1, a1, a2
+; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a1
+; CHECK-NEXT: vsetvli a4, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v30, v16, 1, v0
+; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v9, a3
+; CHECK-NEXT: vsetvli a4, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v28, v16, 1, v0
+; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v10, v8, a3
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v16, v10, 1, v0
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v9, a1
-; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v18, v10, 1, v0
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a2
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v30, v10, 1, v0
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a0
-; CHECK-NEXT: vs8r.v v16, (a2)
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v28, v10, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v24, v10, 1, v0
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetvli a4, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
+; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v9, a2
+; CHECK-NEXT: vsetvli a4, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v26, v16, 1, v0
+; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, a1
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v26, v10, 1, v0
; CHECK-NEXT: vs8r.v v24, (a0)
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v14, v16, 1, v0
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v11, v8, a2
+; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v12, v16, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vmerge.vim v10, v16, 1, v0
+; CHECK-NEXT: vs8r.v v8, (a3)
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vlseg8e8.v v18, (a2)
-; CHECK-NEXT: vlseg8e8.v v10, (a0)
+; CHECK-NEXT: vlseg8e8.v v18, (a0)
+; CHECK-NEXT: vlseg8e8.v v10, (a3)
; CHECK-NEXT: vmv2r.v v8, v18
; CHECK-NEXT: vmv2r.v v26, v20
; CHECK-NEXT: vmv2r.v v28, v22
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
index 2e2f12ac7f506..fdf5a42f93502 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
@@ -11,9 +11,9 @@ define void @vector_interleave_store_nxv32i1_nxv16i1(<vscale x 16 x i1> %a, <vsc
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: li a1, -1
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v12, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmerge.vim v14, v10, 1, v0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
index 0577fb1ff67bb..24a61471a8a26 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
@@ -14,9 +14,9 @@ define <vscale x 32 x i1> @vector_interleave_nxv32i1_nxv16i1(<vscale x 16 x i1>
; V: # %bb.0:
; V-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; V-NEXT: vmv1r.v v9, v0
-; V-NEXT: vmv1r.v v0, v8
; V-NEXT: vmv.v.i v10, 0
; V-NEXT: li a0, -1
+; V-NEXT: vmv1r.v v0, v8
; V-NEXT: vmerge.vim v12, v10, 1, v0
; V-NEXT: vmv1r.v v0, v9
; V-NEXT: vmerge.vim v14, v10, 1, v0
@@ -33,35 +33,35 @@ define <vscale x 32 x i1> @vector_interleave_nxv32i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-LABEL: vector_interleave_nxv32i1_nxv16i1:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, mu
-; ZVBB-NEXT: vmv1r.v v9, v0
-; ZVBB-NEXT: vmv1r.v v0, v8
+; ZVBB-NEXT: vmv1r.v v14, v0
; ZVBB-NEXT: vmv.v.i v10, 0
; ZVBB-NEXT: li a0, 1
-; ZVBB-NEXT: vmerge.vim v10, v10, 1, v0
-; ZVBB-NEXT: vwsll.vi v12, v10, 8
-; ZVBB-NEXT: vmv1r.v v0, v9
-; ZVBB-NEXT: vwaddu.wx v12, v12, a0, v0.t
+; ZVBB-NEXT: vmv1r.v v0, v8
+; ZVBB-NEXT: vmerge.vim v12, v10, 1, v0
+; ZVBB-NEXT: vwsll.vi v8, v12, 8
+; ZVBB-NEXT: vmv1r.v v0, v14
+; ZVBB-NEXT: vwaddu.wx v8, v8, a0, v0.t
; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: vmsne.vi v8, v14, 0
-; ZVBB-NEXT: vmsne.vi v0, v12, 0
+; ZVBB-NEXT: vmsne.vi v12, v10, 0
+; ZVBB-NEXT: vmsne.vi v0, v8, 0
; ZVBB-NEXT: srli a0, a0, 2
; ZVBB-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vx v0, v8, a0
+; ZVBB-NEXT: vslideup.vx v0, v12, a0
; ZVBB-NEXT: ret
;
; ZIP-LABEL: vector_interleave_nxv32i1_nxv16i1:
; ZIP: # %bb.0:
; ZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZIP-NEXT: vmv1r.v v9, v0
-; ZIP-NEXT: vmv1r.v v0, v8
-; ZIP-NEXT: vmv.v.i v10, 0
+; ZIP-NEXT: vmv.v.i v12, 0
; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: vmerge.vim v12, v10, 1, v0
+; ZIP-NEXT: vmv1r.v v0, v8
+; ZIP-NEXT: vmerge.vim v10, v12, 1, v0
; ZIP-NEXT: vmv1r.v v0, v9
-; ZIP-NEXT: vmerge.vim v8, v10, 1, v0
-; ZIP-NEXT: ri.vzip2b.vv v10, v8, v12
-; ZIP-NEXT: ri.vzip2a.vv v14, v8, v12
-; ZIP-NEXT: vmsne.vi v8, v10, 0
+; ZIP-NEXT: vmerge.vim v8, v12, 1, v0
+; ZIP-NEXT: ri.vzip2b.vv v12, v8, v10
+; ZIP-NEXT: ri.vzip2a.vv v14, v8, v10
+; ZIP-NEXT: vmsne.vi v8, v12, 0
; ZIP-NEXT: vmsne.vi v0, v14, 0
; ZIP-NEXT: srli a0, a0, 2
; ZIP-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
@@ -175,9 +175,9 @@ define <vscale x 4 x i64> @vector_interleave_nxv4i64_nxv2i64(<vscale x 2 x i64>
; V-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; V-NEXT: vid.v v12
; V-NEXT: srli a0, a0, 2
-; V-NEXT: vand.vi v13, v12, 1
-; V-NEXT: vmsne.vi v0, v13, 0
; V-NEXT: vsrl.vi v16, v12, 1
+; V-NEXT: vand.vi v12, v12, 1
+; V-NEXT: vmsne.vi v0, v12, 0
; V-NEXT: vadd.vx v16, v16, a0, v0.t
; V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; V-NEXT: vrgatherei16.vv v12, v8, v16
@@ -190,9 +190,9 @@ define <vscale x 4 x i64> @vector_interleave_nxv4i64_nxv2i64(<vscale x 2 x i64>
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; ZVBB-NEXT: vid.v v12
; ZVBB-NEXT: srli a0, a0, 2
-; ZVBB-NEXT: vand.vi v13, v12, 1
-; ZVBB-NEXT: vmsne.vi v0, v13, 0
; ZVBB-NEXT: vsrl.vi v16, v12, 1
+; ZVBB-NEXT: vand.vi v12, v12, 1
+; ZVBB-NEXT: vmsne.vi v0, v12, 0
; ZVBB-NEXT: vadd.vx v16, v16, a0, v0.t
; ZVBB-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; ZVBB-NEXT: vrgatherei16.vv v12, v8, v16
@@ -216,56 +216,57 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv64i1(<vscale x 64 x i1
; V-LABEL: vector_interleave_nxv128i1_nxv64i1:
; V: # %bb.0:
; V-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; V-NEXT: vmv1r.v v9, v0
-; V-NEXT: vmv1r.v v0, v8
-; V-NEXT: vmv.v.i v24, 0
+; V-NEXT: vmv1r.v v24, v0
+; V-NEXT: vmv.v.i v16, 0
; V-NEXT: li a0, -1
-; V-NEXT: vmerge.vim v16, v24, 1, v0
-; V-NEXT: vmv1r.v v0, v9
-; V-NEXT: vmerge.vim v24, v24, 1, v0
+; V-NEXT: vmv1r.v v0, v8
+; V-NEXT: vmerge.vim v8, v16, 1, v0
+; V-NEXT: vmv1r.v v0, v24
+; V-NEXT: vmerge.vim v16, v16, 1, v0
; V-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; V-NEXT: vwaddu.vv v8, v24, v16
-; V-NEXT: vwaddu.vv v0, v28, v20
-; V-NEXT: vwmaccu.vx v8, a0, v16
-; V-NEXT: vwmaccu.vx v0, a0, v20
+; V-NEXT: vwaddu.vv v24, v16, v8
+; V-NEXT: vmv4r.v v4, v20
+; V-NEXT: vwaddu.vv v16, v4, v12
+; V-NEXT: vwmaccu.vx v24, a0, v8
+; V-NEXT: vwmaccu.vx v16, a0, v12
; V-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; V-NEXT: vmsne.vi v16, v8, 0
-; V-NEXT: vmsne.vi v8, v0, 0
-; V-NEXT: vmv1r.v v0, v16
+; V-NEXT: vmsne.vi v0, v24, 0
+; V-NEXT: vmsne.vi v8, v16, 0
; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv128i1_nxv64i1:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; ZVBB-NEXT: vmv.v.i v24, 0
-; ZVBB-NEXT: vmerge.vim v16, v24, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v8
-; ZVBB-NEXT: vmerge.vim v24, v24, 1, v0
+; ZVBB-NEXT: vmv1r.v v24, v8
+; ZVBB-NEXT: vmv.v.i v16, 0
+; ZVBB-NEXT: vmerge.vim v8, v16, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v24
+; ZVBB-NEXT: vmerge.vim v24, v16, 1, v0
; ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; ZVBB-NEXT: vwsll.vi v8, v24, 8
+; ZVBB-NEXT: vwsll.vi v16, v24, 8
; ZVBB-NEXT: vwsll.vi v0, v28, 8
-; ZVBB-NEXT: vwaddu.wv v8, v8, v16
-; ZVBB-NEXT: vwaddu.wv v0, v0, v20
+; ZVBB-NEXT: vwaddu.wv v16, v16, v8
+; ZVBB-NEXT: vwaddu.wv v0, v0, v12
; ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; ZVBB-NEXT: vmsne.vi v16, v8, 0
+; ZVBB-NEXT: vmsne.vi v9, v16, 0
; ZVBB-NEXT: vmsne.vi v8, v0, 0
-; ZVBB-NEXT: vmv1r.v v0, v16
+; ZVBB-NEXT: vmv1r.v v0, v9
; ZVBB-NEXT: ret
;
; ZIP-LABEL: vector_interleave_nxv128i1_nxv64i1:
; ZIP: # %bb.0:
; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; ZIP-NEXT: vmv1r.v v9, v0
+; ZIP-NEXT: vmv1r.v v24, v0
+; ZIP-NEXT: vmv.v.i v16, 0
; ZIP-NEXT: vmv1r.v v0, v8
-; ZIP-NEXT: vmv.v.i v24, 0
-; ZIP-NEXT: vmerge.vim v16, v24, 1, v0
-; ZIP-NEXT: vmv1r.v v0, v9
-; ZIP-NEXT: vmerge.vim v8, v24, 1, v0
+; ZIP-NEXT: vmerge.vim v8, v16, 1, v0
+; ZIP-NEXT: vmv1r.v v0, v24
+; ZIP-NEXT: vmerge.vim v16, v16, 1, v0
; ZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; ZIP-NEXT: ri.vzip2b.vv v4, v8, v16
-; ZIP-NEXT: ri.vzip2b.vv v28, v12, v20
-; ZIP-NEXT: ri.vzip2a.vv v0, v8, v16
-; ZIP-NEXT: ri.vzip2a.vv v24, v12, v20
+; ZIP-NEXT: ri.vzip2b.vv v4, v16, v8
+; ZIP-NEXT: ri.vzip2b.vv v28, v20, v12
+; ZIP-NEXT: ri.vzip2a.vv v0, v16, v8
+; ZIP-NEXT: ri.vzip2a.vv v24, v20, v12
; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZIP-NEXT: vmsne.vi v9, v0, 0
; ZIP-NEXT: vmsne.vi v8, v24, 0
@@ -400,13 +401,13 @@ define <vscale x 16 x i64> @vector_interleave_nxv16i64_nxv8i64(<vscale x 8 x i64
; V-NEXT: srli a0, a0, 1
; V-NEXT: vmv4r.v v28, v16
; V-NEXT: vmv4r.v v16, v12
+; V-NEXT: vsrl.vi v4, v6, 1
; V-NEXT: vand.vi v8, v6, 1
; V-NEXT: vmsne.vi v0, v8, 0
-; V-NEXT: vsrl.vi v6, v6, 1
-; V-NEXT: vadd.vx v6, v6, a0, v0.t
+; V-NEXT: vadd.vx v4, v4, a0, v0.t
; V-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; V-NEXT: vrgatherei16.vv v8, v24, v6
-; V-NEXT: vrgatherei16.vv v24, v16, v6
+; V-NEXT: vrgatherei16.vv v8, v24, v4
+; V-NEXT: vrgatherei16.vv v24, v16, v4
; V-NEXT: vmv.v.v v16, v24
; V-NEXT: ret
;
@@ -419,13 +420,13 @@ define <vscale x 16 x i64> @vector_interleave_nxv16i64_nxv8i64(<vscale x 8 x i64
; ZVBB-NEXT: srli a0, a0, 1
; ZVBB-NEXT: vmv4r.v v28, v16
; ZVBB-NEXT: vmv4r.v v16, v12
+; ZVBB-NEXT: vsrl.vi v4, v6, 1
; ZVBB-NEXT: vand.vi v8, v6, 1
; ZVBB-NEXT: vmsne.vi v0, v8, 0
-; ZVBB-NEXT: vsrl.vi v6, v6, 1
-; ZVBB-NEXT: vadd.vx v6, v6, a0, v0.t
+; ZVBB-NEXT: vadd.vx v4, v4, a0, v0.t
; ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; ZVBB-NEXT: vrgatherei16.vv v8, v24, v6
-; ZVBB-NEXT: vrgatherei16.vv v24, v16, v6
+; ZVBB-NEXT: vrgatherei16.vv v8, v24, v4
+; ZVBB-NEXT: vrgatherei16.vv v24, v16, v4
; ZVBB-NEXT: vmv.v.v v16, v24
; ZVBB-NEXT: ret
;
@@ -491,19 +492,19 @@ define <vscale x 48 x i1> @vector_interleave_nxv48i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmv.v.i v14, 0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vmerge.vim v16, v12, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vim v12, v14, 1, v0
; CHECK-NEXT: slli a2, a1, 1
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmerge.vim v14, v12, 1, v0
+; CHECK-NEXT: vmerge.vim v10, v14, 1, v0
; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v18, v12, 1, v0
+; CHECK-NEXT: vmerge.vim v14, v14, 1, v0
; CHECK-NEXT: add a2, a3, a2
-; CHECK-NEXT: vsseg3e8.v v14, (a0)
+; CHECK-NEXT: vsseg3e8.v v10, (a0)
; CHECK-NEXT: vl2r.v v8, (a2)
; CHECK-NEXT: srli a2, a1, 1
; CHECK-NEXT: vl2r.v v10, (a3)
@@ -532,19 +533,19 @@ define <vscale x 48 x i1> @vector_interleave_nxv48i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmv1r.v v10, v0
-; ZVBB-NEXT: vmv1r.v v0, v8
-; ZVBB-NEXT: vmv.v.i v12, 0
+; ZVBB-NEXT: vmv.v.i v14, 0
; ZVBB-NEXT: addi a0, sp, 16
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: vmerge.vim v16, v12, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v8
+; ZVBB-NEXT: vmerge.vim v12, v14, 1, v0
; ZVBB-NEXT: slli a2, a1, 1
; ZVBB-NEXT: vmv1r.v v0, v10
-; ZVBB-NEXT: vmerge.vim v14, v12, 1, v0
+; ZVBB-NEXT: vmerge.vim v10, v14, 1, v0
; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vmv1r.v v0, v9
-; ZVBB-NEXT: vmerge.vim v18, v12, 1, v0
+; ZVBB-NEXT: vmerge.vim v14, v14, 1, v0
; ZVBB-NEXT: add a2, a3, a2
-; ZVBB-NEXT: vsseg3e8.v v14, (a0)
+; ZVBB-NEXT: vsseg3e8.v v10, (a0)
; ZVBB-NEXT: vl2r.v v8, (a2)
; ZVBB-NEXT: srli a2, a1, 1
; ZVBB-NEXT: vl2r.v v10, (a3)
@@ -788,22 +789,22 @@ define <vscale x 64 x i1> @vector_interleave_nxv64i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmv.v.i v18, 0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vmerge.vim v16, v12, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vim v14, v18, 1, v0
; CHECK-NEXT: slli a2, a1, 1
; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: vmerge.vim v14, v12, 1, v0
+; CHECK-NEXT: vmerge.vim v12, v18, 1, v0
; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v18, v12, 1, v0
+; CHECK-NEXT: vmerge.vim v16, v18, 1, v0
; CHECK-NEXT: add a4, a3, a2
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmerge.vim v20, v12, 1, v0
+; CHECK-NEXT: vmerge.vim v18, v18, 1, v0
; CHECK-NEXT: add a2, a4, a2
-; CHECK-NEXT: vsseg4e8.v v14, (a0)
+; CHECK-NEXT: vsseg4e8.v v12, (a0)
; CHECK-NEXT: vl2r.v v8, (a2)
; CHECK-NEXT: srli a2, a1, 1
; CHECK-NEXT: srli a1, a1, 2
@@ -833,22 +834,22 @@ define <vscale x 64 x i1> @vector_interleave_nxv64i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmv1r.v v11, v0
-; ZVBB-NEXT: vmv1r.v v0, v8
-; ZVBB-NEXT: vmv.v.i v12, 0
+; ZVBB-NEXT: vmv.v.i v18, 0
; ZVBB-NEXT: addi a0, sp, 16
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: vmerge.vim v16, v12, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v8
+; ZVBB-NEXT: vmerge.vim v14, v18, 1, v0
; ZVBB-NEXT: slli a2, a1, 1
; ZVBB-NEXT: vmv1r.v v0, v11
-; ZVBB-NEXT: vmerge.vim v14, v12, 1, v0
+; ZVBB-NEXT: vmerge.vim v12, v18, 1, v0
; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vmv1r.v v0, v9
-; ZVBB-NEXT: vmerge.vim v18, v12, 1, v0
+; ZVBB-NEXT: vmerge.vim v16, v18, 1, v0
; ZVBB-NEXT: add a4, a3, a2
; ZVBB-NEXT: vmv1r.v v0, v10
-; ZVBB-NEXT: vmerge.vim v20, v12, 1, v0
+; ZVBB-NEXT: vmerge.vim v18, v18, 1, v0
; ZVBB-NEXT: add a2, a4, a2
-; ZVBB-NEXT: vsseg4e8.v v14, (a0)
+; ZVBB-NEXT: vsseg4e8.v v12, (a0)
; ZVBB-NEXT: vl2r.v v8, (a2)
; ZVBB-NEXT: srli a2, a1, 1
; ZVBB-NEXT: srli a1, a1, 2
@@ -1099,28 +1100,28 @@ define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vmerge.vim v14, v12, 1, v0
+; CHECK-NEXT: vmerge.vim v22, v12, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v18, v12, 1, v0
-; CHECK-NEXT: add a2, a4, a1
-; CHECK-NEXT: srli a3, a1, 1
-; CHECK-NEXT: vmv2r.v v20, v14
+; CHECK-NEXT: vmerge.vim v14, v12, 1, v0
+; CHECK-NEXT: vmv2r.v v16, v22
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v16, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v21, v18
+; CHECK-NEXT: vmerge.vim v24, v12, 1, v0
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmerge.vim v8, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v22, v16
-; CHECK-NEXT: vmv1r.v v16, v19
+; CHECK-NEXT: vmerge.vim v20, v12, 1, v0
+; CHECK-NEXT: add a2, a4, a1
+; CHECK-NEXT: vmv1r.v v17, v14
+; CHECK-NEXT: srli a3, a1, 1
+; CHECK-NEXT: vmv1r.v v18, v24
+; CHECK-NEXT: vmv1r.v v24, v15
; CHECK-NEXT: add a5, a2, a1
-; CHECK-NEXT: vmv1r.v v23, v8
-; CHECK-NEXT: vmv1r.v v18, v9
+; CHECK-NEXT: vmv1r.v v19, v20
+; CHECK-NEXT: vmv1r.v v26, v21
; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: vmerge.vim v24, v12, 1, v0
+; CHECK-NEXT: vmerge.vim v20, v12, 1, v0
; CHECK-NEXT: vsetvli a6, zero, e8, m1, ta, ma
-; CHECK-NEXT: vsseg5e8.v v20, (a4)
-; CHECK-NEXT: vmv1r.v v19, v25
-; CHECK-NEXT: vsseg5e8.v v15, (a0)
+; CHECK-NEXT: vsseg5e8.v v16, (a4)
+; CHECK-NEXT: vmv1r.v v27, v21
+; CHECK-NEXT: vsseg5e8.v v23, (a0)
; CHECK-NEXT: vl1r.v v8, (a5)
; CHECK-NEXT: add a5, a5, a1
; CHECK-NEXT: vl1r.v v10, (a4)
@@ -1173,28 +1174,28 @@ define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: add a0, sp, a0
; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: vmerge.vim v14, v12, 1, v0
+; ZVBB-NEXT: vmerge.vim v22, v12, 1, v0
; ZVBB-NEXT: vmv1r.v v0, v8
-; ZVBB-NEXT: vmerge.vim v18, v12, 1, v0
-; ZVBB-NEXT: add a2, a4, a1
-; ZVBB-NEXT: srli a3, a1, 1
-; ZVBB-NEXT: vmv2r.v v20, v14
+; ZVBB-NEXT: vmerge.vim v14, v12, 1, v0
+; ZVBB-NEXT: vmv2r.v v16, v22
; ZVBB-NEXT: vmv1r.v v0, v9
-; ZVBB-NEXT: vmerge.vim v16, v12, 1, v0
-; ZVBB-NEXT: vmv1r.v v21, v18
+; ZVBB-NEXT: vmerge.vim v24, v12, 1, v0
; ZVBB-NEXT: vmv1r.v v0, v10
-; ZVBB-NEXT: vmerge.vim v8, v12, 1, v0
-; ZVBB-NEXT: vmv1r.v v22, v16
-; ZVBB-NEXT: vmv1r.v v16, v19
+; ZVBB-NEXT: vmerge.vim v20, v12, 1, v0
+; ZVBB-NEXT: add a2, a4, a1
+; ZVBB-NEXT: vmv1r.v v17, v14
+; ZVBB-NEXT: srli a3, a1, 1
+; ZVBB-NEXT: vmv1r.v v18, v24
+; ZVBB-NEXT: vmv1r.v v24, v15
; ZVBB-NEXT: add a5, a2, a1
-; ZVBB-NEXT: vmv1r.v v23, v8
-; ZVBB-NEXT: vmv1r.v v18, v9
+; ZVBB-NEXT: vmv1r.v v19, v20
+; ZVBB-NEXT: vmv1r.v v26, v21
; ZVBB-NEXT: vmv1r.v v0, v11
-; ZVBB-NEXT: vmerge.vim v24, v12, 1, v0
+; ZVBB-NEXT: vmerge.vim v20, v12, 1, v0
; ZVBB-NEXT: vsetvli a6, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vsseg5e8.v v20, (a4)
-; ZVBB-NEXT: vmv1r.v v19, v25
-; ZVBB-NEXT: vsseg5e8.v v15, (a0)
+; ZVBB-NEXT: vsseg5e8.v v16, (a4)
+; ZVBB-NEXT: vmv1r.v v27, v21
+; ZVBB-NEXT: vsseg5e8.v v23, (a0)
; ZVBB-NEXT: vl1r.v v8, (a5)
; ZVBB-NEXT: add a5, a5, a1
; ZVBB-NEXT: vl1r.v v10, (a4)
@@ -2310,76 +2311,81 @@ define <vscale x 96 x i1> @vector_interleave_nxv96i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v20, 0
-; CHECK-NEXT: vmerge.vim v14, v20, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v22, v20, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmv1r.v v16, v23
-; CHECK-NEXT: vmerge.vim v8, v20, 1, v0
+; CHECK-NEXT: vmv1r.v v13, v12
+; CHECK-NEXT: vmv1r.v v12, v11
+; CHECK-NEXT: vmv1r.v v11, v10
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vmv1r.v v16, v8
+; CHECK-NEXT: vmv.v.i v14, 0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: li a0, 6
+; CHECK-NEXT: mul a1, a1, a0
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 6
-; CHECK-NEXT: mul a0, a0, a1
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vmv1r.v v17, v9
+; CHECK-NEXT: vmerge.vim v8, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmerge.vim v18, v14, 1, v0
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmerge.vim v24, v20, 1, v0
-; CHECK-NEXT: addi a4, sp, 16
-; CHECK-NEXT: vmv1r.v v18, v25
+; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v10, v19
; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: vmerge.vim v26, v20, 1, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vmv1r.v v19, v27
+; CHECK-NEXT: vmerge.vim v22, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v11, v21
; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmerge.vim v10, v20, 1, v0
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: vmv1r.v v20, v11
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vsseg6e8.v v15, (a0)
-; CHECK-NEXT: vmv1r.v v15, v22
-; CHECK-NEXT: add a5, a4, a1
-; CHECK-NEXT: vmv1r.v v16, v8
-; CHECK-NEXT: srli a3, a1, 1
-; CHECK-NEXT: vmv1r.v v17, v24
-; CHECK-NEXT: add a6, a5, a1
-; CHECK-NEXT: vmv1r.v v18, v26
-; CHECK-NEXT: add a7, a2, a1
-; CHECK-NEXT: vmv1r.v v19, v10
-; CHECK-NEXT: vsseg6e8.v v14, (a4)
-; CHECK-NEXT: vl1r.v v8, (a0)
-; CHECK-NEXT: add a0, a6, a1
+; CHECK-NEXT: vmerge.vim v24, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v12, v23
+; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmerge.vim v16, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v13, v25
+; CHECK-NEXT: add a3, a1, a0
+; CHECK-NEXT: vmv1r.v v14, v17
+; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsseg6e8.v v9, (a1)
+; CHECK-NEXT: vmv1r.v v9, v18
+; CHECK-NEXT: add a5, a2, a0
+; CHECK-NEXT: vmv1r.v v10, v20
+; CHECK-NEXT: srli a4, a0, 1
+; CHECK-NEXT: vmv1r.v v11, v22
+; CHECK-NEXT: add a6, a5, a0
+; CHECK-NEXT: vmv1r.v v12, v24
+; CHECK-NEXT: add a7, a3, a0
+; CHECK-NEXT: vmv1r.v v13, v16
+; CHECK-NEXT: vsseg6e8.v v8, (a2)
+; CHECK-NEXT: vl1r.v v8, (a1)
+; CHECK-NEXT: add a1, a6, a0
; CHECK-NEXT: vl1r.v v10, (a6)
-; CHECK-NEXT: add a6, a7, a1
-; CHECK-NEXT: vl1r.v v12, (a4)
-; CHECK-NEXT: add a4, a0, a1
+; CHECK-NEXT: add a6, a7, a0
+; CHECK-NEXT: vl1r.v v12, (a2)
+; CHECK-NEXT: add a2, a1, a0
; CHECK-NEXT: vl1r.v v14, (a7)
-; CHECK-NEXT: add a7, a6, a1
-; CHECK-NEXT: vl1r.v v16, (a4)
-; CHECK-NEXT: add a4, a4, a1
+; CHECK-NEXT: add a7, a6, a0
+; CHECK-NEXT: vl1r.v v16, (a2)
+; CHECK-NEXT: add a2, a2, a0
; CHECK-NEXT: vl1r.v v18, (a7)
-; CHECK-NEXT: add a7, a7, a1
-; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: vl1r.v v9, (a2)
-; CHECK-NEXT: vl1r.v v17, (a4)
-; CHECK-NEXT: vl1r.v v11, (a0)
+; CHECK-NEXT: add a7, a7, a0
+; CHECK-NEXT: srli a0, a0, 2
+; CHECK-NEXT: vl1r.v v9, (a3)
+; CHECK-NEXT: vl1r.v v17, (a2)
+; CHECK-NEXT: vl1r.v v11, (a1)
; CHECK-NEXT: vl1r.v v13, (a5)
; CHECK-NEXT: vl1r.v v19, (a7)
; CHECK-NEXT: vl1r.v v15, (a6)
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmsne.vi v20, v8, 0
; CHECK-NEXT: vmsne.vi v9, v16, 0
; CHECK-NEXT: vmsne.vi v16, v10, 0
; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: vmsne.vi v10, v18, 0
; CHECK-NEXT: vmsne.vi v8, v14, 0
-; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v9, v20, a1
-; CHECK-NEXT: vslideup.vx v0, v16, a1
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v0, v9, a3
-; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v8, v10, a1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslideup.vx v9, v20, a0
+; CHECK-NEXT: vslideup.vx v0, v16, a0
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslideup.vx v0, v9, a4
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 12
; CHECK-NEXT: mul a0, a0, a1
@@ -2395,76 +2401,81 @@ define <vscale x 96 x i1> @vector_interleave_nxv96i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: mul a0, a0, a1
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; ZVBB-NEXT: vmv.v.i v20, 0
-; ZVBB-NEXT: vmerge.vim v14, v20, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v8
-; ZVBB-NEXT: vmerge.vim v22, v20, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v9
-; ZVBB-NEXT: vmv1r.v v16, v23
-; ZVBB-NEXT: vmerge.vim v8, v20, 1, v0
+; ZVBB-NEXT: vmv1r.v v13, v12
+; ZVBB-NEXT: vmv1r.v v12, v11
+; ZVBB-NEXT: vmv1r.v v11, v10
+; ZVBB-NEXT: vmv1r.v v10, v9
+; ZVBB-NEXT: vmv1r.v v16, v8
+; ZVBB-NEXT: vmv.v.i v14, 0
+; ZVBB-NEXT: csrr a1, vlenb
+; ZVBB-NEXT: li a0, 6
+; ZVBB-NEXT: mul a1, a1, a0
+; ZVBB-NEXT: add a1, sp, a1
+; ZVBB-NEXT: addi a1, a1, 16
+; ZVBB-NEXT: addi a2, sp, 16
; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: li a1, 6
-; ZVBB-NEXT: mul a0, a0, a1
-; ZVBB-NEXT: add a0, sp, a0
-; ZVBB-NEXT: addi a0, a0, 16
-; ZVBB-NEXT: vmv1r.v v17, v9
+; ZVBB-NEXT: vmerge.vim v8, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v16
+; ZVBB-NEXT: vmerge.vim v18, v14, 1, v0
; ZVBB-NEXT: vmv1r.v v0, v10
-; ZVBB-NEXT: vmerge.vim v24, v20, 1, v0
-; ZVBB-NEXT: addi a4, sp, 16
-; ZVBB-NEXT: vmv1r.v v18, v25
+; ZVBB-NEXT: vmerge.vim v20, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v10, v19
; ZVBB-NEXT: vmv1r.v v0, v11
-; ZVBB-NEXT: vmerge.vim v26, v20, 1, v0
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: vmv1r.v v19, v27
+; ZVBB-NEXT: vmerge.vim v22, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v11, v21
; ZVBB-NEXT: vmv1r.v v0, v12
-; ZVBB-NEXT: vmerge.vim v10, v20, 1, v0
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: vmv1r.v v20, v11
-; ZVBB-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vsseg6e8.v v15, (a0)
-; ZVBB-NEXT: vmv1r.v v15, v22
-; ZVBB-NEXT: add a5, a4, a1
-; ZVBB-NEXT: vmv1r.v v16, v8
-; ZVBB-NEXT: srli a3, a1, 1
-; ZVBB-NEXT: vmv1r.v v17, v24
-; ZVBB-NEXT: add a6, a5, a1
-; ZVBB-NEXT: vmv1r.v v18, v26
-; ZVBB-NEXT: add a7, a2, a1
-; ZVBB-NEXT: vmv1r.v v19, v10
-; ZVBB-NEXT: vsseg6e8.v v14, (a4)
-; ZVBB-NEXT: vl1r.v v8, (a0)
-; ZVBB-NEXT: add a0, a6, a1
+; ZVBB-NEXT: vmerge.vim v24, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v12, v23
+; ZVBB-NEXT: vmv1r.v v0, v13
+; ZVBB-NEXT: vmerge.vim v16, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v13, v25
+; ZVBB-NEXT: add a3, a1, a0
+; ZVBB-NEXT: vmv1r.v v14, v17
+; ZVBB-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; ZVBB-NEXT: vsseg6e8.v v9, (a1)
+; ZVBB-NEXT: vmv1r.v v9, v18
+; ZVBB-NEXT: add a5, a2, a0
+; ZVBB-NEXT: vmv1r.v v10, v20
+; ZVBB-NEXT: srli a4, a0, 1
+; ZVBB-NEXT: vmv1r.v v11, v22
+; ZVBB-NEXT: add a6, a5, a0
+; ZVBB-NEXT: vmv1r.v v12, v24
+; ZVBB-NEXT: add a7, a3, a0
+; ZVBB-NEXT: vmv1r.v v13, v16
+; ZVBB-NEXT: vsseg6e8.v v8, (a2)
+; ZVBB-NEXT: vl1r.v v8, (a1)
+; ZVBB-NEXT: add a1, a6, a0
; ZVBB-NEXT: vl1r.v v10, (a6)
-; ZVBB-NEXT: add a6, a7, a1
-; ZVBB-NEXT: vl1r.v v12, (a4)
-; ZVBB-NEXT: add a4, a0, a1
+; ZVBB-NEXT: add a6, a7, a0
+; ZVBB-NEXT: vl1r.v v12, (a2)
+; ZVBB-NEXT: add a2, a1, a0
; ZVBB-NEXT: vl1r.v v14, (a7)
-; ZVBB-NEXT: add a7, a6, a1
-; ZVBB-NEXT: vl1r.v v16, (a4)
-; ZVBB-NEXT: add a4, a4, a1
+; ZVBB-NEXT: add a7, a6, a0
+; ZVBB-NEXT: vl1r.v v16, (a2)
+; ZVBB-NEXT: add a2, a2, a0
; ZVBB-NEXT: vl1r.v v18, (a7)
-; ZVBB-NEXT: add a7, a7, a1
-; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: vl1r.v v9, (a2)
-; ZVBB-NEXT: vl1r.v v17, (a4)
-; ZVBB-NEXT: vl1r.v v11, (a0)
+; ZVBB-NEXT: add a7, a7, a0
+; ZVBB-NEXT: srli a0, a0, 2
+; ZVBB-NEXT: vl1r.v v9, (a3)
+; ZVBB-NEXT: vl1r.v v17, (a2)
+; ZVBB-NEXT: vl1r.v v11, (a1)
; ZVBB-NEXT: vl1r.v v13, (a5)
; ZVBB-NEXT: vl1r.v v19, (a7)
; ZVBB-NEXT: vl1r.v v15, (a6)
-; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; ZVBB-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmsne.vi v20, v8, 0
; ZVBB-NEXT: vmsne.vi v9, v16, 0
; ZVBB-NEXT: vmsne.vi v16, v10, 0
; ZVBB-NEXT: vmsne.vi v0, v12, 0
; ZVBB-NEXT: vmsne.vi v10, v18, 0
; ZVBB-NEXT: vmsne.vi v8, v14, 0
-; ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vx v9, v20, a1
-; ZVBB-NEXT: vslideup.vx v0, v16, a1
-; ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v0, v9, a3
-; ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; ZVBB-NEXT: vslideup.vx v8, v10, a1
+; ZVBB-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; ZVBB-NEXT: vslideup.vx v9, v20, a0
+; ZVBB-NEXT: vslideup.vx v0, v16, a0
+; ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; ZVBB-NEXT: vslideup.vx v0, v9, a4
+; ZVBB-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; ZVBB-NEXT: vslideup.vx v8, v10, a0
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: li a1, 12
; ZVBB-NEXT: mul a0, a0, a1
@@ -3656,7 +3667,11 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v14, 0
+; CHECK-NEXT: vmv1r.v v28, v13
+; CHECK-NEXT: vmv1r.v v26, v12
+; CHECK-NEXT: vmv1r.v v14, v11
+; CHECK-NEXT: vmv1r.v v15, v10
+; CHECK-NEXT: vmv.v.i v30, 0
; CHECK-NEXT: addi a3, sp, 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 3
@@ -3664,35 +3679,35 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vmerge.vim v16, v14, 1, v0
+; CHECK-NEXT: vmerge.vim v10, v30, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v22, v14, 1, v0
-; CHECK-NEXT: add a2, a3, a1
-; CHECK-NEXT: vmv4r.v v24, v16
+; CHECK-NEXT: vmerge.vim v16, v30, 1, v0
+; CHECK-NEXT: vmv2r.v v18, v10
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v18, v14, 1, v0
+; CHECK-NEXT: vmerge.vim v12, v30, 1, v0
+; CHECK-NEXT: vmv1r.v v19, v16
+; CHECK-NEXT: vmv1r.v v0, v15
+; CHECK-NEXT: vmerge.vim v24, v30, 1, v0
+; CHECK-NEXT: vmv1r.v v20, v12
+; CHECK-NEXT: vmv1r.v v0, v14
+; CHECK-NEXT: vmerge.vim v14, v30, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmerge.vim v26, v30, 1, v0
+; CHECK-NEXT: add a2, a3, a1
+; CHECK-NEXT: vmv1r.v v21, v24
; CHECK-NEXT: add a4, a2, a1
-; CHECK-NEXT: vmv1r.v v25, v22
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmerge.vim v8, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v26, v18
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v27, v8
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmerge.vim v10, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v28, v20
-; CHECK-NEXT: vmv1r.v v18, v23
+; CHECK-NEXT: vmv1r.v v22, v14
+; CHECK-NEXT: vmv1r.v v12, v17
; CHECK-NEXT: add a5, a4, a1
-; CHECK-NEXT: vmv1r.v v29, v10
-; CHECK-NEXT: vmv1r.v v20, v9
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: vmerge.vim v30, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v22, v11
+; CHECK-NEXT: vmv1r.v v23, v26
+; CHECK-NEXT: vmv1r.v v14, v25
+; CHECK-NEXT: vmv1r.v v0, v28
+; CHECK-NEXT: vmerge.vim v24, v30, 1, v0
+; CHECK-NEXT: vmv1r.v v16, v27
; CHECK-NEXT: vsetvli a6, zero, e8, m1, ta, ma
-; CHECK-NEXT: vsseg7e8.v v24, (a3)
-; CHECK-NEXT: vmv1r.v v23, v31
-; CHECK-NEXT: vsseg7e8.v v17, (a0)
+; CHECK-NEXT: vsseg7e8.v v18, (a3)
+; CHECK-NEXT: vmv1r.v v17, v25
+; CHECK-NEXT: vsseg7e8.v v11, (a0)
; CHECK-NEXT: vl1r.v v8, (a4)
; CHECK-NEXT: add a4, a5, a1
; CHECK-NEXT: vl1r.v v10, (a3)
@@ -3748,7 +3763,11 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; ZVBB-NEXT: mul a0, a0, a1
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; ZVBB-NEXT: vmv.v.i v14, 0
+; ZVBB-NEXT: vmv1r.v v28, v13
+; ZVBB-NEXT: vmv1r.v v26, v12
+; ZVBB-NEXT: vmv1r.v v14, v11
+; ZVBB-NEXT: vmv1r.v v15, v10
+; ZVBB-NEXT: vmv.v.i v30, 0
; ZVBB-NEXT: addi a3, sp, 16
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 3
@@ -3756,35 +3775,35 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; ZVBB-NEXT: add a0, sp, a0
; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: vmerge.vim v16, v14, 1, v0
+; ZVBB-NEXT: vmerge.vim v10, v30, 1, v0
; ZVBB-NEXT: vmv1r.v v0, v8
-; ZVBB-NEXT: vmerge.vim v22, v14, 1, v0
-; ZVBB-NEXT: add a2, a3, a1
-; ZVBB-NEXT: vmv4r.v v24, v16
+; ZVBB-NEXT: vmerge.vim v16, v30, 1, v0
+; ZVBB-NEXT: vmv2r.v v18, v10
; ZVBB-NEXT: vmv1r.v v0, v9
-; ZVBB-NEXT: vmerge.vim v18, v14, 1, v0
+; ZVBB-NEXT: vmerge.vim v12, v30, 1, v0
+; ZVBB-NEXT: vmv1r.v v19, v16
+; ZVBB-NEXT: vmv1r.v v0, v15
+; ZVBB-NEXT: vmerge.vim v24, v30, 1, v0
+; ZVBB-NEXT: vmv1r.v v20, v12
+; ZVBB-NEXT: vmv1r.v v0, v14
+; ZVBB-NEXT: vmerge.vim v14, v30, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v26
+; ZVBB-NEXT: vmerge.vim v26, v30, 1, v0
+; ZVBB-NEXT: add a2, a3, a1
+; ZVBB-NEXT: vmv1r.v v21, v24
; ZVBB-NEXT: add a4, a2, a1
-; ZVBB-NEXT: vmv1r.v v25, v22
-; ZVBB-NEXT: vmv1r.v v0, v10
-; ZVBB-NEXT: vmerge.vim v8, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v26, v18
-; ZVBB-NEXT: vmv1r.v v0, v11
-; ZVBB-NEXT: vmerge.vim v20, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v27, v8
-; ZVBB-NEXT: vmv1r.v v0, v12
-; ZVBB-NEXT: vmerge.vim v10, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v28, v20
-; ZVBB-NEXT: vmv1r.v v18, v23
+; ZVBB-NEXT: vmv1r.v v22, v14
+; ZVBB-NEXT: vmv1r.v v12, v17
; ZVBB-NEXT: add a5, a4, a1
-; ZVBB-NEXT: vmv1r.v v29, v10
-; ZVBB-NEXT: vmv1r.v v20, v9
-; ZVBB-NEXT: vmv1r.v v0, v13
-; ZVBB-NEXT: vmerge.vim v30, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v22, v11
+; ZVBB-NEXT: vmv1r.v v23, v26
+; ZVBB-NEXT: vmv1r.v v14, v25
+; ZVBB-NEXT: vmv1r.v v0, v28
+; ZVBB-NEXT: vmerge.vim v24, v30, 1, v0
+; ZVBB-NEXT: vmv1r.v v16, v27
; ZVBB-NEXT: vsetvli a6, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vsseg7e8.v v24, (a3)
-; ZVBB-NEXT: vmv1r.v v23, v31
-; ZVBB-NEXT: vsseg7e8.v v17, (a0)
+; ZVBB-NEXT: vsseg7e8.v v18, (a3)
+; ZVBB-NEXT: vmv1r.v v17, v25
+; ZVBB-NEXT: vsseg7e8.v v11, (a0)
; ZVBB-NEXT: vl1r.v v8, (a4)
; ZVBB-NEXT: add a4, a5, a1
; ZVBB-NEXT: vl1r.v v10, (a3)
@@ -5486,35 +5505,40 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv16i1(<vscale x 16 x i1
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v22, 0
-; CHECK-NEXT: vmerge.vim v24, v22, 1, v0
+; CHECK-NEXT: vmv1r.v v15, v13
+; CHECK-NEXT: vmv1r.v v13, v11
+; CHECK-NEXT: vmv1r.v v11, v9
+; CHECK-NEXT: vmv.v.i v6, 0
+; CHECK-NEXT: vmerge.vim v22, v6, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v16, v22, 1, v0
-; CHECK-NEXT: vmv1r.v v1, v24
-; CHECK-NEXT: vmv1r.v v2, v16
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v26, v22, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmerge.vim v18, v22, 1, v0
-; CHECK-NEXT: vmv1r.v v3, v26
-; CHECK-NEXT: vmv1r.v v4, v18
+; CHECK-NEXT: vmerge.vim v8, v6, 1, v0
+; CHECK-NEXT: vmv2r.v v28, v26
+; CHECK-NEXT: vmv2r.v v26, v24
+; CHECK-NEXT: vmv2r.v v24, v22
+; CHECK-NEXT: vmv1r.v v25, v8
; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: vmerge.vim v8, v22, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmerge.vim v20, v22, 1, v0
-; CHECK-NEXT: vmv1r.v v5, v8
-; CHECK-NEXT: vmv1r.v v6, v20
+; CHECK-NEXT: vmerge.vim v20, v6, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vim v10, v6, 1, v0
+; CHECK-NEXT: vmv1r.v v26, v20
+; CHECK-NEXT: vmv1r.v v27, v10
; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: vmerge.vim v10, v22, 1, v0
+; CHECK-NEXT: vmerge.vim v16, v6, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmerge.vim v12, v6, 1, v0
+; CHECK-NEXT: vmv1r.v v28, v16
+; CHECK-NEXT: vmv1r.v v29, v12
+; CHECK-NEXT: vmv1r.v v0, v15
+; CHECK-NEXT: vmerge.vim v18, v6, 1, v0
; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmerge.vim v22, v22, 1, v0
-; CHECK-NEXT: vmv1r.v v7, v10
-; CHECK-NEXT: vmv1r.v v8, v22
-; CHECK-NEXT: vmv1r.v v16, v25
+; CHECK-NEXT: vmerge.vim v14, v6, 1, v0
+; CHECK-NEXT: vmv1r.v v30, v18
+; CHECK-NEXT: vmv1r.v v31, v14
+; CHECK-NEXT: vmv1r.v v8, v23
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vsseg8e8.v v1, (a2)
-; CHECK-NEXT: vmv1r.v v18, v27
+; CHECK-NEXT: vsseg8e8.v v24, (a2)
+; CHECK-NEXT: vmv1r.v v10, v21
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
@@ -5526,10 +5550,10 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv16i1(<vscale x 16 x i1
; CHECK-NEXT: add a6, a4, a0
; CHECK-NEXT: add a7, a5, a0
; CHECK-NEXT: add t0, a6, a0
-; CHECK-NEXT: vmv1r.v v20, v9
+; CHECK-NEXT: vmv1r.v v12, v17
; CHECK-NEXT: add t1, a7, a0
-; CHECK-NEXT: vmv1r.v v22, v11
-; CHECK-NEXT: vsseg8e8.v v16, (a1)
+; CHECK-NEXT: vmv1r.v v14, v19
+; CHECK-NEXT: vsseg8e8.v v8, (a1)
; CHECK-NEXT: vl1r.v v8, (a5)
; CHECK-NEXT: add a5, t0, a0
; CHECK-NEXT: vl1r.v v12, (t1)
@@ -5585,35 +5609,40 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv16i1(<vscale x 16 x i1
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; ZVBB-NEXT: vmv.v.i v22, 0
-; ZVBB-NEXT: vmerge.vim v24, v22, 1, v0
+; ZVBB-NEXT: vmv1r.v v15, v13
+; ZVBB-NEXT: vmv1r.v v13, v11
+; ZVBB-NEXT: vmv1r.v v11, v9
+; ZVBB-NEXT: vmv.v.i v6, 0
+; ZVBB-NEXT: vmerge.vim v22, v6, 1, v0
; ZVBB-NEXT: vmv1r.v v0, v8
-; ZVBB-NEXT: vmerge.vim v16, v22, 1, v0
-; ZVBB-NEXT: vmv1r.v v1, v24
-; ZVBB-NEXT: vmv1r.v v2, v16
-; ZVBB-NEXT: vmv1r.v v0, v9
-; ZVBB-NEXT: vmerge.vim v26, v22, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v10
-; ZVBB-NEXT: vmerge.vim v18, v22, 1, v0
-; ZVBB-NEXT: vmv1r.v v3, v26
-; ZVBB-NEXT: vmv1r.v v4, v18
+; ZVBB-NEXT: vmerge.vim v8, v6, 1, v0
+; ZVBB-NEXT: vmv2r.v v28, v26
+; ZVBB-NEXT: vmv2r.v v26, v24
+; ZVBB-NEXT: vmv2r.v v24, v22
+; ZVBB-NEXT: vmv1r.v v25, v8
; ZVBB-NEXT: vmv1r.v v0, v11
-; ZVBB-NEXT: vmerge.vim v8, v22, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v12
-; ZVBB-NEXT: vmerge.vim v20, v22, 1, v0
-; ZVBB-NEXT: vmv1r.v v5, v8
-; ZVBB-NEXT: vmv1r.v v6, v20
+; ZVBB-NEXT: vmerge.vim v20, v6, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v10
+; ZVBB-NEXT: vmerge.vim v10, v6, 1, v0
+; ZVBB-NEXT: vmv1r.v v26, v20
+; ZVBB-NEXT: vmv1r.v v27, v10
; ZVBB-NEXT: vmv1r.v v0, v13
-; ZVBB-NEXT: vmerge.vim v10, v22, 1, v0
+; ZVBB-NEXT: vmerge.vim v16, v6, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v12
+; ZVBB-NEXT: vmerge.vim v12, v6, 1, v0
+; ZVBB-NEXT: vmv1r.v v28, v16
+; ZVBB-NEXT: vmv1r.v v29, v12
+; ZVBB-NEXT: vmv1r.v v0, v15
+; ZVBB-NEXT: vmerge.vim v18, v6, 1, v0
; ZVBB-NEXT: vmv1r.v v0, v14
-; ZVBB-NEXT: vmerge.vim v22, v22, 1, v0
-; ZVBB-NEXT: vmv1r.v v7, v10
-; ZVBB-NEXT: vmv1r.v v8, v22
-; ZVBB-NEXT: vmv1r.v v16, v25
+; ZVBB-NEXT: vmerge.vim v14, v6, 1, v0
+; ZVBB-NEXT: vmv1r.v v30, v18
+; ZVBB-NEXT: vmv1r.v v31, v14
+; ZVBB-NEXT: vmv1r.v v8, v23
; ZVBB-NEXT: addi a2, sp, 16
; ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vsseg8e8.v v1, (a2)
-; ZVBB-NEXT: vmv1r.v v18, v27
+; ZVBB-NEXT: vsseg8e8.v v24, (a2)
+; ZVBB-NEXT: vmv1r.v v10, v21
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: slli a1, a1, 3
; ZVBB-NEXT: add a1, sp, a1
@@ -5625,10 +5654,10 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv16i1(<vscale x 16 x i1
; ZVBB-NEXT: add a6, a4, a0
; ZVBB-NEXT: add a7, a5, a0
; ZVBB-NEXT: add t0, a6, a0
-; ZVBB-NEXT: vmv1r.v v20, v9
+; ZVBB-NEXT: vmv1r.v v12, v17
; ZVBB-NEXT: add t1, a7, a0
-; ZVBB-NEXT: vmv1r.v v22, v11
-; ZVBB-NEXT: vsseg8e8.v v16, (a1)
+; ZVBB-NEXT: vmv1r.v v14, v19
+; ZVBB-NEXT: vsseg8e8.v v8, (a1)
; ZVBB-NEXT: vl1r.v v8, (a5)
; ZVBB-NEXT: add a5, t0, a0
; ZVBB-NEXT: vl1r.v v12, (t1)
@@ -6528,9 +6557,9 @@ define <vscale x 4 x double> @vector_interleave_nxv4f64_nxv2f64(<vscale x 2 x do
; V-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; V-NEXT: vid.v v12
; V-NEXT: srli a0, a0, 2
-; V-NEXT: vand.vi v13, v12, 1
-; V-NEXT: vmsne.vi v0, v13, 0
; V-NEXT: vsrl.vi v16, v12, 1
+; V-NEXT: vand.vi v12, v12, 1
+; V-NEXT: vmsne.vi v0, v12, 0
; V-NEXT: vadd.vx v16, v16, a0, v0.t
; V-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; V-NEXT: vrgatherei16.vv v12, v8, v16
@@ -6543,9 +6572,9 @@ define <vscale x 4 x double> @vector_interleave_nxv4f64_nxv2f64(<vscale x 2 x do
; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; ZVBB-NEXT: vid.v v12
; ZVBB-NEXT: srli a0, a0, 2
-; ZVBB-NEXT: vand.vi v13, v12, 1
-; ZVBB-NEXT: vmsne.vi v0, v13, 0
; ZVBB-NEXT: vsrl.vi v16, v12, 1
+; ZVBB-NEXT: vand.vi v12, v12, 1
+; ZVBB-NEXT: vmsne.vi v0, v12, 0
; ZVBB-NEXT: vadd.vx v16, v16, a0, v0.t
; ZVBB-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; ZVBB-NEXT: vrgatherei16.vv v12, v8, v16
@@ -6691,13 +6720,13 @@ define <vscale x 16 x double> @vector_interleave_nxv16f64_nxv8f64(<vscale x 8 x
; V-NEXT: srli a0, a0, 1
; V-NEXT: vmv4r.v v28, v16
; V-NEXT: vmv4r.v v16, v12
+; V-NEXT: vsrl.vi v4, v6, 1
; V-NEXT: vand.vi v8, v6, 1
; V-NEXT: vmsne.vi v0, v8, 0
-; V-NEXT: vsrl.vi v6, v6, 1
-; V-NEXT: vadd.vx v6, v6, a0, v0.t
+; V-NEXT: vadd.vx v4, v4, a0, v0.t
; V-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; V-NEXT: vrgatherei16.vv v8, v24, v6
-; V-NEXT: vrgatherei16.vv v24, v16, v6
+; V-NEXT: vrgatherei16.vv v8, v24, v4
+; V-NEXT: vrgatherei16.vv v24, v16, v4
; V-NEXT: vmv.v.v v16, v24
; V-NEXT: ret
;
@@ -6710,13 +6739,13 @@ define <vscale x 16 x double> @vector_interleave_nxv16f64_nxv8f64(<vscale x 8 x
; ZVBB-NEXT: srli a0, a0, 1
; ZVBB-NEXT: vmv4r.v v28, v16
; ZVBB-NEXT: vmv4r.v v16, v12
+; ZVBB-NEXT: vsrl.vi v4, v6, 1
; ZVBB-NEXT: vand.vi v8, v6, 1
; ZVBB-NEXT: vmsne.vi v0, v8, 0
-; ZVBB-NEXT: vsrl.vi v6, v6, 1
-; ZVBB-NEXT: vadd.vx v6, v6, a0, v0.t
+; ZVBB-NEXT: vadd.vx v4, v4, a0, v0.t
; ZVBB-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; ZVBB-NEXT: vrgatherei16.vv v8, v24, v6
-; ZVBB-NEXT: vrgatherei16.vv v24, v16, v6
+; ZVBB-NEXT: vrgatherei16.vv v8, v24, v4
+; ZVBB-NEXT: vrgatherei16.vv v24, v16, v4
; ZVBB-NEXT: vmv.v.v v16, v24
; ZVBB-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
index cc389236df3ff..b619a4d5a2eba 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
@@ -14,17 +14,17 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_negone(<vscale x 1 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv1i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmerge.vim v10, v8, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 3
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
-; NOVLDEP-NEXT: vslideup.vi v8, v10, 1
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
; NOVLDEP-NEXT: vand.vi v8, v8, 1
; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
; NOVLDEP-NEXT: ret
@@ -32,19 +32,19 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_negone(<vscale x 1 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv1i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmerge.vim v10, v8, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: srli a0, a0, 3
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; VLDEP-NEXT: vslidedown.vx v8, v8, a0
; VLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; VLDEP-NEXT: vslideup.vi v8, v10, 1
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
; VLDEP-NEXT: vand.vi v8, v8, 1
; VLDEP-NEXT: vmsne.vi v0, v8, 0
; VLDEP-NEXT: ret
@@ -56,17 +56,17 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_max(<vscale x 1 x i1> %a, <vscale
; NOVLDEP-LABEL: splice_nxv1i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmerge.vim v10, v8, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 3
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 1
; NOVLDEP-NEXT: addi a0, a0, -1
-; NOVLDEP-NEXT: vslideup.vx v8, v10, a0
+; NOVLDEP-NEXT: vslideup.vx v8, v9, a0
; NOVLDEP-NEXT: vand.vi v8, v8, 1
; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
; NOVLDEP-NEXT: ret
@@ -74,19 +74,19 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_max(<vscale x 1 x i1> %a, <vscale
; VLDEP-LABEL: splice_nxv1i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmerge.vim v10, v8, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: srli a0, a0, 3
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLDEP-NEXT: vslidedown.vi v8, v8, 1
; VLDEP-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; VLDEP-NEXT: vslideup.vx v8, v10, a0
+; VLDEP-NEXT: vslideup.vx v8, v9, a0
; VLDEP-NEXT: vand.vi v8, v8, 1
; VLDEP-NEXT: vmsne.vi v0, v8, 0
; VLDEP-NEXT: ret
@@ -98,17 +98,17 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_negone(<vscale x 2 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv2i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmerge.vim v10, v8, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 2
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
-; NOVLDEP-NEXT: vslideup.vi v8, v10, 1
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
; NOVLDEP-NEXT: vand.vi v8, v8, 1
; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
; NOVLDEP-NEXT: ret
@@ -116,19 +116,19 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_negone(<vscale x 2 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv2i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmerge.vim v10, v8, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: srli a0, a0, 2
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; VLDEP-NEXT: vslidedown.vx v8, v8, a0
; VLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; VLDEP-NEXT: vslideup.vi v8, v10, 1
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
; VLDEP-NEXT: vand.vi v8, v8, 1
; VLDEP-NEXT: vmsne.vi v0, v8, 0
; VLDEP-NEXT: ret
@@ -140,17 +140,17 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_max(<vscale x 2 x i1> %a, <vscale
; NOVLDEP-LABEL: splice_nxv2i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmerge.vim v10, v8, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 2
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3
; NOVLDEP-NEXT: addi a0, a0, -3
-; NOVLDEP-NEXT: vslideup.vx v8, v10, a0
+; NOVLDEP-NEXT: vslideup.vx v8, v9, a0
; NOVLDEP-NEXT: vand.vi v8, v8, 1
; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
; NOVLDEP-NEXT: ret
@@ -158,19 +158,19 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_max(<vscale x 2 x i1> %a, <vscale
; VLDEP-LABEL: splice_nxv2i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmerge.vim v10, v8, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: srli a0, a0, 2
; VLDEP-NEXT: addi a0, a0, -3
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; VLDEP-NEXT: vslidedown.vi v8, v8, 3
; VLDEP-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; VLDEP-NEXT: vslideup.vx v8, v10, a0
+; VLDEP-NEXT: vslideup.vx v8, v9, a0
; VLDEP-NEXT: vand.vi v8, v8, 1
; VLDEP-NEXT: vmsne.vi v0, v8, 0
; VLDEP-NEXT: ret
@@ -182,17 +182,17 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_negone(<vscale x 4 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv4i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmerge.vim v10, v8, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 1
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
-; NOVLDEP-NEXT: vslideup.vi v8, v10, 1
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
; NOVLDEP-NEXT: vand.vi v8, v8, 1
; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
; NOVLDEP-NEXT: ret
@@ -200,19 +200,19 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_negone(<vscale x 4 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv4i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmerge.vim v10, v8, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: srli a0, a0, 1
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; VLDEP-NEXT: vslidedown.vx v8, v8, a0
; VLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; VLDEP-NEXT: vslideup.vi v8, v10, 1
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
; VLDEP-NEXT: vand.vi v8, v8, 1
; VLDEP-NEXT: vmsne.vi v0, v8, 0
; VLDEP-NEXT: ret
@@ -224,17 +224,17 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_max(<vscale x 4 x i1> %a, <vscale
; NOVLDEP-LABEL: splice_nxv4i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmerge.vim v10, v8, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 1
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 7
; NOVLDEP-NEXT: addi a0, a0, -7
-; NOVLDEP-NEXT: vslideup.vx v8, v10, a0
+; NOVLDEP-NEXT: vslideup.vx v8, v9, a0
; NOVLDEP-NEXT: vand.vi v8, v8, 1
; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
; NOVLDEP-NEXT: ret
@@ -242,19 +242,19 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_max(<vscale x 4 x i1> %a, <vscale
; VLDEP-LABEL: splice_nxv4i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmerge.vim v10, v8, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: srli a0, a0, 1
; VLDEP-NEXT: addi a0, a0, -7
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; VLDEP-NEXT: vslidedown.vi v8, v8, 7
; VLDEP-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; VLDEP-NEXT: vslideup.vx v8, v10, a0
+; VLDEP-NEXT: vslideup.vx v8, v9, a0
; VLDEP-NEXT: vand.vi v8, v8, 1
; VLDEP-NEXT: vmsne.vi v0, v8, 0
; VLDEP-NEXT: ret
@@ -266,16 +266,16 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_negone(<vscale x 8 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv8i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmerge.vim v10, v8, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
-; NOVLDEP-NEXT: vslideup.vi v8, v10, 1
+; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
; NOVLDEP-NEXT: vand.vi v8, v8, 1
; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
; NOVLDEP-NEXT: ret
@@ -283,18 +283,18 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_negone(<vscale x 8 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv8i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmerge.vim v10, v8, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; VLDEP-NEXT: vslidedown.vx v8, v8, a0
; VLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; VLDEP-NEXT: vslideup.vi v8, v10, 1
+; VLDEP-NEXT: vslideup.vi v8, v9, 1
; VLDEP-NEXT: vand.vi v8, v8, 1
; VLDEP-NEXT: vmsne.vi v0, v8, 0
; VLDEP-NEXT: ret
@@ -306,16 +306,16 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_max(<vscale x 8 x i1> %a, <vscale
; NOVLDEP-LABEL: splice_nxv8i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmerge.vim v10, v8, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 15
; NOVLDEP-NEXT: addi a0, a0, -15
-; NOVLDEP-NEXT: vslideup.vx v8, v10, a0
+; NOVLDEP-NEXT: vslideup.vx v8, v9, a0
; NOVLDEP-NEXT: vand.vi v8, v8, 1
; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
; NOVLDEP-NEXT: ret
@@ -323,18 +323,18 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_max(<vscale x 8 x i1> %a, <vscale
; VLDEP-LABEL: splice_nxv8i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmerge.vim v10, v8, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: addi a0, a0, -15
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; VLDEP-NEXT: vslidedown.vi v8, v8, 15
; VLDEP-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; VLDEP-NEXT: vslideup.vx v8, v10, a0
+; VLDEP-NEXT: vslideup.vx v8, v9, a0
; VLDEP-NEXT: vand.vi v8, v8, 1
; VLDEP-NEXT: vmsne.vi v0, v8, 0
; VLDEP-NEXT: ret
@@ -347,16 +347,16 @@ define <vscale x 16 x i1> @splice_nxv16i1_offset_negone(<vscale x 16 x i1> %a, <
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmerge.vim v12, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v10, v12, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
; NOVLDEP-NEXT: slli a0, a0, 1
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
-; NOVLDEP-NEXT: vslideup.vi v8, v12, 1
+; NOVLDEP-NEXT: vslideup.vi v8, v10, 1
; NOVLDEP-NEXT: vand.vi v8, v8, 1
; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
; NOVLDEP-NEXT: ret
@@ -365,18 +365,18 @@ define <vscale x 16 x i1> @splice_nxv16i1_offset_negone(<vscale x 16 x i1> %a, <
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmerge.vim v12, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v10, v12, 1, v0
; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
; VLDEP-NEXT: slli a0, a0, 1
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, m2, ta, ma
; VLDEP-NEXT: vslidedown.vx v8, v8, a0
; VLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; VLDEP-NEXT: vslideup.vi v8, v12, 1
+; VLDEP-NEXT: vslideup.vi v8, v10, 1
; VLDEP-NEXT: vand.vi v8, v8, 1
; VLDEP-NEXT: vmsne.vi v0, v8, 0
; VLDEP-NEXT: ret
@@ -389,16 +389,16 @@ define <vscale x 16 x i1> @splice_nxv16i1_offset_max(<vscale x 16 x i1> %a, <vsc
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmerge.vim v12, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v10, v12, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
; NOVLDEP-NEXT: slli a0, a0, 1
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 31
; NOVLDEP-NEXT: addi a0, a0, -31
-; NOVLDEP-NEXT: vslideup.vx v8, v12, a0
+; NOVLDEP-NEXT: vslideup.vx v8, v10, a0
; NOVLDEP-NEXT: vand.vi v8, v8, 1
; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
; NOVLDEP-NEXT: ret
@@ -407,18 +407,18 @@ define <vscale x 16 x i1> @splice_nxv16i1_offset_max(<vscale x 16 x i1> %a, <vsc
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmerge.vim v12, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v10, v12, 1, v0
; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
; VLDEP-NEXT: slli a0, a0, 1
; VLDEP-NEXT: addi a0, a0, -31
; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; VLDEP-NEXT: vslidedown.vi v8, v8, 31
; VLDEP-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; VLDEP-NEXT: vslideup.vx v8, v12, a0
+; VLDEP-NEXT: vslideup.vx v8, v10, a0
; VLDEP-NEXT: vand.vi v8, v8, 1
; VLDEP-NEXT: vmsne.vi v0, v8, 0
; VLDEP-NEXT: ret
@@ -431,16 +431,16 @@ define <vscale x 32 x i1> @splice_nxv32i1_offset_negone(<vscale x 32 x i1> %a, <
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v12, 0
+; NOVLDEP-NEXT: vmv.v.i v16, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmerge.vim v16, v12, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v12, v16, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
; NOVLDEP-NEXT: slli a0, a0, 2
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
-; NOVLDEP-NEXT: vslideup.vi v8, v16, 1
+; NOVLDEP-NEXT: vslideup.vi v8, v12, 1
; NOVLDEP-NEXT: vand.vi v8, v8, 1
; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
; NOVLDEP-NEXT: ret
@@ -449,18 +449,18 @@ define <vscale x 32 x i1> @splice_nxv32i1_offset_negone(<vscale x 32 x i1> %a, <
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v12, 0
+; VLDEP-NEXT: vmv.v.i v16, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmerge.vim v16, v12, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v12, v16, 1, v0
; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
; VLDEP-NEXT: slli a0, a0, 2
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, m4, ta, ma
; VLDEP-NEXT: vslidedown.vx v8, v8, a0
; VLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; VLDEP-NEXT: vslideup.vi v8, v16, 1
+; VLDEP-NEXT: vslideup.vi v8, v12, 1
; VLDEP-NEXT: vand.vi v8, v8, 1
; VLDEP-NEXT: vmsne.vi v0, v8, 0
; VLDEP-NEXT: ret
@@ -472,38 +472,36 @@ define <vscale x 32 x i1> @splice_nxv32i1_offset_max(<vscale x 32 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv32i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v12, 0
+; NOVLDEP-NEXT: vmv.v.i v16, 0
; NOVLDEP-NEXT: li a0, 63
-; NOVLDEP-NEXT: vmerge.vim v16, v12, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
-; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vmerge.vim v12, v16, 1, v0
+; NOVLDEP-NEXT: vslidedown.vx v12, v12, a0
; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
; NOVLDEP-NEXT: slli a0, a0, 2
; NOVLDEP-NEXT: addi a0, a0, -63
-; NOVLDEP-NEXT: vslideup.vx v8, v16, a0
-; NOVLDEP-NEXT: vand.vi v8, v8, 1
+; NOVLDEP-NEXT: vslideup.vx v12, v8, a0
+; NOVLDEP-NEXT: vand.vi v8, v12, 1
; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: splice_nxv32i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; VLDEP-NEXT: vmv.v.i v12, 0
+; VLDEP-NEXT: vmv.v.i v16, 0
; VLDEP-NEXT: csrr a0, vlenb
; VLDEP-NEXT: li a1, 63
-; VLDEP-NEXT: vmerge.vim v16, v12, 1, v0
+; VLDEP-NEXT: vmerge.vim v12, v16, 1, v0
; VLDEP-NEXT: slli a0, a0, 2
; VLDEP-NEXT: addi a0, a0, -63
; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; VLDEP-NEXT: vslidedown.vx v16, v16, a1
+; VLDEP-NEXT: vslidedown.vx v12, v12, a1
; VLDEP-NEXT: vmv1r.v v0, v8
; VLDEP-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
-; VLDEP-NEXT: vslideup.vx v16, v8, a0
-; VLDEP-NEXT: vand.vi v8, v16, 1
+; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; VLDEP-NEXT: vslideup.vx v12, v8, a0
+; VLDEP-NEXT: vand.vi v8, v12, 1
; VLDEP-NEXT: vmsne.vi v0, v8, 0
; VLDEP-NEXT: ret
%res = call <vscale x 32 x i1> @llvm.vector.splice.nxv32i1(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b, i32 63)
@@ -515,16 +513,16 @@ define <vscale x 64 x i1> @splice_nxv64i1_offset_negone(<vscale x 64 x i1> %a, <
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v16, 0
+; NOVLDEP-NEXT: vmv.v.i v24, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmerge.vim v24, v16, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v16, v24, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v24, 1, v0
; NOVLDEP-NEXT: slli a0, a0, 3
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
-; NOVLDEP-NEXT: vslideup.vi v8, v24, 1
+; NOVLDEP-NEXT: vslideup.vi v8, v16, 1
; NOVLDEP-NEXT: vand.vi v8, v8, 1
; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
; NOVLDEP-NEXT: ret
@@ -533,18 +531,18 @@ define <vscale x 64 x i1> @splice_nxv64i1_offset_negone(<vscale x 64 x i1> %a, <
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v16, 0
+; VLDEP-NEXT: vmv.v.i v24, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmerge.vim v24, v16, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v16, v24, 1, v0
; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v24, 1, v0
; VLDEP-NEXT: slli a0, a0, 3
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, m8, ta, ma
; VLDEP-NEXT: vslidedown.vx v8, v8, a0
; VLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; VLDEP-NEXT: vslideup.vi v8, v24, 1
+; VLDEP-NEXT: vslideup.vi v8, v16, 1
; VLDEP-NEXT: vand.vi v8, v8, 1
; VLDEP-NEXT: vmsne.vi v0, v8, 0
; VLDEP-NEXT: ret
@@ -556,38 +554,36 @@ define <vscale x 64 x i1> @splice_nxv64i1_offset_max(<vscale x 64 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv64i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v16, 0
+; NOVLDEP-NEXT: vmv.v.i v24, 0
; NOVLDEP-NEXT: li a0, 127
-; NOVLDEP-NEXT: vmerge.vim v24, v16, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
-; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vmerge.vim v16, v24, 1, v0
+; NOVLDEP-NEXT: vslidedown.vx v16, v16, a0
; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v8, v24, 1, v0
; NOVLDEP-NEXT: slli a0, a0, 3
; NOVLDEP-NEXT: addi a0, a0, -127
-; NOVLDEP-NEXT: vslideup.vx v8, v24, a0
-; NOVLDEP-NEXT: vand.vi v8, v8, 1
+; NOVLDEP-NEXT: vslideup.vx v16, v8, a0
+; NOVLDEP-NEXT: vand.vi v8, v16, 1
; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: splice_nxv64i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; VLDEP-NEXT: vmv.v.i v16, 0
+; VLDEP-NEXT: vmv.v.i v24, 0
; VLDEP-NEXT: csrr a0, vlenb
; VLDEP-NEXT: li a1, 127
-; VLDEP-NEXT: vmerge.vim v24, v16, 1, v0
+; VLDEP-NEXT: vmerge.vim v16, v24, 1, v0
; VLDEP-NEXT: slli a0, a0, 3
; VLDEP-NEXT: addi a0, a0, -127
; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; VLDEP-NEXT: vslidedown.vx v24, v24, a1
+; VLDEP-NEXT: vslidedown.vx v16, v16, a1
; VLDEP-NEXT: vmv1r.v v0, v8
; VLDEP-NEXT: vsetvli a1, zero, e8, m8, ta, ma
-; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
-; VLDEP-NEXT: vslideup.vx v24, v8, a0
-; VLDEP-NEXT: vand.vi v8, v24, 1
+; VLDEP-NEXT: vmerge.vim v8, v24, 1, v0
+; VLDEP-NEXT: vslideup.vx v16, v8, a0
+; VLDEP-NEXT: vand.vi v8, v16, 1
; VLDEP-NEXT: vmsne.vi v0, v8, 0
; VLDEP-NEXT: ret
%res = call <vscale x 64 x i1> @llvm.vector.splice.nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b, i32 127)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
index 54f1f324dafa4..00cfcde16969f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
@@ -745,11 +745,11 @@ define <vscale x 8 x double> @vfabs_vv_nxv8f64_unmasked(<vscale x 8 x double> %v
define <vscale x 16 x double> @vfabs_vv_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv16f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
index d03b068e11ea8..16de0a036d65e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
@@ -919,44 +919,86 @@ define <vscale x 32 x bfloat> @vfadd_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; ZVFH-NEXT: addi sp, sp, -16
; ZVFH-NEXT: .cfi_def_cfa_offset 16
; ZVFH-NEXT: csrr a1, vlenb
+; ZVFH-NEXT: mv a2, a1
; ZVFH-NEXT: slli a1, a1, 3
+; ZVFH-NEXT: add a2, a2, a1
+; ZVFH-NEXT: slli a1, a1, 1
+; ZVFH-NEXT: add a1, a1, a2
; ZVFH-NEXT: sub sp, sp, a1
-; ZVFH-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFH-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
; ZVFH-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFH-NEXT: vmv1r.v v7, v0
+; ZVFH-NEXT: vmv8r.v v24, v16
+; ZVFH-NEXT: vmv8r.v v16, v8
; ZVFH-NEXT: csrr a2, vlenb
; ZVFH-NEXT: slli a1, a2, 1
; ZVFH-NEXT: srli a2, a2, 2
; ZVFH-NEXT: sub a3, a0, a1
-; ZVFH-NEXT: vslidedown.vx v0, v0, a2
+; ZVFH-NEXT: csrr a4, vlenb
+; ZVFH-NEXT: slli a4, a4, 4
+; ZVFH-NEXT: add a4, sp, a4
+; ZVFH-NEXT: addi a4, a4, 16
+; ZVFH-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; ZVFH-NEXT: vslidedown.vx v7, v0, a2
; ZVFH-NEXT: sltu a2, a0, a3
; ZVFH-NEXT: addi a2, a2, -1
; ZVFH-NEXT: and a2, a2, a3
-; ZVFH-NEXT: addi a3, sp, 16
-; ZVFH-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFH-NEXT: vmv1r.v v0, v7
+; ZVFH-NEXT: csrr a3, vlenb
+; ZVFH-NEXT: slli a3, a3, 3
+; ZVFH-NEXT: add a3, sp, a3
+; ZVFH-NEXT: addi a3, a3, 16
+; ZVFH-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFH-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a3, a2, 4
+; ZVFH-NEXT: add a2, a3, a2
+; ZVFH-NEXT: add a2, sp, a2
+; ZVFH-NEXT: addi a2, a2, 16
+; ZVFH-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFH-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
-; ZVFH-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFH-NEXT: vfadd.vv v16, v16, v24, v0.t
+; ZVFH-NEXT: vfadd.vv v24, v24, v8, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFH-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
+; ZVFH-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
; ZVFH-NEXT: bltu a0, a1, .LBB22_2
; ZVFH-NEXT: # %bb.1:
; ZVFH-NEXT: mv a0, a1
; ZVFH-NEXT: .LBB22_2:
-; ZVFH-NEXT: vmv1r.v v0, v7
-; ZVFH-NEXT: addi a1, sp, 16
-; ZVFH-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFH-NEXT: csrr a1, vlenb
+; ZVFH-NEXT: slli a1, a1, 4
+; ZVFH-NEXT: add a1, sp, a1
+; ZVFH-NEXT: addi a1, a1, 16
+; ZVFH-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFH-NEXT: csrr a1, vlenb
+; ZVFH-NEXT: slli a1, a1, 3
+; ZVFH-NEXT: add a1, sp, a1
+; ZVFH-NEXT: addi a1, a1, 16
+; ZVFH-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFH-NEXT: vfwcvtbf16.f.f.v v24, v16, v0.t
+; ZVFH-NEXT: addi a0, sp, 16
+; ZVFH-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFH-NEXT: vmv1r.v v8, v0
+; ZVFH-NEXT: csrr a0, vlenb
+; ZVFH-NEXT: slli a1, a0, 4
+; ZVFH-NEXT: add a0, a1, a0
+; ZVFH-NEXT: add a0, sp, a0
+; ZVFH-NEXT: addi a0, a0, 16
+; ZVFH-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFH-NEXT: vfwcvtbf16.f.f.v v16, v24, v0.t
-; ZVFH-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t
+; ZVFH-NEXT: addi a0, sp, 16
+; ZVFH-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFH-NEXT: vfadd.vv v16, v24, v16, v0.t
+; ZVFH-NEXT: vfadd.vv v16, v16, v24, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFH-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; ZVFH-NEXT: csrr a0, vlenb
+; ZVFH-NEXT: mv a1, a0
; ZVFH-NEXT: slli a0, a0, 3
+; ZVFH-NEXT: add a1, a1, a0
+; ZVFH-NEXT: slli a0, a0, 1
+; ZVFH-NEXT: add a0, a0, a1
; ZVFH-NEXT: add sp, sp, a0
; ZVFH-NEXT: .cfi_def_cfa sp, 16
; ZVFH-NEXT: addi sp, sp, 16
@@ -968,44 +1010,86 @@ define <vscale x 32 x bfloat> @vfadd_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: mv a2, a1
; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a2, a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 4
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 4
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfadd.vv v24, v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB22_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: addi a1, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v8, v0
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v16, v24, v0.t
-; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfadd.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -1017,44 +1101,86 @@ define <vscale x 32 x bfloat> @vfadd_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; ZVFBFA-NEXT: addi sp, sp, -16
; ZVFBFA-NEXT: .cfi_def_cfa_offset 16
; ZVFBFA-NEXT: csrr a1, vlenb
+; ZVFBFA-NEXT: mv a2, a1
; ZVFBFA-NEXT: slli a1, a1, 3
+; ZVFBFA-NEXT: add a2, a2, a1
+; ZVFBFA-NEXT: slli a1, a1, 1
+; ZVFBFA-NEXT: add a1, a1, a2
; ZVFBFA-NEXT: sub sp, sp, a1
-; ZVFBFA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFBFA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
; ZVFBFA-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFBFA-NEXT: vmv1r.v v7, v0
+; ZVFBFA-NEXT: vmv8r.v v24, v16
+; ZVFBFA-NEXT: vmv8r.v v16, v8
; ZVFBFA-NEXT: csrr a2, vlenb
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
-; ZVFBFA-NEXT: vslidedown.vx v0, v0, a2
+; ZVFBFA-NEXT: csrr a4, vlenb
+; ZVFBFA-NEXT: slli a4, a4, 4
+; ZVFBFA-NEXT: add a4, sp, a4
+; ZVFBFA-NEXT: addi a4, a4, 16
+; ZVFBFA-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; ZVFBFA-NEXT: vslidedown.vx v7, v0, a2
; ZVFBFA-NEXT: sltu a2, a0, a3
; ZVFBFA-NEXT: addi a2, a2, -1
; ZVFBFA-NEXT: and a2, a2, a3
-; ZVFBFA-NEXT: addi a3, sp, 16
-; ZVFBFA-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vmv1r.v v0, v7
+; ZVFBFA-NEXT: csrr a3, vlenb
+; ZVFBFA-NEXT: slli a3, a3, 3
+; ZVFBFA-NEXT: add a3, sp, a3
+; ZVFBFA-NEXT: addi a3, a3, 16
+; ZVFBFA-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFBFA-NEXT: vsetvli zero, a2, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a3, a2, 4
+; ZVFBFA-NEXT: add a2, a3, a2
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFBFA-NEXT: vfadd.vv v16, v16, v24, v0.t
+; ZVFBFA-NEXT: vfadd.vv v24, v24, v8, v0.t
; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
-; ZVFBFA-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFBFA-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFBFA-NEXT: bltu a0, a1, .LBB22_2
; ZVFBFA-NEXT: # %bb.1:
; ZVFBFA-NEXT: mv a0, a1
; ZVFBFA-NEXT: .LBB22_2:
-; ZVFBFA-NEXT: vmv1r.v v0, v7
-; ZVFBFA-NEXT: addi a1, sp, 16
-; ZVFBFA-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFBFA-NEXT: csrr a1, vlenb
+; ZVFBFA-NEXT: slli a1, a1, 4
+; ZVFBFA-NEXT: add a1, sp, a1
+; ZVFBFA-NEXT: addi a1, a1, 16
+; ZVFBFA-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFBFA-NEXT: csrr a1, vlenb
+; ZVFBFA-NEXT: slli a1, a1, 3
+; ZVFBFA-NEXT: add a1, sp, a1
+; ZVFBFA-NEXT: addi a1, a1, 16
+; ZVFBFA-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFBFA-NEXT: addi a0, sp, 16
+; ZVFBFA-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vmv1r.v v8, v0
+; ZVFBFA-NEXT: csrr a0, vlenb
+; ZVFBFA-NEXT: slli a1, a0, 4
+; ZVFBFA-NEXT: add a0, a1, a0
+; ZVFBFA-NEXT: add a0, sp, a0
+; ZVFBFA-NEXT: addi a0, a0, 16
+; ZVFBFA-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v24, v0.t
-; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v8, v0.t
+; ZVFBFA-NEXT: addi a0, sp, 16
+; ZVFBFA-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFBFA-NEXT: vfadd.vv v16, v24, v16, v0.t
+; ZVFBFA-NEXT: vfadd.vv v16, v16, v24, v0.t
; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
; ZVFBFA-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFBFA-NEXT: csrr a0, vlenb
+; ZVFBFA-NEXT: mv a1, a0
; ZVFBFA-NEXT: slli a0, a0, 3
+; ZVFBFA-NEXT: add a1, a1, a0
+; ZVFBFA-NEXT: slli a0, a0, 1
+; ZVFBFA-NEXT: add a0, a0, a1
; ZVFBFA-NEXT: add sp, sp, a0
; ZVFBFA-NEXT: .cfi_def_cfa sp, 16
; ZVFBFA-NEXT: addi sp, sp, 16
@@ -1070,44 +1196,83 @@ define <vscale x 32 x bfloat> @vfadd_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; ZVFH-NEXT: addi sp, sp, -16
; ZVFH-NEXT: .cfi_def_cfa_offset 16
; ZVFH-NEXT: csrr a1, vlenb
-; ZVFH-NEXT: slli a1, a1, 3
+; ZVFH-NEXT: slli a2, a1, 4
+; ZVFH-NEXT: add a1, a2, a1
; ZVFH-NEXT: sub sp, sp, a1
-; ZVFH-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
; ZVFH-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; ZVFH-NEXT: vmset.m v24
+; ZVFH-NEXT: vmv8r.v v24, v16
+; ZVFH-NEXT: vmv8r.v v16, v8
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: vmset.m v8
; ZVFH-NEXT: slli a1, a2, 1
; ZVFH-NEXT: srli a2, a2, 2
; ZVFH-NEXT: sub a3, a0, a1
; ZVFH-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFH-NEXT: vslidedown.vx v0, v24, a2
+; ZVFH-NEXT: vslidedown.vx v8, v8, a2
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a2, a2, 4
+; ZVFH-NEXT: add a2, sp, a2
+; ZVFH-NEXT: addi a2, a2, 16
+; ZVFH-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; ZVFH-NEXT: sltu a2, a0, a3
; ZVFH-NEXT: addi a2, a2, -1
; ZVFH-NEXT: and a2, a2, a3
+; ZVFH-NEXT: csrr a3, vlenb
+; ZVFH-NEXT: slli a3, a3, 4
+; ZVFH-NEXT: add a3, sp, a3
+; ZVFH-NEXT: addi a3, a3, 16
+; ZVFH-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFH-NEXT: addi a3, sp, 16
-; ZVFH-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFH-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFH-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a2, a2, 4
+; ZVFH-NEXT: add a2, sp, a2
+; ZVFH-NEXT: addi a2, a2, 16
+; ZVFH-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a2, a2, 3
+; ZVFH-NEXT: add a2, sp, a2
+; ZVFH-NEXT: addi a2, a2, 16
+; ZVFH-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFH-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
-; ZVFH-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a2, a2, 4
+; ZVFH-NEXT: add a2, sp, a2
+; ZVFH-NEXT: addi a2, a2, 16
+; ZVFH-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFH-NEXT: vfadd.vv v16, v16, v24, v0.t
+; ZVFH-NEXT: vfadd.vv v24, v24, v8, v0.t
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a2, a2, 4
+; ZVFH-NEXT: add a2, sp, a2
+; ZVFH-NEXT: addi a2, a2, 16
+; ZVFH-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFH-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
+; ZVFH-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
; ZVFH-NEXT: bltu a0, a1, .LBB23_2
; ZVFH-NEXT: # %bb.1:
; ZVFH-NEXT: mv a0, a1
; ZVFH-NEXT: .LBB23_2:
; ZVFH-NEXT: addi a1, sp, 16
-; ZVFH-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFH-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfwcvtbf16.f.f.v v16, v24
-; ZVFH-NEXT: vfwcvtbf16.f.f.v v24, v8
+; ZVFH-NEXT: vfwcvtbf16.f.f.v v24, v16
+; ZVFH-NEXT: csrr a0, vlenb
+; ZVFH-NEXT: slli a0, a0, 3
+; ZVFH-NEXT: add a0, sp, a0
+; ZVFH-NEXT: addi a0, a0, 16
+; ZVFH-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; ZVFH-NEXT: vfwcvtbf16.f.f.v v16, v0
; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFH-NEXT: vfadd.vv v16, v24, v16
+; ZVFH-NEXT: vfadd.vv v16, v16, v24
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFH-NEXT: vfncvtbf16.f.f.w v8, v16
; ZVFH-NEXT: csrr a0, vlenb
-; ZVFH-NEXT: slli a0, a0, 3
+; ZVFH-NEXT: slli a1, a0, 4
+; ZVFH-NEXT: add a0, a1, a0
; ZVFH-NEXT: add sp, sp, a0
; ZVFH-NEXT: .cfi_def_cfa sp, 16
; ZVFH-NEXT: addi sp, sp, 16
@@ -1119,44 +1284,83 @@ define <vscale x 32 x bfloat> @vfadd_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a2, a1, 4
+; ZVFHMIN-NEXT: add a1, a2, a1
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; ZVFHMIN-NEXT: vmset.m v24
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: vmset.m v8
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfadd.vv v24, v24, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB23_2:
; ZVFHMIN-NEXT: addi a1, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v16, v24
-; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v24, v8
+; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v24, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v16, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfadd.vv v16, v24, v16
+; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -1168,44 +1372,83 @@ define <vscale x 32 x bfloat> @vfadd_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; ZVFBFA-NEXT: addi sp, sp, -16
; ZVFBFA-NEXT: .cfi_def_cfa_offset 16
; ZVFBFA-NEXT: csrr a1, vlenb
-; ZVFBFA-NEXT: slli a1, a1, 3
+; ZVFBFA-NEXT: slli a2, a1, 4
+; ZVFBFA-NEXT: add a1, a2, a1
; ZVFBFA-NEXT: sub sp, sp, a1
-; ZVFBFA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
; ZVFBFA-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; ZVFBFA-NEXT: vmset.m v24
+; ZVFBFA-NEXT: vmv8r.v v24, v16
+; ZVFBFA-NEXT: vmv8r.v v16, v8
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: vmset.m v8
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
; ZVFBFA-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFBFA-NEXT: vslidedown.vx v0, v24, a2
+; ZVFBFA-NEXT: vslidedown.vx v8, v8, a2
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 4
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; ZVFBFA-NEXT: sltu a2, a0, a3
; ZVFBFA-NEXT: addi a2, a2, -1
; ZVFBFA-NEXT: and a2, a2, a3
+; ZVFBFA-NEXT: csrr a3, vlenb
+; ZVFBFA-NEXT: slli a3, a3, 4
+; ZVFBFA-NEXT: add a3, sp, a3
+; ZVFBFA-NEXT: addi a3, a3, 16
+; ZVFBFA-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFBFA-NEXT: addi a3, sp, 16
-; ZVFBFA-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFBFA-NEXT: vsetvli zero, a2, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 4
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 3
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 4
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFBFA-NEXT: vfadd.vv v16, v16, v24, v0.t
+; ZVFBFA-NEXT: vfadd.vv v24, v24, v8, v0.t
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 4
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
-; ZVFBFA-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFBFA-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFBFA-NEXT: bltu a0, a1, .LBB23_2
; ZVFBFA-NEXT: # %bb.1:
; ZVFBFA-NEXT: mv a0, a1
; ZVFBFA-NEXT: .LBB23_2:
; ZVFBFA-NEXT: addi a1, sp, 16
-; ZVFBFA-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFBFA-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
-; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v24
-; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v8
+; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFBFA-NEXT: csrr a0, vlenb
+; ZVFBFA-NEXT: slli a0, a0, 3
+; ZVFBFA-NEXT: add a0, sp, a0
+; ZVFBFA-NEXT: addi a0, a0, 16
+; ZVFBFA-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v0
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFBFA-NEXT: vfadd.vv v16, v24, v16
+; ZVFBFA-NEXT: vfadd.vv v16, v16, v24
; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
; ZVFBFA-NEXT: vfncvt.f.f.w v8, v16
; ZVFBFA-NEXT: csrr a0, vlenb
-; ZVFBFA-NEXT: slli a0, a0, 3
+; ZVFBFA-NEXT: slli a1, a0, 4
+; ZVFBFA-NEXT: add a0, a1, a0
; ZVFBFA-NEXT: add sp, sp, a0
; ZVFBFA-NEXT: .cfi_def_cfa sp, 16
; ZVFBFA-NEXT: addi sp, sp, 16
@@ -1224,16 +1467,16 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; ZVFH-NEXT: slli a1, a1, 4
; ZVFH-NEXT: sub sp, sp, a1
; ZVFH-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; ZVFH-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFH-NEXT: vmv1r.v v7, v0
; ZVFH-NEXT: fmv.x.h a1, fa0
; ZVFH-NEXT: csrr a2, vlenb
-; ZVFH-NEXT: vmv.v.x v24, a1
+; ZVFH-NEXT: vsetvli a3, zero, e16, m8, ta, ma
+; ZVFH-NEXT: vmv.v.x v16, a1
; ZVFH-NEXT: slli a1, a2, 1
; ZVFH-NEXT: srli a2, a2, 2
; ZVFH-NEXT: sub a3, a0, a1
+; ZVFH-NEXT: vmv1r.v v7, v0
; ZVFH-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFH-NEXT: vslidedown.vx v0, v0, a2
+; ZVFH-NEXT: vslidedown.vx v6, v0, a2
; ZVFH-NEXT: sltu a2, a0, a3
; ZVFH-NEXT: addi a2, a2, -1
; ZVFH-NEXT: and a2, a2, a3
@@ -1241,12 +1484,13 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; ZVFH-NEXT: slli a3, a3, 3
; ZVFH-NEXT: add a3, sp, a3
; ZVFH-NEXT: addi a3, a3, 16
-; ZVFH-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVFH-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFH-NEXT: vmv1r.v v0, v6
; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFH-NEXT: vfwcvtbf16.f.f.v v16, v28, v0.t
-; ZVFH-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; ZVFH-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
+; ZVFH-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFH-NEXT: vfadd.vv v16, v24, v16, v0.t
+; ZVFH-NEXT: vfadd.vv v16, v16, v24, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFH-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; ZVFH-NEXT: bltu a0, a1, .LBB24_2
@@ -1258,6 +1502,7 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; ZVFH-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; ZVFH-NEXT: addi a0, sp, 16
; ZVFH-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFH-NEXT: vmv1r.v v8, v7
; ZVFH-NEXT: csrr a0, vlenb
; ZVFH-NEXT: slli a0, a0, 3
; ZVFH-NEXT: add a0, sp, a0
@@ -1286,16 +1531,16 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: sub sp, sp, a1
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: vmv.v.x v24, a1
+; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v16, a1
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
+; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
@@ -1303,12 +1548,13 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v16, v28, v0.t
-; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfadd.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB24_2
@@ -1320,6 +1566,7 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v8, v7
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
@@ -1349,24 +1596,25 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; ZVFBFA-NEXT: sub sp, sp, a1
; ZVFBFA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; ZVFBFA-NEXT: vsetvli a1, zero, e16alt, m8, ta, ma
-; ZVFBFA-NEXT: vmv1r.v v7, v0
-; ZVFBFA-NEXT: vfmv.v.f v24, fa0
+; ZVFBFA-NEXT: vfmv.v.f v16, fa0
; ZVFBFA-NEXT: csrr a2, vlenb
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
+; ZVFBFA-NEXT: vmv1r.v v7, v0
; ZVFBFA-NEXT: vsetvli a4, zero, e8alt, mf2, ta, ma
-; ZVFBFA-NEXT: vslidedown.vx v0, v0, a2
+; ZVFBFA-NEXT: vslidedown.vx v6, v0, a2
; ZVFBFA-NEXT: sltu a2, a0, a3
; ZVFBFA-NEXT: addi a2, a2, -1
; ZVFBFA-NEXT: and a2, a2, a3
; ZVFBFA-NEXT: addi a3, sp, 16
-; ZVFBFA-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vmv1r.v v0, v6
; ZVFBFA-NEXT: vsetvli zero, a2, e16alt, m4, ta, ma
-; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v28, v0.t
-; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFBFA-NEXT: vfadd.vv v16, v24, v16, v0.t
+; ZVFBFA-NEXT: vfadd.vv v16, v16, v24, v0.t
; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
; ZVFBFA-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFBFA-NEXT: bltu a0, a1, .LBB24_2
@@ -1402,37 +1650,78 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16_unmasked(<vscale x 32 x bfloat
; ZVFH-NEXT: addi sp, sp, -16
; ZVFH-NEXT: .cfi_def_cfa_offset 16
; ZVFH-NEXT: csrr a1, vlenb
-; ZVFH-NEXT: slli a1, a1, 3
+; ZVFH-NEXT: slli a2, a1, 4
+; ZVFH-NEXT: add a1, a2, a1
; ZVFH-NEXT: sub sp, sp, a1
-; ZVFH-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFH-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
+; ZVFH-NEXT: csrr a1, vlenb
+; ZVFH-NEXT: slli a1, a1, 3
+; ZVFH-NEXT: add a1, sp, a1
+; ZVFH-NEXT: addi a1, a1, 16
+; ZVFH-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; ZVFH-NEXT: fmv.x.h a1, fa0
; ZVFH-NEXT: csrr a2, vlenb
; ZVFH-NEXT: vsetvli a3, zero, e16, m8, ta, ma
-; ZVFH-NEXT: vmset.m v24
-; ZVFH-NEXT: vmv.v.x v16, a1
+; ZVFH-NEXT: vmset.m v16
+; ZVFH-NEXT: vmv.v.x v8, a1
; ZVFH-NEXT: slli a1, a2, 1
; ZVFH-NEXT: srli a2, a2, 2
; ZVFH-NEXT: sub a3, a0, a1
; ZVFH-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFH-NEXT: vslidedown.vx v0, v24, a2
+; ZVFH-NEXT: vslidedown.vx v16, v16, a2
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a2, a2, 4
+; ZVFH-NEXT: add a2, sp, a2
+; ZVFH-NEXT: addi a2, a2, 16
+; ZVFH-NEXT: vs1r.v v16, (a2) # vscale x 8-byte Folded Spill
; ZVFH-NEXT: sltu a2, a0, a3
; ZVFH-NEXT: addi a2, a2, -1
; ZVFH-NEXT: and a2, a2, a3
+; ZVFH-NEXT: csrr a3, vlenb
+; ZVFH-NEXT: slli a3, a3, 4
+; ZVFH-NEXT: add a3, sp, a3
+; ZVFH-NEXT: addi a3, a3, 16
+; ZVFH-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFH-NEXT: addi a3, sp, 16
-; ZVFH-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFH-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFH-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
+; ZVFH-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a2, a2, 4
+; ZVFH-NEXT: add a2, sp, a2
+; ZVFH-NEXT: addi a2, a2, 16
+; ZVFH-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a2, a2, 3
+; ZVFH-NEXT: add a2, sp, a2
+; ZVFH-NEXT: addi a2, a2, 16
+; ZVFH-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFH-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a2, a2, 4
+; ZVFH-NEXT: add a2, sp, a2
+; ZVFH-NEXT: addi a2, a2, 16
+; ZVFH-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFH-NEXT: vfadd.vv v16, v16, v24, v0.t
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a2, a2, 4
+; ZVFH-NEXT: add a2, sp, a2
+; ZVFH-NEXT: addi a2, a2, 16
+; ZVFH-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFH-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; ZVFH-NEXT: bltu a0, a1, .LBB25_2
; ZVFH-NEXT: # %bb.1:
; ZVFH-NEXT: mv a0, a1
; ZVFH-NEXT: .LBB25_2:
+; ZVFH-NEXT: csrr a1, vlenb
+; ZVFH-NEXT: slli a1, a1, 3
+; ZVFH-NEXT: add a1, sp, a1
+; ZVFH-NEXT: addi a1, a1, 16
+; ZVFH-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; ZVFH-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFH-NEXT: vfwcvtbf16.f.f.v v16, v8
+; ZVFH-NEXT: vfwcvtbf16.f.f.v v16, v24
; ZVFH-NEXT: addi a0, sp, 16
; ZVFH-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; ZVFH-NEXT: vfwcvtbf16.f.f.v v24, v0
@@ -1441,7 +1730,8 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16_unmasked(<vscale x 32 x bfloat
; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFH-NEXT: vfncvtbf16.f.f.w v8, v16
; ZVFH-NEXT: csrr a0, vlenb
-; ZVFH-NEXT: slli a0, a0, 3
+; ZVFH-NEXT: slli a1, a0, 4
+; ZVFH-NEXT: add a0, a1, a0
; ZVFH-NEXT: add sp, sp, a0
; ZVFH-NEXT: .cfi_def_cfa sp, 16
; ZVFH-NEXT: addi sp, sp, 16
@@ -1453,37 +1743,78 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16_unmasked(<vscale x 32 x bfloat
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a2, a1, 4
+; ZVFHMIN-NEXT: add a1, a2, a1
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmset.m v24
-; ZVFHMIN-NEXT: vmv.v.x v16, a1
+; ZVFHMIN-NEXT: vmset.m v16
+; ZVFHMIN-NEXT: vmv.v.x v8, a1
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2
+; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v16, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB25_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB25_2:
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v16, v8
+; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v16, v24
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v24, v0
@@ -1492,7 +1823,8 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16_unmasked(<vscale x 32 x bfloat
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvtbf16.f.f.w v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -1504,28 +1836,64 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16_unmasked(<vscale x 32 x bfloat
; ZVFBFA-NEXT: addi sp, sp, -16
; ZVFBFA-NEXT: .cfi_def_cfa_offset 16
; ZVFBFA-NEXT: csrr a1, vlenb
-; ZVFBFA-NEXT: slli a1, a1, 3
+; ZVFBFA-NEXT: slli a2, a1, 4
+; ZVFBFA-NEXT: add a1, a2, a1
; ZVFBFA-NEXT: sub sp, sp, a1
-; ZVFBFA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFBFA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
+; ZVFBFA-NEXT: csrr a1, vlenb
+; ZVFBFA-NEXT: slli a1, a1, 3
+; ZVFBFA-NEXT: add a1, sp, a1
+; ZVFBFA-NEXT: addi a1, a1, 16
+; ZVFBFA-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; ZVFBFA-NEXT: vsetvli a1, zero, e16alt, m8, ta, ma
-; ZVFBFA-NEXT: vfmv.v.f v16, fa0
+; ZVFBFA-NEXT: vfmv.v.f v24, fa0
; ZVFBFA-NEXT: csrr a2, vlenb
-; ZVFBFA-NEXT: vmset.m v24
+; ZVFBFA-NEXT: vmset.m v16
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
; ZVFBFA-NEXT: vsetvli a4, zero, e8alt, mf2, ta, ma
-; ZVFBFA-NEXT: vslidedown.vx v0, v24, a2
+; ZVFBFA-NEXT: vslidedown.vx v16, v16, a2
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 4
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vs1r.v v16, (a2) # vscale x 8-byte Folded Spill
; ZVFBFA-NEXT: sltu a2, a0, a3
; ZVFBFA-NEXT: addi a2, a2, -1
; ZVFBFA-NEXT: and a2, a2, a3
+; ZVFBFA-NEXT: csrr a3, vlenb
+; ZVFBFA-NEXT: slli a3, a3, 4
+; ZVFBFA-NEXT: add a3, sp, a3
+; ZVFBFA-NEXT: addi a3, a3, 16
+; ZVFBFA-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFBFA-NEXT: addi a3, sp, 16
-; ZVFBFA-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFBFA-NEXT: vsetvli zero, a2, e16alt, m4, ta, ma
-; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFBFA-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 4
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 3
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 4
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFBFA-NEXT: vfadd.vv v16, v16, v24, v0.t
+; ZVFBFA-NEXT: vfadd.vv v16, v16, v8, v0.t
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 4
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
; ZVFBFA-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFBFA-NEXT: bltu a0, a1, .LBB25_2
@@ -1536,13 +1904,19 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16_unmasked(<vscale x 32 x bfloat
; ZVFBFA-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; ZVFBFA-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v24
-; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v8
+; ZVFBFA-NEXT: csrr a0, vlenb
+; ZVFBFA-NEXT: slli a0, a0, 3
+; ZVFBFA-NEXT: add a0, sp, a0
+; ZVFBFA-NEXT: addi a0, a0, 16
+; ZVFBFA-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v0
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFA-NEXT: vfadd.vv v16, v24, v16
; ZVFBFA-NEXT: vsetvli zero, zero, e16alt, m4, ta, ma
; ZVFBFA-NEXT: vfncvt.f.f.w v8, v16
; ZVFBFA-NEXT: csrr a0, vlenb
-; ZVFBFA-NEXT: slli a0, a0, 3
+; ZVFBFA-NEXT: slli a1, a0, 4
+; ZVFBFA-NEXT: add a0, a1, a0
; ZVFBFA-NEXT: add sp, sp, a0
; ZVFBFA-NEXT: .cfi_def_cfa sp, 16
; ZVFBFA-NEXT: addi sp, sp, 16
@@ -2342,44 +2716,86 @@ define <vscale x 32 x half> @vfadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: mv a2, a1
; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a2, a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 4
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 4
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfadd.vv v24, v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB48_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB48_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: addi a1, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v8, v0
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfadd.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -2391,44 +2807,86 @@ define <vscale x 32 x half> @vfadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFBFA-NEXT: addi sp, sp, -16
; ZVFBFA-NEXT: .cfi_def_cfa_offset 16
; ZVFBFA-NEXT: csrr a1, vlenb
+; ZVFBFA-NEXT: mv a2, a1
; ZVFBFA-NEXT: slli a1, a1, 3
+; ZVFBFA-NEXT: add a2, a2, a1
+; ZVFBFA-NEXT: slli a1, a1, 1
+; ZVFBFA-NEXT: add a1, a1, a2
; ZVFBFA-NEXT: sub sp, sp, a1
-; ZVFBFA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFBFA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
; ZVFBFA-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFBFA-NEXT: vmv1r.v v7, v0
+; ZVFBFA-NEXT: vmv8r.v v24, v16
+; ZVFBFA-NEXT: vmv8r.v v16, v8
; ZVFBFA-NEXT: csrr a2, vlenb
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
-; ZVFBFA-NEXT: vslidedown.vx v0, v0, a2
+; ZVFBFA-NEXT: csrr a4, vlenb
+; ZVFBFA-NEXT: slli a4, a4, 4
+; ZVFBFA-NEXT: add a4, sp, a4
+; ZVFBFA-NEXT: addi a4, a4, 16
+; ZVFBFA-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; ZVFBFA-NEXT: vslidedown.vx v7, v0, a2
; ZVFBFA-NEXT: sltu a2, a0, a3
; ZVFBFA-NEXT: addi a2, a2, -1
; ZVFBFA-NEXT: and a2, a2, a3
-; ZVFBFA-NEXT: addi a3, sp, 16
-; ZVFBFA-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vmv1r.v v0, v7
+; ZVFBFA-NEXT: csrr a3, vlenb
+; ZVFBFA-NEXT: slli a3, a3, 3
+; ZVFBFA-NEXT: add a3, sp, a3
+; ZVFBFA-NEXT: addi a3, a3, 16
+; ZVFBFA-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFBFA-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a3, a2, 4
+; ZVFBFA-NEXT: add a2, a3, a2
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFBFA-NEXT: vfadd.vv v16, v16, v24, v0.t
+; ZVFBFA-NEXT: vfadd.vv v24, v24, v8, v0.t
; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFBFA-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFBFA-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFBFA-NEXT: bltu a0, a1, .LBB48_2
; ZVFBFA-NEXT: # %bb.1:
; ZVFBFA-NEXT: mv a0, a1
; ZVFBFA-NEXT: .LBB48_2:
-; ZVFBFA-NEXT: vmv1r.v v0, v7
-; ZVFBFA-NEXT: addi a1, sp, 16
-; ZVFBFA-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFBFA-NEXT: csrr a1, vlenb
+; ZVFBFA-NEXT: slli a1, a1, 4
+; ZVFBFA-NEXT: add a1, sp, a1
+; ZVFBFA-NEXT: addi a1, a1, 16
+; ZVFBFA-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFBFA-NEXT: csrr a1, vlenb
+; ZVFBFA-NEXT: slli a1, a1, 3
+; ZVFBFA-NEXT: add a1, sp, a1
+; ZVFBFA-NEXT: addi a1, a1, 16
+; ZVFBFA-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFBFA-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFBFA-NEXT: addi a0, sp, 16
+; ZVFBFA-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vmv1r.v v8, v0
+; ZVFBFA-NEXT: csrr a0, vlenb
+; ZVFBFA-NEXT: slli a1, a0, 4
+; ZVFBFA-NEXT: add a0, a1, a0
+; ZVFBFA-NEXT: add a0, sp, a0
+; ZVFBFA-NEXT: addi a0, a0, 16
+; ZVFBFA-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v24, v0.t
-; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v8, v0.t
+; ZVFBFA-NEXT: addi a0, sp, 16
+; ZVFBFA-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFBFA-NEXT: vfadd.vv v16, v24, v16, v0.t
+; ZVFBFA-NEXT: vfadd.vv v16, v16, v24, v0.t
; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFBFA-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFBFA-NEXT: csrr a0, vlenb
+; ZVFBFA-NEXT: mv a1, a0
; ZVFBFA-NEXT: slli a0, a0, 3
+; ZVFBFA-NEXT: add a1, a1, a0
+; ZVFBFA-NEXT: slli a0, a0, 1
+; ZVFBFA-NEXT: add a0, a0, a1
; ZVFBFA-NEXT: add sp, sp, a0
; ZVFBFA-NEXT: .cfi_def_cfa sp, 16
; ZVFBFA-NEXT: addi sp, sp, 16
@@ -2450,44 +2908,83 @@ define <vscale x 32 x half> @vfadd_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a2, a1, 4
+; ZVFHMIN-NEXT: add a1, a2, a1
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; ZVFHMIN-NEXT: vmset.m v24
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: vmset.m v8
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfadd.vv v24, v24, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB49_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB49_2:
; ZVFHMIN-NEXT: addi a1, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfadd.vv v16, v24, v16
+; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -2499,44 +2996,83 @@ define <vscale x 32 x half> @vfadd_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFBFA-NEXT: addi sp, sp, -16
; ZVFBFA-NEXT: .cfi_def_cfa_offset 16
; ZVFBFA-NEXT: csrr a1, vlenb
-; ZVFBFA-NEXT: slli a1, a1, 3
+; ZVFBFA-NEXT: slli a2, a1, 4
+; ZVFBFA-NEXT: add a1, a2, a1
; ZVFBFA-NEXT: sub sp, sp, a1
-; ZVFBFA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
; ZVFBFA-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; ZVFBFA-NEXT: vmset.m v24
+; ZVFBFA-NEXT: vmv8r.v v24, v16
+; ZVFBFA-NEXT: vmv8r.v v16, v8
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: vmset.m v8
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
; ZVFBFA-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFBFA-NEXT: vslidedown.vx v0, v24, a2
+; ZVFBFA-NEXT: vslidedown.vx v8, v8, a2
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 4
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; ZVFBFA-NEXT: sltu a2, a0, a3
; ZVFBFA-NEXT: addi a2, a2, -1
; ZVFBFA-NEXT: and a2, a2, a3
+; ZVFBFA-NEXT: csrr a3, vlenb
+; ZVFBFA-NEXT: slli a3, a3, 4
+; ZVFBFA-NEXT: add a3, sp, a3
+; ZVFBFA-NEXT: addi a3, a3, 16
+; ZVFBFA-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFBFA-NEXT: addi a3, sp, 16
-; ZVFBFA-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFBFA-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFBFA-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 4
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 3
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 4
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFBFA-NEXT: vfadd.vv v16, v16, v24, v0.t
+; ZVFBFA-NEXT: vfadd.vv v24, v24, v8, v0.t
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 4
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFBFA-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFBFA-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFBFA-NEXT: bltu a0, a1, .LBB49_2
; ZVFBFA-NEXT: # %bb.1:
; ZVFBFA-NEXT: mv a0, a1
; ZVFBFA-NEXT: .LBB49_2:
; ZVFBFA-NEXT: addi a1, sp, 16
-; ZVFBFA-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFBFA-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFBFA-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v24
-; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v8
+; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFBFA-NEXT: csrr a0, vlenb
+; ZVFBFA-NEXT: slli a0, a0, 3
+; ZVFBFA-NEXT: add a0, sp, a0
+; ZVFBFA-NEXT: addi a0, a0, 16
+; ZVFBFA-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v0
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFBFA-NEXT: vfadd.vv v16, v24, v16
+; ZVFBFA-NEXT: vfadd.vv v16, v16, v24
; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFBFA-NEXT: vfncvt.f.f.w v8, v16
; ZVFBFA-NEXT: csrr a0, vlenb
-; ZVFBFA-NEXT: slli a0, a0, 3
+; ZVFBFA-NEXT: slli a1, a0, 4
+; ZVFBFA-NEXT: add a0, a1, a0
; ZVFBFA-NEXT: add sp, sp, a0
; ZVFBFA-NEXT: .cfi_def_cfa sp, 16
; ZVFBFA-NEXT: addi sp, sp, 16
@@ -2561,16 +3097,16 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: sub sp, sp, a1
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: vmv.v.x v24, a1
+; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v16, a1
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
+; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
@@ -2578,12 +3114,13 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfadd.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB50_2
@@ -2595,6 +3132,7 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v8, v7
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
@@ -2623,16 +3161,16 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFBFA-NEXT: slli a1, a1, 4
; ZVFBFA-NEXT: sub sp, sp, a1
; ZVFBFA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; ZVFBFA-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFBFA-NEXT: vmv1r.v v7, v0
; ZVFBFA-NEXT: fmv.x.w a1, fa0
; ZVFBFA-NEXT: csrr a2, vlenb
-; ZVFBFA-NEXT: vmv.v.x v24, a1
+; ZVFBFA-NEXT: vsetvli a3, zero, e16, m8, ta, ma
+; ZVFBFA-NEXT: vmv.v.x v16, a1
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
+; ZVFBFA-NEXT: vmv1r.v v7, v0
; ZVFBFA-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFBFA-NEXT: vslidedown.vx v0, v0, a2
+; ZVFBFA-NEXT: vslidedown.vx v6, v0, a2
; ZVFBFA-NEXT: sltu a2, a0, a3
; ZVFBFA-NEXT: addi a2, a2, -1
; ZVFBFA-NEXT: and a2, a2, a3
@@ -2640,12 +3178,13 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFBFA-NEXT: slli a3, a3, 3
; ZVFBFA-NEXT: add a3, sp, a3
; ZVFBFA-NEXT: addi a3, a3, 16
-; ZVFBFA-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vmv1r.v v0, v6
; ZVFBFA-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v28, v0.t
-; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFBFA-NEXT: vfadd.vv v16, v24, v16, v0.t
+; ZVFBFA-NEXT: vfadd.vv v16, v16, v24, v0.t
; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFBFA-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFBFA-NEXT: bltu a0, a1, .LBB50_2
@@ -2657,6 +3196,7 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFBFA-NEXT: addi a0, sp, 16
; ZVFBFA-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vmv1r.v v8, v7
; ZVFBFA-NEXT: csrr a0, vlenb
; ZVFBFA-NEXT: slli a0, a0, 3
; ZVFBFA-NEXT: add a0, sp, a0
@@ -2694,37 +3234,78 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a2, a1, 4
+; ZVFHMIN-NEXT: add a1, a2, a1
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmset.m v24
-; ZVFHMIN-NEXT: vmv.v.x v16, a1
+; ZVFHMIN-NEXT: vmset.m v16
+; ZVFHMIN-NEXT: vmv.v.x v8, a1
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2
+; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v16, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfadd.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB51_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB51_2:
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0
@@ -2733,7 +3314,8 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -2745,37 +3327,78 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFBFA-NEXT: addi sp, sp, -16
; ZVFBFA-NEXT: .cfi_def_cfa_offset 16
; ZVFBFA-NEXT: csrr a1, vlenb
-; ZVFBFA-NEXT: slli a1, a1, 3
+; ZVFBFA-NEXT: slli a2, a1, 4
+; ZVFBFA-NEXT: add a1, a2, a1
; ZVFBFA-NEXT: sub sp, sp, a1
-; ZVFBFA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFBFA-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
+; ZVFBFA-NEXT: csrr a1, vlenb
+; ZVFBFA-NEXT: slli a1, a1, 3
+; ZVFBFA-NEXT: add a1, sp, a1
+; ZVFBFA-NEXT: addi a1, a1, 16
+; ZVFBFA-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; ZVFBFA-NEXT: fmv.x.w a1, fa0
; ZVFBFA-NEXT: csrr a2, vlenb
; ZVFBFA-NEXT: vsetvli a3, zero, e16, m8, ta, ma
-; ZVFBFA-NEXT: vmset.m v24
-; ZVFBFA-NEXT: vmv.v.x v16, a1
+; ZVFBFA-NEXT: vmset.m v16
+; ZVFBFA-NEXT: vmv.v.x v8, a1
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
; ZVFBFA-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFBFA-NEXT: vslidedown.vx v0, v24, a2
+; ZVFBFA-NEXT: vslidedown.vx v16, v16, a2
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 4
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vs1r.v v16, (a2) # vscale x 8-byte Folded Spill
; ZVFBFA-NEXT: sltu a2, a0, a3
; ZVFBFA-NEXT: addi a2, a2, -1
; ZVFBFA-NEXT: and a2, a2, a3
+; ZVFBFA-NEXT: csrr a3, vlenb
+; ZVFBFA-NEXT: slli a3, a3, 4
+; ZVFBFA-NEXT: add a3, sp, a3
+; ZVFBFA-NEXT: addi a3, a3, 16
+; ZVFBFA-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFBFA-NEXT: addi a3, sp, 16
-; ZVFBFA-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVFBFA-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 4
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 3
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 4
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFA-NEXT: vfadd.vv v16, v16, v24, v0.t
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 4
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFBFA-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFBFA-NEXT: bltu a0, a1, .LBB51_2
; ZVFBFA-NEXT: # %bb.1:
; ZVFBFA-NEXT: mv a0, a1
; ZVFBFA-NEXT: .LBB51_2:
+; ZVFBFA-NEXT: csrr a1, vlenb
+; ZVFBFA-NEXT: slli a1, a1, 3
+; ZVFBFA-NEXT: add a1, sp, a1
+; ZVFBFA-NEXT: addi a1, a1, 16
+; ZVFBFA-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; ZVFBFA-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v24
; ZVFBFA-NEXT: addi a0, sp, 16
; ZVFBFA-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v0
@@ -2784,7 +3407,8 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFBFA-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFBFA-NEXT: vfncvt.f.f.w v8, v16
; ZVFBFA-NEXT: csrr a0, vlenb
-; ZVFBFA-NEXT: slli a0, a0, 3
+; ZVFBFA-NEXT: slli a1, a0, 4
+; ZVFBFA-NEXT: add a0, a1, a0
; ZVFBFA-NEXT: add sp, sp, a0
; ZVFBFA-NEXT: .cfi_def_cfa sp, 16
; ZVFBFA-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcmp-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfcmp-constrained-sdnode.ll
index 1981c78398b06..4283c12c23286 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfcmp-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfcmp-constrained-sdnode.ll
@@ -56,8 +56,8 @@ define <vscale x 1 x i1> @fcmp_ogt_vf_nxv1f16(<vscale x 1 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -72,8 +72,8 @@ define <vscale x 1 x i1> @fcmp_ogt_fv_nxv1f16(<vscale x 1 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -101,8 +101,8 @@ define <vscale x 1 x i1> @fcmp_oge_vf_nxv1f16(<vscale x 1 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -117,8 +117,8 @@ define <vscale x 1 x i1> @fcmp_oge_fv_nxv1f16(<vscale x 1 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -146,8 +146,8 @@ define <vscale x 1 x i1> @fcmp_olt_vf_nxv1f16(<vscale x 1 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -162,8 +162,8 @@ define <vscale x 1 x i1> @fcmp_olt_fv_nxv1f16(<vscale x 1 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -191,8 +191,8 @@ define <vscale x 1 x i1> @fcmp_ole_vf_nxv1f16(<vscale x 1 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -207,8 +207,8 @@ define <vscale x 1 x i1> @fcmp_ole_fv_nxv1f16(<vscale x 1 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -387,8 +387,8 @@ define <vscale x 1 x i1> @fcmp_ugt_vf_nxv1f16(<vscale x 1 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -404,8 +404,8 @@ define <vscale x 1 x i1> @fcmp_ugt_fv_nxv1f16(<vscale x 1 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -435,8 +435,8 @@ define <vscale x 1 x i1> @fcmp_uge_vf_nxv1f16(<vscale x 1 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -452,8 +452,8 @@ define <vscale x 1 x i1> @fcmp_uge_fv_nxv1f16(<vscale x 1 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -483,8 +483,8 @@ define <vscale x 1 x i1> @fcmp_ult_vf_nxv1f16(<vscale x 1 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -500,8 +500,8 @@ define <vscale x 1 x i1> @fcmp_ult_fv_nxv1f16(<vscale x 1 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -531,8 +531,8 @@ define <vscale x 1 x i1> @fcmp_ule_vf_nxv1f16(<vscale x 1 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -548,8 +548,8 @@ define <vscale x 1 x i1> @fcmp_ule_fv_nxv1f16(<vscale x 1 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -688,8 +688,8 @@ define <vscale x 2 x i1> @fcmp_ogt_vf_nxv2f16(<vscale x 2 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -704,8 +704,8 @@ define <vscale x 2 x i1> @fcmp_ogt_fv_nxv2f16(<vscale x 2 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -733,8 +733,8 @@ define <vscale x 2 x i1> @fcmp_oge_vf_nxv2f16(<vscale x 2 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -749,8 +749,8 @@ define <vscale x 2 x i1> @fcmp_oge_fv_nxv2f16(<vscale x 2 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -778,8 +778,8 @@ define <vscale x 2 x i1> @fcmp_olt_vf_nxv2f16(<vscale x 2 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -794,8 +794,8 @@ define <vscale x 2 x i1> @fcmp_olt_fv_nxv2f16(<vscale x 2 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -823,8 +823,8 @@ define <vscale x 2 x i1> @fcmp_ole_vf_nxv2f16(<vscale x 2 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -839,8 +839,8 @@ define <vscale x 2 x i1> @fcmp_ole_fv_nxv2f16(<vscale x 2 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1019,8 +1019,8 @@ define <vscale x 2 x i1> @fcmp_ugt_vf_nxv2f16(<vscale x 2 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1036,8 +1036,8 @@ define <vscale x 2 x i1> @fcmp_ugt_fv_nxv2f16(<vscale x 2 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1067,8 +1067,8 @@ define <vscale x 2 x i1> @fcmp_uge_vf_nxv2f16(<vscale x 2 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1084,8 +1084,8 @@ define <vscale x 2 x i1> @fcmp_uge_fv_nxv2f16(<vscale x 2 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1115,8 +1115,8 @@ define <vscale x 2 x i1> @fcmp_ult_vf_nxv2f16(<vscale x 2 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1132,8 +1132,8 @@ define <vscale x 2 x i1> @fcmp_ult_fv_nxv2f16(<vscale x 2 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1163,8 +1163,8 @@ define <vscale x 2 x i1> @fcmp_ule_vf_nxv2f16(<vscale x 2 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1180,8 +1180,8 @@ define <vscale x 2 x i1> @fcmp_ule_fv_nxv2f16(<vscale x 2 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1320,8 +1320,8 @@ define <vscale x 4 x i1> @fcmp_ogt_vf_nxv4f16(<vscale x 4 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1336,8 +1336,8 @@ define <vscale x 4 x i1> @fcmp_ogt_fv_nxv4f16(<vscale x 4 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1365,8 +1365,8 @@ define <vscale x 4 x i1> @fcmp_oge_vf_nxv4f16(<vscale x 4 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1381,8 +1381,8 @@ define <vscale x 4 x i1> @fcmp_oge_fv_nxv4f16(<vscale x 4 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1410,8 +1410,8 @@ define <vscale x 4 x i1> @fcmp_olt_vf_nxv4f16(<vscale x 4 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1426,8 +1426,8 @@ define <vscale x 4 x i1> @fcmp_olt_fv_nxv4f16(<vscale x 4 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1455,8 +1455,8 @@ define <vscale x 4 x i1> @fcmp_ole_vf_nxv4f16(<vscale x 4 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1471,8 +1471,8 @@ define <vscale x 4 x i1> @fcmp_ole_fv_nxv4f16(<vscale x 4 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -1651,8 +1651,8 @@ define <vscale x 4 x i1> @fcmp_ugt_vf_nxv4f16(<vscale x 4 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1668,8 +1668,8 @@ define <vscale x 4 x i1> @fcmp_ugt_fv_nxv4f16(<vscale x 4 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1699,8 +1699,8 @@ define <vscale x 4 x i1> @fcmp_uge_vf_nxv4f16(<vscale x 4 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1716,8 +1716,8 @@ define <vscale x 4 x i1> @fcmp_uge_fv_nxv4f16(<vscale x 4 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1747,8 +1747,8 @@ define <vscale x 4 x i1> @fcmp_ult_vf_nxv4f16(<vscale x 4 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1764,8 +1764,8 @@ define <vscale x 4 x i1> @fcmp_ult_fv_nxv4f16(<vscale x 4 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1795,8 +1795,8 @@ define <vscale x 4 x i1> @fcmp_ule_vf_nxv4f16(<vscale x 4 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -1812,8 +1812,8 @@ define <vscale x 4 x i1> @fcmp_ule_fv_nxv4f16(<vscale x 4 x half> %va, half %b)
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -2145,8 +2145,8 @@ define <vscale x 8 x i1> @fcmp_one_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-NEXT: vmfeq.vv v12, v10, v10
; CHECK-NEXT: vmfeq.vv v13, v8, v8
; CHECK-NEXT: vmand.mm v12, v13, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vv v13, v8, v10, v0.t
; CHECK-NEXT: vmflt.vv v12, v10, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v13
@@ -2163,8 +2163,8 @@ define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v12, v13
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v10, v11
@@ -2183,8 +2183,8 @@ define <vscale x 8 x i1> @fcmp_one_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v13, v12
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v10, v11
@@ -2244,8 +2244,8 @@ define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; CHECK-NEXT: vmfeq.vv v12, v10, v10
; CHECK-NEXT: vmfeq.vv v13, v8, v8
; CHECK-NEXT: vmand.mm v12, v13, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vv v13, v8, v10, v0.t
; CHECK-NEXT: vmflt.vv v12, v10, v8, v0.t
; CHECK-NEXT: vmnor.mm v0, v12, v13
@@ -2262,8 +2262,8 @@ define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v12, v13
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v10, v11
@@ -2282,8 +2282,8 @@ define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v13, v12
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v10, v11
@@ -2819,8 +2819,8 @@ define <vscale x 16 x i1> @fcmp_one_vv_nxv16f16(<vscale x 16 x half> %va, <vscal
; CHECK-NEXT: vmfeq.vv v16, v12, v12
; CHECK-NEXT: vmfeq.vv v17, v8, v8
; CHECK-NEXT: vmand.mm v16, v17, v16
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vv v17, v8, v12, v0.t
; CHECK-NEXT: vmflt.vv v16, v12, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v16, v17
@@ -2837,8 +2837,8 @@ define <vscale x 16 x i1> @fcmp_one_vf_nxv16f16(<vscale x 16 x half> %va, half %
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v12, v16
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v13
@@ -2857,8 +2857,8 @@ define <vscale x 16 x i1> @fcmp_one_fv_nxv16f16(<vscale x 16 x half> %va, half %
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v16, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v13
@@ -2918,8 +2918,8 @@ define <vscale x 16 x i1> @fcmp_ueq_vv_nxv16f16(<vscale x 16 x half> %va, <vscal
; CHECK-NEXT: vmfeq.vv v16, v12, v12
; CHECK-NEXT: vmfeq.vv v17, v8, v8
; CHECK-NEXT: vmand.mm v16, v17, v16
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vv v17, v8, v12, v0.t
; CHECK-NEXT: vmflt.vv v16, v12, v8, v0.t
; CHECK-NEXT: vmnor.mm v0, v16, v17
@@ -2936,8 +2936,8 @@ define <vscale x 16 x i1> @fcmp_ueq_vf_nxv16f16(<vscale x 16 x half> %va, half %
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v12, v16
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v12, v13
@@ -2956,8 +2956,8 @@ define <vscale x 16 x i1> @fcmp_ueq_fv_nxv16f16(<vscale x 16 x half> %va, half %
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v16, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v12, v13
@@ -3493,8 +3493,8 @@ define <vscale x 32 x i1> @fcmp_one_vv_nxv32f16(<vscale x 32 x half> %va, <vscal
; CHECK-NEXT: vmfeq.vv v24, v16, v16
; CHECK-NEXT: vmfeq.vv v25, v8, v8
; CHECK-NEXT: vmand.mm v24, v25, v24
-; CHECK-NEXT: vmv1r.v v25, v24
; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v25, v24
; CHECK-NEXT: vmflt.vv v25, v8, v16, v0.t
; CHECK-NEXT: vmflt.vv v24, v16, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v24, v25
@@ -3511,8 +3511,8 @@ define <vscale x 32 x i1> @fcmp_one_vf_nxv32f16(<vscale x 32 x half> %va, half %
; CHECK-NEXT: vmfeq.vf v24, v16, fa0
; CHECK-NEXT: vmfeq.vv v16, v8, v8
; CHECK-NEXT: vmand.mm v16, v16, v24
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vf v17, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v16, v17
@@ -3531,8 +3531,8 @@ define <vscale x 32 x i1> @fcmp_one_fv_nxv32f16(<vscale x 32 x half> %va, half %
; CHECK-NEXT: vmfeq.vf v24, v16, fa0
; CHECK-NEXT: vmfeq.vv v16, v8, v8
; CHECK-NEXT: vmand.mm v16, v24, v16
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmfgt.vf v17, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v16, v17
@@ -3592,8 +3592,8 @@ define <vscale x 32 x i1> @fcmp_ueq_vv_nxv32f16(<vscale x 32 x half> %va, <vscal
; CHECK-NEXT: vmfeq.vv v24, v16, v16
; CHECK-NEXT: vmfeq.vv v25, v8, v8
; CHECK-NEXT: vmand.mm v24, v25, v24
-; CHECK-NEXT: vmv1r.v v25, v24
; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v25, v24
; CHECK-NEXT: vmflt.vv v25, v8, v16, v0.t
; CHECK-NEXT: vmflt.vv v24, v16, v8, v0.t
; CHECK-NEXT: vmnor.mm v0, v24, v25
@@ -3610,8 +3610,8 @@ define <vscale x 32 x i1> @fcmp_ueq_vf_nxv32f16(<vscale x 32 x half> %va, half %
; CHECK-NEXT: vmfeq.vf v24, v16, fa0
; CHECK-NEXT: vmfeq.vv v16, v8, v8
; CHECK-NEXT: vmand.mm v16, v16, v24
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vf v17, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v16, v17
@@ -3630,8 +3630,8 @@ define <vscale x 32 x i1> @fcmp_ueq_fv_nxv32f16(<vscale x 32 x half> %va, half %
; CHECK-NEXT: vmfeq.vf v24, v16, fa0
; CHECK-NEXT: vmfeq.vv v16, v8, v8
; CHECK-NEXT: vmand.mm v16, v24, v16
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmfgt.vf v17, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v16, v17
@@ -3974,8 +3974,8 @@ define <vscale x 1 x i1> @fcmp_ogt_vf_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -3990,8 +3990,8 @@ define <vscale x 1 x i1> @fcmp_ogt_fv_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4019,8 +4019,8 @@ define <vscale x 1 x i1> @fcmp_oge_vf_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4035,8 +4035,8 @@ define <vscale x 1 x i1> @fcmp_oge_fv_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4064,8 +4064,8 @@ define <vscale x 1 x i1> @fcmp_olt_vf_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4080,8 +4080,8 @@ define <vscale x 1 x i1> @fcmp_olt_fv_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4109,8 +4109,8 @@ define <vscale x 1 x i1> @fcmp_ole_vf_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4125,8 +4125,8 @@ define <vscale x 1 x i1> @fcmp_ole_fv_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4305,8 +4305,8 @@ define <vscale x 1 x i1> @fcmp_ugt_vf_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4322,8 +4322,8 @@ define <vscale x 1 x i1> @fcmp_ugt_fv_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4353,8 +4353,8 @@ define <vscale x 1 x i1> @fcmp_uge_vf_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4370,8 +4370,8 @@ define <vscale x 1 x i1> @fcmp_uge_fv_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4401,8 +4401,8 @@ define <vscale x 1 x i1> @fcmp_ult_vf_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4418,8 +4418,8 @@ define <vscale x 1 x i1> @fcmp_ult_fv_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4449,8 +4449,8 @@ define <vscale x 1 x i1> @fcmp_ule_vf_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4466,8 +4466,8 @@ define <vscale x 1 x i1> @fcmp_ule_fv_nxv1f32(<vscale x 1 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4606,8 +4606,8 @@ define <vscale x 2 x i1> @fcmp_ogt_vf_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4622,8 +4622,8 @@ define <vscale x 2 x i1> @fcmp_ogt_fv_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4651,8 +4651,8 @@ define <vscale x 2 x i1> @fcmp_oge_vf_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4667,8 +4667,8 @@ define <vscale x 2 x i1> @fcmp_oge_fv_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4696,8 +4696,8 @@ define <vscale x 2 x i1> @fcmp_olt_vf_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4712,8 +4712,8 @@ define <vscale x 2 x i1> @fcmp_olt_fv_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4741,8 +4741,8 @@ define <vscale x 2 x i1> @fcmp_ole_vf_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4757,8 +4757,8 @@ define <vscale x 2 x i1> @fcmp_ole_fv_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -4937,8 +4937,8 @@ define <vscale x 2 x i1> @fcmp_ugt_vf_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4954,8 +4954,8 @@ define <vscale x 2 x i1> @fcmp_ugt_fv_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -4985,8 +4985,8 @@ define <vscale x 2 x i1> @fcmp_uge_vf_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5002,8 +5002,8 @@ define <vscale x 2 x i1> @fcmp_uge_fv_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5033,8 +5033,8 @@ define <vscale x 2 x i1> @fcmp_ult_vf_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5050,8 +5050,8 @@ define <vscale x 2 x i1> @fcmp_ult_fv_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5081,8 +5081,8 @@ define <vscale x 2 x i1> @fcmp_ule_vf_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5098,8 +5098,8 @@ define <vscale x 2 x i1> @fcmp_ule_fv_nxv2f32(<vscale x 2 x float> %va, float %b
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -5431,8 +5431,8 @@ define <vscale x 4 x i1> @fcmp_one_vv_nxv4f32(<vscale x 4 x float> %va, <vscale
; CHECK-NEXT: vmfeq.vv v12, v10, v10
; CHECK-NEXT: vmfeq.vv v13, v8, v8
; CHECK-NEXT: vmand.mm v12, v13, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vv v13, v8, v10, v0.t
; CHECK-NEXT: vmflt.vv v12, v10, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v13
@@ -5449,8 +5449,8 @@ define <vscale x 4 x i1> @fcmp_one_vf_nxv4f32(<vscale x 4 x float> %va, float %b
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v12, v13
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v10, v11
@@ -5469,8 +5469,8 @@ define <vscale x 4 x i1> @fcmp_one_fv_nxv4f32(<vscale x 4 x float> %va, float %b
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v13, v12
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v10, v11
@@ -5530,8 +5530,8 @@ define <vscale x 4 x i1> @fcmp_ueq_vv_nxv4f32(<vscale x 4 x float> %va, <vscale
; CHECK-NEXT: vmfeq.vv v12, v10, v10
; CHECK-NEXT: vmfeq.vv v13, v8, v8
; CHECK-NEXT: vmand.mm v12, v13, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vv v13, v8, v10, v0.t
; CHECK-NEXT: vmflt.vv v12, v10, v8, v0.t
; CHECK-NEXT: vmnor.mm v0, v12, v13
@@ -5548,8 +5548,8 @@ define <vscale x 4 x i1> @fcmp_ueq_vf_nxv4f32(<vscale x 4 x float> %va, float %b
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v12, v13
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v10, v11
@@ -5568,8 +5568,8 @@ define <vscale x 4 x i1> @fcmp_ueq_fv_nxv4f32(<vscale x 4 x float> %va, float %b
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v13, v12
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v10, v11
@@ -6105,8 +6105,8 @@ define <vscale x 8 x i1> @fcmp_one_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-NEXT: vmfeq.vv v16, v12, v12
; CHECK-NEXT: vmfeq.vv v17, v8, v8
; CHECK-NEXT: vmand.mm v16, v17, v16
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vv v17, v8, v12, v0.t
; CHECK-NEXT: vmflt.vv v16, v12, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v16, v17
@@ -6123,8 +6123,8 @@ define <vscale x 8 x i1> @fcmp_one_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v12, v16
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v13
@@ -6143,8 +6143,8 @@ define <vscale x 8 x i1> @fcmp_one_fv_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v16, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v13
@@ -6204,8 +6204,8 @@ define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f32(<vscale x 8 x float> %va, <vscale
; CHECK-NEXT: vmfeq.vv v16, v12, v12
; CHECK-NEXT: vmfeq.vv v17, v8, v8
; CHECK-NEXT: vmand.mm v16, v17, v16
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vv v17, v8, v12, v0.t
; CHECK-NEXT: vmflt.vv v16, v12, v8, v0.t
; CHECK-NEXT: vmnor.mm v0, v16, v17
@@ -6222,8 +6222,8 @@ define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v12, v16
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v12, v13
@@ -6242,8 +6242,8 @@ define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f32(<vscale x 8 x float> %va, float %b
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v16, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v12, v13
@@ -6779,8 +6779,8 @@ define <vscale x 16 x i1> @fcmp_one_vv_nxv16f32(<vscale x 16 x float> %va, <vsca
; CHECK-NEXT: vmfeq.vv v24, v16, v16
; CHECK-NEXT: vmfeq.vv v25, v8, v8
; CHECK-NEXT: vmand.mm v24, v25, v24
-; CHECK-NEXT: vmv1r.v v25, v24
; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v25, v24
; CHECK-NEXT: vmflt.vv v25, v8, v16, v0.t
; CHECK-NEXT: vmflt.vv v24, v16, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v24, v25
@@ -6797,8 +6797,8 @@ define <vscale x 16 x i1> @fcmp_one_vf_nxv16f32(<vscale x 16 x float> %va, float
; CHECK-NEXT: vmfeq.vf v24, v16, fa0
; CHECK-NEXT: vmfeq.vv v16, v8, v8
; CHECK-NEXT: vmand.mm v16, v16, v24
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vf v17, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v16, v17
@@ -6817,8 +6817,8 @@ define <vscale x 16 x i1> @fcmp_one_fv_nxv16f32(<vscale x 16 x float> %va, float
; CHECK-NEXT: vmfeq.vf v24, v16, fa0
; CHECK-NEXT: vmfeq.vv v16, v8, v8
; CHECK-NEXT: vmand.mm v16, v24, v16
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmfgt.vf v17, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v16, v17
@@ -6878,8 +6878,8 @@ define <vscale x 16 x i1> @fcmp_ueq_vv_nxv16f32(<vscale x 16 x float> %va, <vsca
; CHECK-NEXT: vmfeq.vv v24, v16, v16
; CHECK-NEXT: vmfeq.vv v25, v8, v8
; CHECK-NEXT: vmand.mm v24, v25, v24
-; CHECK-NEXT: vmv1r.v v25, v24
; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v25, v24
; CHECK-NEXT: vmflt.vv v25, v8, v16, v0.t
; CHECK-NEXT: vmflt.vv v24, v16, v8, v0.t
; CHECK-NEXT: vmnor.mm v0, v24, v25
@@ -6896,8 +6896,8 @@ define <vscale x 16 x i1> @fcmp_ueq_vf_nxv16f32(<vscale x 16 x float> %va, float
; CHECK-NEXT: vmfeq.vf v24, v16, fa0
; CHECK-NEXT: vmfeq.vv v16, v8, v8
; CHECK-NEXT: vmand.mm v16, v16, v24
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vf v17, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v16, v17
@@ -6916,8 +6916,8 @@ define <vscale x 16 x i1> @fcmp_ueq_fv_nxv16f32(<vscale x 16 x float> %va, float
; CHECK-NEXT: vmfeq.vf v24, v16, fa0
; CHECK-NEXT: vmfeq.vv v16, v8, v8
; CHECK-NEXT: vmand.mm v16, v24, v16
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmfgt.vf v17, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v16, v17
@@ -7260,8 +7260,8 @@ define <vscale x 1 x i1> @fcmp_ogt_vf_nxv1f64(<vscale x 1 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7276,8 +7276,8 @@ define <vscale x 1 x i1> @fcmp_ogt_fv_nxv1f64(<vscale x 1 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7305,8 +7305,8 @@ define <vscale x 1 x i1> @fcmp_oge_vf_nxv1f64(<vscale x 1 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7321,8 +7321,8 @@ define <vscale x 1 x i1> @fcmp_oge_fv_nxv1f64(<vscale x 1 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7350,8 +7350,8 @@ define <vscale x 1 x i1> @fcmp_olt_vf_nxv1f64(<vscale x 1 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7366,8 +7366,8 @@ define <vscale x 1 x i1> @fcmp_olt_fv_nxv1f64(<vscale x 1 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7395,8 +7395,8 @@ define <vscale x 1 x i1> @fcmp_ole_vf_nxv1f64(<vscale x 1 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7411,8 +7411,8 @@ define <vscale x 1 x i1> @fcmp_ole_fv_nxv1f64(<vscale x 1 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: ret
@@ -7591,8 +7591,8 @@ define <vscale x 1 x i1> @fcmp_ugt_vf_nxv1f64(<vscale x 1 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -7608,8 +7608,8 @@ define <vscale x 1 x i1> @fcmp_ugt_fv_nxv1f64(<vscale x 1 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -7639,8 +7639,8 @@ define <vscale x 1 x i1> @fcmp_uge_vf_nxv1f64(<vscale x 1 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -7656,8 +7656,8 @@ define <vscale x 1 x i1> @fcmp_uge_fv_nxv1f64(<vscale x 1 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -7687,8 +7687,8 @@ define <vscale x 1 x i1> @fcmp_ult_vf_nxv1f64(<vscale x 1 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -7704,8 +7704,8 @@ define <vscale x 1 x i1> @fcmp_ult_fv_nxv1f64(<vscale x 1 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -7735,8 +7735,8 @@ define <vscale x 1 x i1> @fcmp_ule_vf_nxv1f64(<vscale x 1 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v9, v10
; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -7752,8 +7752,8 @@ define <vscale x 1 x i1> @fcmp_ule_fv_nxv1f64(<vscale x 1 x double> %va, double
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vf v9, v9, fa0
+; CHECK-NEXT: vmfeq.vv v10, v8, v8
; CHECK-NEXT: vmand.mm v0, v10, v9
; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
; CHECK-NEXT: vmnot.m v0, v0
@@ -8085,8 +8085,8 @@ define <vscale x 2 x i1> @fcmp_one_vv_nxv2f64(<vscale x 2 x double> %va, <vscale
; CHECK-NEXT: vmfeq.vv v12, v10, v10
; CHECK-NEXT: vmfeq.vv v13, v8, v8
; CHECK-NEXT: vmand.mm v12, v13, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vv v13, v8, v10, v0.t
; CHECK-NEXT: vmflt.vv v12, v10, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v13
@@ -8103,8 +8103,8 @@ define <vscale x 2 x i1> @fcmp_one_vf_nxv2f64(<vscale x 2 x double> %va, double
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v12, v13
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v10, v11
@@ -8123,8 +8123,8 @@ define <vscale x 2 x i1> @fcmp_one_fv_nxv2f64(<vscale x 2 x double> %va, double
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v13, v12
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v10, v11
@@ -8184,8 +8184,8 @@ define <vscale x 2 x i1> @fcmp_ueq_vv_nxv2f64(<vscale x 2 x double> %va, <vscale
; CHECK-NEXT: vmfeq.vv v12, v10, v10
; CHECK-NEXT: vmfeq.vv v13, v8, v8
; CHECK-NEXT: vmand.mm v12, v13, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vv v13, v8, v10, v0.t
; CHECK-NEXT: vmflt.vv v12, v10, v8, v0.t
; CHECK-NEXT: vmnor.mm v0, v12, v13
@@ -8202,8 +8202,8 @@ define <vscale x 2 x i1> @fcmp_ueq_vf_nxv2f64(<vscale x 2 x double> %va, double
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v12, v13
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v10, v11
@@ -8222,8 +8222,8 @@ define <vscale x 2 x i1> @fcmp_ueq_fv_nxv2f64(<vscale x 2 x double> %va, double
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmfeq.vf v13, v10, fa0
; CHECK-NEXT: vmand.mm v10, v13, v12
-; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v10, v11
@@ -8759,8 +8759,8 @@ define <vscale x 4 x i1> @fcmp_one_vv_nxv4f64(<vscale x 4 x double> %va, <vscale
; CHECK-NEXT: vmfeq.vv v16, v12, v12
; CHECK-NEXT: vmfeq.vv v17, v8, v8
; CHECK-NEXT: vmand.mm v16, v17, v16
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vv v17, v8, v12, v0.t
; CHECK-NEXT: vmflt.vv v16, v12, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v16, v17
@@ -8777,8 +8777,8 @@ define <vscale x 4 x i1> @fcmp_one_vf_nxv4f64(<vscale x 4 x double> %va, double
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v12, v16
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v13
@@ -8797,8 +8797,8 @@ define <vscale x 4 x i1> @fcmp_one_fv_nxv4f64(<vscale x 4 x double> %va, double
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v16, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v13
@@ -8858,8 +8858,8 @@ define <vscale x 4 x i1> @fcmp_ueq_vv_nxv4f64(<vscale x 4 x double> %va, <vscale
; CHECK-NEXT: vmfeq.vv v16, v12, v12
; CHECK-NEXT: vmfeq.vv v17, v8, v8
; CHECK-NEXT: vmand.mm v16, v17, v16
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vv v17, v8, v12, v0.t
; CHECK-NEXT: vmflt.vv v16, v12, v8, v0.t
; CHECK-NEXT: vmnor.mm v0, v16, v17
@@ -8876,8 +8876,8 @@ define <vscale x 4 x i1> @fcmp_ueq_vf_nxv4f64(<vscale x 4 x double> %va, double
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v12, v16
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v12, v13
@@ -8896,8 +8896,8 @@ define <vscale x 4 x i1> @fcmp_ueq_fv_nxv4f64(<vscale x 4 x double> %va, double
; CHECK-NEXT: vmfeq.vf v16, v12, fa0
; CHECK-NEXT: vmfeq.vv v12, v8, v8
; CHECK-NEXT: vmand.mm v12, v16, v12
-; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v12, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v12, v13
@@ -9433,8 +9433,8 @@ define <vscale x 8 x i1> @fcmp_one_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-NEXT: vmfeq.vv v24, v16, v16
; CHECK-NEXT: vmfeq.vv v25, v8, v8
; CHECK-NEXT: vmand.mm v24, v25, v24
-; CHECK-NEXT: vmv1r.v v25, v24
; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v25, v24
; CHECK-NEXT: vmflt.vv v25, v8, v16, v0.t
; CHECK-NEXT: vmflt.vv v24, v16, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v24, v25
@@ -9451,8 +9451,8 @@ define <vscale x 8 x i1> @fcmp_one_vf_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-NEXT: vmfeq.vf v24, v16, fa0
; CHECK-NEXT: vmfeq.vv v16, v8, v8
; CHECK-NEXT: vmand.mm v16, v16, v24
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vf v17, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v16, v17
@@ -9471,8 +9471,8 @@ define <vscale x 8 x i1> @fcmp_one_fv_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-NEXT: vmfeq.vf v24, v16, fa0
; CHECK-NEXT: vmfeq.vv v16, v8, v8
; CHECK-NEXT: vmand.mm v16, v24, v16
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmfgt.vf v17, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vmor.mm v0, v16, v17
@@ -9532,8 +9532,8 @@ define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f64(<vscale x 8 x double> %va, <vscale
; CHECK-NEXT: vmfeq.vv v24, v16, v16
; CHECK-NEXT: vmfeq.vv v25, v8, v8
; CHECK-NEXT: vmand.mm v24, v25, v24
-; CHECK-NEXT: vmv1r.v v25, v24
; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v25, v24
; CHECK-NEXT: vmflt.vv v25, v8, v16, v0.t
; CHECK-NEXT: vmflt.vv v24, v16, v8, v0.t
; CHECK-NEXT: vmnor.mm v0, v24, v25
@@ -9550,8 +9550,8 @@ define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-NEXT: vmfeq.vf v24, v16, fa0
; CHECK-NEXT: vmfeq.vv v16, v8, v8
; CHECK-NEXT: vmand.mm v16, v16, v24
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vf v17, v8, fa0, v0.t
; CHECK-NEXT: vmfgt.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v16, v17
@@ -9570,8 +9570,8 @@ define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f64(<vscale x 8 x double> %va, double
; CHECK-NEXT: vmfeq.vf v24, v16, fa0
; CHECK-NEXT: vmfeq.vv v16, v8, v8
; CHECK-NEXT: vmand.mm v16, v24, v16
-; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmfgt.vf v17, v8, fa0, v0.t
; CHECK-NEXT: vmflt.vf v16, v8, fa0, v0.t
; CHECK-NEXT: vmnor.mm v0, v16, v17
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
index e9d7137919ac9..fb4eca7837738 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
@@ -358,44 +358,86 @@ define <vscale x 32 x bfloat> @vfdiv_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vmv8r.v v24, v16
+; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: csrr a4, vlenb
+; CHECK-NEXT: slli a4, a4, 4
+; CHECK-NEXT: add a4, sp, a4
+; CHECK-NEXT: addi a4, a4, 16
+; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vslidedown.vx v7, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: addi a3, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 4
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfdiv.vv v16, v16, v24, v0.t
+; CHECK-NEXT: vfdiv.vv v24, v24, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB20_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB20_2:
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16, v0.t
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 4
+; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfdiv.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vfdiv.vv v16, v16, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -411,44 +453,83 @@ define <vscale x 32 x bfloat> @vfdiv_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a2, a1, 4
+; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; CHECK-NEXT: vmset.m v24
+; CHECK-NEXT: vmv8r.v v24, v16
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: vmset.m v8
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v24, a2
+; CHECK-NEXT: vslidedown.vx v8, v8, a2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 4
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a3, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfdiv.vv v16, v16, v24, v0.t
+; CHECK-NEXT: vfdiv.vv v24, v24, v8, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB21_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB21_2:
; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfdiv.vv v16, v24, v16
+; CHECK-NEXT: vfdiv.vv v16, v16, v24
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 4
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -467,16 +548,16 @@ define <vscale x 32 x bfloat> @vfdiv_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: fmv.x.h a1, fa0
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: vmv.v.x v24, a1
+; CHECK-NEXT: vsetvli a3, zero, e16, m8, ta, ma
+; CHECK-NEXT: vmv.v.x v16, a1
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: vslidedown.vx v6, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
@@ -484,12 +565,13 @@ define <vscale x 32 x bfloat> @vfdiv_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; CHECK-NEXT: slli a3, a3, 3
; CHECK-NEXT: add a3, sp, a3
; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v28, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfdiv.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vfdiv.vv v16, v16, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB22_2
@@ -501,6 +583,7 @@ define <vscale x 32 x bfloat> @vfdiv_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
@@ -532,37 +615,78 @@ define <vscale x 32 x bfloat> @vfdiv_vf_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a2, a1, 4
+; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: fmv.x.h a1, fa0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: vsetvli a3, zero, e16, m8, ta, ma
-; CHECK-NEXT: vmset.m v24
-; CHECK-NEXT: vmv.v.x v16, a1
+; CHECK-NEXT: vmset.m v16
+; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v24, a2
+; CHECK-NEXT: vslidedown.vx v16, v16, a2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v16, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 4
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a3, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfdiv.vv v16, v16, v24, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB23_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB23_2:
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v0
@@ -571,7 +695,8 @@ define <vscale x 32 x bfloat> @vfdiv_vf_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 4
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -1055,44 +1180,86 @@ define <vscale x 32 x half> @vfdiv_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: mv a2, a1
; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a2, a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 4
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 4
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfdiv.vv v24, v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB44_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB44_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: addi a1, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v8, v0
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfdiv.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -1114,44 +1281,83 @@ define <vscale x 32 x half> @vfdiv_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a2, a1, 4
+; ZVFHMIN-NEXT: add a1, a2, a1
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; ZVFHMIN-NEXT: vmset.m v24
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: vmset.m v8
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfdiv.vv v24, v24, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB45_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB45_2:
; ZVFHMIN-NEXT: addi a1, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfdiv.vv v16, v24, v16
+; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -1176,16 +1382,16 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: sub sp, sp, a1
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: vmv.v.x v24, a1
+; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v16, a1
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
+; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
@@ -1193,12 +1399,13 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfdiv.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB46_2
@@ -1210,6 +1417,7 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v8, v7
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
@@ -1247,37 +1455,78 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a2, a1, 4
+; ZVFHMIN-NEXT: add a1, a2, a1
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmset.m v24
-; ZVFHMIN-NEXT: vmv.v.x v16, a1
+; ZVFHMIN-NEXT: vmset.m v16
+; ZVFHMIN-NEXT: vmv.v.x v8, a1
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2
+; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v16, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfdiv.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB47_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB47_2:
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0
@@ -1286,7 +1535,8 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
index c25a0d47c5c53..48b0bfd21bdba 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
@@ -465,14 +465,14 @@ define <vscale x 16 x bfloat> @vfma_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vmv4r.v v4, v12
-; CHECK-NEXT: vmv4r.v v20, v8
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v4, v0.t
+; CHECK-NEXT: vmv4r.v v24, v8
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v16, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v4, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; CHECK-NEXT: vfmadd.vv v24, v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v24, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 16 x bfloat> @llvm.vp.fma.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %b, <vscale x 16 x bfloat> %c, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x bfloat> %v
@@ -582,11 +582,13 @@ define <vscale x 32 x bfloat> @vfma_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vs
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 5
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a3, a3, a2
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: sub sp, sp, a2
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v3, v0
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: mv a3, a2
@@ -594,13 +596,38 @@ define <vscale x 32 x bfloat> @vfma_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vs
; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a3, a3, a2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: vl8re16.v v16, (a0)
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a0, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a1, a0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: csrr a4, vlenb
+; CHECK-NEXT: slli a4, a4, 3
+; CHECK-NEXT: mv a5, a4
+; CHECK-NEXT: slli a4, a4, 1
+; CHECK-NEXT: add a4, a4, a5
+; CHECK-NEXT: add a4, sp, a4
+; CHECK-NEXT: addi a4, a4, 16
+; CHECK-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vslidedown.vx v8, v8, a2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a4, a2, 5
+; CHECK-NEXT: add a2, a4, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: sltu a2, a1, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
@@ -609,80 +636,118 @@ define <vscale x 32 x bfloat> @vfma_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vs
; CHECK-NEXT: add a3, sp, a3
; CHECK-NEXT: addi a3, a3, 16
; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a4, a3, 5
+; CHECK-NEXT: add a3, a4, a3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v28, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v24, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a3, a3, a2
; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v4, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmadd.vv v8, v16, v24, v0.t
+; CHECK-NEXT: vfmadd.vv v24, v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v4, v8, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: bltu a1, a0, .LBB30_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: .LBB30_2:
-; CHECK-NEXT: vmv1r.v v0, v3
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: mv a2, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a2
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 5
+; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a1, a1, a0
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v24, v0.t
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 5
+; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmadd.vv v8, v16, v24, v0.t
-; CHECK-NEXT: vmv.v.v v16, v8
-; CHECK-NEXT: vmv4r.v v12, v4
+; CHECK-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: slli a0, a0, 2
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -702,40 +767,57 @@ define <vscale x 32 x bfloat> @vfma_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat>
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, ma
+; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: vl8re16.v v16, (a0)
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; CHECK-NEXT: vmset.m v24
+; CHECK-NEXT: vmset.m v8
; CHECK-NEXT: slli a0, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a1, a0
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v24, a2
+; CHECK-NEXT: vslidedown.vx v8, v8, a2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: mv a4, a2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: add a2, a2, a4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: sltu a2, a1, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: addi a3, sp, 16
+; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: mv a4, a3
+; CHECK-NEXT: slli a3, a3, 1
+; CHECK-NEXT: add a3, a3, a4
; CHECK-NEXT: add a3, sp, a3
; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
-; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v28, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: mv a3, a2
@@ -743,33 +825,46 @@ define <vscale x 32 x bfloat> @vfma_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat>
; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl1r.v v24, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v4, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmadd.vv v8, v16, v24, v0.t
+; CHECK-NEXT: vfmadd.vv v24, v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v20, v8, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
; CHECK-NEXT: bltu a1, a0, .LBB31_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: .LBB31_2:
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8
-; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16
+; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v0, v16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: mv a1, a0
@@ -777,15 +872,11 @@ define <vscale x 32 x bfloat> @vfma_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat>
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v0, v8
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmadd.vv v0, v24, v8
+; CHECK-NEXT: vfmadd.vv v0, v24, v16
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v16, v0
-; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add sp, sp, a0
@@ -803,103 +894,204 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bfl
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 5
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v3, v0
-; CHECK-NEXT: vmv8r.v v24, v8
-; CHECK-NEXT: fmv.x.h a2, fa0
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a1, a3, 1
-; CHECK-NEXT: srli a3, a3, 2
-; CHECK-NEXT: sub a4, a0, a1
-; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: sltu a3, a0, a4
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a3, a3, a4
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: slli a4, a4, 3
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
-; CHECK-NEXT: addi a4, sp, 16
-; CHECK-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
+; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 5
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: fmv.x.h a1, fa0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: slli a4, a4, 3
+; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: mv a5, a4
; CHECK-NEXT: slli a4, a4, 1
; CHECK-NEXT: add a4, a4, a5
; CHECK-NEXT: add a4, sp, a4
; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v28, v0.t
-; CHECK-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; CHECK-NEXT: vmv.v.x v8, a2
+; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: mv a4, a2
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: add a2, a2, a4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: mv a4, a3
+; CHECK-NEXT: slli a3, a3, 1
+; CHECK-NEXT: add a3, a3, a4
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 5
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmadd.vv v24, v16, v8, v0.t
-; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v4, v24, v0.t
-; CHECK-NEXT: bltu a0, a1, .LBB32_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a1
-; CHECK-NEXT: .LBB32_2:
-; CHECK-NEXT: vmv1r.v v0, v3
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; CHECK-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; CHECK-NEXT: vfncvtbf16.f.f.w v4, v24, v0.t
+; CHECK-NEXT: bltu a0, a1, .LBB32_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: mv a0, a1
+; CHECK-NEXT: .LBB32_2:
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16, v0.t
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16, v0.t
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: slli a0, a0, 2
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v24, v0.t
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; CHECK-NEXT: vfmadd.vv v16, v24, v8, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmadd.vv v8, v16, v24, v0.t
-; CHECK-NEXT: vmv.v.v v16, v8
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vmv4r.v v12, v4
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -917,11 +1109,18 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_commute(<vscale x 32 x bfloat>
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 5
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v3, v0
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 5
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: mv a2, a1
@@ -932,12 +1131,24 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_commute(<vscale x 32 x bfloat>
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: fmv.x.h a1, fa0
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: vsetvli a3, zero, e16, m8, ta, ma
+; CHECK-NEXT: vmv.v.x v24, a1
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: csrr a4, vlenb
+; CHECK-NEXT: slli a4, a4, 5
+; CHECK-NEXT: add a4, sp, a4
+; CHECK-NEXT: addi a4, a4, 16
+; CHECK-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: vslidedown.vx v8, v8, a2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a4, a2, 5
+; CHECK-NEXT: add a2, a4, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
@@ -946,16 +1157,34 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_commute(<vscale x 32 x bfloat>
; CHECK-NEXT: add a3, sp, a3
; CHECK-NEXT: addi a3, a3, 16
; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a4, a3, 5
+; CHECK-NEXT: add a3, a4, a3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v28, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: mv a3, a2
@@ -963,43 +1192,50 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_commute(<vscale x 32 x bfloat>
; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
+; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmadd.vv v8, v16, v24, v0.t
+; CHECK-NEXT: vfmadd.vv v24, v16, v8, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v4, v8, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: bltu a0, a1, .LBB33_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB33_2:
-; CHECK-NEXT: vmv1r.v v0, v3
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 5
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 5
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t
+; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: mv a1, a0
@@ -1007,24 +1243,33 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_commute(<vscale x 32 x bfloat>
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 5
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmadd.vv v16, v24, v8, v0.t
-; CHECK-NEXT: vmv4r.v v12, v4
+; CHECK-NEXT: vfmadd.vv v8, v16, v24, v0.t
+; CHECK-NEXT: vmv.v.v v16, v8
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: slli a0, a0, 2
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -1048,61 +1293,73 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_unmasked(<vscale x 32 x bfloat>
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
-; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; CHECK-NEXT: vmv8r.v v24, v8
-; CHECK-NEXT: fmv.x.h a2, fa0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: fmv.x.h a1, fa0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: vsetvli a3, zero, e16, m8, ta, ma
+; CHECK-NEXT: vmset.m v7
+; CHECK-NEXT: vmv.v.x v8, a1
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v7, v7, a2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 5
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v7, (a2) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: vmset.m v8
-; CHECK-NEXT: slli a1, a3, 1
-; CHECK-NEXT: srli a3, a3, 2
-; CHECK-NEXT: sub a4, a0, a1
-; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a3
-; CHECK-NEXT: sltu a3, a0, a4
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a3, a3, a4
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: slli a4, a4, 5
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: slli a4, a4, 4
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: slli a4, a4, 3
-; CHECK-NEXT: mv a5, a4
-; CHECK-NEXT: slli a4, a4, 1
-; CHECK-NEXT: add a4, a4, a5
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: slli a4, a4, 3
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; CHECK-NEXT: vmv.v.x v8, a2
+; CHECK-NEXT: slli a3, a3, 4
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 5
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: slli a2, a2, 5
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v28, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 5
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfmadd.vv v24, v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -1112,14 +1369,14 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_unmasked(<vscale x 32 x bfloat>
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 5
+; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
@@ -1130,20 +1387,23 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_unmasked(<vscale x 32 x bfloat>
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v0, v24
-; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v0, v16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmadd.vv v24, v0, v16
+; CHECK-NEXT: vfmadd.vv v0, v24, v16
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v24
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: mv a1, a0
@@ -1166,9 +1426,12 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_unmasked_commute(<vscale x 32 x
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 5
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: mv a2, a1
@@ -1186,7 +1449,12 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_unmasked_commute(<vscale x 32 x
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a2
+; CHECK-NEXT: vslidedown.vx v8, v8, a2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 5
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
@@ -1195,6 +1463,11 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_unmasked_commute(<vscale x 32 x
; CHECK-NEXT: add a3, sp, a3
; CHECK-NEXT: addi a3, a3, 16
; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 5
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
; CHECK-NEXT: addi a2, sp, 16
@@ -1204,22 +1477,42 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_unmasked_commute(<vscale x 32 x
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 5
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v28, v0.t
; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 5
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: mv a3, a2
; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
+; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 5
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmadd.vv v8, v16, v24, v0.t
+; CHECK-NEXT: vfmadd.vv v24, v16, v8, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 5
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v20, v8, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB35_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -1230,9 +1523,12 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_unmasked_commute(<vscale x 32 x
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v24
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: mv a1, a0
@@ -1240,23 +1536,28 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_unmasked_commute(<vscale x 32 x
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v0
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v0, v8
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v0, v16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmadd.vv v0, v24, v8
+; CHECK-NEXT: vfmadd.vv v0, v24, v16
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v16, v0
-; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: slli a0, a0, 2
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -1876,14 +2177,14 @@ define <vscale x 16 x half> @vfma_vv_nxv16f16(<vscale x 16 x half> %va, <vscale
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vmv4r.v v4, v12
-; ZVFHMIN-NEXT: vmv4r.v v20, v8
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
+; ZVFHMIN-NEXT: vmv4r.v v24, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 16 x half> @llvm.vp.fma.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %b, <vscale x 16 x half> %c, <vscale x 16 x i1> %m, i32 %evl)
ret <vscale x 16 x half> %v
@@ -2031,11 +2332,13 @@ define <vscale x 32 x half> @vfma_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a3, a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v3, v0
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -2043,13 +2346,38 @@ define <vscale x 32 x half> @vfma_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a3, a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vmv8r.v v24, v8
; ZVFHMIN-NEXT: vl8re16.v v16, (a0)
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a0, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a1, a0
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 3
+; ZVFHMIN-NEXT: mv a5, a4
+; ZVFHMIN-NEXT: slli a4, a4, 1
+; ZVFHMIN-NEXT: add a4, a4, a5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a4, a2, 5
+; ZVFHMIN-NEXT: add a2, a4, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a1, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
@@ -2058,80 +2386,118 @@ define <vscale x 32 x half> @vfma_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a4, a3, 5
+; ZVFHMIN-NEXT: add a3, a4, a3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v24, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a3, a3, a2
; ZVFHMIN-NEXT: slli a2, a2, 1
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v24
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v8, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a1, a0, .LBB66_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB66_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a2
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
; ZVFHMIN-NEXT: slli a0, a0, 1
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv.v.v v16, v8
-; ZVFHMIN-NEXT: vmv4r.v v12, v4
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -2158,40 +2524,57 @@ define <vscale x 32 x half> @vfma_vv_nxv32f16_unmasked(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: sub sp, sp, a2
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli a2, zero, e8, m4, ta, ma
+; ZVFHMIN-NEXT: vmv8r.v v24, v8
; ZVFHMIN-NEXT: vl8re16.v v16, (a0)
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; ZVFHMIN-NEXT: vmset.m v24
+; ZVFHMIN-NEXT: vmset.m v8
; ZVFHMIN-NEXT: slli a0, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a1, a0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a4, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a1, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: addi a3, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: mv a4, a3
+; ZVFHMIN-NEXT: slli a3, a3, 1
+; ZVFHMIN-NEXT: add a3, a3, a4
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -2199,33 +2582,46 @@ define <vscale x 32 x half> @vfma_vv_nxv32f16_unmasked(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v24, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v24
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v8, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a1, a0, .LBB67_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB67_2:
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
-; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -2233,15 +2629,11 @@ define <vscale x 32 x half> @vfma_vv_nxv32f16_unmasked(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v0, v24, v8
+; ZVFHMIN-NEXT: vfmadd.vv v0, v24, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v0
-; ZVFHMIN-NEXT: vmv8r.v v8, v16
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add sp, sp, a0
@@ -2265,103 +2657,204 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16(<vscale x 32 x half> %va, half %b,
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a2, a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v3, v0
-; ZVFHMIN-NEXT: vmv8r.v v24, v8
-; ZVFHMIN-NEXT: fmv.x.h a2, fa0
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a1, a3, 1
-; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: sub a4, a0, a1
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a3
-; ZVFHMIN-NEXT: sltu a3, a0, a4
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: addi a4, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv1r.v v24, v0
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: fmv.x.h a1, fa0
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: vmv.v.x v8, a1
+; ZVFHMIN-NEXT: slli a1, a2, 1
+; ZVFHMIN-NEXT: srli a2, a2, 2
+; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
+; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: mv a5, a4
; ZVFHMIN-NEXT: slli a4, a4, 1
; ZVFHMIN-NEXT: add a4, a4, a5
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
-; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a2
+; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a4, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a2, a0, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: mv a4, a3
+; ZVFHMIN-NEXT: slli a3, a3, 1
+; ZVFHMIN-NEXT: add a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB68_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB68_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a2
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: slli a0, a0, 2
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv.v.v v16, v8
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vmv4r.v v12, v4
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -2385,11 +2878,18 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_commute(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a2, a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 2
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v3, v0
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: mv a2, a1
@@ -2400,12 +2900,24 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_commute(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: vmv.v.x v8, a1
+; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v24, a1
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a4, a2, 5
+; ZVFHMIN-NEXT: add a2, a4, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
@@ -2414,16 +2926,34 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_commute(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a4, a3, 5
+; ZVFHMIN-NEXT: add a3, a4, a3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -2431,28 +2961,50 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_commute(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v8, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a0, a1, .LBB69_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB69_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -2460,39 +3012,33 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_commute(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
-; ZVFHMIN-NEXT: vmv4r.v v12, v4
+; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
+; ZVFHMIN-NEXT: vmv.v.v v16, v8
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -2522,61 +3068,73 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_unmasked(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
-; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; ZVFHMIN-NEXT: vmv8r.v v24, v8
-; ZVFHMIN-NEXT: fmv.x.h a2, fa0
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a2
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: fmv.x.h a1, fa0
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmset.m v7
+; ZVFHMIN-NEXT: vmv.v.x v8, a1
+; ZVFHMIN-NEXT: slli a1, a2, 1
+; ZVFHMIN-NEXT: srli a2, a2, 2
+; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v7, v7, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v7, (a2) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a2, a0, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vmset.m v8
-; ZVFHMIN-NEXT: slli a1, a3, 1
-; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: sub a4, a0, a1
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
-; ZVFHMIN-NEXT: sltu a3, a0, a4
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 5
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 4
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: mv a5, a4
-; ZVFHMIN-NEXT: slli a4, a4, 1
-; ZVFHMIN-NEXT: add a4, a4, a5
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a2
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -2586,14 +3144,14 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_unmasked(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB70_2:
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
@@ -2604,20 +3162,23 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_unmasked(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24
-; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v0, v16
+; ZVFHMIN-NEXT: vfmadd.vv v0, v24, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -2646,9 +3207,12 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_unmasked_commute(<vscale x 32 x ha
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 2
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: mv a2, a1
@@ -2666,7 +3230,12 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_unmasked_commute(<vscale x 32 x ha
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a2
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
@@ -2675,6 +3244,11 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_unmasked_commute(<vscale x 32 x ha
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
@@ -2684,22 +3258,42 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_unmasked_commute(<vscale x 32 x ha
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
; ZVFHMIN-NEXT: slli a2, a2, 1
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v8, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB71_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
@@ -2710,9 +3304,12 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_unmasked_commute(<vscale x 32 x ha
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -2720,23 +3317,28 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_unmasked_commute(<vscale x 32 x ha
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v0, v24, v8
+; ZVFHMIN-NEXT: vfmadd.vv v0, v24, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v0
-; ZVFHMIN-NEXT: vmv8r.v v8, v16
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -3408,8 +4010,6 @@ define <vscale x 16 x double> @vfma_vv_nxv16f64(<vscale x 16 x double> %va, <vsc
; CHECK-NEXT: add a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: mv a3, a1
@@ -3455,8 +4055,10 @@ define <vscale x 16 x double> @vfma_vv_nxv16f64(<vscale x 16 x double> %va, <vsc
; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: and a0, a7, a6
+; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: mv a3, a2
@@ -3623,12 +4225,12 @@ define <vscale x 1 x half> @vfmsub_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: lui a1, 8
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v10, v10, a1, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t
+; ZVFHMIN-NEXT: vxor.vx v8, v10, a1, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v12, v10, v11, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v12, v11, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
@@ -3675,12 +4277,12 @@ define <vscale x 1 x half> @vfmsub_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v9, v9, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t
+; ZVFHMIN-NEXT: vxor.vx v8, v9, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v12, v9, v11, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v12, v11, v9, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
@@ -3704,14 +4306,14 @@ define <vscale x 1 x half> @vfmsub_vf_nxv1f16_commute(<vscale x 1 x half> %va, h
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v9, v9, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t
+; ZVFHMIN-NEXT: vxor.vx v8, v9, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v9, v8, v11, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v11, v8, v9, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v11, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
@@ -4024,8 +4626,8 @@ define <vscale x 1 x half> @vfnmadd_vf_nxv1f16_neg_splat(<vscale x 1 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v10, v10, a0, v0.t
; ZVFHMIN-NEXT: vxor.vx v9, v9, a0, v0.t
+; ZVFHMIN-NEXT: vxor.vx v10, v10, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
@@ -4055,8 +4657,8 @@ define <vscale x 1 x half> @vfnmadd_vf_nxv1f16_neg_splat_commute(<vscale x 1 x h
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v10, v10, a0, v0.t
; ZVFHMIN-NEXT: vxor.vx v9, v9, a0, v0.t
+; ZVFHMIN-NEXT: vxor.vx v10, v10, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
@@ -4257,14 +4859,14 @@ define <vscale x 1 x half> @vfnmsub_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: lui a0, 8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
; ZVFHMIN-NEXT: vxor.vx v8, v8, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v9, v11, v8, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v12, v9, v11, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
@@ -4286,14 +4888,14 @@ define <vscale x 1 x half> @vfnmsub_vf_nxv1f16_commute(<vscale x 1 x half> %va,
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: lui a0, 8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
; ZVFHMIN-NEXT: vxor.vx v8, v8, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v11, v9, v8, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v9, v8, v11, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v11, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
@@ -4373,14 +4975,14 @@ define <vscale x 1 x half> @vfnmsub_vf_nxv1f16_neg_splat(<vscale x 1 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v10, v10, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
+; ZVFHMIN-NEXT: vxor.vx v9, v10, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v11, v9, v10, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v10, v9, v11, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v11, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
@@ -4402,12 +5004,12 @@ define <vscale x 1 x half> @vfnmsub_vf_nxv1f16_neg_splat_commute(<vscale x 1 x h
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v10, v10, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
+; ZVFHMIN-NEXT: vxor.vx v9, v10, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v9, v11, v10, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v9, v10, v11, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
@@ -4488,12 +5090,12 @@ define <vscale x 2 x half> @vfmsub_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: lui a1, 8
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v10, v10, a1, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t
+; ZVFHMIN-NEXT: vxor.vx v8, v10, a1, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v12, v10, v11, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v12, v11, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
@@ -4540,12 +5142,12 @@ define <vscale x 2 x half> @vfmsub_vf_nxv2f16(<vscale x 2 x half> %va, half %b,
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v9, v9, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t
+; ZVFHMIN-NEXT: vxor.vx v8, v9, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v12, v9, v11, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v12, v11, v9, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
@@ -4569,14 +5171,14 @@ define <vscale x 2 x half> @vfmsub_vf_nxv2f16_commute(<vscale x 2 x half> %va, h
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v9, v9, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t
+; ZVFHMIN-NEXT: vxor.vx v8, v9, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v9, v8, v11, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v11, v8, v9, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v11, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 2 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> poison, <vscale x 2 x i32> zeroinitializer
@@ -4889,8 +5491,8 @@ define <vscale x 2 x half> @vfnmadd_vf_nxv2f16_neg_splat(<vscale x 2 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v10, v10, a0, v0.t
; ZVFHMIN-NEXT: vxor.vx v9, v9, a0, v0.t
+; ZVFHMIN-NEXT: vxor.vx v10, v10, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
@@ -4920,8 +5522,8 @@ define <vscale x 2 x half> @vfnmadd_vf_nxv2f16_neg_splat_commute(<vscale x 2 x h
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v10, v10, a0, v0.t
; ZVFHMIN-NEXT: vxor.vx v9, v9, a0, v0.t
+; ZVFHMIN-NEXT: vxor.vx v10, v10, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
@@ -5122,14 +5724,14 @@ define <vscale x 2 x half> @vfnmsub_vf_nxv2f16(<vscale x 2 x half> %va, half %b,
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: lui a0, 8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
; ZVFHMIN-NEXT: vxor.vx v8, v8, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v9, v11, v8, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v12, v9, v11, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 2 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> poison, <vscale x 2 x i32> zeroinitializer
@@ -5151,14 +5753,14 @@ define <vscale x 2 x half> @vfnmsub_vf_nxv2f16_commute(<vscale x 2 x half> %va,
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: lui a0, 8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
; ZVFHMIN-NEXT: vxor.vx v8, v8, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v11, v9, v8, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v9, v8, v11, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v11, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 2 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> poison, <vscale x 2 x i32> zeroinitializer
@@ -5238,14 +5840,14 @@ define <vscale x 2 x half> @vfnmsub_vf_nxv2f16_neg_splat(<vscale x 2 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v10, v10, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
+; ZVFHMIN-NEXT: vxor.vx v9, v10, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v11, v9, v10, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v10, v9, v11, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v11, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 2 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> poison, <vscale x 2 x i32> zeroinitializer
@@ -5267,12 +5869,12 @@ define <vscale x 2 x half> @vfnmsub_vf_nxv2f16_neg_splat_commute(<vscale x 2 x h
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v10, v10, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v10, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v9, v0.t
+; ZVFHMIN-NEXT: vxor.vx v9, v10, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v9, v11, v10, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v9, v10, v11, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9, v0.t
; ZVFHMIN-NEXT: ret
@@ -5353,9 +5955,9 @@ define <vscale x 4 x half> @vfmsub_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: lui a1, 8
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v12, v10, a1, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
+; ZVFHMIN-NEXT: vxor.vx v8, v10, a1, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v9, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v14, v12, v10, v0.t
@@ -5403,16 +6005,16 @@ define <vscale x 4 x half> @vfmsub_vf_nxv4f16(<vscale x 4 x half> %va, half %b,
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v16, a1
+; ZVFHMIN-NEXT: vmv.v.x v14, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v9, v9, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v16, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vxor.vx v12, v9, a0, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v14, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v14, v12, v10, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v12, v10, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v14, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 4 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> poison, <vscale x 4 x i32> zeroinitializer
@@ -5434,14 +6036,14 @@ define <vscale x 4 x half> @vfmsub_vf_nxv4f16_commute(<vscale x 4 x half> %va, h
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v14, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v9, v9, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v14, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
+; ZVFHMIN-NEXT: vxor.vx v12, v9, a0, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v14, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v12, v8, v10, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v10, v12, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 4 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> poison, <vscale x 4 x i32> zeroinitializer
@@ -5754,8 +6356,8 @@ define <vscale x 4 x half> @vfnmadd_vf_nxv4f16_neg_splat(<vscale x 4 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v14, v10, a0, v0.t
; ZVFHMIN-NEXT: vxor.vx v9, v9, a0, v0.t
+; ZVFHMIN-NEXT: vxor.vx v14, v10, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v14, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8, v0.t
@@ -5785,8 +6387,8 @@ define <vscale x 4 x half> @vfnmadd_vf_nxv4f16_neg_splat_commute(<vscale x 4 x h
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v14, v10, a0, v0.t
; ZVFHMIN-NEXT: vxor.vx v9, v9, a0, v0.t
+; ZVFHMIN-NEXT: vxor.vx v14, v10, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v14, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8, v0.t
@@ -5985,16 +6587,16 @@ define <vscale x 4 x half> @vfnmsub_vf_nxv4f16(<vscale x 4 x half> %va, half %b,
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v16, a1
+; ZVFHMIN-NEXT: vmv.v.x v14, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v16, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
+; ZVFHMIN-NEXT: vxor.vx v12, v8, a0, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v14, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v14, v10, v12, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v12, v8, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v14, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 4 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> poison, <vscale x 4 x i32> zeroinitializer
@@ -6016,14 +6618,14 @@ define <vscale x 4 x half> @vfnmsub_vf_nxv4f16_commute(<vscale x 4 x half> %va,
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v14, a1
; ZVFHMIN-NEXT: lui a0, 8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
; ZVFHMIN-NEXT: vxor.vx v8, v8, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v14, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v10, v8, v12, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v12, v8, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 4 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> poison, <vscale x 4 x i32> zeroinitializer
@@ -6101,16 +6703,16 @@ define <vscale x 4 x half> @vfnmsub_vf_nxv4f16_neg_splat(<vscale x 4 x half> %va
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v10, a1
+; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v12, v10, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
+; ZVFHMIN-NEXT: vxor.vx v9, v12, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v10, v14, v12, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v12, v14, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 4 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> poison, <vscale x 4 x i32> zeroinitializer
@@ -6130,14 +6732,14 @@ define <vscale x 4 x half> @vfnmsub_vf_nxv4f16_neg_splat_commute(<vscale x 4 x h
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v10, a1
+; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v12, v10, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9, v0.t
+; ZVFHMIN-NEXT: vxor.vx v9, v12, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v14, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v14, v10, v12, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v14, v12, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v14, v0.t
; ZVFHMIN-NEXT: ret
@@ -6218,9 +6820,9 @@ define <vscale x 8 x half> @vfmsub_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: lui a1, 8
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v16, v12, a1, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v16, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; ZVFHMIN-NEXT: vxor.vx v8, v12, a1, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v10, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v20, v16, v12, v0.t
@@ -6268,16 +6870,16 @@ define <vscale x 8 x half> @vfmsub_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v24, a1
+; ZVFHMIN-NEXT: vmv.v.x v20, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v10, v10, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v24, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
+; ZVFHMIN-NEXT: vxor.vx v16, v10, a0, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v20, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v20, v16, v12, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v12, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v20, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
@@ -6299,14 +6901,14 @@ define <vscale x 8 x half> @vfmsub_vf_nxv8f16_commute(<vscale x 8 x half> %va, h
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v20, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v10, v10, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
+; ZVFHMIN-NEXT: vxor.vx v16, v10, a0, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v20, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v12, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v12, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
@@ -6619,8 +7221,8 @@ define <vscale x 8 x half> @vfnmadd_vf_nxv8f16_neg_splat(<vscale x 8 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v20, v12, a0, v0.t
; ZVFHMIN-NEXT: vxor.vx v10, v10, a0, v0.t
+; ZVFHMIN-NEXT: vxor.vx v20, v12, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v20, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8, v0.t
@@ -6650,8 +7252,8 @@ define <vscale x 8 x half> @vfnmadd_vf_nxv8f16_neg_splat_commute(<vscale x 8 x h
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v12, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v20, v12, a0, v0.t
; ZVFHMIN-NEXT: vxor.vx v10, v10, a0, v0.t
+; ZVFHMIN-NEXT: vxor.vx v20, v12, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v20, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8, v0.t
@@ -6850,16 +7452,16 @@ define <vscale x 8 x half> @vfnmsub_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v24, a1
+; ZVFHMIN-NEXT: vmv.v.x v20, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v24, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10, v0.t
+; ZVFHMIN-NEXT: vxor.vx v16, v8, a0, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v20, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v20, v12, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v20, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
@@ -6881,14 +7483,14 @@ define <vscale x 8 x half> @vfnmsub_vf_nxv8f16_commute(<vscale x 8 x half> %va,
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v20, a1
; ZVFHMIN-NEXT: lui a0, 8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10, v0.t
; ZVFHMIN-NEXT: vxor.vx v8, v8, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v12, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
@@ -6966,16 +7568,16 @@ define <vscale x 8 x half> @vfnmsub_vf_nxv8f16_neg_splat(<vscale x 8 x half> %va
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v12, a1
+; ZVFHMIN-NEXT: vmv.v.x v16, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v16, v12, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v16, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10, v0.t
+; ZVFHMIN-NEXT: vxor.vx v10, v16, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v12, v20, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v20, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
@@ -6995,14 +7597,14 @@ define <vscale x 8 x half> @vfnmsub_vf_nxv8f16_neg_splat_commute(<vscale x 8 x h
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v12, a1
+; ZVFHMIN-NEXT: vmv.v.x v16, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v16, v12, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v16, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10, v0.t
+; ZVFHMIN-NEXT: vxor.vx v10, v16, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v20, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v20, v12, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v20, v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v20, v0.t
; ZVFHMIN-NEXT: ret
@@ -7085,14 +7687,14 @@ define <vscale x 16 x half> @vfmsub_vv_nxv16f16(<vscale x 16 x half> %va, <vscal
; ZVFHMIN-NEXT: vmv4r.v v4, v12
; ZVFHMIN-NEXT: vmv4r.v v20, v8
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v16, v16, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: vxor.vx v24, v16, a0, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
; ZVFHMIN-NEXT: ret
%negc = call <vscale x 16 x half> @llvm.vp.fneg.nxv16f16(<vscale x 16 x half> %c, <vscale x 16 x i1> %m, i32 %evl)
%v = call <vscale x 16 x half> @llvm.vp.fma.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %b, <vscale x 16 x half> %negc, <vscale x 16 x i1> %m, i32 %evl)
@@ -7133,19 +7735,18 @@ define <vscale x 16 x half> @vfmsub_vf_nxv16f16(<vscale x 16 x half> %va, half %
;
; ZVFHMIN-LABEL: vfmsub_vf_nxv16f16:
; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vmv4r.v v16, v8
-; ZVFHMIN-NEXT: fmv.x.h a0, fa0
-; ZVFHMIN-NEXT: vmv.v.x v4, a0
+; ZVFHMIN-NEXT: vmv.v.x v4, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v20, v12, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; ZVFHMIN-NEXT: vxor.vx v24, v12, a0, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 16 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> poison, <vscale x 16 x i32> zeroinitializer
@@ -7167,14 +7768,14 @@ define <vscale x 16 x half> @vfmsub_vf_nxv16f16_commute(<vscale x 16 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v4, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v12, v12, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; ZVFHMIN-NEXT: vxor.vx v24, v12, a0, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 16 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> poison, <vscale x 16 x i32> zeroinitializer
@@ -7254,13 +7855,13 @@ define <vscale x 16 x half> @vfnmadd_vv_nxv16f16(<vscale x 16 x half> %va, <vsca
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vmv4r.v v4, v8
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v8, v12, a0, v0.t
-; ZVFHMIN-NEXT: vxor.vx v12, v16, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t
+; ZVFHMIN-NEXT: vxor.vx v20, v12, a0, v0.t
+; ZVFHMIN-NEXT: vxor.vx v16, v16, a0, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
; ZVFHMIN-NEXT: ret
@@ -7490,13 +8091,13 @@ define <vscale x 16 x half> @vfnmadd_vf_nxv16f16_neg_splat(<vscale x 16 x half>
; ZVFHMIN-NEXT: fmv.x.h a0, fa0
; ZVFHMIN-NEXT: vmv.v.x v8, a0
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a0, v0.t
-; ZVFHMIN-NEXT: vxor.vx v12, v12, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t
+; ZVFHMIN-NEXT: vxor.vx v16, v12, a0, v0.t
+; ZVFHMIN-NEXT: vxor.vx v20, v8, a0, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
; ZVFHMIN-NEXT: ret
@@ -7522,10 +8123,10 @@ define <vscale x 16 x half> @vfnmadd_vf_nxv16f16_neg_splat_commute(<vscale x 16
; ZVFHMIN-NEXT: fmv.x.h a0, fa0
; ZVFHMIN-NEXT: vmv.v.x v8, a0
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v16, v8, a0, v0.t
-; ZVFHMIN-NEXT: vxor.vx v20, v12, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vxor.vx v16, v12, a0, v0.t
+; ZVFHMIN-NEXT: vxor.vx v20, v8, a0, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
@@ -7615,13 +8216,13 @@ define <vscale x 16 x half> @vfnmsub_vv_nxv16f16(<vscale x 16 x half> %va, <vsca
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vmv4r.v v4, v8
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v8, v12, a0, v0.t
-; ZVFHMIN-NEXT: vxor.vx v12, v16, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t
+; ZVFHMIN-NEXT: vxor.vx v20, v12, a0, v0.t
+; ZVFHMIN-NEXT: vxor.vx v16, v16, a0, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
; ZVFHMIN-NEXT: ret
@@ -7722,19 +8323,18 @@ define <vscale x 16 x half> @vfnmsub_vf_nxv16f16(<vscale x 16 x half> %va, half
;
; ZVFHMIN-LABEL: vfnmsub_vf_nxv16f16:
; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vmv4r.v v16, v12
-; ZVFHMIN-NEXT: fmv.x.h a0, fa0
-; ZVFHMIN-NEXT: vmv.v.x v4, a0
+; ZVFHMIN-NEXT: vmv.v.x v4, a1
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v20, v8, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vxor.vx v24, v8, a0, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 16 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> poison, <vscale x 16 x i32> zeroinitializer
@@ -7756,14 +8356,14 @@ define <vscale x 16 x half> @vfnmsub_vf_nxv16f16_commute(<vscale x 16 x half> %v
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v4, a1
; ZVFHMIN-NEXT: lui a0, 8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vxor.vx v8, v8, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 16 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> poison, <vscale x 16 x i32> zeroinitializer
@@ -7840,18 +8440,19 @@ define <vscale x 16 x half> @vfnmsub_vf_nxv16f16_neg_splat(<vscale x 16 x half>
; ZVFHMIN-LABEL: vfnmsub_vf_nxv16f16_neg_splat:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vmv4r.v v16, v12
; ZVFHMIN-NEXT: vmv4r.v v4, v8
; ZVFHMIN-NEXT: fmv.x.h a0, fa0
-; ZVFHMIN-NEXT: vmv.v.x v8, a0
+; ZVFHMIN-NEXT: vmv.v.x v20, a0
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vxor.vx v16, v20, a0, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 16 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> poison, <vscale x 16 x i32> zeroinitializer
@@ -7873,14 +8474,14 @@ define <vscale x 16 x half> @vfnmsub_vf_nxv16f16_neg_splat_commute(<vscale x 16
; ZVFHMIN-NEXT: vmv4r.v v16, v12
; ZVFHMIN-NEXT: vmv4r.v v4, v8
; ZVFHMIN-NEXT: fmv.x.h a0, fa0
-; ZVFHMIN-NEXT: vmv.v.x v8, a0
+; ZVFHMIN-NEXT: vmv.v.x v20, a0
; ZVFHMIN-NEXT: lui a0, 8
-; ZVFHMIN-NEXT: vxor.vx v20, v8, a0, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vxor.vx v16, v20, a0, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
@@ -7963,19 +8564,30 @@ define <vscale x 32 x half> @vfmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscal
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a3, a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v3, v0
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: mv a3, a2
; ZVFHMIN-NEXT: slli a2, a2, 1
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vmv8r.v v16, v8
; ZVFHMIN-NEXT: vl8re16.v v24, (a0)
; ZVFHMIN-NEXT: lui a2, 8
@@ -7983,28 +8595,64 @@ define <vscale x 32 x half> @vfmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscal
; ZVFHMIN-NEXT: slli a0, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a4, a1, a0
-; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a3
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: slli a5, a5, 4
+; ZVFHMIN-NEXT: mv a6, a5
+; ZVFHMIN-NEXT: slli a5, a5, 1
+; ZVFHMIN-NEXT: add a5, a5, a6
+; ZVFHMIN-NEXT: add a5, sp, a5
+; ZVFHMIN-NEXT: addi a5, a5, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a5) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
; ZVFHMIN-NEXT: sltu a3, a1, a4
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: slli a5, a5, 4
+; ZVFHMIN-NEXT: mv a6, a5
+; ZVFHMIN-NEXT: slli a5, a5, 1
+; ZVFHMIN-NEXT: add a5, a5, a6
+; ZVFHMIN-NEXT: add a5, sp, a5
+; ZVFHMIN-NEXT: addi a5, a5, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v24, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: vmv4r.v v8, v24
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v16, v0
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -8013,38 +8661,64 @@ define <vscale x 32 x half> @vfmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscal
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a1, a0, .LBB280_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB280_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a2
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -8052,23 +8726,27 @@ define <vscale x 32 x half> @vfmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscal
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v24, v16, v0.t
-; ZVFHMIN-NEXT: vmv.v.v v16, v8
-; ZVFHMIN-NEXT: vmv4r.v v12, v4
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -8092,20 +8770,20 @@ define <vscale x 32 x half> @vfmsub_vv_nxv32f16_unmasked(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
-; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: mv a3, a2
; ZVFHMIN-NEXT: slli a2, a2, 1
; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: sub sp, sp, a2
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli a2, zero, e8, m4, ta, ma
-; ZVFHMIN-NEXT: vmv8r.v v24, v8
-; ZVFHMIN-NEXT: vl8re16.v v16, (a0)
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
+; ZVFHMIN-NEXT: vl8re16.v v24, (a0)
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: vmset.m v8
; ZVFHMIN-NEXT: csrr a3, vlenb
@@ -8113,16 +8791,54 @@ define <vscale x 32 x half> @vfmsub_vv_nxv32f16_unmasked(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a4, a1, a0
; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: mv a5, a3
+; ZVFHMIN-NEXT: slli a3, a3, 2
+; ZVFHMIN-NEXT: add a3, a3, a5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a3, a1, a4
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v16, v16, a2
+; ZVFHMIN-NEXT: vxor.vx v24, v24, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: vmv4r.v v8, v16
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a4, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vmv4r.v v8, v24
; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
@@ -8130,48 +8846,65 @@ define <vscale x 32 x half> @vfmsub_vv_nxv32f16_unmasked(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: slli a2, a2, 2
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a1, a0, .LBB281_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB281_2:
; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
+; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -8179,20 +8912,32 @@ define <vscale x 32 x half> @vfmsub_vv_nxv32f16_unmasked(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v0, v16, v24
+; ZVFHMIN-NEXT: vfmadd.vv v0, v24, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
-; ZVFHMIN-NEXT: add sp, sp, a0
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 0
@@ -8214,96 +8959,148 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16(<vscale x 32 x half> %va, half %
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a2, a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 2
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v3, v0
-; ZVFHMIN-NEXT: fmv.x.h a2, fa0
-; ZVFHMIN-NEXT: lui a1, 8
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv8r.v v24, v8
+; ZVFHMIN-NEXT: fmv.x.h a1, fa0
+; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vxor.vx v24, v16, a1, v0.t
-; ZVFHMIN-NEXT: vmv8r.v v16, v8
+; ZVFHMIN-NEXT: vmv.v.x v8, a1
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: mv a4, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: sub a4, a0, a1
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a3
-; ZVFHMIN-NEXT: sltu a3, a0, a4
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: mv a5, a4
-; ZVFHMIN-NEXT: slli a4, a4, 1
-; ZVFHMIN-NEXT: add a4, a4, a5
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
-; ZVFHMIN-NEXT: addi a4, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: sub a2, a0, a1
; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
+; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a4, a3, 5
+; ZVFHMIN-NEXT: add a3, a4, a3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a3, a0, a2
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a4, a3, 5
+; ZVFHMIN-NEXT: add a3, a4, a3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v16, a2
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a0, a1, .LBB282_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB282_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
-; ZVFHMIN-NEXT: mv a2, a1
-; ZVFHMIN-NEXT: slli a1, a1, 1
-; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -8311,15 +9108,26 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16(<vscale x 32 x half> %va, half %
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv.v.v v16, v8
-; ZVFHMIN-NEXT: vmv4r.v v12, v4
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -8344,48 +9152,46 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16_commute(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
-; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v3, v0
-; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: mv a2, a1
-; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a2, a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 2
; ZVFHMIN-NEXT: add a1, a1, a2
+; ZVFHMIN-NEXT: sub sp, sp, a1
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a2, a1, 5
+; ZVFHMIN-NEXT: add a1, a2, a1
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vmv.v.x v8, a1
+; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v24, a1
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a3
; ZVFHMIN-NEXT: sltu a3, a0, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -8393,43 +9199,51 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16_commute(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v24, v0
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v24
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v8, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a0, a1, .LBB283_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB283_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -8437,24 +9251,26 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16_commute(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
-; ZVFHMIN-NEXT: vmv4r.v v12, v4
+; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
+; ZVFHMIN-NEXT: vmv.v.v v16, v8
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -8485,64 +9301,76 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16_unmasked(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
-; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; ZVFHMIN-NEXT: vmv8r.v v24, v8
-; ZVFHMIN-NEXT: fmv.x.h a2, fa0
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vmset.m v8
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v16, v16, a1
-; ZVFHMIN-NEXT: slli a1, a3, 1
-; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: sub a4, a0, a1
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
-; ZVFHMIN-NEXT: sltu a3, a0, a4
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: mv a5, a4
-; ZVFHMIN-NEXT: slli a4, a4, 1
-; ZVFHMIN-NEXT: add a4, a4, a5
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 4
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 5
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a2
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a2
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: fmv.x.h a1, fa0
+; ZVFHMIN-NEXT: lui a2, 8
+; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmset.m v7
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: vmv.v.x v8, a1
+; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vxor.vx v16, v16, a2
+; ZVFHMIN-NEXT: slli a1, a3, 1
+; ZVFHMIN-NEXT: srli a3, a3, 2
+; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v7, v7, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v7, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a3, a0, a2
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -8553,37 +9381,40 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16_unmasked(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: .LBB284_2:
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
-; ZVFHMIN-NEXT: mv a2, a1
-; ZVFHMIN-NEXT: slli a1, a1, 1
-; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v0, v16
+; ZVFHMIN-NEXT: vfmadd.vv v0, v24, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -8627,16 +9458,16 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16_unmasked_commute(<vscale x 32 x
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmset.m v24
+; ZVFHMIN-NEXT: vmset.m v8
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vmv.v.x v8, a1
+; ZVFHMIN-NEXT: vmv.v.x v24, a1
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; ZVFHMIN-NEXT: vxor.vx v16, v16, a2
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a3
+; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
; ZVFHMIN-NEXT: sltu a3, a0, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a2, a3, a2
@@ -8646,15 +9477,14 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16_unmasked_commute(<vscale x 32 x
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v24, v0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -8662,14 +9492,13 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16_unmasked_commute(<vscale x 32 x
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v24
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v8, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB285_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
@@ -8678,9 +9507,9 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16_unmasked_commute(<vscale x 32 x
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
@@ -8696,15 +9525,14 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16_unmasked_commute(<vscale x 32 x
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v0, v24, v8
+; ZVFHMIN-NEXT: vfmadd.vv v0, v24, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v0
-; ZVFHMIN-NEXT: vmv8r.v v8, v16
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add sp, sp, a0
@@ -8733,11 +9561,16 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v3, v0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -8754,14 +9587,29 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v8, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a0, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a4, a1, a0
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: slli a5, a5, 5
+; ZVFHMIN-NEXT: add a5, sp, a5
+; ZVFHMIN-NEXT: addi a5, a5, 16
+; ZVFHMIN-NEXT: vl1r.v v24, (a5) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a3
+; ZVFHMIN-NEXT: vslidedown.vx v7, v24, a3
; ZVFHMIN-NEXT: sltu a3, a1, a4
; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: slli a5, a5, 5
+; ZVFHMIN-NEXT: add a5, sp, a5
+; ZVFHMIN-NEXT: addi a5, a5, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a5, vlenb
; ZVFHMIN-NEXT: slli a5, a5, 4
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
@@ -8770,22 +9618,21 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v8, v7
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -8793,19 +9640,24 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a1, a0, .LBB286_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB286_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
@@ -8813,8 +9665,6 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
@@ -8833,22 +9683,23 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
-; ZVFHMIN-NEXT: vmv4r.v v12, v4
+; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
+; ZVFHMIN-NEXT: vmv.v.v v16, v8
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -8873,49 +9724,79 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a3, a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v3, v0
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: slli a2, a2, 2
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vl8re16.v v8, (a0)
+; ZVFHMIN-NEXT: vl8re16.v v24, (a0)
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a4, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a0, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a4, a1, a0
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: slli a5, a5, 3
+; ZVFHMIN-NEXT: mv a6, a5
+; ZVFHMIN-NEXT: slli a5, a5, 2
+; ZVFHMIN-NEXT: add a5, a5, a6
+; ZVFHMIN-NEXT: add a5, sp, a5
+; ZVFHMIN-NEXT: addi a5, a5, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a5) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a3
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
; ZVFHMIN-NEXT: sltu a3, a1, a4
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: slli a5, a5, 3
+; ZVFHMIN-NEXT: mv a6, a5
+; ZVFHMIN-NEXT: slli a5, a5, 2
+; ZVFHMIN-NEXT: add a5, a5, a6
+; ZVFHMIN-NEXT: add a5, sp, a5
+; ZVFHMIN-NEXT: addi a5, a5, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: vmv4r.v v8, v24
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -8923,63 +9804,99 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v16, v0
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a1, a0, .LBB287_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB287_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a2
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a2
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: slli a0, a0, 2
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv.v.v v16, v8
-; ZVFHMIN-NEXT: vmv4r.v v12, v4
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -9004,9 +9921,12 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_unmasked(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -9026,13 +9946,23 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_unmasked(<vscale x 32 x half> %
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a4, a1, a0
; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a3, a1, a4
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: vxor.vx v8, v24, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a3, a3, a4
; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
@@ -9046,6 +9976,11 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_unmasked(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
@@ -9054,12 +9989,27 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_unmasked(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a1, a0, .LBB288_2
@@ -9073,14 +10023,17 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_unmasked(<vscale x 32 x half> %
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
-; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -9088,16 +10041,22 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_unmasked(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v0
+; ZVFHMIN-NEXT: vfmadd.vv v0, v16, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -9122,14 +10081,14 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_unmasked_commuted(<vscale x 32
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
-; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: slli a2, a2, 2
; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: sub sp, sp, a2
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
@@ -9147,24 +10106,19 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_unmasked_commuted(<vscale x 32
; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
; ZVFHMIN-NEXT: sltu a3, a1, a4
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v24, a2
+; ZVFHMIN-NEXT: vxor.vx v24, v24, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vmv4r.v v8, v24
+; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -9172,10 +10126,31 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_unmasked_commuted(<vscale x 32
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v16, v0
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -9185,37 +10160,43 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_unmasked_commuted(<vscale x 32
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB289_2:
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a2
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v0, v16, v24
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -9239,15 +10220,29 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a2, a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 2
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v3, v0
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a2, a1, 5
+; ZVFHMIN-NEXT: add a1, a2, a1
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vmv.v.x v24, a1
+; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v16, a1
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: mv a4, a1
@@ -9255,33 +10250,79 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: add a1, a1, a4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vxor.vx v24, v8, a2, v0.t
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a4, a1, 5
+; ZVFHMIN-NEXT: add a1, a4, a1
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v8, v8, a2, v0.t
-; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v16, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a3
+; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a4, a3, 5
+; ZVFHMIN-NEXT: add a3, a4, a3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a3, a0, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a4, a3, 5
+; ZVFHMIN-NEXT: add a3, a4, a3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: vmv8r.v v24, v8
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -9291,37 +10332,59 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a0, a1, .LBB290_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB290_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -9329,23 +10392,31 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v24, v16, v0.t
-; ZVFHMIN-NEXT: vmv.v.v v16, v8
-; ZVFHMIN-NEXT: vmv4r.v v12, v4
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -9371,15 +10442,29 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a2, a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 2
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v3, v0
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a2, a1, 5
+; ZVFHMIN-NEXT: add a1, a2, a1
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vmv.v.x v24, a1
+; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v16, a1
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: mv a4, a1
@@ -9387,15 +10472,42 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a1, a1, a4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vxor.vx v24, v8, a2, v0.t
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a4, a1, 5
+; ZVFHMIN-NEXT: add a1, a4, a1
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v8, v8, a2, v0.t
-; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v16, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a3
+; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a4, a3, 5
+; ZVFHMIN-NEXT: add a3, a4, a3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a3, a0, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a2, a3, a2
@@ -9403,17 +10515,35 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a4, a3, 5
+; ZVFHMIN-NEXT: add a3, a4, a3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -9423,17 +10553,35 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a0, a1, .LBB291_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB291_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: add a1, sp, a1
@@ -9441,7 +10589,11 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
@@ -9456,28 +10608,27 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v24, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
; ZVFHMIN-NEXT: vmv.v.v v16, v8
-; ZVFHMIN-NEXT: vmv4r.v v12, v4
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -9509,105 +10660,122 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_unmasked(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
-; ZVFHMIN-NEXT: fmv.x.h a2, fa0
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli a3, zero, e8, m4, ta, ma
+; ZVFHMIN-NEXT: fmv.x.h a1, fa0
+; ZVFHMIN-NEXT: lui a2, 8
+; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma
; ZVFHMIN-NEXT: vmset.m v7
; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: vmv.v.x v24, a1
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: mv a4, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v24, v8, a1
-; ZVFHMIN-NEXT: vxor.vx v8, v16, a1
+; ZVFHMIN-NEXT: vxor.vx v8, v8, a2
+; ZVFHMIN-NEXT: vxor.vx v16, v16, a2
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: sub a4, a0, a1
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a3
-; ZVFHMIN-NEXT: sltu a3, a0, a4
+; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v7, v7, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v7, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a3, a0, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: mv a5, a4
-; ZVFHMIN-NEXT: slli a4, a4, 1
-; ZVFHMIN-NEXT: add a4, a4, a5
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 4
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 5
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a2
+; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vmv8r.v v8, v16
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB292_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB292_2:
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
-; ZVFHMIN-NEXT: mv a2, a1
-; ZVFHMIN-NEXT: slli a1, a1, 1
-; ZVFHMIN-NEXT: add a1, a1, a2
+; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24
-; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v0, v16
+; ZVFHMIN-NEXT: vfmadd.vv v0, v24, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -9638,59 +10806,85 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_unmasked_commute(<vscale x 32 x
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 2
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: fmv.x.h a2, fa0
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli a3, zero, e8, m4, ta, ma
-; ZVFHMIN-NEXT: vmset.m v24
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
+; ZVFHMIN-NEXT: fmv.x.h a1, fa0
+; ZVFHMIN-NEXT: lui a2, 8
+; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmset.m v7
; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: vmv.v.x v24, a1
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: mv a4, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
-; ZVFHMIN-NEXT: vxor.vx v16, v16, a1
+; ZVFHMIN-NEXT: vxor.vx v8, v8, a2
+; ZVFHMIN-NEXT: vxor.vx v16, v16, a2
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: sub a4, a0, a1
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a3
-; ZVFHMIN-NEXT: sltu a3, a0, a4
+; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v7, v7, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v7, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a3, a0, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 4
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: mv a5, a4
-; ZVFHMIN-NEXT: slli a4, a4, 1
-; ZVFHMIN-NEXT: add a4, a4, a5
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
-; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a2
; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB293_2
@@ -9698,17 +10892,23 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_unmasked_commute(<vscale x 32 x
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB293_2:
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -9718,20 +10918,20 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_unmasked_commute(<vscale x 32 x
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v0, v24
+; ZVFHMIN-NEXT: vfmadd.vv v0, v24, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -9757,11 +10957,18 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a2, a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 2
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v3, v0
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: mv a2, a1
@@ -9773,32 +10980,73 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v24, a1
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: vxor.vx v8, v24, a2, v0.t
-; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a3
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a4, a3, 5
+; ZVFHMIN-NEXT: add a3, a4, a3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a3, a0, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a4, a3, 5
+; ZVFHMIN-NEXT: add a3, a4, a3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv8r.v v16, v24
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -9806,30 +11054,52 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a0, a1, .LBB294_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB294_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
@@ -9841,28 +11111,27 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v24, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
; ZVFHMIN-NEXT: vmv.v.v v16, v8
-; ZVFHMIN-NEXT: vmv4r.v v12, v4
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -9888,11 +11157,18 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a2, a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 2
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v3, v0
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: mv a2, a1
@@ -9904,32 +11180,72 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v24, a1
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: vxor.vx v8, v24, a2, v0.t
-; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a3
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a4, a3, 5
+; ZVFHMIN-NEXT: add a3, a4, a3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a3, a0, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a4, a3, 5
+; ZVFHMIN-NEXT: add a3, a4, a3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -9938,38 +11254,60 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v8, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a0, a1, .LBB295_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB295_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -9978,22 +11316,30 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv.v.v v16, v8
-; ZVFHMIN-NEXT: vmv4r.v v12, v4
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -10019,9 +11365,12 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_unmasked(<vscale x 32
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 2
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: mv a2, a1
@@ -10043,7 +11392,12 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_unmasked(<vscale x 32
; ZVFHMIN-NEXT: vxor.vx v8, v24, a2
; ZVFHMIN-NEXT: sub a2, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a3
+; ZVFHMIN-NEXT: vslidedown.vx v24, v7, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a3, a0, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a2, a3, a2
@@ -10052,6 +11406,11 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_unmasked(<vscale x 32
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
@@ -10061,6 +11420,11 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_unmasked(<vscale x 32
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
@@ -10069,12 +11433,17 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_unmasked(<vscale x 32
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB296_2
@@ -10088,7 +11457,10 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_unmasked(<vscale x 32
; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
-; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
@@ -10105,14 +11477,20 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_unmasked(<vscale x 32
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
-; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v0, v24, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -10138,9 +11516,12 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_unmasked_commute(<vsc
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 2
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: mv a2, a1
@@ -10162,7 +11543,12 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_unmasked_commute(<vsc
; ZVFHMIN-NEXT: vxor.vx v8, v24, a2
; ZVFHMIN-NEXT: sub a2, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v7, a3
+; ZVFHMIN-NEXT: vslidedown.vx v24, v7, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a3, a0, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a2, a3, a2
@@ -10171,6 +11557,11 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_unmasked_commute(<vsc
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
@@ -10180,6 +11571,11 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_unmasked_commute(<vsc
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
@@ -10188,14 +11584,19 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_unmasked_commute(<vsc
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v24, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v8, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB297_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
@@ -10204,17 +11605,20 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_unmasked_commute(<vsc
; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
-; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -10222,17 +11626,22 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_unmasked_commute(<vsc
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v8
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v0, v24, v8
+; ZVFHMIN-NEXT: vfmadd.vv v0, v24, v16
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v0
-; ZVFHMIN-NEXT: vmv8r.v v8, v16
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -10260,11 +11669,16 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v3, v0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -10281,14 +11695,29 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v8, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a0, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a4, a1, a0
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: slli a5, a5, 5
+; ZVFHMIN-NEXT: add a5, sp, a5
+; ZVFHMIN-NEXT: addi a5, a5, 16
+; ZVFHMIN-NEXT: vl1r.v v24, (a5) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a3
+; ZVFHMIN-NEXT: vslidedown.vx v7, v24, a3
; ZVFHMIN-NEXT: sltu a3, a1, a4
; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: slli a5, a5, 5
+; ZVFHMIN-NEXT: add a5, sp, a5
+; ZVFHMIN-NEXT: addi a5, a5, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a5, vlenb
; ZVFHMIN-NEXT: slli a5, a5, 4
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
@@ -10297,22 +11726,21 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v8, v7
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -10320,19 +11748,24 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a1, a0, .LBB298_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB298_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
@@ -10340,8 +11773,6 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
@@ -10360,22 +11791,23 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
-; ZVFHMIN-NEXT: vmv4r.v v12, v4
+; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
+; ZVFHMIN-NEXT: vmv.v.v v16, v8
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -10400,49 +11832,79 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a3, a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v3, v0
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: slli a2, a2, 2
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vl8re16.v v8, (a0)
+; ZVFHMIN-NEXT: vl8re16.v v24, (a0)
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a4, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a0, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a4, a1, a0
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a3
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: slli a5, a5, 3
+; ZVFHMIN-NEXT: mv a6, a5
+; ZVFHMIN-NEXT: slli a5, a5, 2
+; ZVFHMIN-NEXT: add a5, a5, a6
+; ZVFHMIN-NEXT: add a5, sp, a5
+; ZVFHMIN-NEXT: addi a5, a5, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a5) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
; ZVFHMIN-NEXT: sltu a3, a1, a4
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: slli a5, a5, 3
+; ZVFHMIN-NEXT: mv a6, a5
+; ZVFHMIN-NEXT: slli a5, a5, 2
+; ZVFHMIN-NEXT: add a5, a5, a6
+; ZVFHMIN-NEXT: add a5, sp, a5
+; ZVFHMIN-NEXT: addi a5, a5, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: vmv4r.v v8, v24
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -10450,63 +11912,99 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v16, v0
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a1, a0, .LBB299_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB299_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a2
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a2
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: slli a0, a0, 2
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv.v.v v16, v8
-; ZVFHMIN-NEXT: vmv4r.v v12, v4
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -10531,9 +12029,12 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_unmasked(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -10553,13 +12054,23 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_unmasked(<vscale x 32 x half> %
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a4, a1, a0
; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a3, a1, a4
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: vxor.vx v8, v24, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a3, a3, a4
; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
@@ -10573,6 +12084,11 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_unmasked(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
@@ -10581,12 +12097,27 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_unmasked(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a1, a0, .LBB300_2
@@ -10600,14 +12131,17 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_unmasked(<vscale x 32 x half> %
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
-; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -10615,16 +12149,22 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_unmasked(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v0
+; ZVFHMIN-NEXT: vfmadd.vv v0, v16, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -10649,14 +12189,14 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_unmasked_commuted(<vscale x 32
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
-; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: slli a2, a2, 2
; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: sub sp, sp, a2
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
@@ -10674,24 +12214,19 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_unmasked_commuted(<vscale x 32
; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
; ZVFHMIN-NEXT: sltu a3, a1, a4
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v24, a2
+; ZVFHMIN-NEXT: vxor.vx v24, v24, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vmv4r.v v8, v24
+; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -10699,10 +12234,31 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_unmasked_commuted(<vscale x 32
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v16, v0
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -10712,37 +12268,43 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_unmasked_commuted(<vscale x 32
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB301_2:
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a2
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v0, v16, v24
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -10766,62 +12328,128 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a2, a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 2
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v3, v0
-; ZVFHMIN-NEXT: vmv8r.v v24, v16
-; ZVFHMIN-NEXT: fmv.x.h a2, fa0
-; ZVFHMIN-NEXT: lui a1, 8
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: fmv.x.h a1, fa0
+; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vxor.vx v16, v8, a1, v0.t
-; ZVFHMIN-NEXT: slli a1, a3, 1
-; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: sub a4, a0, a1
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a3
-; ZVFHMIN-NEXT: sltu a3, a0, a4
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: addi a4, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v24, a1
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: mv a4, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vxor.vx v8, v8, a2, v0.t
+; ZVFHMIN-NEXT: slli a1, a3, 1
+; ZVFHMIN-NEXT: srli a3, a3, 2
+; ZVFHMIN-NEXT: sub a2, a0, a1
; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: mv a5, a4
-; ZVFHMIN-NEXT: slli a4, a4, 1
-; ZVFHMIN-NEXT: add a4, a4, a5
+; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
-; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a2
+; ZVFHMIN-NEXT: vl1r.v v24, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v24, v24, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a4, a3, 5
+; ZVFHMIN-NEXT: add a3, a4, a3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a3, a0, a2
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a4, a3, 5
+; ZVFHMIN-NEXT: add a3, a4, a3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a0, a1, .LBB302_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB302_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: add a1, sp, a1
@@ -10829,43 +12457,45 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v24, v16, v0.t
-; ZVFHMIN-NEXT: vmv.v.v v16, v8
-; ZVFHMIN-NEXT: vmv4r.v v12, v4
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -10890,112 +12520,239 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a2, a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v3, v0
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: mv a2, a1
; ZVFHMIN-NEXT: slli a1, a1, 1
; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: fmv.x.h a2, fa0
-; ZVFHMIN-NEXT: lui a1, 8
+; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: fmv.x.h a1, fa0
+; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vxor.vx v16, v8, a1, v0.t
+; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v24, a1
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: mv a4, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vxor.vx v8, v8, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: sub a4, a0, a1
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a3
-; ZVFHMIN-NEXT: sltu a3, a0, a4
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: sub a2, a0, a1
; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
+; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: mv a5, a4
; ZVFHMIN-NEXT: slli a4, a4, 1
; ZVFHMIN-NEXT: add a4, a4, a5
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
-; ZVFHMIN-NEXT: addi a4, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v16, a2
+; ZVFHMIN-NEXT: vl1r.v v24, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v24, v24, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: mv a4, a3
+; ZVFHMIN-NEXT: slli a3, a3, 2
+; ZVFHMIN-NEXT: add a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a3, a0, a2
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: mv a4, a3
+; ZVFHMIN-NEXT: slli a3, a3, 2
+; ZVFHMIN-NEXT: add a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a0, a1, .LBB303_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB303_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: slli a0, a0, 1
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
-; ZVFHMIN-NEXT: vmv4r.v v12, v4
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -11026,104 +12783,120 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_unmasked(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
-; ZVFHMIN-NEXT: fmv.x.h a2, fa0
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli a3, zero, e8, m4, ta, ma
-; ZVFHMIN-NEXT: vmset.m v24
+; ZVFHMIN-NEXT: fmv.x.h a1, fa0
+; ZVFHMIN-NEXT: lui a2, 8
+; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmset.m v7
; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: vmv.v.x v24, a1
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: mv a4, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
+; ZVFHMIN-NEXT: vxor.vx v8, v8, a2
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: sub a4, a0, a1
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a3
-; ZVFHMIN-NEXT: sltu a3, a0, a4
+; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v7, v7, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v7, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a3, a0, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: mv a5, a4
-; ZVFHMIN-NEXT: slli a4, a4, 1
-; ZVFHMIN-NEXT: add a4, a4, a5
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 4
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 5
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a2
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB304_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB304_2:
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
-; ZVFHMIN-NEXT: mv a2, a1
-; ZVFHMIN-NEXT: slli a1, a1, 1
-; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24
-; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v0
+; ZVFHMIN-NEXT: vfmadd.vv v0, v16, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -11156,53 +12929,76 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_unmasked_commute(<vscale x 32 x
; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: sub sp, sp, a1
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: fmv.x.h a2, fa0
-; ZVFHMIN-NEXT: lui a1, 8
-; ZVFHMIN-NEXT: vsetvli a3, zero, e8, m4, ta, ma
+; ZVFHMIN-NEXT: fmv.x.h a1, fa0
+; ZVFHMIN-NEXT: lui a2, 8
+; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma
; ZVFHMIN-NEXT: vmset.m v24
; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: vmv.v.x v0, a1
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a1
+; ZVFHMIN-NEXT: vxor.vx v8, v8, a2
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: sub a4, a0, a1
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a3
-; ZVFHMIN-NEXT: sltu a3, a0, a4
+; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v24, v24, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: mv a4, a3
+; ZVFHMIN-NEXT: slli a3, a3, 1
+; ZVFHMIN-NEXT: add a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a3, a0, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 4
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: addi a3, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: mv a4, a3
+; ZVFHMIN-NEXT: slli a3, a3, 1
+; ZVFHMIN-NEXT: add a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: mv a5, a4
-; ZVFHMIN-NEXT: slli a4, a4, 1
-; ZVFHMIN-NEXT: add a4, a4, a5
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a2
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v16, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
@@ -11211,39 +13007,42 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_unmasked_commute(<vscale x 32 x
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB305_2:
-; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 4
-; ZVFHMIN-NEXT: add a1, sp, a1
-; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: addi a1, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v24
-; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v0, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v0
+; ZVFHMIN-NEXT: vfmadd.vv v0, v16, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add sp, sp, a0
@@ -11270,13 +13069,23 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a2, a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 2
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v3, v0
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 2
+; ZVFHMIN-NEXT: add a1, a1, a2
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
@@ -11291,31 +13100,47 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vmv.v.x v16, a1
+; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v24, a1
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: vxor.vx v8, v16, a2, v0.t
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 3
+; ZVFHMIN-NEXT: mv a5, a4
+; ZVFHMIN-NEXT: slli a4, a4, 2
+; ZVFHMIN-NEXT: add a4, a4, a5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vxor.vx v16, v24, a2, v0.t
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 3
+; ZVFHMIN-NEXT: mv a5, a4
+; ZVFHMIN-NEXT: slli a4, a4, 2
+; ZVFHMIN-NEXT: add a4, a4, a5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a3
+; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
; ZVFHMIN-NEXT: sltu a3, a0, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -11323,39 +13148,50 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a0, a1, .LBB306_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB306_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: mv a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 2
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -11364,21 +13200,53 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
-; ZVFHMIN-NEXT: vmv4r.v v12, v4
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -11403,12 +13271,15 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: slli a2, a1, 5
+; ZVFHMIN-NEXT: add a1, a2, a1
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v3, v0
-; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: mv a2, a1
@@ -11420,31 +13291,43 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vmv.v.x v16, a1
+; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v24, a1
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: vxor.vx v8, v16, a2, v0.t
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a3
+; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
; ZVFHMIN-NEXT: sltu a3, a0, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: vmv4r.v v8, v24
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v24, v0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -11452,39 +13335,42 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v24
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v24, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v8, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a0, a1, .LBB307_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB307_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -11492,23 +13378,22 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v24, v16, v0.t
-; ZVFHMIN-NEXT: vmv.v.v v16, v8
-; ZVFHMIN-NEXT: vmv4r.v v12, v4
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -11543,11 +13428,6 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat_unmasked(<vscale x 32
; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 4
-; ZVFHMIN-NEXT: add a1, sp, a1
-; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
@@ -11555,45 +13435,44 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat_unmasked(<vscale x 32
; ZVFHMIN-NEXT: vmset.m v8
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v16, a1
+; ZVFHMIN-NEXT: vmv.v.x v24, a1
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: vxor.vx v16, v16, a2
+; ZVFHMIN-NEXT: vxor.vx v0, v24, a2
; ZVFHMIN-NEXT: sub a2, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
+; ZVFHMIN-NEXT: vslidedown.vx v12, v8, a3
; ZVFHMIN-NEXT: sltu a3, a0, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a2, a3, a2
-; ZVFHMIN-NEXT: vmv4r.v v8, v16
+; ZVFHMIN-NEXT: vmv4r.v v8, v0
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB308_2
@@ -11610,16 +13489,16 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat_unmasked(<vscale x 32
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
@@ -11659,8 +13538,6 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat_unmasked_commute(<vsc
; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: sub sp, sp, a1
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; ZVFHMIN-NEXT: vmv8r.v v24, v16
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: mv a2, a1
@@ -11671,36 +13548,36 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat_unmasked_commute(<vsc
; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
+; ZVFHMIN-NEXT: vsetvli a3, zero, e8, m4, ta, ma
; ZVFHMIN-NEXT: vmset.m v8
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v16, a1
+; ZVFHMIN-NEXT: vmv.v.x v24, a1
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: vxor.vx v16, v16, a2
+; ZVFHMIN-NEXT: vxor.vx v24, v24, a2
; ZVFHMIN-NEXT: sub a2, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
; ZVFHMIN-NEXT: sltu a3, a0, a2
; ZVFHMIN-NEXT: addi a3, a3, -1
; ZVFHMIN-NEXT: and a2, a3, a2
-; ZVFHMIN-NEXT: vmv4r.v v8, v16
+; ZVFHMIN-NEXT: vmv4r.v v8, v24
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vmv4r.v v16, v24
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v24, v0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -11708,14 +13585,13 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat_unmasked_commute(<vsc
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v24
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB309_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
index 394887fee67fc..42dd2dd28f614 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
@@ -168,44 +168,86 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vmv8r.v v24, v16
+; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: csrr a4, vlenb
+; CHECK-NEXT: slli a4, a4, 4
+; CHECK-NEXT: add a4, sp, a4
+; CHECK-NEXT: addi a4, a4, 16
+; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vslidedown.vx v7, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: addi a3, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 4
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmax.vv v16, v16, v24, v0.t
+; CHECK-NEXT: vfmax.vv v24, v24, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB10_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB10_2:
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16, v0.t
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 4
+; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmax.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vfmax.vv v16, v16, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -221,44 +263,83 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a2, a1, 4
+; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; CHECK-NEXT: vmset.m v24
+; CHECK-NEXT: vmv8r.v v24, v16
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: vmset.m v8
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v24, a2
+; CHECK-NEXT: vslidedown.vx v8, v8, a2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 4
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a3, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmax.vv v16, v16, v24, v0.t
+; CHECK-NEXT: vfmax.vv v24, v24, v8, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB11_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB11_2:
; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmax.vv v16, v24, v16
+; CHECK-NEXT: vfmax.vv v16, v16, v24
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 4
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -490,44 +571,86 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: mv a2, a1
; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a2, a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 4
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 4
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmax.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfmax.vv v24, v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB22_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: addi a1, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v8, v0
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmax.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vfmax.vv v16, v16, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -549,44 +672,83 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a2, a1, 4
+; ZVFHMIN-NEXT: add a1, a2, a1
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; ZVFHMIN-NEXT: vmset.m v24
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: vmset.m v8
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmax.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfmax.vv v24, v24, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB23_2:
; ZVFHMIN-NEXT: addi a1, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmax.vv v16, v24, v16
+; ZVFHMIN-NEXT: vfmax.vv v16, v16, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
index 5c5542619b6ef..91b9d2d4e3258 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
@@ -168,44 +168,86 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vmv8r.v v24, v16
+; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: csrr a4, vlenb
+; CHECK-NEXT: slli a4, a4, 4
+; CHECK-NEXT: add a4, sp, a4
+; CHECK-NEXT: addi a4, a4, 16
+; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vslidedown.vx v7, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: addi a3, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 4
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmin.vv v16, v16, v24, v0.t
+; CHECK-NEXT: vfmin.vv v24, v24, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB10_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB10_2:
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16, v0.t
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 4
+; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmin.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vfmin.vv v16, v16, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -221,44 +263,83 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a2, a1, 4
+; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; CHECK-NEXT: vmset.m v24
+; CHECK-NEXT: vmv8r.v v24, v16
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: vmset.m v8
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v24, a2
+; CHECK-NEXT: vslidedown.vx v8, v8, a2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 4
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a3, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmin.vv v16, v16, v24, v0.t
+; CHECK-NEXT: vfmin.vv v24, v24, v8, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB11_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB11_2:
; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfmin.vv v16, v24, v16
+; CHECK-NEXT: vfmin.vv v16, v16, v24
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 4
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -490,44 +571,86 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: mv a2, a1
; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a2, a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 4
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 4
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmin.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfmin.vv v24, v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB22_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: addi a1, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v8, v0
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmin.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vfmin.vv v16, v16, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -549,44 +672,83 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a2, a1, 4
+; ZVFHMIN-NEXT: add a1, a2, a1
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; ZVFHMIN-NEXT: vmset.m v24
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: vmset.m v8
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmin.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfmin.vv v24, v24, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB23_2:
; ZVFHMIN-NEXT: addi a1, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmin.vv v16, v24, v16
+; ZVFHMIN-NEXT: vfmin.vv v16, v16, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
index eb77b4b4dbac3..92127a8e2f664 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
@@ -480,44 +480,86 @@ define <vscale x 32 x half> @vfmul_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: mv a2, a1
; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a2, a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 4
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 4
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfmul.vv v24, v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB20_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB20_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: addi a1, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v8, v0
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmul.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -539,44 +581,83 @@ define <vscale x 32 x half> @vfmul_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a2, a1, 4
+; ZVFHMIN-NEXT: add a1, a2, a1
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; ZVFHMIN-NEXT: vmset.m v24
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: vmset.m v8
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfmul.vv v24, v24, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB21_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB21_2:
; ZVFHMIN-NEXT: addi a1, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmul.vv v16, v24, v16
+; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -601,16 +682,16 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: sub sp, sp, a1
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: vmv.v.x v24, a1
+; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v16, a1
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
+; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
@@ -618,12 +699,13 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmul.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2
@@ -635,6 +717,7 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v8, v7
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
@@ -672,37 +755,78 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a2, a1, 4
+; ZVFHMIN-NEXT: add a1, a2, a1
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmset.m v24
-; ZVFHMIN-NEXT: vmv.v.x v16, a1
+; ZVFHMIN-NEXT: vmset.m v16
+; ZVFHMIN-NEXT: vmv.v.x v8, a1
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2
+; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v16, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmul.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB23_2:
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0
@@ -711,7 +835,8 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
index 03de2c97e685c..5733f4345fc99 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll
@@ -1078,8 +1078,6 @@ define <vscale x 16 x double> @vfma_vv_nxv16f64(<vscale x 16 x double> %va, <vsc
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 48 * vlenb
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a1, a1, a3
@@ -1121,8 +1119,10 @@ define <vscale x 16 x double> @vfma_vv_nxv16f64(<vscale x 16 x double> %va, <vsc
; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: and a0, a7, a6
+; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a2, a2, a3
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
index 5f372772b289d..6213a190e5c12 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
@@ -709,11 +709,11 @@ define <vscale x 8 x double> @vfneg_vv_nxv8f64_unmasked(<vscale x 8 x double> %v
define <vscale x 16 x double> @vfneg_vv_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfneg_vv_nxv16f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
index 458795db7965d..622fbaade9e95 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
@@ -86,11 +86,11 @@ define <vscale x 7 x double> @vfpext_nxv7f32_nxv7f64(<vscale x 7 x float> %a, <v
define <vscale x 32 x float> @vfpext_nxv32f16_nxv32f32(<vscale x 32 x half> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vfpext_nxv32f16_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
index 7127d10e67dbc..14753384b6460 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
@@ -462,11 +462,11 @@ define <vscale x 2 x i64> @vfptosi_nxv2i64_nxv2f64_unmasked(<vscale x 2 x double
define <vscale x 32 x i16> @vfptosi_nxv32i16_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptosi_nxv32i16_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2
@@ -490,11 +490,11 @@ define <vscale x 32 x i16> @vfptosi_nxv32i16_nxv32f32(<vscale x 32 x float> %va,
define <vscale x 32 x i32> @vfptosi_nxv32i32_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptosi_nxv32i32_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
index 07b58ed057508..5073a806cc2a5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
@@ -462,11 +462,11 @@ define <vscale x 2 x i64> @vfptoui_nxv2i64_nxv2f64_unmasked(<vscale x 2 x double
define <vscale x 32 x i16> @vfptoui_nxv32i16_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptoui_nxv32i16_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2
@@ -490,11 +490,11 @@ define <vscale x 32 x i16> @vfptoui_nxv32i16_nxv32f32(<vscale x 32 x float> %va,
define <vscale x 32 x i32> @vfptoui_nxv32i32_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptoui_nxv32i32_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
index 4177672b3a306..475707f27d7e9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
@@ -86,11 +86,11 @@ define <vscale x 7 x float> @vfptrunc_nxv7f32_nxv7f64(<vscale x 7 x double> %a,
define <vscale x 16 x float> @vfptrunc_nxv16f32_nxv16f64(<vscale x 16 x double> %a, <vscale x 16 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vfptrunc_nxv16f32_nxv16f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
@@ -119,8 +119,6 @@ define <vscale x 32 x float> @vfptrunc_nxv32f32_nxv32f64(<vscale x 32 x double>
; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
@@ -144,10 +142,13 @@ define <vscale x 32 x float> @vfptrunc_nxv32f32_nxv32f64(<vscale x 32 x double>
; CHECK-NEXT: and a4, a7, a4
; CHECK-NEXT: srli a7, a1, 2
; CHECK-NEXT: vl8re64.v v8, (a6)
-; CHECK-NEXT: vslidedown.vx v24, v0, a7
+; CHECK-NEXT: vsetvli a6, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v25, v0, a7
+; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v6, v0, a5
-; CHECK-NEXT: vslidedown.vx v0, v24, a5
+; CHECK-NEXT: vmv1r.v v24, v25
+; CHECK-NEXT: vslidedown.vx v0, v25, a5
; CHECK-NEXT: bltu a0, a1, .LBB8_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -165,9 +166,9 @@ define <vscale x 32 x float> @vfptrunc_nxv32f32_nxv32f64(<vscale x 32 x double>
; CHECK-NEXT: sltu a3, a2, a0
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a0, a3, a0
-; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: addi a3, sp, 16
; CHECK-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a2, a1, .LBB8_6
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
index 451b13edb794e..63651bd3955bb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
@@ -155,33 +155,33 @@ define <vscale x 16 x bfloat> @vfsqrt_vv_nxv16bf16_unmasked(<vscale x 16 x bfloa
define <vscale x 32 x bfloat> @vfsqrt_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfsqrt_vv_nxv32bf16:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: sltu a4, a0, a3
; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfsqrt.v v24, v24, v0.t
+; CHECK-NEXT: vfsqrt.v v16, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB10_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB10_2:
-; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfsqrt.v v24, v24, v0.t
+; CHECK-NEXT: vfsqrt.v v16, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v8, v24, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 32 x bfloat> @llvm.vp.sqrt.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x bfloat> %v
@@ -198,9 +198,9 @@ define <vscale x 32 x bfloat> @vfsqrt_vv_nxv32bf16_unmasked(<vscale x 32 x bfloa
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: sltu a4, a0, a3
; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v16, a2
; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v16, a2
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -431,33 +431,33 @@ define <vscale x 32 x half> @vfsqrt_vv_nxv32f16(<vscale x 32 x half> %va, <vscal
;
; ZVFHMIN-LABEL: vfsqrt_vv_nxv32f16:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: sltu a4, a0, a3
; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
; ZVFHMIN-NEXT: and a3, a4, a3
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vmv1r.v v24, v0
+; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfsqrt.v v24, v24, v0.t
+; ZVFHMIN-NEXT: vfsqrt.v v16, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB22_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vmv1r.v v0, v24
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfsqrt.v v24, v24, v0.t
+; ZVFHMIN-NEXT: vfsqrt.v v16, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: ret
%v = call <vscale x 32 x half> @llvm.vp.sqrt.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x half> %v
@@ -480,9 +480,9 @@ define <vscale x 32 x half> @vfsqrt_vv_nxv32f16_unmasked(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: sltu a4, a0, a3
; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v16, a2
; ZVFHMIN-NEXT: and a3, a4, a3
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v0, v16, a2
; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -709,11 +709,11 @@ define <vscale x 8 x double> @vfsqrt_vv_nxv8f64_unmasked(<vscale x 8 x double> %
define <vscale x 16 x double> @vfsqrt_vv_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfsqrt_vv_nxv16f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
index 6637aced3cdac..54d42930ed724 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
@@ -358,44 +358,86 @@ define <vscale x 32 x bfloat> @vfsub_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vmv8r.v v24, v16
+; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: csrr a4, vlenb
+; CHECK-NEXT: slli a4, a4, 4
+; CHECK-NEXT: add a4, sp, a4
+; CHECK-NEXT: addi a4, a4, 16
+; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vslidedown.vx v7, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: addi a3, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 4
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfsub.vv v16, v16, v24, v0.t
+; CHECK-NEXT: vfsub.vv v24, v24, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB20_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB20_2:
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16, v0.t
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 4
+; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8, v0.t
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfsub.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vfsub.vv v16, v16, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -411,44 +453,83 @@ define <vscale x 32 x bfloat> @vfsub_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a2, a1, 4
+; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; CHECK-NEXT: vmset.m v24
+; CHECK-NEXT: vmv8r.v v24, v16
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: vmset.m v8
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v24, a2
+; CHECK-NEXT: vslidedown.vx v8, v8, a2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 4
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a3, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfsub.vv v16, v16, v24, v0.t
+; CHECK-NEXT: vfsub.vv v24, v24, v8, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
+; CHECK-NEXT: vfncvtbf16.f.f.w v12, v24, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB21_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB21_2:
; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfsub.vv v16, v24, v16
+; CHECK-NEXT: vfsub.vv v16, v16, v24
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 4
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -467,16 +548,16 @@ define <vscale x 32 x bfloat> @vfsub_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: fmv.x.h a1, fa0
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: vmv.v.x v24, a1
+; CHECK-NEXT: vsetvli a3, zero, e16, m8, ta, ma
+; CHECK-NEXT: vmv.v.x v16, a1
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: vslidedown.vx v6, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
@@ -484,12 +565,13 @@ define <vscale x 32 x bfloat> @vfsub_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; CHECK-NEXT: slli a3, a3, 3
; CHECK-NEXT: add a3, sp, a3
; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v28, v0.t
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vfsub.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vfsub.vv v16, v16, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB22_2
@@ -501,6 +583,7 @@ define <vscale x 32 x bfloat> @vfsub_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8, v0.t
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v8, v7
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
@@ -532,37 +615,78 @@ define <vscale x 32 x bfloat> @vfsub_vf_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a2, a1, 4
+; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: fmv.x.h a1, fa0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: vsetvli a3, zero, e16, m8, ta, ma
-; CHECK-NEXT: vmset.m v24
-; CHECK-NEXT: vmv.v.x v16, a1
+; CHECK-NEXT: vmset.m v16
+; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v24, a2
+; CHECK-NEXT: vslidedown.vx v16, v16, a2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs1r.v v16, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 4
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; CHECK-NEXT: addi a3, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfsub.vv v16, v16, v24, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB23_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB23_2:
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v0
@@ -571,7 +695,8 @@ define <vscale x 32 x bfloat> @vfsub_vf_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 4
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -1055,44 +1180,86 @@ define <vscale x 32 x half> @vfsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: mv a2, a1
; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a2, a2, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 4
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a3, a2, 4
+; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfsub.vv v24, v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB44_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB44_2:
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: addi a1, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v8, v0
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfsub.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -1114,44 +1281,83 @@ define <vscale x 32 x half> @vfsub_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a2, a1, 4
+; ZVFHMIN-NEXT: add a1, a2, a1
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; ZVFHMIN-NEXT: vmset.m v24
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: vmset.m v8
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: vfsub.vv v24, v24, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB45_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB45_2:
; ZVFHMIN-NEXT: addi a1, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfsub.vv v16, v24, v16
+; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -1176,16 +1382,16 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: sub sp, sp, a1
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: vmv.v.x v24, a1
+; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v16, a1
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
+; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
@@ -1193,12 +1399,13 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfsub.vv v16, v24, v16, v0.t
+; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB46_2
@@ -1210,6 +1417,7 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v8, v7
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
@@ -1247,37 +1455,78 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a2, a1, 4
+; ZVFHMIN-NEXT: add a1, a2, a1
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x11, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 17 * vlenb
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: vsetvli a3, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmset.m v24
-; ZVFHMIN-NEXT: vmv.v.x v16, a1
+; ZVFHMIN-NEXT: vmset.m v16
+; ZVFHMIN-NEXT: vmv.v.x v8, a1
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2
+; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a2
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs1r.v v16, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a3, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfsub.vv v16, v16, v24, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: bltu a0, a1, .LBB47_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
; ZVFHMIN-NEXT: .LBB47_2:
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0
@@ -1286,7 +1535,8 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a1, a0, 4
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
index f5f87570f6cad..e107093580b8a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
@@ -1966,9 +1966,9 @@ define <vscale x 1 x i32> @vmand_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b,
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vmand.mm v8, v0, v8
; CHECK-NEXT: vmand.mm v0, v0, v8
-; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
-; CHECK-NEXT: vadd.vv v8, v9, v9, v0.t
+; CHECK-NEXT: vadd.vv v9, v9, v9, v0.t
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
@@ -1982,9 +1982,9 @@ define <vscale x 1 x i32> @vmnand_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b,
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vmnand.mm v8, v0, v8
; CHECK-NEXT: vmand.mm v0, v0, v8
-; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
-; CHECK-NEXT: vadd.vv v8, v9, v9, v0.t
+; CHECK-NEXT: vadd.vv v9, v9, v9, v0.t
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
@@ -1998,9 +1998,9 @@ define <vscale x 1 x i32> @vmandn_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b,
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vmandn.mm v8, v0, v8
; CHECK-NEXT: vmand.mm v0, v0, v8
-; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
-; CHECK-NEXT: vadd.vv v8, v9, v9, v0.t
+; CHECK-NEXT: vadd.vv v9, v9, v9, v0.t
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmandn.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
@@ -2014,9 +2014,9 @@ define <vscale x 1 x i32> @vmxor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b,
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vmxor.mm v8, v0, v8
; CHECK-NEXT: vmand.mm v0, v0, v8
-; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
-; CHECK-NEXT: vadd.vv v8, v9, v9, v0.t
+; CHECK-NEXT: vadd.vv v9, v9, v9, v0.t
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
@@ -2030,9 +2030,9 @@ define <vscale x 1 x i32> @vmor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vmor.mm v8, v0, v8
; CHECK-NEXT: vmand.mm v0, v0, v8
-; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
-; CHECK-NEXT: vadd.vv v8, v9, v9, v0.t
+; CHECK-NEXT: vadd.vv v9, v9, v9, v0.t
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
@@ -2047,9 +2047,9 @@ define <vscale x 1 x i32> @vmnor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b,
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vmnor.mm v8, v0, v8
; CHECK-NEXT: vmand.mm v0, v0, v8
-; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
-; CHECK-NEXT: vadd.vv v8, v9, v9, v0.t
+; CHECK-NEXT: vadd.vv v9, v9, v9, v0.t
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
@@ -2063,9 +2063,9 @@ define <vscale x 1 x i32> @vmorn_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b,
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vmorn.mm v8, v0, v8
; CHECK-NEXT: vmand.mm v0, v0, v8
-; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
-; CHECK-NEXT: vadd.vv v8, v9, v9, v0.t
+; CHECK-NEXT: vadd.vv v9, v9, v9, v0.t
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmorn.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
@@ -2079,9 +2079,9 @@ define <vscale x 1 x i32> @vmxnor_mm(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b,
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vmxnor.mm v8, v0, v8
; CHECK-NEXT: vmand.mm v0, v0, v8
-; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, tu, mu
-; CHECK-NEXT: vadd.vv v8, v9, v9, v0.t
+; CHECK-NEXT: vadd.vv v9, v9, v9, v0.t
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%1 = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, iXLen -1)
%2 = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %1, iXLen %vl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
index 3cf464247250a..7944afbbbb892 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
@@ -391,7 +391,7 @@ define <vscale x 128 x i8> @vmax_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <vs
; CHECK-LABEL: vmax_vx_nxv128i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
@@ -405,7 +405,7 @@ define <vscale x 128 x i8> @vmax_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <vs
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB34_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vmax.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
@@ -928,11 +928,11 @@ define <vscale x 16 x i32> @vmax_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i
define <vscale x 32 x i32> @vmax_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vmax_vx_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: srli a3, a2, 2
; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: sltu a4, a1, a3
@@ -1000,11 +1000,11 @@ define <vscale x 32 x i32> @vmax_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i3
;
; RV64-LABEL: vmax_vx_nxv32i32_evl_nx8:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: srli a3, a1, 2
; RV64-NEXT: slli a2, a1, 1
+; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: sub a3, a1, a2
; RV64-NEXT: sltu a4, a1, a3
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
index e755d099df4a8..0a3190f84c748 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
@@ -390,7 +390,7 @@ define <vscale x 128 x i8> @vmaxu_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <v
; CHECK-LABEL: vmaxu_vx_nxv128i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
@@ -404,7 +404,7 @@ define <vscale x 128 x i8> @vmaxu_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <v
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB34_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vmaxu.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
@@ -927,11 +927,11 @@ define <vscale x 16 x i32> @vmaxu_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vmaxu_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vmaxu_vx_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: srli a3, a2, 2
; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: sltu a4, a1, a3
@@ -999,11 +999,11 @@ define <vscale x 32 x i32> @vmaxu_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i
;
; RV64-LABEL: vmaxu_vx_nxv32i32_evl_nx8:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: srli a3, a1, 2
; RV64-NEXT: slli a2, a1, 1
+; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: sub a3, a1, a2
; RV64-NEXT: sltu a4, a1, a3
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
index 961f63cbfbc95..ef94044613c6a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
@@ -391,7 +391,7 @@ define <vscale x 128 x i8> @vmin_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <vs
; CHECK-LABEL: vmin_vx_nxv128i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
@@ -405,7 +405,7 @@ define <vscale x 128 x i8> @vmin_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <vs
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB34_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
@@ -928,11 +928,11 @@ define <vscale x 16 x i32> @vmin_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i
define <vscale x 32 x i32> @vmin_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vmin_vx_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: srli a3, a2, 2
; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: sltu a4, a1, a3
@@ -1000,11 +1000,11 @@ define <vscale x 32 x i32> @vmin_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i3
;
; RV64-LABEL: vmin_vx_nxv32i32_evl_nx8:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: srli a3, a1, 2
; RV64-NEXT: slli a2, a1, 1
+; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: sub a3, a1, a2
; RV64-NEXT: sltu a4, a1, a3
diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
index 631799d24e14c..40c2375849548 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
@@ -390,7 +390,7 @@ define <vscale x 128 x i8> @vminu_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <v
; CHECK-LABEL: vminu_vx_nxv128i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
@@ -404,7 +404,7 @@ define <vscale x 128 x i8> @vminu_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <v
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB34_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
@@ -927,11 +927,11 @@ define <vscale x 16 x i32> @vminu_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vminu_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vminu_vx_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: srli a3, a2, 2
; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: sltu a4, a1, a3
@@ -999,11 +999,11 @@ define <vscale x 32 x i32> @vminu_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i
;
; RV64-LABEL: vminu_vx_nxv32i32_evl_nx8:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: srli a3, a1, 2
; RV64-NEXT: slli a2, a1, 1
+; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: sub a3, a1, a2
; RV64-NEXT: sltu a4, a1, a3
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmseq.ll b/llvm/test/CodeGen/RISCV/rvv/vmseq.ll
index c87010b144696..4dadaaec903f4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmseq.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmseq.ll
@@ -1328,11 +1328,11 @@ define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vmv1r.v v11, v0
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmseq.vv v11, v8, v12, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmseq.vv v12, v8, v14, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1390,11 +1390,11 @@ define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vmv1r.v v13, v0
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmseq.vv v13, v8, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmseq.vv v16, v8, v20, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsge.ll b/llvm/test/CodeGen/RISCV/rvv/vmsge.ll
index 44cccb7a3c321..987271cf9e3a6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsge.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsge.ll
@@ -1383,11 +1383,11 @@ define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vmv1r.v v11, v0
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsle.vv v11, v12, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmsle.vv v12, v14, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1446,11 +1446,11 @@ define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vmv1r.v v13, v0
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsle.vv v13, v16, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmsle.vv v16, v20, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
index 7a22dff27c44c..f4f4e884e0cdb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
@@ -1345,11 +1345,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vmv1r.v v11, v0
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsleu.vv v11, v12, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmsleu.vv v12, v14, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1408,11 +1408,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vmv1r.v v13, v0
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsleu.vv v13, v16, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmsleu.vv v16, v20, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
index f7b5cad0c8ed9..23d117a02505b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
@@ -1328,11 +1328,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vmv1r.v v11, v0
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmslt.vv v11, v12, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmslt.vv v12, v14, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1390,11 +1390,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vmv1r.v v13, v0
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmslt.vv v13, v16, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmslt.vv v16, v20, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
index 2f79b1ca2b93e..f546196038252 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
@@ -1328,11 +1328,11 @@ define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vmv1r.v v11, v0
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsltu.vv v11, v12, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmsltu.vv v12, v14, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1390,11 +1390,11 @@ define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vmv1r.v v13, v0
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsltu.vv v13, v16, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmsltu.vv v16, v20, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsle.ll b/llvm/test/CodeGen/RISCV/rvv/vmsle.ll
index ec60f75bb206d..02c6e644df646 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsle.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsle.ll
@@ -1328,11 +1328,11 @@ define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vmv1r.v v11, v0
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsle.vv v11, v8, v12, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmsle.vv v12, v8, v14, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1390,11 +1390,11 @@ define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vmv1r.v v13, v0
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsle.vv v13, v8, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmsle.vv v16, v8, v20, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
index 1c57fc9002857..76989d2994749 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
@@ -1328,11 +1328,11 @@ define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vmv1r.v v11, v0
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsleu.vv v11, v8, v12, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmsleu.vv v12, v8, v14, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1390,11 +1390,11 @@ define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vmv1r.v v13, v0
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsleu.vv v13, v8, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmsleu.vv v16, v8, v20, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmslt.ll b/llvm/test/CodeGen/RISCV/rvv/vmslt.ll
index e528d07dac51f..6f6a07e6c02bc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmslt.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmslt.ll
@@ -1328,11 +1328,11 @@ define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vmv1r.v v11, v0
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmslt.vv v11, v8, v12, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmslt.vv v12, v8, v14, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1390,11 +1390,11 @@ define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vmv1r.v v13, v0
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmslt.vv v13, v8, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmslt.vv v16, v8, v20, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
index 8a909d0c03715..82ad07fc5b9ab 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
@@ -1328,11 +1328,11 @@ define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vmv1r.v v11, v0
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsltu.vv v11, v8, v12, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmsltu.vv v12, v8, v14, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1390,11 +1390,11 @@ define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vmv1r.v v13, v0
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsltu.vv v13, v8, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmsltu.vv v16, v8, v20, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsne.ll b/llvm/test/CodeGen/RISCV/rvv/vmsne.ll
index 7e27d98cf9161..a485fdf4e505f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsne.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsne.ll
@@ -1328,11 +1328,11 @@ define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v12, (a0), zero
-; RV32-NEXT: vmv1r.v v11, v0
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsne.vv v11, v8, v12, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmsne.vv v12, v8, v14, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1390,11 +1390,11 @@ define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v16, (a0), zero
-; RV32-NEXT: vmv1r.v v13, v0
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsne.vv v13, v8, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmsne.vv v16, v8, v20, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
index 4b8effb70586e..3e81dcb29e559 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
@@ -7,15 +7,15 @@ define <2 x i1> @test_vp_reverse_v2i1_masked(<2 x i1> %src, <2 x i1> %mask, i32
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
+; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vid.v v10, v0.t
-; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t
+; CHECK-NEXT: vid.v v9, v0.t
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vrsub.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmsne.vi v0, v11, 0, v0.t
+; CHECK-NEXT: vrgatherei16.vv v10, v11, v9, v0.t
+; CHECK-NEXT: vmsne.vi v0, v10, 0, v0.t
; CHECK-NEXT: ret
%dst = call <2 x i1> @llvm.experimental.vp.reverse.v2i1(<2 x i1> %src, <2 x i1> %mask, i32 %evl)
ret <2 x i1> %dst
@@ -46,15 +46,15 @@ define <4 x i1> @test_vp_reverse_v4i1_masked(<4 x i1> %src, <4 x i1> %mask, i32
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
+; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vid.v v10, v0.t
-; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t
+; CHECK-NEXT: vid.v v9, v0.t
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vrsub.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmsne.vi v0, v11, 0, v0.t
+; CHECK-NEXT: vrgatherei16.vv v10, v11, v9, v0.t
+; CHECK-NEXT: vmsne.vi v0, v10, 0, v0.t
; CHECK-NEXT: ret
%dst = call <4 x i1> @llvm.experimental.vp.reverse.v4i1(<4 x i1> %src, <4 x i1> %mask, i32 %evl)
ret <4 x i1> %dst
@@ -85,15 +85,15 @@ define <8 x i1> @test_vp_reverse_v8i1_masked(<8 x i1> %src, <8 x i1> %mask, i32
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
+; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vid.v v10, v0.t
-; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t
+; CHECK-NEXT: vid.v v9, v0.t
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vrsub.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmsne.vi v0, v11, 0, v0.t
+; CHECK-NEXT: vrgatherei16.vv v10, v11, v9, v0.t
+; CHECK-NEXT: vmsne.vi v0, v10, 0, v0.t
; CHECK-NEXT: ret
%dst = call <8 x i1> @llvm.experimental.vp.reverse.v8i1(<8 x i1> %src, <8 x i1> %mask, i32 %evl)
ret <8 x i1> %dst
@@ -124,15 +124,15 @@ define <16 x i1> @test_vp_reverse_v16i1_masked(<16 x i1> %src, <16 x i1> %mask,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
+; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vid.v v10, v0.t
-; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t
+; CHECK-NEXT: vid.v v8, v0.t
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v12, v9, v10, v0.t
-; CHECK-NEXT: vmsne.vi v0, v12, 0, v0.t
+; CHECK-NEXT: vrgatherei16.vv v11, v10, v8, v0.t
+; CHECK-NEXT: vmsne.vi v0, v11, 0, v0.t
; CHECK-NEXT: ret
%dst = call <16 x i1> @llvm.experimental.vp.reverse.v16i1(<16 x i1> %src, <16 x i1> %mask, i32 %evl)
ret <16 x i1> %dst
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
index bb15a2241faa6..510a18d8b756f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
@@ -6,15 +6,15 @@ define <vscale x 1 x i1> @test_vp_reverse_nxv1i1_masked(<vscale x 1 x i1> %src,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
+; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vid.v v10, v0.t
-; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t
+; CHECK-NEXT: vid.v v9, v0.t
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vrsub.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmsne.vi v0, v11, 0, v0.t
+; CHECK-NEXT: vrgatherei16.vv v10, v11, v9, v0.t
+; CHECK-NEXT: vmsne.vi v0, v10, 0, v0.t
; CHECK-NEXT: ret
%dst = call <vscale x 1 x i1> @llvm.experimental.vp.reverse.nxv1i1(<vscale x 1 x i1> %src, <vscale x 1 x i1> %mask, i32 %evl)
ret <vscale x 1 x i1> %dst
@@ -45,15 +45,15 @@ define <vscale x 2 x i1> @test_vp_reverse_nxv2i1_masked(<vscale x 2 x i1> %src,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
+; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vid.v v10, v0.t
-; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t
+; CHECK-NEXT: vid.v v9, v0.t
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vrsub.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmsne.vi v0, v11, 0, v0.t
+; CHECK-NEXT: vrgatherei16.vv v10, v11, v9, v0.t
+; CHECK-NEXT: vmsne.vi v0, v10, 0, v0.t
; CHECK-NEXT: ret
%dst = call <vscale x 2 x i1> @llvm.experimental.vp.reverse.nxv2i1(<vscale x 2 x i1> %src, <vscale x 2 x i1> %mask, i32 %evl)
ret <vscale x 2 x i1> %dst
@@ -84,15 +84,15 @@ define <vscale x 4 x i1> @test_vp_reverse_nxv4i1_masked(<vscale x 4 x i1> %src,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
+; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT: vid.v v10, v0.t
-; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t
+; CHECK-NEXT: vid.v v9, v0.t
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vrsub.vx v9, v9, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vmsne.vi v0, v11, 0, v0.t
+; CHECK-NEXT: vrgatherei16.vv v10, v11, v9, v0.t
+; CHECK-NEXT: vmsne.vi v0, v10, 0, v0.t
; CHECK-NEXT: ret
%dst = call <vscale x 4 x i1> @llvm.experimental.vp.reverse.nxv4i1(<vscale x 4 x i1> %src, <vscale x 4 x i1> %mask, i32 %evl)
ret <vscale x 4 x i1> %dst
@@ -123,15 +123,15 @@ define <vscale x 8 x i1> @test_vp_reverse_nxv8i1_masked(<vscale x 8 x i1> %src,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
+; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vid.v v10, v0.t
-; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t
+; CHECK-NEXT: vid.v v8, v0.t
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v12, v9, v10, v0.t
-; CHECK-NEXT: vmsne.vi v0, v12, 0, v0.t
+; CHECK-NEXT: vrgatherei16.vv v11, v10, v8, v0.t
+; CHECK-NEXT: vmsne.vi v0, v11, 0, v0.t
; CHECK-NEXT: ret
%dst = call <vscale x 8 x i1> @llvm.experimental.vp.reverse.nxv8i1(<vscale x 8 x i1> %src, <vscale x 8 x i1> %mask, i32 %evl)
ret <vscale x 8 x i1> %dst
@@ -162,15 +162,15 @@ define <vscale x 16 x i1> @test_vp_reverse_nxv16i1_masked(<vscale x 16 x i1> %sr
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
+; CHECK-NEXT: vmerge.vim v12, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT: vid.v v12, v0.t
-; CHECK-NEXT: vrsub.vx v12, v12, a0, v0.t
+; CHECK-NEXT: vid.v v8, v0.t
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v16, v10, v12, v0.t
-; CHECK-NEXT: vmsne.vi v8, v16, 0, v0.t
+; CHECK-NEXT: vrgatherei16.vv v14, v12, v8, v0.t
+; CHECK-NEXT: vmsne.vi v8, v14, 0, v0.t
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
%dst = call <vscale x 16 x i1> @llvm.experimental.vp.reverse.nxv16i1(<vscale x 16 x i1> %src, <vscale x 16 x i1> %mask, i32 %evl)
@@ -202,15 +202,15 @@ define <vscale x 32 x i1> @test_vp_reverse_nxv32i1_masked(<vscale x 32 x i1> %sr
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
+; CHECK-NEXT: vmerge.vim v16, v12, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
-; CHECK-NEXT: vid.v v16, v0.t
-; CHECK-NEXT: vrsub.vx v16, v16, a0, v0.t
+; CHECK-NEXT: vid.v v8, v0.t
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v24, v12, v16, v0.t
-; CHECK-NEXT: vmsne.vi v8, v24, 0, v0.t
+; CHECK-NEXT: vrgatherei16.vv v20, v16, v8, v0.t
+; CHECK-NEXT: vmsne.vi v8, v20, 0, v0.t
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret
%dst = call <vscale x 32 x i1> @llvm.experimental.vp.reverse.nxv32i1(<vscale x 32 x i1> %src, <vscale x 32 x i1> %mask, i32 %evl)
@@ -241,31 +241,32 @@ define <vscale x 64 x i1> @test_vp_reverse_nxv64i1_masked(<vscale x 64 x i1> %sr
; CHECK-LABEL: test_vp_reverse_nxv64i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmv1r.v v26, v8
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, ma
-; CHECK-NEXT: vid.v v10
+; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: addi a2, a1, -1
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: vsetvli a3, zero, e16, m2, ta, ma
-; CHECK-NEXT: vrsub.vx v10, v10, a2
+; CHECK-NEXT: vrsub.vx v24, v16, a2
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; CHECK-NEXT: vrgatherei16.vv v31, v16, v10
-; CHECK-NEXT: vrgatherei16.vv v30, v17, v10
-; CHECK-NEXT: vrgatherei16.vv v29, v18, v10
-; CHECK-NEXT: vrgatherei16.vv v28, v19, v10
-; CHECK-NEXT: vrgatherei16.vv v27, v20, v10
-; CHECK-NEXT: vrgatherei16.vv v26, v21, v10
-; CHECK-NEXT: vrgatherei16.vv v25, v22, v10
-; CHECK-NEXT: vrgatherei16.vv v24, v23, v10
+; CHECK-NEXT: vrgatherei16.vv v23, v8, v24
+; CHECK-NEXT: vrgatherei16.vv v22, v9, v24
+; CHECK-NEXT: vrgatherei16.vv v21, v10, v24
+; CHECK-NEXT: vrgatherei16.vv v20, v11, v24
+; CHECK-NEXT: vrgatherei16.vv v19, v12, v24
+; CHECK-NEXT: vrgatherei16.vv v18, v13, v24
+; CHECK-NEXT: vrgatherei16.vv v17, v14, v24
+; CHECK-NEXT: vrgatherei16.vv v16, v15, v24
; CHECK-NEXT: sub a1, a1, a0
-; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vslidedown.vx v16, v24, a1, v0.t
-; CHECK-NEXT: vmsne.vi v8, v16, 0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vslidedown.vx v8, v16, a1, v0.t
+; CHECK-NEXT: vmsne.vi v16, v8, 0, v0.t
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: ret
%dst = call <vscale x 64 x i1> @llvm.experimental.vp.reverse.nxv64i1(<vscale x 64 x i1> %src, <vscale x 64 x i1> %mask, i32 %evl)
ret <vscale x 64 x i1> %dst
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
index aa9854f7681f1..d2e6b0e6ae526 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
@@ -8,14 +8,14 @@ define <2 x i1> @test_vp_splice_v2i1(<2 x i1> %va, <2 x i1> %vb, i32 zeroext %ev
; NOVLDEP-LABEL: test_vp_splice_v2i1:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v9, v9, 1
; NOVLDEP-NEXT: addi a0, a0, -1
@@ -26,14 +26,14 @@ define <2 x i1> @test_vp_splice_v2i1(<2 x i1> %va, <2 x i1> %vb, i32 zeroext %ev
; VLDEP-LABEL: test_vp_splice_v2i1:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLDEP-NEXT: vslidedown.vi v9, v9, 1
@@ -50,14 +50,14 @@ define <2 x i1> @test_vp_splice_v2i1_negative_offset(<2 x i1> %va, <2 x i1> %vb,
; NOVLDEP-LABEL: test_vp_splice_v2i1_negative_offset:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; NOVLDEP-NEXT: vslidedown.vx v9, v9, a0
@@ -68,14 +68,14 @@ define <2 x i1> @test_vp_splice_v2i1_negative_offset(<2 x i1> %va, <2 x i1> %vb,
; VLDEP-LABEL: test_vp_splice_v2i1_negative_offset:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; VLDEP-NEXT: vslidedown.vx v9, v9, a0
@@ -92,43 +92,43 @@ define <2 x i1> @test_vp_splice_v2i1_masked(<2 x i1> %va, <2 x i1> %vb, <2 x i1>
; NOVLDEP-LABEL: test_vp_splice_v2i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v11, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v10, v11, 1, v0
-; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vslidedown.vi v10, v10, 1, v0.t
+; NOVLDEP-NEXT: vslidedown.vi v9, v10, 1, v0.t
+; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; NOVLDEP-NEXT: vslideup.vx v10, v8, a0, v0.t
+; NOVLDEP-NEXT: vslideup.vx v9, v8, a0, v0.t
; NOVLDEP-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmsne.vi v0, v10, 0, v0.t
+; NOVLDEP-NEXT: vmsne.vi v0, v9, 0, v0.t
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: test_vp_splice_v2i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv.v.i v11, 0
-; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v10, v11, 1, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; VLDEP-NEXT: vslidedown.vi v10, v10, 1, v0.t
+; VLDEP-NEXT: vslidedown.vi v9, v10, 1, v0.t
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; VLDEP-NEXT: vslideup.vx v10, v8, a0, v0.t
+; VLDEP-NEXT: vslideup.vx v9, v8, a0, v0.t
; VLDEP-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; VLDEP-NEXT: vmsne.vi v0, v10, 0, v0.t
+; VLDEP-NEXT: vmsne.vi v0, v9, 0, v0.t
; VLDEP-NEXT: ret
%v = call <2 x i1> @llvm.experimental.vp.splice.v2i1(<2 x i1> %va, <2 x i1> %vb, i32 1, <2 x i1> %mask, i32 %evla, i32 %evlb)
ret <2 x i1> %v
@@ -138,14 +138,14 @@ define <4 x i1> @test_vp_splice_v4i1(<4 x i1> %va, <4 x i1> %vb, i32 zeroext %ev
; NOVLDEP-LABEL: test_vp_splice_v4i1:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v9, v9, 3
; NOVLDEP-NEXT: addi a0, a0, -3
@@ -156,14 +156,14 @@ define <4 x i1> @test_vp_splice_v4i1(<4 x i1> %va, <4 x i1> %vb, i32 zeroext %ev
; VLDEP-LABEL: test_vp_splice_v4i1:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; VLDEP-NEXT: addi a0, a0, -3
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; VLDEP-NEXT: vslidedown.vi v9, v9, 3
@@ -180,14 +180,14 @@ define <4 x i1> @test_vp_splice_v4i1_negative_offset(<4 x i1> %va, <4 x i1> %vb,
; NOVLDEP-LABEL: test_vp_splice_v4i1_negative_offset:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; NOVLDEP-NEXT: addi a0, a0, -3
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; NOVLDEP-NEXT: vslidedown.vx v9, v9, a0
@@ -198,14 +198,14 @@ define <4 x i1> @test_vp_splice_v4i1_negative_offset(<4 x i1> %va, <4 x i1> %vb,
; VLDEP-LABEL: test_vp_splice_v4i1_negative_offset:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; VLDEP-NEXT: addi a0, a0, -3
; VLDEP-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
; VLDEP-NEXT: vslidedown.vx v9, v9, a0
@@ -222,43 +222,43 @@ define <4 x i1> @test_vp_splice_v4i1_masked(<4 x i1> %va, <4 x i1> %vb, <4 x i1>
; NOVLDEP-LABEL: test_vp_splice_v4i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v11, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v10, v11, 1, v0
-; NOVLDEP-NEXT: addi a0, a0, -3
+; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vslidedown.vi v10, v10, 3, v0.t
+; NOVLDEP-NEXT: vslidedown.vi v9, v10, 3, v0.t
+; NOVLDEP-NEXT: addi a0, a0, -3
; NOVLDEP-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; NOVLDEP-NEXT: vslideup.vx v10, v8, a0, v0.t
+; NOVLDEP-NEXT: vslideup.vx v9, v8, a0, v0.t
; NOVLDEP-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmsne.vi v0, v10, 0, v0.t
+; NOVLDEP-NEXT: vmsne.vi v0, v9, 0, v0.t
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: test_vp_splice_v4i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv.v.i v11, 0
-; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v10, v11, 1, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; VLDEP-NEXT: addi a0, a0, -3
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; VLDEP-NEXT: vslidedown.vi v10, v10, 3, v0.t
+; VLDEP-NEXT: vslidedown.vi v9, v10, 3, v0.t
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; VLDEP-NEXT: vslideup.vx v10, v8, a0, v0.t
+; VLDEP-NEXT: vslideup.vx v9, v8, a0, v0.t
; VLDEP-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; VLDEP-NEXT: vmsne.vi v0, v10, 0, v0.t
+; VLDEP-NEXT: vmsne.vi v0, v9, 0, v0.t
; VLDEP-NEXT: ret
%v = call <4 x i1> @llvm.experimental.vp.splice.v4i1(<4 x i1> %va, <4 x i1> %vb, i32 3, <4 x i1> %mask, i32 %evla, i32 %evlb)
ret <4 x i1> %v
@@ -268,14 +268,14 @@ define <8 x i1> @test_vp_splice_v8i1(<8 x i1> %va, <8 x i1> %vb, i32 zeroext %ev
; NOVLDEP-LABEL: test_vp_splice_v8i1:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v9, v9, 5
; NOVLDEP-NEXT: addi a0, a0, -5
@@ -286,14 +286,14 @@ define <8 x i1> @test_vp_splice_v8i1(<8 x i1> %va, <8 x i1> %vb, i32 zeroext %ev
; VLDEP-LABEL: test_vp_splice_v8i1:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; VLDEP-NEXT: vslidedown.vi v9, v9, 5
@@ -310,14 +310,14 @@ define <8 x i1> @test_vp_splice_v8i1_negative_offset(<8 x i1> %va, <8 x i1> %vb,
; NOVLDEP-LABEL: test_vp_splice_v8i1_negative_offset:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; NOVLDEP-NEXT: addi a0, a0, -5
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; NOVLDEP-NEXT: vslidedown.vx v9, v9, a0
@@ -328,14 +328,14 @@ define <8 x i1> @test_vp_splice_v8i1_negative_offset(<8 x i1> %va, <8 x i1> %vb,
; VLDEP-LABEL: test_vp_splice_v8i1_negative_offset:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vsetivli zero, 5, e8, mf2, ta, ma
; VLDEP-NEXT: vslidedown.vx v9, v9, a0
@@ -352,43 +352,43 @@ define <8 x i1> @test_vp_splice_v8i1_masked(<8 x i1> %va, <8 x i1> %vb, <8 x i1>
; NOVLDEP-LABEL: test_vp_splice_v8i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v11, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v10, v11, 1, v0
-; NOVLDEP-NEXT: addi a0, a0, -5
+; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vslidedown.vi v10, v10, 5, v0.t
+; NOVLDEP-NEXT: vslidedown.vi v9, v10, 5, v0.t
+; NOVLDEP-NEXT: addi a0, a0, -5
; NOVLDEP-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; NOVLDEP-NEXT: vslideup.vx v10, v8, a0, v0.t
+; NOVLDEP-NEXT: vslideup.vx v9, v8, a0, v0.t
; NOVLDEP-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmsne.vi v0, v10, 0, v0.t
+; NOVLDEP-NEXT: vmsne.vi v0, v9, 0, v0.t
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: test_vp_splice_v8i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv.v.i v11, 0
-; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v10, v11, 1, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; VLDEP-NEXT: vslidedown.vi v10, v10, 5, v0.t
+; VLDEP-NEXT: vslidedown.vi v9, v10, 5, v0.t
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; VLDEP-NEXT: vslideup.vx v10, v8, a0, v0.t
+; VLDEP-NEXT: vslideup.vx v9, v8, a0, v0.t
; VLDEP-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; VLDEP-NEXT: vmsne.vi v0, v10, 0, v0.t
+; VLDEP-NEXT: vmsne.vi v0, v9, 0, v0.t
; VLDEP-NEXT: ret
%v = call <8 x i1> @llvm.experimental.vp.splice.v8i1(<8 x i1> %va, <8 x i1> %vb, i32 5, <8 x i1> %mask, i32 %evla, i32 %evlb)
ret <8 x i1> %v
@@ -398,14 +398,14 @@ define <16 x i1> @test_vp_splice_v16i1(<16 x i1> %va, <16 x i1> %vb, i32 zeroext
; NOVLDEP-LABEL: test_vp_splice_v16i1:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v9, v9, 5
; NOVLDEP-NEXT: addi a0, a0, -5
@@ -416,14 +416,14 @@ define <16 x i1> @test_vp_splice_v16i1(<16 x i1> %va, <16 x i1> %vb, i32 zeroext
; VLDEP-LABEL: test_vp_splice_v16i1:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; VLDEP-NEXT: vslidedown.vi v9, v9, 5
@@ -440,14 +440,14 @@ define <16 x i1> @test_vp_splice_v16i1_negative_offset(<16 x i1> %va, <16 x i1>
; NOVLDEP-LABEL: test_vp_splice_v16i1_negative_offset:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; NOVLDEP-NEXT: addi a0, a0, -5
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; NOVLDEP-NEXT: vslidedown.vx v9, v9, a0
@@ -458,14 +458,14 @@ define <16 x i1> @test_vp_splice_v16i1_negative_offset(<16 x i1> %va, <16 x i1>
; VLDEP-LABEL: test_vp_splice_v16i1_negative_offset:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vsetivli zero, 5, e8, m1, ta, ma
; VLDEP-NEXT: vslidedown.vx v9, v9, a0
@@ -482,43 +482,43 @@ define <16 x i1> @test_vp_splice_v16i1_masked(<16 x i1> %va, <16 x i1> %vb, <16
; NOVLDEP-LABEL: test_vp_splice_v16i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v11, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v10, v11, 1, v0
-; NOVLDEP-NEXT: addi a0, a0, -5
+; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; NOVLDEP-NEXT: vslidedown.vi v10, v10, 5, v0.t
+; NOVLDEP-NEXT: vslidedown.vi v9, v10, 5, v0.t
+; NOVLDEP-NEXT: addi a0, a0, -5
; NOVLDEP-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; NOVLDEP-NEXT: vslideup.vx v10, v8, a0, v0.t
+; NOVLDEP-NEXT: vslideup.vx v9, v8, a0, v0.t
; NOVLDEP-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmsne.vi v0, v10, 0, v0.t
+; NOVLDEP-NEXT: vmsne.vi v0, v9, 0, v0.t
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: test_vp_splice_v16i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; VLDEP-NEXT: vmv.v.i v11, 0
-; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v10, v11, 1, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; VLDEP-NEXT: vslidedown.vi v10, v10, 5, v0.t
+; VLDEP-NEXT: vslidedown.vi v9, v10, 5, v0.t
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; VLDEP-NEXT: vslideup.vx v10, v8, a0, v0.t
+; VLDEP-NEXT: vslideup.vx v9, v8, a0, v0.t
; VLDEP-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; VLDEP-NEXT: vmsne.vi v0, v10, 0, v0.t
+; VLDEP-NEXT: vmsne.vi v0, v9, 0, v0.t
; VLDEP-NEXT: ret
%v = call <16 x i1> @llvm.experimental.vp.splice.v16i1(<16 x i1> %va, <16 x i1> %vb, i32 5, <16 x i1> %mask, i32 %evla, i32 %evlb)
ret <16 x i1> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
index 3215b4548243c..100d03580dc0b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
@@ -6,14 +6,14 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1(<vscale x 1 x i1> %va, <vscale x
; NOVLDEP-LABEL: test_vp_splice_nxv1i1:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v9, v9, 1
; NOVLDEP-NEXT: addi a0, a0, -1
@@ -24,14 +24,14 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1(<vscale x 1 x i1> %va, <vscale x
; VLDEP-LABEL: test_vp_splice_nxv1i1:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLDEP-NEXT: vslidedown.vi v9, v9, 1
@@ -48,14 +48,14 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1_negative_offset(<vscale x 1 x i1
; NOVLDEP-LABEL: test_vp_splice_nxv1i1_negative_offset:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; NOVLDEP-NEXT: addi a0, a0, -2
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; NOVLDEP-NEXT: vslidedown.vx v9, v9, a0
@@ -66,14 +66,14 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1_negative_offset(<vscale x 1 x i1
; VLDEP-LABEL: test_vp_splice_nxv1i1_negative_offset:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; VLDEP-NEXT: addi a0, a0, -2
; VLDEP-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; VLDEP-NEXT: vslidedown.vx v9, v9, a0
@@ -90,43 +90,43 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1_masked(<vscale x 1 x i1> %va, <v
; NOVLDEP-LABEL: test_vp_splice_nxv1i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v11, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v10, v11, 1, v0
-; NOVLDEP-NEXT: addi a0, a0, -1
+; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vslidedown.vi v10, v10, 1, v0.t
+; NOVLDEP-NEXT: vslidedown.vi v9, v10, 1, v0.t
+; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
-; NOVLDEP-NEXT: vslideup.vx v10, v8, a0, v0.t
+; NOVLDEP-NEXT: vslideup.vx v9, v8, a0, v0.t
; NOVLDEP-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmsne.vi v0, v10, 0, v0.t
+; NOVLDEP-NEXT: vmsne.vi v0, v9, 0, v0.t
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: test_vp_splice_nxv1i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv.v.i v11, 0
-; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v10, v11, 1, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; VLDEP-NEXT: vslidedown.vi v10, v10, 1, v0.t
+; VLDEP-NEXT: vslidedown.vi v9, v10, 1, v0.t
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; VLDEP-NEXT: vslideup.vx v10, v8, a0, v0.t
+; VLDEP-NEXT: vslideup.vx v9, v8, a0, v0.t
; VLDEP-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; VLDEP-NEXT: vmsne.vi v0, v10, 0, v0.t
+; VLDEP-NEXT: vmsne.vi v0, v9, 0, v0.t
; VLDEP-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.experimental.vp.splice.nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, i32 1, <vscale x 1 x i1> %mask, i32 %evla, i32 %evlb)
ret <vscale x 1 x i1> %v
@@ -136,14 +136,14 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1(<vscale x 2 x i1> %va, <vscale x
; NOVLDEP-LABEL: test_vp_splice_nxv2i1:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v9, v9, 3
; NOVLDEP-NEXT: addi a0, a0, -3
@@ -154,14 +154,14 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1(<vscale x 2 x i1> %va, <vscale x
; VLDEP-LABEL: test_vp_splice_nxv2i1:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; VLDEP-NEXT: addi a0, a0, -3
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; VLDEP-NEXT: vslidedown.vi v9, v9, 3
@@ -178,14 +178,14 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1_negative_offset(<vscale x 2 x i1
; NOVLDEP-LABEL: test_vp_splice_nxv2i1_negative_offset:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; NOVLDEP-NEXT: addi a0, a0, -4
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; NOVLDEP-NEXT: vslidedown.vx v9, v9, a0
@@ -196,14 +196,14 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1_negative_offset(<vscale x 2 x i1
; VLDEP-LABEL: test_vp_splice_nxv2i1_negative_offset:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; VLDEP-NEXT: addi a0, a0, -4
; VLDEP-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; VLDEP-NEXT: vslidedown.vx v9, v9, a0
@@ -220,43 +220,43 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1_masked(<vscale x 2 x i1> %va, <v
; NOVLDEP-LABEL: test_vp_splice_nxv2i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v11, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v10, v11, 1, v0
-; NOVLDEP-NEXT: addi a0, a0, -3
+; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vslidedown.vi v10, v10, 3, v0.t
+; NOVLDEP-NEXT: vslidedown.vi v9, v10, 3, v0.t
+; NOVLDEP-NEXT: addi a0, a0, -3
; NOVLDEP-NEXT: vsetvli zero, zero, e8, mf4, ta, mu
-; NOVLDEP-NEXT: vslideup.vx v10, v8, a0, v0.t
+; NOVLDEP-NEXT: vslideup.vx v9, v8, a0, v0.t
; NOVLDEP-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmsne.vi v0, v10, 0, v0.t
+; NOVLDEP-NEXT: vmsne.vi v0, v9, 0, v0.t
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: test_vp_splice_nxv2i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv.v.i v11, 0
-; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v10, v11, 1, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; VLDEP-NEXT: addi a0, a0, -3
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; VLDEP-NEXT: vslidedown.vi v10, v10, 3, v0.t
+; VLDEP-NEXT: vslidedown.vi v9, v10, 3, v0.t
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; VLDEP-NEXT: vslideup.vx v10, v8, a0, v0.t
+; VLDEP-NEXT: vslideup.vx v9, v8, a0, v0.t
; VLDEP-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; VLDEP-NEXT: vmsne.vi v0, v10, 0, v0.t
+; VLDEP-NEXT: vmsne.vi v0, v9, 0, v0.t
; VLDEP-NEXT: ret
%v = call <vscale x 2 x i1> @llvm.experimental.vp.splice.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, i32 3, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
ret <vscale x 2 x i1> %v
@@ -266,14 +266,14 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1(<vscale x 4 x i1> %va, <vscale x
; NOVLDEP-LABEL: test_vp_splice_nxv4i1:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v9, v9, 5
; NOVLDEP-NEXT: addi a0, a0, -5
@@ -284,14 +284,14 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1(<vscale x 4 x i1> %va, <vscale x
; VLDEP-LABEL: test_vp_splice_nxv4i1:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; VLDEP-NEXT: vslidedown.vi v9, v9, 5
@@ -308,14 +308,14 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1_negative_offset(<vscale x 4 x i1
; NOVLDEP-LABEL: test_vp_splice_nxv4i1_negative_offset:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; NOVLDEP-NEXT: addi a0, a0, -5
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; NOVLDEP-NEXT: vslidedown.vx v9, v9, a0
@@ -326,14 +326,14 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1_negative_offset(<vscale x 4 x i1
; VLDEP-LABEL: test_vp_splice_nxv4i1_negative_offset:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vsetivli zero, 5, e8, mf2, ta, ma
; VLDEP-NEXT: vslidedown.vx v9, v9, a0
@@ -350,43 +350,43 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1_masked(<vscale x 4 x i1> %va, <v
; NOVLDEP-LABEL: test_vp_splice_nxv4i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v11, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v10, v11, 1, v0
-; NOVLDEP-NEXT: addi a0, a0, -5
+; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vslidedown.vi v10, v10, 5, v0.t
+; NOVLDEP-NEXT: vslidedown.vi v9, v10, 5, v0.t
+; NOVLDEP-NEXT: addi a0, a0, -5
; NOVLDEP-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
-; NOVLDEP-NEXT: vslideup.vx v10, v8, a0, v0.t
+; NOVLDEP-NEXT: vslideup.vx v9, v8, a0, v0.t
; NOVLDEP-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmsne.vi v0, v10, 0, v0.t
+; NOVLDEP-NEXT: vmsne.vi v0, v9, 0, v0.t
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: test_vp_splice_nxv4i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv.v.i v11, 0
-; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v10, v11, 1, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; VLDEP-NEXT: vslidedown.vi v10, v10, 5, v0.t
+; VLDEP-NEXT: vslidedown.vi v9, v10, 5, v0.t
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; VLDEP-NEXT: vslideup.vx v10, v8, a0, v0.t
+; VLDEP-NEXT: vslideup.vx v9, v8, a0, v0.t
; VLDEP-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; VLDEP-NEXT: vmsne.vi v0, v10, 0, v0.t
+; VLDEP-NEXT: vmsne.vi v0, v9, 0, v0.t
; VLDEP-NEXT: ret
%v = call <vscale x 4 x i1> @llvm.experimental.vp.splice.nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, i32 5, <vscale x 4 x i1> %mask, i32 %evla, i32 %evlb)
ret <vscale x 4 x i1> %v
@@ -396,14 +396,14 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1(<vscale x 8 x i1> %va, <vscale x
; NOVLDEP-LABEL: test_vp_splice_nxv8i1:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v9, v9, 5
; NOVLDEP-NEXT: addi a0, a0, -5
@@ -414,14 +414,14 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1(<vscale x 8 x i1> %va, <vscale x
; VLDEP-LABEL: test_vp_splice_nxv8i1:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; VLDEP-NEXT: vslidedown.vi v9, v9, 5
@@ -438,14 +438,14 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1_negative_offset(<vscale x 8 x i1
; NOVLDEP-LABEL: test_vp_splice_nxv8i1_negative_offset:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; NOVLDEP-NEXT: addi a0, a0, -5
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; NOVLDEP-NEXT: vslidedown.vx v9, v9, a0
@@ -456,14 +456,14 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1_negative_offset(<vscale x 8 x i1
; VLDEP-LABEL: test_vp_splice_nxv8i1_negative_offset:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v9, v9, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vsetivli zero, 5, e8, m1, ta, ma
; VLDEP-NEXT: vslidedown.vx v9, v9, a0
@@ -480,43 +480,43 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1_masked(<vscale x 8 x i1> %va, <v
; NOVLDEP-LABEL: test_vp_splice_nxv8i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v11, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v10, v11, 1, v0
-; NOVLDEP-NEXT: addi a0, a0, -5
+; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; NOVLDEP-NEXT: vslidedown.vi v10, v10, 5, v0.t
+; NOVLDEP-NEXT: vslidedown.vi v9, v10, 5, v0.t
+; NOVLDEP-NEXT: addi a0, a0, -5
; NOVLDEP-NEXT: vsetvli zero, zero, e8, m1, ta, mu
-; NOVLDEP-NEXT: vslideup.vx v10, v8, a0, v0.t
+; NOVLDEP-NEXT: vslideup.vx v9, v8, a0, v0.t
; NOVLDEP-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmsne.vi v0, v10, 0, v0.t
+; NOVLDEP-NEXT: vmsne.vi v0, v9, 0, v0.t
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: test_vp_splice_nxv8i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; VLDEP-NEXT: vmv.v.i v11, 0
-; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v10, v11, 1, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; VLDEP-NEXT: vslidedown.vi v10, v10, 5, v0.t
+; VLDEP-NEXT: vslidedown.vi v9, v10, 5, v0.t
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; VLDEP-NEXT: vslideup.vx v10, v8, a0, v0.t
+; VLDEP-NEXT: vslideup.vx v9, v8, a0, v0.t
; VLDEP-NEXT: vsetvli zero, zero, e8, m1, ta, ma
-; VLDEP-NEXT: vmsne.vi v0, v10, 0, v0.t
+; VLDEP-NEXT: vmsne.vi v0, v9, 0, v0.t
; VLDEP-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.experimental.vp.splice.nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, i32 5, <vscale x 8 x i1> %mask, i32 %evla, i32 %evlb)
ret <vscale x 8 x i1> %v
@@ -526,38 +526,38 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1(<vscale x 16 x i1> %va, <vscal
; NOVLDEP-LABEL: test_vp_splice_nxv16i1:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v12, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v12
; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
-; NOVLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v12, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5
+; NOVLDEP-NEXT: vslidedown.vi v10, v10, 5
; NOVLDEP-NEXT: addi a0, a0, -5
-; NOVLDEP-NEXT: vslideup.vx v8, v10, a0
-; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
+; NOVLDEP-NEXT: vslideup.vx v10, v8, a0
+; NOVLDEP-NEXT: vmsne.vi v0, v10, 0
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: test_vp_splice_nxv16i1:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v12, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v0, v12
; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
-; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; VLDEP-NEXT: vmv.v.i v12, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; VLDEP-NEXT: vslidedown.vi v8, v8, 5
+; VLDEP-NEXT: vslidedown.vi v10, v10, 5
; VLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; VLDEP-NEXT: vslideup.vx v8, v10, a0
-; VLDEP-NEXT: vmsne.vi v0, v8, 0
+; VLDEP-NEXT: vslideup.vx v10, v8, a0
+; VLDEP-NEXT: vmsne.vi v0, v10, 0
; VLDEP-NEXT: ret
%v = call <vscale x 16 x i1> @llvm.experimental.vp.splice.nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, i32 5, <vscale x 16 x i1> splat (i1 1), i32 %evla, i32 %evlb)
@@ -568,38 +568,38 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1_negative_offset(<vscale x 16 x
; NOVLDEP-LABEL: test_vp_splice_nxv16i1_negative_offset:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v12, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v12
; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
-; NOVLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v12, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
; NOVLDEP-NEXT: addi a0, a0, -5
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
-; NOVLDEP-NEXT: vslideup.vi v8, v10, 5
-; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
+; NOVLDEP-NEXT: vslidedown.vx v10, v10, a0
+; NOVLDEP-NEXT: vslideup.vi v10, v8, 5
+; NOVLDEP-NEXT: vmsne.vi v0, v10, 0
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: test_vp_splice_nxv16i1_negative_offset:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v12, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v0, v12
; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
-; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; VLDEP-NEXT: vmv.v.i v12, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vsetivli zero, 5, e8, m2, ta, ma
-; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vslidedown.vx v10, v10, a0
; VLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; VLDEP-NEXT: vslideup.vi v8, v10, 5
-; VLDEP-NEXT: vmsne.vi v0, v8, 0
+; VLDEP-NEXT: vslideup.vi v10, v8, 5
+; VLDEP-NEXT: vmsne.vi v0, v10, 0
; VLDEP-NEXT: ret
%v = call <vscale x 16 x i1> @llvm.experimental.vp.splice.nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, i32 -5, <vscale x 16 x i1> splat (i1 1), i32 %evla, i32 %evlb)
@@ -610,18 +610,18 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1_masked(<vscale x 16 x i1> %va,
; NOVLDEP-LABEL: test_vp_splice_nxv16i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv1r.v v14, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v12, 0
-; NOVLDEP-NEXT: vmerge.vim v12, v12, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v12, v10, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v14, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v10, v14, 1, v0
-; NOVLDEP-NEXT: addi a0, a0, -5
+; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v14
+; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v10, v10, 5, v0.t
+; NOVLDEP-NEXT: addi a0, a0, -5
; NOVLDEP-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; NOVLDEP-NEXT: vslideup.vx v10, v12, a0, v0.t
; NOVLDEP-NEXT: vsetvli zero, zero, e8, m2, ta, ma
@@ -632,14 +632,14 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1_masked(<vscale x 16 x i1> %va,
; VLDEP-LABEL: test_vp_splice_nxv16i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv1r.v v14, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v12, 0
-; VLDEP-NEXT: vmerge.vim v12, v12, 1, v0
+; VLDEP-NEXT: vmerge.vim v12, v10, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; VLDEP-NEXT: vmv.v.i v14, 0
-; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v10, v14, 1, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v0, v14
+; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -658,38 +658,38 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1(<vscale x 32 x i1> %va, <vscal
; NOVLDEP-LABEL: test_vp_splice_nxv32i1:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v16, v0
+; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; NOVLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v12, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v16
; NOVLDEP-NEXT: vmerge.vim v12, v12, 1, v0
-; NOVLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v16, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5
+; NOVLDEP-NEXT: vslidedown.vi v12, v12, 5
; NOVLDEP-NEXT: addi a0, a0, -5
-; NOVLDEP-NEXT: vslideup.vx v8, v12, a0
-; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
+; NOVLDEP-NEXT: vslideup.vx v12, v8, a0
+; NOVLDEP-NEXT: vmsne.vi v0, v12, 0
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: test_vp_splice_nxv32i1:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v16, v0
+; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; VLDEP-NEXT: vmv.v.i v12, 0
+; VLDEP-NEXT: vmv1r.v v0, v16
; VLDEP-NEXT: vmerge.vim v12, v12, 1, v0
-; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; VLDEP-NEXT: vmv.v.i v16, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; VLDEP-NEXT: vslidedown.vi v8, v8, 5
+; VLDEP-NEXT: vslidedown.vi v12, v12, 5
; VLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; VLDEP-NEXT: vslideup.vx v8, v12, a0
-; VLDEP-NEXT: vmsne.vi v0, v8, 0
+; VLDEP-NEXT: vslideup.vx v12, v8, a0
+; VLDEP-NEXT: vmsne.vi v0, v12, 0
; VLDEP-NEXT: ret
%v = call <vscale x 32 x i1> @llvm.experimental.vp.splice.nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, i32 5, <vscale x 32 x i1> splat (i1 1), i32 %evla, i32 %evlb)
@@ -700,38 +700,38 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1_negative_offset(<vscale x 32 x
; NOVLDEP-LABEL: test_vp_splice_nxv32i1_negative_offset:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v16, v0
+; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; NOVLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v12, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v16
; NOVLDEP-NEXT: vmerge.vim v12, v12, 1, v0
-; NOVLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v16, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
; NOVLDEP-NEXT: addi a0, a0, -5
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
-; NOVLDEP-NEXT: vslideup.vi v8, v12, 5
-; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
+; NOVLDEP-NEXT: vslidedown.vx v12, v12, a0
+; NOVLDEP-NEXT: vslideup.vi v12, v8, 5
+; NOVLDEP-NEXT: vmsne.vi v0, v12, 0
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: test_vp_splice_nxv32i1_negative_offset:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v16, v0
+; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; VLDEP-NEXT: vmv.v.i v12, 0
+; VLDEP-NEXT: vmv1r.v v0, v16
; VLDEP-NEXT: vmerge.vim v12, v12, 1, v0
-; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; VLDEP-NEXT: vmv.v.i v16, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vsetivli zero, 5, e8, m4, ta, ma
-; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vslidedown.vx v12, v12, a0
; VLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; VLDEP-NEXT: vslideup.vi v8, v12, 5
-; VLDEP-NEXT: vmsne.vi v0, v8, 0
+; VLDEP-NEXT: vslideup.vi v12, v8, 5
+; VLDEP-NEXT: vmsne.vi v0, v12, 0
; VLDEP-NEXT: ret
%v = call <vscale x 32 x i1> @llvm.experimental.vp.splice.nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, i32 -5, <vscale x 32 x i1> splat (i1 1), i32 %evla, i32 %evlb)
@@ -743,21 +743,21 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1_masked(<vscale x 32 x i1> %va,
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
; NOVLDEP-NEXT: vmv.v.i v12, 0
-; NOVLDEP-NEXT: vmerge.vim v12, v12, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v16, v12, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v16, 0
+; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v16, v16, 1, v0
-; NOVLDEP-NEXT: addi a0, a0, -5
+; NOVLDEP-NEXT: vmerge.vim v12, v12, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; NOVLDEP-NEXT: vslidedown.vi v16, v16, 5, v0.t
+; NOVLDEP-NEXT: vslidedown.vi v12, v12, 5, v0.t
+; NOVLDEP-NEXT: addi a0, a0, -5
; NOVLDEP-NEXT: vsetvli zero, zero, e8, m4, ta, mu
-; NOVLDEP-NEXT: vslideup.vx v16, v12, a0, v0.t
+; NOVLDEP-NEXT: vslideup.vx v12, v16, a0, v0.t
; NOVLDEP-NEXT: vsetvli zero, zero, e8, m4, ta, ma
-; NOVLDEP-NEXT: vmsne.vi v8, v16, 0, v0.t
+; NOVLDEP-NEXT: vmsne.vi v8, v12, 0, v0.t
; NOVLDEP-NEXT: vmv1r.v v0, v8
; NOVLDEP-NEXT: ret
;
@@ -765,21 +765,21 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1_masked(<vscale x 32 x i1> %va,
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
; VLDEP-NEXT: vmv.v.i v12, 0
-; VLDEP-NEXT: vmerge.vim v12, v12, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v16, v12, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; VLDEP-NEXT: vmv.v.i v16, 0
+; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v16, v16, 1, v0
+; VLDEP-NEXT: vmerge.vim v12, v12, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; VLDEP-NEXT: vslidedown.vi v16, v16, 5, v0.t
+; VLDEP-NEXT: vslidedown.vi v12, v12, 5, v0.t
; VLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; VLDEP-NEXT: vslideup.vx v16, v12, a0, v0.t
+; VLDEP-NEXT: vslideup.vx v12, v16, a0, v0.t
; VLDEP-NEXT: vsetvli zero, zero, e8, m4, ta, ma
-; VLDEP-NEXT: vmsne.vi v8, v16, 0, v0.t
+; VLDEP-NEXT: vmsne.vi v8, v12, 0, v0.t
; VLDEP-NEXT: vmv1r.v v0, v8
; VLDEP-NEXT: ret
%v = call <vscale x 32 x i1> @llvm.experimental.vp.splice.nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, i32 5, <vscale x 32 x i1> %mask, i32 %evla, i32 %evlb)
@@ -790,38 +790,38 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1(<vscale x 64 x i1> %va, <vscal
; NOVLDEP-LABEL: test_vp_splice_nxv64i1:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v24, v0
+; NOVLDEP-NEXT: vmv.v.i v16, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; NOVLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v16, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v24
; NOVLDEP-NEXT: vmerge.vim v16, v16, 1, v0
-; NOVLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v24, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v24, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; NOVLDEP-NEXT: vslidedown.vi v8, v8, 5
+; NOVLDEP-NEXT: vslidedown.vi v16, v16, 5
; NOVLDEP-NEXT: addi a0, a0, -5
-; NOVLDEP-NEXT: vslideup.vx v8, v16, a0
-; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
+; NOVLDEP-NEXT: vslideup.vx v16, v8, a0
+; NOVLDEP-NEXT: vmsne.vi v0, v16, 0
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: test_vp_splice_nxv64i1:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v24, v0
+; VLDEP-NEXT: vmv.v.i v16, 0
; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; VLDEP-NEXT: vmv.v.i v16, 0
+; VLDEP-NEXT: vmv1r.v v0, v24
; VLDEP-NEXT: vmerge.vim v16, v16, 1, v0
-; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; VLDEP-NEXT: vmv.v.i v24, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v24, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; VLDEP-NEXT: vslidedown.vi v8, v8, 5
+; VLDEP-NEXT: vslidedown.vi v16, v16, 5
; VLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; VLDEP-NEXT: vslideup.vx v8, v16, a0
-; VLDEP-NEXT: vmsne.vi v0, v8, 0
+; VLDEP-NEXT: vslideup.vx v16, v8, a0
+; VLDEP-NEXT: vmsne.vi v0, v16, 0
; VLDEP-NEXT: ret
%v = call <vscale x 64 x i1> @llvm.experimental.vp.splice.nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, i32 5, <vscale x 64 x i1> splat (i1 1), i32 %evla, i32 %evlb)
@@ -832,38 +832,38 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1_negative_offset(<vscale x 64 x
; NOVLDEP-LABEL: test_vp_splice_nxv64i1_negative_offset:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv1r.v v24, v0
+; NOVLDEP-NEXT: vmv.v.i v16, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; NOVLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v16, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v24
; NOVLDEP-NEXT: vmerge.vim v16, v16, 1, v0
-; NOVLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v24, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v24, 1, v0
; NOVLDEP-NEXT: addi a0, a0, -5
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
-; NOVLDEP-NEXT: vslideup.vi v8, v16, 5
-; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
+; NOVLDEP-NEXT: vslidedown.vx v16, v16, a0
+; NOVLDEP-NEXT: vslideup.vi v16, v8, 5
+; NOVLDEP-NEXT: vmsne.vi v0, v16, 0
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: test_vp_splice_nxv64i1_negative_offset:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv1r.v v24, v0
+; VLDEP-NEXT: vmv.v.i v16, 0
; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; VLDEP-NEXT: vmv.v.i v16, 0
+; VLDEP-NEXT: vmv1r.v v0, v24
; VLDEP-NEXT: vmerge.vim v16, v16, 1, v0
-; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; VLDEP-NEXT: vmv.v.i v24, 0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v24, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vsetivli zero, 5, e8, m8, ta, ma
-; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vslidedown.vx v16, v16, a0
; VLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; VLDEP-NEXT: vslideup.vi v8, v16, 5
-; VLDEP-NEXT: vmsne.vi v0, v8, 0
+; VLDEP-NEXT: vslideup.vi v16, v8, 5
+; VLDEP-NEXT: vmsne.vi v0, v16, 0
; VLDEP-NEXT: ret
%v = call <vscale x 64 x i1> @llvm.experimental.vp.splice.nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, i32 -5, <vscale x 64 x i1> splat (i1 1), i32 %evla, i32 %evlb)
@@ -875,21 +875,21 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1_masked(<vscale x 64 x i1> %va,
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
; NOVLDEP-NEXT: vmv.v.i v16, 0
-; NOVLDEP-NEXT: vmerge.vim v16, v16, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v24, v16, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v24, 0
+; NOVLDEP-NEXT: vmv.v.i v16, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v24, v24, 1, v0
-; NOVLDEP-NEXT: addi a0, a0, -5
+; NOVLDEP-NEXT: vmerge.vim v16, v16, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; NOVLDEP-NEXT: vslidedown.vi v24, v24, 5, v0.t
+; NOVLDEP-NEXT: vslidedown.vi v16, v16, 5, v0.t
+; NOVLDEP-NEXT: addi a0, a0, -5
; NOVLDEP-NEXT: vsetvli zero, zero, e8, m8, ta, mu
-; NOVLDEP-NEXT: vslideup.vx v24, v16, a0, v0.t
+; NOVLDEP-NEXT: vslideup.vx v16, v24, a0, v0.t
; NOVLDEP-NEXT: vsetvli zero, zero, e8, m8, ta, ma
-; NOVLDEP-NEXT: vmsne.vi v8, v24, 0, v0.t
+; NOVLDEP-NEXT: vmsne.vi v8, v16, 0, v0.t
; NOVLDEP-NEXT: vmv1r.v v0, v8
; NOVLDEP-NEXT: ret
;
@@ -897,21 +897,21 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1_masked(<vscale x 64 x i1> %va,
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
; VLDEP-NEXT: vmv.v.i v16, 0
-; VLDEP-NEXT: vmerge.vim v16, v16, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v24, v16, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; VLDEP-NEXT: vmv.v.i v24, 0
+; VLDEP-NEXT: vmv.v.i v16, 0
; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v24, v24, 1, v0
+; VLDEP-NEXT: vmerge.vim v16, v16, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; VLDEP-NEXT: vslidedown.vi v24, v24, 5, v0.t
+; VLDEP-NEXT: vslidedown.vi v16, v16, 5, v0.t
; VLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; VLDEP-NEXT: vslideup.vx v24, v16, a0, v0.t
+; VLDEP-NEXT: vslideup.vx v16, v24, a0, v0.t
; VLDEP-NEXT: vsetvli zero, zero, e8, m8, ta, ma
-; VLDEP-NEXT: vmsne.vi v8, v24, 0, v0.t
+; VLDEP-NEXT: vmsne.vi v8, v16, 0, v0.t
; VLDEP-NEXT: vmv1r.v v0, v8
; VLDEP-NEXT: ret
%v = call <vscale x 64 x i1> @llvm.experimental.vp.splice.nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, i32 5, <vscale x 64 x i1> %mask, i32 %evla, i32 %evlb)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll b/llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll
index d1f1538570011..bb00ac0de1941 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-vaaddu.ll
@@ -120,8 +120,8 @@ define <vscale x 2 x i16> @vaaddu_8(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8, v0.t
-; CHECK-NEXT: csrwi vxrm, 0
; CHECK-NEXT: vzext.vf2 v8, v9, v0.t
+; CHECK-NEXT: csrwi vxrm, 0
; CHECK-NEXT: vaaddu.vv v8, v10, v8, v0.t
; CHECK-NEXT: ret
%xz = call <vscale x 2 x i32> @llvm.vp.zext.nxv2i32.nxv2i8(<vscale x 2 x i8> %x, <vscale x 2 x i1> %m, i32 %vl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll b/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
index d7d767e600db5..77808ad541088 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
@@ -357,76 +357,76 @@ define void @masked_load_store_factor2_v2_shared_mask(<vscale x 2 x i1> %mask, p
define i32 @masked_load_store_factor2_v2_shared_mask_extract(<vscale x 2 x i1> %mask, ptr %ptr, i32 zeroext %evl) {
; RV32-LABEL: masked_load_store_factor2_v2_shared_mask_extract:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v8, v0
; RV32-NEXT: slli a2, a1, 1
-; RV32-NEXT: vmv.v.i v9, 0
+; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
+; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: li a3, -1
-; RV32-NEXT: vmerge.vim v10, v9, 1, v0
-; RV32-NEXT: vwaddu.vv v11, v10, v10
-; RV32-NEXT: vwmaccu.vx v11, a3, v10
+; RV32-NEXT: vmerge.vim v9, v8, 1, v0
+; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vwaddu.vv v10, v9, v9
+; RV32-NEXT: vwmaccu.vx v10, a3, v9
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma
-; RV32-NEXT: vmv.v.i v10, 0
+; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: srli a3, a3, 2
; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV32-NEXT: vmsne.vi v0, v11, 0
+; RV32-NEXT: vmsne.vi v0, v10, 0
; RV32-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; RV32-NEXT: vslidedown.vx v11, v11, a3
+; RV32-NEXT: vslidedown.vx v10, v10, a3
; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma
-; RV32-NEXT: vmerge.vim v10, v10, 1, v0
-; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV32-NEXT: vmsne.vi v0, v11, 0
; RV32-NEXT: vmerge.vim v9, v9, 1, v0
-; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma
-; RV32-NEXT: vslideup.vx v10, v9, a3
+; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; RV32-NEXT: vmsne.vi v0, v10, 0
-; RV32-NEXT: vle32.v v10, (a0), v0.t
+; RV32-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma
+; RV32-NEXT: vslideup.vx v9, v8, a3
+; RV32-NEXT: vmsne.vi v0, v9, 0
+; RV32-NEXT: vle32.v v8, (a0), v0.t
; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; RV32-NEXT: vnsrl.wx v13, v10, a2
-; RV32-NEXT: vnsrl.wi v12, v10, 0
-; RV32-NEXT: vmv.x.s a1, v10
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vsseg2e32.v v12, (a0), v0.t
+; RV32-NEXT: vnsrl.wx v11, v8, a2
+; RV32-NEXT: vnsrl.wi v10, v8, 0
+; RV32-NEXT: vmv.x.s a1, v8
+; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vsseg2e32.v v10, (a0), v0.t
; RV32-NEXT: mv a0, a1
; RV32-NEXT: ret
;
; RV64-LABEL: masked_load_store_factor2_v2_shared_mask_extract:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v8, v0
-; RV64-NEXT: vmv.v.i v9, 0
+; RV64-NEXT: vmv.v.i v8, 0
; RV64-NEXT: li a2, -1
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv.v.i v10, 0
+; RV64-NEXT: vmv.v.i v9, 0
; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmerge.vim v11, v9, 1, v0
-; RV64-NEXT: vwaddu.vv v12, v11, v11
-; RV64-NEXT: vwmaccu.vx v12, a2, v11
+; RV64-NEXT: vmerge.vim v10, v8, 1, v0
+; RV64-NEXT: vmv1r.v v12, v0
+; RV64-NEXT: vwaddu.vv v11, v10, v10
+; RV64-NEXT: vwmaccu.vx v11, a2, v10
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: srli a2, a2, 2
-; RV64-NEXT: vmsne.vi v0, v12, 0
-; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vslidedown.vx v11, v12, a2
-; RV64-NEXT: vmerge.vim v10, v10, 1, v0
-; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV64-NEXT: vmsne.vi v0, v11, 0
+; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; RV64-NEXT: vslidedown.vx v10, v11, a2
; RV64-NEXT: vmerge.vim v9, v9, 1, v0
+; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
+; RV64-NEXT: vmsne.vi v0, v10, 0
+; RV64-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vslideup.vx v10, v9, a2
+; RV64-NEXT: vslideup.vx v9, v8, a2
; RV64-NEXT: slli a2, a1, 33
-; RV64-NEXT: vmsne.vi v0, v10, 0
; RV64-NEXT: srli a2, a2, 32
+; RV64-NEXT: vmsne.vi v0, v9, 0
; RV64-NEXT: vsetvli zero, a2, e32, m2, ta, ma
-; RV64-NEXT: vle32.v v10, (a0), v0.t
+; RV64-NEXT: vle32.v v8, (a0), v0.t
; RV64-NEXT: li a2, 32
; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, ma
-; RV64-NEXT: vnsrl.wx v13, v10, a2
-; RV64-NEXT: vnsrl.wi v12, v10, 0
-; RV64-NEXT: vmv.x.s a1, v10
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vsseg2e32.v v12, (a0), v0.t
+; RV64-NEXT: vnsrl.wx v11, v8, a2
+; RV64-NEXT: vnsrl.wi v10, v8, 0
+; RV64-NEXT: vmv.x.s a1, v8
+; RV64-NEXT: vmv1r.v v0, v12
+; RV64-NEXT: vsseg2e32.v v10, (a0), v0.t
; RV64-NEXT: mv a0, a1
; RV64-NEXT: ret
%rvl = mul nuw i32 %evl, 2
@@ -501,16 +501,16 @@ define {<vscale x 2 x i32>, <vscale x 2 x i32>} @not_same_mask(<vscale x 2 x i1>
; RV32-LABEL: not_same_mask:
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v9, v0
-; RV32-NEXT: vmv1r.v v0, v8
+; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: slli a1, a1, 1
-; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vmv.v.i v12, 0
; RV32-NEXT: li a2, -1
-; RV32-NEXT: vmerge.vim v10, v8, 1, v0
-; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmerge.vim v9, v8, 1, v0
-; RV32-NEXT: vwaddu.vv v11, v9, v10
-; RV32-NEXT: vwmaccu.vx v11, a2, v10
+; RV32-NEXT: vmv1r.v v0, v8
+; RV32-NEXT: vmerge.vim v9, v12, 1, v0
+; RV32-NEXT: vmv1r.v v0, v10
+; RV32-NEXT: vmerge.vim v10, v12, 1, v0
+; RV32-NEXT: vwaddu.vv v11, v10, v9
+; RV32-NEXT: vwmaccu.vx v11, a2, v9
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; RV32-NEXT: vmv.v.i v9, 0
@@ -523,7 +523,7 @@ define {<vscale x 2 x i32>, <vscale x 2 x i32>} @not_same_mask(<vscale x 2 x i1>
; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV32-NEXT: vmsne.vi v0, v10, 0
-; RV32-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-NEXT: vmerge.vim v8, v12, 1, v0
; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; RV32-NEXT: vslideup.vx v9, v8, a2
; RV32-NEXT: vmsne.vi v0, v9, 0
@@ -537,32 +537,32 @@ define {<vscale x 2 x i32>, <vscale x 2 x i32>} @not_same_mask(<vscale x 2 x i1>
; RV64-LABEL: not_same_mask:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: vmv1r.v v11, v0
+; RV64-NEXT: vmv.v.i v13, 0
; RV64-NEXT: li a2, -1
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv.v.i v10, 0
+; RV64-NEXT: vmv.v.i v9, 0
+; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmerge.vim v11, v8, 1, v0
-; RV64-NEXT: vmv1r.v v0, v9
-; RV64-NEXT: vmerge.vim v9, v8, 1, v0
-; RV64-NEXT: vwaddu.vv v12, v9, v11
-; RV64-NEXT: vwmaccu.vx v12, a2, v11
+; RV64-NEXT: vmerge.vim v10, v13, 1, v0
+; RV64-NEXT: vmv1r.v v0, v11
+; RV64-NEXT: vmerge.vim v11, v13, 1, v0
+; RV64-NEXT: vwaddu.vv v12, v11, v10
+; RV64-NEXT: vwmaccu.vx v12, a2, v10
; RV64-NEXT: csrr a2, vlenb
+; RV64-NEXT: slli a1, a1, 33
; RV64-NEXT: srli a2, a2, 2
+; RV64-NEXT: srli a1, a1, 32
; RV64-NEXT: vmsne.vi v0, v12, 0
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vslidedown.vx v9, v12, a2
-; RV64-NEXT: vmerge.vim v10, v10, 1, v0
+; RV64-NEXT: vslidedown.vx v10, v12, a2
+; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmsne.vi v0, v9, 0
-; RV64-NEXT: slli a1, a1, 33
-; RV64-NEXT: vmerge.vim v8, v8, 1, v0
-; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vslideup.vx v10, v8, a2
; RV64-NEXT: vmsne.vi v0, v10, 0
-; RV64-NEXT: srli a1, a1, 32
+; RV64-NEXT: vmerge.vim v8, v13, 1, v0
+; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; RV64-NEXT: vslideup.vx v9, v8, a2
+; RV64-NEXT: vmsne.vi v0, v9, 0
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma
; RV64-NEXT: vle32.v v10, (a0), v0.t
; RV64-NEXT: li a0, 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
index a075bba81d3c6..40d781f403952 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
@@ -248,8 +248,6 @@ define <vscale x 8 x i8> @vpgather_baseidx_nxv8i8(ptr %base, <vscale x 8 x i8> %
define <vscale x 32 x i8> @vpgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8> %idxs, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_nxv32i8:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a2, a3, 1
; RV32-NEXT: srli a3, a3, 2
@@ -257,6 +255,8 @@ define <vscale x 32 x i8> @vpgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8
; RV32-NEXT: sltu a5, a1, a4
; RV32-NEXT: addi a5, a5, -1
; RV32-NEXT: and a4, a5, a4
+; RV32-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vslidedown.vx v0, v0, a3
; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vsext.vf4 v16, v10
@@ -275,12 +275,12 @@ define <vscale x 32 x i8> @vpgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8
;
; RV64-LABEL: vpgather_baseidx_nxv32i8:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v12, v0
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a3, a2, 1
; RV64-NEXT: srli a4, a2, 2
; RV64-NEXT: sub a5, a1, a3
+; RV64-NEXT: vsetvli a6, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v12, v0
; RV64-NEXT: vslidedown.vx v13, v0, a4
; RV64-NEXT: sltu a4, a1, a5
; RV64-NEXT: addi a4, a4, -1
@@ -290,6 +290,7 @@ define <vscale x 32 x i8> @vpgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8
; RV64-NEXT: addi a6, a6, -1
; RV64-NEXT: and a6, a6, a4
; RV64-NEXT: srli a4, a2, 3
+; RV64-NEXT: vmv1r.v v14, v13
; RV64-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vx v0, v13, a4
; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma
@@ -302,7 +303,7 @@ define <vscale x 32 x i8> @vpgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8
; RV64-NEXT: vluxei64.v v11, (a0), v16, v0.t
; RV64-NEXT: vsetvli zero, a5, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v10
-; RV64-NEXT: vmv1r.v v0, v13
+; RV64-NEXT: vmv1r.v v0, v14
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; RV64-NEXT: vluxei64.v v10, (a0), v16, v0.t
; RV64-NEXT: bltu a1, a3, .LBB12_4
@@ -2361,15 +2362,15 @@ define <vscale x 8 x double> @vpgather_baseidx_nxv8f64(ptr %base, <vscale x 8 x
define <vscale x 16 x double> @vpgather_nxv16f64(<vscale x 16 x ptr> %ptrs, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_nxv16f64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v24, v0
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: sub a2, a0, a1
-; RV32-NEXT: srli a3, a1, 3
-; RV32-NEXT: vslidedown.vx v0, v0, a3
; RV32-NEXT: sltu a3, a0, a2
; RV32-NEXT: addi a3, a3, -1
; RV32-NEXT: and a2, a3, a2
+; RV32-NEXT: srli a3, a1, 3
+; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; RV32-NEXT: vmv1r.v v24, v0
+; RV32-NEXT: vslidedown.vx v0, v0, a3
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (zero), v12, v0.t
; RV32-NEXT: bltu a0, a1, .LBB111_2
@@ -2384,15 +2385,15 @@ define <vscale x 16 x double> @vpgather_nxv16f64(<vscale x 16 x ptr> %ptrs, <vsc
;
; RV64-LABEL: vpgather_nxv16f64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: sub a2, a0, a1
-; RV64-NEXT: srli a3, a1, 3
-; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: sltu a3, a0, a2
; RV64-NEXT: addi a3, a3, -1
; RV64-NEXT: and a2, a3, a2
+; RV64-NEXT: srli a3, a1, 3
+; RV64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (zero), v16, v0.t
; RV64-NEXT: bltu a0, a1, .LBB111_2
@@ -2425,9 +2426,9 @@ define <vscale x 16 x double> @vpgather_baseidx_nxv16i16_nxv16f64(ptr %base, <vs
; RV32-NEXT: srli a2, a2, 3
; RV32-NEXT: sltu a1, a1, a3
; RV32-NEXT: addi a1, a1, -1
-; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vx v0, v0, a2
; RV32-NEXT: and a1, a1, a3
+; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vx v0, v0, a2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v28, v0.t
; RV32-NEXT: ret
@@ -2435,29 +2436,29 @@ define <vscale x 16 x double> @vpgather_baseidx_nxv16i16_nxv16f64(ptr %base, <vs
; RV64-LABEL: vpgather_baseidx_nxv16i16_nxv16f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma
-; RV64-NEXT: vmv1r.v v12, v0
; RV64-NEXT: vsext.vf4 v16, v10
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: sub a3, a1, a2
-; RV64-NEXT: srli a4, a2, 3
-; RV64-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v0, v0, a4
; RV64-NEXT: sltu a4, a1, a3
; RV64-NEXT: addi a4, a4, -1
; RV64-NEXT: and a3, a4, a3
+; RV64-NEXT: srli a4, a2, 3
+; RV64-NEXT: vmv1r.v v7, v0
+; RV64-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vx v0, v0, a4
; RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v24, v8
-; RV64-NEXT: vsll.vi v24, v24, 3
+; RV64-NEXT: vsll.vi v8, v24, 3
; RV64-NEXT: bltu a1, a2, .LBB112_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a1, a2
; RV64-NEXT: .LBB112_2:
-; RV64-NEXT: vmv1r.v v0, v12
+; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vluxei64.v v8, (a0), v24, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, ptr %base, <vscale x 16 x i16> %idxs
%v = call <vscale x 16 x double> @llvm.vp.gather.nxv16f64.nxv16p0(<vscale x 16 x ptr> %ptrs, <vscale x 16 x i1> %m, i32 %evl)
@@ -2482,9 +2483,9 @@ define <vscale x 16 x double> @vpgather_baseidx_sext_nxv16i16_nxv16f64(ptr %base
; RV32-NEXT: srli a2, a2, 3
; RV32-NEXT: sltu a1, a1, a3
; RV32-NEXT: addi a1, a1, -1
-; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vx v0, v0, a2
; RV32-NEXT: and a1, a1, a3
+; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vx v0, v0, a2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v28, v0.t
; RV32-NEXT: ret
@@ -2492,29 +2493,29 @@ define <vscale x 16 x double> @vpgather_baseidx_sext_nxv16i16_nxv16f64(ptr %base
; RV64-LABEL: vpgather_baseidx_sext_nxv16i16_nxv16f64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma
-; RV64-NEXT: vmv1r.v v12, v0
; RV64-NEXT: vsext.vf4 v16, v10
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: sub a3, a1, a2
-; RV64-NEXT: srli a4, a2, 3
-; RV64-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v0, v0, a4
; RV64-NEXT: sltu a4, a1, a3
; RV64-NEXT: addi a4, a4, -1
; RV64-NEXT: and a3, a4, a3
+; RV64-NEXT: srli a4, a2, 3
+; RV64-NEXT: vmv1r.v v7, v0
+; RV64-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vx v0, v0, a4
; RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v24, v8
-; RV64-NEXT: vsll.vi v24, v24, 3
+; RV64-NEXT: vsll.vi v8, v24, 3
; RV64-NEXT: bltu a1, a2, .LBB113_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a1, a2
; RV64-NEXT: .LBB113_2:
-; RV64-NEXT: vmv1r.v v0, v12
+; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vluxei64.v v8, (a0), v24, v0.t
+; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: ret
%eidxs = sext <vscale x 16 x i16> %idxs to <vscale x 16 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <vscale x 16 x i64> %eidxs
@@ -2540,9 +2541,9 @@ define <vscale x 16 x double> @vpgather_baseidx_zext_nxv16i16_nxv16f64(ptr %base
; RV32-NEXT: srli a2, a2, 3
; RV32-NEXT: sltu a1, a1, a3
; RV32-NEXT: addi a1, a1, -1
-; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vx v0, v0, a2
; RV32-NEXT: and a1, a1, a3
+; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vx v0, v0, a2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v28, v0.t
; RV32-NEXT: ret
@@ -2564,9 +2565,9 @@ define <vscale x 16 x double> @vpgather_baseidx_zext_nxv16i16_nxv16f64(ptr %base
; RV64-NEXT: srli a2, a2, 3
; RV64-NEXT: sltu a1, a1, a3
; RV64-NEXT: addi a1, a1, -1
-; RV64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v0, v0, a2
; RV64-NEXT: and a1, a1, a3
+; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vx v0, v0, a2
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vluxei32.v v16, (a0), v28, v0.t
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpload.ll b/llvm/test/CodeGen/RISCV/rvv/vpload.ll
index 2ece316c7e54a..629eb961485fb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpload.ll
@@ -452,17 +452,17 @@ define <vscale x 8 x double> @vpload_nxv8f64(ptr %ptr, <vscale x 8 x i1> %m, i32
define <vscale x 16 x double> @vpload_nxv16f64(ptr %ptr, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpload_nxv16f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: slli a4, a2, 3
-; CHECK-NEXT: srli a5, a2, 3
-; CHECK-NEXT: vslidedown.vx v0, v0, a5
; CHECK-NEXT: sltu a5, a1, a3
; CHECK-NEXT: addi a5, a5, -1
; CHECK-NEXT: and a3, a5, a3
+; CHECK-NEXT: srli a5, a2, 3
; CHECK-NEXT: add a4, a0, a4
+; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a5
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a4), v0.t
; CHECK-NEXT: bltu a1, a2, .LBB44_2
@@ -487,46 +487,46 @@ define <vscale x 16 x double> @vpload_nxv17f64(ptr %ptr, ptr %out, <vscale x 17
; CHECK-LABEL: vpload_nxv17f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a5, a3, 1
-; CHECK-NEXT: mv a4, a2
-; CHECK-NEXT: bltu a2, a5, .LBB45_2
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: csrr a4, vlenb
+; CHECK-NEXT: slli a6, a4, 1
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: bltu a2, a6, .LBB45_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a4, a5
+; CHECK-NEXT: mv a3, a6
; CHECK-NEXT: .LBB45_2:
-; CHECK-NEXT: sub a6, a4, a3
-; CHECK-NEXT: slli a7, a3, 3
-; CHECK-NEXT: sltu t0, a4, a6
+; CHECK-NEXT: sub a5, a3, a4
+; CHECK-NEXT: slli a7, a4, 3
+; CHECK-NEXT: sltu t0, a3, a5
; CHECK-NEXT: addi t0, t0, -1
-; CHECK-NEXT: and a6, t0, a6
-; CHECK-NEXT: srli t0, a3, 3
-; CHECK-NEXT: sub t1, a2, a5
-; CHECK-NEXT: add a5, a0, a7
+; CHECK-NEXT: and a5, t0, a5
+; CHECK-NEXT: srli t0, a4, 3
+; CHECK-NEXT: sub t1, a2, a6
+; CHECK-NEXT: add a6, a0, a7
; CHECK-NEXT: sltu a2, a2, t1
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, t1
; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, t0
-; CHECK-NEXT: bltu a2, a3, .LBB45_4
+; CHECK-NEXT: vslidedown.vx v0, v9, t0
+; CHECK-NEXT: bltu a2, a4, .LBB45_4
; CHECK-NEXT: # %bb.3:
-; CHECK-NEXT: mv a2, a3
+; CHECK-NEXT: mv a2, a4
; CHECK-NEXT: .LBB45_4:
-; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma
-; CHECK-NEXT: vle64.v v16, (a5), v0.t
-; CHECK-NEXT: slli a5, a3, 4
-; CHECK-NEXT: srli a6, a3, 2
-; CHECK-NEXT: vsetvli a7, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a6
+; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma
+; CHECK-NEXT: vle64.v v16, (a6), v0.t
+; CHECK-NEXT: slli a5, a4, 4
+; CHECK-NEXT: srli a6, a4, 2
; CHECK-NEXT: add a5, a0, a5
+; CHECK-NEXT: vsetvli a7, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v9, a6
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v24, (a5), v0.t
-; CHECK-NEXT: bltu a4, a3, .LBB45_6
+; CHECK-NEXT: bltu a3, a4, .LBB45_6
; CHECK-NEXT: # %bb.5:
-; CHECK-NEXT: mv a4, a3
+; CHECK-NEXT: mv a3, a4
; CHECK-NEXT: .LBB45_6:
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0), v0.t
; CHECK-NEXT: vs1r.v v24, (a1)
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
index f92ee37051840..26e9bc1c97aa8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
@@ -127,17 +127,17 @@ define <vscale x 16 x i1> @vpmerge_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16
; RV64-LABEL: vpmerge_nxv16i1:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; RV64-NEXT: vmv.v.i v10, 0
+; RV64-NEXT: vmv.v.i v12, 0
; RV64-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; RV64-NEXT: vmerge.vim v12, v10, 1, v0
+; RV64-NEXT: vmerge.vim v10, v12, 1, v0
; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; RV64-NEXT: vmerge.vim v10, v10, 1, v0
+; RV64-NEXT: vmerge.vim v12, v12, 1, v0
; RV64-NEXT: vmv1r.v v0, v9
; RV64-NEXT: vsetvli zero, a0, e8, m2, tu, ma
-; RV64-NEXT: vmerge.vvm v10, v10, v12, v0
+; RV64-NEXT: vmerge.vvm v12, v12, v10, v0
; RV64-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; RV64-NEXT: vmsne.vi v0, v10, 0
+; RV64-NEXT: vmsne.vi v0, v12, 0
; RV64-NEXT: ret
%v = call <vscale x 16 x i1> @llvm.vp.merge.nxv16i1(<vscale x 16 x i1> %m, <vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, i32 %evl)
ret <vscale x 16 x i1> %v
@@ -147,17 +147,17 @@ define <vscale x 32 x i1> @vpmerge_nxv32i1(<vscale x 32 x i1> %va, <vscale x 32
; CHECK-LABEL: vpmerge_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v12, 1, v0
+; CHECK-NEXT: vmerge.vim v12, v16, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
+; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma
-; CHECK-NEXT: vmerge.vvm v12, v12, v16, v0
+; CHECK-NEXT: vmerge.vvm v16, v16, v12, v0
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; CHECK-NEXT: vmsne.vi v0, v12, 0
+; CHECK-NEXT: vmsne.vi v0, v16, 0
; CHECK-NEXT: ret
%v = call <vscale x 32 x i1> @llvm.vp.merge.nxv32i1(<vscale x 32 x i1> %m, <vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, i32 %evl)
ret <vscale x 32 x i1> %v
@@ -167,17 +167,17 @@ define <vscale x 64 x i1> @vpmerge_nxv64i1(<vscale x 64 x i1> %va, <vscale x 64
; CHECK-LABEL: vpmerge_nxv64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmv.v.i v24, 0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
+; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
+; CHECK-NEXT: vmerge.vim v24, v24, 1, v0
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, ma
-; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
+; CHECK-NEXT: vmerge.vvm v24, v24, v16, v0
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmsne.vi v0, v16, 0
+; CHECK-NEXT: vmsne.vi v0, v24, 0
; CHECK-NEXT: ret
%v = call <vscale x 64 x i1> @llvm.vp.merge.nxv64i1(<vscale x 64 x i1> %m, <vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, i32 %evl)
ret <vscale x 64 x i1> %v
@@ -190,6 +190,7 @@ define <vscale x 128 x i1> @vpmerge_nxv128i1(<vscale x 128 x i1> %va, <vscale x
; CHECK-NEXT: vmv1r.v v7, v12
; CHECK-NEXT: vmv1r.v v4, v11
; CHECK-NEXT: vmv1r.v v6, v10
+; CHECK-NEXT: vmv1r.v v24, v9
; CHECK-NEXT: vmv1r.v v5, v8
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
@@ -199,33 +200,33 @@ define <vscale x 128 x i1> @vpmerge_nxv128i1(<vscale x 128 x i1> %va, <vscale x
; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: sub a2, a0, a2
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
+; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
; CHECK-NEXT: sltu a0, a0, a2
; CHECK-NEXT: vmv1r.v v0, v4
; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
+; CHECK-NEXT: vmerge.vvm v24, v24, v16, v0
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmsne.vi v24, v8, 0
+; CHECK-NEXT: vmsne.vi v4, v24, 0
; CHECK-NEXT: and a0, a0, a2
; CHECK-NEXT: vmv1r.v v0, v5
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
+; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
+; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, ma
-; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT: vmerge.vvm v24, v24, v16, v0
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmsne.vi v8, v16, 0
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmsne.vi v8, v24, 0
+; CHECK-NEXT: vmv1r.v v0, v4
; CHECK-NEXT: ret
%v = call <vscale x 128 x i1> @llvm.vp.merge.nxv128i1(<vscale x 128 x i1> %m, <vscale x 128 x i1> %va, <vscale x 128 x i1> %vb, i32 %evl)
ret <vscale x 128 x i1> %v
@@ -538,7 +539,7 @@ define <vscale x 128 x i8> @vpmerge_vv_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vmv1r.v v6, v0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
@@ -557,7 +558,7 @@ define <vscale x 128 x i8> @vpmerge_vv_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: .LBB35_2:
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a3, e8, m8, tu, ma
@@ -578,7 +579,7 @@ define <vscale x 128 x i8> @vpmerge_vx_nxv128i8(i8 %a, <vscale x 128 x i8> %vb,
; CHECK-LABEL: vpmerge_vx_nxv128i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
@@ -592,7 +593,7 @@ define <vscale x 128 x i8> @vpmerge_vx_nxv128i8(i8 %a, <vscale x 128 x i8> %vb,
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB36_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, tu, ma
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
@@ -606,7 +607,7 @@ define <vscale x 128 x i8> @vpmerge_vi_nxv128i8(<vscale x 128 x i8> %vb, <vscale
; CHECK-LABEL: vpmerge_vi_nxv128i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
@@ -620,7 +621,7 @@ define <vscale x 128 x i8> @vpmerge_vi_nxv128i8(<vscale x 128 x i8> %vb, <vscale
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: .LBB37_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
; CHECK-NEXT: vmerge.vim v8, v8, 2, v0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
index 7e4a60095d7cc..71683ce249318 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
@@ -2196,9 +2196,9 @@ define void @vpscatter_nxv16f64(<vscale x 16 x double> %val, <vscale x 16 x ptr>
; RV32-NEXT: srli a0, a0, 3
; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1
-; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vx v0, v0, a0
; RV32-NEXT: and a1, a1, a2
+; RV32-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vx v0, v0, a0
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v16, (zero), v28, v0.t
; RV32-NEXT: ret
@@ -2229,9 +2229,9 @@ define void @vpscatter_nxv16f64(<vscale x 16 x double> %val, <vscale x 16 x ptr>
; RV64-NEXT: srli a1, a1, 3
; RV64-NEXT: sltu a2, a2, a0
; RV64-NEXT: addi a2, a2, -1
-; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v0, v0, a1
; RV64-NEXT: and a0, a2, a0
+; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vx v0, v0, a1
; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
@@ -2266,9 +2266,9 @@ define void @vpscatter_baseidx_nxv16i16_nxv16f64(<vscale x 16 x double> %val, pt
; RV32-NEXT: srli a1, a1, 3
; RV32-NEXT: sltu a2, a2, a3
; RV32-NEXT: addi a2, a2, -1
-; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vx v0, v0, a1
; RV32-NEXT: and a2, a2, a3
+; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vx v0, v0, a1
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v16, (a0), v28, v0.t
; RV32-NEXT: ret
@@ -2286,8 +2286,8 @@ define void @vpscatter_baseidx_nxv16i16_nxv16f64(<vscale x 16 x double> %val, pt
; RV64-NEXT: vl4re16.v v4, (a1)
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, ma
-; RV64-NEXT: vsext.vf4 v16, v6
-; RV64-NEXT: vsll.vi v16, v16, 3
+; RV64-NEXT: vsext.vf4 v24, v6
+; RV64-NEXT: vsll.vi v16, v24, 3
; RV64-NEXT: vsext.vf4 v24, v4
; RV64-NEXT: vsll.vi v24, v24, 3
; RV64-NEXT: mv a3, a2
@@ -2301,9 +2301,9 @@ define void @vpscatter_baseidx_nxv16i16_nxv16f64(<vscale x 16 x double> %val, pt
; RV64-NEXT: srli a1, a1, 3
; RV64-NEXT: sltu a2, a2, a3
; RV64-NEXT: addi a2, a2, -1
-; RV64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v0, v0, a1
; RV64-NEXT: and a2, a2, a3
+; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vx v0, v0, a1
; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
@@ -2339,9 +2339,9 @@ define void @vpscatter_baseidx_sext_nxv16i16_nxv16f64(<vscale x 16 x double> %va
; RV32-NEXT: srli a1, a1, 3
; RV32-NEXT: sltu a2, a2, a3
; RV32-NEXT: addi a2, a2, -1
-; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vx v0, v0, a1
; RV32-NEXT: and a2, a2, a3
+; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vx v0, v0, a1
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v16, (a0), v28, v0.t
; RV32-NEXT: ret
@@ -2359,8 +2359,8 @@ define void @vpscatter_baseidx_sext_nxv16i16_nxv16f64(<vscale x 16 x double> %va
; RV64-NEXT: vl4re16.v v4, (a1)
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, ma
-; RV64-NEXT: vsext.vf4 v16, v6
-; RV64-NEXT: vsll.vi v16, v16, 3
+; RV64-NEXT: vsext.vf4 v24, v6
+; RV64-NEXT: vsll.vi v16, v24, 3
; RV64-NEXT: vsext.vf4 v24, v4
; RV64-NEXT: vsll.vi v24, v24, 3
; RV64-NEXT: mv a3, a2
@@ -2374,9 +2374,9 @@ define void @vpscatter_baseidx_sext_nxv16i16_nxv16f64(<vscale x 16 x double> %va
; RV64-NEXT: srli a1, a1, 3
; RV64-NEXT: sltu a2, a2, a3
; RV64-NEXT: addi a2, a2, -1
-; RV64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v0, v0, a1
; RV64-NEXT: and a2, a2, a3
+; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vx v0, v0, a1
; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
@@ -2413,9 +2413,9 @@ define void @vpscatter_baseidx_zext_nxv16i16_nxv16f64(<vscale x 16 x double> %va
; RV32-NEXT: srli a1, a1, 3
; RV32-NEXT: sltu a2, a2, a3
; RV32-NEXT: addi a2, a2, -1
-; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vx v0, v0, a1
; RV32-NEXT: and a2, a2, a3
+; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vx v0, v0, a1
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v16, (a0), v28, v0.t
; RV32-NEXT: ret
@@ -2438,9 +2438,9 @@ define void @vpscatter_baseidx_zext_nxv16i16_nxv16f64(<vscale x 16 x double> %va
; RV64-NEXT: srli a1, a1, 3
; RV64-NEXT: sltu a2, a2, a3
; RV64-NEXT: addi a2, a2, -1
-; RV64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v0, v0, a1
; RV64-NEXT: and a2, a2, a3
+; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vx v0, v0, a1
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vsoxei32.v v16, (a0), v28, v0.t
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpstore.ll b/llvm/test/CodeGen/RISCV/rvv/vpstore.ll
index 9fd8b9d23cb5e..0532832dd3f11 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpstore.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpstore.ll
@@ -369,15 +369,15 @@ define void @vpstore_nxv16f64(<vscale x 16 x double> %val, ptr %ptr, <vscale x 1
; CHECK-NEXT: .LBB35_2:
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-NEXT: vse64.v v8, (a0), v0.t
-; CHECK-NEXT: srli a3, a2, 3
-; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: sub a3, a1, a2
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: srli a2, a2, 3
; CHECK-NEXT: sltu a1, a1, a3
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a1, a1, a3
-; CHECK-NEXT: add a0, a0, a2
+; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vse64.v v16, (a0), v0.t
; CHECK-NEXT: ret
@@ -390,8 +390,6 @@ define void @vpstore_nxv16f64(<vscale x 16 x double> %val, ptr %ptr, <vscale x 1
define void @vpstore_nxv17f64(<vscale x 17 x double> %val, ptr %ptr, <vscale x 17 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpstore_nxv17f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a4, a3, 1
; CHECK-NEXT: mv a5, a2
@@ -404,14 +402,14 @@ define void @vpstore_nxv17f64(<vscale x 17 x double> %val, ptr %ptr, <vscale x 1
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a6, a3
; CHECK-NEXT: .LBB36_4:
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; CHECK-NEXT: vse64.v v8, (a1), v0.t
; CHECK-NEXT: sub a0, a5, a3
; CHECK-NEXT: srli a6, a3, 3
+; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v7, a6
+; CHECK-NEXT: vslidedown.vx v0, v0, a6
; CHECK-NEXT: slli a6, a3, 3
; CHECK-NEXT: sub a4, a2, a4
; CHECK-NEXT: sltu a5, a5, a0
@@ -429,9 +427,9 @@ define void @vpstore_nxv17f64(<vscale x 17 x double> %val, ptr %ptr, <vscale x 1
; CHECK-NEXT: .LBB36_6:
; CHECK-NEXT: slli a2, a3, 4
; CHECK-NEXT: srli a3, a3, 2
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v7, a3
; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v8, a3
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vse64.v v24, (a1), v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
index df97f19df7f99..15b3508d8e20d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
@@ -89,7 +89,7 @@ define half @vpreduce_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x
; CHECK-NEXT: srli a1, a2, 1
; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v24, v0, a1
+; CHECK-NEXT: vslidedown.vx v25, v0, a1
; CHECK-NEXT: sub a1, a0, a2
; CHECK-NEXT: sltu a3, a0, a1
; CHECK-NEXT: addi a3, a3, -1
@@ -99,13 +99,13 @@ define half @vpreduce_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x
; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: .LBB6_2:
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v24, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vfredusum.vs v24, v8, v24, v0.t
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; CHECK-NEXT: vfredusum.vs v25, v16, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredusum.vs v24, v16, v24, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v24
; CHECK-NEXT: ret
%r = call reassoc half @llvm.vp.reduce.fadd.nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 %evl)
ret half %r
@@ -118,7 +118,7 @@ define half @vpreduce_ord_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscal
; CHECK-NEXT: srli a1, a2, 1
; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v24, v0, a1
+; CHECK-NEXT: vslidedown.vx v25, v0, a1
; CHECK-NEXT: sub a1, a0, a2
; CHECK-NEXT: sltu a3, a0, a1
; CHECK-NEXT: addi a3, a3, -1
@@ -128,13 +128,13 @@ define half @vpreduce_ord_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscal
; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfmv.s.f v25, fa0
+; CHECK-NEXT: vfmv.s.f v24, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vfredosum.vs v24, v8, v24, v0.t
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; CHECK-NEXT: vfredosum.vs v25, v16, v25, v0.t
-; CHECK-NEXT: vfmv.f.s fa0, v25
+; CHECK-NEXT: vfredosum.vs v24, v16, v24, v0.t
+; CHECK-NEXT: vfmv.f.s fa0, v24
; CHECK-NEXT: ret
%r = call half @llvm.vp.reduce.fadd.nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 %evl)
ret half %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
index 7eea35afe0aa0..295d146ea7a7a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
@@ -882,7 +882,7 @@ define signext i32 @vpreduce_umax_nxv32i32(i32 signext %s, <vscale x 32 x i32> %
; CHECK-NEXT: srli a2, a3, 2
; CHECK-NEXT: slli a3, a3, 1
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v24, v0, a2
+; CHECK-NEXT: vslidedown.vx v25, v0, a2
; CHECK-NEXT: sub a2, a1, a3
; CHECK-NEXT: sltu a4, a1, a2
; CHECK-NEXT: addi a4, a4, -1
@@ -892,13 +892,13 @@ define signext i32 @vpreduce_umax_nxv32i32(i32 signext %s, <vscale x 32 x i32> %
; CHECK-NEXT: mv a1, a3
; CHECK-NEXT: .LBB67_2:
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-NEXT: vmv.s.x v25, a0
+; CHECK-NEXT: vmv.s.x v24, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; CHECK-NEXT: vredmaxu.vs v25, v8, v25, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vredmaxu.vs v24, v8, v24, v0.t
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; CHECK-NEXT: vredmaxu.vs v25, v16, v25, v0.t
-; CHECK-NEXT: vmv.x.s a0, v25
+; CHECK-NEXT: vredmaxu.vs v24, v16, v24, v0.t
+; CHECK-NEXT: vmv.x.s a0, v24
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.umax.nxv32i32(i32 %s, <vscale x 32 x i32> %v, <vscale x 32 x i1> %m, i32 %evl)
ret i32 %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
index 98634fe55de41..e197ada5706ab 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
@@ -552,7 +552,7 @@ define <vscale x 128 x i8> @vsadd_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
; CHECK-LABEL: vsadd_vi_nxv128i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
@@ -566,7 +566,7 @@ define <vscale x 128 x i8> @vsadd_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: .LBB50_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
@@ -1305,11 +1305,11 @@ define <vscale x 16 x i32> @vsadd_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vsadd_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
index a7d304261f87f..c35b8af7ffc4f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
@@ -551,7 +551,7 @@ define <vscale x 128 x i8> @vsaddu_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK-LABEL: vsaddu_vi_nxv128i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
@@ -565,7 +565,7 @@ define <vscale x 128 x i8> @vsaddu_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: .LBB50_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
; CHECK-NEXT: ret
@@ -1304,11 +1304,11 @@ define <vscale x 16 x i32> @vsaddu_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vsaddu_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll b/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
index c62a1d17dd924..2a1bd8dd35a55 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
@@ -153,13 +153,15 @@ define <vscale x 2 x i32> @vwop_vscale_sext_i1i32_multiple_users(ptr %x, ptr %y,
; NO_FOLDING: # %bb.0:
; NO_FOLDING-NEXT: vsetvli a3, zero, e32, m1, ta, ma
; NO_FOLDING-NEXT: vlm.v v0, (a0)
+; NO_FOLDING-NEXT: vlm.v v10, (a1)
+; NO_FOLDING-NEXT: vlm.v v11, (a2)
; NO_FOLDING-NEXT: vmv.v.i v8, 0
; NO_FOLDING-NEXT: vmerge.vim v9, v8, -1, v0
-; NO_FOLDING-NEXT: vlm.v v0, (a1)
+; NO_FOLDING-NEXT: vmv.v.v v0, v10
; NO_FOLDING-NEXT: vmerge.vim v10, v8, -1, v0
-; NO_FOLDING-NEXT: vlm.v v0, (a2)
-; NO_FOLDING-NEXT: vmul.vv v10, v9, v10
+; NO_FOLDING-NEXT: vmv.v.v v0, v11
; NO_FOLDING-NEXT: vmerge.vim v8, v8, -1, v0
+; NO_FOLDING-NEXT: vmul.vv v10, v9, v10
; NO_FOLDING-NEXT: vadd.vv v11, v9, v8
; NO_FOLDING-NEXT: vsub.vv v8, v9, v8
; NO_FOLDING-NEXT: vor.vv v9, v10, v11
@@ -170,13 +172,15 @@ define <vscale x 2 x i32> @vwop_vscale_sext_i1i32_multiple_users(ptr %x, ptr %y,
; FOLDING: # %bb.0:
; FOLDING-NEXT: vsetvli a3, zero, e32, m1, ta, ma
; FOLDING-NEXT: vlm.v v0, (a0)
+; FOLDING-NEXT: vlm.v v10, (a1)
+; FOLDING-NEXT: vlm.v v11, (a2)
; FOLDING-NEXT: vmv.v.i v8, 0
; FOLDING-NEXT: vmerge.vim v9, v8, -1, v0
-; FOLDING-NEXT: vlm.v v0, (a1)
+; FOLDING-NEXT: vmv.v.v v0, v10
; FOLDING-NEXT: vmerge.vim v10, v8, -1, v0
-; FOLDING-NEXT: vlm.v v0, (a2)
-; FOLDING-NEXT: vmul.vv v10, v9, v10
+; FOLDING-NEXT: vmv.v.v v0, v11
; FOLDING-NEXT: vmerge.vim v8, v8, -1, v0
+; FOLDING-NEXT: vmul.vv v10, v9, v10
; FOLDING-NEXT: vadd.vv v11, v9, v8
; FOLDING-NEXT: vsub.vv v8, v9, v8
; FOLDING-NEXT: vor.vv v9, v10, v11
@@ -201,13 +205,15 @@ define <vscale x 2 x i8> @vwop_vscale_sext_i1i8_multiple_users(ptr %x, ptr %y, p
; NO_FOLDING: # %bb.0:
; NO_FOLDING-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; NO_FOLDING-NEXT: vlm.v v0, (a0)
+; NO_FOLDING-NEXT: vlm.v v10, (a1)
+; NO_FOLDING-NEXT: vlm.v v11, (a2)
; NO_FOLDING-NEXT: vmv.v.i v8, 0
; NO_FOLDING-NEXT: vmerge.vim v9, v8, -1, v0
-; NO_FOLDING-NEXT: vlm.v v0, (a1)
+; NO_FOLDING-NEXT: vmv1r.v v0, v10
; NO_FOLDING-NEXT: vmerge.vim v10, v8, -1, v0
-; NO_FOLDING-NEXT: vlm.v v0, (a2)
-; NO_FOLDING-NEXT: vmul.vv v10, v9, v10
+; NO_FOLDING-NEXT: vmv1r.v v0, v11
; NO_FOLDING-NEXT: vmerge.vim v8, v8, -1, v0
+; NO_FOLDING-NEXT: vmul.vv v10, v9, v10
; NO_FOLDING-NEXT: vadd.vv v11, v9, v8
; NO_FOLDING-NEXT: vsub.vv v8, v9, v8
; NO_FOLDING-NEXT: vor.vv v9, v10, v11
@@ -218,13 +224,15 @@ define <vscale x 2 x i8> @vwop_vscale_sext_i1i8_multiple_users(ptr %x, ptr %y, p
; FOLDING: # %bb.0:
; FOLDING-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; FOLDING-NEXT: vlm.v v0, (a0)
+; FOLDING-NEXT: vlm.v v10, (a1)
+; FOLDING-NEXT: vlm.v v11, (a2)
; FOLDING-NEXT: vmv.v.i v8, 0
; FOLDING-NEXT: vmerge.vim v9, v8, -1, v0
-; FOLDING-NEXT: vlm.v v0, (a1)
+; FOLDING-NEXT: vmv1r.v v0, v10
; FOLDING-NEXT: vmerge.vim v10, v8, -1, v0
-; FOLDING-NEXT: vlm.v v0, (a2)
-; FOLDING-NEXT: vmul.vv v10, v9, v10
+; FOLDING-NEXT: vmv1r.v v0, v11
; FOLDING-NEXT: vmerge.vim v8, v8, -1, v0
+; FOLDING-NEXT: vmul.vv v10, v9, v10
; FOLDING-NEXT: vadd.vv v11, v9, v8
; FOLDING-NEXT: vsub.vv v8, v9, v8
; FOLDING-NEXT: vor.vv v9, v10, v11
@@ -428,36 +436,36 @@ define <vscale x 2 x i32> @vwop_vscale_zext_i1i32_multiple_users(ptr %x, ptr %y,
; NO_FOLDING: # %bb.0:
; NO_FOLDING-NEXT: vsetvli a3, zero, e32, m1, ta, mu
; NO_FOLDING-NEXT: vlm.v v0, (a0)
-; NO_FOLDING-NEXT: vlm.v v8, (a2)
-; NO_FOLDING-NEXT: vmv.v.i v9, 0
-; NO_FOLDING-NEXT: vmerge.vim v10, v9, 1, v0
-; NO_FOLDING-NEXT: vlm.v v9, (a1)
-; NO_FOLDING-NEXT: vmv.v.v v11, v10
-; NO_FOLDING-NEXT: vmv.v.v v0, v8
-; NO_FOLDING-NEXT: vadd.vi v11, v10, 1, v0.t
-; NO_FOLDING-NEXT: vmv.v.v v12, v10
-; NO_FOLDING-NEXT: vadd.vi v12, v10, -1, v0.t
-; NO_FOLDING-NEXT: vmv.v.v v0, v9
-; NO_FOLDING-NEXT: vor.vv v11, v11, v10, v0.t
-; NO_FOLDING-NEXT: vor.vv v8, v11, v12
+; NO_FOLDING-NEXT: vlm.v v10, (a1)
+; NO_FOLDING-NEXT: vlm.v v11, (a2)
+; NO_FOLDING-NEXT: vmv.v.i v8, 0
+; NO_FOLDING-NEXT: vmerge.vim v8, v8, 1, v0
+; NO_FOLDING-NEXT: vmv.v.v v9, v8
+; NO_FOLDING-NEXT: vmv.v.v v0, v11
+; NO_FOLDING-NEXT: vadd.vi v9, v8, 1, v0.t
+; NO_FOLDING-NEXT: vmv.v.v v0, v10
+; NO_FOLDING-NEXT: vor.vv v9, v9, v8, v0.t
+; NO_FOLDING-NEXT: vmv.v.v v0, v11
+; NO_FOLDING-NEXT: vadd.vi v8, v8, -1, v0.t
+; NO_FOLDING-NEXT: vor.vv v8, v9, v8
; NO_FOLDING-NEXT: ret
;
; FOLDING-LABEL: vwop_vscale_zext_i1i32_multiple_users:
; FOLDING: # %bb.0:
; FOLDING-NEXT: vsetvli a3, zero, e32, m1, ta, mu
; FOLDING-NEXT: vlm.v v0, (a0)
-; FOLDING-NEXT: vlm.v v8, (a2)
-; FOLDING-NEXT: vmv.v.i v9, 0
-; FOLDING-NEXT: vmerge.vim v10, v9, 1, v0
-; FOLDING-NEXT: vlm.v v9, (a1)
-; FOLDING-NEXT: vmv.v.v v11, v10
-; FOLDING-NEXT: vmv.v.v v0, v8
-; FOLDING-NEXT: vadd.vi v11, v10, 1, v0.t
-; FOLDING-NEXT: vmv.v.v v12, v10
-; FOLDING-NEXT: vadd.vi v12, v10, -1, v0.t
-; FOLDING-NEXT: vmv.v.v v0, v9
-; FOLDING-NEXT: vor.vv v11, v11, v10, v0.t
-; FOLDING-NEXT: vor.vv v8, v11, v12
+; FOLDING-NEXT: vlm.v v10, (a1)
+; FOLDING-NEXT: vlm.v v11, (a2)
+; FOLDING-NEXT: vmv.v.i v8, 0
+; FOLDING-NEXT: vmerge.vim v8, v8, 1, v0
+; FOLDING-NEXT: vmv.v.v v9, v8
+; FOLDING-NEXT: vmv.v.v v0, v11
+; FOLDING-NEXT: vadd.vi v9, v8, 1, v0.t
+; FOLDING-NEXT: vmv.v.v v0, v10
+; FOLDING-NEXT: vor.vv v9, v9, v8, v0.t
+; FOLDING-NEXT: vmv.v.v v0, v11
+; FOLDING-NEXT: vadd.vi v8, v8, -1, v0.t
+; FOLDING-NEXT: vor.vv v8, v9, v8
; FOLDING-NEXT: ret
%a = load <vscale x 2 x i1>, ptr %x
%b = load <vscale x 2 x i1>, ptr %y
@@ -478,36 +486,36 @@ define <vscale x 2 x i8> @vwop_vscale_zext_i1i8_multiple_users(ptr %x, ptr %y, p
; NO_FOLDING: # %bb.0:
; NO_FOLDING-NEXT: vsetvli a3, zero, e8, mf4, ta, mu
; NO_FOLDING-NEXT: vlm.v v0, (a0)
-; NO_FOLDING-NEXT: vlm.v v8, (a2)
-; NO_FOLDING-NEXT: vmv.v.i v9, 0
-; NO_FOLDING-NEXT: vmerge.vim v10, v9, 1, v0
-; NO_FOLDING-NEXT: vlm.v v9, (a1)
-; NO_FOLDING-NEXT: vmv1r.v v11, v10
-; NO_FOLDING-NEXT: vmv1r.v v0, v8
-; NO_FOLDING-NEXT: vadd.vi v11, v10, 1, v0.t
-; NO_FOLDING-NEXT: vmv1r.v v12, v10
-; NO_FOLDING-NEXT: vadd.vi v12, v10, -1, v0.t
-; NO_FOLDING-NEXT: vmv1r.v v0, v9
-; NO_FOLDING-NEXT: vor.vv v11, v11, v10, v0.t
-; NO_FOLDING-NEXT: vor.vv v8, v11, v12
+; NO_FOLDING-NEXT: vlm.v v10, (a1)
+; NO_FOLDING-NEXT: vlm.v v11, (a2)
+; NO_FOLDING-NEXT: vmv.v.i v8, 0
+; NO_FOLDING-NEXT: vmerge.vim v8, v8, 1, v0
+; NO_FOLDING-NEXT: vmv1r.v v9, v8
+; NO_FOLDING-NEXT: vmv1r.v v0, v11
+; NO_FOLDING-NEXT: vadd.vi v9, v8, 1, v0.t
+; NO_FOLDING-NEXT: vmv1r.v v0, v10
+; NO_FOLDING-NEXT: vor.vv v9, v9, v8, v0.t
+; NO_FOLDING-NEXT: vmv1r.v v0, v11
+; NO_FOLDING-NEXT: vadd.vi v8, v8, -1, v0.t
+; NO_FOLDING-NEXT: vor.vv v8, v9, v8
; NO_FOLDING-NEXT: ret
;
; FOLDING-LABEL: vwop_vscale_zext_i1i8_multiple_users:
; FOLDING: # %bb.0:
; FOLDING-NEXT: vsetvli a3, zero, e8, mf4, ta, mu
; FOLDING-NEXT: vlm.v v0, (a0)
-; FOLDING-NEXT: vlm.v v8, (a2)
-; FOLDING-NEXT: vmv.v.i v9, 0
-; FOLDING-NEXT: vmerge.vim v10, v9, 1, v0
-; FOLDING-NEXT: vlm.v v9, (a1)
-; FOLDING-NEXT: vmv1r.v v11, v10
-; FOLDING-NEXT: vmv1r.v v0, v8
-; FOLDING-NEXT: vadd.vi v11, v10, 1, v0.t
-; FOLDING-NEXT: vmv1r.v v12, v10
-; FOLDING-NEXT: vadd.vi v12, v10, -1, v0.t
-; FOLDING-NEXT: vmv1r.v v0, v9
-; FOLDING-NEXT: vor.vv v11, v11, v10, v0.t
-; FOLDING-NEXT: vor.vv v8, v11, v12
+; FOLDING-NEXT: vlm.v v10, (a1)
+; FOLDING-NEXT: vlm.v v11, (a2)
+; FOLDING-NEXT: vmv.v.i v8, 0
+; FOLDING-NEXT: vmerge.vim v8, v8, 1, v0
+; FOLDING-NEXT: vmv1r.v v9, v8
+; FOLDING-NEXT: vmv1r.v v0, v11
+; FOLDING-NEXT: vadd.vi v9, v8, 1, v0.t
+; FOLDING-NEXT: vmv1r.v v0, v10
+; FOLDING-NEXT: vor.vv v9, v9, v8, v0.t
+; FOLDING-NEXT: vmv1r.v v0, v11
+; FOLDING-NEXT: vadd.vi v8, v8, -1, v0.t
+; FOLDING-NEXT: vor.vv v8, v9, v8
; FOLDING-NEXT: ret
%a = load <vscale x 2 x i1>, ptr %x
%b = load <vscale x 2 x i1>, ptr %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
index 30044ad580143..1391f0a564708 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
@@ -494,17 +494,17 @@ define <vscale x 8 x double> @vfmerge_nzv_nxv8f64(<vscale x 8 x double> %va, <vs
define <vscale x 16 x double> @vselect_combine_regression(<vscale x 16 x i64> %va, <vscale x 16 x double> %vb) {
; CHECK-LABEL: vselect_combine_regression:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmv8r.v v24, v16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu
+; CHECK-NEXT: vmseq.vi v24, v16, 0
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: vle64.v v8, (a0), v0.t
-; CHECK-NEXT: vmseq.vi v0, v24, 0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vle64.v v16, (a0), v0.t
+; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vle64.v v16, (a1), v0.t
; CHECK-NEXT: ret
%cond = icmp eq <vscale x 16 x i64> %va, zeroinitializer
%sel = select <vscale x 16 x i1> %cond, <vscale x 16 x double> %vb, <vscale x 16 x double> zeroinitializer
@@ -522,15 +522,15 @@ define void @vselect_legalize_regression(<vscale x 16 x double> %a, <vscale x 16
; CHECK-NEXT: srli a2, a0, 3
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmand.mm v7, v0, v7
+; CHECK-NEXT: vmand.mm v0, v0, v7
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v7, a2
-; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: vslidedown.vx v7, v0, a2
; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, ma
-; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: vs8r.v v8, (a1)
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: vs8r.v v16, (a0)
; CHECK-NEXT: ret
%cond = and <vscale x 16 x i1> %ma, %mb
diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
index d1933560f2698..2ae06e31c17dc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
@@ -303,29 +303,29 @@ define <vscale x 32 x i32> @select_nxv32i32(<vscale x 32 x i1> %a, <vscale x 32
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a4, a3, 3
; CHECK-NEXT: slli a1, a3, 1
-; CHECK-NEXT: srli a3, a3, 2
; CHECK-NEXT: add a4, a0, a4
; CHECK-NEXT: sub a5, a2, a1
; CHECK-NEXT: vl8re32.v v24, (a4)
; CHECK-NEXT: sltu a4, a2, a5
; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a4, a4, a5
; CHECK-NEXT: vl8re32.v v8, (a0)
+; CHECK-NEXT: srli a3, a3, 2
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: and a4, a4, a5
; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: bltu a2, a1, .LBB27_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB27_2:
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
; CHECK-NEXT: csrr a0, vlenb
@@ -342,21 +342,21 @@ define <vscale x 32 x i32> @select_nxv32i32(<vscale x 32 x i1> %a, <vscale x 32
define <vscale x 32 x i32> @select_evl_nxv32i32(<vscale x 32 x i1> %a, <vscale x 32 x i32> %b, <vscale x 32 x i32> %c) {
; RV32-LABEL: select_evl_nxv32i32:
; RV32: # %bb.0:
-; RV32-NEXT: vl8re32.v v24, (a0)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
-; RV32-NEXT: vmerge.vvm v8, v24, v8, v0
+; RV32-NEXT: vl8re32.v v24, (a0)
; RV32-NEXT: slli a2, a1, 3
; RV32-NEXT: add a0, a0, a2
; RV32-NEXT: slli a2, a1, 1
; RV32-NEXT: sub a2, a1, a2
+; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; RV32-NEXT: vmerge.vvm v8, v24, v8, v0
; RV32-NEXT: vl8re32.v v24, (a0)
; RV32-NEXT: sltu a0, a1, a2
; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: srli a1, a1, 2
-; RV32-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; RV32-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; RV32-NEXT: vslidedown.vx v0, v0, a1
-; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; RV32-NEXT: vmerge.vvm v16, v24, v16, v0
; RV32-NEXT: ret
@@ -371,29 +371,29 @@ define <vscale x 32 x i32> @select_evl_nxv32i32(<vscale x 32 x i1> %a, <vscale x
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v7, v0
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a3, a1, 3
; RV64-NEXT: slli a2, a1, 1
-; RV64-NEXT: srli a4, a1, 2
; RV64-NEXT: add a3, a0, a3
-; RV64-NEXT: sub a5, a1, a2
+; RV64-NEXT: sub a4, a1, a2
; RV64-NEXT: vl8re32.v v24, (a3)
-; RV64-NEXT: sltu a3, a1, a5
+; RV64-NEXT: sltu a3, a1, a4
; RV64-NEXT: addi a3, a3, -1
+; RV64-NEXT: and a3, a3, a4
; RV64-NEXT: vl8re32.v v8, (a0)
-; RV64-NEXT: vslidedown.vx v0, v0, a4
-; RV64-NEXT: and a3, a3, a5
+; RV64-NEXT: srli a0, a1, 2
+; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v7, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a0
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vmerge.vvm v16, v24, v16, v0
; RV64-NEXT: bltu a1, a2, .LBB28_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a1, a2
; RV64-NEXT: .LBB28_2:
-; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV64-NEXT: vmerge.vvm v8, v8, v24, v0
; RV64-NEXT: csrr a0, vlenb
@@ -632,28 +632,28 @@ define <vscale x 16 x double> @select_nxv16f64(<vscale x 16 x i1> %a, <vscale x
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a3, a1, 3
; CHECK-NEXT: sub a4, a2, a1
; CHECK-NEXT: add a3, a0, a3
-; CHECK-NEXT: sltu a5, a2, a4
; CHECK-NEXT: vl8re64.v v24, (a3)
-; CHECK-NEXT: addi a5, a5, -1
-; CHECK-NEXT: srli a3, a1, 3
+; CHECK-NEXT: sltu a3, a2, a4
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a3, a3, a4
; CHECK-NEXT: vl8re64.v v8, (a0)
-; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: and a4, a5, a4
-; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; CHECK-NEXT: srli a0, a1, 3
+; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a0
+; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: bltu a2, a1, .LBB50_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB50_2:
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
; CHECK-NEXT: csrr a0, vlenb
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
index 5b56bfc535b75..eb3b93996fbeb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
@@ -97,10 +97,10 @@ define void @test6(ptr nocapture readonly %A, ptr nocapture %B, i64 %n) {
; CHECK-NEXT: add a5, a0, a4
; CHECK-NEXT: vle32.v v8, (a5)
; CHECK-NEXT: add a3, a3, a2
+; CHECK-NEXT: add a4, a4, a1
; CHECK-NEXT: vmsle.vi v9, v8, -3
; CHECK-NEXT: vmsgt.vi v10, v8, 2
; CHECK-NEXT: vmor.mm v0, v9, v10
-; CHECK-NEXT: add a4, a4, a1
; CHECK-NEXT: vse32.v v8, (a4), v0.t
; CHECK-NEXT: vsetvli a2, a2, e32, m1, ta, ma
; CHECK-NEXT: bnez a2, .LBB5_2
@@ -809,30 +809,32 @@ entry:
define void @coalesce_vl_clobber(ptr %p) {
; CHECK-LABEL: coalesce_vl_clobber:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: li a2, 0
; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: li a2, 0
; CHECK-NEXT: vsetivli zero, 0, e8, mf2, ta, ma
-; CHECK-NEXT: vmclr.m v8
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
+; CHECK-NEXT: vmclr.m v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv1r.v v12, v0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: .LBB43_1: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vsetvli a3, a2, e8, mf8, ta, ma
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: slli a1, a1, 32
-; CHECK-NEXT: vsetivli zero, 0, e8, mf2, ta, mu
+; CHECK-NEXT: slli a2, a2, 32
+; CHECK-NEXT: vsetvli a3, a1, e8, mf8, ta, ma
+; CHECK-NEXT: vsetivli zero, 0, e8, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: srli a2, a2, 32
+; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
+; CHECK-NEXT: vsetvli zero, a3, e32, m2, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: srli a1, a1, 32
-; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
-; CHECK-NEXT: vslideup.vx v10, v9, a1, v0.t
+; CHECK-NEXT: vsetivli zero, 0, e8, mf2, ta, mu
+; CHECK-NEXT: vslideup.vx v9, v8, a2, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmsne.vi v0, v10, 0, v0.t
+; CHECK-NEXT: vmsne.vi v0, v9, 0, v0.t
; CHECK-NEXT: vsetvli zero, a3, e32, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vse32.v v10, (a0), v0.t
-; CHECK-NEXT: li a2, 1
-; CHECK-NEXT: mv a1, a3
+; CHECK-NEXT: li a1, 1
+; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: j .LBB43_1
entry:
br label %vector.body
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
index 07411b1c7ae08..61de230f9c8d1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
@@ -137,11 +137,11 @@ define <vscale x 2 x i64> @vsext_nxv2i32_nxv2i64_unmasked(<vscale x 2 x i32> %a,
define <vscale x 32 x i32> @vsext_nxv32i8_nxv32i32(<vscale x 32 x i8> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vsext_nxv32i8_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
index 7f96da141c363..6a96645620d0c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
@@ -471,11 +471,11 @@ define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i64_unmasked(<vscale x 2 x i64
define <vscale x 32 x half> @vsitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: vsitofp_nxv32f16_nxv32i32:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFH-NEXT: vmv1r.v v24, v0
; ZVFH-NEXT: csrr a1, vlenb
; ZVFH-NEXT: srli a2, a1, 2
; ZVFH-NEXT: slli a1, a1, 1
+; ZVFH-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; ZVFH-NEXT: vmv1r.v v24, v0
; ZVFH-NEXT: vslidedown.vx v0, v0, a2
; ZVFH-NEXT: sub a2, a0, a1
; ZVFH-NEXT: sltu a3, a0, a2
@@ -495,11 +495,11 @@ define <vscale x 32 x half> @vsitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va,
;
; ZVFHMIN-LABEL: vsitofp_nxv32f16_nxv32i32:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: srli a2, a1, 2
; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
; ZVFHMIN-NEXT: sub a2, a0, a1
; ZVFHMIN-NEXT: sltu a3, a0, a2
@@ -527,11 +527,11 @@ define <vscale x 32 x half> @vsitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va,
define <vscale x 32 x float> @vsitofp_nxv32f32_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_nxv32f32_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
index 0ac2ef7e251c0..6c0160591f245 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
@@ -569,7 +569,7 @@ define <vscale x 128 x i8> @vssub_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
; CHECK-LABEL: vssub_vi_nxv128i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
@@ -584,7 +584,7 @@ define <vscale x 128 x i8> @vssub_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: .LBB50_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a2, v0.t
; CHECK-NEXT: ret
@@ -1346,11 +1346,11 @@ define <vscale x 16 x i32> @vssub_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vssub_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
index bde279a4d1f2b..a041b8478b0bb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
@@ -567,7 +567,7 @@ define <vscale x 128 x i8> @vssubu_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK-LABEL: vssubu_vi_nxv128i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
@@ -582,7 +582,7 @@ define <vscale x 128 x i8> @vssubu_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: .LBB50_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a2, v0.t
; CHECK-NEXT: ret
@@ -1344,11 +1344,11 @@ define <vscale x 16 x i32> @vssubu_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vssubu_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
index 0c1ca369521f7..63f6cadbc123c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
@@ -141,24 +141,24 @@ define <vscale x 2 x i16> @vtrunc_nxv2i16_nxv2i64_unmasked(<vscale x 2 x i64> %a
define <vscale x 15 x i16> @vtrunc_nxv15i16_nxv15i64(<vscale x 15 x i64> %a, <vscale x 15 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv15i16_nxv15i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v28, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v28, v16, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v18, v28, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v18, v24, 0, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB12_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB12_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v28
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v20, v8, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
@@ -194,25 +194,25 @@ define <vscale x 2 x i32> @vtrunc_nxv2i32_nxv2i64_unmasked(<vscale x 2 x i64> %a
define <vscale x 32 x i7> @vtrunc_nxv32i7_nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv32i7_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v28, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v28, v16, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v18, v28, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v18, v24, 0, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB15_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB15_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v28
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v20, v8, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
@@ -226,25 +226,25 @@ define <vscale x 32 x i7> @vtrunc_nxv32i7_nxv32i32(<vscale x 32 x i32> %a, <vsca
define <vscale x 32 x i8> @vtrunc_nxv32i8_nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv32i8_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v28, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a2, a3, a2
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vnsrl.wi v28, v16, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
-; CHECK-NEXT: vnsrl.wi v18, v28, 0, v0.t
+; CHECK-NEXT: vnsrl.wi v18, v24, 0, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB16_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB16_2:
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmv1r.v v0, v28
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v20, v8, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
@@ -264,8 +264,6 @@ define <vscale x 32 x i32> @vtrunc_nxv32i64_nxv32i32(<vscale x 32 x i64> %a, <vs
; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
@@ -289,10 +287,13 @@ define <vscale x 32 x i32> @vtrunc_nxv32i64_nxv32i32(<vscale x 32 x i64> %a, <vs
; CHECK-NEXT: and a4, a7, a4
; CHECK-NEXT: srli a7, a1, 2
; CHECK-NEXT: vl8re64.v v8, (a6)
-; CHECK-NEXT: vslidedown.vx v24, v0, a7
+; CHECK-NEXT: vsetvli a6, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v25, v0, a7
+; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v6, v0, a5
-; CHECK-NEXT: vslidedown.vx v0, v24, a5
+; CHECK-NEXT: vmv1r.v v24, v25
+; CHECK-NEXT: vslidedown.vx v0, v25, a5
; CHECK-NEXT: bltu a0, a1, .LBB17_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -310,9 +311,9 @@ define <vscale x 32 x i32> @vtrunc_nxv32i64_nxv32i32(<vscale x 32 x i64> %a, <vs
; CHECK-NEXT: sltu a3, a2, a0
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a0, a3, a0
-; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: addi a3, sp, 16
; CHECK-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v12, v16, 0, v0.t
; CHECK-NEXT: bltu a2, a1, .LBB17_6
diff --git a/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
index c0c749ebf3186..a23fb0c7db18b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
@@ -471,11 +471,11 @@ define <vscale x 2 x double> @vuitofp_nxv2f64_nxv2i64_unmasked(<vscale x 2 x i64
define <vscale x 32 x half> @vuitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: vuitofp_nxv32f16_nxv32i32:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFH-NEXT: vmv1r.v v24, v0
; ZVFH-NEXT: csrr a1, vlenb
; ZVFH-NEXT: srli a2, a1, 2
; ZVFH-NEXT: slli a1, a1, 1
+; ZVFH-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; ZVFH-NEXT: vmv1r.v v24, v0
; ZVFH-NEXT: vslidedown.vx v0, v0, a2
; ZVFH-NEXT: sub a2, a0, a1
; ZVFH-NEXT: sltu a3, a0, a2
@@ -495,11 +495,11 @@ define <vscale x 32 x half> @vuitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va,
;
; ZVFHMIN-LABEL: vuitofp_nxv32f16_nxv32i32:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: srli a2, a1, 2
; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
; ZVFHMIN-NEXT: sub a2, a0, a1
; ZVFHMIN-NEXT: sltu a3, a0, a2
@@ -527,11 +527,11 @@ define <vscale x 32 x half> @vuitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va,
define <vscale x 32 x float> @vuitofp_nxv32f32_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_nxv32f32_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd-mask-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd-mask-sdnode.ll
index 747fb5a3e7ff8..aa01c5c95a944 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwadd-mask-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwadd-mask-sdnode.ll
@@ -5,13 +5,12 @@
define <vscale x 8 x i64> @vwadd_wv_mask_v8i32(<vscale x 8 x i32> %x, <vscale x 8 x i64> %y) {
; CHECK-LABEL: vwadd_wv_mask_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: li a0, 42
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vmslt.vx v0, v8, a0
-; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m4, tu, mu
-; CHECK-NEXT: vwadd.wv v8, v8, v24, v0.t
+; CHECK-NEXT: vwadd.wv v16, v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%mask = icmp slt <vscale x 8 x i32> %x, splat (i32 42)
%a = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %x, <vscale x 8 x i32> zeroinitializer
@@ -23,13 +22,12 @@ define <vscale x 8 x i64> @vwadd_wv_mask_v8i32(<vscale x 8 x i32> %x, <vscale x
define <vscale x 8 x i64> @vwaddu_wv_mask_v8i32(<vscale x 8 x i32> %x, <vscale x 8 x i64> %y) {
; CHECK-LABEL: vwaddu_wv_mask_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: li a0, 42
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vmslt.vx v0, v8, a0
-; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m4, tu, mu
-; CHECK-NEXT: vwaddu.wv v8, v8, v24, v0.t
+; CHECK-NEXT: vwaddu.wv v16, v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%mask = icmp slt <vscale x 8 x i32> %x, splat (i32 42)
%a = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %x, <vscale x 8 x i32> zeroinitializer
@@ -60,13 +58,12 @@ define <vscale x 8 x i64> @vwaddu_vv_mask_v8i32(<vscale x 8 x i32> %x, <vscale x
define <vscale x 8 x i64> @vwadd_wv_mask_v8i32_commutative(<vscale x 8 x i32> %x, <vscale x 8 x i64> %y) {
; CHECK-LABEL: vwadd_wv_mask_v8i32_commutative:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: li a0, 42
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vmslt.vx v0, v8, a0
-; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m4, tu, mu
-; CHECK-NEXT: vwadd.wv v8, v8, v24, v0.t
+; CHECK-NEXT: vwadd.wv v16, v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%mask = icmp slt <vscale x 8 x i32> %x, splat (i32 42)
%a = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %x, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsub-mask-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwsub-mask-sdnode.ll
index 22f9f97373415..2d3a3e16bd9e4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsub-mask-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsub-mask-sdnode.ll
@@ -5,13 +5,12 @@
define <vscale x 8 x i64> @vwsub_wv_mask_v8i32(<vscale x 8 x i32> %x, <vscale x 8 x i64> %y) {
; CHECK-LABEL: vwsub_wv_mask_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: li a0, 42
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vmslt.vx v0, v8, a0
-; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m4, tu, mu
-; CHECK-NEXT: vwsub.wv v8, v8, v24, v0.t
+; CHECK-NEXT: vwsub.wv v16, v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%mask = icmp slt <vscale x 8 x i32> %x, splat (i32 42)
%a = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %x, <vscale x 8 x i32> zeroinitializer
@@ -23,13 +22,12 @@ define <vscale x 8 x i64> @vwsub_wv_mask_v8i32(<vscale x 8 x i32> %x, <vscale x
define <vscale x 8 x i64> @vwsubu_wv_mask_v8i32(<vscale x 8 x i32> %x, <vscale x 8 x i64> %y) {
; CHECK-LABEL: vwsubu_wv_mask_v8i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: li a0, 42
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vmslt.vx v0, v8, a0
-; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m4, tu, mu
-; CHECK-NEXT: vwsubu.wv v8, v8, v24, v0.t
+; CHECK-NEXT: vwsubu.wv v16, v16, v8, v0.t
+; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%mask = icmp slt <vscale x 8 x i32> %x, splat (i32 42)
%a = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %x, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
index 9713b617b8384..d3ec428c825ee 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
@@ -137,11 +137,11 @@ define <vscale x 2 x i64> @vzext_nxv2i32_nxv2i64_unmasked(<vscale x 2 x i32> %a,
define <vscale x 32 x i32> @vzext_nxv32i8_nxv32i32(<vscale x 32 x i8> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vzext_nxv32i8_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 2
; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: sltu a3, a0, a2
diff --git a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
index 06bbe5209df35..dc185945d9a0d 100644
--- a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
@@ -746,9 +746,9 @@ define void @test_srem_vec(ptr %X) nounwind {
; RV32MV-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32MV-NEXT: vand.vv v8, v8, v10
; RV32MV-NEXT: vand.vv v10, v12, v10
+; RV32MV-NEXT: vmv.v.i v12, 0
; RV32MV-NEXT: vmsne.vv v0, v8, v10
-; RV32MV-NEXT: vmv.v.i v8, 0
-; RV32MV-NEXT: vmerge.vim v8, v8, -1, v0
+; RV32MV-NEXT: vmerge.vim v8, v12, -1, v0
; RV32MV-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV32MV-NEXT: vslidedown.vi v12, v8, 1
; RV32MV-NEXT: vslidedown.vi v13, v8, 2
diff --git a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
index ba9c926c57152..186613fb685cc 100644
--- a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
@@ -584,15 +584,9 @@ define void @test_urem_vec(ptr %X) nounwind {
; RV32MV-NEXT: srli a1, a1, 21
; RV32MV-NEXT: vslide1down.vx v10, v10, a1
; RV32MV-NEXT: li a1, 2047
-; RV32MV-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV32MV-NEXT: vmv.v.i v11, 1
+; RV32MV-NEXT: addi a3, a3, -1527
; RV32MV-NEXT: andi a2, a2, 2047
-; RV32MV-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; RV32MV-NEXT: vslide1down.vx v10, v10, a2
-; RV32MV-NEXT: lui a2, %hi(.LCPI4_1)
-; RV32MV-NEXT: addi a2, a2, %lo(.LCPI4_1)
-; RV32MV-NEXT: addi a3, a3, -1527
-; RV32MV-NEXT: vsext.vf2 v12, v11
; RV32MV-NEXT: vslidedown.vi v10, v10, 1
; RV32MV-NEXT: vsub.vv v8, v10, v8
; RV32MV-NEXT: vsetvli zero, zero, e32, m1, ta, ma
@@ -602,14 +596,20 @@ define void @test_urem_vec(ptr %X) nounwind {
; RV32MV-NEXT: vmul.vv v8, v8, v9
; RV32MV-NEXT: vadd.vv v9, v8, v8
; RV32MV-NEXT: vsll.vv v9, v9, v11
-; RV32MV-NEXT: vle16.v v10, (a2)
+; RV32MV-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32MV-NEXT: vmv.v.i v10, 1
+; RV32MV-NEXT: lui a2, %hi(.LCPI4_1)
+; RV32MV-NEXT: addi a2, a2, %lo(.LCPI4_1)
+; RV32MV-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV32MV-NEXT: vsext.vf2 v11, v10
; RV32MV-NEXT: vand.vx v8, v8, a1
-; RV32MV-NEXT: vsrl.vv v8, v8, v12
+; RV32MV-NEXT: vsrl.vv v8, v8, v11
+; RV32MV-NEXT: vle16.v v10, (a2)
; RV32MV-NEXT: vor.vv v8, v8, v9
+; RV32MV-NEXT: vmv.v.i v9, 0
; RV32MV-NEXT: vand.vx v8, v8, a1
; RV32MV-NEXT: vmsltu.vv v0, v10, v8
-; RV32MV-NEXT: vmv.v.i v8, 0
-; RV32MV-NEXT: vmerge.vim v8, v8, -1, v0
+; RV32MV-NEXT: vmerge.vim v8, v9, -1, v0
; RV32MV-NEXT: vslidedown.vi v9, v8, 2
; RV32MV-NEXT: vmv.x.s a1, v8
; RV32MV-NEXT: vslidedown.vi v8, v8, 1
@@ -645,15 +645,9 @@ define void @test_urem_vec(ptr %X) nounwind {
; RV64MV-NEXT: srli a2, a2, 53
; RV64MV-NEXT: vslide1down.vx v10, v10, a2
; RV64MV-NEXT: li a2, 2047
-; RV64MV-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64MV-NEXT: vmv.v.i v11, 1
+; RV64MV-NEXT: addi a3, a3, -1527
; RV64MV-NEXT: srli a1, a1, 22
-; RV64MV-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; RV64MV-NEXT: vslide1down.vx v10, v10, a1
-; RV64MV-NEXT: lui a1, %hi(.LCPI4_1)
-; RV64MV-NEXT: addi a1, a1, %lo(.LCPI4_1)
-; RV64MV-NEXT: addi a3, a3, -1527
-; RV64MV-NEXT: vsext.vf2 v12, v11
; RV64MV-NEXT: vslidedown.vi v10, v10, 1
; RV64MV-NEXT: vsub.vv v8, v10, v8
; RV64MV-NEXT: vsetvli zero, zero, e32, m1, ta, ma
@@ -663,14 +657,20 @@ define void @test_urem_vec(ptr %X) nounwind {
; RV64MV-NEXT: vmul.vv v8, v8, v9
; RV64MV-NEXT: vadd.vv v9, v8, v8
; RV64MV-NEXT: vsll.vv v9, v9, v11
-; RV64MV-NEXT: vle16.v v10, (a1)
+; RV64MV-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64MV-NEXT: vmv.v.i v10, 1
+; RV64MV-NEXT: lui a1, %hi(.LCPI4_1)
+; RV64MV-NEXT: addi a1, a1, %lo(.LCPI4_1)
+; RV64MV-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; RV64MV-NEXT: vsext.vf2 v11, v10
; RV64MV-NEXT: vand.vx v8, v8, a2
-; RV64MV-NEXT: vsrl.vv v8, v8, v12
+; RV64MV-NEXT: vsrl.vv v8, v8, v11
+; RV64MV-NEXT: vle16.v v10, (a1)
; RV64MV-NEXT: vor.vv v8, v8, v9
+; RV64MV-NEXT: vmv.v.i v9, 0
; RV64MV-NEXT: vand.vx v8, v8, a2
; RV64MV-NEXT: vmsltu.vv v0, v10, v8
-; RV64MV-NEXT: vmv.v.i v8, 0
-; RV64MV-NEXT: vmerge.vim v8, v8, -1, v0
+; RV64MV-NEXT: vmerge.vim v8, v9, -1, v0
; RV64MV-NEXT: vmv.x.s a1, v8
; RV64MV-NEXT: vslidedown.vi v9, v8, 1
; RV64MV-NEXT: vslidedown.vi v8, v8, 2
>From 336897f7b90b65f1e7678913ee1a70004e1cad98 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Wed, 21 Jan 2026 18:38:29 +0800
Subject: [PATCH 2/5] [RISCV] Adjust mask mutation to fix errors
---
.../RISCV/RISCVVectorMaskDAGMutation.cpp | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp b/llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp
index 3bd2705f021a6..419886b9b5deb 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp
@@ -43,6 +43,11 @@
namespace llvm {
+static bool isCopyFromV0(const MachineInstr &MI) {
+ return MI.isFullCopy() && MI.getOperand(1).getReg() == RISCV::V0 &&
+ MI.getOperand(0).getReg().isVirtual();
+}
+
static bool isCopyToV0(const MachineInstr &MI) {
return MI.isFullCopy() && MI.getOperand(0).getReg() == RISCV::V0 &&
MI.getOperand(1).getReg().isVirtual();
@@ -72,8 +77,40 @@ class RISCVVectorMaskDAGMutation : public ScheduleDAGMutation {
void apply(ScheduleDAGInstrs *DAG) override {
SUnit *NearestUseV0SU = nullptr;
SmallVector<SUnit *, 2> DefMask;
+ SUnit *CopyFromV0 = nullptr;
+ SUnit *NearestHasVMV0OpSU = nullptr;
+
+ auto HasVMV0Op = [&](const MachineInstr *MI) {
+ for (const MachineOperand &Use : MI->uses()) {
+ if (!Use.isReg())
+ continue;
+ Register Reg = Use.getReg();
+ if (!Reg.isVirtual())
+ continue;
+ if (DAG->MRI.getRegClass(Reg)->getID() == RISCV::VMV0RegClassID)
+ return true;
+ }
+ return false;
+ };
+
for (SUnit &SU : DAG->SUnits) {
const MachineInstr *MI = SU.getInstr();
+ // The copies of v0 should not go accross these instructions with vmv0
+ // operands.
+ if (HasVMV0Op(MI)) {
+ NearestHasVMV0OpSU = &SU;
+ if (CopyFromV0) {
+ DAG->addEdge(&SU, SDep(CopyFromV0, SDep::Artificial));
+ CopyFromV0 = nullptr;
+ }
+ }
+
+ if (NearestHasVMV0OpSU && NearestHasVMV0OpSU != &SU && isCopyToV0(*MI))
+ DAG->addEdge(&SU, SDep(NearestHasVMV0OpSU, SDep::Artificial));
+
+ if (isCopyFromV0(*MI))
+ CopyFromV0 = &SU;
+
bool UseV0 = MI->findRegisterUseOperand(RISCV::V0, TRI);
if (isSoleUseCopyToV0(SU) && !UseV0)
DefMask.push_back(&SU);
>From 795e56f83f824167e27e3cfbdd47014fb7e88632 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Wed, 21 Jan 2026 19:22:53 +0800
Subject: [PATCH 3/5] [RISCV] Change the limit of register pressure VMV0 to 1
---
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 7 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.h | 3 +
.../CodeGen/RISCV/combine-storetomstore.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/abs-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll | 60 +-
llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll | 8 +-
.../RISCV/rvv/combine-reduce-add-to-vcpop.ll | 494 ++++---
.../RISCV/rvv/constant-folding-crash.ll | 10 +-
llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll | 72 +-
llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll | 187 ++-
llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll | 88 +-
llvm/test/CodeGen/RISCV/rvv/expandload.ll | 309 ++--
llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll | 42 +-
.../CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-bitreverse-vp.ll | 61 +-
.../RISCV/rvv/fixed-vectors-bswap-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-ceil-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-ctlz-vp.ll | 1084 +++++---------
.../RISCV/rvv/fixed-vectors-ctpop-vp.ll | 362 +++--
.../RISCV/rvv/fixed-vectors-cttz-vp.ll | 888 +++++-------
.../RISCV/rvv/fixed-vectors-extract-i1.ll | 108 +-
.../RISCV/rvv/fixed-vectors-floor-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-fmaximum-vp.ll | 163 +--
.../RISCV/rvv/fixed-vectors-fminimum-vp.ll | 163 +--
.../RISCV/rvv/fixed-vectors-fpext-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-fptosi-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-fptoui-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-fptrunc-vp.ll | 2 +-
.../rvv/fixed-vectors-interleaved-access.ll | 712 ++++-----
.../rvv/fixed-vectors-reduction-fp-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-reduction-fp.ll | 150 +-
.../rvv/fixed-vectors-reduction-int-vp.ll | 4 +-
.../rvv/fixed-vectors-reduction-mask-vp.ll | 18 +-
.../RISCV/rvv/fixed-vectors-round-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-roundeven-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-roundtozero-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-setcc-int-vp.ll | 30 +-
.../RISCV/rvv/fixed-vectors-sext-vp.ll | 2 +-
.../rvv/fixed-vectors-shuffle-deinterleave.ll | 6 +-
.../fixed-vectors-shuffle-deinterleave2.ll | 50 +-
.../RISCV/rvv/fixed-vectors-sitofp-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-strided-vpload.ll | 29 +-
.../RISCV/rvv/fixed-vectors-trunc-vp.ll | 642 ++++-----
.../RISCV/rvv/fixed-vectors-uitofp-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-vadd-vp.ll | 15 +-
.../RISCV/rvv/fixed-vectors-vfabs-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-vfneg-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-vfsqrt-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-vmax-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-vmaxu-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-vmin-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-vminu-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-vsadd-vp.ll | 15 +-
.../RISCV/rvv/fixed-vectors-vsaddu-vp.ll | 15 +-
.../RISCV/rvv/fixed-vectors-vselect-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-vssub-vp.ll | 13 +-
.../RISCV/rvv/fixed-vectors-vssubu-vp.ll | 13 +-
.../RISCV/rvv/fixed-vectors-zext-vp.ll | 2 +-
llvm/test/CodeGen/RISCV/rvv/floor-vp.ll | 8 +-
.../test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll | 66 +-
llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll | 473 +++---
.../test/CodeGen/RISCV/rvv/fminimum-sdnode.ll | 66 +-
llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll | 473 +++---
llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll | 141 +-
.../CodeGen/RISCV/rvv/insert-subvector.ll | 2 +-
llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll | 10 +-
.../test/CodeGen/RISCV/rvv/mscatter-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll | 16 +-
llvm/test/CodeGen/RISCV/rvv/pr165232.ll | 309 ++--
llvm/test/CodeGen/RISCV/rvv/pr88576.ll | 24 +-
.../CodeGen/RISCV/rvv/reproducer-pr146855.ll | 3 +-
llvm/test/CodeGen/RISCV/rvv/round-vp.ll | 8 +-
llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll | 8 +-
llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll | 8 +-
llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll | 592 ++++----
llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll | 64 +-
llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll | 44 +-
.../RISCV/rvv/vector-deinterleave-fixed.ll | 18 +-
.../CodeGen/RISCV/rvv/vector-deinterleave.ll | 256 ++--
.../RISCV/rvv/vector-interleave-store.ll | 12 +-
.../CodeGen/RISCV/rvv/vector-interleave.ll | 476 +++----
llvm/test/CodeGen/RISCV/rvv/vector-splice.ll | 308 ++--
llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll | 174 +--
llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll | 72 +-
llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll | 1269 ++++++++++-------
llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll | 18 +-
llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll | 72 +-
llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll | 44 +-
llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll | 44 +-
llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll | 44 +-
llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll | 44 +-
llvm/test/CodeGen/RISCV/rvv/vmseq.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmsge.ll | 32 +-
llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll | 32 +-
llvm/test/CodeGen/RISCV/rvv/vmsgt.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmsle.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmsleu.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmslt.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmsltu.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmsne.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll | 4 +-
.../rvv/vp-reverse-mask-fixed-vectors.ll | 16 +-
.../test/CodeGen/RISCV/rvv/vp-reverse-mask.ll | 28 +-
.../RISCV/rvv/vp-splice-mask-fixed-vectors.ll | 160 +--
.../RISCV/rvv/vp-splice-mask-vectors.ll | 274 ++--
.../RISCV/rvv/vp-vector-interleaved-access.ll | 62 +-
.../test/CodeGen/RISCV/rvv/vpgather-sdnode.ll | 34 +-
llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll | 110 +-
.../CodeGen/RISCV/rvv/vreductions-fp-vp.ll | 32 +-
.../CodeGen/RISCV/rvv/vreductions-int-vp.ll | 16 +-
.../CodeGen/RISCV/rvv/vreductions-mask-vp.ll | 24 +-
llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll | 36 +-
.../RISCV/rvv/vscale-vw-web-simplification.ll | 40 +-
llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll | 22 +-
llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll | 18 +-
llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll | 54 +-
llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll | 42 +-
llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll | 42 +-
llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll | 48 +-
llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll | 54 +-
llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll | 18 +-
136 files changed, 6011 insertions(+), 6870 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 52331a0952f70..7535da24d8524 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -859,6 +859,13 @@ float RISCVRegisterInfo::getSpillWeightScaleFactor(
return getRegClassWeight(RC).RegWeight;
}
+unsigned RISCVRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF,
+ unsigned Idx) const {
+ if (Idx == RISCV::RegisterPressureSets::VMV0)
+ return 1;
+ return RISCVGenRegisterInfo::getRegPressureSetLimit(MF, Idx);
+}
+
// Add two address hints to improve chances of being able to use a compressed
// instruction.
bool RISCVRegisterInfo::getRegAllocationHints(
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
index f29f85e4987f6..f0d5e9e387ab6 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -145,6 +145,9 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
float getSpillWeightScaleFactor(const TargetRegisterClass *RC) const override;
+ unsigned getRegPressureSetLimit(const MachineFunction &MF,
+ unsigned Idx) const override;
+
bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
SmallVectorImpl<MCPhysReg> &Hints,
const MachineFunction &MF, const VirtRegMap *VRM,
diff --git a/llvm/test/CodeGen/RISCV/combine-storetomstore.ll b/llvm/test/CodeGen/RISCV/combine-storetomstore.ll
index 19882d41b5445..ad0bcf57c78a9 100644
--- a/llvm/test/CodeGen/RISCV/combine-storetomstore.ll
+++ b/llvm/test/CodeGen/RISCV/combine-storetomstore.ll
@@ -212,10 +212,10 @@ define void @test_masked_store_success_v8f16(<8 x half> %x, ptr %ptr, <8 x i1> %
; RISCV-NEXT: vmv1r.v v13, v0
; RISCV-NEXT: vmerge.vim v8, v9, 1, v0
; RISCV-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RISCV-NEXT: vslidedown.vi v8, v8, 2
+; RISCV-NEXT: vslidedown.vi v10, v8, 2
; RISCV-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; RISCV-NEXT: vmsne.vi v0, v8, 0
; RISCV-NEXT: vmv.v.i v8, 0
+; RISCV-NEXT: vmsne.vi v0, v10, 0
; RISCV-NEXT: vmv1r.v v12, v0
; RISCV-NEXT: vmerge.vim v10, v8, 1, v0
; RISCV-NEXT: vslidedown.vi v10, v10, 1
@@ -567,10 +567,10 @@ define void @test_masked_store_multiple_v8i32(<8 x i32> %x, <8 x i32> %y, ptr %p
; RISCV-LABEL: test_masked_store_multiple_v8i32:
; RISCV: # %bb.0:
; RISCV-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RISCV-NEXT: vle32.v v14, (a1)
+; RISCV-NEXT: vle32.v v16, (a1)
; RISCV-NEXT: vse32.v v8, (a0), v0.t
; RISCV-NEXT: vmv1r.v v0, v12
-; RISCV-NEXT: vmerge.vvm v8, v14, v10, v0
+; RISCV-NEXT: vmerge.vvm v8, v16, v10, v0
; RISCV-NEXT: vse32.v v8, (a1)
; RISCV-NEXT: ret
%load = load <8 x i32>, ptr %ptr1, align 32
@@ -586,10 +586,10 @@ define void @test_masked_store_multiple_v8i64(<8 x i64> %x, <8 x i64> %y, ptr %p
; RISCV-LABEL: test_masked_store_multiple_v8i64:
; RISCV: # %bb.0:
; RISCV-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RISCV-NEXT: vle64.v v20, (a1)
+; RISCV-NEXT: vle64.v v24, (a1)
; RISCV-NEXT: vse64.v v8, (a0), v0.t
; RISCV-NEXT: vmv1r.v v0, v16
-; RISCV-NEXT: vmerge.vvm v8, v20, v12, v0
+; RISCV-NEXT: vmerge.vvm v8, v24, v12, v0
; RISCV-NEXT: vse64.v v8, (a1)
; RISCV-NEXT: ret
%load = load <8 x i64>, ptr %ptr1, align 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
index dbe3609d61934..77fcd3f4a3506 100644
--- a/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
@@ -514,14 +514,14 @@ define <vscale x 16 x i64> @vp_abs_nxv16i64(<vscale x 16 x i64> %va, <vscale x 1
; CHECK-LABEL: vp_abs_nxv16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v16, 0, v0.t
; CHECK-NEXT: vmax.vv v16, v16, v24, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
index 5c7667b902863..a13ab90bfb8f4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
@@ -3327,23 +3327,23 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64_unmasked(<vscale x 8 x i64> %va
define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv64i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: lui a1, 1
-; CHECK-NEXT: lui a3, 3
-; CHECK-NEXT: srli a4, a2, 1
-; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: lui a2, 1
+; CHECK-NEXT: lui a5, 3
+; CHECK-NEXT: slli a3, a1, 2
+; CHECK-NEXT: sub a4, a0, a3
+; CHECK-NEXT: sltu a6, a0, a4
+; CHECK-NEXT: addi a6, a6, -1
+; CHECK-NEXT: and a6, a6, a4
+; CHECK-NEXT: lui a7, 5
+; CHECK-NEXT: srli t0, a1, 1
+; CHECK-NEXT: addi a4, a2, -241
+; CHECK-NEXT: addi a2, a5, 819
+; CHECK-NEXT: addi a1, a7, 1365
; CHECK-NEXT: vsetvli a5, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a4
-; CHECK-NEXT: sub a4, a0, a2
-; CHECK-NEXT: sltu a5, a0, a4
-; CHECK-NEXT: addi a5, a5, -1
-; CHECK-NEXT: and a5, a5, a4
-; CHECK-NEXT: lui a6, 5
-; CHECK-NEXT: addi a4, a1, -241
-; CHECK-NEXT: addi a3, a3, 819
-; CHECK-NEXT: addi a1, a6, 1365
-; CHECK-NEXT: vsetvli zero, a5, e16, m8, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, t0
+; CHECK-NEXT: vsetvli zero, a6, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
@@ -3353,8 +3353,8 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: vsrl.vi v24, v16, 2, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a3, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a3, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a2, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: vsrl.vi v24, v16, 1, v0.t
@@ -3362,9 +3362,9 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 1, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
-; CHECK-NEXT: bltu a0, a2, .LBB46_2
+; CHECK-NEXT: bltu a0, a3, .LBB46_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: mv a0, a3
; CHECK-NEXT: .LBB46_2:
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -3377,8 +3377,8 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
; CHECK-NEXT: vsrl.vi v24, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a3, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a2, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
; CHECK-NEXT: vsrl.vi v24, v8, 1, v0.t
@@ -3390,17 +3390,17 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv64i16:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: srli a2, a1, 1
-; CHECK-ZVBB-NEXT: slli a1, a1, 2
-; CHECK-ZVBB-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-ZVBB-NEXT: csrr a2, vlenb
+; CHECK-ZVBB-NEXT: slli a1, a2, 2
+; CHECK-ZVBB-NEXT: sub a3, a0, a1
+; CHECK-ZVBB-NEXT: sltu a4, a0, a3
+; CHECK-ZVBB-NEXT: addi a4, a4, -1
+; CHECK-ZVBB-NEXT: and a3, a4, a3
+; CHECK-ZVBB-NEXT: srli a2, a2, 1
+; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, m1, ta, ma
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-ZVBB-NEXT: sub a2, a0, a1
-; CHECK-ZVBB-NEXT: sltu a3, a0, a2
-; CHECK-ZVBB-NEXT: addi a3, a3, -1
-; CHECK-ZVBB-NEXT: and a2, a3, a2
-; CHECK-ZVBB-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli zero, a3, e16, m8, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v16, v16, v0.t
; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB46_2
; CHECK-ZVBB-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
index fc2940e1649b2..8ef3c228b3f29 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
@@ -1819,17 +1819,17 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32
define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv64i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 2
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
@@ -1846,17 +1846,17 @@ define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv64i16:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: csrr a1, vlenb
-; CHECK-ZVKB-NEXT: srli a2, a1, 1
-; CHECK-ZVKB-NEXT: slli a1, a1, 2
-; CHECK-ZVKB-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-ZVKB-NEXT: csrr a2, vlenb
+; CHECK-ZVKB-NEXT: slli a1, a2, 2
+; CHECK-ZVKB-NEXT: sub a3, a0, a1
+; CHECK-ZVKB-NEXT: sltu a4, a0, a3
+; CHECK-ZVKB-NEXT: addi a4, a4, -1
+; CHECK-ZVKB-NEXT: and a3, a4, a3
+; CHECK-ZVKB-NEXT: srli a2, a2, 1
+; CHECK-ZVKB-NEXT: vsetvli a4, zero, e8, m1, ta, ma
; CHECK-ZVKB-NEXT: vmv1r.v v24, v0
; CHECK-ZVKB-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-ZVKB-NEXT: sub a2, a0, a1
-; CHECK-ZVKB-NEXT: sltu a3, a0, a2
-; CHECK-ZVKB-NEXT: addi a3, a3, -1
-; CHECK-ZVKB-NEXT: and a2, a3, a2
-; CHECK-ZVKB-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli zero, a3, e16, m8, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v16, v16, v0.t
; CHECK-ZVKB-NEXT: bltu a0, a1, .LBB32_2
; CHECK-ZVKB-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
index b84878f227a7a..2af49bd353f68 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
@@ -17,12 +17,12 @@ define <vscale x 1 x bfloat> @vp_ceil_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -67,12 +67,12 @@ define <vscale x 2 x bfloat> @vp_ceil_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
@@ -410,12 +410,12 @@ define <vscale x 1 x half> @vp_ceil_vv_nxv1f16(<vscale x 1 x half> %va, <vscale
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -494,12 +494,12 @@ define <vscale x 2 x half> @vp_ceil_vv_nxv2f16(<vscale x 2 x half> %va, <vscale
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll b/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
index acc1c794c5e94..dfd057c9d7dea 100644
--- a/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
@@ -95,154 +95,128 @@ define i32 @test_v256i1(<256 x i1> %x) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a1, a1, a0
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x14, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 20 * vlenb
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add a1, a1, a0
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs1r.v v0, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vmv1r.v v16, v8
; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vslidedown.vi v26, v16, 8
+; CHECK-NEXT: vmv1r.v v25, v16
+; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v26, 4
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a2, a1, 5
+; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vslidedown.vi v8, v8, 8
+; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v25, 4
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl1r.v v8, (a1) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vslidedown.vi v8, v8, 8
+; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v24, 4
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a2, a1, 4
; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
-; CHECK-NEXT: vadd.vv v16, v24, v16
-; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a2, a1, 3
; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
+; CHECK-NEXT: vadd.vv v16, v24, v16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a2, a1, 4
-; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
-; CHECK-NEXT: vadd.vv v16, v16, v24
-; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v0, 8
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a2, a1, 3
+; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl1r.v v16, (a1) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v16, 4
+; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v24, v24, v16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a2, a2, a1
; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl1r.v v16, (a1) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vslidedown.vi v24, v16, 4
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
-; CHECK-NEXT: vadd.vv v16, v24, v16
-; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: add a2, a2, a1
; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl1r.v v24, (a1) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v24, 4
+; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a2, a1, 4
; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl1r.v v24, (a1) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vslidedown.vi v7, v24, 4
+; CHECK-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v16, v0, v16
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vl1r.v v7, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v7, 4
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vadd.vv v8, v8, v24
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: slli a1, a0, 5
; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vv v24, v24, v0
+; CHECK-NEXT: vadd.vv v8, v8, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v24, v0, v24
; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vadd.vv v8, v24, v8
; CHECK-NEXT: vmv.s.x v16, zero
; CHECK-NEXT: vredsum.vs v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a2, a2, a1
; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add sp, sp, a1
@@ -359,46 +333,83 @@ entry:
define i32 @test_nxv128i1(<vscale x 128 x i1> %x) {
; CHECK-LABEL: test_nxv128i1:
; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: sub sp, sp, a0
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v8
-; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vmv1r.v v7, v8
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
-; CHECK-NEXT: srli a1, a0, 1
+; CHECK-NEXT: srli a1, a0, 2
+; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a1
+; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v6, v24, a1
-; CHECK-NEXT: vslidedown.vx v5, v0, a1
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
-; CHECK-NEXT: vmv1r.v v4, v24
-; CHECK-NEXT: vmv1r.v v0, v5
-; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vslidedown.vx v0, v0, a0
+; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
+; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a1
+; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
+; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v7, a1
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
-; CHECK-NEXT: vadd.vv v16, v16, v24
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v7, a0
-; CHECK-NEXT: vslidedown.vx v7, v5, a0
-; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v4, a0
-; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v6, a0
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v7, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
; CHECK-NEXT: vadd.vv v8, v24, v8
-; CHECK-NEXT: vadd.vv v8, v16, v8
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a1
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
+; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v16, v24, v16
+; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vmv.s.x v16, zero
; CHECK-NEXT: vredsum.vs v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add sp, sp, a1
+; CHECK-NEXT: .cfi_def_cfa sp, 16
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
entry:
%a = zext <vscale x 128 x i1> %x to <vscale x 128 x i32>
@@ -412,98 +423,243 @@ define i32 @test_nxv256i1(<vscale x 256 x i1> %x) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v6, v10
-; CHECK-NEXT: vmv1r.v v4, v9
-; CHECK-NEXT: vmv1r.v v24, v8
-; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmv1r.v v7, v9
+; CHECK-NEXT: vmv.v.i v24, 0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
; CHECK-NEXT: srli a0, a1, 2
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v3, v4, a0
-; CHECK-NEXT: vslidedown.vx v2, v0, a0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v4
-; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
-; CHECK-NEXT: vadd.vv v16, v16, v24
+; CHECK-NEXT: vslidedown.vx v0, v0, a0
+; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: mv a3, a2
; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a3, a3, a2
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v8, a0
+; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: srli a1, a1, 1
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v11, a1
+; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v2
-; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
+; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a0
+; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 4
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vim v8, v24, 1, v0
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a1
+; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
+; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a0
+; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v24, v24, 1, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a3, a3, a2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v6, a0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v7, a0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a3, a3, a2
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
+; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a3, a3, a2
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v6, a1
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v3
; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
-; CHECK-NEXT: vadd.vv v16, v16, v24
+; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a3, a3, a2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
+; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a3, a3, a2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: srli a1, a1, 1
+; CHECK-NEXT: vs1r.v v7, (a2) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
+; CHECK-NEXT: vadd.vv v8, v24, v8
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a3, a3, a2
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v24, v24, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a3, a3, a2
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vl1r.v v24, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v4, v4, a1
-; CHECK-NEXT: vslidedown.vx v3, v7, a1
-; CHECK-NEXT: vslidedown.vx v6, v6, a1
-; CHECK-NEXT: vslidedown.vx v0, v5, a1
-; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v3
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v4
-; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vadd.vv v24, v8, v16
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v3, a0
-; CHECK-NEXT: vslidedown.vx v5, v5, a0
-; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v5
-; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v6, a0
+; CHECK-NEXT: vslidedown.vx v0, v24, a1
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a2, a1, 3
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
+; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
+; CHECK-NEXT: vadd.vv v16, v24, v16
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v4, a0
+; CHECK-NEXT: vslidedown.vx v0, v0, a0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 4
+; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
+; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v24, v24, v0
; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: slli a0, a0, 2
+; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vadd.vv v16, v16, v24
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vv v8, v24, v8
-; CHECK-NEXT: vadd.vv v8, v16, v8
+; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vmv.s.x v16, zero
; CHECK-NEXT: vredsum.vs v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add sp, sp, a1
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll b/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
index f05f07eacaf4c..4572658c5985f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
@@ -23,16 +23,17 @@ define void @constant_folding_crash(ptr %v54, <4 x ptr> %lanes.a, <4 x ptr> %lan
; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vmerge.vim v10, v10, 1, v0
; RV32-NEXT: vrgather.vi v11, v10, 0
-; RV32-NEXT: vmsne.vi v11, v11, 0
; RV32-NEXT: andi a0, a0, 1
; RV32-NEXT: seqz a0, a0
; RV32-NEXT: vmv.v.x v10, a0
; RV32-NEXT: vmsne.vi v0, v10, 0
; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
+; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV32-NEXT: vmsne.vi v0, v11, 0
+; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: vmv.v.i v8, 10
-; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: vse32.v v8, (a0), v0.t
; RV32-NEXT: ret
;
@@ -43,17 +44,18 @@ define void @constant_folding_crash(ptr %v54, <4 x ptr> %lanes.a, <4 x ptr> %lan
; RV64-NEXT: vmv.v.i v12, 0
; RV64-NEXT: vmerge.vim v12, v12, 1, v0
; RV64-NEXT: vrgather.vi v13, v12, 0
-; RV64-NEXT: vmsne.vi v13, v13, 0
; RV64-NEXT: andi a0, a0, 1
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vmsne.vi v0, v12, 0
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vmerge.vvm v8, v10, v8, v0
+; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV64-NEXT: vmsne.vi v0, v13, 0
+; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV64-NEXT: vmv.v.i v8, 10
-; RV64-NEXT: vmv1r.v v0, v13
; RV64-NEXT: vse32.v v8, (a0), v0.t
; RV64-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
index b2d5fb276ba66..5a465219b2124 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
@@ -1188,24 +1188,24 @@ define <vscale x 16 x i64> @vp_ctlz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; CHECK-LABEL: vp_ctlz_nxv16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: fsrmi a4, 1
+; CHECK-NEXT: fsrmi a5, 1
; CHECK-NEXT: li a2, 52
-; CHECK-NEXT: srli a3, a1, 3
-; CHECK-NEXT: sub a5, a0, a1
-; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: sltu a3, a0, a5
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a5, a3, a5
; CHECK-NEXT: li a3, 1086
-; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma
+; CHECK-NEXT: li a4, 64
+; CHECK-NEXT: sub a6, a0, a1
+; CHECK-NEXT: sltu a7, a0, a6
+; CHECK-NEXT: addi a7, a7, -1
+; CHECK-NEXT: and a6, a7, a6
+; CHECK-NEXT: srli a7, a1, 3
+; CHECK-NEXT: vsetvli t0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a7
+; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t
-; CHECK-NEXT: fsrm a4
; CHECK-NEXT: vsrl.vx v16, v16, a2, v0.t
; CHECK-NEXT: vrsub.vx v16, v16, a3, v0.t
-; CHECK-NEXT: li a4, 64
; CHECK-NEXT: vminu.vx v16, v16, a4, v0.t
+; CHECK-NEXT: fsrm a5
; CHECK-NEXT: bltu a0, a1, .LBB46_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -1223,14 +1223,14 @@ define <vscale x 16 x i64> @vp_ctlz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; CHECK-ZVBB-LABEL: vp_ctlz_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: srli a2, a1, 3
-; CHECK-ZVBB-NEXT: sub a3, a0, a1
+; CHECK-ZVBB-NEXT: sub a2, a0, a1
+; CHECK-ZVBB-NEXT: sltu a3, a0, a2
+; CHECK-ZVBB-NEXT: addi a3, a3, -1
+; CHECK-ZVBB-NEXT: and a2, a3, a2
+; CHECK-ZVBB-NEXT: srli a3, a1, 3
; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
-; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-ZVBB-NEXT: sltu a2, a0, a3
-; CHECK-ZVBB-NEXT: addi a2, a2, -1
-; CHECK-ZVBB-NEXT: and a2, a2, a3
+; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a3
; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v16, v16, v0.t
; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB46_2
@@ -2396,22 +2396,22 @@ define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: fsrmi a3, 1
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a4, a0, a1
-; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a4
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a4, a2, a4
+; CHECK-NEXT: fsrmi a4, 1
; CHECK-NEXT: li a2, 52
-; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; CHECK-NEXT: li a3, 1086
+; CHECK-NEXT: sub a5, a0, a1
+; CHECK-NEXT: sltu a6, a0, a5
+; CHECK-NEXT: addi a6, a6, -1
+; CHECK-NEXT: and a5, a6, a5
+; CHECK-NEXT: srli a6, a1, 3
+; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a6
+; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma
; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t
-; CHECK-NEXT: fsrm a3
; CHECK-NEXT: vsrl.vx v16, v16, a2, v0.t
-; CHECK-NEXT: li a3, 1086
; CHECK-NEXT: vrsub.vx v16, v16, a3, v0.t
+; CHECK-NEXT: fsrm a4
; CHECK-NEXT: bltu a0, a1, .LBB94_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -2428,14 +2428,14 @@ define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: srli a2, a1, 3
-; CHECK-ZVBB-NEXT: sub a3, a0, a1
+; CHECK-ZVBB-NEXT: sub a2, a0, a1
+; CHECK-ZVBB-NEXT: sltu a3, a0, a2
+; CHECK-ZVBB-NEXT: addi a3, a3, -1
+; CHECK-ZVBB-NEXT: and a2, a3, a2
+; CHECK-ZVBB-NEXT: srli a3, a1, 3
; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
-; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-ZVBB-NEXT: sltu a2, a0, a3
-; CHECK-ZVBB-NEXT: addi a2, a2, -1
-; CHECK-ZVBB-NEXT: and a2, a2, a3
+; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a3
; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v16, v16, v0.t
; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB94_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
index 1b03694ee3b36..37adb42ad3e9a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
@@ -1985,63 +1985,63 @@ define <vscale x 16 x i64> @vp_ctpop_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV32-NEXT: srli a3, a1, 3
; RV32-NEXT: sub a4, a0, a1
; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 48
-; RV32-NEXT: mul a5, a5, a6
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs1r.v v0, (a5) # vscale x 8-byte Folded Spill
-; RV32-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vx v0, v0, a3
-; RV32-NEXT: sltu a3, a0, a4
; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a2
-; RV32-NEXT: addi a3, a3, -1
-; RV32-NEXT: and a3, a3, a4
-; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV32-NEXT: sltu a2, a0, a4
+; RV32-NEXT: addi a2, a2, -1
+; RV32-NEXT: and a2, a2, a4
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: li a5, 48
+; RV32-NEXT: mul a4, a4, a5
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vx v0, v0, a3
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 5
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 5
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vsub.vv v8, v16, v8, v0.t
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: addi a2, a2, 819
+; RV32-NEXT: lui a3, 209715
+; RV32-NEXT: addi a3, a3, 819
; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a2
-; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV32-NEXT: vmv.v.x v24, a3
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v8, v24, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: addi a3, sp, 16
+; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a2, 61681
+; RV32-NEXT: lui a3, 61681
; RV32-NEXT: lui a4, 4112
-; RV32-NEXT: addi a2, a2, -241
+; RV32-NEXT: addi a3, a3, -241
; RV32-NEXT: addi a4, a4, 257
; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: vmv.v.x v16, a3
+; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: li a5, 24
-; RV32-NEXT: mul a2, a2, a5
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV32-NEXT: mul a3, a3, a5
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a4
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmul.vv v16, v16, v8, v0.t
; RV32-NEXT: li a2, 56
; RV32-NEXT: vsrl.vx v8, v16, a2, v0.t
@@ -2124,97 +2124,76 @@ define <vscale x 16 x i64> @vp_ctpop_nxv16i64(<vscale x 16 x i64> %va, <vscale x
;
; RV64-LABEL: vp_ctpop_nxv16i64:
; RV64: # %bb.0:
-; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: srli a1, a5, 3
-; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v7, v0, a1
-; RV64-NEXT: mv a1, a0
-; RV64-NEXT: bltu a0, a5, .LBB46_2
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: srli a3, a1, 3
+; RV64-NEXT: mv a2, a0
+; RV64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vx v7, v0, a3
+; RV64-NEXT: bltu a0, a1, .LBB46_2
; RV64-NEXT: # %bb.1:
-; RV64-NEXT: mv a1, a5
+; RV64-NEXT: mv a2, a1
; RV64-NEXT: .LBB46_2:
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
-; RV64-NEXT: lui a6, 4112
+; RV64-NEXT: lui a5, 4112
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: addi a3, a3, 819
; RV64-NEXT: addi a4, a4, -241
-; RV64-NEXT: addi a6, a6, 257
-; RV64-NEXT: slli a7, a2, 32
-; RV64-NEXT: add a7, a2, a7
-; RV64-NEXT: slli a2, a3, 32
-; RV64-NEXT: add t0, a3, a2
-; RV64-NEXT: slli a2, a4, 32
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: slli a2, a6, 32
-; RV64-NEXT: add a2, a6, a2
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: sub a5, a0, a5
-; RV64-NEXT: sltu a0, a0, a5
-; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a0, a0, a5
-; RV64-NEXT: vand.vx v24, v24, a7, v0.t
+; RV64-NEXT: addi a5, a5, 257
+; RV64-NEXT: slli a6, a2, 32
+; RV64-NEXT: add a2, a2, a6
+; RV64-NEXT: slli a6, a3, 32
+; RV64-NEXT: add a3, a3, a6
+; RV64-NEXT: slli a6, a4, 32
+; RV64-NEXT: add a4, a4, a6
+; RV64-NEXT: slli a6, a5, 32
+; RV64-NEXT: add a5, a5, a6
+; RV64-NEXT: li a6, 56
+; RV64-NEXT: vand.vx v24, v24, a2, v0.t
; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v6, v0
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a7, v0.t
-; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v8, t0, v0.t
+; RV64-NEXT: vand.vx v24, v8, a3, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, t0, v0.t
+; RV64-NEXT: vand.vx v8, v8, a3, v0.t
; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v16, t0, v0.t
-; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, t0, v0.t
-; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vand.vx v8, v8, a4, v0.t
+; RV64-NEXT: vmul.vx v8, v8, a5, v0.t
+; RV64-NEXT: vsrl.vx v8, v8, a6, v0.t
+; RV64-NEXT: sub a1, a0, a1
+; RV64-NEXT: sltu a0, a0, a1
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a2, v0.t
+; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
+; RV64-NEXT: vand.vx v24, v16, a3, v0.t
+; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
+; RV64-NEXT: vand.vx v16, v16, a3, v0.t
+; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vmul.vx v8, v8, a2, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v16, a4, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v8, v8, a3, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vmul.vx v16, v16, a2, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a3, v0.t
+; RV64-NEXT: vmul.vx v16, v16, a5, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a6, v0.t
; RV64-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_ctpop_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: srli a2, a1, 3
-; CHECK-ZVBB-NEXT: sub a3, a0, a1
+; CHECK-ZVBB-NEXT: sub a2, a0, a1
+; CHECK-ZVBB-NEXT: sltu a3, a0, a2
+; CHECK-ZVBB-NEXT: addi a3, a3, -1
+; CHECK-ZVBB-NEXT: and a2, a3, a2
+; CHECK-ZVBB-NEXT: srli a3, a1, 3
; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
-; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-ZVBB-NEXT: sltu a2, a0, a3
-; CHECK-ZVBB-NEXT: addi a2, a2, -1
-; CHECK-ZVBB-NEXT: and a2, a2, a3
+; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a3
; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vcpop.v v16, v16, v0.t
; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB46_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
index bf003ef675a36..ed2dc76750466 100644
--- a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
@@ -2150,8 +2150,11 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: lui a2, 349525
-; RV32-NEXT: srli a3, a1, 3
-; RV32-NEXT: sub a4, a0, a1
+; RV32-NEXT: sub a3, a0, a1
+; RV32-NEXT: sltu a4, a0, a3
+; RV32-NEXT: addi a4, a4, -1
+; RV32-NEXT: and a3, a4, a3
+; RV32-NEXT: srli a4, a1, 3
; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: li a6, 48
@@ -2160,10 +2163,7 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs1r.v v0, (a5) # vscale x 8-byte Folded Spill
; RV32-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vx v0, v0, a3
-; RV32-NEXT: sltu a3, a0, a4
-; RV32-NEXT: addi a3, a3, -1
-; RV32-NEXT: and a3, a3, a4
+; RV32-NEXT: vslidedown.vx v0, v0, a4
; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV32-NEXT: vadd.vi v8, v16, -1, v0.t
; RV32-NEXT: vnot.v v16, v16, v0.t
@@ -2304,26 +2304,26 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
; RV64-NEXT: lui a5, 4112
-; RV64-NEXT: srli a6, a1, 3
-; RV64-NEXT: sub a7, a0, a1
+; RV64-NEXT: sub a6, a0, a1
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: addi a3, a3, 819
-; RV64-NEXT: addi t0, a4, -241
-; RV64-NEXT: addi t1, a5, 257
-; RV64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v7, v0
-; RV64-NEXT: vslidedown.vx v0, v0, a6
+; RV64-NEXT: addi a7, a4, -241
+; RV64-NEXT: addi t0, a5, 257
; RV64-NEXT: slli a5, a2, 32
; RV64-NEXT: add a5, a2, a5
; RV64-NEXT: slli a4, a3, 32
; RV64-NEXT: add a4, a3, a4
-; RV64-NEXT: slli a2, t0, 32
-; RV64-NEXT: add a2, t0, a2
-; RV64-NEXT: slli a3, t1, 32
-; RV64-NEXT: add a3, t1, a3
-; RV64-NEXT: sltu a6, a0, a7
-; RV64-NEXT: addi a6, a6, -1
-; RV64-NEXT: and a6, a6, a7
+; RV64-NEXT: slli a2, a7, 32
+; RV64-NEXT: add a2, a7, a2
+; RV64-NEXT: slli a3, t0, 32
+; RV64-NEXT: add a3, t0, a3
+; RV64-NEXT: sltu a7, a0, a6
+; RV64-NEXT: addi a7, a7, -1
+; RV64-NEXT: and a6, a7, a6
+; RV64-NEXT: srli a7, a1, 3
+; RV64-NEXT: vsetvli t0, zero, e8, mf4, ta, ma
+; RV64-NEXT: vmv1r.v v7, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a7
; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; RV64-NEXT: vadd.vi v24, v16, -1, v0.t
; RV64-NEXT: vnot.v v16, v16, v0.t
@@ -2367,14 +2367,14 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; CHECK-ZVBB-LABEL: vp_cttz_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: srli a2, a1, 3
-; CHECK-ZVBB-NEXT: sub a3, a0, a1
+; CHECK-ZVBB-NEXT: sub a2, a0, a1
+; CHECK-ZVBB-NEXT: sltu a3, a0, a2
+; CHECK-ZVBB-NEXT: addi a3, a3, -1
+; CHECK-ZVBB-NEXT: and a2, a3, a2
+; CHECK-ZVBB-NEXT: srli a3, a1, 3
; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
-; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-ZVBB-NEXT: sltu a2, a0, a3
-; CHECK-ZVBB-NEXT: addi a2, a2, -1
-; CHECK-ZVBB-NEXT: and a2, a2, a3
+; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a3
; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v16, v16, v0.t
; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB46_2
@@ -3747,24 +3747,24 @@ define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
; CHECK-LABEL: vp_cttz_zero_undef_nxv16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: fsrmi a3, 1
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a4, a0, a1
-; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a4
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a4, a2, a4
+; CHECK-NEXT: fsrmi a4, 1
; CHECK-NEXT: li a2, 52
-; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; CHECK-NEXT: li a3, 1023
+; CHECK-NEXT: sub a5, a0, a1
+; CHECK-NEXT: sltu a6, a0, a5
+; CHECK-NEXT: addi a6, a6, -1
+; CHECK-NEXT: and a5, a6, a5
+; CHECK-NEXT: srli a6, a1, 3
+; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a6
+; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v16, 0, v0.t
; CHECK-NEXT: vand.vv v16, v16, v24, v0.t
; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t
-; CHECK-NEXT: fsrm a3
; CHECK-NEXT: vsrl.vx v16, v16, a2, v0.t
-; CHECK-NEXT: li a3, 1023
; CHECK-NEXT: vsub.vx v16, v16, a3, v0.t
+; CHECK-NEXT: fsrm a4
; CHECK-NEXT: bltu a0, a1, .LBB94_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -3783,14 +3783,14 @@ define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: srli a2, a1, 3
-; CHECK-ZVBB-NEXT: sub a3, a0, a1
+; CHECK-ZVBB-NEXT: sub a2, a0, a1
+; CHECK-ZVBB-NEXT: sltu a3, a0, a2
+; CHECK-ZVBB-NEXT: addi a3, a3, -1
+; CHECK-ZVBB-NEXT: and a2, a3, a2
+; CHECK-ZVBB-NEXT: srli a3, a1, 3
; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
-; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-ZVBB-NEXT: sltu a2, a0, a3
-; CHECK-ZVBB-NEXT: addi a2, a2, -1
-; CHECK-ZVBB-NEXT: and a2, a2, a3
+; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a3
; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v16, v16, v0.t
; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB94_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/expandload.ll b/llvm/test/CodeGen/RISCV/rvv/expandload.ll
index f13a9d0764c8b..0a2c8c9693b47 100644
--- a/llvm/test/CodeGen/RISCV/rvv/expandload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/expandload.ll
@@ -218,24 +218,31 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: csrr a2, vlenb
-; CHECK-RV32-NEXT: slli a3, a2, 5
-; CHECK-RV32-NEXT: add a2, a3, a2
+; CHECK-RV32-NEXT: li a3, 34
+; CHECK-RV32-NEXT: mul a2, a2, a3
; CHECK-RV32-NEXT: sub sp, sp, a2
-; CHECK-RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; CHECK-RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x22, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 34 * vlenb
; CHECK-RV32-NEXT: csrr a2, vlenb
-; CHECK-RV32-NEXT: li a3, 24
+; CHECK-RV32-NEXT: li a3, 26
; CHECK-RV32-NEXT: mul a2, a2, a3
; CHECK-RV32-NEXT: add a2, sp, a2
; CHECK-RV32-NEXT: addi a2, a2, 16
; CHECK-RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: csrr a2, vlenb
-; CHECK-RV32-NEXT: slli a2, a2, 5
+; CHECK-RV32-NEXT: li a3, 25
+; CHECK-RV32-NEXT: mul a2, a2, a3
+; CHECK-RV32-NEXT: add a2, sp, a2
+; CHECK-RV32-NEXT: addi a2, a2, 16
+; CHECK-RV32-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
+; CHECK-RV32-NEXT: csrr a2, vlenb
+; CHECK-RV32-NEXT: li a3, 24
+; CHECK-RV32-NEXT: mul a2, a2, a3
; CHECK-RV32-NEXT: add a2, sp, a2
; CHECK-RV32-NEXT: addi a2, a2, 16
; CHECK-RV32-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: li a2, 128
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v8, v0, 1
+; CHECK-RV32-NEXT: vslidedown.vi v11, v0, 1
; CHECK-RV32-NEXT: li a3, 32
; CHECK-RV32-NEXT: vmv.x.s a4, v0
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -246,9 +253,9 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV32-NEXT: addi a1, a1, 16
; CHECK-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vsrl.vx v9, v8, a3
+; CHECK-RV32-NEXT: vsrl.vx v9, v11, a3
; CHECK-RV32-NEXT: vsrl.vx v10, v0, a3
-; CHECK-RV32-NEXT: vmv.x.s a1, v8
+; CHECK-RV32-NEXT: vmv.x.s a1, v11
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV32-NEXT: vcpop.m a3, v0
; CHECK-RV32-NEXT: cpop a4, a4
@@ -256,12 +263,12 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV32-NEXT: vmv.x.s a5, v9
; CHECK-RV32-NEXT: vmv.x.s a6, v10
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-RV32-NEXT: vle8.v v8, (a0)
+; CHECK-RV32-NEXT: vle8.v v24, (a0)
; CHECK-RV32-NEXT: csrr a3, vlenb
; CHECK-RV32-NEXT: slli a3, a3, 4
; CHECK-RV32-NEXT: add a3, sp, a3
; CHECK-RV32-NEXT: addi a3, a3, 16
-; CHECK-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: cpop a1, a1
; CHECK-RV32-NEXT: cpop a3, a6
; CHECK-RV32-NEXT: cpop a5, a5
@@ -269,65 +276,75 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV32-NEXT: add a1, a1, a5
; CHECK-RV32-NEXT: add a1, a3, a1
; CHECK-RV32-NEXT: add a0, a0, a1
-; CHECK-RV32-NEXT: csrr a1, vlenb
-; CHECK-RV32-NEXT: slli a1, a1, 5
-; CHECK-RV32-NEXT: add a1, sp, a1
-; CHECK-RV32-NEXT: addi a1, a1, 16
-; CHECK-RV32-NEXT: vl1r.v v8, (a1) # vscale x 8-byte Folded Reload
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV32-NEXT: vcpop.m a1, v8
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-RV32-NEXT: vle8.v v8, (a0)
; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, mu
-; CHECK-RV32-NEXT: viota.m v16, v0
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 4
+; CHECK-RV32-NEXT: li a1, 25
+; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; CHECK-RV32-NEXT: viota.m v8, v24
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: li a1, 24
+; CHECK-RV32-NEXT: li a1, 25
; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: vrgather.vv v8, v24, v16, v0.t
+; CHECK-RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: li a1, 24
+; CHECK-RV32-NEXT: li a1, 26
; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 5
+; CHECK-RV32-NEXT: slli a0, a0, 4
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
-; CHECK-RV32-NEXT: viota.m v8, v24
+; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vrgather.vv v16, v24, v8, v0.t
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 5
+; CHECK-RV32-NEXT: li a1, 26
+; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: csrr a0, vlenb
+; CHECK-RV32-NEXT: li a1, 24
+; CHECK-RV32-NEXT: mul a0, a0, a1
+; CHECK-RV32-NEXT: add a0, sp, a0
+; CHECK-RV32-NEXT: addi a0, a0, 16
+; CHECK-RV32-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV32-NEXT: viota.m v16, v8
; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: slli a0, a0, 3
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: vrgather.vv v16, v24, v8, v0.t
; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: li a1, 24
; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
+; CHECK-RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vrgather.vv v24, v8, v16, v0.t
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a1, a0, 5
-; CHECK-RV32-NEXT: add a0, a1, a0
+; CHECK-RV32-NEXT: li a1, 26
+; CHECK-RV32-NEXT: mul a0, a0, a1
+; CHECK-RV32-NEXT: add a0, sp, a0
+; CHECK-RV32-NEXT: addi a0, a0, 16
+; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv.v.v v16, v24
+; CHECK-RV32-NEXT: csrr a0, vlenb
+; CHECK-RV32-NEXT: li a1, 34
+; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add sp, sp, a0
; CHECK-RV32-NEXT: .cfi_def_cfa sp, 16
; CHECK-RV32-NEXT: addi sp, sp, 16
@@ -339,24 +356,31 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV64-NEXT: addi sp, sp, -16
; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV64-NEXT: csrr a2, vlenb
-; CHECK-RV64-NEXT: slli a3, a2, 5
-; CHECK-RV64-NEXT: add a2, a3, a2
+; CHECK-RV64-NEXT: li a3, 34
+; CHECK-RV64-NEXT: mul a2, a2, a3
; CHECK-RV64-NEXT: sub sp, sp, a2
-; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x22, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 34 * vlenb
; CHECK-RV64-NEXT: csrr a2, vlenb
-; CHECK-RV64-NEXT: li a3, 24
+; CHECK-RV64-NEXT: li a3, 26
; CHECK-RV64-NEXT: mul a2, a2, a3
; CHECK-RV64-NEXT: add a2, sp, a2
; CHECK-RV64-NEXT: addi a2, a2, 16
; CHECK-RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: csrr a2, vlenb
-; CHECK-RV64-NEXT: slli a2, a2, 5
+; CHECK-RV64-NEXT: li a3, 25
+; CHECK-RV64-NEXT: mul a2, a2, a3
+; CHECK-RV64-NEXT: add a2, sp, a2
+; CHECK-RV64-NEXT: addi a2, a2, 16
+; CHECK-RV64-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
+; CHECK-RV64-NEXT: csrr a2, vlenb
+; CHECK-RV64-NEXT: li a3, 24
+; CHECK-RV64-NEXT: mul a2, a2, a3
; CHECK-RV64-NEXT: add a2, sp, a2
; CHECK-RV64-NEXT: addi a2, a2, 16
; CHECK-RV64-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: li a2, 128
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v8, v0, 1
+; CHECK-RV64-NEXT: vslidedown.vi v9, v0, 1
; CHECK-RV64-NEXT: vmv.x.s a3, v0
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV64-NEXT: vle8.v v16, (a1)
@@ -366,21 +390,16 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV64-NEXT: addi a1, a1, 16
; CHECK-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a2, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vmv.x.s a1, v8
+; CHECK-RV64-NEXT: vmv.x.s a1, v9
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV64-NEXT: vcpop.m a4, v0
; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; CHECK-RV64-NEXT: vle8.v v8, (a0)
+; CHECK-RV64-NEXT: vle8.v v24, (a0)
; CHECK-RV64-NEXT: csrr a4, vlenb
; CHECK-RV64-NEXT: slli a4, a4, 4
; CHECK-RV64-NEXT: add a4, sp, a4
; CHECK-RV64-NEXT: addi a4, a4, 16
-; CHECK-RV64-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: csrr a4, vlenb
-; CHECK-RV64-NEXT: slli a4, a4, 5
-; CHECK-RV64-NEXT: add a4, sp, a4
-; CHECK-RV64-NEXT: addi a4, a4, 16
-; CHECK-RV64-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; CHECK-RV64-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV64-NEXT: vcpop.m a4, v8
; CHECK-RV64-NEXT: cpop a3, a3
@@ -391,54 +410,68 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV64-NEXT: vle8.v v8, (a0)
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: csrr a0, vlenb
+; CHECK-RV64-NEXT: li a1, 25
+; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: add a0, sp, a0
+; CHECK-RV64-NEXT: addi a0, a0, 16
+; CHECK-RV64-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, mu
-; CHECK-RV64-NEXT: viota.m v16, v0
+; CHECK-RV64-NEXT: viota.m v24, v8
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 4
+; CHECK-RV64-NEXT: li a1, 25
+; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 24
+; CHECK-RV64-NEXT: li a1, 26
; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV64-NEXT: vrgather.vv v8, v24, v16, v0.t
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 24
-; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: slli a0, a0, 4
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 5
+; CHECK-RV64-NEXT: li a1, 26
+; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
-; CHECK-RV64-NEXT: viota.m v24, v8
+; CHECK-RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 5
+; CHECK-RV64-NEXT: li a1, 24
+; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV64-NEXT: vl1r.v v16, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV64-NEXT: viota.m v24, v16
; CHECK-RV64-NEXT: csrr a0, vlenb
; CHECK-RV64-NEXT: slli a0, a0, 3
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: csrr a0, vlenb
+; CHECK-RV64-NEXT: li a1, 24
+; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: add a0, sp, a0
+; CHECK-RV64-NEXT: addi a0, a0, 16
+; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vrgather.vv v16, v8, v24, v0.t
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 24
+; CHECK-RV64-NEXT: li a1, 26
; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a1, a0, 5
-; CHECK-RV64-NEXT: add a0, a1, a0
+; CHECK-RV64-NEXT: li a1, 34
+; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add sp, sp, a0
; CHECK-RV64-NEXT: .cfi_def_cfa sp, 16
; CHECK-RV64-NEXT: addi sp, sp, 16
@@ -694,22 +727,22 @@ define <128 x i16> @test_expandload_v128i16(ptr %base, <128 x i1> %mask, <128 x
; CHECK-RV32-NEXT: add a1, sp, a1
; CHECK-RV32-NEXT: addi a1, a1, 16
; CHECK-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m8, ta, ma
; CHECK-RV32-NEXT: vmv8r.v v16, v8
; CHECK-RV32-NEXT: li a1, 64
-; CHECK-RV32-NEXT: vslidedown.vi v8, v0, 8
-; CHECK-RV32-NEXT: csrr a2, vlenb
-; CHECK-RV32-NEXT: slli a2, a2, 5
-; CHECK-RV32-NEXT: add a2, sp, a2
-; CHECK-RV32-NEXT: addi a2, a2, 16
-; CHECK-RV32-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: li a2, 32
-; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-RV32-NEXT: vmv.x.s a3, v0
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-RV32-NEXT: vcpop.m a4, v0
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV32-NEXT: vsrl.vx v8, v0, a2
+; CHECK-RV32-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vi v9, v0, 8
+; CHECK-RV32-NEXT: csrr a2, vlenb
+; CHECK-RV32-NEXT: slli a2, a2, 5
+; CHECK-RV32-NEXT: add a2, sp, a2
+; CHECK-RV32-NEXT: addi a2, a2, 16
+; CHECK-RV32-NEXT: vs1r.v v9, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: csrr a2, vlenb
; CHECK-RV32-NEXT: slli a2, a2, 5
; CHECK-RV32-NEXT: add a2, sp, a2
@@ -798,20 +831,21 @@ define <128 x i16> @test_expandload_v128i16(ptr %base, <128 x i1> %mask, <128 x
; CHECK-RV64-NEXT: addi a1, a1, 16
; CHECK-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: li a1, 64
-; CHECK-RV64-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 8
-; CHECK-RV64-NEXT: csrr a2, vlenb
-; CHECK-RV64-NEXT: slli a2, a2, 5
-; CHECK-RV64-NEXT: add a2, sp, a2
-; CHECK-RV64-NEXT: addi a2, a2, 16
-; CHECK-RV64-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-RV64-NEXT: vcpop.m a2, v0
+; CHECK-RV64-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 8
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 16
+; CHECK-RV64-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: csrr a3, vlenb
; CHECK-RV64-NEXT: slli a3, a3, 5
; CHECK-RV64-NEXT: add a3, sp, a3
; CHECK-RV64-NEXT: addi a3, a3, 16
; CHECK-RV64-NEXT: vl1r.v v24, (a3) # vscale x 8-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-RV64-NEXT: vcpop.m a3, v24
; CHECK-RV64-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-RV64-NEXT: vle16.v v24, (a0)
@@ -1084,20 +1118,21 @@ define <64 x i32> @test_expandload_v64i32(ptr %base, <64 x i1> %mask, <64 x i32>
; CHECK-RV32-NEXT: addi a1, a1, 16
; CHECK-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: li a1, 32
-; CHECK-RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v24, v0, 4
-; CHECK-RV32-NEXT: csrr a2, vlenb
-; CHECK-RV32-NEXT: slli a2, a2, 5
-; CHECK-RV32-NEXT: add a2, sp, a2
-; CHECK-RV32-NEXT: addi a2, a2, 16
-; CHECK-RV32-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vcpop.m a2, v0
+; CHECK-RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vi v24, v0, 4
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 16
+; CHECK-RV32-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: csrr a3, vlenb
; CHECK-RV32-NEXT: slli a3, a3, 5
; CHECK-RV32-NEXT: add a3, sp, a3
; CHECK-RV32-NEXT: addi a3, a3, 16
; CHECK-RV32-NEXT: vl1r.v v24, (a3) # vscale x 8-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vcpop.m a3, v24
; CHECK-RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-RV32-NEXT: vle32.v v24, (a0)
@@ -1166,37 +1201,33 @@ define <64 x i32> @test_expandload_v64i32(ptr %base, <64 x i1> %mask, <64 x i32>
; CHECK-RV64-NEXT: addi sp, sp, -16
; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV64-NEXT: csrr a1, vlenb
-; CHECK-RV64-NEXT: slli a2, a1, 5
-; CHECK-RV64-NEXT: add a1, a2, a1
+; CHECK-RV64-NEXT: li a2, 25
+; CHECK-RV64-NEXT: mul a1, a1, a2
; CHECK-RV64-NEXT: sub sp, sp, a1
-; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
; CHECK-RV64-NEXT: csrr a1, vlenb
-; CHECK-RV64-NEXT: li a2, 24
-; CHECK-RV64-NEXT: mul a1, a1, a2
+; CHECK-RV64-NEXT: slli a1, a1, 4
; CHECK-RV64-NEXT: add a1, sp, a1
; CHECK-RV64-NEXT: addi a1, a1, 16
; CHECK-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: li a1, 32
-; CHECK-RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 4
-; CHECK-RV64-NEXT: csrr a2, vlenb
-; CHECK-RV64-NEXT: slli a2, a2, 5
-; CHECK-RV64-NEXT: add a2, sp, a2
-; CHECK-RV64-NEXT: addi a2, a2, 16
-; CHECK-RV64-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
-; CHECK-RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-RV64-NEXT: vmv.x.s a2, v0
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vcpop.m a3, v0
; CHECK-RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; CHECK-RV64-NEXT: vle32.v v24, (a0)
+; CHECK-RV64-NEXT: vle32.v v16, (a0)
+; CHECK-RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 4
; CHECK-RV64-NEXT: csrr a3, vlenb
-; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: li a4, 24
+; CHECK-RV64-NEXT: mul a3, a3, a4
; CHECK-RV64-NEXT: add a3, sp, a3
; CHECK-RV64-NEXT: addi a3, a3, 16
-; CHECK-RV64-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: csrr a3, vlenb
-; CHECK-RV64-NEXT: slli a3, a3, 5
+; CHECK-RV64-NEXT: li a4, 24
+; CHECK-RV64-NEXT: mul a3, a3, a4
; CHECK-RV64-NEXT: add a3, sp, a3
; CHECK-RV64-NEXT: addi a3, a3, 16
; CHECK-RV64-NEXT: vl1r.v v24, (a3) # vscale x 8-byte Folded Reload
@@ -1214,28 +1245,24 @@ define <64 x i32> @test_expandload_v64i32(ptr %base, <64 x i1> %mask, <64 x i32>
; CHECK-RV64-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-RV64-NEXT: viota.m v24, v0
-; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 4
-; CHECK-RV64-NEXT: add a0, sp, a0
-; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 5
+; CHECK-RV64-NEXT: li a1, 24
+; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: viota.m v16, v24
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 5
+; CHECK-RV64-NEXT: li a1, 24
+; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 24
-; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: slli a0, a0, 4
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -1249,8 +1276,8 @@ define <64 x i32> @test_expandload_v64i32(ptr %base, <64 x i1> %mask, <64 x i32>
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a1, a0, 5
-; CHECK-RV64-NEXT: add a0, a1, a0
+; CHECK-RV64-NEXT: li a1, 25
+; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add sp, sp, a0
; CHECK-RV64-NEXT: .cfi_def_cfa sp, 16
; CHECK-RV64-NEXT: addi sp, sp, 16
@@ -1438,17 +1465,17 @@ define <32 x i64> @test_expandload_v32i64(ptr %base, <32 x i1> %mask, <32 x i64>
; CHECK-RV32-NEXT: addi a1, a1, 16
; CHECK-RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: vmv.x.s a1, v0
-; CHECK-RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-RV32-NEXT: csrr a2, vlenb
-; CHECK-RV32-NEXT: slli a2, a2, 5
-; CHECK-RV32-NEXT: add a2, sp, a2
-; CHECK-RV32-NEXT: addi a2, a2, 16
-; CHECK-RV32-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: zext.h a1, a1
; CHECK-RV32-NEXT: cpop a1, a1
; CHECK-RV32-NEXT: slli a1, a1, 3
; CHECK-RV32-NEXT: add a0, a0, a1
+; CHECK-RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-RV32-NEXT: csrr a1, vlenb
+; CHECK-RV32-NEXT: slli a1, a1, 5
+; CHECK-RV32-NEXT: add a1, sp, a1
+; CHECK-RV32-NEXT: addi a1, a1, 16
+; CHECK-RV32-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: csrr a1, vlenb
; CHECK-RV32-NEXT: slli a1, a1, 5
; CHECK-RV32-NEXT: add a1, sp, a1
@@ -1479,24 +1506,23 @@ define <32 x i64> @test_expandload_v32i64(ptr %base, <32 x i1> %mask, <32 x i64>
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
; CHECK-RV32-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
-; CHECK-RV32-NEXT: viota.m v16, v24
+; CHECK-RV32-NEXT: viota.m v8, v24
; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: slli a0, a0, 5
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
; CHECK-RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 4
+; CHECK-RV32-NEXT: slli a0, a0, 3
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 3
+; CHECK-RV32-NEXT: slli a0, a0, 4
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: vrgather.vv v8, v24, v16, v0.t
-; CHECK-RV32-NEXT: vmv.v.v v16, v8
+; CHECK-RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vrgather.vv v16, v24, v8, v0.t
; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
@@ -1533,17 +1559,17 @@ define <32 x i64> @test_expandload_v32i64(ptr %base, <32 x i1> %mask, <32 x i64>
; CHECK-RV64-NEXT: addi a1, a1, 16
; CHECK-RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: vmv.x.s a1, v0
-; CHECK-RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-RV64-NEXT: csrr a2, vlenb
-; CHECK-RV64-NEXT: slli a2, a2, 5
-; CHECK-RV64-NEXT: add a2, sp, a2
-; CHECK-RV64-NEXT: addi a2, a2, 16
-; CHECK-RV64-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: zext.h a1, a1
; CHECK-RV64-NEXT: cpopw a1, a1
; CHECK-RV64-NEXT: slli a1, a1, 3
; CHECK-RV64-NEXT: add a0, a0, a1
+; CHECK-RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-RV64-NEXT: csrr a1, vlenb
+; CHECK-RV64-NEXT: slli a1, a1, 5
+; CHECK-RV64-NEXT: add a1, sp, a1
+; CHECK-RV64-NEXT: addi a1, a1, 16
+; CHECK-RV64-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: csrr a1, vlenb
; CHECK-RV64-NEXT: slli a1, a1, 5
; CHECK-RV64-NEXT: add a1, sp, a1
@@ -1574,24 +1600,23 @@ define <32 x i64> @test_expandload_v32i64(ptr %base, <32 x i1> %mask, <32 x i64>
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
-; CHECK-RV64-NEXT: viota.m v16, v24
+; CHECK-RV64-NEXT: viota.m v8, v24
; CHECK-RV64-NEXT: csrr a0, vlenb
; CHECK-RV64-NEXT: slli a0, a0, 5
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 4
+; CHECK-RV64-NEXT: slli a0, a0, 3
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 3
+; CHECK-RV64-NEXT: slli a0, a0, 4
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV64-NEXT: vrgather.vv v8, v24, v16, v0.t
-; CHECK-RV64-NEXT: vmv.v.v v16, v8
+; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vrgather.vv v16, v24, v8, v0.t
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
index 62dadfe936e44..e0edf68e949b6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
@@ -139,22 +139,21 @@ define i1 @extractelt_nxv128i1(ptr %x, i64 %idx) nounwind {
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: sub sp, sp, a3
; RV32-NEXT: andi sp, sp, -64
-; RV32-NEXT: addi a3, sp, 64
-; RV32-NEXT: vl8r.v v8, (a0)
; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: vl8r.v v8, (a0)
; RV32-NEXT: add a0, a0, a2
; RV32-NEXT: vl8r.v v16, (a0)
; RV32-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: vmseq.vi v0, v8, 0
-; RV32-NEXT: vmv.v.i v8, 0
-; RV32-NEXT: add a1, a3, a1
-; RV32-NEXT: vmseq.vi v25, v16, 0
-; RV32-NEXT: vmerge.vim v16, v8, 1, v0
-; RV32-NEXT: vs8r.v v16, (a3)
-; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: vmv1r.v v0, v25
-; RV32-NEXT: vmerge.vim v8, v8, 1, v0
-; RV32-NEXT: vs8r.v v8, (a2)
+; RV32-NEXT: vmerge.vim v8, v24, 1, v0
+; RV32-NEXT: vmseq.vi v0, v16, 0
+; RV32-NEXT: vmerge.vim v16, v24, 1, v0
+; RV32-NEXT: addi a0, sp, 64
+; RV32-NEXT: add a1, a0, a1
+; RV32-NEXT: vs8r.v v8, (a0)
+; RV32-NEXT: add a0, a0, a2
+; RV32-NEXT: vs8r.v v16, (a0)
; RV32-NEXT: lbu a0, 0(a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -179,22 +178,21 @@ define i1 @extractelt_nxv128i1(ptr %x, i64 %idx) nounwind {
; RV64-NEXT: slli a3, a3, 4
; RV64-NEXT: sub sp, sp, a3
; RV64-NEXT: andi sp, sp, -64
-; RV64-NEXT: addi a3, sp, 64
-; RV64-NEXT: vl8r.v v8, (a0)
; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: vl8r.v v8, (a0)
; RV64-NEXT: add a0, a0, a2
; RV64-NEXT: vl8r.v v16, (a0)
; RV64-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; RV64-NEXT: vmv.v.i v24, 0
; RV64-NEXT: vmseq.vi v0, v8, 0
-; RV64-NEXT: vmv.v.i v8, 0
-; RV64-NEXT: add a1, a3, a1
-; RV64-NEXT: vmseq.vi v25, v16, 0
-; RV64-NEXT: vmerge.vim v16, v8, 1, v0
-; RV64-NEXT: vs8r.v v16, (a3)
-; RV64-NEXT: add a2, a3, a2
-; RV64-NEXT: vmv1r.v v0, v25
-; RV64-NEXT: vmerge.vim v8, v8, 1, v0
-; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: vmerge.vim v8, v24, 1, v0
+; RV64-NEXT: vmseq.vi v0, v16, 0
+; RV64-NEXT: vmerge.vim v16, v24, 1, v0
+; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: add a1, a0, a1
+; RV64-NEXT: vs8r.v v8, (a0)
+; RV64-NEXT: add a0, a0, a2
+; RV64-NEXT: vs8r.v v16, (a0)
; RV64-NEXT: lbu a0, 0(a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
index fa81e1f6f3514..836883c002b8b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
@@ -382,9 +382,9 @@ define <32 x i64> @vp_abs_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl)
; CHECK-LABEL: vp_abs_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v7, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB34_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
index faf9e630b0e10..ddc0cba841fec 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
@@ -2696,9 +2696,9 @@ define <128 x i16> @vp_bitreverse_v128i16(<128 x i16> %va, <128 x i1> %m, i32 ze
; CHECK-LABEL: vp_bitreverse_v128i16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 64
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v7, v0, 8
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB34_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 64
@@ -2706,59 +2706,50 @@ define <128 x i16> @vp_bitreverse_v128i16(<128 x i16> %va, <128 x i1> %m, i32 ze
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v8, 8, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: lui a2, 1
-; CHECK-NEXT: lui a4, 3
-; CHECK-NEXT: addi a3, a0, -64
-; CHECK-NEXT: sltu a0, a0, a3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a3, a0, a3
-; CHECK-NEXT: lui a0, 5
+; CHECK-NEXT: lui a1, 1
+; CHECK-NEXT: lui a2, 3
+; CHECK-NEXT: lui a3, 5
; CHECK-NEXT: vor.vv v8, v8, v24, v0.t
-; CHECK-NEXT: addi a5, a2, -241
-; CHECK-NEXT: addi a2, a4, 819
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: addi a1, a1, -241
+; CHECK-NEXT: addi a2, a2, 819
+; CHECK-NEXT: addi a3, a3, 1365
; CHECK-NEXT: vsrl.vi v24, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a5, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a5, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
-; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a2, v0.t
; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v24, v16, 4, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a5, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a5, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
-; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a0, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a3, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
+; CHECK-NEXT: addi a4, a0, -64
+; CHECK-NEXT: sltu a0, a0, a4
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a4
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
+; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
+; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
+; CHECK-NEXT: vsrl.vi v24, v16, 4, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
+; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
+; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: vsrl.vi v24, v16, 2, v0.t
; CHECK-NEXT: vand.vx v16, v16, a2, v0.t
; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: vsrl.vi v24, v16, 1, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a0, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a3, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a3, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 1, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
index d8b109fcbf77f..83f08ec191d91 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
@@ -1556,9 +1556,9 @@ define <128 x i16> @vp_bswap_v128i16(<128 x i16> %va, <128 x i1> %m, i32 zeroext
; CHECK-LABEL: vp_bswap_v128i16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 64
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v7, v0, 8
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB26_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 64
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
index 5d1a22368ddef..f4d1c2e291ee6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
@@ -31,12 +31,12 @@ define <2 x half> @vp_ceil_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl)
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -115,12 +115,12 @@ define <4 x half> @vp_ceil_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl)
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
index 0a1dcd4c6abb7..a70aefd2bacf0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
@@ -1887,301 +1887,183 @@ define <16 x i64> @vp_ctlz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v32i64:
; RV32: # %bb.0:
-; RV32-NEXT: li a2, 16
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 49
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: sub sp, sp, a1
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a2, a1, 5
+; RV32-NEXT: add a1, a2, a1
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: li a1, 16
+; RV32-NEXT: mv a2, a0
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v24, v0
-; RV32-NEXT: vslidedown.vi v7, v0, 2
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: bltu a0, a2, .LBB34_2
+; RV32-NEXT: vslidedown.vi v16, v0, 2
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 5
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
+; RV32-NEXT: bltu a0, a1, .LBB34_2
; RV32-NEXT: # %bb.1:
-; RV32-NEXT: li a1, 16
+; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB34_2:
-; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 26
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: sub sp, sp, a2
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
-; RV32-NEXT: vmv1r.v v0, v24
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV32-NEXT: li a2, 32
-; RV32-NEXT: addi a3, a0, -16
-; RV32-NEXT: sltu a0, a0, a3
-; RV32-NEXT: addi a0, a0, -1
-; RV32-NEXT: and a0, a0, a3
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: li a1, 32
; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: addi a3, a3, 1365
-; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v6, v0
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v16, 2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 16, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a5, a4, 3
-; RV32-NEXT: add a4, a5, a4
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: li a5, 25
-; RV32-NEXT: mul a4, a4, a5
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vs1r.v v6, (a4) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a4, a3, 4
-; RV32-NEXT: add a3, a4, a3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.v.x v24, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
+; RV32-NEXT: li a4, 24
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v16, v16, v24, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a3, 209715
+; RV32-NEXT: addi a3, a3, 819
+; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
+; RV32-NEXT: li a4, 41
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
+; RV32-NEXT: li a4, 41
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a4, a3, 4
-; RV32-NEXT: add a3, a4, a3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
+; RV32-NEXT: li a4, 41
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a4, a3, 3
-; RV32-NEXT: add a3, a4, a3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v24, v16, a2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v8, v16, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 3
-; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs1r.v v7, (a2) # vscale x 8-byte Folded Spill
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 4
-; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a4, 61681
+; RV32-NEXT: lui a5, 4112
+; RV32-NEXT: li a3, 56
+; RV32-NEXT: addi a4, a4, -241
+; RV32-NEXT: addi a5, a5, 257
+; RV32-NEXT: vsetvli a6, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a4
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: slli a4, a4, 3
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a5
+; RV32-NEXT: addi a4, sp, 16
+; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v8, v8, a3, v0.t
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
-; RV32-NEXT: vmv1r.v v7, v0
; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: addi a2, a0, -16
+; RV32-NEXT: sltu a0, a0, a2
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 3
-; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: slli a4, a2, 5
+; RV32-NEXT: add a2, a4, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v24, 4, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 3
-; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vadd.vv v24, v8, v24, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 4
-; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v8, v24, 1, v0.t
+; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 24
+; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 41
+; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a2, 61681
-; RV32-NEXT: lui a3, 4112
-; RV32-NEXT: addi a2, a2, -241
-; RV32-NEXT: addi a3, a3, 257
; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a4, 25
-; RV32-NEXT: mul a2, a2, a4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a4, a2, 4
-; RV32-NEXT: add a2, a4, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a3, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 26
+; RV32-NEXT: li a1, 49
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -2192,133 +2074,88 @@ define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV64-LABEL: vp_ctlz_v32i64:
; RV64: # %bb.0:
; RV64-NEXT: li a2, 16
+; RV64-NEXT: mv a1, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v7, v0, 2
-; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB34_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB34_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: li a6, 32
+; RV64-NEXT: li a1, 32
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
; RV64-NEXT: lui a5, 4112
-; RV64-NEXT: addi a7, a2, 1365
-; RV64-NEXT: addi a2, a3, 819
-; RV64-NEXT: addi a3, a4, -241
-; RV64-NEXT: addi a4, a5, 257
-; RV64-NEXT: slli a5, a7, 32
-; RV64-NEXT: add a7, a7, a5
-; RV64-NEXT: slli a5, a2, 32
-; RV64-NEXT: add a5, a2, a5
+; RV64-NEXT: addi a2, a2, 1365
+; RV64-NEXT: addi a3, a3, 819
+; RV64-NEXT: addi a4, a4, -241
+; RV64-NEXT: addi a5, a5, 257
+; RV64-NEXT: slli a6, a2, 32
+; RV64-NEXT: add a6, a2, a6
; RV64-NEXT: slli a2, a3, 32
-; RV64-NEXT: add a2, a3, a2
-; RV64-NEXT: slli a3, a4, 32
-; RV64-NEXT: add a3, a4, a3
-; RV64-NEXT: addi a4, a0, -16
-; RV64-NEXT: sltu a0, a0, a4
-; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a4, a0, a4
-; RV64-NEXT: li a0, 56
+; RV64-NEXT: add a3, a3, a2
+; RV64-NEXT: slli a2, a4, 32
+; RV64-NEXT: add a2, a4, a2
+; RV64-NEXT: slli a4, a5, 32
+; RV64-NEXT: add a4, a5, a4
+; RV64-NEXT: li a5, 56
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 2, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v6, v0
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 8, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 2, v0.t
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 16, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vsrl.vx v24, v8, a1, v0.t
+; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV64-NEXT: vand.vx v24, v8, a3, v0.t
+; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV64-NEXT: vand.vx v8, v8, a3, v0.t
+; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: vsrl.vx v8, v8, a5, v0.t
+; RV64-NEXT: addi a7, a0, -16
+; RV64-NEXT: sltu a0, a0, a7
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a0, a0, a7
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
+; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vsrl.vi v24, v16, 2, v0.t
+; RV64-NEXT: vor.vv v16, v16, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v24, v8, a6, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 8, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vnot.v v8, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 16, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a7, v0.t
-; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v24, v16, a6, v0.t
+; RV64-NEXT: vsrl.vx v24, v16, a1, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v8, a5, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vnot.v v16, v16, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v8, v8, a5, v0.t
-; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a7, v0.t
+; RV64-NEXT: vand.vx v24, v24, a6, v0.t
; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v16, a5, v0.t
+; RV64-NEXT: vand.vx v24, v16, a3, v0.t
; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v16, a5, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v16, v16, a3, v0.t
; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vmul.vx v16, v16, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t
+; RV64-NEXT: vmul.vx v16, v16, a4, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a5, v0.t
; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
@@ -4426,323 +4263,205 @@ define <16 x i64> @vp_ctlz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroex
; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vsrl.vx v16, v8, a4
; RV64-NEXT: vor.vv v8, v8, v16
-; RV64-NEXT: vnot.v v8, v8
-; RV64-NEXT: vsrl.vi v16, v8, 1
-; RV64-NEXT: vand.vx v16, v16, a0
-; RV64-NEXT: vsub.vv v8, v8, v16
-; RV64-NEXT: vand.vx v16, v8, a1
-; RV64-NEXT: vsrl.vi v8, v8, 2
-; RV64-NEXT: vand.vx v8, v8, a1
-; RV64-NEXT: vadd.vv v8, v16, v8
-; RV64-NEXT: vsrl.vi v16, v8, 4
-; RV64-NEXT: vadd.vv v8, v8, v16
-; RV64-NEXT: vand.vx v8, v8, a2
-; RV64-NEXT: vmul.vx v8, v8, a3
-; RV64-NEXT: li a0, 56
-; RV64-NEXT: vsrl.vx v8, v8, a0
-; RV64-NEXT: ret
- %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl)
- ret <16 x i64> %v
-}
-
-define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vp_ctlz_zero_undef_v32i64:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 16
-; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v24, v0
-; RV32-NEXT: vslidedown.vi v7, v0, 2
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: bltu a0, a2, .LBB70_2
-; RV32-NEXT: # %bb.1:
-; RV32-NEXT: li a1, 16
-; RV32-NEXT: .LBB70_2:
-; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 26
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: sub sp, sp, a2
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
-; RV32-NEXT: vmv1r.v v0, v24
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV32-NEXT: li a2, 32
-; RV32-NEXT: addi a3, a0, -16
-; RV32-NEXT: sltu a0, a0, a3
-; RV32-NEXT: addi a0, a0, -1
-; RV32-NEXT: and a0, a0, a3
-; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: addi a3, a3, 1365
-; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v6, v0
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v16, 2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 16, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a5, a4, 3
-; RV32-NEXT: add a4, a5, a4
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: li a5, 25
-; RV32-NEXT: mul a4, a4, a5
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vs1r.v v6, (a4) # vscale x 8-byte Folded Spill
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
+; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vsrl.vi v16, v8, 1
+; RV64-NEXT: vand.vx v16, v16, a0
+; RV64-NEXT: vsub.vv v8, v8, v16
+; RV64-NEXT: vand.vx v16, v8, a1
+; RV64-NEXT: vsrl.vi v8, v8, 2
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vadd.vv v8, v16, v8
+; RV64-NEXT: vsrl.vi v16, v8, 4
+; RV64-NEXT: vadd.vv v8, v8, v16
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vmul.vx v8, v8, a3
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: vsrl.vx v8, v8, a0
+; RV64-NEXT: ret
+ %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl)
+ ret <16 x i64> %v
+}
+
+define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
+; RV32-LABEL: vp_ctlz_zero_undef_v32i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 49
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: sub sp, sp, a1
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a2, a1, 5
+; RV32-NEXT: add a1, a2, a1
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: li a1, 16
+; RV32-NEXT: mv a2, a0
+; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vi v16, v0, 2
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a4, a3, 4
-; RV32-NEXT: add a3, a4, a3
+; RV32-NEXT: slli a3, a3, 5
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
+; RV32-NEXT: bltu a0, a1, .LBB70_2
+; RV32-NEXT: # %bb.1:
+; RV32-NEXT: li a2, 16
+; RV32-NEXT: .LBB70_2:
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: li a1, 32
+; RV32-NEXT: lui a3, 349525
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: addi a3, a3, 1365
+; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v24, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
+; RV32-NEXT: li a4, 24
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v16, v16, v24, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a3, 209715
+; RV32-NEXT: addi a3, a3, 819
+; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
+; RV32-NEXT: li a4, 41
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
+; RV32-NEXT: li a4, 41
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a4, a3, 4
-; RV32-NEXT: add a3, a4, a3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
+; RV32-NEXT: li a4, 41
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a4, a3, 3
-; RV32-NEXT: add a3, a4, a3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v24, v16, a2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v8, v16, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 3
-; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs1r.v v7, (a2) # vscale x 8-byte Folded Spill
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 4
-; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a4, 61681
+; RV32-NEXT: lui a5, 4112
+; RV32-NEXT: li a3, 56
+; RV32-NEXT: addi a4, a4, -241
+; RV32-NEXT: addi a5, a5, 257
+; RV32-NEXT: vsetvli a6, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a4
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: slli a4, a4, 3
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a5
+; RV32-NEXT: addi a4, sp, 16
+; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v8, v8, a3, v0.t
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
-; RV32-NEXT: vmv1r.v v7, v0
; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: addi a2, a0, -16
+; RV32-NEXT: sltu a0, a0, a2
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 3
-; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: slli a4, a2, 5
+; RV32-NEXT: add a2, a4, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v24, 4, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 3
-; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vadd.vv v24, v8, v24, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 4
-; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v8, v24, 1, v0.t
+; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 24
+; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 41
+; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a2, 61681
-; RV32-NEXT: lui a3, 4112
-; RV32-NEXT: addi a2, a2, -241
-; RV32-NEXT: addi a3, a3, 257
; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a4, 25
-; RV32-NEXT: mul a2, a2, a4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a4, a2, 4
-; RV32-NEXT: add a2, a4, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a3, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 26
+; RV32-NEXT: li a1, 49
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -4753,133 +4472,88 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV64-LABEL: vp_ctlz_zero_undef_v32i64:
; RV64: # %bb.0:
; RV64-NEXT: li a2, 16
+; RV64-NEXT: mv a1, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v7, v0, 2
-; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB70_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB70_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: li a6, 32
+; RV64-NEXT: li a1, 32
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
; RV64-NEXT: lui a5, 4112
-; RV64-NEXT: addi a7, a2, 1365
-; RV64-NEXT: addi a2, a3, 819
-; RV64-NEXT: addi a3, a4, -241
-; RV64-NEXT: addi a4, a5, 257
-; RV64-NEXT: slli a5, a7, 32
-; RV64-NEXT: add a7, a7, a5
-; RV64-NEXT: slli a5, a2, 32
-; RV64-NEXT: add a5, a2, a5
+; RV64-NEXT: addi a2, a2, 1365
+; RV64-NEXT: addi a3, a3, 819
+; RV64-NEXT: addi a4, a4, -241
+; RV64-NEXT: addi a5, a5, 257
+; RV64-NEXT: slli a6, a2, 32
+; RV64-NEXT: add a6, a2, a6
; RV64-NEXT: slli a2, a3, 32
-; RV64-NEXT: add a2, a3, a2
-; RV64-NEXT: slli a3, a4, 32
-; RV64-NEXT: add a3, a4, a3
-; RV64-NEXT: addi a4, a0, -16
-; RV64-NEXT: sltu a0, a0, a4
-; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a4, a0, a4
-; RV64-NEXT: li a0, 56
+; RV64-NEXT: add a3, a3, a2
+; RV64-NEXT: slli a2, a4, 32
+; RV64-NEXT: add a2, a4, a2
+; RV64-NEXT: slli a4, a5, 32
+; RV64-NEXT: add a4, a5, a4
+; RV64-NEXT: li a5, 56
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 2, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v6, v0
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 8, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 2, v0.t
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 16, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vsrl.vx v24, v8, a1, v0.t
+; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV64-NEXT: vand.vx v24, v8, a3, v0.t
+; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV64-NEXT: vand.vx v8, v8, a3, v0.t
+; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: vsrl.vx v8, v8, a5, v0.t
+; RV64-NEXT: addi a7, a0, -16
+; RV64-NEXT: sltu a0, a0, a7
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a0, a0, a7
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
+; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vsrl.vi v24, v16, 2, v0.t
+; RV64-NEXT: vor.vv v16, v16, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v24, v8, a6, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 8, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vnot.v v8, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 16, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a7, v0.t
-; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v24, v16, a6, v0.t
+; RV64-NEXT: vsrl.vx v24, v16, a1, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v8, a5, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vnot.v v16, v16, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v8, v8, a5, v0.t
-; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a7, v0.t
+; RV64-NEXT: vand.vx v24, v24, a6, v0.t
; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v16, a5, v0.t
+; RV64-NEXT: vand.vx v24, v16, a3, v0.t
; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v16, a5, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v16, v16, a3, v0.t
; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vmul.vx v16, v16, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t
+; RV64-NEXT: vmul.vx v16, v16, a4, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a5, v0.t
; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
index ec6b0290a18ce..289948dbbf87d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
@@ -1394,122 +1394,219 @@ define <32 x i64> @vp_ctpop_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 24
+; RV32-NEXT: li a2, 49
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
+; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: li a2, 16
+; RV32-NEXT: li a1, 16
+; RV32-NEXT: mv a2, a0
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v16, v0
-; RV32-NEXT: vslidedown.vi v7, v0, 2
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: bltu a0, a2, .LBB34_2
+; RV32-NEXT: vslidedown.vi v16, v0, 2
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 48
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
+; RV32-NEXT: bltu a0, a1, .LBB34_2
; RV32-NEXT: # %bb.1:
-; RV32-NEXT: li a1, 16
+; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB34_2:
-; RV32-NEXT: vmv1r.v v0, v16
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV32-NEXT: lui a2, 349525
-; RV32-NEXT: addi a2, a2, 1365
+; RV32-NEXT: lui a1, 349525
+; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a2
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vmv.v.x v24, a1
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24, v0.t
; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a1
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 40
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 40
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 40
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a3, 61681
+; RV32-NEXT: lui a4, 4112
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: addi a3, a3, -241
+; RV32-NEXT: addi a4, a4, 257
+; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a3
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a4
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: addi a2, sp, 16
; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v6, v0
; RV32-NEXT: addi a2, a0, -16
; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a2
-; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
-; RV32-NEXT: addi a3, sp, 16
-; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: li a3, 48
+; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v8, v24, 1, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 24
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 40
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a2, 61681
-; RV32-NEXT: addi a2, a2, -241
-; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: lui a2, 4112
-; RV32-NEXT: addi a2, a2, 257
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 49
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -1520,82 +1617,61 @@ define <32 x i64> @vp_ctpop_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; RV64-LABEL: vp_ctpop_v32i64:
; RV64: # %bb.0:
; RV64-NEXT: li a2, 16
+; RV64-NEXT: mv a1, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v7, v0, 2
-; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB34_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB34_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: lui a3, 209715
-; RV64-NEXT: lui a4, 61681
-; RV64-NEXT: lui a5, 4112
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: addi a3, a3, 819
-; RV64-NEXT: addi a4, a4, -241
-; RV64-NEXT: addi a5, a5, 257
-; RV64-NEXT: slli a6, a2, 32
-; RV64-NEXT: add a6, a2, a6
-; RV64-NEXT: slli a2, a3, 32
-; RV64-NEXT: add a7, a3, a2
-; RV64-NEXT: slli a3, a4, 32
-; RV64-NEXT: add a3, a4, a3
-; RV64-NEXT: slli a2, a5, 32
-; RV64-NEXT: add a2, a5, a2
-; RV64-NEXT: addi a4, a0, -16
-; RV64-NEXT: sltu a0, a0, a4
-; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a4, a0, a4
-; RV64-NEXT: li a0, 56
-; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: lui a2, 209715
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: lui a4, 4112
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: addi a2, a2, 819
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 257
+; RV64-NEXT: slli a5, a1, 32
+; RV64-NEXT: add a1, a1, a5
+; RV64-NEXT: slli a5, a2, 32
+; RV64-NEXT: add a2, a2, a5
+; RV64-NEXT: slli a5, a3, 32
+; RV64-NEXT: add a3, a3, a5
+; RV64-NEXT: slli a5, a4, 32
+; RV64-NEXT: add a4, a4, a5
+; RV64-NEXT: li a5, 56
+; RV64-NEXT: vand.vx v24, v24, a1, v0.t
; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v6, v0
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a6, v0.t
-; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v8, a7, v0.t
+; RV64-NEXT: vand.vx v24, v8, a2, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a7, v0.t
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v16, a7, v0.t
-; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a7, v0.t
-; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
+; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: vsrl.vx v8, v8, a5, v0.t
+; RV64-NEXT: addi a6, a0, -16
+; RV64-NEXT: sltu a0, a0, a6
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a0, a0, a6
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a1, v0.t
+; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
+; RV64-NEXT: vand.vx v24, v16, a2, v0.t
+; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
+; RV64-NEXT: vand.vx v16, v16, a2, v0.t
+; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vmul.vx v8, v8, a2, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v16, a3, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vmul.vx v16, v16, a2, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t
+; RV64-NEXT: vmul.vx v16, v16, a4, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a5, v0.t
; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.ctpop.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
index 5ad84a7fe96c5..46d62f48e7ef8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
@@ -1526,253 +1526,160 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 26
+; RV32-NEXT: li a2, 49
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: slli a2, a1, 5
+; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: li a2, 16
+; RV32-NEXT: li a1, 16
+; RV32-NEXT: mv a2, a0
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v24, v0, 2
+; RV32-NEXT: vslidedown.vi v16, v0, 2
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 5
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
+; RV32-NEXT: bltu a0, a1, .LBB34_2
+; RV32-NEXT: # %bb.1:
+; RV32-NEXT: li a2, 16
+; RV32-NEXT: .LBB34_2:
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vadd.vi v16, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: lui a1, 349525
+; RV32-NEXT: vand.vv v24, v8, v16, v0.t
+; RV32-NEXT: addi a1, a1, 1365
+; RV32-NEXT: vsrl.vi v16, v24, 1, v0.t
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v8, a1
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a3, 24
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: bltu a0, a2, .LBB34_2
-; RV32-NEXT: # %bb.1:
-; RV32-NEXT: li a1, 16
-; RV32-NEXT: .LBB34_2:
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vadd.vi v24, v8, -1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v16, v16, v8, v0.t
+; RV32-NEXT: vsub.vv v8, v24, v16, v0.t
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a1
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 41
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 41
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 41
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a3, 61681
+; RV32-NEXT: lui a4, 4112
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: addi a3, a3, -241
+; RV32-NEXT: addi a4, a4, 257
+; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
-; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a2
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v16, v24, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: vmv.v.x v16, a4
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: addi a2, a0, -16
; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vi v8, v16, -1, v0.t
-; RV32-NEXT: vnot.v v16, v16, v0.t
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v24, v16, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v24, 4, v0.t
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vadd.vv v24, v8, v24, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl1r.v v7, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: slli a3, a2, 5
+; RV32-NEXT: add a2, a3, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vadd.vi v8, v24, -1, v0.t
+; RV32-NEXT: vnot.v v24, v24, v0.t
+; RV32-NEXT: vand.vv v8, v24, v8, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 24
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 41
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a2, 61681
-; RV32-NEXT: addi a2, a2, -241
; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: vmv1r.v v6, v0
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: lui a2, 4112
-; RV32-NEXT: addi a2, a2, 257
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 26
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 49
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -1783,9 +1690,9 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV64-LABEL: vp_cttz_v32i64:
; RV64: # %bb.0:
; RV64-NEXT: li a2, 16
+; RV64-NEXT: mv a1, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v7, v0, 2
-; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB34_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
@@ -1793,78 +1700,57 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vadd.vi v24, v8, -1, v0.t
; RV64-NEXT: vnot.v v8, v8, v0.t
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: lui a3, 209715
-; RV64-NEXT: lui a4, 61681
-; RV64-NEXT: lui a5, 4112
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: addi a3, a3, 819
-; RV64-NEXT: addi a4, a4, -241
-; RV64-NEXT: addi a5, a5, 257
-; RV64-NEXT: slli a6, a2, 32
-; RV64-NEXT: add a6, a2, a6
-; RV64-NEXT: slli a2, a3, 32
-; RV64-NEXT: add a7, a3, a2
-; RV64-NEXT: slli a2, a4, 32
-; RV64-NEXT: add a2, a4, a2
-; RV64-NEXT: slli a3, a5, 32
-; RV64-NEXT: add a3, a5, a3
-; RV64-NEXT: addi a4, a0, -16
-; RV64-NEXT: sltu a0, a0, a4
-; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a4, a0, a4
-; RV64-NEXT: li a0, 56
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: lui a2, 209715
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: lui a4, 4112
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: addi a2, a2, 819
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 257
+; RV64-NEXT: slli a5, a1, 32
+; RV64-NEXT: add a1, a1, a5
+; RV64-NEXT: slli a5, a2, 32
+; RV64-NEXT: add a2, a2, a5
+; RV64-NEXT: slli a5, a3, 32
+; RV64-NEXT: add a3, a3, a5
+; RV64-NEXT: slli a5, a4, 32
+; RV64-NEXT: add a4, a4, a5
+; RV64-NEXT: li a5, 56
; RV64-NEXT: vand.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a6, v0.t
-; RV64-NEXT: vsub.vv v24, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v6, v0
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vadd.vi v8, v16, -1, v0.t
-; RV64-NEXT: vnot.v v16, v16, v0.t
-; RV64-NEXT: vand.vv v8, v16, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v24, a7, v0.t
-; RV64-NEXT: vsrl.vi v24, v24, 2, v0.t
-; RV64-NEXT: vand.vx v24, v24, a7, v0.t
-; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: vand.vx v24, v24, a1, v0.t
; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v8, a7, v0.t
+; RV64-NEXT: vand.vx v24, v8, a2, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a7, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vadd.vv v24, v24, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vmul.vx v8, v16, a3, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v16, v24, 4, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV64-NEXT: vand.vx v8, v8, a3, v0.t
+; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: vsrl.vx v8, v8, a5, v0.t
+; RV64-NEXT: addi a6, a0, -16
+; RV64-NEXT: sltu a0, a0, a6
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a0, a0, a6
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vadd.vi v24, v16, -1, v0.t
+; RV64-NEXT: vnot.v v16, v16, v0.t
+; RV64-NEXT: vand.vv v16, v16, v24, v0.t
+; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a1, v0.t
+; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
+; RV64-NEXT: vand.vx v24, v16, a2, v0.t
+; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vmul.vx v16, v16, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t
+; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
+; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV64-NEXT: vand.vx v16, v16, a3, v0.t
+; RV64-NEXT: vmul.vx v16, v16, a4, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a5, v0.t
; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
@@ -3569,253 +3455,160 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 26
+; RV32-NEXT: li a2, 49
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: slli a2, a1, 5
+; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: li a2, 16
+; RV32-NEXT: li a1, 16
+; RV32-NEXT: mv a2, a0
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v24, v0, 2
+; RV32-NEXT: vslidedown.vi v16, v0, 2
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 5
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
+; RV32-NEXT: bltu a0, a1, .LBB70_2
+; RV32-NEXT: # %bb.1:
+; RV32-NEXT: li a2, 16
+; RV32-NEXT: .LBB70_2:
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vadd.vi v16, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: lui a1, 349525
+; RV32-NEXT: vand.vv v24, v8, v16, v0.t
+; RV32-NEXT: addi a1, a1, 1365
+; RV32-NEXT: vsrl.vi v16, v24, 1, v0.t
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v8, a1
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a3, 24
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: bltu a0, a2, .LBB70_2
-; RV32-NEXT: # %bb.1:
-; RV32-NEXT: li a1, 16
-; RV32-NEXT: .LBB70_2:
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vadd.vi v24, v8, -1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v16, v16, v8, v0.t
+; RV32-NEXT: vsub.vv v8, v24, v16, v0.t
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a1
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 41
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 41
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 41
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a3, 61681
+; RV32-NEXT: lui a4, 4112
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: addi a3, a3, -241
+; RV32-NEXT: addi a4, a4, 257
+; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
-; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a2
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v16, v24, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: vmv.v.x v16, a4
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: addi a2, a0, -16
; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vi v8, v16, -1, v0.t
-; RV32-NEXT: vnot.v v16, v16, v0.t
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v24, v16, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v24, 4, v0.t
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vadd.vv v24, v8, v24, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl1r.v v7, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: slli a3, a2, 5
+; RV32-NEXT: add a2, a3, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vadd.vi v8, v24, -1, v0.t
+; RV32-NEXT: vnot.v v24, v24, v0.t
+; RV32-NEXT: vand.vv v8, v24, v8, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 24
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 41
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a2, 61681
-; RV32-NEXT: addi a2, a2, -241
; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: vmv1r.v v6, v0
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: lui a2, 4112
-; RV32-NEXT: addi a2, a2, 257
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 26
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 49
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -3826,9 +3619,9 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV64-LABEL: vp_cttz_zero_undef_v32i64:
; RV64: # %bb.0:
; RV64-NEXT: li a2, 16
+; RV64-NEXT: mv a1, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v7, v0, 2
-; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB70_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
@@ -3836,78 +3629,57 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vadd.vi v24, v8, -1, v0.t
; RV64-NEXT: vnot.v v8, v8, v0.t
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: lui a3, 209715
-; RV64-NEXT: lui a4, 61681
-; RV64-NEXT: lui a5, 4112
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: addi a3, a3, 819
-; RV64-NEXT: addi a4, a4, -241
-; RV64-NEXT: addi a5, a5, 257
-; RV64-NEXT: slli a6, a2, 32
-; RV64-NEXT: add a6, a2, a6
-; RV64-NEXT: slli a2, a3, 32
-; RV64-NEXT: add a7, a3, a2
-; RV64-NEXT: slli a2, a4, 32
-; RV64-NEXT: add a2, a4, a2
-; RV64-NEXT: slli a3, a5, 32
-; RV64-NEXT: add a3, a5, a3
-; RV64-NEXT: addi a4, a0, -16
-; RV64-NEXT: sltu a0, a0, a4
-; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a4, a0, a4
-; RV64-NEXT: li a0, 56
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: lui a2, 209715
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: lui a4, 4112
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: addi a2, a2, 819
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 257
+; RV64-NEXT: slli a5, a1, 32
+; RV64-NEXT: add a1, a1, a5
+; RV64-NEXT: slli a5, a2, 32
+; RV64-NEXT: add a2, a2, a5
+; RV64-NEXT: slli a5, a3, 32
+; RV64-NEXT: add a3, a3, a5
+; RV64-NEXT: slli a5, a4, 32
+; RV64-NEXT: add a4, a4, a5
+; RV64-NEXT: li a5, 56
; RV64-NEXT: vand.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a6, v0.t
-; RV64-NEXT: vsub.vv v24, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v6, v0
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vadd.vi v8, v16, -1, v0.t
-; RV64-NEXT: vnot.v v16, v16, v0.t
-; RV64-NEXT: vand.vv v8, v16, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v24, a7, v0.t
-; RV64-NEXT: vsrl.vi v24, v24, 2, v0.t
-; RV64-NEXT: vand.vx v24, v24, a7, v0.t
-; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: vand.vx v24, v24, a1, v0.t
; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v8, a7, v0.t
+; RV64-NEXT: vand.vx v24, v8, a2, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a7, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vadd.vv v24, v24, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vmul.vx v8, v16, a3, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v16, v24, 4, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV64-NEXT: vand.vx v8, v8, a3, v0.t
+; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: vsrl.vx v8, v8, a5, v0.t
+; RV64-NEXT: addi a6, a0, -16
+; RV64-NEXT: sltu a0, a0, a6
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a0, a0, a6
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vadd.vi v24, v16, -1, v0.t
+; RV64-NEXT: vnot.v v16, v16, v0.t
+; RV64-NEXT: vand.vv v16, v16, v24, v0.t
+; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a1, v0.t
+; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
+; RV64-NEXT: vand.vx v24, v16, a2, v0.t
+; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vmul.vx v16, v16, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t
+; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
+; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV64-NEXT: vand.vx v16, v16, a3, v0.t
+; RV64-NEXT: vmul.vx v16, v16, a4, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a5, v0.t
; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
index f37a3cf5e6bb2..5060e01cf9ee6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
@@ -324,24 +324,23 @@ define i1 @extractelt_v256i1(ptr %x, i64 %idx) nounwind {
; RV32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
; RV32-NEXT: addi s0, sp, 384
; RV32-NEXT: andi sp, sp, -128
-; RV32-NEXT: zext.b a1, a1
; RV32-NEXT: li a2, 128
-; RV32-NEXT: addi a3, a0, 128
; RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; RV32-NEXT: vle8.v v16, (a3)
-; RV32-NEXT: mv a2, sp
; RV32-NEXT: vle8.v v8, (a0)
-; RV32-NEXT: addi a0, sp, 128
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: vmseq.vi v24, v16, 0
-; RV32-NEXT: vmv.v.i v16, 0
+; RV32-NEXT: addi a0, a0, 128
+; RV32-NEXT: vle8.v v16, (a0)
+; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: vmseq.vi v0, v8, 0
-; RV32-NEXT: vmerge.vim v8, v16, 1, v0
-; RV32-NEXT: vmv1r.v v0, v24
-; RV32-NEXT: vmerge.vim v16, v16, 1, v0
-; RV32-NEXT: vse8.v v8, (a2)
-; RV32-NEXT: vse8.v v16, (a0)
-; RV32-NEXT: lbu a0, 0(a1)
+; RV32-NEXT: vmerge.vim v8, v24, 1, v0
+; RV32-NEXT: vmseq.vi v0, v16, 0
+; RV32-NEXT: vmerge.vim v16, v24, 1, v0
+; RV32-NEXT: zext.b a0, a1
+; RV32-NEXT: mv a1, sp
+; RV32-NEXT: addi a2, sp, 128
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: vse8.v v8, (a1)
+; RV32-NEXT: vse8.v v16, (a2)
+; RV32-NEXT: lbu a0, 0(a0)
; RV32-NEXT: addi sp, s0, -384
; RV32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
@@ -355,24 +354,23 @@ define i1 @extractelt_v256i1(ptr %x, i64 %idx) nounwind {
; RV64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
; RV64-NEXT: addi s0, sp, 384
; RV64-NEXT: andi sp, sp, -128
-; RV64-NEXT: zext.b a1, a1
; RV64-NEXT: li a2, 128
-; RV64-NEXT: addi a3, a0, 128
; RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; RV64-NEXT: vle8.v v16, (a3)
-; RV64-NEXT: mv a2, sp
; RV64-NEXT: vle8.v v8, (a0)
-; RV64-NEXT: addi a0, sp, 128
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: vmseq.vi v24, v16, 0
-; RV64-NEXT: vmv.v.i v16, 0
+; RV64-NEXT: addi a0, a0, 128
+; RV64-NEXT: vle8.v v16, (a0)
+; RV64-NEXT: vmv.v.i v24, 0
; RV64-NEXT: vmseq.vi v0, v8, 0
-; RV64-NEXT: vmerge.vim v8, v16, 1, v0
-; RV64-NEXT: vmv1r.v v0, v24
-; RV64-NEXT: vmerge.vim v16, v16, 1, v0
-; RV64-NEXT: vse8.v v8, (a2)
-; RV64-NEXT: vse8.v v16, (a0)
-; RV64-NEXT: lbu a0, 0(a1)
+; RV64-NEXT: vmerge.vim v8, v24, 1, v0
+; RV64-NEXT: vmseq.vi v0, v16, 0
+; RV64-NEXT: vmerge.vim v16, v24, 1, v0
+; RV64-NEXT: zext.b a0, a1
+; RV64-NEXT: mv a1, sp
+; RV64-NEXT: addi a2, sp, 128
+; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: vse8.v v8, (a1)
+; RV64-NEXT: vse8.v v16, (a2)
+; RV64-NEXT: lbu a0, 0(a0)
; RV64-NEXT: addi sp, s0, -384
; RV64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
@@ -386,24 +384,23 @@ define i1 @extractelt_v256i1(ptr %x, i64 %idx) nounwind {
; RV32ZBS-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
; RV32ZBS-NEXT: addi s0, sp, 384
; RV32ZBS-NEXT: andi sp, sp, -128
-; RV32ZBS-NEXT: zext.b a1, a1
; RV32ZBS-NEXT: li a2, 128
-; RV32ZBS-NEXT: addi a3, a0, 128
; RV32ZBS-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; RV32ZBS-NEXT: vle8.v v16, (a3)
-; RV32ZBS-NEXT: mv a2, sp
; RV32ZBS-NEXT: vle8.v v8, (a0)
-; RV32ZBS-NEXT: addi a0, sp, 128
-; RV32ZBS-NEXT: add a1, a2, a1
-; RV32ZBS-NEXT: vmseq.vi v24, v16, 0
-; RV32ZBS-NEXT: vmv.v.i v16, 0
+; RV32ZBS-NEXT: addi a0, a0, 128
+; RV32ZBS-NEXT: vle8.v v16, (a0)
+; RV32ZBS-NEXT: vmv.v.i v24, 0
; RV32ZBS-NEXT: vmseq.vi v0, v8, 0
-; RV32ZBS-NEXT: vmerge.vim v8, v16, 1, v0
-; RV32ZBS-NEXT: vmv1r.v v0, v24
-; RV32ZBS-NEXT: vmerge.vim v16, v16, 1, v0
-; RV32ZBS-NEXT: vse8.v v8, (a2)
-; RV32ZBS-NEXT: vse8.v v16, (a0)
-; RV32ZBS-NEXT: lbu a0, 0(a1)
+; RV32ZBS-NEXT: vmerge.vim v8, v24, 1, v0
+; RV32ZBS-NEXT: vmseq.vi v0, v16, 0
+; RV32ZBS-NEXT: vmerge.vim v16, v24, 1, v0
+; RV32ZBS-NEXT: zext.b a0, a1
+; RV32ZBS-NEXT: mv a1, sp
+; RV32ZBS-NEXT: addi a2, sp, 128
+; RV32ZBS-NEXT: add a0, a1, a0
+; RV32ZBS-NEXT: vse8.v v8, (a1)
+; RV32ZBS-NEXT: vse8.v v16, (a2)
+; RV32ZBS-NEXT: lbu a0, 0(a0)
; RV32ZBS-NEXT: addi sp, s0, -384
; RV32ZBS-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
; RV32ZBS-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
@@ -417,24 +414,23 @@ define i1 @extractelt_v256i1(ptr %x, i64 %idx) nounwind {
; RV64ZBS-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
; RV64ZBS-NEXT: addi s0, sp, 384
; RV64ZBS-NEXT: andi sp, sp, -128
-; RV64ZBS-NEXT: zext.b a1, a1
; RV64ZBS-NEXT: li a2, 128
-; RV64ZBS-NEXT: addi a3, a0, 128
; RV64ZBS-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; RV64ZBS-NEXT: vle8.v v16, (a3)
-; RV64ZBS-NEXT: mv a2, sp
; RV64ZBS-NEXT: vle8.v v8, (a0)
-; RV64ZBS-NEXT: addi a0, sp, 128
-; RV64ZBS-NEXT: add a1, a2, a1
-; RV64ZBS-NEXT: vmseq.vi v24, v16, 0
-; RV64ZBS-NEXT: vmv.v.i v16, 0
+; RV64ZBS-NEXT: addi a0, a0, 128
+; RV64ZBS-NEXT: vle8.v v16, (a0)
+; RV64ZBS-NEXT: vmv.v.i v24, 0
; RV64ZBS-NEXT: vmseq.vi v0, v8, 0
-; RV64ZBS-NEXT: vmerge.vim v8, v16, 1, v0
-; RV64ZBS-NEXT: vmv1r.v v0, v24
-; RV64ZBS-NEXT: vmerge.vim v16, v16, 1, v0
-; RV64ZBS-NEXT: vse8.v v8, (a2)
-; RV64ZBS-NEXT: vse8.v v16, (a0)
-; RV64ZBS-NEXT: lbu a0, 0(a1)
+; RV64ZBS-NEXT: vmerge.vim v8, v24, 1, v0
+; RV64ZBS-NEXT: vmseq.vi v0, v16, 0
+; RV64ZBS-NEXT: vmerge.vim v16, v24, 1, v0
+; RV64ZBS-NEXT: zext.b a0, a1
+; RV64ZBS-NEXT: mv a1, sp
+; RV64ZBS-NEXT: addi a2, sp, 128
+; RV64ZBS-NEXT: add a0, a1, a0
+; RV64ZBS-NEXT: vse8.v v8, (a1)
+; RV64ZBS-NEXT: vse8.v v16, (a2)
+; RV64ZBS-NEXT: lbu a0, 0(a0)
; RV64ZBS-NEXT: addi sp, s0, -384
; RV64ZBS-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; RV64ZBS-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
index b5ec8d73c48de..de4cff9b4c3e0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
@@ -31,12 +31,12 @@ define <2 x half> @vp_floor_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl)
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -115,12 +115,12 @@ define <4 x half> @vp_floor_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl)
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
index d0dd105deb029..21dab2385a796 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
@@ -526,13 +526,12 @@ define <32 x double> @vfmax_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a3, 41
+; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a3, 24
-; CHECK-NEXT: mul a1, a1, a3
+; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
@@ -540,126 +539,59 @@ define <32 x double> @vfmax_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a1)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vle64.v v16, (a0)
+; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a4, a3, 5
-; CHECK-NEXT: add a3, a4, a3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 5
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vslidedown.vi v6, v0, 2
; CHECK-NEXT: bltu a2, a1, .LBB24_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB24_2:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a3, a1, 5
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v24, v8, v8, v0.t
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a3, a1, 5
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v25, v16, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vmv1r.v v7, v25
-; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v7, v24, v24, v0.t
+; CHECK-NEXT: vmv1r.v v5, v0
+; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
+; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vfmax.vv v8, v8, v16, v0.t
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: addi a0, a2, -16
+; CHECK-NEXT: sltu a1, a2, a0
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
-; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: addi a1, a2, -16
-; CHECK-NEXT: sltu a2, a2, a1
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a1, a2, a1
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 5
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: li a3, 24
-; CHECK-NEXT: mul a2, a2, a3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v7, v8, v8, v0.t
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 4
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v6, v8, v8, v0.t
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a3, a2, 5
-; CHECK-NEXT: add a2, a3, a2
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfmax.vv v16, v16, v24, v0.t
+; CHECK-NEXT: vmfeq.vv v16, v24, v24, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a2, a0, 5
-; CHECK-NEXT: add a0, a2, a0
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmfeq.vv v7, v8, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a2, 24
-; CHECK-NEXT: mul a0, a0, a2
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0
+; CHECK-NEXT: vmerge.vvm v24, v8, v24, v0
; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vfmax.vv v16, v16, v24, v0.t
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a1, a0, 5
-; CHECK-NEXT: add a0, a1, a0
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vfmax.vv v16, v24, v16, v0.t
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 41
+; CHECK-NEXT: li a1, 24
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
@@ -680,13 +612,16 @@ define <32 x double> @vfmax_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a1)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
@@ -699,26 +634,25 @@ define <32 x double> @vfmax_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: .LBB25_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v24, v24
; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
; CHECK-NEXT: vfmax.vv v8, v8, v16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -726,10 +660,7 @@ define <32 x double> @vfmax_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
; CHECK-NEXT: vfmax.vv v16, v16, v24
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
index 6897082b4fb83..45c047b12f704 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
@@ -526,13 +526,12 @@ define <32 x double> @vfmin_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a3, 41
+; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a3, 24
-; CHECK-NEXT: mul a1, a1, a3
+; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
@@ -540,126 +539,59 @@ define <32 x double> @vfmin_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a1)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vle64.v v16, (a0)
+; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: mv a0, a2
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a4, a3, 5
-; CHECK-NEXT: add a3, a4, a3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 5
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vslidedown.vi v6, v0, 2
; CHECK-NEXT: bltu a2, a1, .LBB24_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB24_2:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a3, a1, 5
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v24, v8, v8, v0.t
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a3, a1, 5
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v25, v16, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vmv1r.v v7, v25
-; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
+; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v7, v24, v24, v0.t
+; CHECK-NEXT: vmv1r.v v5, v0
+; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
+; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vfmin.vv v8, v8, v16, v0.t
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: addi a0, a2, -16
+; CHECK-NEXT: sltu a1, a2, a0
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0
-; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: addi a1, a2, -16
-; CHECK-NEXT: sltu a2, a2, a1
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a1, a2, a1
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 5
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: li a3, 24
-; CHECK-NEXT: mul a2, a2, a3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v7, v8, v8, v0.t
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 4
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v6, v8, v8, v0.t
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a3, a2, 5
-; CHECK-NEXT: add a2, a3, a2
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-NEXT: vfmin.vv v16, v16, v24, v0.t
+; CHECK-NEXT: vmfeq.vv v16, v24, v24, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a2, a0, 5
-; CHECK-NEXT: add a0, a2, a0
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmfeq.vv v7, v8, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a2, 24
-; CHECK-NEXT: mul a0, a0, a2
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0
+; CHECK-NEXT: vmerge.vvm v24, v8, v24, v0
; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vfmin.vv v16, v16, v24, v0.t
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a1, a0, 5
-; CHECK-NEXT: add a0, a1, a0
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vfmin.vv v16, v24, v16, v0.t
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 41
+; CHECK-NEXT: li a1, 24
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
@@ -680,13 +612,16 @@ define <32 x double> @vfmin_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a1)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
@@ -699,26 +634,25 @@ define <32 x double> @vfmin_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: .LBB25_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v24, v24
; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
; CHECK-NEXT: vfmin.vv v8, v8, v16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -726,10 +660,7 @@ define <32 x double> @vfmin_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
; CHECK-NEXT: vfmin.vv v16, v16, v24
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
index 135088631abac..19bedd47808fd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
@@ -87,9 +87,9 @@ define <32 x double> @vfpext_v32f32_v32f64(<32 x float> %a, <32 x i1> %m, i32 ze
; CHECK-LABEL: vfpext_v32f32_v32f64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB7_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
index 96eda109e1c70..b298a37655a2f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
@@ -367,9 +367,9 @@ define <32 x i64> @vfptosi_v32i64_v32f64(<32 x double> %va, <32 x i1> %m, i32 ze
; CHECK-LABEL: vfptosi_v32i64_v32f64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB25_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
index 4020100bf364b..ac83f1e630ce3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
@@ -367,9 +367,9 @@ define <32 x i64> @vfptoui_v32i64_v32f64(<32 x double> %va, <32 x i1> %m, i32 ze
; CHECK-LABEL: vfptoui_v32i64_v32f64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB25_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
index e509722b623a2..472ed89cce10c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
@@ -89,8 +89,8 @@ define <32 x float> @vfptrunc_v32f32_v32f64(<32 x double> %a, <32 x i1> %m, i32
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: vslidedown.vi v12, v0, 2
; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: vslidedown.vi v12, v0, 2
; CHECK-NEXT: bltu a0, a2, .LBB7_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
index 8fde7053e5a50..e1fbf9c511d81 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
@@ -530,231 +530,192 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 70
+; RV32-NEXT: li a3, 76
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: sub sp, sp, a2
-; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc6, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 70 * vlenb
-; RV32-NEXT: addi a6, a1, 128
-; RV32-NEXT: li a2, 32
+; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xcc, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 76 * vlenb
+; RV32-NEXT: addi a5, a1, 128
+; RV32-NEXT: li a6, 32
; RV32-NEXT: lui a4, 12291
-; RV32-NEXT: lui a7, %hi(.LCPI27_0)
-; RV32-NEXT: addi a7, a7, %lo(.LCPI27_0)
; RV32-NEXT: lui a3, 49164
-; RV32-NEXT: lui a5, 196656
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; RV32-NEXT: vle32.v v16, (a6)
-; RV32-NEXT: lui a6, 786624
-; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
-; RV32-NEXT: vle16.v v8, (a7)
-; RV32-NEXT: csrr a7, vlenb
-; RV32-NEXT: li t0, 66
-; RV32-NEXT: mul a7, a7, t0
-; RV32-NEXT: add a7, sp, a7
-; RV32-NEXT: addi a7, a7, 16
-; RV32-NEXT: vs2r.v v8, (a7) # vscale x 16-byte Folded Spill
-; RV32-NEXT: lui a7, 768
+; RV32-NEXT: lui a2, 196656
+; RV32-NEXT: vsetvli zero, a6, e32, m8, ta, ma
+; RV32-NEXT: vle32.v v8, (a5)
+; RV32-NEXT: lui a5, 786624
+; RV32-NEXT: vle32.v v24, (a1)
; RV32-NEXT: addi a4, a4, 3
; RV32-NEXT: vmv.s.x v0, a4
-; RV32-NEXT: lui a4, 3073
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; RV32-NEXT: vle32.v v8, (a1)
+; RV32-NEXT: lui a4, 768
; RV32-NEXT: addi a3, a3, 12
-; RV32-NEXT: addi a5, a5, 48
-; RV32-NEXT: addi a6, a6, 192
-; RV32-NEXT: addi a7, a7, 768
-; RV32-NEXT: addi a4, a4, -1024
-; RV32-NEXT: vmv.s.x v25, a3
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li t0, 58
-; RV32-NEXT: mul a3, a3, t0
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs1r.v v25, (a3) # vscale x 8-byte Folded Spill
-; RV32-NEXT: vmv.s.x v7, a5
-; RV32-NEXT: vmv.s.x v6, a6
-; RV32-NEXT: vmv.s.x v5, a7
-; RV32-NEXT: vmerge.vvm v24, v16, v8, v0
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a5, 34
-; RV32-NEXT: mul a3, a3, a5
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv.s.x v4, a4
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 58
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vmerge.vvm v24, v16, v8, v0
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 1
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vmerge.vvm v24, v16, v8, v0
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 22
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vmerge.vvm v24, v16, v8, v0
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 42
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v5
-; RV32-NEXT: vmerge.vvm v24, v16, v8, v0
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 50
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v4
-; RV32-NEXT: vmerge.vvm v8, v16, v8, v0
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 58
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 66
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl2r.v v8, (a3) # vscale x 16-byte Folded Reload
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 34
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vrgatherei16.vv v16, v24, v8
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 14
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV32-NEXT: csrr a6, vlenb
+; RV32-NEXT: li a7, 48
+; RV32-NEXT: mul a6, a6, a7
+; RV32-NEXT: add a6, sp, a6
+; RV32-NEXT: addi a6, a6, 16
+; RV32-NEXT: vs8r.v v16, (a6) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.s.x v0, a3
+; RV32-NEXT: lui a3, 3073
+; RV32-NEXT: addi a2, a2, 48
+; RV32-NEXT: addi a5, a5, 192
+; RV32-NEXT: addi a4, a4, 768
+; RV32-NEXT: addi a3, a3, -1024
+; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV32-NEXT: csrr a6, vlenb
+; RV32-NEXT: li a7, 20
+; RV32-NEXT: mul a6, a6, a7
+; RV32-NEXT: add a6, sp, a6
+; RV32-NEXT: addi a6, a6, 16
+; RV32-NEXT: vs8r.v v16, (a6) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.s.x v0, a2
+; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 5
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.s.x v0, a5
+; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a5, 40
+; RV32-NEXT: mul a2, a2, a5
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.s.x v0, a4
+; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a4, 56
+; RV32-NEXT: mul a2, a2, a4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.s.x v0, a3
+; RV32-NEXT: vmerge.vvm v8, v8, v24, v0
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 6
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: addi a1, a1, 256
-; RV32-NEXT: lui a3, 12
-; RV32-NEXT: lui a4, 3
-; RV32-NEXT: li a5, 48
-; RV32-NEXT: li a6, 192
-; RV32-NEXT: addi a4, a4, 3
-; RV32-NEXT: addi a7, a3, 12
-; RV32-NEXT: vmv.s.x v28, a5
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; RV32-NEXT: lui a2, 12
+; RV32-NEXT: lui a3, 3
+; RV32-NEXT: li a4, 48
+; RV32-NEXT: li a5, 192
; RV32-NEXT: vle32.v v8, (a1)
-; RV32-NEXT: vmv.s.x v7, a6
-; RV32-NEXT: vmv.s.x v0, a4
-; RV32-NEXT: vmv.s.x v29, a7
+; RV32-NEXT: addi a3, a3, 3
+; RV32-NEXT: addi a1, a2, 12
+; RV32-NEXT: vmv.s.x v0, a3
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
-; RV32-NEXT: vslidedown.vi v16, v8, 16
+; RV32-NEXT: vslidedown.vi v24, v8, 16
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
-; RV32-NEXT: vmerge.vvm v24, v16, v8, v0
-; RV32-NEXT: vmv1r.v v0, v29
-; RV32-NEXT: vmerge.vvm v12, v16, v8, v0
+; RV32-NEXT: vmerge.vvm v12, v24, v8, v0
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs4r.v v12, (a3) # vscale x 32-byte Folded Spill
+; RV32-NEXT: vmv.s.x v0, a1
+; RV32-NEXT: vmerge.vvm v12, v24, v8, v0
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 10
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: li a3, 12
+; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v28
-; RV32-NEXT: vmerge.vvm v12, v16, v8, v0
+; RV32-NEXT: vmv.s.x v0, a4
+; RV32-NEXT: vmerge.vvm v12, v24, v8, v0
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 34
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: li a3, 28
+; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
+; RV32-NEXT: vmv.s.x v0, a5
; RV32-NEXT: vslideup.vi v12, v8, 4
-; RV32-NEXT: vslideup.vi v28, v8, 2
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vmerge.vvm v8, v16, v8, v0
+; RV32-NEXT: vslideup.vi v4, v8, 2
+; RV32-NEXT: vmerge.vvm v8, v24, v8, v0
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 30
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
-; RV32-NEXT: lui a1, %hi(.LCPI27_1)
-; RV32-NEXT: addi a1, a1, %lo(.LCPI27_1)
-; RV32-NEXT: vmv.s.x v0, a3
-; RV32-NEXT: vslideup.vi v12, v16, 10, v0.t
+; RV32-NEXT: lui a1, %hi(.LCPI27_0)
+; RV32-NEXT: addi a1, a1, %lo(.LCPI27_0)
+; RV32-NEXT: vmv.s.x v0, a2
+; RV32-NEXT: vslideup.vi v12, v24, 10, v0.t
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 66
+; RV32-NEXT: li a3, 72
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs4r.v v12, (a2) # vscale x 32-byte Folded Spill
; RV32-NEXT: vle16.v v8, (a1)
-; RV32-NEXT: vslideup.vi v28, v16, 8, v0.t
-; RV32-NEXT: lui a1, %hi(.LCPI27_3)
-; RV32-NEXT: addi a1, a1, %lo(.LCPI27_3)
+; RV32-NEXT: vslideup.vi v4, v24, 8, v0.t
+; RV32-NEXT: lui a1, %hi(.LCPI27_1)
+; RV32-NEXT: addi a1, a1, %lo(.LCPI27_1)
; RV32-NEXT: vle16.v v10, (a1)
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vs2r.v v10, (a1) # vscale x 16-byte Folded Spill
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 1
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32-NEXT: vrgatherei16.vv v16, v0, v8
+; RV32-NEXT: vrgatherei16.vv v24, v16, v8
+; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: lui a1, %hi(.LCPI27_3)
+; RV32-NEXT: addi a1, a1, %lo(.LCPI27_3)
+; RV32-NEXT: vle16.v v2, (a1)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 20
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vrgatherei16.vv v16, v24, v10
; RV32-NEXT: lui a1, %hi(.LCPI27_2)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_2)
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vle16.v v20, (a1)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 22
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vl2r.v v22, (a1) # vscale x 16-byte Folded Reload
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vrgatherei16.vv v8, v0, v22
+; RV32-NEXT: vrgatherei16.vv v8, v24, v2
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 14
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 66
+; RV32-NEXT: li a2, 72
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
+; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetivli zero, 12, e32, m4, tu, ma
-; RV32-NEXT: vmv.v.v v12, v0
+; RV32-NEXT: vmv.v.v v12, v24
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 66
+; RV32-NEXT: li a2, 72
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
-; RV32-NEXT: vmv.v.v v28, v16
+; RV32-NEXT: vmv.v.v v4, v16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 22
+; RV32-NEXT: li a2, 48
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs4r.v v28, (a1) # vscale x 32-byte Folded Spill
+; RV32-NEXT: vs4r.v v4, (a1) # vscale x 32-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vrgatherei16.vv v16, v24, v20
+; RV32-NEXT: vrgatherei16.vv v16, v12, v20
; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
; RV32-NEXT: vmv.v.v v16, v8
; RV32-NEXT: lui a1, %hi(.LCPI27_4)
@@ -764,36 +725,36 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV32-NEXT: vle16.v v20, (a2)
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT: vle16.v v7, (a1)
+; RV32-NEXT: vle16.v v26, (a1)
; RV32-NEXT: lui a1, %hi(.LCPI27_7)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_7)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vle16.v v22, (a1)
+; RV32-NEXT: vle16.v v24, (a1)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 42
+; RV32-NEXT: li a2, 40
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vrgatherei16.vv v8, v24, v20
+; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vrgatherei16.vv v8, v0, v20
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 10
+; RV32-NEXT: li a2, 12
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vrgatherei16.vv v0, v12, v7
+; RV32-NEXT: vrgatherei16.vv v20, v12, v26
; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
-; RV32-NEXT: vmv.v.v v0, v8
+; RV32-NEXT: vmv.v.v v20, v8
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 50
+; RV32-NEXT: li a2, 56
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vrgatherei16.vv v8, v24, v22
+; RV32-NEXT: vrgatherei16.vv v8, v0, v24
; RV32-NEXT: lui a1, %hi(.LCPI27_6)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_6)
; RV32-NEXT: lui a2, %hi(.LCPI27_8)
@@ -803,62 +764,60 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: lui a1, %hi(.LCPI27_9)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_9)
; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; RV32-NEXT: vle16.v v4, (a1)
+; RV32-NEXT: vle16.v v28, (a1)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vle16.v v7, (a2)
+; RV32-NEXT: vle16.v v30, (a2)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 34
+; RV32-NEXT: li a2, 28
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl4r.v v24, (a1) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vrgatherei16.vv v20, v24, v12
+; RV32-NEXT: vl4r.v v4, (a1) # vscale x 32-byte Folded Reload
+; RV32-NEXT: vrgatherei16.vv v24, v4, v12
; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
-; RV32-NEXT: vmv.v.v v20, v8
+; RV32-NEXT: vmv.v.v v24, v8
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 58
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a1, a1, 6
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vrgatherei16.vv v8, v24, v4
+; RV32-NEXT: vrgatherei16.vv v8, v0, v28
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 30
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl4r.v v24, (a1) # vscale x 32-byte Folded Reload
+; RV32-NEXT: vl4r.v v4, (a1) # vscale x 32-byte Folded Reload
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vrgatherei16.vv v12, v24, v7
+; RV32-NEXT: vrgatherei16.vv v12, v4, v30
; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
; RV32-NEXT: vmv.v.v v12, v8
; RV32-NEXT: addi a1, a0, 320
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vse32.v v12, (a1)
; RV32-NEXT: addi a1, a0, 256
-; RV32-NEXT: vse32.v v20, (a1)
+; RV32-NEXT: vse32.v v24, (a1)
; RV32-NEXT: addi a1, a0, 192
-; RV32-NEXT: vse32.v v0, (a1)
+; RV32-NEXT: vse32.v v20, (a1)
; RV32-NEXT: addi a1, a0, 128
; RV32-NEXT: vse32.v v16, (a1)
; RV32-NEXT: addi a1, a0, 64
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 22
+; RV32-NEXT: li a3, 48
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 66
+; RV32-NEXT: li a2, 72
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 70
+; RV32-NEXT: li a1, 76
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -871,135 +830,116 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 78
+; RV64-NEXT: li a3, 68
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: sub sp, sp, a2
-; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xce, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 78 * vlenb
+; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc4, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 68 * vlenb
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vle64.v v24, (a1)
-; RV64-NEXT: addi a3, a1, 128
-; RV64-NEXT: lui a2, 1
-; RV64-NEXT: vle64.v v16, (a3)
-; RV64-NEXT: lui a3, %hi(.LCPI27_0)
-; RV64-NEXT: addi a3, a3, %lo(.LCPI27_0)
-; RV64-NEXT: vle16.v v6, (a3)
-; RV64-NEXT: li a3, 1040
-; RV64-NEXT: vmv.s.x v5, a3
-; RV64-NEXT: addi a3, a2, 65
-; RV64-NEXT: vmv.s.x v0, a3
-; RV64-NEXT: lui a3, 2
-; RV64-NEXT: addi a3, a3, 130
-; RV64-NEXT: vmv.s.x v3, a3
-; RV64-NEXT: lui a3, 4
-; RV64-NEXT: addi a3, a3, 260
-; RV64-NEXT: vmv.s.x v4, a3
-; RV64-NEXT: lui a3, 8
-; RV64-NEXT: addi a3, a3, 520
-; RV64-NEXT: addi a2, a2, -2016
-; RV64-NEXT: vmv.s.x v1, a3
-; RV64-NEXT: vmerge.vvm v8, v16, v24, v0
-; RV64-NEXT: csrr a3, vlenb
-; RV64-NEXT: li a4, 22
-; RV64-NEXT: mul a3, a3, a4
-; RV64-NEXT: add a3, sp, a3
-; RV64-NEXT: addi a3, a3, 16
-; RV64-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv.s.x v2, a2
-; RV64-NEXT: vmv1r.v v0, v3
-; RV64-NEXT: vmerge.vvm v8, v16, v24, v0
+; RV64-NEXT: vle64.v v8, (a1)
+; RV64-NEXT: addi a4, a1, 128
+; RV64-NEXT: lui a3, 1
+; RV64-NEXT: lui a2, %hi(.LCPI27_0)
+; RV64-NEXT: addi a2, a2, %lo(.LCPI27_0)
+; RV64-NEXT: lui a5, 2
+; RV64-NEXT: lui a6, 4
+; RV64-NEXT: vle64.v v16, (a4)
+; RV64-NEXT: addi a4, a3, 65
+; RV64-NEXT: vmv.s.x v0, a4
+; RV64-NEXT: lui a4, 8
+; RV64-NEXT: addi a5, a5, 130
+; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV64-NEXT: csrr a7, vlenb
+; RV64-NEXT: li t0, 60
+; RV64-NEXT: mul a7, a7, t0
+; RV64-NEXT: add a7, sp, a7
+; RV64-NEXT: addi a7, a7, 16
+; RV64-NEXT: vs8r.v v24, (a7) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv.s.x v0, a5
+; RV64-NEXT: li a5, 1040
+; RV64-NEXT: addi a6, a6, 260
+; RV64-NEXT: addi a4, a4, 520
+; RV64-NEXT: addi a3, a3, -2016
+; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV64-NEXT: csrr a7, vlenb
+; RV64-NEXT: li t0, 12
+; RV64-NEXT: mul a7, a7, t0
+; RV64-NEXT: add a7, sp, a7
+; RV64-NEXT: addi a7, a7, 16
+; RV64-NEXT: vs8r.v v24, (a7) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv.s.x v0, a6
+; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV64-NEXT: csrr a6, vlenb
+; RV64-NEXT: slli a6, a6, 2
+; RV64-NEXT: add a6, sp, a6
+; RV64-NEXT: addi a6, a6, 16
+; RV64-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv.s.x v0, a4
+; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV64-NEXT: csrr a4, vlenb
+; RV64-NEXT: li a6, 36
+; RV64-NEXT: mul a4, a4, a6
+; RV64-NEXT: add a4, sp, a4
+; RV64-NEXT: addi a4, a4, 16
+; RV64-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv.s.x v0, a5
+; RV64-NEXT: vle16.v v6, (a2)
+; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 70
-; RV64-NEXT: mul a2, a2, a3
+; RV64-NEXT: li a4, 44
+; RV64-NEXT: mul a2, a2, a4
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v4
-; RV64-NEXT: vmerge.vvm v8, v16, v24, v0
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 62
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v1
-; RV64-NEXT: vmerge.vvm v8, v16, v24, v0
+; RV64-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv.s.x v0, a3
+; RV64-NEXT: vmerge.vvm v8, v16, v8, v0
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 38
+; RV64-NEXT: li a3, 52
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv.v.v v8, v16
-; RV64-NEXT: vmv1r.v v0, v5
-; RV64-NEXT: vmerge.vvm v16, v16, v24, v0
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 46
+; RV64-NEXT: li a3, 60
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v2
-; RV64-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vrgatherei16.vv v16, v8, v6
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 54
+; RV64-NEXT: li a3, 28
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 22
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vrgatherei16.vv v8, v16, v6
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 30
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; RV64-NEXT: lui a2, %hi(.LCPI27_1)
; RV64-NEXT: addi a2, a2, %lo(.LCPI27_1)
; RV64-NEXT: lui a3, %hi(.LCPI27_2)
; RV64-NEXT: addi a3, a3, %lo(.LCPI27_2)
; RV64-NEXT: vle16.v v8, (a2)
; RV64-NEXT: vle16.v v10, (a3)
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 18
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs2r.v v10, (a2) # vscale x 16-byte Folded Spill
; RV64-NEXT: addi a1, a1, 256
; RV64-NEXT: vle64.v v16, (a1)
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 70
+; RV64-NEXT: li a2, 12
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vrgatherei16.vv v0, v24, v8
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs8r.v v0, (a1) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vrgatherei16.vv v24, v0, v8
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 62
+; RV64-NEXT: li a2, 20
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 18
-; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: slli a1, a1, 2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl2r.v v6, (a1) # vscale x 16-byte Folded Reload
-; RV64-NEXT: vrgatherei16.vv v24, v8, v6
+; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vrgatherei16.vv v24, v0, v10
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 22
+; RV64-NEXT: li a2, 12
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
@@ -1009,250 +949,198 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: vmv4r.v v8, v16
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vslideup.vi v8, v16, 5, v0.t
-; RV64-NEXT: vmv.v.v v24, v8
-; RV64-NEXT: vslidedown.vi v8, v16, 1
-; RV64-NEXT: vslideup.vi v8, v16, 4, v0.t
-; RV64-NEXT: vmv.v.v v28, v8
+; RV64-NEXT: vslidedown.vi v4, v16, 1
+; RV64-NEXT: vslideup.vi v4, v16, 4, v0.t
; RV64-NEXT: li a1, 128
-; RV64-NEXT: vmv.s.x v8, a1
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 70
-; RV64-NEXT: mul a1, a1, a2
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
-; RV64-NEXT: vslideup.vi v4, v16, 2
+; RV64-NEXT: vmv.s.x v0, a1
+; RV64-NEXT: vslideup.vi v12, v16, 2
; RV64-NEXT: vsetivli zero, 8, e64, m8, ta, ma
-; RV64-NEXT: vslidedown.vi v8, v16, 8
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 70
-; RV64-NEXT: mul a1, a1, a2
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vslidedown.vi v24, v16, 8
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vslideup.vi v4, v8, 5, v0.t
-; RV64-NEXT: vslideup.vi v12, v16, 1
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 70
-; RV64-NEXT: mul a1, a1, a2
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; RV64-NEXT: vslideup.vi v12, v8, 4, v0.t
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 70
-; RV64-NEXT: mul a1, a1, a2
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; RV64-NEXT: vrgather.vi v24, v8, 4, v0.t
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 62
-; RV64-NEXT: mul a1, a1, a2
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v24, (a1) # vscale x 32-byte Folded Spill
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 70
-; RV64-NEXT: mul a1, a1, a2
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; RV64-NEXT: vrgather.vi v28, v8, 5, v0.t
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 10
-; RV64-NEXT: mul a1, a1, a2
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v28, (a1) # vscale x 32-byte Folded Spill
-; RV64-NEXT: vslideup.vi v24, v8, 6
+; RV64-NEXT: vslideup.vi v12, v24, 5, v0.t
+; RV64-NEXT: vslideup.vi v20, v16, 1
+; RV64-NEXT: vslideup.vi v20, v24, 4, v0.t
+; RV64-NEXT: vmv.v.v v28, v20
+; RV64-NEXT: vrgather.vi v8, v24, 4, v0.t
+; RV64-NEXT: vrgather.vi v4, v24, 5, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 70
+; RV64-NEXT: li a2, 60
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; RV64-NEXT: vslideup.vi v24, v8, 1, v0.t
+; RV64-NEXT: vs4r.v v4, (a1) # vscale x 32-byte Folded Spill
+; RV64-NEXT: vslideup.vi v20, v24, 6
+; RV64-NEXT: vslideup.vi v20, v24, 1, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 18
-; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: slli a1, a1, 2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v24, (a1) # vscale x 32-byte Folded Spill
+; RV64-NEXT: vs4r.v v20, (a1) # vscale x 32-byte Folded Spill
; RV64-NEXT: li a1, 64
; RV64-NEXT: vmv.s.x v0, a1
-; RV64-NEXT: vmv4r.v v24, v8
-; RV64-NEXT: vslideup.vi v24, v8, 5, v0.t
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 14
-; RV64-NEXT: mul a1, a1, a2
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v24, (a1) # vscale x 32-byte Folded Spill
+; RV64-NEXT: vmv4r.v v20, v24
+; RV64-NEXT: vslideup.vi v20, v24, 5, v0.t
; RV64-NEXT: lui a1, %hi(.LCPI27_3)
; RV64-NEXT: addi a1, a1, %lo(.LCPI27_3)
; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; RV64-NEXT: vle16.v v8, (a1)
-; RV64-NEXT: addi a1, sp, 16
-; RV64-NEXT: vs2r.v v8, (a1) # vscale x 16-byte Folded Spill
+; RV64-NEXT: vle16.v v24, (a1)
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 30
+; RV64-NEXT: li a2, 28
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
-; RV64-NEXT: vmv.v.v v4, v24
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 70
-; RV64-NEXT: mul a1, a1, a2
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v4, (a1) # vscale x 32-byte Folded Spill
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmv.v.v v12, v24
+; RV64-NEXT: vmv.v.v v12, v0
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 30
+; RV64-NEXT: li a2, 28
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 22
+; RV64-NEXT: li a2, 20
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmv.v.v v28, v0
+; RV64-NEXT: addi a1, sp, 16
+; RV64-NEXT: vs4r.v v28, (a1) # vscale x 32-byte Folded Spill
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 62
+; RV64-NEXT: li a2, 12
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
+; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
-; RV64-NEXT: vmv.v.v v12, v8
+; RV64-NEXT: vmv.v.v v8, v0
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 62
+; RV64-NEXT: li a2, 20
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
+; RV64-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 38
+; RV64-NEXT: li a2, 36
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: addi a1, sp, 16
-; RV64-NEXT: vl2r.v v20, (a1) # vscale x 16-byte Folded Reload
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vrgatherei16.vv v0, v8, v20
+; RV64-NEXT: vrgatherei16.vv v0, v8, v24
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 10
+; RV64-NEXT: li a2, 60
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v28, (a1) # vscale x 32-byte Folded Reload
+; RV64-NEXT: vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
-; RV64-NEXT: vmv.v.v v28, v0
+; RV64-NEXT: vmv.v.v v8, v0
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 60
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; RV64-NEXT: li a1, 192
; RV64-NEXT: lui a2, %hi(.LCPI27_4)
; RV64-NEXT: addi a2, a2, %lo(.LCPI27_4)
; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV64-NEXT: vle16.v v8, (a2)
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 38
+; RV64-NEXT: li a3, 12
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs2r.v v8, (a2) # vscale x 16-byte Folded Spill
; RV64-NEXT: vmv.s.x v0, a1
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 36
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vrgather.vi v8, v16, 2
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 18
-; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: slli a1, a1, 2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v20, v8, v12, v0
-; RV64-NEXT: vmv1r.v v26, v0
+; RV64-NEXT: vmerge.vvm v24, v8, v12, v0
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 46
+; RV64-NEXT: li a2, 44
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 38
+; RV64-NEXT: li a2, 12
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl2r.v v24, (a1) # vscale x 16-byte Folded Reload
+; RV64-NEXT: vl2r.v v28, (a1) # vscale x 16-byte Folded Reload
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vrgatherei16.vv v8, v0, v24
+; RV64-NEXT: vrgatherei16.vv v8, v0, v28
; RV64-NEXT: lui a1, %hi(.LCPI27_5)
; RV64-NEXT: addi a1, a1, %lo(.LCPI27_5)
-; RV64-NEXT: vle16.v v24, (a1)
+; RV64-NEXT: vle16.v v28, (a1)
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
-; RV64-NEXT: vmv.v.v v20, v8
+; RV64-NEXT: vmv.v.v v24, v8
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vrgather.vi v8, v16, 3
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 14
+; RV64-NEXT: li a2, 36
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vmv1r.v v0, v26
-; RV64-NEXT: vmerge.vvm v16, v8, v12, v0
+; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vmerge.vvm v16, v8, v20, v0
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 54
+; RV64-NEXT: li a2, 52
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vrgatherei16.vv v8, v0, v24
+; RV64-NEXT: vrgatherei16.vv v8, v0, v28
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
; RV64-NEXT: vmv.v.v v16, v8
; RV64-NEXT: addi a1, a0, 320
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vse64.v v16, (a1)
; RV64-NEXT: addi a1, a0, 256
-; RV64-NEXT: vse64.v v20, (a1)
+; RV64-NEXT: vse64.v v24, (a1)
; RV64-NEXT: addi a1, a0, 192
-; RV64-NEXT: vse64.v v28, (a1)
-; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 62
+; RV64-NEXT: li a3, 60
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
; RV64-NEXT: vse64.v v8, (a1)
-; RV64-NEXT: addi a1, a0, 64
+; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 30
+; RV64-NEXT: li a3, 20
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
; RV64-NEXT: vse64.v v8, (a1)
+; RV64-NEXT: addi a1, a0, 64
+; RV64-NEXT: addi a2, sp, 16
+; RV64-NEXT: vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
+; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 70
+; RV64-NEXT: li a2, 28
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 78
+; RV64-NEXT: li a1, 68
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
index 58826b4f67bf1..6887f11fe38c7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
@@ -112,9 +112,9 @@ define float @vpreduce_fadd_v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32
; CHECK-LABEL: vpreduce_fadd_v64f32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 32
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v25, v0, 4
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB8_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 32
@@ -140,9 +140,9 @@ define float @vpreduce_ord_fadd_v64f32(float %s, <64 x float> %v, <64 x i1> %m,
; CHECK-LABEL: vpreduce_ord_fadd_v64f32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 32
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v25, v0, 4
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB9_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
index 52be38834661d..0401fe04556a9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
@@ -1891,58 +1891,53 @@ define float @vreduce_fminimum_v128f32(ptr %x) {
; CHECK-NEXT: addi a1, a0, 384
; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: addi a1, a0, 256
-; CHECK-NEXT: vle32.v v24, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v24, v16, v16
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v7, v8, v8
; CHECK-NEXT: vle32.v v24, (a1)
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v24, v24
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmerge.vvm v24, v24, v8, v0
+; CHECK-NEXT: vmerge.vvm v24, v8, v24, v0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
@@ -2307,26 +2302,22 @@ define double @vreduce_fminimum_v64f64(ptr %x) {
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmfeq.vv v24, v16, v16
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
-; RV32-NEXT: vmfeq.vv v7, v8, v8
+; RV32-NEXT: vmfeq.vv v0, v16, v16
; RV32-NEXT: vle64.v v24, (a1)
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vmerge.vvm v16, v16, v8, v0
+; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmfeq.vv v0, v8, v8
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
@@ -2337,21 +2328,20 @@ define double @vreduce_fminimum_v64f64(ptr %x) {
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmfeq.vv v0, v8, v8
-; RV32-NEXT: vmfeq.vv v7, v24, v24
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmfeq.vv v0, v16, v16
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmerge.vvm v16, v16, v24, v0
+; RV32-NEXT: vmfeq.vv v0, v24, v24
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vmerge.vvm v24, v24, v8, v0
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -2417,26 +2407,22 @@ define double @vreduce_fminimum_v64f64(ptr %x) {
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmfeq.vv v24, v16, v16
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
-; RV64-NEXT: vmfeq.vv v7, v8, v8
+; RV64-NEXT: vmfeq.vv v0, v16, v16
; RV64-NEXT: vle64.v v24, (a1)
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vmerge.vvm v16, v16, v8, v0
+; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmfeq.vv v0, v8, v8
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vmerge.vvm v8, v8, v16, v0
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
@@ -2447,21 +2433,20 @@ define double @vreduce_fminimum_v64f64(ptr %x) {
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmfeq.vv v0, v8, v8
-; RV64-NEXT: vmfeq.vv v7, v24, v24
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmfeq.vv v0, v16, v16
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmerge.vvm v16, v16, v24, v0
+; RV64-NEXT: vmfeq.vv v0, v24, v24
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vmerge.vvm v24, v24, v8, v0
; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -2806,58 +2791,53 @@ define float @vreduce_fmaximum_v128f32(ptr %x) {
; CHECK-NEXT: addi a1, a0, 384
; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: addi a1, a0, 256
-; CHECK-NEXT: vle32.v v24, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v24, v16, v16
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v7, v8, v8
; CHECK-NEXT: vle32.v v24, (a1)
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v24, v24
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmerge.vvm v24, v24, v8, v0
+; CHECK-NEXT: vmerge.vvm v24, v8, v24, v0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
@@ -3222,26 +3202,22 @@ define double @vreduce_fmaximum_v64f64(ptr %x) {
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmfeq.vv v24, v16, v16
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
-; RV32-NEXT: vmfeq.vv v7, v8, v8
+; RV32-NEXT: vmfeq.vv v0, v16, v16
; RV32-NEXT: vle64.v v24, (a1)
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vmerge.vvm v16, v16, v8, v0
+; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmfeq.vv v0, v8, v8
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
@@ -3252,21 +3228,20 @@ define double @vreduce_fmaximum_v64f64(ptr %x) {
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmfeq.vv v0, v8, v8
-; RV32-NEXT: vmfeq.vv v7, v24, v24
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmfeq.vv v0, v16, v16
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmerge.vvm v16, v16, v24, v0
+; RV32-NEXT: vmfeq.vv v0, v24, v24
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vmerge.vvm v24, v24, v8, v0
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -3332,26 +3307,22 @@ define double @vreduce_fmaximum_v64f64(ptr %x) {
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmfeq.vv v24, v16, v16
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
-; RV64-NEXT: vmfeq.vv v7, v8, v8
+; RV64-NEXT: vmfeq.vv v0, v16, v16
; RV64-NEXT: vle64.v v24, (a1)
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vmerge.vvm v16, v16, v8, v0
+; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmfeq.vv v0, v8, v8
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vmerge.vvm v8, v8, v16, v0
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
@@ -3362,21 +3333,20 @@ define double @vreduce_fmaximum_v64f64(ptr %x) {
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmfeq.vv v0, v8, v8
-; RV64-NEXT: vmfeq.vv v7, v24, v24
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmfeq.vv v0, v16, v16
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmerge.vvm v16, v16, v24, v0
+; RV64-NEXT: vmfeq.vv v0, v24, v24
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vmerge.vvm v24, v24, v8, v0
; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
index 4b5d581e7b668..564c4fb40a70b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
@@ -645,18 +645,18 @@ define signext i32 @vpreduce_xor_v64i32(i32 signext %s, <64 x i32> %v, <64 x i1>
; CHECK-LABEL: vpreduce_xor_v64i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v25, v0, 4
-; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bltu a1, a3, .LBB49_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: .LBB49_2:
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vmv.s.x v24, a0
-; CHECK-NEXT: addi a0, a1, -32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vredxor.vs v24, v8, v24, v0.t
+; CHECK-NEXT: addi a0, a1, -32
; CHECK-NEXT: sltu a1, a1, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
index 447367f6a9f29..3e88d19fb95e7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
@@ -201,6 +201,9 @@ define zeroext i1 @vpreduce_and_v16i1(i1 zeroext %s, <16 x i1> %v, <16 x i1> %m,
define zeroext i1 @vpreduce_and_v256i1(i1 zeroext %s, <256 x i1> %v, <256 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_and_v256i1:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v11, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: li a3, 128
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bltu a1, a3, .LBB14_2
@@ -208,19 +211,18 @@ define zeroext i1 @vpreduce_and_v256i1(i1 zeroext %s, <256 x i1> %v, <256 x i1>
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: .LBB14_2:
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; CHECK-NEXT: vmnot.m v11, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vcpop.m a2, v11, v0.t
-; CHECK-NEXT: seqz a2, a2
-; CHECK-NEXT: and a0, a2, a0
-; CHECK-NEXT: addi a2, a1, -128
-; CHECK-NEXT: sltu a1, a1, a2
+; CHECK-NEXT: vmnot.m v9, v11
+; CHECK-NEXT: vcpop.m a2, v9, v0.t
+; CHECK-NEXT: addi a3, a1, -128
+; CHECK-NEXT: sltu a1, a1, a3
; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a1, a1, a2
+; CHECK-NEXT: and a1, a1, a3
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmnot.m v8, v8
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vcpop.m a1, v8, v0.t
+; CHECK-NEXT: seqz a2, a2
+; CHECK-NEXT: and a0, a2, a0
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
index dcb2fde553d58..9af900ce005e5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
@@ -31,12 +31,12 @@ define <2 x half> @vp_round_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl)
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -115,12 +115,12 @@ define <4 x half> @vp_round_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl)
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
index f398cb306559b..656a62a693da8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
@@ -31,12 +31,12 @@ define <2 x half> @vp_roundeven_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -115,12 +115,12 @@ define <4 x half> @vp_roundeven_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
index bfbf6c8371a4e..0a06067a65782 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
@@ -31,12 +31,12 @@ define <2 x half> @vp_roundtozero_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -115,12 +115,12 @@ define <4 x half> @vp_roundtozero_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
index f9b97da6d02aa..f76c7fcb628b5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
@@ -596,15 +596,15 @@ define <256 x i1> @icmp_eq_vv_v256i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1>
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: li a1, 128
; CHECK-NEXT: addi a4, a0, 128
+; CHECK-NEXT: addi a5, a3, -128
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v0, (a2)
-; CHECK-NEXT: addi a2, a3, -128
; CHECK-NEXT: vle8.v v24, (a4)
-; CHECK-NEXT: sltu a4, a3, a2
+; CHECK-NEXT: sltu a4, a3, a5
+; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a2, a4, a2
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-NEXT: and a4, a4, a5
+; CHECK-NEXT: vsetvli zero, a4, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vv v7, v16, v24, v0.t
; CHECK-NEXT: bltu a3, a1, .LBB51_2
; CHECK-NEXT: # %bb.1:
@@ -634,12 +634,12 @@ define <256 x i1> @icmp_eq_vx_v256i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 z
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
+; CHECK-NEXT: addi a4, a2, -128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: addi a1, a2, -128
-; CHECK-NEXT: sltu a4, a2, a1
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a1, a4, a1
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB52_2
@@ -664,12 +664,12 @@ define <256 x i1> @icmp_eq_vx_swap_v256i8(<256 x i8> %va, i8 %b, <256 x i1> %m,
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
+; CHECK-NEXT: addi a4, a2, -128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: addi a1, a2, -128
-; CHECK-NEXT: sltu a4, a2, a1
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a1, a4, a1
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB53_2
@@ -1289,9 +1289,9 @@ define <64 x i1> @icmp_eq_vx_v64i32(<64 x i32> %va, i32 %b, <64 x i1> %m, i32 ze
; CHECK-LABEL: icmp_eq_vx_v64i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v25, v0, 4
-; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bltu a1, a3, .LBB100_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 32
@@ -1319,9 +1319,9 @@ define <64 x i1> @icmp_eq_vx_swap_v64i32(<64 x i32> %va, i32 %b, <64 x i1> %m, i
; CHECK-LABEL: icmp_eq_vx_swap_v64i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v25, v0, 4
-; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bltu a1, a3, .LBB101_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
index b03415e1a8550..6dc54bce9aaa0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
@@ -138,9 +138,9 @@ define <32 x i64> @vsext_v32i64_v32i32(<32 x i32> %va, <32 x i1> %m, i32 zeroext
; CHECK-LABEL: vsext_v32i64_v32i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB12_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
index 03bde17b1230a..33583a4b5beca 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
@@ -145,12 +145,11 @@ define void @deinterleave6_0_i8(ptr %in, ptr %out) {
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.v.i v0, 2
-; CHECK-NEXT: vmv.v.i v10, 4
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 8
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 5, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv.v.i v0, 4
; CHECK-NEXT: vrgather.vi v8, v9, 4, v0.t
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -190,12 +189,11 @@ define void @deinterleave7_0_i8(ptr %in, ptr %out) {
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.v.i v0, 2
-; CHECK-NEXT: vmv.v.i v10, 4
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 8
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 6, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv.v.i v0, 4
; CHECK-NEXT: vrgather.vi v8, v9, 6, v0.t
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
index aa86624440754..cb0cc43389b6b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
@@ -1611,40 +1611,38 @@ define <16 x i64> @unzip2a_dual_v16i64_exact(<16 x i64> %a, <16 x i64> %b) vscal
; V: # %bb.0: # %entry
; V-NEXT: vsetivli zero, 4, e64, m1, ta, mu
; V-NEXT: vslideup.vi v16, v15, 2
-; V-NEXT: vmv.v.i v17, 8
-; V-NEXT: vmv.v.i v19, 2
-; V-NEXT: vmv.v.i v18, 12
-; V-NEXT: vmv.v.v v0, v17
+; V-NEXT: vmv.v.i v0, 8
+; V-NEXT: vslideup.vi v17, v11, 2
; V-NEXT: vslideup.vi v16, v15, 1, v0.t
-; V-NEXT: vmv.v.v v0, v19
+; V-NEXT: vmv.v.v v15, v0
+; V-NEXT: vmv.v.i v0, 2
; V-NEXT: vslidedown.vi v14, v14, 1, v0.t
+; V-NEXT: vmv.v.v v18, v0
+; V-NEXT: vmv.v.v v0, v15
+; V-NEXT: vslideup.vi v17, v11, 1, v0.t
+; V-NEXT: vmv.v.v v11, v15
; V-NEXT: vmv.v.v v0, v18
-; V-NEXT: vmerge.vvm v15, v14, v16, v0
-; V-NEXT: vslideup.vi v14, v13, 2
-; V-NEXT: vmv.v.v v0, v17
-; V-NEXT: vslideup.vi v14, v13, 1, v0.t
-; V-NEXT: vmv.v.v v0, v19
-; V-NEXT: vslidedown.vi v12, v12, 1, v0.t
-; V-NEXT: vmv.v.v v0, v18
-; V-NEXT: vmerge.vvm v14, v12, v14, v0
-; V-NEXT: vslideup.vi v12, v11, 2
-; V-NEXT: li a0, -256
-; V-NEXT: vmv.v.v v0, v17
-; V-NEXT: vslideup.vi v12, v11, 1, v0.t
-; V-NEXT: vmv.v.v v0, v19
; V-NEXT: vslidedown.vi v10, v10, 1, v0.t
-; V-NEXT: vmv.v.v v0, v18
-; V-NEXT: vmerge.vvm v13, v10, v12, v0
-; V-NEXT: vslideup.vi v10, v9, 2
-; V-NEXT: vmv.v.v v0, v17
-; V-NEXT: vslideup.vi v10, v9, 1, v0.t
+; V-NEXT: vmv.v.v v19, v18
+; V-NEXT: vslideup.vi v15, v13, 2
+; V-NEXT: vslideup.vi v18, v9, 2
+; V-NEXT: vmv.v.v v0, v11
+; V-NEXT: vslideup.vi v15, v13, 1, v0.t
+; V-NEXT: vslideup.vi v18, v9, 1, v0.t
+; V-NEXT: vmv.v.i v0, 12
+; V-NEXT: vmerge.vvm v11, v14, v16, v0
+; V-NEXT: vmerge.vvm v9, v10, v17, v0
+; V-NEXT: vmv.v.v v10, v0
; V-NEXT: vmv.v.v v0, v19
+; V-NEXT: vslidedown.vi v12, v12, 1, v0.t
; V-NEXT: vslidedown.vi v8, v8, 1, v0.t
-; V-NEXT: vmv.v.v v0, v18
-; V-NEXT: vmerge.vvm v12, v8, v10, v0
+; V-NEXT: vmv.v.v v0, v10
+; V-NEXT: vmerge.vvm v10, v12, v15, v0
+; V-NEXT: li a0, -256
+; V-NEXT: vmerge.vvm v8, v8, v18, v0
; V-NEXT: vmv.s.x v0, a0
; V-NEXT: vsetivli zero, 16, e64, m4, ta, ma
-; V-NEXT: vmerge.vvm v8, v12, v12, v0
+; V-NEXT: vmerge.vvm v8, v8, v8, v0
; V-NEXT: ret
;
; ZVE32F-LABEL: unzip2a_dual_v16i64_exact:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
index afa8f2fda2ed4..feec2470461de 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
@@ -363,9 +363,9 @@ define <32 x double> @vsitofp_v32f64_v32i64(<32 x i64> %va, <32 x i1> %m, i32 ze
; CHECK-LABEL: vsitofp_v32f64_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB25_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
index f44f90085eabd..95f110f0e1a2c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
@@ -493,17 +493,16 @@ define <32 x double> @strided_vpload_v32f64(ptr %ptr, i32 signext %stride, <32 x
; CHECK-NEXT: .LBB45_2:
; CHECK-NEXT: mul a4, a3, a1
; CHECK-NEXT: addi a5, a2, -16
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v8, v0, 2
-; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: add a4, a0, a4
; CHECK-NEXT: sltu a2, a2, a5
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a5
-; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vlse64.v v16, (a4), a1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t
; CHECK-NEXT: ret
@@ -539,8 +538,6 @@ define <32 x double> @strided_vpload_v32f64_allones_mask(ptr %ptr, i32 signext %
define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask, i32 zeroext %evl) {
; CHECK-RV32-LABEL: strided_load_v33f64:
; CHECK-RV32: # %bb.0:
-; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-RV32-NEXT: vmv1r.v v16, v0
; CHECK-RV32-NEXT: li a5, 32
; CHECK-RV32-NEXT: mv a3, a4
; CHECK-RV32-NEXT: bltu a4, a5, .LBB47_2
@@ -559,7 +556,8 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
; CHECK-RV32-NEXT: li a7, 16
; CHECK-RV32-NEXT: .LBB47_4:
; CHECK-RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v0, v16, 4
+; CHECK-RV32-NEXT: vmv1r.v v16, v0
+; CHECK-RV32-NEXT: vslidedown.vi v0, v0, 4
; CHECK-RV32-NEXT: vsetvli zero, a7, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v8, (a6), a2, v0.t
; CHECK-RV32-NEXT: addi a6, a3, -16
@@ -572,12 +570,11 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
; CHECK-RV32-NEXT: .LBB47_6:
; CHECK-RV32-NEXT: mul a5, a4, a2
; CHECK-RV32-NEXT: vmv1r.v v0, v16
-; CHECK-RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v9, v16, 2
; CHECK-RV32-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v16, (a1), a2, v0.t
+; CHECK-RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vi v0, v0, 2
; CHECK-RV32-NEXT: add a1, a1, a5
-; CHECK-RV32-NEXT: vmv1r.v v0, v9
; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v24, (a1), a2, v0.t
; CHECK-RV32-NEXT: addi a1, a0, 128
@@ -591,8 +588,6 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
;
; CHECK-RV64-LABEL: strided_load_v33f64:
; CHECK-RV64: # %bb.0:
-; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-RV64-NEXT: vmv1r.v v16, v0
; CHECK-RV64-NEXT: li a5, 32
; CHECK-RV64-NEXT: mv a4, a3
; CHECK-RV64-NEXT: bltu a3, a5, .LBB47_2
@@ -611,7 +606,8 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
; CHECK-RV64-NEXT: li a7, 16
; CHECK-RV64-NEXT: .LBB47_4:
; CHECK-RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v0, v16, 4
+; CHECK-RV64-NEXT: vmv1r.v v16, v0
+; CHECK-RV64-NEXT: vslidedown.vi v0, v0, 4
; CHECK-RV64-NEXT: vsetvli zero, a7, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v8, (a6), a2, v0.t
; CHECK-RV64-NEXT: addi a6, a4, -16
@@ -624,12 +620,11 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
; CHECK-RV64-NEXT: .LBB47_6:
; CHECK-RV64-NEXT: mul a5, a3, a2
; CHECK-RV64-NEXT: vmv1r.v v0, v16
-; CHECK-RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v9, v16, 2
; CHECK-RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v16, (a1), a2, v0.t
+; CHECK-RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vi v0, v0, 2
; CHECK-RV64-NEXT: add a1, a1, a5
-; CHECK-RV64-NEXT: vmv1r.v v0, v9
; CHECK-RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v24, (a1), a2, v0.t
; CHECK-RV64-NEXT: addi a1, a0, 128
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
index 17a76735dfdb1..32ace86a0d1fc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
@@ -48,8 +48,8 @@ define <128 x i7> @vtrunc_v128i7_v128i16(<128 x i16> %a, <128 x i1> %m, i32 zero
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: li a1, 64
-; CHECK-NEXT: vslidedown.vi v12, v0, 8
; CHECK-NEXT: mv a2, a0
+; CHECK-NEXT: vslidedown.vi v12, v0, 8
; CHECK-NEXT: bltu a0, a1, .LBB4_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 64
@@ -207,215 +207,201 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: sw s0, 28(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset s0, -4
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 82
+; RV32-NEXT: li a3, 73
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: sub sp, sp, a2
-; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0xd2, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 82 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0xc9, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 73 * vlenb
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 41
-; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 49
+; RV32-NEXT: li a3, 40
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: addi a3, a7, -64
+; RV32-NEXT: li a2, 16
+; RV32-NEXT: sltu a4, a7, a3
+; RV32-NEXT: addi a4, a4, -1
+; RV32-NEXT: and a4, a4, a3
+; RV32-NEXT: addi a3, a4, -32
+; RV32-NEXT: sltu a5, a4, a3
+; RV32-NEXT: addi a5, a5, -1
+; RV32-NEXT: and a3, a5, a3
+; RV32-NEXT: addi a6, a3, -16
+; RV32-NEXT: mv a5, a3
; RV32-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; RV32-NEXT: vslidedown.vi v8, v0, 8
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 57
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
+; RV32-NEXT: csrr t0, vlenb
+; RV32-NEXT: li t1, 48
+; RV32-NEXT: mul t0, t0, t1
+; RV32-NEXT: add t0, sp, t0
+; RV32-NEXT: addi t0, t0, 16
+; RV32-NEXT: vs1r.v v0, (t0) # vscale x 8-byte Folded Spill
; RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; RV32-NEXT: vslidedown.vi v9, v0, 4
-; RV32-NEXT: addi a2, a7, -64
-; RV32-NEXT: vmv1r.v v28, v8
-; RV32-NEXT: vslidedown.vi v8, v8, 4
-; RV32-NEXT: sltu a3, a7, a2
-; RV32-NEXT: addi a3, a3, -1
-; RV32-NEXT: and a4, a3, a2
-; RV32-NEXT: addi a2, a4, -32
-; RV32-NEXT: sltu a3, a4, a2
-; RV32-NEXT: addi a3, a3, -1
-; RV32-NEXT: and a3, a3, a2
-; RV32-NEXT: li a2, 16
-; RV32-NEXT: addi t0, a3, -16
-; RV32-NEXT: mv a5, a3
+; RV32-NEXT: vmv1r.v v13, v8
+; RV32-NEXT: vslidedown.vi v10, v8, 4
; RV32-NEXT: bltu a3, a2, .LBB16_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a5, 16
; RV32-NEXT: .LBB16_2:
; RV32-NEXT: li t2, 64
-; RV32-NEXT: sltu t1, a3, t0
-; RV32-NEXT: mv a6, a7
+; RV32-NEXT: sltu t1, a3, a6
+; RV32-NEXT: mv t0, a7
; RV32-NEXT: bltu a7, t2, .LBB16_4
; RV32-NEXT: # %bb.3:
-; RV32-NEXT: li a6, 64
+; RV32-NEXT: li t0, 64
; RV32-NEXT: .LBB16_4:
-; RV32-NEXT: addi t2, a1, 128
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li t3, 24
-; RV32-NEXT: mul a3, a3, t3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs1r.v v9, (a3) # vscale x 8-byte Folded Spill
+; RV32-NEXT: addi t3, a1, 128
+; RV32-NEXT: vmv1r.v v12, v9
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v29, v9, 2
-; RV32-NEXT: addi t6, a1, 512
-; RV32-NEXT: addi t4, a1, 640
-; RV32-NEXT: vmv1r.v v30, v8
-; RV32-NEXT: vslidedown.vi v0, v8, 2
+; RV32-NEXT: vslidedown.vi v14, v9, 2
+; RV32-NEXT: addi s0, a1, 512
+; RV32-NEXT: addi t6, a1, 640
; RV32-NEXT: addi t1, t1, -1
-; RV32-NEXT: addi t3, a1, 384
-; RV32-NEXT: vslidedown.vi v31, v28, 2
+; RV32-NEXT: addi t2, a1, 384
; RV32-NEXT: li a3, 32
-; RV32-NEXT: addi t5, a6, -32
-; RV32-NEXT: sltu a6, a6, t5
-; RV32-NEXT: addi a6, a6, -1
-; RV32-NEXT: and a6, a6, t5
-; RV32-NEXT: addi t5, a6, -16
-; RV32-NEXT: sltu s0, a6, t5
-; RV32-NEXT: addi s0, s0, -1
-; RV32-NEXT: bltu a6, a2, .LBB16_6
+; RV32-NEXT: addi t4, t0, -32
+; RV32-NEXT: sltu t0, t0, t4
+; RV32-NEXT: addi t0, t0, -1
+; RV32-NEXT: and t0, t0, t4
+; RV32-NEXT: addi t4, t0, -16
+; RV32-NEXT: sltu t5, t0, t4
+; RV32-NEXT: addi t5, t5, -1
+; RV32-NEXT: vslidedown.vi v0, v10, 2
+; RV32-NEXT: vslidedown.vi v15, v13, 2
+; RV32-NEXT: bltu t0, a2, .LBB16_6
; RV32-NEXT: # %bb.5:
-; RV32-NEXT: li a6, 16
+; RV32-NEXT: li t0, 16
; RV32-NEXT: .LBB16_6:
+; RV32-NEXT: vmv1r.v v7, v10
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vle64.v v8, (t6)
-; RV32-NEXT: csrr t6, vlenb
+; RV32-NEXT: vle64.v v16, (s0)
+; RV32-NEXT: csrr s0, vlenb
; RV32-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
-; RV32-NEXT: li a0, 66
-; RV32-NEXT: mul t6, t6, a0
+; RV32-NEXT: li a0, 57
+; RV32-NEXT: mul s0, s0, a0
; RV32-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
-; RV32-NEXT: add t6, sp, t6
-; RV32-NEXT: addi t6, t6, 16
-; RV32-NEXT: vs8r.v v8, (t6) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vle64.v v16, (t4)
-; RV32-NEXT: vle64.v v8, (t2)
-; RV32-NEXT: csrr t2, vlenb
-; RV32-NEXT: li t4, 25
-; RV32-NEXT: mul t2, t2, t4
-; RV32-NEXT: add t2, sp, t2
-; RV32-NEXT: addi t2, t2, 16
-; RV32-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vle64.v v8, (a1)
+; RV32-NEXT: add s0, sp, s0
+; RV32-NEXT: addi s0, s0, 16
+; RV32-NEXT: vs8r.v v16, (s0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vle64.v v24, (t6)
+; RV32-NEXT: vle64.v v16, (t3)
+; RV32-NEXT: csrr t3, vlenb
+; RV32-NEXT: slli t3, t3, 4
+; RV32-NEXT: add t3, sp, t3
+; RV32-NEXT: addi t3, t3, 16
+; RV32-NEXT: vs8r.v v16, (t3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vle64.v v16, (a1)
+; RV32-NEXT: csrr t3, vlenb
+; RV32-NEXT: slli t3, t3, 3
+; RV32-NEXT: add t3, sp, t3
+; RV32-NEXT: addi t3, t3, 16
+; RV32-NEXT: vs8r.v v16, (t3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vle64.v v16, (t2)
; RV32-NEXT: csrr t2, vlenb
-; RV32-NEXT: li t4, 58
-; RV32-NEXT: mul t2, t2, t4
-; RV32-NEXT: add t2, sp, t2
-; RV32-NEXT: addi t2, t2, 16
-; RV32-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vle64.v v8, (t3)
-; RV32-NEXT: csrr t2, vlenb
-; RV32-NEXT: slli t2, t2, 4
+; RV32-NEXT: li t3, 49
+; RV32-NEXT: mul t2, t2, t3
; RV32-NEXT: add t2, sp, t2
; RV32-NEXT: addi t2, t2, 16
-; RV32-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: and t2, t1, t0
-; RV32-NEXT: and t1, s0, t5
+; RV32-NEXT: vs8r.v v16, (t2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: and t2, t1, a6
+; RV32-NEXT: and t1, t5, t4
; RV32-NEXT: addi a1, a1, 256
-; RV32-NEXT: mv t0, a4
+; RV32-NEXT: mv a6, a4
; RV32-NEXT: bltu a4, a3, .LBB16_8
; RV32-NEXT: # %bb.7:
-; RV32-NEXT: li t0, 32
+; RV32-NEXT: li a6, 32
; RV32-NEXT: .LBB16_8:
; RV32-NEXT: vsetvli zero, t2, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
-; RV32-NEXT: addi t2, sp, 16
-; RV32-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v30
+; RV32-NEXT: vnsrl.wi v8, v24, 0, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: csrr t2, vlenb
-; RV32-NEXT: li t3, 66
+; RV32-NEXT: li t3, 57
; RV32-NEXT: mul t2, t2, t3
; RV32-NEXT: add t2, sp, t2
; RV32-NEXT: addi t2, t2, 16
; RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a5, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; RV32-NEXT: vnsrl.wi v24, v16, 0, v0.t
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li t2, 74
-; RV32-NEXT: mul a5, a5, t2
+; RV32-NEXT: slli t2, a5, 6
+; RV32-NEXT: add a5, t2, a5
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v29
+; RV32-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v14
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li t2, 25
-; RV32-NEXT: mul a5, a5, t2
+; RV32-NEXT: slli a5, a5, 4
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, t1, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; RV32-NEXT: vnsrl.wi v24, v16, 0, v0.t
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli t1, a5, 5
-; RV32-NEXT: add a5, t1, a5
+; RV32-NEXT: li t1, 24
+; RV32-NEXT: mul a5, a5, t1
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: addi a5, t0, -16
-; RV32-NEXT: sltu t0, t0, a5
-; RV32-NEXT: addi t0, t0, -1
-; RV32-NEXT: and a5, t0, a5
+; RV32-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: csrr a5, vlenb
+; RV32-NEXT: slli a5, a5, 3
+; RV32-NEXT: add a5, sp, a5
+; RV32-NEXT: addi a5, a5, 16
+; RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, t0, e32, m4, ta, ma
+; RV32-NEXT: vnsrl.wi v16, v24, 0, v0.t
+; RV32-NEXT: csrr a5, vlenb
+; RV32-NEXT: li t0, 57
+; RV32-NEXT: mul a5, a5, t0
+; RV32-NEXT: add a5, sp, a5
+; RV32-NEXT: addi a5, a5, 16
+; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; RV32-NEXT: addi a5, a6, -16
+; RV32-NEXT: sltu a6, a6, a5
+; RV32-NEXT: addi a6, a6, -1
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vle64.v v8, (a1)
+; RV32-NEXT: vle64.v v16, (a1)
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: and a1, a6, a5
+; RV32-NEXT: vmv1r.v v0, v15
+; RV32-NEXT: csrr a5, vlenb
+; RV32-NEXT: li a6, 49
+; RV32-NEXT: mul a5, a5, a6
+; RV32-NEXT: add a5, sp, a5
+; RV32-NEXT: addi a5, a5, 16
+; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV32-NEXT: vnsrl.wi v24, v16, 0, v0.t
+; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li t0, 57
-; RV32-NEXT: mul a1, a1, t0
+; RV32-NEXT: li a5, 48
+; RV32-NEXT: mul a1, a1, a5
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl1r.v v8, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vl1r.v v12, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v8, v8, 2
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li t0, 25
-; RV32-NEXT: mul a1, a1, t0
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li t0, 58
-; RV32-NEXT: mul a1, a1, t0
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li t0, 24
-; RV32-NEXT: mul a1, a1, t0
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a6, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a6, 66
-; RV32-NEXT: mul a1, a1, a6
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v31
+; RV32-NEXT: vslidedown.vi v12, v12, 2
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a5, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; RV32-NEXT: vs1r.v v12, (a1) # vscale x 8-byte Folded Spill
; RV32-NEXT: bltu a4, a2, .LBB16_10
; RV32-NEXT: # %bb.9:
; RV32-NEXT: li a4, 16
; RV32-NEXT: .LBB16_10:
-; RV32-NEXT: vmv1r.v v0, v28
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
@@ -424,7 +410,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: vsetvli zero, a4, e32, m4, ta, ma
; RV32-NEXT: vnsrl.wi v16, v24, 0, v0.t
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a4, 58
+; RV32-NEXT: li a4, 49
; RV32-NEXT: mul a1, a1, a4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
@@ -434,68 +420,65 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: # %bb.11:
; RV32-NEXT: li a1, 32
; RV32-NEXT: .LBB16_12:
-; RV32-NEXT: addi a4, sp, 16
-; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmv4r.v v24, v16
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a5, a4, 5
-; RV32-NEXT: add a4, a5, a4
+; RV32-NEXT: li a5, 24
+; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
+; RV32-NEXT: addi a4, sp, 16
+; RV32-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: li a5, 74
-; RV32-NEXT: mul a4, a4, a5
+; RV32-NEXT: slli a5, a4, 6
+; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; RV32-NEXT: vslideup.vi v16, v24, 16
+; RV32-NEXT: vslideup.vi v16, v8, 16
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: li a5, 74
-; RV32-NEXT: mul a4, a4, a5
+; RV32-NEXT: slli a5, a4, 6
+; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32-NEXT: addi a4, a1, -16
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 66
+; RV32-NEXT: li a6, 57
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vslideup.vi v16, v0, 16
+; RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vslideup.vi v8, v0, 16
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 66
+; RV32-NEXT: li a6, 57
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 58
+; RV32-NEXT: li a6, 49
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vslideup.vi v16, v8, 16
+; RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vslideup.vi v8, v24, 16
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 58
+; RV32-NEXT: li a6, 49
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
; RV32-NEXT: sltu a1, a1, a4
; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a4
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: li a5, 41
-; RV32-NEXT: mul a4, a4, a5
+; RV32-NEXT: slli a4, a4, 5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: li a5, 25
-; RV32-NEXT: mul a4, a4, a5
+; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
@@ -506,13 +489,13 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: li a7, 16
; RV32-NEXT: .LBB16_14:
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 57
+; RV32-NEXT: li a2, 48
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 49
+; RV32-NEXT: li a2, 40
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
@@ -524,7 +507,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: vse32.v v24, (a0)
; RV32-NEXT: addi a1, a0, 256
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 58
+; RV32-NEXT: li a3, 49
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
@@ -532,7 +515,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: addi a1, a0, 128
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 66
+; RV32-NEXT: li a3, 57
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
@@ -540,14 +523,14 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: addi a0, a0, 384
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 74
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a2, a1, 6
+; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 82
+; RV32-NEXT: li a1, 73
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 32
@@ -564,215 +547,201 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: sd s0, 40(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset s0, -8
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 82
+; RV64-NEXT: li a3, 73
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: sub sp, sp, a2
-; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0xd2, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 82 * vlenb
+; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0xc9, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 73 * vlenb
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 41
-; RV64-NEXT: mul a2, a2, a3
+; RV64-NEXT: slli a2, a2, 5
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 32
; RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 49
+; RV64-NEXT: li a3, 40
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 32
; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: addi a3, a7, -64
+; RV64-NEXT: li a2, 16
+; RV64-NEXT: sltu a4, a7, a3
+; RV64-NEXT: addi a4, a4, -1
+; RV64-NEXT: and a4, a4, a3
+; RV64-NEXT: addi a3, a4, -32
+; RV64-NEXT: sltu a5, a4, a3
+; RV64-NEXT: addi a5, a5, -1
+; RV64-NEXT: and a3, a5, a3
+; RV64-NEXT: addi a6, a3, -16
+; RV64-NEXT: mv a5, a3
; RV64-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v0, 8
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 57
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 32
-; RV64-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
+; RV64-NEXT: csrr t0, vlenb
+; RV64-NEXT: li t1, 48
+; RV64-NEXT: mul t0, t0, t1
+; RV64-NEXT: add t0, sp, t0
+; RV64-NEXT: addi t0, t0, 32
+; RV64-NEXT: vs1r.v v0, (t0) # vscale x 8-byte Folded Spill
; RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vi v9, v0, 4
-; RV64-NEXT: addi a2, a7, -64
-; RV64-NEXT: vmv1r.v v28, v8
-; RV64-NEXT: vslidedown.vi v8, v8, 4
-; RV64-NEXT: sltu a3, a7, a2
-; RV64-NEXT: addi a3, a3, -1
-; RV64-NEXT: and a4, a3, a2
-; RV64-NEXT: addi a2, a4, -32
-; RV64-NEXT: sltu a3, a4, a2
-; RV64-NEXT: addi a3, a3, -1
-; RV64-NEXT: and a3, a3, a2
-; RV64-NEXT: li a2, 16
-; RV64-NEXT: addi t0, a3, -16
-; RV64-NEXT: mv a5, a3
+; RV64-NEXT: vmv1r.v v13, v8
+; RV64-NEXT: vslidedown.vi v10, v8, 4
; RV64-NEXT: bltu a3, a2, .LBB16_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a5, 16
; RV64-NEXT: .LBB16_2:
; RV64-NEXT: li t2, 64
-; RV64-NEXT: sltu t1, a3, t0
-; RV64-NEXT: mv a6, a7
+; RV64-NEXT: sltu t1, a3, a6
+; RV64-NEXT: mv t0, a7
; RV64-NEXT: bltu a7, t2, .LBB16_4
; RV64-NEXT: # %bb.3:
-; RV64-NEXT: li a6, 64
+; RV64-NEXT: li t0, 64
; RV64-NEXT: .LBB16_4:
-; RV64-NEXT: addi t2, a1, 128
-; RV64-NEXT: csrr a3, vlenb
-; RV64-NEXT: li t3, 24
-; RV64-NEXT: mul a3, a3, t3
-; RV64-NEXT: add a3, sp, a3
-; RV64-NEXT: addi a3, a3, 32
-; RV64-NEXT: vs1r.v v9, (a3) # vscale x 8-byte Folded Spill
+; RV64-NEXT: addi t3, a1, 128
+; RV64-NEXT: vmv1r.v v12, v9
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vi v29, v9, 2
-; RV64-NEXT: addi t6, a1, 512
-; RV64-NEXT: addi t4, a1, 640
-; RV64-NEXT: vmv1r.v v30, v8
-; RV64-NEXT: vslidedown.vi v0, v8, 2
+; RV64-NEXT: vslidedown.vi v14, v9, 2
+; RV64-NEXT: addi s0, a1, 512
+; RV64-NEXT: addi t6, a1, 640
; RV64-NEXT: addi t1, t1, -1
-; RV64-NEXT: addi t3, a1, 384
-; RV64-NEXT: vslidedown.vi v31, v28, 2
+; RV64-NEXT: addi t2, a1, 384
; RV64-NEXT: li a3, 32
-; RV64-NEXT: addi t5, a6, -32
-; RV64-NEXT: sltu a6, a6, t5
-; RV64-NEXT: addi a6, a6, -1
-; RV64-NEXT: and a6, a6, t5
-; RV64-NEXT: addi t5, a6, -16
-; RV64-NEXT: sltu s0, a6, t5
-; RV64-NEXT: addi s0, s0, -1
-; RV64-NEXT: bltu a6, a2, .LBB16_6
+; RV64-NEXT: addi t4, t0, -32
+; RV64-NEXT: sltu t0, t0, t4
+; RV64-NEXT: addi t0, t0, -1
+; RV64-NEXT: and t0, t0, t4
+; RV64-NEXT: addi t4, t0, -16
+; RV64-NEXT: sltu t5, t0, t4
+; RV64-NEXT: addi t5, t5, -1
+; RV64-NEXT: vslidedown.vi v0, v10, 2
+; RV64-NEXT: vslidedown.vi v15, v13, 2
+; RV64-NEXT: bltu t0, a2, .LBB16_6
; RV64-NEXT: # %bb.5:
-; RV64-NEXT: li a6, 16
+; RV64-NEXT: li t0, 16
; RV64-NEXT: .LBB16_6:
+; RV64-NEXT: vmv1r.v v7, v10
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vle64.v v8, (t6)
-; RV64-NEXT: csrr t6, vlenb
+; RV64-NEXT: vle64.v v16, (s0)
+; RV64-NEXT: csrr s0, vlenb
; RV64-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT: li a0, 66
-; RV64-NEXT: mul t6, t6, a0
+; RV64-NEXT: li a0, 57
+; RV64-NEXT: mul s0, s0, a0
; RV64-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
-; RV64-NEXT: add t6, sp, t6
-; RV64-NEXT: addi t6, t6, 32
-; RV64-NEXT: vs8r.v v8, (t6) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vle64.v v16, (t4)
-; RV64-NEXT: vle64.v v8, (t2)
-; RV64-NEXT: csrr t2, vlenb
-; RV64-NEXT: li t4, 25
-; RV64-NEXT: mul t2, t2, t4
-; RV64-NEXT: add t2, sp, t2
-; RV64-NEXT: addi t2, t2, 32
-; RV64-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vle64.v v8, (a1)
+; RV64-NEXT: add s0, sp, s0
+; RV64-NEXT: addi s0, s0, 32
+; RV64-NEXT: vs8r.v v16, (s0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vle64.v v24, (t6)
+; RV64-NEXT: vle64.v v16, (t3)
+; RV64-NEXT: csrr t3, vlenb
+; RV64-NEXT: slli t3, t3, 4
+; RV64-NEXT: add t3, sp, t3
+; RV64-NEXT: addi t3, t3, 32
+; RV64-NEXT: vs8r.v v16, (t3) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vle64.v v16, (a1)
+; RV64-NEXT: csrr t3, vlenb
+; RV64-NEXT: slli t3, t3, 3
+; RV64-NEXT: add t3, sp, t3
+; RV64-NEXT: addi t3, t3, 32
+; RV64-NEXT: vs8r.v v16, (t3) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vle64.v v16, (t2)
; RV64-NEXT: csrr t2, vlenb
-; RV64-NEXT: li t4, 58
-; RV64-NEXT: mul t2, t2, t4
-; RV64-NEXT: add t2, sp, t2
-; RV64-NEXT: addi t2, t2, 32
-; RV64-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vle64.v v8, (t3)
-; RV64-NEXT: csrr t2, vlenb
-; RV64-NEXT: slli t2, t2, 4
+; RV64-NEXT: li t3, 49
+; RV64-NEXT: mul t2, t2, t3
; RV64-NEXT: add t2, sp, t2
; RV64-NEXT: addi t2, t2, 32
-; RV64-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: and t2, t1, t0
-; RV64-NEXT: and t1, s0, t5
+; RV64-NEXT: vs8r.v v16, (t2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: and t2, t1, a6
+; RV64-NEXT: and t1, t5, t4
; RV64-NEXT: addi a1, a1, 256
-; RV64-NEXT: mv t0, a4
+; RV64-NEXT: mv a6, a4
; RV64-NEXT: bltu a4, a3, .LBB16_8
; RV64-NEXT: # %bb.7:
-; RV64-NEXT: li t0, 32
+; RV64-NEXT: li a6, 32
; RV64-NEXT: .LBB16_8:
; RV64-NEXT: vsetvli zero, t2, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
-; RV64-NEXT: addi t2, sp, 32
-; RV64-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v30
+; RV64-NEXT: vnsrl.wi v8, v24, 0, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: csrr t2, vlenb
-; RV64-NEXT: li t3, 66
+; RV64-NEXT: li t3, 57
; RV64-NEXT: mul t2, t2, t3
; RV64-NEXT: add t2, sp, t2
; RV64-NEXT: addi t2, t2, 32
; RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, a5, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; RV64-NEXT: vnsrl.wi v24, v16, 0, v0.t
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li t2, 74
-; RV64-NEXT: mul a5, a5, t2
+; RV64-NEXT: slli t2, a5, 6
+; RV64-NEXT: add a5, t2, a5
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v29
+; RV64-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv1r.v v0, v14
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li t2, 25
-; RV64-NEXT: mul a5, a5, t2
+; RV64-NEXT: slli a5, a5, 4
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, t1, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; RV64-NEXT: vnsrl.wi v24, v16, 0, v0.t
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: slli t1, a5, 5
-; RV64-NEXT: add a5, t1, a5
+; RV64-NEXT: li t1, 24
+; RV64-NEXT: mul a5, a5, t1
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; RV64-NEXT: addi a5, t0, -16
-; RV64-NEXT: sltu t0, t0, a5
-; RV64-NEXT: addi t0, t0, -1
-; RV64-NEXT: and a5, t0, a5
+; RV64-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv1r.v v0, v12
+; RV64-NEXT: csrr a5, vlenb
+; RV64-NEXT: slli a5, a5, 3
+; RV64-NEXT: add a5, sp, a5
+; RV64-NEXT: addi a5, a5, 32
+; RV64-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vsetvli zero, t0, e32, m4, ta, ma
+; RV64-NEXT: vnsrl.wi v16, v24, 0, v0.t
+; RV64-NEXT: csrr a5, vlenb
+; RV64-NEXT: li t0, 57
+; RV64-NEXT: mul a5, a5, t0
+; RV64-NEXT: add a5, sp, a5
+; RV64-NEXT: addi a5, a5, 32
+; RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; RV64-NEXT: addi a5, a6, -16
+; RV64-NEXT: sltu a6, a6, a5
+; RV64-NEXT: addi a6, a6, -1
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vle64.v v8, (a1)
+; RV64-NEXT: vle64.v v16, (a1)
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV64-NEXT: and a1, a6, a5
+; RV64-NEXT: vmv1r.v v0, v15
+; RV64-NEXT: csrr a5, vlenb
+; RV64-NEXT: li a6, 49
+; RV64-NEXT: mul a5, a5, a6
+; RV64-NEXT: add a5, sp, a5
+; RV64-NEXT: addi a5, a5, 32
+; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV64-NEXT: vnsrl.wi v24, v16, 0, v0.t
+; RV64-NEXT: addi a1, sp, 32
+; RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li t0, 57
-; RV64-NEXT: mul a1, a1, t0
+; RV64-NEXT: li a5, 48
+; RV64-NEXT: mul a1, a1, a5
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vl1r.v v8, (a1) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vl1r.v v12, (a1) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vi v8, v8, 2
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li t0, 25
-; RV64-NEXT: mul a1, a1, t0
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li t0, 58
-; RV64-NEXT: mul a1, a1, t0
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li t0, 24
-; RV64-NEXT: mul a1, a1, t0
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; RV64-NEXT: vsetvli zero, a6, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a6, 66
-; RV64-NEXT: mul a1, a1, a6
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v31
+; RV64-NEXT: vslidedown.vi v12, v12, 2
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 4
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetvli zero, a5, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; RV64-NEXT: vs1r.v v12, (a1) # vscale x 8-byte Folded Spill
; RV64-NEXT: bltu a4, a2, .LBB16_10
; RV64-NEXT: # %bb.9:
; RV64-NEXT: li a4, 16
; RV64-NEXT: .LBB16_10:
-; RV64-NEXT: vmv1r.v v0, v28
+; RV64-NEXT: vmv1r.v v0, v13
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, sp, a1
@@ -781,7 +750,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: vsetvli zero, a4, e32, m4, ta, ma
; RV64-NEXT: vnsrl.wi v16, v24, 0, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a4, 58
+; RV64-NEXT: li a4, 49
; RV64-NEXT: mul a1, a1, a4
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
@@ -791,68 +760,65 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: # %bb.11:
; RV64-NEXT: li a1, 32
; RV64-NEXT: .LBB16_12:
-; RV64-NEXT: addi a4, sp, 32
-; RV64-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmv4r.v v24, v16
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a5, a4, 5
-; RV64-NEXT: add a4, a5, a4
+; RV64-NEXT: li a5, 24
+; RV64-NEXT: mul a4, a4, a5
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
; RV64-NEXT: vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
+; RV64-NEXT: addi a4, sp, 32
+; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: li a5, 74
-; RV64-NEXT: mul a4, a4, a5
+; RV64-NEXT: slli a5, a4, 6
+; RV64-NEXT: add a4, a5, a4
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
; RV64-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; RV64-NEXT: vslideup.vi v16, v24, 16
+; RV64-NEXT: vslideup.vi v16, v8, 16
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: li a5, 74
-; RV64-NEXT: mul a4, a4, a5
+; RV64-NEXT: slli a5, a4, 6
+; RV64-NEXT: add a4, a5, a4
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64-NEXT: addi a4, a1, -16
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 66
+; RV64-NEXT: li a6, 57
; RV64-NEXT: mul a5, a5, a6
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vslideup.vi v16, v0, 16
+; RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vslideup.vi v8, v0, 16
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 66
+; RV64-NEXT: li a6, 57
; RV64-NEXT: mul a5, a5, a6
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 58
+; RV64-NEXT: li a6, 49
; RV64-NEXT: mul a5, a5, a6
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vslideup.vi v16, v8, 16
+; RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vslideup.vi v8, v24, 16
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 58
+; RV64-NEXT: li a6, 49
; RV64-NEXT: mul a5, a5, a6
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
; RV64-NEXT: sltu a1, a1, a4
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: and a1, a1, a4
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: li a5, 41
-; RV64-NEXT: mul a4, a4, a5
+; RV64-NEXT: slli a4, a4, 5
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
; RV64-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: li a5, 25
-; RV64-NEXT: mul a4, a4, a5
+; RV64-NEXT: slli a4, a4, 4
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
; RV64-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
@@ -863,13 +829,13 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: li a7, 16
; RV64-NEXT: .LBB16_14:
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 57
+; RV64-NEXT: li a2, 48
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 49
+; RV64-NEXT: li a2, 40
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
@@ -881,7 +847,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: vse32.v v24, (a0)
; RV64-NEXT: addi a1, a0, 256
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 58
+; RV64-NEXT: li a3, 49
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 32
@@ -889,7 +855,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: vse32.v v8, (a1)
; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 66
+; RV64-NEXT: li a3, 57
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 32
@@ -897,14 +863,14 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: vse32.v v8, (a1)
; RV64-NEXT: addi a0, a0, 384
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 74
-; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: slli a2, a1, 6
+; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 82
+; RV64-NEXT: li a1, 73
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 48
@@ -923,8 +889,8 @@ define <32 x i32> @vtrunc_v32i32_v32i64(<32 x i64> %a, <32 x i1> %m, i32 zeroext
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: vslidedown.vi v12, v0, 2
; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: vslidedown.vi v12, v0, 2
; CHECK-NEXT: bltu a0, a2, .LBB17_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
index 3d1febe95421f..2b35ad000e6d6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
@@ -363,9 +363,9 @@ define <32 x double> @vuitofp_v32f64_v32i64(<32 x i64> %va, <32 x i1> %m, i32 ze
; CHECK-LABEL: vuitofp_v32f64_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB25_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
index 1fc4283795075..06a958b4df7d2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
@@ -352,12 +352,12 @@ define <256 x i8> @vadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %ev
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
+; CHECK-NEXT: addi a3, a1, -128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: addi a0, a1, -128
-; CHECK-NEXT: sltu a3, a1, a0
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a0, a3, a0
+; CHECK-NEXT: sltu a0, a1, a3
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a3
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB32_2
@@ -1319,9 +1319,9 @@ define <32 x i64> @vadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; CHECK-LABEL: vadd_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB108_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
@@ -1375,11 +1375,10 @@ define <32 x i64> @vadd_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
define <32 x i64> @vadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vadd_vx_v32i64_evl27:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
index 671da89366041..d752848664009 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
@@ -548,9 +548,9 @@ define <32 x double> @vfabs_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; CHECK-LABEL: vfabs_vv_v32f64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB34_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
index e94c8278f511a..58d889860abd2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
@@ -524,9 +524,9 @@ define <32 x double> @vfneg_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; CHECK-LABEL: vfneg_vv_v32f64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB34_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
index b431d4873fa1b..ef5497c766e30 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
@@ -352,9 +352,9 @@ define <32 x double> @vfsqrt_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zero
; CHECK-LABEL: vfsqrt_vv_v32f64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB26_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
index eafb52c1c006a..179c303fb3414 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
@@ -256,12 +256,12 @@ define <256 x i8> @vmax_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zero
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
+; CHECK-NEXT: addi a4, a2, -128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: addi a1, a2, -128
-; CHECK-NEXT: sltu a4, a2, a1
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a1, a4, a1
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmax.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB22_2
@@ -991,9 +991,9 @@ define <32 x i64> @vmax_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; CHECK-LABEL: vmax_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB74_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
index dd234cb203873..729621d7c53eb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
@@ -255,12 +255,12 @@ define <256 x i8> @vmaxu_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zer
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
+; CHECK-NEXT: addi a4, a2, -128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: addi a1, a2, -128
-; CHECK-NEXT: sltu a4, a2, a1
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a1, a4, a1
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmaxu.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB22_2
@@ -990,9 +990,9 @@ define <32 x i64> @vmaxu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; CHECK-LABEL: vmaxu_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB74_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
index 609d1df976dde..e3a3087241e2f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
@@ -256,12 +256,12 @@ define <256 x i8> @vmin_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zero
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
+; CHECK-NEXT: addi a4, a2, -128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: addi a1, a2, -128
-; CHECK-NEXT: sltu a4, a2, a1
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a1, a4, a1
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmin.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB22_2
@@ -991,9 +991,9 @@ define <32 x i64> @vmin_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; CHECK-LABEL: vmin_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB74_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
index 7c4efb760393e..f7a4c11f576ca 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
@@ -255,12 +255,12 @@ define <256 x i8> @vminu_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zer
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
+; CHECK-NEXT: addi a4, a2, -128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: addi a1, a2, -128
-; CHECK-NEXT: sltu a4, a2, a1
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a1, a4, a1
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vminu.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB22_2
@@ -990,9 +990,9 @@ define <32 x i64> @vminu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; CHECK-LABEL: vminu_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB74_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
index a72ae512b2019..bcd4c530334d0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
@@ -361,12 +361,12 @@ define <256 x i8> @vsadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %e
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
+; CHECK-NEXT: addi a3, a1, -128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: addi a0, a1, -128
-; CHECK-NEXT: sltu a3, a1, a0
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a0, a3, a0
+; CHECK-NEXT: sltu a0, a1, a3
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a3
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB32_2
@@ -1326,9 +1326,9 @@ define <32 x i64> @vsadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; CHECK-LABEL: vsadd_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB108_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
@@ -1382,11 +1382,10 @@ define <32 x i64> @vsadd_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
define <32 x i64> @vsadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vsadd_vx_v32i64_evl27:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
index 51bab9bcf2997..1c3348f8f5f13 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
@@ -357,12 +357,12 @@ define <256 x i8> @vsaddu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
+; CHECK-NEXT: addi a3, a1, -128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: addi a0, a1, -128
-; CHECK-NEXT: sltu a3, a1, a0
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a0, a3, a0
+; CHECK-NEXT: sltu a0, a1, a3
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a3
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB32_2
@@ -1322,9 +1322,9 @@ define <32 x i64> @vsaddu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %e
; CHECK-LABEL: vsaddu_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB108_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
@@ -1378,11 +1378,10 @@ define <32 x i64> @vsaddu_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
define <32 x i64> @vsaddu_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vsaddu_vx_v32i64_evl27:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
index 2db96dca3123d..cbf4c37b70ecb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
@@ -140,8 +140,8 @@ define <256 x i8> @select_v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c, i3
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v6, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: addi a4, a1, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -152,7 +152,6 @@ define <256 x i8> @select_v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c, i3
; CHECK-NEXT: vle8.v v16, (a1)
; CHECK-NEXT: addi a4, a4, -1
; CHECK-NEXT: and a0, a4, a0
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vmerge.vvm v24, v8, v24, v0
; CHECK-NEXT: bltu a3, a2, .LBB11_2
@@ -180,17 +179,16 @@ define <256 x i8> @select_evl_v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c
; CHECK-LABEL: select_evl_v256i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v8
-; CHECK-NEXT: vmv1r.v v6, v0
+; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: addi a3, a1, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v24, (a3)
; CHECK-NEXT: vle8.v v8, (a1)
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v24, (a0), v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: vmv8r.v v16, v24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
index f5aba6885efcc..1cb1a838a2596 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
@@ -374,11 +374,11 @@ define <256 x i8> @vssub_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %e
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: addi a3, a1, -128
+; CHECK-NEXT: sltu a4, a1, a3
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: sltu a0, a1, a3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a3, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t
@@ -1366,9 +1366,9 @@ define <32 x i64> @vssub_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; CHECK-LABEL: vssub_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB108_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
@@ -1425,12 +1425,11 @@ define <32 x i64> @vssub_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
define <32 x i64> @vssub_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vssub_vx_v32i64_evl27:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
index 1d74d1f5a6ead..199a341e12acd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
@@ -369,11 +369,11 @@ define <256 x i8> @vssubu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: addi a3, a1, -128
+; CHECK-NEXT: sltu a4, a1, a3
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: sltu a0, a1, a3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a3, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t
@@ -1361,9 +1361,9 @@ define <32 x i64> @vssubu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %e
; CHECK-LABEL: vssubu_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB108_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
@@ -1420,12 +1420,11 @@ define <32 x i64> @vssubu_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
define <32 x i64> @vssubu_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vssubu_vx_v32i64_evl27:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
index 714c027fbfa0b..890a537683ba2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
@@ -138,9 +138,9 @@ define <32 x i64> @vzext_v32i64_v32i32(<32 x i32> %va, <32 x i1> %m, i32 zeroext
; CHECK-LABEL: vzext_v32i64_v32i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB12_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
index fe41552c4c984..333216423ad63 100644
--- a/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
@@ -17,12 +17,12 @@ define <vscale x 1 x bfloat> @vp_floor_nxv1bf16(<vscale x 1 x bfloat> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -67,12 +67,12 @@ define <vscale x 2 x bfloat> @vp_floor_nxv2bf16(<vscale x 2 x bfloat> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
@@ -410,12 +410,12 @@ define <vscale x 1 x half> @vp_floor_nxv1f16(<vscale x 1 x half> %va, <vscale x
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -494,12 +494,12 @@ define <vscale x 2 x half> @vp_floor_nxv2f16(<vscale x 2 x half> %va, <vscale x
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
index c0ddb812f833e..cebc7287c0a7e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
@@ -169,47 +169,46 @@ define <vscale x 32 x bfloat> @vfmax_nxv32bf16_vv(<vscale x 32 x bfloat> %a, <vs
; ZVFBFMIN-NEXT: slli a0, a0, 4
; ZVFBFMIN-NEXT: sub sp, sp, a0
; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vmv8r.v v0, v16
-; ZVFBFMIN-NEXT: vmv8r.v v24, v8
+; ZVFBFMIN-NEXT: vmv8r.v v24, v16
; ZVFBFMIN-NEXT: addi a0, sp, 16
-; ZVFBFMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v0
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v24
+; ZVFBFMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFBFMIN-NEXT: vmv8r.v v0, v8
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v24
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v0
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmfeq.vv v3, v16, v16
; ZVFBFMIN-NEXT: vmerge.vvm v24, v8, v16, v0
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
; ZVFBFMIN-NEXT: addi a0, a0, 16
; ZVFBFMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFBFMIN-NEXT: vmv1r.v v0, v3
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v8, v0
+; ZVFBFMIN-NEXT: addi a0, sp, 16
+; ZVFBFMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v24, v4
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v28
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
; ZVFBFMIN-NEXT: addi a0, a0, 16
-; ZVFBFMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFBFMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFBFMIN-NEXT: vfmax.vv v8, v8, v16
+; ZVFBFMIN-NEXT: vfmax.vv v8, v8, v24
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
; ZVFBFMIN-NEXT: addi a0, a0, 16
; ZVFBFMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVFBFMIN-NEXT: addi a0, sp, 16
-; ZVFBFMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v20
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v4
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmerge.vvm v16, v8, v24, v0
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v24, v24
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v24, v8, v0
-; ZVFBFMIN-NEXT: vfmax.vv v16, v8, v16
+; ZVFBFMIN-NEXT: vmerge.vvm v24, v8, v16, v0
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v8, v0
+; ZVFBFMIN-NEXT: vfmax.vv v16, v8, v24
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
@@ -400,47 +399,46 @@ define <vscale x 32 x half> @vfmax_nxv32f16_vv(<vscale x 32 x half> %a, <vscale
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: sub sp, sp, a0
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vmv8r.v v0, v16
-; ZVFHMIN-NEXT: vmv8r.v v24, v8
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24
+; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv8r.v v0, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmfeq.vv v3, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
+; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmax.vv v8, v8, v16
+; ZVFHMIN-NEXT: vfmax.vv v8, v8, v24
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v16, v8, v24, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24
-; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v8, v0
-; ZVFHMIN-NEXT: vfmax.vv v16, v8, v16
+; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
+; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
+; ZVFHMIN-NEXT: vfmax.vv v16, v8, v24
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
index 4fe3faadf0fb8..c5da02c3af05c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
@@ -228,15 +228,18 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a2, 26
-; CHECK-NEXT: mul a1, a1, a2
+; CHECK-NEXT: slli a2, a1, 5
+; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
@@ -249,21 +252,18 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a4, 25
-; CHECK-NEXT: mul a3, a3, a4
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: mul a2, a2, a4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 25
@@ -289,14 +289,13 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v4, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v9, v16, v16, v0.t
-; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; CHECK-NEXT: vmv1r.v v6, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v6, v9
; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vfmax.vv v16, v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
@@ -328,21 +327,33 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v24, v8, v8, v0.t
-; CHECK-NEXT: vmfeq.vv v25, v16, v16, v0.t
+; CHECK-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; CHECK-NEXT: vmv1r.v v6, v0
; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vmv1r.v v6, v25
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 25
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 25
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vfmax.vv v16, v16, v24, v0.t
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 26
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a1, a0, 5
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -358,92 +369,46 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 5
+; CHECK-NEXT: li a2, 24
+; CHECK-NEXT: mul a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: vmset.m v8
+; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
+; CHECK-NEXT: vmset.m v24
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a2
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: li a4, 24
-; CHECK-NEXT: mul a2, a2, a4
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vslidedown.vx v0, v24, a2
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: li a4, 24
-; CHECK-NEXT: mul a3, a3, a4
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a3, a3, 3
; CHECK-NEXT: add a3, sp, a3
; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: li a3, 24
-; CHECK-NEXT: mul a2, a2, a3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v7, v24, v24, v0.t
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: li a3, 24
-; CHECK-NEXT: mul a2, a2, a3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmfeq.vv v6, v24, v24, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: li a3, 24
-; CHECK-NEXT: mul a2, a2, a3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmv1r.v v7, v17
+; CHECK-NEXT: vmfeq.vv v7, v8, v8, v0.t
+; CHECK-NEXT: vmv1r.v v5, v0
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: li a3, 24
-; CHECK-NEXT: mul a2, a2, a3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v5
; CHECK-NEXT: vfmax.vv v16, v8, v16, v0.t
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: li a3, 24
-; CHECK-NEXT: mul a2, a2, a3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: addi a2, sp, 16
@@ -469,16 +434,14 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 24
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmfeq.vv v0, v24, v24
; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 24
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
@@ -488,7 +451,8 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: li a1, 24
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -843,15 +807,18 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: li a2, 26
-; ZVFHMIN-NEXT: mul a1, a1, a2
+; ZVFHMIN-NEXT: slli a2, a1, 5
+; ZVFHMIN-NEXT: add a1, a2, a1
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -864,21 +831,18 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: li a4, 25
-; ZVFHMIN-NEXT: mul a3, a3, a4
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: mul a2, a2, a4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: li a3, 25
@@ -904,14 +868,13 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v9, v16, v16, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
+; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v6, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: vmv1r.v v6, v9
; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vfmax.vv v16, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
@@ -943,21 +906,33 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v24, v8, v8, v0.t
-; ZVFHMIN-NEXT: vmfeq.vv v25, v16, v16, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v6, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v24
-; ZVFHMIN-NEXT: vmv1r.v v6, v25
; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v8, v0
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: li a1, 25
+; ZVFHMIN-NEXT: mul a0, a0, a1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v8, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: li a1, 25
+; ZVFHMIN-NEXT: mul a0, a0, a1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfmax.vv v16, v16, v24, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: li a1, 26
-; ZVFHMIN-NEXT: mul a0, a0, a1
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -983,92 +958,46 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: li a2, 24
+; ZVFHMIN-NEXT: mul a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 4
-; ZVFHMIN-NEXT: add a1, sp, a1
-; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; ZVFHMIN-NEXT: vmv8r.v v16, v8
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: vmset.m v8
+; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma
+; ZVFHMIN-NEXT: vmset.m v24
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a2
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: li a4, 24
-; ZVFHMIN-NEXT: mul a2, a2, a4
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: li a4, 24
-; ZVFHMIN-NEXT: mul a3, a3, a4
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: li a3, 24
-; ZVFHMIN-NEXT: mul a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v7, v24, v24, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: li a3, 24
-; ZVFHMIN-NEXT: mul a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vmfeq.vv v6, v24, v24, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: li a3, 24
-; ZVFHMIN-NEXT: mul a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v17, v8, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: vmv1r.v v7, v17
+; ZVFHMIN-NEXT: vmfeq.vv v7, v8, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v5, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vmerge.vvm v16, v24, v8, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v24, v0
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: li a3, 24
-; ZVFHMIN-NEXT: mul a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v5
; ZVFHMIN-NEXT: vfmax.vv v16, v8, v16, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: li a3, 24
-; ZVFHMIN-NEXT: mul a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
@@ -1094,16 +1023,14 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
; ZVFHMIN-NEXT: vmerge.vvm v16, v8, v24, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: li a1, 24
-; ZVFHMIN-NEXT: mul a0, a0, a1
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24
; ZVFHMIN-NEXT: vmerge.vvm v16, v24, v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: li a1, 24
-; ZVFHMIN-NEXT: mul a0, a0, a1
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
@@ -1113,7 +1040,8 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: li a1, 24
+; ZVFHMIN-NEXT: mul a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -1382,141 +1310,73 @@ define <vscale x 16 x double> @vfmax_vv_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a3, 27
+; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1b, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 27 * vlenb
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a3, a1, 3
-; CHECK-NEXT: srli a4, a1, 3
-; CHECK-NEXT: csrr a5, vlenb
-; CHECK-NEXT: li a6, 26
-; CHECK-NEXT: mul a5, a5, a6
-; CHECK-NEXT: add a5, sp, a5
-; CHECK-NEXT: addi a5, a5, 16
-; CHECK-NEXT: vs1r.v v0, (a5) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vslidedown.vx v24, v0, a4
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: li a5, 18
-; CHECK-NEXT: mul a4, a4, a5
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vs1r.v v24, (a4) # vscale x 8-byte Folded Spill
; CHECK-NEXT: sub a4, a2, a1
; CHECK-NEXT: add a3, a0, a3
; CHECK-NEXT: vl8re64.v v24, (a3)
; CHECK-NEXT: sltu a3, a2, a4
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a3, a3, a4
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: li a5, 18
-; CHECK-NEXT: mul a4, a4, a5
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: srli a4, a1, 3
+; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v5, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a4
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v5, v16, v16, v0.t
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: li a4, 18
-; CHECK-NEXT: mul a3, a3, a4
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v4, v24, v24, v0.t
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a4, a3, 3
-; CHECK-NEXT: add a3, a4, a3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs1r.v v5, (a3) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs1r.v v4, (a3) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vl8re64.v v0, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a3, 10
-; CHECK-NEXT: mul a0, a0, a3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a3, a0, 3
-; CHECK-NEXT: add a0, a3, a0
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; CHECK-NEXT: vmfeq.vv v6, v24, v24, v0.t
+; CHECK-NEXT: vmv1r.v v4, v0
+; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a3, 18
-; CHECK-NEXT: mul a0, a0, a3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v4
; CHECK-NEXT: vfmax.vv v8, v16, v8, v0.t
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a3, 18
-; CHECK-NEXT: mul a0, a0, a3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: bltu a2, a1, .LBB40_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB40_2:
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v5
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 26
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v16, v24, v24, v0.t
+; CHECK-NEXT: vmfeq.vv v24, v16, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 10
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 26
-; CHECK-NEXT: mul a0, a0, a1
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vmv1r.v v7, v17
-; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
+; CHECK-NEXT: vmfeq.vv v7, v8, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 26
-; CHECK-NEXT: mul a0, a0, a1
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vfmax.vv v8, v8, v16, v0.t
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 18
-; CHECK-NEXT: mul a0, a0, a1
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vfmax.vv v8, v8, v24, v0.t
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 27
+; CHECK-NEXT: li a1, 24
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
@@ -1537,7 +1397,10 @@ define <vscale x 16 x double> @vfmax_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a3, a1, 3
@@ -1548,43 +1411,32 @@ define <vscale x 16 x double> @vfmax_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a3, a3, a4
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v8, v16, v16
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v7, v24, v24
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: vfmax.vv v8, v16, v8
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: bltu a2, a1, .LBB41_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB41_2:
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -1592,10 +1444,7 @@ define <vscale x 16 x double> @vfmax_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: vfmax.vv v8, v8, v24
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
index 02ae0b8032776..13d41efc556bb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
@@ -169,47 +169,46 @@ define <vscale x 32 x bfloat> @vfmin_nxv32bf16_vv(<vscale x 32 x bfloat> %a, <vs
; ZVFBFMIN-NEXT: slli a0, a0, 4
; ZVFBFMIN-NEXT: sub sp, sp, a0
; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vmv8r.v v0, v16
-; ZVFBFMIN-NEXT: vmv8r.v v24, v8
+; ZVFBFMIN-NEXT: vmv8r.v v24, v16
; ZVFBFMIN-NEXT: addi a0, sp, 16
-; ZVFBFMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v0
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v24
+; ZVFBFMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFBFMIN-NEXT: vmv8r.v v0, v8
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v24
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v0
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmfeq.vv v3, v16, v16
; ZVFBFMIN-NEXT: vmerge.vvm v24, v8, v16, v0
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
; ZVFBFMIN-NEXT: addi a0, a0, 16
; ZVFBFMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFBFMIN-NEXT: vmv1r.v v0, v3
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v8, v0
+; ZVFBFMIN-NEXT: addi a0, sp, 16
+; ZVFBFMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v24, v4
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v28
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
; ZVFBFMIN-NEXT: addi a0, a0, 16
-; ZVFBFMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFBFMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFBFMIN-NEXT: vfmin.vv v8, v8, v16
+; ZVFBFMIN-NEXT: vfmin.vv v8, v8, v24
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
; ZVFBFMIN-NEXT: addi a0, a0, 16
; ZVFBFMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVFBFMIN-NEXT: addi a0, sp, 16
-; ZVFBFMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v20
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v4
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmerge.vvm v16, v8, v24, v0
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v24, v24
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v24, v8, v0
-; ZVFBFMIN-NEXT: vfmin.vv v16, v8, v16
+; ZVFBFMIN-NEXT: vmerge.vvm v24, v8, v16, v0
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v8, v0
+; ZVFBFMIN-NEXT: vfmin.vv v16, v8, v24
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
@@ -400,47 +399,46 @@ define <vscale x 32 x half> @vfmin_nxv32f16_vv(<vscale x 32 x half> %a, <vscale
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: sub sp, sp, a0
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vmv8r.v v0, v16
-; ZVFHMIN-NEXT: vmv8r.v v24, v8
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24
+; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv8r.v v0, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmfeq.vv v3, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
+; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmin.vv v8, v8, v16
+; ZVFHMIN-NEXT: vfmin.vv v8, v8, v24
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v16, v8, v24, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24
-; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v8, v0
-; ZVFHMIN-NEXT: vfmin.vv v16, v8, v16
+; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
+; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
+; ZVFHMIN-NEXT: vfmin.vv v16, v8, v24
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
index e8b708fb84aad..72cd2ef1d9702 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
@@ -228,15 +228,18 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a2, 26
-; CHECK-NEXT: mul a1, a1, a2
+; CHECK-NEXT: slli a2, a1, 5
+; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
@@ -249,21 +252,18 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a4, 25
-; CHECK-NEXT: mul a3, a3, a4
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: mul a2, a2, a4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 25
@@ -289,14 +289,13 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v4, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v9, v16, v16, v0.t
-; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; CHECK-NEXT: vmv1r.v v6, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv1r.v v6, v9
; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vfmin.vv v16, v16, v8, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
@@ -328,21 +327,33 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v24, v8, v8, v0.t
-; CHECK-NEXT: vmfeq.vv v25, v16, v16, v0.t
+; CHECK-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; CHECK-NEXT: vmv1r.v v6, v0
; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vmv1r.v v6, v25
; CHECK-NEXT: vmerge.vvm v24, v8, v16, v0
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 25
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 25
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vfmin.vv v16, v16, v24, v0.t
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 26
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a1, a0, 5
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -358,92 +369,46 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 5
+; CHECK-NEXT: li a2, 24
+; CHECK-NEXT: mul a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: vmset.m v8
+; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
+; CHECK-NEXT: vmset.m v24
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v8, a2
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: li a4, 24
-; CHECK-NEXT: mul a2, a2, a4
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vslidedown.vx v0, v24, a2
; CHECK-NEXT: sltu a2, a0, a3
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: li a4, 24
-; CHECK-NEXT: mul a3, a3, a4
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a3, a3, 3
; CHECK-NEXT: add a3, sp, a3
; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: li a3, 24
-; CHECK-NEXT: mul a2, a2, a3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v7, v24, v24, v0.t
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: li a3, 24
-; CHECK-NEXT: mul a2, a2, a3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmfeq.vv v6, v24, v24, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: li a3, 24
-; CHECK-NEXT: mul a2, a2, a3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmv1r.v v7, v17
+; CHECK-NEXT: vmfeq.vv v7, v8, v8, v0.t
+; CHECK-NEXT: vmv1r.v v5, v0
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: li a3, 24
-; CHECK-NEXT: mul a2, a2, a3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v5
; CHECK-NEXT: vfmin.vv v16, v8, v16, v0.t
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: li a3, 24
-; CHECK-NEXT: mul a2, a2, a3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
; CHECK-NEXT: addi a2, sp, 16
@@ -469,16 +434,14 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 24
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmfeq.vv v0, v24, v24
; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 24
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
@@ -488,7 +451,8 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: li a1, 24
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -843,15 +807,18 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: li a2, 26
-; ZVFHMIN-NEXT: mul a1, a1, a2
+; ZVFHMIN-NEXT: slli a2, a1, 5
+; ZVFHMIN-NEXT: add a1, a2, a1
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -864,21 +831,18 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: li a4, 25
-; ZVFHMIN-NEXT: mul a3, a3, a4
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: mul a2, a2, a4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: li a3, 25
@@ -904,14 +868,13 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v9, v16, v16, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v7, v0
+; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v6, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: vmv1r.v v6, v9
; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v16, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v24, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vfmin.vv v16, v16, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
@@ -943,21 +906,33 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v24, v8, v8, v0.t
-; ZVFHMIN-NEXT: vmfeq.vv v25, v16, v16, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v6, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v24
-; ZVFHMIN-NEXT: vmv1r.v v6, v25
; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v8, v0
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: li a1, 25
+; ZVFHMIN-NEXT: mul a0, a0, a1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vmerge.vvm v16, v16, v8, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: li a1, 25
+; ZVFHMIN-NEXT: mul a0, a0, a1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfmin.vv v16, v16, v24, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: li a1, 26
-; ZVFHMIN-NEXT: mul a0, a0, a1
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -983,92 +958,46 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: li a2, 24
+; ZVFHMIN-NEXT: mul a1, a1, a2
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
-; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 4
-; ZVFHMIN-NEXT: add a1, sp, a1
-; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; ZVFHMIN-NEXT: vmv8r.v v16, v8
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: vmset.m v8
+; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma
+; ZVFHMIN-NEXT: vmset.m v24
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a2
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: li a4, 24
-; ZVFHMIN-NEXT: mul a2, a2, a4
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2
; ZVFHMIN-NEXT: sltu a2, a0, a3
; ZVFHMIN-NEXT: addi a2, a2, -1
; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: li a4, 24
-; ZVFHMIN-NEXT: mul a3, a3, a4
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: li a3, 24
-; ZVFHMIN-NEXT: mul a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v7, v24, v24, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: li a3, 24
-; ZVFHMIN-NEXT: mul a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vmfeq.vv v6, v24, v24, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: li a3, 24
-; ZVFHMIN-NEXT: mul a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v17, v8, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: vmv1r.v v7, v17
+; ZVFHMIN-NEXT: vmfeq.vv v7, v8, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v5, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vmerge.vvm v16, v24, v8, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v24, v0
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: li a3, 24
-; ZVFHMIN-NEXT: mul a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v5
; ZVFHMIN-NEXT: vfmin.vv v16, v8, v16, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: li a3, 24
-; ZVFHMIN-NEXT: mul a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
@@ -1094,16 +1023,14 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
; ZVFHMIN-NEXT: vmerge.vvm v16, v8, v24, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: li a1, 24
-; ZVFHMIN-NEXT: mul a0, a0, a1
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24
; ZVFHMIN-NEXT: vmerge.vvm v16, v24, v8, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: li a1, 24
-; ZVFHMIN-NEXT: mul a0, a0, a1
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
@@ -1113,7 +1040,8 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: li a1, 24
+; ZVFHMIN-NEXT: mul a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -1382,141 +1310,73 @@ define <vscale x 16 x double> @vfmin_vv_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a3, 27
+; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1b, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 27 * vlenb
-; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a3, a1, 3
-; CHECK-NEXT: srli a4, a1, 3
-; CHECK-NEXT: csrr a5, vlenb
-; CHECK-NEXT: li a6, 26
-; CHECK-NEXT: mul a5, a5, a6
-; CHECK-NEXT: add a5, sp, a5
-; CHECK-NEXT: addi a5, a5, 16
-; CHECK-NEXT: vs1r.v v0, (a5) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vslidedown.vx v24, v0, a4
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: li a5, 18
-; CHECK-NEXT: mul a4, a4, a5
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vs1r.v v24, (a4) # vscale x 8-byte Folded Spill
; CHECK-NEXT: sub a4, a2, a1
; CHECK-NEXT: add a3, a0, a3
; CHECK-NEXT: vl8re64.v v24, (a3)
; CHECK-NEXT: sltu a3, a2, a4
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a3, a3, a4
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: li a5, 18
-; CHECK-NEXT: mul a4, a4, a5
-; CHECK-NEXT: add a4, sp, a4
-; CHECK-NEXT: addi a4, a4, 16
-; CHECK-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: srli a4, a1, 3
+; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v5, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a4
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v5, v16, v16, v0.t
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: li a4, 18
-; CHECK-NEXT: mul a3, a3, a4
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v4, v24, v24, v0.t
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a4, a3, 3
-; CHECK-NEXT: add a3, a4, a3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs1r.v v5, (a3) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs1r.v v4, (a3) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vl8re64.v v0, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a3, 10
-; CHECK-NEXT: mul a0, a0, a3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a3, a0, 3
-; CHECK-NEXT: add a0, a3, a0
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vmfeq.vv v7, v16, v16, v0.t
+; CHECK-NEXT: vmfeq.vv v6, v24, v24, v0.t
+; CHECK-NEXT: vmv1r.v v4, v0
+; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a3, 18
-; CHECK-NEXT: mul a0, a0, a3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v4
; CHECK-NEXT: vfmin.vv v8, v16, v8, v0.t
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a3, 18
-; CHECK-NEXT: mul a0, a0, a3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: bltu a2, a1, .LBB40_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB40_2:
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v5
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 26
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v16, v24, v24, v0.t
+; CHECK-NEXT: vmfeq.vv v24, v16, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 10
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 26
-; CHECK-NEXT: mul a0, a0, a1
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v17, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vmv1r.v v7, v17
-; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
+; CHECK-NEXT: vmfeq.vv v7, v8, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 26
-; CHECK-NEXT: mul a0, a0, a1
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vfmin.vv v8, v8, v16, v0.t
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 18
-; CHECK-NEXT: mul a0, a0, a1
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vfmin.vv v8, v8, v24, v0.t
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 27
+; CHECK-NEXT: li a1, 24
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
@@ -1537,7 +1397,10 @@ define <vscale x 16 x double> @vfmin_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a3, a1, 3
@@ -1548,43 +1411,32 @@ define <vscale x 16 x double> @vfmin_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a3, a3, a4
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v8, v16, v16
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v7, v24, v24
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: vfmin.vv v8, v16, v8
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: bltu a2, a1, .LBB41_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB41_2:
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -1592,10 +1444,7 @@ define <vscale x 16 x double> @vfmin_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: vfmin.vv v8, v8, v24
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
index 5d00204f903fe..1a0d1431de1d0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
@@ -1506,104 +1506,69 @@ define <vscale x 16 x i64> @fshl_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a3, a1, 5
-; CHECK-NEXT: add a1, a3, a1
+; CHECK-NEXT: li a3, 26
+; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a3, a1, 4
+; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: li a1, 63
; CHECK-NEXT: slli a5, a3, 3
-; CHECK-NEXT: srli a1, a3, 3
; CHECK-NEXT: sub a6, a4, a3
-; CHECK-NEXT: csrr a7, vlenb
-; CHECK-NEXT: slli a7, a7, 5
-; CHECK-NEXT: add a7, sp, a7
-; CHECK-NEXT: addi a7, a7, 16
+; CHECK-NEXT: add a7, a2, a5
+; CHECK-NEXT: vl8re64.v v8, (a7)
+; CHECK-NEXT: sltu a7, a4, a6
+; CHECK-NEXT: addi a7, a7, -1
+; CHECK-NEXT: and a6, a7, a6
+; CHECK-NEXT: srli a7, a3, 3
+; CHECK-NEXT: csrr t0, vlenb
+; CHECK-NEXT: li t1, 25
+; CHECK-NEXT: mul t0, t0, t1
+; CHECK-NEXT: add t0, sp, t0
+; CHECK-NEXT: addi t0, t0, 16
+; CHECK-NEXT: vs1r.v v0, (t0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vsetvli t0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a7
+; CHECK-NEXT: addi a7, sp, 16
; CHECK-NEXT: vs1r.v v0, (a7) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v0, a1
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a7, 24
-; CHECK-NEXT: mul a1, a1, a7
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: add a1, a2, a5
-; CHECK-NEXT: vl8re64.v v8, (a1)
-; CHECK-NEXT: sltu a1, a4, a6
-; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a6, a1, a6
-; CHECK-NEXT: li a1, 63
-; CHECK-NEXT: csrr a7, vlenb
-; CHECK-NEXT: li t0, 24
-; CHECK-NEXT: mul a7, a7, t0
-; CHECK-NEXT: add a7, sp, a7
-; CHECK-NEXT: addi a7, a7, 16
-; CHECK-NEXT: vl1r.v v0, (a7) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; CHECK-NEXT: vand.vx v24, v8, a1, v0.t
+; CHECK-NEXT: vsll.vv v16, v16, v24, v0.t
; CHECK-NEXT: csrr a6, vlenb
-; CHECK-NEXT: li a7, 24
-; CHECK-NEXT: mul a6, a6, a7
+; CHECK-NEXT: slli a7, a6, 3
+; CHECK-NEXT: add a6, a7, a6
; CHECK-NEXT: add a6, sp, a6
; CHECK-NEXT: addi a6, a6, 16
-; CHECK-NEXT: vl1r.v v0, (a6) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsll.vv v16, v16, v24, v0.t
-; CHECK-NEXT: addi a6, sp, 16
; CHECK-NEXT: vs8r.v v16, (a6) # vscale x 64-byte Folded Spill
; CHECK-NEXT: add a5, a0, a5
-; CHECK-NEXT: csrr a6, vlenb
-; CHECK-NEXT: li a7, 24
-; CHECK-NEXT: mul a6, a6, a7
-; CHECK-NEXT: add a6, sp, a6
-; CHECK-NEXT: addi a6, a6, 16
-; CHECK-NEXT: vl1r.v v0, (a6) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vnot.v v24, v8, v0.t
; CHECK-NEXT: vl8re64.v v16, (a5)
-; CHECK-NEXT: csrr a5, vlenb
-; CHECK-NEXT: li a6, 24
-; CHECK-NEXT: mul a5, a5, a6
-; CHECK-NEXT: add a5, sp, a5
-; CHECK-NEXT: addi a5, a5, 16
-; CHECK-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vand.vx v8, v24, a1, v0.t
; CHECK-NEXT: vl8re64.v v24, (a0)
+; CHECK-NEXT: vl8re64.v v0, (a2)
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vl8re64.v v24, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a2, 24
-; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsrl.vi v16, v16, 1, v0.t
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a2, 24
-; CHECK-NEXT: mul a0, a0, a2
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsrl.vv v8, v16, v8, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a2, 24
-; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: slli a2, a0, 3
+; CHECK-NEXT: add a0, a2, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a2, 24
-; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: slli a2, a0, 3
+; CHECK-NEXT: add a0, a2, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
@@ -1612,68 +1577,74 @@ define <vscale x 16 x i64> @fshl_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
; CHECK-NEXT: mv a4, a3
; CHECK-NEXT: .LBB47_2:
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: li a2, 25
+; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; CHECK-NEXT: vsrl.vi v16, v24, 1, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: li a2, 25
+; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
-; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vnot.v v24, v24, v0.t
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vnot.v v24, v8, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: li a2, 25
+; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: li a2, 25
+; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsrl.vv v16, v16, v24, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: li a2, 25
+; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vand.vx v24, v8, a1, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a1, a0, 4
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: li a1, 25
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsll.vv v24, v8, v24, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: li a1, 25
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vor.vv v8, v24, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 24
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a1, a0, 5
-; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: li a1, 26
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
index 0d6d09e8dfa08..e81abda5f301c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
@@ -453,8 +453,8 @@ define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_2(<vscale x 4 x i1> %v, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
+; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: srli a1, a0, 3
diff --git a/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
index d3c3349919ec9..1ac2ee1234d78 100644
--- a/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
@@ -52,14 +52,14 @@ define <vscale x 16 x i64> @llrint_nxv16i64_nxv16f32(<vscale x 16 x float> %x, <
; CHECK-LABEL: llrint_nxv16i64_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma
; CHECK-NEXT: vfwcvt.x.f.v v16, v12, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB4_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
index e672a3a554962..a7bd1d379eb43 100644
--- a/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
@@ -114,14 +114,14 @@ define <vscale x 16 x iXLen> @lrint_nxv16f32(<vscale x 16 x float> %x, <vscale x
; RV64-i64-LABEL: lrint_nxv16f32:
; RV64-i64: # %bb.0:
; RV64-i64-NEXT: csrr a1, vlenb
-; RV64-i64-NEXT: srli a2, a1, 3
-; RV64-i64-NEXT: sub a3, a0, a1
+; RV64-i64-NEXT: sub a2, a0, a1
+; RV64-i64-NEXT: sltu a3, a0, a2
+; RV64-i64-NEXT: addi a3, a3, -1
+; RV64-i64-NEXT: and a2, a3, a2
+; RV64-i64-NEXT: srli a3, a1, 3
; RV64-i64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; RV64-i64-NEXT: vmv1r.v v24, v0
-; RV64-i64-NEXT: vslidedown.vx v0, v0, a2
-; RV64-i64-NEXT: sltu a2, a0, a3
-; RV64-i64-NEXT: addi a2, a2, -1
-; RV64-i64-NEXT: and a2, a2, a3
+; RV64-i64-NEXT: vslidedown.vx v0, v0, a3
; RV64-i64-NEXT: vsetvli zero, a2, e32, m4, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v16, v12, v0.t
; RV64-i64-NEXT: bltu a0, a1, .LBB4_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
index 75b8aa515a717..792426e96dceb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
@@ -2284,16 +2284,16 @@ define <vscale x 32 x i8> @mgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8>
; RV64-NEXT: vluxei64.v v13, (a0), v16, v0.t
; RV64-NEXT: srli a1, a1, 2
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vslidedown.vx v9, v8, a1
-; RV64-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v0, v9, a2
+; RV64-NEXT: vslidedown.vx v8, v8, a1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v11
-; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
+; RV64-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vx v0, v8, a2
+; RV64-NEXT: vsetvli a1, zero, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v15, (a0), v16, v0.t
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v10
-; RV64-NEXT: vmv1r.v v0, v9
+; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v14, (a0), v16, v0.t
; RV64-NEXT: vmv4r.v v8, v12
diff --git a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
index 639a91535f191..a7afdcc817343 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
@@ -1951,8 +1951,8 @@ define void @mscatter_baseidx_zext_nxv1i1_nxv1i8(<vscale x 1 x i8> %val, ptr %ba
; CHECK-LABEL: mscatter_baseidx_zext_nxv1i1_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
+; CHECK-NEXT: vmv.v.i v11, 0
+; CHECK-NEXT: vmerge.vim v10, v11, 1, v0
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vsoxei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
index f7b68ce1f64b8..4e69a2623339d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
@@ -17,10 +17,10 @@ define <vscale x 1 x bfloat> @vp_nearbyint_nxv1bf16(<vscale x 1 x bfloat> %va, <
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
@@ -67,10 +67,10 @@ define <vscale x 2 x bfloat> @vp_nearbyint_nxv2bf16(<vscale x 2 x bfloat> %va, <
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
@@ -296,12 +296,12 @@ define <vscale x 32 x bfloat> @vp_nearbyint_nxv32bf16(<vscale x 32 x bfloat> %va
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; CHECK-NEXT: fsflags a2
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
+; CHECK-NEXT: fsflags a2
; CHECK-NEXT: bltu a0, a1, .LBB10_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -359,12 +359,12 @@ define <vscale x 32 x bfloat> @vp_nearbyint_nxv32bf16_unmasked(<vscale x 32 x bf
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; CHECK-NEXT: fsflags a2
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
+; CHECK-NEXT: fsflags a2
; CHECK-NEXT: bltu a0, a1, .LBB11_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -410,10 +410,10 @@ define <vscale x 1 x half> @vp_nearbyint_nxv1f16(<vscale x 1 x half> %va, <vscal
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
@@ -494,10 +494,10 @@ define <vscale x 2 x half> @vp_nearbyint_nxv2f16(<vscale x 2 x half> %va, <vscal
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
@@ -865,12 +865,12 @@ define <vscale x 32 x half> @vp_nearbyint_nxv32f16(<vscale x 32 x half> %va, <vs
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; ZVFHMIN-NEXT: fsflags a2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: fsflags a2
; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
@@ -944,12 +944,12 @@ define <vscale x 32 x half> @vp_nearbyint_nxv32f16_unmasked(<vscale x 32 x half>
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; ZVFHMIN-NEXT: fsflags a2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: fsflags a2
; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr165232.ll b/llvm/test/CodeGen/RISCV/rvv/pr165232.ll
index 39a1b3b6e4559..9c4c293d599b4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/pr165232.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/pr165232.ll
@@ -12,254 +12,183 @@ define i1 @main(ptr %var_117, ptr %arrayinit.element3045, ptr %arrayinit.element
; CHECK-NEXT: csrr t0, vlenb
; CHECK-NEXT: slli t0, t0, 1
; CHECK-NEXT: mv t1, t0
+; CHECK-NEXT: slli t0, t0, 3
+; CHECK-NEXT: add t0, t0, t1
+; CHECK-NEXT: sub sp, sp, t0
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x12, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 18 * vlenb
+; CHECK-NEXT: csrr t0, vlenb
+; CHECK-NEXT: slli t0, t0, 1
+; CHECK-NEXT: mv t1, t0
; CHECK-NEXT: slli t0, t0, 2
-; CHECK-NEXT: add t1, t1, t0
+; CHECK-NEXT: add t0, t0, t1
+; CHECK-NEXT: add t0, sp, t0
+; CHECK-NEXT: addi t0, t0, 16
+; CHECK-NEXT: vs4r.v v12, (t0) # vscale x 32-byte Folded Spill
+; CHECK-NEXT: csrr t1, vlenb
+; CHECK-NEXT: slli t1, t1, 2
+; CHECK-NEXT: add t0, t0, t1
+; CHECK-NEXT: vs4r.v v16, (t0) # vscale x 32-byte Folded Spill
+; CHECK-NEXT: csrr t0, vlenb
+; CHECK-NEXT: slli t0, t0, 1
+; CHECK-NEXT: mv t1, t0
; CHECK-NEXT: slli t0, t0, 1
; CHECK-NEXT: add t0, t0, t1
-; CHECK-NEXT: sub sp, sp, t0
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
-; CHECK-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd a2, 0(sp) # 8-byte Folded Spill
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 2
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: ld t0, 56(a1)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: ld t1, 48(a1)
+; CHECK-NEXT: add t0, sp, t0
+; CHECK-NEXT: addi t0, t0, 16
+; CHECK-NEXT: vs4r.v v8, (t0) # vscale x 32-byte Folded Spill
+; CHECK-NEXT: csrr t0, vlenb
+; CHECK-NEXT: slli t0, t0, 1
+; CHECK-NEXT: mv t1, t0
+; CHECK-NEXT: slli t0, t0, 3
+; CHECK-NEXT: add t0, t0, t1
+; CHECK-NEXT: add t0, sp, t0
+; CHECK-NEXT: ld t0, 56(t0)
+; CHECK-NEXT: csrr t1, vlenb
+; CHECK-NEXT: slli t1, t1, 1
+; CHECK-NEXT: mv t2, t1
+; CHECK-NEXT: slli t1, t1, 3
+; CHECK-NEXT: add t1, t1, t2
+; CHECK-NEXT: add t1, sp, t1
+; CHECK-NEXT: ld t1, 48(t1)
; CHECK-NEXT: vsetvli t2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: ld t2, 40(a1)
-; CHECK-NEXT: # kill: def $v13 killed $v12 killed $vtype
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: ld t3, 32(a1)
-; CHECK-NEXT: vmv.v.i v14, 0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: ld t4, 16(a1)
+; CHECK-NEXT: vmv.v.i v13, 0
+; CHECK-NEXT: csrr t2, vlenb
+; CHECK-NEXT: slli t2, t2, 1
+; CHECK-NEXT: mv t3, t2
+; CHECK-NEXT: slli t2, t2, 3
+; CHECK-NEXT: add t2, t2, t3
+; CHECK-NEXT: add t2, sp, t2
+; CHECK-NEXT: ld t2, 40(t2)
+; CHECK-NEXT: # kill: def $v14 killed $v13 killed $vtype
+; CHECK-NEXT: csrr t3, vlenb
+; CHECK-NEXT: slli t3, t3, 1
+; CHECK-NEXT: mv t4, t3
+; CHECK-NEXT: slli t3, t3, 3
+; CHECK-NEXT: add t3, t3, t4
+; CHECK-NEXT: add t3, sp, t3
+; CHECK-NEXT: ld t3, 32(t3)
; CHECK-NEXT: vmv.v.i v15, 0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: ld t5, 24(a1)
+; CHECK-NEXT: csrr t4, vlenb
+; CHECK-NEXT: slli t4, t4, 1
+; CHECK-NEXT: mv t5, t4
+; CHECK-NEXT: slli t4, t4, 3
+; CHECK-NEXT: add t4, t4, t5
+; CHECK-NEXT: add t4, sp, t4
+; CHECK-NEXT: ld t4, 16(t4)
; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: csrr t5, vlenb
+; CHECK-NEXT: slli t5, t5, 1
+; CHECK-NEXT: mv t6, t5
+; CHECK-NEXT: slli t5, t5, 3
+; CHECK-NEXT: add t5, t5, t6
+; CHECK-NEXT: add t5, sp, t5
+; CHECK-NEXT: ld t5, 24(t5)
+; CHECK-NEXT: vmv.v.i v17, 0
; CHECK-NEXT: vsetvli t6, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v20, 0
-; CHECK-NEXT: vmv1r.v v17, v12
+; CHECK-NEXT: vmv1r.v v18, v13
; CHECK-NEXT: sd zero, 0(a0)
; CHECK-NEXT: vmv.v.i v22, 0
-; CHECK-NEXT: vmv1r.v v18, v12
-; CHECK-NEXT: vmv4r.v v8, v12
+; CHECK-NEXT: vmv1r.v v19, v13
+; CHECK-NEXT: vmv1r.v v8, v13
; CHECK-NEXT: li t6, 1023
; CHECK-NEXT: vmv.v.i v24, 0
-; CHECK-NEXT: vmv1r.v v9, v12
+; CHECK-NEXT: vmv1r.v v9, v13
; CHECK-NEXT: slli t6, t6, 52
; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vs4r.v v20, (a1) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 2
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: ld a2, 0(sp) # 8-byte Folded Reload
-; CHECK-NEXT: vs4r.v v24, (a1) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
-; CHECK-NEXT: vmv1r.v v10, v12
+; CHECK-NEXT: vmv1r.v v10, v13
; CHECK-NEXT: sd t6, 0(t5)
-; CHECK-NEXT: vmv1r.v v19, v12
-; CHECK-NEXT: vmv1r.v v20, v13
-; CHECK-NEXT: vmv1r.v v21, v14
-; CHECK-NEXT: vmv1r.v v22, v15
-; CHECK-NEXT: vmv1r.v v23, v16
-; CHECK-NEXT: vmv1r.v v24, v17
-; CHECK-NEXT: vmv1r.v v25, v18
-; CHECK-NEXT: vmv1r.v v11, v12
+; CHECK-NEXT: vmv1r.v v11, v13
; CHECK-NEXT: csrr t5, vlenb
; CHECK-NEXT: slli t5, t5, 1
-; CHECK-NEXT: mv t6, t5
-; CHECK-NEXT: slli t5, t5, 2
-; CHECK-NEXT: add t5, t5, t6
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
; CHECK-NEXT: vs4r.v v8, (t5) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: vsetivli zero, 0, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; CHECK-NEXT: vmclr.m v8
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: csrr t5, vlenb
-; CHECK-NEXT: slli t6, t5, 3
-; CHECK-NEXT: add t5, t6, t5
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
; CHECK-NEXT: vs1r.v v8, (t5) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: csrr t5, vlenb
-; CHECK-NEXT: slli t5, t5, 3
-; CHECK-NEXT: add t5, sp, t5
-; CHECK-NEXT: addi t5, t5, 16
+; CHECK-NEXT: addi t5, sp, 16
; CHECK-NEXT: vs1r.v v8, (t5) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: .LBB0_1: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmv.v.i v30, 0
-; CHECK-NEXT: vmv.v.i v31, 0
-; CHECK-NEXT: vmv.v.i v13, 0
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmv.v.i v11, 0
-; CHECK-NEXT: vmv.v.i v18, 0
-; CHECK-NEXT: vmv2r.v v0, v18
-; CHECK-NEXT: vmv2r.v v2, v20
-; CHECK-NEXT: vmv2r.v v4, v22
-; CHECK-NEXT: vmv2r.v v6, v24
-; CHECK-NEXT: vmv2r.v v14, v16
-; CHECK-NEXT: vmv2r.v v28, v16
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: csrr t5, vlenb
-; CHECK-NEXT: slli t6, t5, 3
-; CHECK-NEXT: add t5, t6, t5
-; CHECK-NEXT: add t5, sp, t5
-; CHECK-NEXT: addi t5, t5, 16
-; CHECK-NEXT: vl1r.v v8, (t5) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
-; CHECK-NEXT: vle32.v v30, (t4)
-; CHECK-NEXT: vle32.v v31, (t1)
-; CHECK-NEXT: vle32.v v11, (a7)
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vmv.v.i v6, 0
+; CHECK-NEXT: vmv.v.i v28, 0
+; CHECK-NEXT: vmv1r.v v30, v9
+; CHECK-NEXT: vmv1r.v v12, v9
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, ma
; CHECK-NEXT: vle64.v v28, (a4)
-; CHECK-NEXT: vle32.v v13, (t2)
-; CHECK-NEXT: vle32.v v26, (t3)
-; CHECK-NEXT: vle32.v v10, (a6)
-; CHECK-NEXT: vmv1r.v v2, v11
+; CHECK-NEXT: vle32.v v30, (a2)
+; CHECK-NEXT: vle32.v v12, (a3)
; CHECK-NEXT: csrr t5, vlenb
-; CHECK-NEXT: slli t5, t5, 3
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
-; CHECK-NEXT: vl1r.v v0, (t5) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vl1r.v v10, (t5) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v8, v28, v16, v0.t
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vmflt.vv v10, v28, v6, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu
-; CHECK-NEXT: vle32.v v12, (a2)
-; CHECK-NEXT: vle32.v v10, (a3)
-; CHECK-NEXT: vle32.v v18, (a5)
-; CHECK-NEXT: vmv1r.v v0, v30
+; CHECK-NEXT: vssub.vv v12, v9, v30, v0.t
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vmv1r.v v11, v9
+; CHECK-NEXT: vmv1r.v v28, v9
+; CHECK-NEXT: vmv1r.v v29, v9
+; CHECK-NEXT: vmv1r.v v30, v9
+; CHECK-NEXT: vmv1r.v v31, v9
+; CHECK-NEXT: vle32.v v10, (t4)
+; CHECK-NEXT: vle32.v v31, (a7)
+; CHECK-NEXT: vle32.v v11, (t1)
+; CHECK-NEXT: vle32.v v28, (t2)
+; CHECK-NEXT: vle32.v v29, (t3)
+; CHECK-NEXT: vmv1r.v v2, v13
+; CHECK-NEXT: vmv1r.v v4, v15
+; CHECK-NEXT: vmv1r.v v5, v16
+; CHECK-NEXT: vmv1r.v v6, v17
+; CHECK-NEXT: vmv1r.v v7, v18
+; CHECK-NEXT: vmv1r.v v8, v19
+; CHECK-NEXT: vle32.v v30, (a6)
+; CHECK-NEXT: vmv1r.v v3, v31
+; CHECK-NEXT: vmv1r.v v11, v9
+; CHECK-NEXT: vle32.v v11, (a5)
+; CHECK-NEXT: vmv1r.v v1, v10
; CHECK-NEXT: csrr t5, vlenb
; CHECK-NEXT: slli t5, t5, 1
-; CHECK-NEXT: mv t6, t5
-; CHECK-NEXT: slli t5, t5, 2
-; CHECK-NEXT: add t5, t5, t6
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
; CHECK-NEXT: vl4r.v v28, (t5) # vscale x 32-byte Folded Reload
; CHECK-NEXT: vsseg4e32.v v28, (zero)
-; CHECK-NEXT: vsseg8e32.v v0, (a1)
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vssub.vv v10, v9, v12, v0.t
+; CHECK-NEXT: vsseg8e32.v v1, (a1)
; CHECK-NEXT: csrr t5, vlenb
; CHECK-NEXT: slli t5, t5, 1
; CHECK-NEXT: mv t6, t5
; CHECK-NEXT: slli t5, t5, 1
-; CHECK-NEXT: add t6, t6, t5
-; CHECK-NEXT: slli t5, t5, 1
; CHECK-NEXT: add t5, t5, t6
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
-; CHECK-NEXT: vl2r.v v2, (t5) # vscale x 16-byte Folded Reload
-; CHECK-NEXT: csrr t6, vlenb
-; CHECK-NEXT: slli t6, t6, 1
-; CHECK-NEXT: add t5, t5, t6
-; CHECK-NEXT: vl2r.v v4, (t5) # vscale x 16-byte Folded Reload
+; CHECK-NEXT: vl4r.v v28, (t5) # vscale x 32-byte Folded Reload
; CHECK-NEXT: vsetvli zero, t0, e64, m2, ta, ma
-; CHECK-NEXT: vsseg2e64.v v2, (zero)
+; CHECK-NEXT: vsseg2e64.v v28, (zero)
; CHECK-NEXT: addi t5, sp, 16
-; CHECK-NEXT: vl2r.v v2, (t5) # vscale x 16-byte Folded Reload
-; CHECK-NEXT: csrr t6, vlenb
-; CHECK-NEXT: slli t6, t6, 1
-; CHECK-NEXT: add t5, t5, t6
-; CHECK-NEXT: vl4r.v v4, (t5) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: slli t6, t6, 1
-; CHECK-NEXT: add t5, t5, t6
-; CHECK-NEXT: vl2r.v v8, (t5) # vscale x 16-byte Folded Reload
-; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vl1r.v v0, (t5) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetivli zero, 0, e64, m2, ta, ma
-; CHECK-NEXT: vsseg4e64.v v2, (zero), v0.t
+; CHECK-NEXT: vsseg4e64.v v20, (zero), v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vsseg8e32.v v10, (a0)
+; CHECK-NEXT: vsseg8e32.v v12, (a0)
; CHECK-NEXT: csrr t5, vlenb
; CHECK-NEXT: slli t5, t5, 1
; CHECK-NEXT: mv t6, t5
-; CHECK-NEXT: slli t5, t5, 3
+; CHECK-NEXT: slli t5, t5, 2
; CHECK-NEXT: add t5, t5, t6
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
-; CHECK-NEXT: vl2r.v v2, (t5) # vscale x 16-byte Folded Reload
-; CHECK-NEXT: csrr t6, vlenb
-; CHECK-NEXT: slli t6, t6, 1
-; CHECK-NEXT: add t5, t5, t6
-; CHECK-NEXT: vl4r.v v4, (t5) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: slli t6, t6, 1
-; CHECK-NEXT: add t5, t5, t6
-; CHECK-NEXT: vl2r.v v8, (t5) # vscale x 16-byte Folded Reload
+; CHECK-NEXT: vl8r.v v0, (t5) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; CHECK-NEXT: vsseg4e64.v v2, (zero)
+; CHECK-NEXT: vsseg4e64.v v0, (zero)
; CHECK-NEXT: j .LBB0_1
entry:
store double 0.000000e+00, ptr %var_117, align 8
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr88576.ll b/llvm/test/CodeGen/RISCV/rvv/pr88576.ll
index 0d025d06b0da4..f0cb7ab0f45b8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/pr88576.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/pr88576.ll
@@ -22,28 +22,18 @@ define i1 @foo(<vscale x 16 x i8> %x, i64 %y) {
; CHECK-NEXT: addi s0, sp, 80
; CHECK-NEXT: .cfi_def_cfa s0, 0
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 2
-; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 2
-; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: andi sp, sp, -64
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 64
+; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v1
+; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
+; CHECK-NEXT: addi a2, sp, 64
; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: add a0, a2, a0
; CHECK-NEXT: add a1, a2, a1
-; CHECK-NEXT: addi a3, sp, 64
-; CHECK-NEXT: vs2r.v v0, (a3) # vscale x 16-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v1
-; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
-; CHECK-NEXT: addi a3, sp, 64
-; CHECK-NEXT: vl2r.v v0, (a3) # vscale x 16-byte Folded Reload
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vs8r.v v8, (a2)
; CHECK-NEXT: lbu a0, 0(a0)
diff --git a/llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll b/llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
index bfff09bc35c8e..b66ef6511a823 100644
--- a/llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
@@ -19,11 +19,12 @@ define i32 @_ZN4Mesh12rezone_countESt6vectorIiSaIiEERiS3_(<vscale x 4 x i32> %wi
; CHECK-NEXT: vmv2r.v v14, v8
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vle32.v v14, (a0), v0.t
-; CHECK-NEXT: vor.vi v12, v12, 1, v0.t
; CHECK-NEXT: vand.vi v14, v14, 1
; CHECK-NEXT: vmsne.vi v16, v14, 0
; CHECK-NEXT: vmand.mm v0, v17, v16
; CHECK-NEXT: vmerge.vim v10, v10, -1, v0
+; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vor.vi v12, v12, 1, v0.t
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: j .LBB0_1
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll
index c5a3b2252de19..7c6074d2dcf5b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll
@@ -17,12 +17,12 @@ define <vscale x 1 x bfloat> @vp_round_nxv1bf16(<vscale x 1 x bfloat> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -67,12 +67,12 @@ define <vscale x 2 x bfloat> @vp_round_nxv2bf16(<vscale x 2 x bfloat> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
@@ -410,12 +410,12 @@ define <vscale x 1 x half> @vp_round_nxv1f16(<vscale x 1 x half> %va, <vscale x
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -494,12 +494,12 @@ define <vscale x 2 x half> @vp_round_nxv2f16(<vscale x 2 x half> %va, <vscale x
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll b/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
index 443909ba2cc25..40a4642d51979 100644
--- a/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
@@ -17,12 +17,12 @@ define <vscale x 1 x bfloat> @vp_roundeven_nxv1bf16(<vscale x 1 x bfloat> %va, <
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -67,12 +67,12 @@ define <vscale x 2 x bfloat> @vp_roundeven_nxv2bf16(<vscale x 2 x bfloat> %va, <
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
@@ -410,12 +410,12 @@ define <vscale x 1 x half> @vp_roundeven_nxv1f16(<vscale x 1 x half> %va, <vscal
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -494,12 +494,12 @@ define <vscale x 2 x half> @vp_roundeven_nxv2f16(<vscale x 2 x half> %va, <vscal
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
index b81e2d7568ceb..6238d57e7eea5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
@@ -17,12 +17,12 @@ define <vscale x 1 x bfloat> @vp_roundtozero_nxv1bf16(<vscale x 1 x bfloat> %va,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -67,12 +67,12 @@ define <vscale x 2 x bfloat> @vp_roundtozero_nxv2bf16(<vscale x 2 x bfloat> %va,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
@@ -410,12 +410,12 @@ define <vscale x 1 x half> @vp_roundtozero_nxv1f16(<vscale x 1 x half> %va, <vsc
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -494,12 +494,12 @@ define <vscale x 2 x half> @vp_roundtozero_nxv2f16(<vscale x 2 x half> %va, <vsc
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
index 92f665477d24f..6ad291b37f313 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
@@ -1342,26 +1342,28 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64bf16(<vscale x 64 x bfloat> %va, <vs
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a3, a3, a1
+; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a3, a3, a1
-; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1b, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 27 * vlenb
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vmv8r.v v0, v16
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x2a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 42 * vlenb
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: mv a3, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a3, a3, a1
; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a3, a3, a1
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a1, a1, a3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a3, a1, 5
+; CHECK-NEXT: add a1, a3, a1
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a1, a3, 3
@@ -1369,7 +1371,7 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64bf16(<vscale x 64 x bfloat> %va, <vs
; CHECK-NEXT: slli a4, a3, 1
; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: sub a6, a2, a5
-; CHECK-NEXT: vl8re16.v v16, (a1)
+; CHECK-NEXT: vl8re16.v v24, (a1)
; CHECK-NEXT: sltu a1, a2, a6
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a6, a1, a6
@@ -1379,42 +1381,47 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64bf16(<vscale x 64 x bfloat> %va, <vs
; CHECK-NEXT: and a7, a7, a1
; CHECK-NEXT: srli a1, a3, 1
; CHECK-NEXT: srli a3, a3, 2
-; CHECK-NEXT: csrr t0, vlenb
-; CHECK-NEXT: slli t0, t0, 1
-; CHECK-NEXT: mv t1, t0
-; CHECK-NEXT: slli t0, t0, 3
-; CHECK-NEXT: add t0, t0, t1
-; CHECK-NEXT: add t0, sp, t0
-; CHECK-NEXT: addi t0, t0, 16
-; CHECK-NEXT: vs1r.v v24, (t0) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vslidedown.vx v24, v24, a1
; CHECK-NEXT: vl8re16.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: mv t0, a0
-; CHECK-NEXT: slli a0, a0, 2
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add t0, t0, a0
+; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add a0, a0, t0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a7, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli t0, a0, 3
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli t0, a0, 4
; CHECK-NEXT: add a0, t0, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v24, a3
+; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20
+; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: mv t0, a0
; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add t0, t0, a0
+; CHECK-NEXT: slli a0, a0, 2
+; CHECK-NEXT: add a0, a0, t0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a7, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v4
+; CHECK-NEXT: vl1r.v v28, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v28, v28, a1
+; CHECK-NEXT: vmv.v.v v7, v28
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v28, a3
; CHECK-NEXT: bltu a6, a4, .LBB85_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a6, a4
@@ -1423,111 +1430,120 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64bf16(<vscale x 64 x bfloat> %va, <vs
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v20, v8, v24, v0.t
-; CHECK-NEXT: vsetvli zero, a6, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v16
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv8r.v v24, v16
+; CHECK-NEXT: vsetvli zero, a7, e32, m8, ta, ma
+; CHECK-NEXT: vmfeq.vv v16, v24, v8, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs1r.v v16, (a0) # vscale x 8-byte Folded Spill
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v0
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a6, e16, m4, ta, ma
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v8
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a6, a0, 3
+; CHECK-NEXT: slli a6, a0, 4
; CHECK-NEXT: add a0, a6, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v8
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v16, v8, v24, v0.t
+; CHECK-NEXT: vmfeq.vv v8, v24, v16, v0.t
; CHECK-NEXT: bltu a2, a5, .LBB85_4
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a2, a5
; CHECK-NEXT: .LBB85_4:
; CHECK-NEXT: sub a0, a2, a4
; CHECK-NEXT: csrr a5, vlenb
-; CHECK-NEXT: slli a5, a5, 1
; CHECK-NEXT: mv a6, a5
; CHECK-NEXT: slli a5, a5, 3
+; CHECK-NEXT: add a6, a6, a5
+; CHECK-NEXT: slli a5, a5, 2
; CHECK-NEXT: add a5, a5, a6
; CHECK-NEXT: add a5, sp, a5
; CHECK-NEXT: addi a5, a5, 16
-; CHECK-NEXT: vl1r.v v8, (a5) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vl1r.v v9, (a5) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v17, v8, a3
+; CHECK-NEXT: vslidedown.vx v9, v9, a3
; CHECK-NEXT: sltu a5, a2, a0
; CHECK-NEXT: addi a5, a5, -1
; CHECK-NEXT: and a0, a5, a0
; CHECK-NEXT: csrr a5, vlenb
-; CHECK-NEXT: mv a6, a5
-; CHECK-NEXT: slli a5, a5, 1
-; CHECK-NEXT: add a6, a6, a5
-; CHECK-NEXT: slli a5, a5, 3
-; CHECK-NEXT: add a5, a5, a6
+; CHECK-NEXT: slli a6, a5, 5
+; CHECK-NEXT: add a5, a6, a5
; CHECK-NEXT: add a5, sp, a5
; CHECK-NEXT: addi a5, a5, 16
-; CHECK-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v28
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: mv a5, a0
-; CHECK-NEXT: slli a0, a0, 2
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a5, a5, a0
+; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add a0, a0, a5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v4
-; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v4
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v17, v24, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v9, v16, v24, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v10, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v16, v20, a3
+; CHECK-NEXT: vslideup.vx v8, v10, a3
; CHECK-NEXT: bltu a2, a4, .LBB85_6
; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: mv a2, a4
; CHECK-NEXT: .LBB85_6:
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: mv a4, a0
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add a4, a4, a0
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, a0, a4
+; CHECK-NEXT: slli a4, a0, 5
+; CHECK-NEXT: add a0, a4, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v24
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v24
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: mv a2, a0
-; CHECK-NEXT: slli a0, a0, 2
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a2, a2, a0
+; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a2, a2, a0
+; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v18, v8, v24, v0.t
+; CHECK-NEXT: vmfeq.vv v10, v16, v24, v0.t
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslideup.vx v18, v17, a3
+; CHECK-NEXT: vslideup.vx v10, v9, a3
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v18, v16, a1
-; CHECK-NEXT: vmv.v.v v0, v18
+; CHECK-NEXT: vslideup.vx v10, v8, a1
+; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add a1, a1, a0
-; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
@@ -3522,26 +3538,28 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: mv a3, a1
; ZVFHMIN-NEXT: slli a1, a1, 1
-; ZVFHMIN-NEXT: add a3, a3, a1
+; ZVFHMIN-NEXT: mv a3, a1
; ZVFHMIN-NEXT: slli a1, a1, 2
; ZVFHMIN-NEXT: add a3, a3, a1
-; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: slli a1, a1, 2
; ZVFHMIN-NEXT: add a1, a1, a3
; ZVFHMIN-NEXT: sub sp, sp, a1
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1b, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 27 * vlenb
-; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; ZVFHMIN-NEXT: vmv1r.v v24, v0
-; ZVFHMIN-NEXT: vmv8r.v v0, v16
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x2a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 42 * vlenb
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: mv a3, a1
-; ZVFHMIN-NEXT: slli a1, a1, 1
-; ZVFHMIN-NEXT: add a3, a3, a1
; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: add a3, a3, a1
+; ZVFHMIN-NEXT: slli a1, a1, 2
; ZVFHMIN-NEXT: add a1, a1, a3
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a3, a1, 5
+; ZVFHMIN-NEXT: add a1, a3, a1
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a1, a3, 3
@@ -3549,7 +3567,7 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFHMIN-NEXT: slli a4, a3, 1
; ZVFHMIN-NEXT: add a1, a0, a1
; ZVFHMIN-NEXT: sub a6, a2, a5
-; ZVFHMIN-NEXT: vl8re16.v v16, (a1)
+; ZVFHMIN-NEXT: vl8re16.v v24, (a1)
; ZVFHMIN-NEXT: sltu a1, a2, a6
; ZVFHMIN-NEXT: addi a1, a1, -1
; ZVFHMIN-NEXT: and a6, a1, a6
@@ -3559,42 +3577,47 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFHMIN-NEXT: and a7, a7, a1
; ZVFHMIN-NEXT: srli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: csrr t0, vlenb
-; ZVFHMIN-NEXT: slli t0, t0, 1
-; ZVFHMIN-NEXT: mv t1, t0
-; ZVFHMIN-NEXT: slli t0, t0, 3
-; ZVFHMIN-NEXT: add t0, t0, t1
-; ZVFHMIN-NEXT: add t0, sp, t0
-; ZVFHMIN-NEXT: addi t0, t0, 16
-; ZVFHMIN-NEXT: vs1r.v v24, (t0) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: vslidedown.vx v24, v24, a1
; ZVFHMIN-NEXT: vl8re16.v v8, (a0)
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 1
; ZVFHMIN-NEXT: mv t0, a0
-; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add t0, t0, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
; ZVFHMIN-NEXT: add a0, a0, t0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a7, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli t0, a0, 3
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli t0, a0, 4
; ZVFHMIN-NEXT: add a0, t0, a0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v8, v24, a3
+; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: mv t0, a0
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add t0, t0, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, t0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs1r.v v8, (a0) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a7, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4
+; ZVFHMIN-NEXT: vl1r.v v28, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v28, v28, a1
+; ZVFHMIN-NEXT: vmv.v.v v7, v28
+; ZVFHMIN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v0, v28, a3
; ZVFHMIN-NEXT: bltu a6, a4, .LBB171_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a6, a4
@@ -3603,111 +3626,120 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v20, v8, v24, v0.t
-; ZVFHMIN-NEXT: vsetvli zero, a6, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: vsetvli zero, a7, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs1r.v v16, (a0) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v0
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a6, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a6, a0, 3
+; ZVFHMIN-NEXT: slli a6, a0, 4
; ZVFHMIN-NEXT: add a0, a6, a0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v16, v0.t
; ZVFHMIN-NEXT: bltu a2, a5, .LBB171_4
; ZVFHMIN-NEXT: # %bb.3:
; ZVFHMIN-NEXT: mv a2, a5
; ZVFHMIN-NEXT: .LBB171_4:
; ZVFHMIN-NEXT: sub a0, a2, a4
; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 1
; ZVFHMIN-NEXT: mv a6, a5
; ZVFHMIN-NEXT: slli a5, a5, 3
+; ZVFHMIN-NEXT: add a6, a6, a5
+; ZVFHMIN-NEXT: slli a5, a5, 2
; ZVFHMIN-NEXT: add a5, a5, a6
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl1r.v v8, (a5) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v9, (a5) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v17, v8, a3
+; ZVFHMIN-NEXT: vslidedown.vx v9, v9, a3
; ZVFHMIN-NEXT: sltu a5, a2, a0
; ZVFHMIN-NEXT: addi a5, a5, -1
; ZVFHMIN-NEXT: and a0, a5, a0
; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: mv a6, a5
-; ZVFHMIN-NEXT: slli a5, a5, 1
-; ZVFHMIN-NEXT: add a6, a6, a5
-; ZVFHMIN-NEXT: slli a5, a5, 3
-; ZVFHMIN-NEXT: add a5, a5, a6
+; ZVFHMIN-NEXT: slli a6, a5, 5
+; ZVFHMIN-NEXT: add a5, a6, a5
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 1
; ZVFHMIN-NEXT: mv a5, a0
-; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a5, a5, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
; ZVFHMIN-NEXT: add a0, a0, a5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4
-; ZVFHMIN-NEXT: vmv1r.v v0, v17
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4
+; ZVFHMIN-NEXT: vmv1r.v v0, v9
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v17, v24, v8, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v9, v16, v24, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl1r.v v10, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslideup.vx v16, v20, a3
+; ZVFHMIN-NEXT: vslideup.vx v8, v10, a3
; ZVFHMIN-NEXT: bltu a2, a4, .LBB171_6
; ZVFHMIN-NEXT: # %bb.5:
; ZVFHMIN-NEXT: mv a2, a4
; ZVFHMIN-NEXT: .LBB171_6:
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: mv a4, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a4, a4, a0
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: add a0, a0, a4
+; ZVFHMIN-NEXT: slli a4, a0, 5
+; ZVFHMIN-NEXT: add a0, a4, a0
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 1
; ZVFHMIN-NEXT: mv a2, a0
-; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a2, a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
; ZVFHMIN-NEXT: add a0, a0, a2
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 1
; ZVFHMIN-NEXT: mv a2, a0
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a2, a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
; ZVFHMIN-NEXT: add a0, a0, a2
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v18, v8, v24, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v10, v16, v24, v0.t
; ZVFHMIN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslideup.vx v18, v17, a3
+; ZVFHMIN-NEXT: vslideup.vx v10, v9, a3
; ZVFHMIN-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZVFHMIN-NEXT: vslideup.vx v18, v16, a1
-; ZVFHMIN-NEXT: vmv.v.v v0, v18
+; ZVFHMIN-NEXT: vslideup.vx v10, v8, a1
+; ZVFHMIN-NEXT: vmv.v.v v0, v10
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: slli a0, a0, 2
; ZVFHMIN-NEXT: add a1, a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: slli a0, a0, 2
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
@@ -4797,14 +4829,10 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK32-NEXT: .cfi_offset s3, -20
; CHECK32-NEXT: .cfi_offset s4, -24
; CHECK32-NEXT: csrr a1, vlenb
-; CHECK32-NEXT: slli a1, a1, 1
-; CHECK32-NEXT: mv a3, a1
-; CHECK32-NEXT: slli a1, a1, 2
-; CHECK32-NEXT: add a3, a3, a1
-; CHECK32-NEXT: slli a1, a1, 1
-; CHECK32-NEXT: add a1, a1, a3
+; CHECK32-NEXT: slli a3, a1, 5
+; CHECK32-NEXT: add a1, a3, a1
; CHECK32-NEXT: sub sp, sp, a1
-; CHECK32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 26 * vlenb
+; CHECK32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 33 * vlenb
; CHECK32-NEXT: mv s1, a6
; CHECK32-NEXT: csrr a1, vlenb
; CHECK32-NEXT: add a1, sp, a1
@@ -4813,14 +4841,17 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK32-NEXT: mv s3, a2
; CHECK32-NEXT: mv s2, a0
; CHECK32-NEXT: csrr a0, vlenb
-; CHECK32-NEXT: slli a1, a0, 3
+; CHECK32-NEXT: slli a1, a0, 4
; CHECK32-NEXT: add a0, a1, a0
; CHECK32-NEXT: add a0, sp, a0
; CHECK32-NEXT: addi a0, a0, 16
; CHECK32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; CHECK32-NEXT: csrr a0, vlenb
-; CHECK32-NEXT: slli a1, a0, 4
-; CHECK32-NEXT: add a0, a1, a0
+; CHECK32-NEXT: mv a1, a0
+; CHECK32-NEXT: slli a0, a0, 3
+; CHECK32-NEXT: add a1, a1, a0
+; CHECK32-NEXT: slli a0, a0, 1
+; CHECK32-NEXT: add a0, a0, a1
; CHECK32-NEXT: add a0, sp, a0
; CHECK32-NEXT: addi a0, a0, 16
; CHECK32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
@@ -4835,74 +4866,76 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK32-NEXT: csrr a2, vlenb
; CHECK32-NEXT: add a2, sp, a2
; CHECK32-NEXT: addi a2, a2, 16
-; CHECK32-NEXT: vl1r.v v8, (a2) # vscale x 8-byte Folded Reload
+; CHECK32-NEXT: vl1r.v v16, (a2) # vscale x 8-byte Folded Reload
; CHECK32-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK32-NEXT: vslidedown.vx v25, v8, s4
-; CHECK32-NEXT: vmv1r.v v7, v25
+; CHECK32-NEXT: vslidedown.vx v25, v16, s4
+; CHECK32-NEXT: vmv1r.v v6, v25
; CHECK32-NEXT: add a2, s3, a4
-; CHECK32-NEXT: vl8re64.v v24, (a2)
-; CHECK32-NEXT: slli a6, s0, 4
+; CHECK32-NEXT: vl8re64.v v8, (a2)
+; CHECK32-NEXT: slli a5, s0, 4
; CHECK32-NEXT: slli a2, s0, 1
-; CHECK32-NEXT: vmv1r.v v6, v8
-; CHECK32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; CHECK32-NEXT: vslidedown.vx v0, v8, a0
; CHECK32-NEXT: mv a3, s1
+; CHECK32-NEXT: vmv1r.v v7, v16
+; CHECK32-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
+; CHECK32-NEXT: vslidedown.vx v0, v16, a0
; CHECK32-NEXT: bltu s1, a2, .LBB257_2
; CHECK32-NEXT: # %bb.1:
; CHECK32-NEXT: mv a3, a2
; CHECK32-NEXT: .LBB257_2:
-; CHECK32-NEXT: add a5, s3, a1
-; CHECK32-NEXT: add a1, s2, a4
-; CHECK32-NEXT: vslidedown.vx v16, v7, a0
-; CHECK32-NEXT: csrr a4, vlenb
-; CHECK32-NEXT: mv a7, a4
-; CHECK32-NEXT: slli a4, a4, 3
-; CHECK32-NEXT: add a7, a7, a4
-; CHECK32-NEXT: slli a4, a4, 1
-; CHECK32-NEXT: add a4, a4, a7
-; CHECK32-NEXT: add a4, sp, a4
-; CHECK32-NEXT: addi a4, a4, 16
-; CHECK32-NEXT: vs1r.v v16, (a4) # vscale x 8-byte Folded Spill
-; CHECK32-NEXT: add a4, s3, a6
-; CHECK32-NEXT: vl8re64.v v16, (s3)
; CHECK32-NEXT: sub a6, a3, s0
; CHECK32-NEXT: sltu a7, a3, a6
; CHECK32-NEXT: addi a7, a7, -1
; CHECK32-NEXT: and a6, a7, a6
+; CHECK32-NEXT: add a1, s3, a1
+; CHECK32-NEXT: add a4, s2, a4
+; CHECK32-NEXT: vl8re64.v v16, (s3)
; CHECK32-NEXT: csrr a7, vlenb
-; CHECK32-NEXT: slli t0, a7, 3
+; CHECK32-NEXT: slli t0, a7, 4
; CHECK32-NEXT: add a7, t0, a7
; CHECK32-NEXT: add a7, sp, a7
; CHECK32-NEXT: addi a7, a7, 16
-; CHECK32-NEXT: vl8r.v v8, (a7) # vscale x 64-byte Folded Reload
+; CHECK32-NEXT: vl8r.v v24, (a7) # vscale x 64-byte Folded Reload
; CHECK32-NEXT: vsetvli zero, a6, e64, m8, ta, ma
-; CHECK32-NEXT: vmfeq.vv v5, v8, v24, v0.t
+; CHECK32-NEXT: vmfeq.vv v5, v24, v8, v0.t
+; CHECK32-NEXT: vmv1r.v v25, v6
+; CHECK32-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
+; CHECK32-NEXT: vslidedown.vx v8, v6, a0
+; CHECK32-NEXT: csrr a6, vlenb
+; CHECK32-NEXT: slli a7, a6, 4
+; CHECK32-NEXT: add a6, a7, a6
+; CHECK32-NEXT: add a6, sp, a6
+; CHECK32-NEXT: addi a6, a6, 16
+; CHECK32-NEXT: vs1r.v v8, (a6) # vscale x 8-byte Folded Spill
+; CHECK32-NEXT: add a5, s3, a5
; CHECK32-NEXT: bltu a3, s0, .LBB257_4
; CHECK32-NEXT: # %bb.3:
; CHECK32-NEXT: mv a3, s0
; CHECK32-NEXT: .LBB257_4:
-; CHECK32-NEXT: vl8re64.v v8, (a5)
-; CHECK32-NEXT: csrr a5, vlenb
-; CHECK32-NEXT: slli a6, a5, 3
-; CHECK32-NEXT: add a5, a6, a5
-; CHECK32-NEXT: add a5, sp, a5
-; CHECK32-NEXT: addi a5, a5, 16
-; CHECK32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; CHECK32-NEXT: vmv1r.v v0, v6
-; CHECK32-NEXT: csrr a5, vlenb
-; CHECK32-NEXT: slli a6, a5, 4
-; CHECK32-NEXT: add a5, a6, a5
-; CHECK32-NEXT: add a5, sp, a5
-; CHECK32-NEXT: addi a5, a5, 16
-; CHECK32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
-; CHECK32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; CHECK32-NEXT: vmfeq.vv v24, v8, v16, v0.t
; CHECK32-NEXT: vl8re64.v v8, (a1)
; CHECK32-NEXT: csrr a1, vlenb
+; CHECK32-NEXT: slli a6, a1, 3
+; CHECK32-NEXT: add a1, a6, a1
; CHECK32-NEXT: add a1, sp, a1
; CHECK32-NEXT: addi a1, a1, 16
; CHECK32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; CHECK32-NEXT: vmv1r.v v0, v7
+; CHECK32-NEXT: csrr a1, vlenb
+; CHECK32-NEXT: mv a6, a1
+; CHECK32-NEXT: slli a1, a1, 3
+; CHECK32-NEXT: add a6, a6, a1
+; CHECK32-NEXT: slli a1, a1, 1
+; CHECK32-NEXT: add a1, a1, a6
+; CHECK32-NEXT: add a1, sp, a1
+; CHECK32-NEXT: addi a1, a1, 16
+; CHECK32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; CHECK32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; CHECK32-NEXT: vmfeq.vv v24, v8, v16, v0.t
; CHECK32-NEXT: vl8re64.v v8, (a4)
+; CHECK32-NEXT: csrr a1, vlenb
+; CHECK32-NEXT: add a1, sp, a1
+; CHECK32-NEXT: addi a1, a1, 16
+; CHECK32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; CHECK32-NEXT: vl8re64.v v8, (a5)
; CHECK32-NEXT: sub a1, s1, a2
; CHECK32-NEXT: sltu a2, s1, a1
; CHECK32-NEXT: vl8re64.v v16, (s2)
@@ -4911,8 +4944,11 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK32-NEXT: vsetvli zero, s4, e8, mf2, tu, ma
; CHECK32-NEXT: vslideup.vx v24, v5, a0
; CHECK32-NEXT: csrr a1, vlenb
-; CHECK32-NEXT: slli a2, a1, 4
-; CHECK32-NEXT: add a1, a2, a1
+; CHECK32-NEXT: mv a2, a1
+; CHECK32-NEXT: slli a1, a1, 3
+; CHECK32-NEXT: add a2, a2, a1
+; CHECK32-NEXT: slli a1, a1, 1
+; CHECK32-NEXT: add a1, a1, a2
; CHECK32-NEXT: add a1, sp, a1
; CHECK32-NEXT: addi a1, a1, 16
; CHECK32-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
@@ -4921,7 +4957,7 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK32-NEXT: # %bb.5:
; CHECK32-NEXT: mv a1, s0
; CHECK32-NEXT: .LBB257_6:
-; CHECK32-NEXT: vmv1r.v v0, v7
+; CHECK32-NEXT: vmv1r.v v0, v25
; CHECK32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK32-NEXT: vmfeq.vv v24, v16, v8, v0.t
; CHECK32-NEXT: addi a1, sp, 16
@@ -4929,8 +4965,11 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK32-NEXT: li a1, 3
; CHECK32-NEXT: call __mulsi3
; CHECK32-NEXT: csrr a1, vlenb
-; CHECK32-NEXT: slli a2, a1, 4
-; CHECK32-NEXT: add a1, a2, a1
+; CHECK32-NEXT: mv a2, a1
+; CHECK32-NEXT: slli a1, a1, 3
+; CHECK32-NEXT: add a2, a2, a1
+; CHECK32-NEXT: slli a1, a1, 1
+; CHECK32-NEXT: add a1, a1, a2
; CHECK32-NEXT: add a1, sp, a1
; CHECK32-NEXT: addi a1, a1, 16
; CHECK32-NEXT: vl1r.v v9, (a1) # vscale x 8-byte Folded Reload
@@ -4943,11 +4982,8 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK32-NEXT: addi a2, a2, -1
; CHECK32-NEXT: and a1, a2, a1
; CHECK32-NEXT: csrr a2, vlenb
-; CHECK32-NEXT: mv a3, a2
-; CHECK32-NEXT: slli a2, a2, 3
-; CHECK32-NEXT: add a3, a3, a2
-; CHECK32-NEXT: slli a2, a2, 1
-; CHECK32-NEXT: add a2, a2, a3
+; CHECK32-NEXT: slli a3, a2, 4
+; CHECK32-NEXT: add a2, a3, a2
; CHECK32-NEXT: add a2, sp, a2
; CHECK32-NEXT: addi a2, a2, 16
; CHECK32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
@@ -4967,12 +5003,8 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK32-NEXT: vslideup.vx v9, v8, a0
; CHECK32-NEXT: vmv1r.v v0, v9
; CHECK32-NEXT: csrr a0, vlenb
-; CHECK32-NEXT: slli a0, a0, 1
-; CHECK32-NEXT: mv a1, a0
-; CHECK32-NEXT: slli a0, a0, 2
-; CHECK32-NEXT: add a1, a1, a0
-; CHECK32-NEXT: slli a0, a0, 1
-; CHECK32-NEXT: add a0, a0, a1
+; CHECK32-NEXT: slli a1, a0, 5
+; CHECK32-NEXT: add a0, a1, a0
; CHECK32-NEXT: add sp, sp, a0
; CHECK32-NEXT: .cfi_def_cfa sp, 48
; CHECK32-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
@@ -5008,14 +5040,10 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK64-NEXT: .cfi_offset s3, -40
; CHECK64-NEXT: .cfi_offset s4, -48
; CHECK64-NEXT: csrr a1, vlenb
-; CHECK64-NEXT: slli a1, a1, 1
-; CHECK64-NEXT: mv a3, a1
-; CHECK64-NEXT: slli a1, a1, 2
-; CHECK64-NEXT: add a3, a3, a1
-; CHECK64-NEXT: slli a1, a1, 1
-; CHECK64-NEXT: add a1, a1, a3
+; CHECK64-NEXT: slli a3, a1, 5
+; CHECK64-NEXT: add a1, a3, a1
; CHECK64-NEXT: sub sp, sp, a1
-; CHECK64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 26 * vlenb
+; CHECK64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 33 * vlenb
; CHECK64-NEXT: mv s1, a6
; CHECK64-NEXT: csrr a1, vlenb
; CHECK64-NEXT: add a1, sp, a1
@@ -5024,14 +5052,17 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK64-NEXT: mv s3, a2
; CHECK64-NEXT: mv s2, a0
; CHECK64-NEXT: csrr a0, vlenb
-; CHECK64-NEXT: slli a1, a0, 3
+; CHECK64-NEXT: slli a1, a0, 4
; CHECK64-NEXT: add a0, a1, a0
; CHECK64-NEXT: add a0, sp, a0
; CHECK64-NEXT: addi a0, a0, 16
; CHECK64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; CHECK64-NEXT: csrr a0, vlenb
-; CHECK64-NEXT: slli a1, a0, 4
-; CHECK64-NEXT: add a0, a1, a0
+; CHECK64-NEXT: mv a1, a0
+; CHECK64-NEXT: slli a0, a0, 3
+; CHECK64-NEXT: add a1, a1, a0
+; CHECK64-NEXT: slli a0, a0, 1
+; CHECK64-NEXT: add a0, a0, a1
; CHECK64-NEXT: add a0, sp, a0
; CHECK64-NEXT: addi a0, a0, 16
; CHECK64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
@@ -5046,74 +5077,76 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK64-NEXT: csrr a2, vlenb
; CHECK64-NEXT: add a2, sp, a2
; CHECK64-NEXT: addi a2, a2, 16
-; CHECK64-NEXT: vl1r.v v8, (a2) # vscale x 8-byte Folded Reload
+; CHECK64-NEXT: vl1r.v v16, (a2) # vscale x 8-byte Folded Reload
; CHECK64-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK64-NEXT: vslidedown.vx v25, v8, s4
-; CHECK64-NEXT: vmv1r.v v7, v25
+; CHECK64-NEXT: vslidedown.vx v25, v16, s4
+; CHECK64-NEXT: vmv1r.v v6, v25
; CHECK64-NEXT: add a2, s3, a4
-; CHECK64-NEXT: vl8re64.v v24, (a2)
-; CHECK64-NEXT: slli a6, s0, 4
+; CHECK64-NEXT: vl8re64.v v8, (a2)
+; CHECK64-NEXT: slli a5, s0, 4
; CHECK64-NEXT: slli a2, s0, 1
-; CHECK64-NEXT: vmv1r.v v6, v8
-; CHECK64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; CHECK64-NEXT: vslidedown.vx v0, v8, a0
; CHECK64-NEXT: mv a3, s1
+; CHECK64-NEXT: vmv1r.v v7, v16
+; CHECK64-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
+; CHECK64-NEXT: vslidedown.vx v0, v16, a0
; CHECK64-NEXT: bltu s1, a2, .LBB257_2
; CHECK64-NEXT: # %bb.1:
; CHECK64-NEXT: mv a3, a2
; CHECK64-NEXT: .LBB257_2:
-; CHECK64-NEXT: add a5, s3, a1
-; CHECK64-NEXT: add a1, s2, a4
-; CHECK64-NEXT: vslidedown.vx v16, v7, a0
-; CHECK64-NEXT: csrr a4, vlenb
-; CHECK64-NEXT: mv a7, a4
-; CHECK64-NEXT: slli a4, a4, 3
-; CHECK64-NEXT: add a7, a7, a4
-; CHECK64-NEXT: slli a4, a4, 1
-; CHECK64-NEXT: add a4, a4, a7
-; CHECK64-NEXT: add a4, sp, a4
-; CHECK64-NEXT: addi a4, a4, 16
-; CHECK64-NEXT: vs1r.v v16, (a4) # vscale x 8-byte Folded Spill
-; CHECK64-NEXT: add a4, s3, a6
-; CHECK64-NEXT: vl8re64.v v16, (s3)
; CHECK64-NEXT: sub a6, a3, s0
; CHECK64-NEXT: sltu a7, a3, a6
; CHECK64-NEXT: addi a7, a7, -1
; CHECK64-NEXT: and a6, a7, a6
+; CHECK64-NEXT: add a1, s3, a1
+; CHECK64-NEXT: add a4, s2, a4
+; CHECK64-NEXT: vl8re64.v v16, (s3)
; CHECK64-NEXT: csrr a7, vlenb
-; CHECK64-NEXT: slli t0, a7, 3
+; CHECK64-NEXT: slli t0, a7, 4
; CHECK64-NEXT: add a7, t0, a7
; CHECK64-NEXT: add a7, sp, a7
; CHECK64-NEXT: addi a7, a7, 16
-; CHECK64-NEXT: vl8r.v v8, (a7) # vscale x 64-byte Folded Reload
+; CHECK64-NEXT: vl8r.v v24, (a7) # vscale x 64-byte Folded Reload
; CHECK64-NEXT: vsetvli zero, a6, e64, m8, ta, ma
-; CHECK64-NEXT: vmfeq.vv v5, v8, v24, v0.t
+; CHECK64-NEXT: vmfeq.vv v5, v24, v8, v0.t
+; CHECK64-NEXT: vmv1r.v v25, v6
+; CHECK64-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
+; CHECK64-NEXT: vslidedown.vx v8, v6, a0
+; CHECK64-NEXT: csrr a6, vlenb
+; CHECK64-NEXT: slli a7, a6, 4
+; CHECK64-NEXT: add a6, a7, a6
+; CHECK64-NEXT: add a6, sp, a6
+; CHECK64-NEXT: addi a6, a6, 16
+; CHECK64-NEXT: vs1r.v v8, (a6) # vscale x 8-byte Folded Spill
+; CHECK64-NEXT: add a5, s3, a5
; CHECK64-NEXT: bltu a3, s0, .LBB257_4
; CHECK64-NEXT: # %bb.3:
; CHECK64-NEXT: mv a3, s0
; CHECK64-NEXT: .LBB257_4:
-; CHECK64-NEXT: vl8re64.v v8, (a5)
-; CHECK64-NEXT: csrr a5, vlenb
-; CHECK64-NEXT: slli a6, a5, 3
-; CHECK64-NEXT: add a5, a6, a5
-; CHECK64-NEXT: add a5, sp, a5
-; CHECK64-NEXT: addi a5, a5, 16
-; CHECK64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; CHECK64-NEXT: vmv1r.v v0, v6
-; CHECK64-NEXT: csrr a5, vlenb
-; CHECK64-NEXT: slli a6, a5, 4
-; CHECK64-NEXT: add a5, a6, a5
-; CHECK64-NEXT: add a5, sp, a5
-; CHECK64-NEXT: addi a5, a5, 16
-; CHECK64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
-; CHECK64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; CHECK64-NEXT: vmfeq.vv v24, v8, v16, v0.t
; CHECK64-NEXT: vl8re64.v v8, (a1)
; CHECK64-NEXT: csrr a1, vlenb
+; CHECK64-NEXT: slli a6, a1, 3
+; CHECK64-NEXT: add a1, a6, a1
; CHECK64-NEXT: add a1, sp, a1
; CHECK64-NEXT: addi a1, a1, 16
; CHECK64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; CHECK64-NEXT: vmv1r.v v0, v7
+; CHECK64-NEXT: csrr a1, vlenb
+; CHECK64-NEXT: mv a6, a1
+; CHECK64-NEXT: slli a1, a1, 3
+; CHECK64-NEXT: add a6, a6, a1
+; CHECK64-NEXT: slli a1, a1, 1
+; CHECK64-NEXT: add a1, a1, a6
+; CHECK64-NEXT: add a1, sp, a1
+; CHECK64-NEXT: addi a1, a1, 16
+; CHECK64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; CHECK64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; CHECK64-NEXT: vmfeq.vv v24, v8, v16, v0.t
; CHECK64-NEXT: vl8re64.v v8, (a4)
+; CHECK64-NEXT: csrr a1, vlenb
+; CHECK64-NEXT: add a1, sp, a1
+; CHECK64-NEXT: addi a1, a1, 16
+; CHECK64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; CHECK64-NEXT: vl8re64.v v8, (a5)
; CHECK64-NEXT: sub a1, s1, a2
; CHECK64-NEXT: sltu a2, s1, a1
; CHECK64-NEXT: vl8re64.v v16, (s2)
@@ -5122,8 +5155,11 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK64-NEXT: vsetvli zero, s4, e8, mf2, tu, ma
; CHECK64-NEXT: vslideup.vx v24, v5, a0
; CHECK64-NEXT: csrr a1, vlenb
-; CHECK64-NEXT: slli a2, a1, 4
-; CHECK64-NEXT: add a1, a2, a1
+; CHECK64-NEXT: mv a2, a1
+; CHECK64-NEXT: slli a1, a1, 3
+; CHECK64-NEXT: add a2, a2, a1
+; CHECK64-NEXT: slli a1, a1, 1
+; CHECK64-NEXT: add a1, a1, a2
; CHECK64-NEXT: add a1, sp, a1
; CHECK64-NEXT: addi a1, a1, 16
; CHECK64-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
@@ -5132,7 +5168,7 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK64-NEXT: # %bb.5:
; CHECK64-NEXT: mv a1, s0
; CHECK64-NEXT: .LBB257_6:
-; CHECK64-NEXT: vmv1r.v v0, v7
+; CHECK64-NEXT: vmv1r.v v0, v25
; CHECK64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK64-NEXT: vmfeq.vv v24, v16, v8, v0.t
; CHECK64-NEXT: addi a1, sp, 16
@@ -5140,8 +5176,11 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK64-NEXT: li a1, 3
; CHECK64-NEXT: call __muldi3
; CHECK64-NEXT: csrr a1, vlenb
-; CHECK64-NEXT: slli a2, a1, 4
-; CHECK64-NEXT: add a1, a2, a1
+; CHECK64-NEXT: mv a2, a1
+; CHECK64-NEXT: slli a1, a1, 3
+; CHECK64-NEXT: add a2, a2, a1
+; CHECK64-NEXT: slli a1, a1, 1
+; CHECK64-NEXT: add a1, a1, a2
; CHECK64-NEXT: add a1, sp, a1
; CHECK64-NEXT: addi a1, a1, 16
; CHECK64-NEXT: vl1r.v v9, (a1) # vscale x 8-byte Folded Reload
@@ -5154,11 +5193,8 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK64-NEXT: addi a2, a2, -1
; CHECK64-NEXT: and a1, a2, a1
; CHECK64-NEXT: csrr a2, vlenb
-; CHECK64-NEXT: mv a3, a2
-; CHECK64-NEXT: slli a2, a2, 3
-; CHECK64-NEXT: add a3, a3, a2
-; CHECK64-NEXT: slli a2, a2, 1
-; CHECK64-NEXT: add a2, a2, a3
+; CHECK64-NEXT: slli a3, a2, 4
+; CHECK64-NEXT: add a2, a3, a2
; CHECK64-NEXT: add a2, sp, a2
; CHECK64-NEXT: addi a2, a2, 16
; CHECK64-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
@@ -5178,12 +5214,8 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK64-NEXT: vslideup.vx v9, v8, a0
; CHECK64-NEXT: vmv1r.v v0, v9
; CHECK64-NEXT: csrr a0, vlenb
-; CHECK64-NEXT: slli a0, a0, 1
-; CHECK64-NEXT: mv a1, a0
-; CHECK64-NEXT: slli a0, a0, 2
-; CHECK64-NEXT: add a1, a1, a0
-; CHECK64-NEXT: slli a0, a0, 1
-; CHECK64-NEXT: add a0, a0, a1
+; CHECK64-NEXT: slli a1, a0, 5
+; CHECK64-NEXT: add a0, a1, a0
; CHECK64-NEXT: add sp, sp, a0
; CHECK64-NEXT: .cfi_def_cfa sp, 64
; CHECK64-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
index 5de9b5550035f..2dd99a820b8d3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
@@ -1078,16 +1078,16 @@ define <vscale x 128 x i1> @icmp_eq_vv_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: sub a4, a3, a1
-; CHECK-NEXT: vl8r.v v24, (a2)
-; CHECK-NEXT: sltu a2, a3, a4
+; CHECK-NEXT: add a4, a0, a1
+; CHECK-NEXT: sub a5, a3, a1
+; CHECK-NEXT: vl8r.v v24, (a4)
+; CHECK-NEXT: sltu a4, a3, a5
+; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vl8r.v v8, (a0)
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a4
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a4, a4, a5
+; CHECK-NEXT: vsetvli zero, a4, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vv v7, v16, v24, v0.t
; CHECK-NEXT: bltu a3, a1, .LBB96_2
; CHECK-NEXT: # %bb.1:
@@ -1116,18 +1116,18 @@ define <vscale x 128 x i1> @icmp_eq_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: sub a3, a2, a1
-; CHECK-NEXT: sltu a4, a2, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
-; CHECK-NEXT: bltu a2, a1, .LBB97_2
+; CHECK-NEXT: bltu a2, a3, .LBB97_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB97_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -1146,18 +1146,18 @@ define <vscale x 128 x i1> @icmp_eq_vx_swap_nxv128i8(<vscale x 128 x i8> %va, i8
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: sub a3, a2, a1
-; CHECK-NEXT: sltu a4, a2, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
-; CHECK-NEXT: bltu a2, a1, .LBB98_2
+; CHECK-NEXT: bltu a2, a3, .LBB98_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB98_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -2250,13 +2250,13 @@ define <vscale x 32 x i1> @icmp_eq_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b,
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: srli a2, a3, 2
; CHECK-NEXT: slli a3, a3, 1
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a4, a1, a3
; CHECK-NEXT: sltu a5, a1, a4
; CHECK-NEXT: addi a5, a5, -1
; CHECK-NEXT: and a4, a5, a4
+; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a3, .LBB190_2
@@ -2282,13 +2282,13 @@ define <vscale x 32 x i1> @icmp_eq_vx_swap_nxv32i32(<vscale x 32 x i32> %va, i32
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: srli a2, a3, 2
; CHECK-NEXT: slli a3, a3, 1
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a4, a1, a3
; CHECK-NEXT: sltu a5, a1, a4
; CHECK-NEXT: addi a5, a5, -1
; CHECK-NEXT: and a4, a5, a4
+; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a3, .LBB191_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll b/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
index 16f373e148bbf..8f519a1d5f7b1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
@@ -709,12 +709,12 @@ define <vscale x 16 x double> @strided_load_nxv17f64(ptr %ptr, i64 %stride, <vsc
; CHECK-RV32-NEXT: .LBB57_4:
; CHECK-RV32-NEXT: mul t1, a5, a1
; CHECK-RV32-NEXT: srli t2, a2, 3
-; CHECK-RV32-NEXT: sub a7, a3, a7
; CHECK-RV32-NEXT: add t1, a0, t1
; CHECK-RV32-NEXT: vsetvli t3, zero, e8, mf4, ta, ma
; CHECK-RV32-NEXT: vslidedown.vx v0, v9, t2
; CHECK-RV32-NEXT: vsetvli zero, t0, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v16, (t1), a1, v0.t
+; CHECK-RV32-NEXT: sub a7, a3, a7
; CHECK-RV32-NEXT: sltu a3, a3, a7
; CHECK-RV32-NEXT: addi a3, a3, -1
; CHECK-RV32-NEXT: and a3, a3, a7
@@ -757,12 +757,12 @@ define <vscale x 16 x double> @strided_load_nxv17f64(ptr %ptr, i64 %stride, <vsc
; CHECK-RV64-NEXT: .LBB57_4:
; CHECK-RV64-NEXT: mul t1, a5, a1
; CHECK-RV64-NEXT: srli t2, a4, 3
-; CHECK-RV64-NEXT: sub a7, a2, a7
; CHECK-RV64-NEXT: add t1, a0, t1
; CHECK-RV64-NEXT: vsetvli t3, zero, e8, mf4, ta, ma
; CHECK-RV64-NEXT: vslidedown.vx v0, v9, t2
; CHECK-RV64-NEXT: vsetvli zero, t0, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v16, (t1), a1, v0.t
+; CHECK-RV64-NEXT: sub a7, a2, a7
; CHECK-RV64-NEXT: sltu a2, a2, a7
; CHECK-RV64-NEXT: addi a2, a2, -1
; CHECK-RV64-NEXT: and a2, a2, a7
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
index f850fb822507c..eda4c53e32478 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
@@ -547,18 +547,18 @@ define <vscale x 128 x i8> @vadd_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub a2, a1, a0
-; CHECK-NEXT: sltu a3, a1, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-NEXT: sltu a0, a1, a3
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a3
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t
-; CHECK-NEXT: bltu a1, a0, .LBB50_2
+; CHECK-NEXT: bltu a1, a2, .LBB50_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
@@ -1299,17 +1299,17 @@ define <vscale x 16 x i32> @vadd_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va, i
define <vscale x 32 x i32> @vadd_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vadd_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB118_2
; CHECK-NEXT: # %bb.1:
@@ -1368,15 +1368,15 @@ define <vscale x 32 x i32> @vadd_vi_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, <v
; RV64-LABEL: vadd_vi_nxv32i32_evl_nx8:
; RV64: # %bb.0:
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: srli a2, a0, 2
; RV64-NEXT: slli a1, a0, 1
-; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
-; RV64-NEXT: vslidedown.vx v0, v0, a2
; RV64-NEXT: sub a2, a0, a1
; RV64-NEXT: sltu a3, a0, a2
; RV64-NEXT: addi a3, a3, -1
; RV64-NEXT: and a2, a3, a2
+; RV64-NEXT: srli a3, a0, 2
+; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV64-NEXT: vadd.vi v16, v16, -1, v0.t
; RV64-NEXT: bltu a0, a1, .LBB120_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
index 93a626e355a6b..69574cc56742b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
@@ -101,16 +101,13 @@ define {<4 x i64>, <4 x i64>} @vector_deinterleave_v4i64_v8i64(<8 x i64> %vec) {
; V-NEXT: vmv.v.i v0, 8
; V-NEXT: vsetivli zero, 4, e64, m4, ta, ma
; V-NEXT: vslidedown.vi v12, v8, 4
-; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; V-NEXT: vmv.v.i v17, 2
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; V-NEXT: vslideup.vi v10, v12, 2
; V-NEXT: vslideup.vi v10, v12, 1, v0.t
; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; V-NEXT: vmv.v.i v18, 12
+; V-NEXT: vmv.v.i v0, 2
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; V-NEXT: vslidedown.vi v14, v8, 1
-; V-NEXT: vmv1r.v v0, v17
; V-NEXT: vslidedown.vi v14, v8, 2, v0.t
; V-NEXT: vslidedown.vi v8, v8, 1, v0.t
; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
@@ -118,7 +115,9 @@ define {<4 x i64>, <4 x i64>} @vector_deinterleave_v4i64_v8i64(<8 x i64> %vec) {
; V-NEXT: vmv2r.v v16, v12
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; V-NEXT: vslideup.vi v16, v12, 1, v0.t
-; V-NEXT: vmv1r.v v0, v18
+; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; V-NEXT: vmv.v.i v0, 12
+; V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; V-NEXT: vmerge.vvm v8, v8, v10, v0
; V-NEXT: vmerge.vvm v10, v14, v16, v0
; V-NEXT: ret
@@ -483,16 +482,13 @@ define {<4 x double>, <4 x double>} @vector_deinterleave_v4f64_v8f64(<8 x double
; V-NEXT: vmv.v.i v0, 8
; V-NEXT: vsetivli zero, 4, e64, m4, ta, ma
; V-NEXT: vslidedown.vi v12, v8, 4
-; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; V-NEXT: vmv.v.i v17, 2
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; V-NEXT: vslideup.vi v10, v12, 2
; V-NEXT: vslideup.vi v10, v12, 1, v0.t
; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; V-NEXT: vmv.v.i v18, 12
+; V-NEXT: vmv.v.i v0, 2
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; V-NEXT: vslidedown.vi v14, v8, 1
-; V-NEXT: vmv1r.v v0, v17
; V-NEXT: vslidedown.vi v14, v8, 2, v0.t
; V-NEXT: vslidedown.vi v8, v8, 1, v0.t
; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
@@ -500,7 +496,9 @@ define {<4 x double>, <4 x double>} @vector_deinterleave_v4f64_v8f64(<8 x double
; V-NEXT: vmv2r.v v16, v12
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; V-NEXT: vslideup.vi v16, v12, 1, v0.t
-; V-NEXT: vmv1r.v v0, v18
+; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; V-NEXT: vmv.v.i v0, 12
+; V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; V-NEXT: vmerge.vvm v8, v8, v10, v0
; V-NEXT: vmerge.vvm v10, v14, v16, v0
; V-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
index 5d39739d8d1f6..afe18a9581ea5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
@@ -188,8 +188,8 @@ define {<vscale x 64 x i1>, <vscale x 64 x i1>} @vector_deinterleave_nxv64i1_nxv
; ZIP: # %bb.0:
; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZIP-NEXT: vmv1r.v v24, v0
-; ZIP-NEXT: vmv.v.i v16, 0
; ZIP-NEXT: vmv1r.v v0, v8
+; ZIP-NEXT: vmv.v.i v16, 0
; ZIP-NEXT: vmerge.vim v8, v16, 1, v0
; ZIP-NEXT: vmv1r.v v0, v24
; ZIP-NEXT: vmerge.vim v24, v16, 1, v0
@@ -357,19 +357,18 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} @vector_dein
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: vmerge.vim v8, v12, 1, v0
+; CHECK-NEXT: vmv1r.v v14, v0
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v10, v0, a1
+; CHECK-NEXT: vslidedown.vx v0, v0, a1
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v10, v12, 1, v0
; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v8, v12, 1, v0
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v14, v0, a0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vslidedown.vx v0, v14, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v10, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: vlseg3e8.v v8, (a1)
@@ -476,32 +475,30 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: sub sp, sp, a0
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v9, v0, a2
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: vmv.v.v v0, v9
-; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v14, v10, 1, v0
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: srli a0, a0, 1
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v12, v10, 1, v0
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v16, v8, a1
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a1
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
-; CHECK-NEXT: vs8r.v v8, (a2)
-; CHECK-NEXT: vlseg4e8.v v8, (a2)
+; CHECK-NEXT: vs8r.v v8, (a0)
+; CHECK-NEXT: vlseg4e8.v v8, (a0)
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmsne.vi v8, v10, 0
; CHECK-NEXT: vmsne.vi v9, v12, 0
@@ -603,36 +600,39 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v24, v12, 1, v0
; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: srli a2, a0, 1
; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vmerge.vim v14, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v8, v9
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v10, v9, a1
-; CHECK-NEXT: vslidedown.vx v9, v9, a2
-; CHECK-NEXT: sub a0, a0, a1
-; CHECK-NEXT: vslidedown.vx v0, v8, a0
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vmerge.vim v8, v12, 1, v0
+; CHECK-NEXT: vmv1r.v v16, v0
+; CHECK-NEXT: srli a1, a0, 2
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a1
+; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v10, v12, 1, v0
+; CHECK-NEXT: sub a1, a0, a1
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v16, a1
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v20, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmerge.vim v26, v12, 1, v0
+; CHECK-NEXT: srli a0, a0, 1
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v16, a0
; CHECK-NEXT: vmv1r.v v18, v21
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v28, v12, 1, v0
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
; CHECK-NEXT: vmv1r.v v19, v14
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vmv1r.v v16, v29
+; CHECK-NEXT: vmv1r.v v16, v13
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vmv1r.v v17, v20
-; CHECK-NEXT: vs8r.v v24, (a0)
+; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v20, v15
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
@@ -834,40 +834,39 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v14, 0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v16, v14, 1, v0
+; CHECK-NEXT: vmerge.vim v24, v14, 1, v0
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: srli a2, a0, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a1
-; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v18, v14, 1, v0
+; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v26, v14, 1, v0
+; CHECK-NEXT: srli a2, a0, 1
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v9, a2
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: sub a0, a0, a1
-; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
+; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v28, v14, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v12, v8, a1
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs8r.v v16, (a2)
-; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v10, v14, 1, v0
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmerge.vim v18, v14, 1, v0
+; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v9, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v8, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmerge.vim v12, v14, 1, v0
-; CHECK-NEXT: vs8r.v v8, (a1)
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vlseg6e8.v v16, (a2)
-; CHECK-NEXT: vlseg6e8.v v10, (a1)
+; CHECK-NEXT: vmerge.vim v16, v14, 1, v0
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs8r.v v24, (a0)
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v8, a1
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
+; CHECK-NEXT: vs8r.v v16, (a2)
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vlseg6e8.v v16, (a0)
+; CHECK-NEXT: vlseg6e8.v v10, (a2)
; CHECK-NEXT: vmv2r.v v8, v16
; CHECK-NEXT: vmv2r.v v22, v18
; CHECK-NEXT: vmv2r.v v24, v20
@@ -1065,51 +1064,50 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vmv1r.v v17, v8
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vmv.v.i v20, 0
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: srli a0, a1, 1
-; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: srli a1, a0, 2
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v8, a1
+; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v22, v20, 1, v0
-; CHECK-NEXT: sub a1, a1, a2
+; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a1
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v9, a2
+; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v14, v20, 1, v0
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a0
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: srli a0, a0, 1
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v9, a0
+; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v12, v20, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v10, v8, a2
-; CHECK-NEXT: vmv1r.v v18, v23
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v24, v20, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmerge.vim v8, v20, 1, v0
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v17, a2
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a1
+; CHECK-NEXT: vmv1r.v v18, v25
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v24, v20, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vim v10, v20, 1, v0
-; CHECK-NEXT: vmv1r.v v19, v24
+; CHECK-NEXT: vmv1r.v v19, v22
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vmv1r.v v16, v15
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v17, a0
-; CHECK-NEXT: vmv1r.v v17, v22
+; CHECK-NEXT: vmv1r.v v17, v24
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v22, v20, 1, v0
-; CHECK-NEXT: vmv1r.v v20, v25
+; CHECK-NEXT: vmerge.vim v24, v20, 1, v0
+; CHECK-NEXT: vmv1r.v v20, v23
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vmv1r.v v21, v22
+; CHECK-NEXT: vmv1r.v v21, v24
; CHECK-NEXT: vs8r.v v8, (a1)
-; CHECK-NEXT: vmv1r.v v22, v23
+; CHECK-NEXT: vmv1r.v v22, v25
; CHECK-NEXT: vs8r.v v16, (a0)
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vlseg7e8.v v8, (a1)
@@ -1339,50 +1337,48 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: srli a3, a1, 1
-; CHECK-NEXT: sub a1, a1, a2
-; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a1
-; CHECK-NEXT: vsetvli a4, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v30, v16, 1, v0
-; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v9, a3
-; CHECK-NEXT: vsetvli a4, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v28, v16, 1, v0
-; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v10, v8, a3
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vsetvli a4, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
-; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v9, a2
-; CHECK-NEXT: vsetvli a4, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v26, v16, 1, v0
-; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.v.i v18, 0
+; CHECK-NEXT: srli a0, a1, 2
+; CHECK-NEXT: sub a2, a1, a0
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v30, v18, 1, v0
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v8, a2
+; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v22, v18, 1, v0
+; CHECK-NEXT: srli a1, a1, 1
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v9, a1
+; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v28, v18, 1, v0
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, a1
-; CHECK-NEXT: vs8r.v v24, (a0)
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v14, v16, 1, v0
+; CHECK-NEXT: vmerge.vim v20, v18, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vmerge.vim v24, v18, 1, v0
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v11, v8, a2
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vslidedown.vx v0, v9, a0
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v12, v16, 1, v0
+; CHECK-NEXT: vmerge.vim v26, v18, 1, v0
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vs8r.v v24, (a1)
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: vmerge.vim v10, v16, 1, v0
-; CHECK-NEXT: vs8r.v v8, (a3)
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vlseg8e8.v v18, (a0)
-; CHECK-NEXT: vlseg8e8.v v10, (a3)
+; CHECK-NEXT: vmerge.vim v16, v18, 1, v0
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v8, a0
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v18, v18, 1, v0
+; CHECK-NEXT: vs8r.v v16, (a2)
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vlseg8e8.v v18, (a1)
+; CHECK-NEXT: vlseg8e8.v v10, (a2)
; CHECK-NEXT: vmv2r.v v8, v18
; CHECK-NEXT: vmv2r.v v26, v20
; CHECK-NEXT: vmv2r.v v28, v22
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
index fdf5a42f93502..c2d053b736305 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
@@ -10,13 +10,13 @@ define void @vector_interleave_store_nxv32i1_nxv16i1(<vscale x 16 x i1> %a, <vsc
; CHECK-LABEL: vector_interleave_store_nxv32i1_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: li a1, -1
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v12, v10, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v14, v10, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v12, v8, 1, v0
+; CHECK-NEXT: li a1, -1
+; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vim v14, v8, 1, v0
; CHECK-NEXT: vwaddu.vv v8, v14, v12
; CHECK-NEXT: vwmaccu.vx v8, a1, v12
; CHECK-NEXT: csrr a1, vlenb
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
index 24a61471a8a26..84558183dbf64 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
@@ -13,13 +13,13 @@ define <vscale x 32 x i1> @vector_interleave_nxv32i1_nxv16i1(<vscale x 16 x i1>
; V-LABEL: vector_interleave_nxv32i1_nxv16i1:
; V: # %bb.0:
; V-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; V-NEXT: vmv1r.v v9, v0
-; V-NEXT: vmv.v.i v10, 0
-; V-NEXT: li a0, -1
+; V-NEXT: vmv1r.v v10, v0
; V-NEXT: vmv1r.v v0, v8
-; V-NEXT: vmerge.vim v12, v10, 1, v0
-; V-NEXT: vmv1r.v v0, v9
-; V-NEXT: vmerge.vim v14, v10, 1, v0
+; V-NEXT: vmv.v.i v8, 0
+; V-NEXT: vmerge.vim v12, v8, 1, v0
+; V-NEXT: li a0, -1
+; V-NEXT: vmv1r.v v0, v10
+; V-NEXT: vmerge.vim v14, v8, 1, v0
; V-NEXT: vwaddu.vv v8, v14, v12
; V-NEXT: vwmaccu.vx v8, a0, v12
; V-NEXT: csrr a0, vlenb
@@ -34,10 +34,10 @@ define <vscale x 32 x i1> @vector_interleave_nxv32i1_nxv16i1(<vscale x 16 x i1>
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; ZVBB-NEXT: vmv1r.v v14, v0
-; ZVBB-NEXT: vmv.v.i v10, 0
-; ZVBB-NEXT: li a0, 1
; ZVBB-NEXT: vmv1r.v v0, v8
-; ZVBB-NEXT: vmerge.vim v12, v10, 1, v0
+; ZVBB-NEXT: vmv.v.i v8, 0
+; ZVBB-NEXT: vmerge.vim v12, v8, 1, v0
+; ZVBB-NEXT: li a0, 1
; ZVBB-NEXT: vwsll.vi v8, v12, 8
; ZVBB-NEXT: vmv1r.v v0, v14
; ZVBB-NEXT: vwaddu.wx v8, v8, a0, v0.t
@@ -52,13 +52,13 @@ define <vscale x 32 x i1> @vector_interleave_nxv32i1_nxv16i1(<vscale x 16 x i1>
; ZIP-LABEL: vector_interleave_nxv32i1_nxv16i1:
; ZIP: # %bb.0:
; ZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; ZIP-NEXT: vmv1r.v v9, v0
-; ZIP-NEXT: vmv.v.i v12, 0
-; ZIP-NEXT: csrr a0, vlenb
+; ZIP-NEXT: vmv1r.v v12, v0
; ZIP-NEXT: vmv1r.v v0, v8
-; ZIP-NEXT: vmerge.vim v10, v12, 1, v0
-; ZIP-NEXT: vmv1r.v v0, v9
-; ZIP-NEXT: vmerge.vim v8, v12, 1, v0
+; ZIP-NEXT: vmv.v.i v8, 0
+; ZIP-NEXT: vmerge.vim v10, v8, 1, v0
+; ZIP-NEXT: csrr a0, vlenb
+; ZIP-NEXT: vmv1r.v v0, v12
+; ZIP-NEXT: vmerge.vim v8, v8, 1, v0
; ZIP-NEXT: ri.vzip2b.vv v12, v8, v10
; ZIP-NEXT: ri.vzip2a.vv v14, v8, v10
; ZIP-NEXT: vmsne.vi v8, v12, 0
@@ -217,21 +217,21 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv64i1(<vscale x 64 x i1
; V: # %bb.0:
; V-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; V-NEXT: vmv1r.v v24, v0
-; V-NEXT: vmv.v.i v16, 0
-; V-NEXT: li a0, -1
; V-NEXT: vmv1r.v v0, v8
+; V-NEXT: vmv.v.i v16, 0
; V-NEXT: vmerge.vim v8, v16, 1, v0
+; V-NEXT: li a0, -1
; V-NEXT: vmv1r.v v0, v24
-; V-NEXT: vmerge.vim v16, v16, 1, v0
+; V-NEXT: vmerge.vim v24, v16, 1, v0
; V-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; V-NEXT: vwaddu.vv v24, v16, v8
-; V-NEXT: vmv4r.v v4, v20
-; V-NEXT: vwaddu.vv v16, v4, v12
-; V-NEXT: vwmaccu.vx v24, a0, v8
-; V-NEXT: vwmaccu.vx v16, a0, v12
+; V-NEXT: vwaddu.vv v16, v24, v8
+; V-NEXT: vwaddu.vv v0, v28, v12
+; V-NEXT: vwmaccu.vx v16, a0, v8
+; V-NEXT: vwmaccu.vx v0, a0, v12
; V-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; V-NEXT: vmsne.vi v0, v24, 0
-; V-NEXT: vmsne.vi v8, v16, 0
+; V-NEXT: vmsne.vi v9, v16, 0
+; V-NEXT: vmsne.vi v8, v0, 0
+; V-NEXT: vmv1r.v v0, v9
; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv128i1_nxv64i1:
@@ -257,8 +257,8 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv64i1(<vscale x 64 x i1
; ZIP: # %bb.0:
; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZIP-NEXT: vmv1r.v v24, v0
-; ZIP-NEXT: vmv.v.i v16, 0
; ZIP-NEXT: vmv1r.v v0, v8
+; ZIP-NEXT: vmv.v.i v16, 0
; ZIP-NEXT: vmerge.vim v8, v16, 1, v0
; ZIP-NEXT: vmv1r.v v0, v24
; ZIP-NEXT: vmerge.vim v16, v16, 1, v0
@@ -492,14 +492,14 @@ define <vscale x 48 x i1> @vector_interleave_nxv48i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vmv.v.i v14, 0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmv.v.i v14, 0
; CHECK-NEXT: vmerge.vim v12, v14, 1, v0
-; CHECK-NEXT: slli a2, a1, 1
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vim v10, v14, 1, v0
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a2, a1, 1
; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmerge.vim v14, v14, 1, v0
@@ -533,14 +533,14 @@ define <vscale x 48 x i1> @vector_interleave_nxv48i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmv1r.v v10, v0
-; ZVBB-NEXT: vmv.v.i v14, 0
-; ZVBB-NEXT: addi a0, sp, 16
-; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: vmv1r.v v0, v8
+; ZVBB-NEXT: vmv.v.i v14, 0
; ZVBB-NEXT: vmerge.vim v12, v14, 1, v0
-; ZVBB-NEXT: slli a2, a1, 1
; ZVBB-NEXT: vmv1r.v v0, v10
; ZVBB-NEXT: vmerge.vim v10, v14, 1, v0
+; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a1, vlenb
+; ZVBB-NEXT: slli a2, a1, 1
; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vmv1r.v v0, v9
; ZVBB-NEXT: vmerge.vim v14, v14, 1, v0
@@ -789,17 +789,17 @@ define <vscale x 64 x i1> @vector_interleave_nxv64i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv.v.i v18, 0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmv.v.i v18, 0
; CHECK-NEXT: vmerge.vim v14, v18, 1, v0
-; CHECK-NEXT: slli a2, a1, 1
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmerge.vim v12, v18, 1, v0
-; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmerge.vim v16, v18, 1, v0
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: add a4, a3, a2
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vim v18, v18, 1, v0
@@ -834,17 +834,17 @@ define <vscale x 64 x i1> @vector_interleave_nxv64i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmv1r.v v11, v0
-; ZVBB-NEXT: vmv.v.i v18, 0
-; ZVBB-NEXT: addi a0, sp, 16
-; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: vmv1r.v v0, v8
+; ZVBB-NEXT: vmv.v.i v18, 0
; ZVBB-NEXT: vmerge.vim v14, v18, 1, v0
-; ZVBB-NEXT: slli a2, a1, 1
; ZVBB-NEXT: vmv1r.v v0, v11
; ZVBB-NEXT: vmerge.vim v12, v18, 1, v0
-; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vmv1r.v v0, v9
; ZVBB-NEXT: vmerge.vim v16, v18, 1, v0
+; ZVBB-NEXT: addi a0, sp, 16
+; ZVBB-NEXT: csrr a1, vlenb
+; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: add a4, a3, a2
; ZVBB-NEXT: vmv1r.v v0, v10
; ZVBB-NEXT: vmerge.vim v18, v18, 1, v0
@@ -1092,7 +1092,15 @@ define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmv.v.i v14, 0
+; CHECK-NEXT: vmerge.vim v24, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vim v22, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vim v12, v14, 1, v0
+; CHECK-NEXT: vmv4r.v v16, v24
+; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vmerge.vim v26, v14, 1, v0
; CHECK-NEXT: addi a4, sp, 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 2
@@ -1100,28 +1108,20 @@ define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vmerge.vim v22, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v14, v12, 1, v0
-; CHECK-NEXT: vmv2r.v v16, v22
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v24, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmerge.vim v20, v12, 1, v0
; CHECK-NEXT: add a2, a4, a1
-; CHECK-NEXT: vmv1r.v v17, v14
+; CHECK-NEXT: vmv1r.v v17, v22
; CHECK-NEXT: srli a3, a1, 1
-; CHECK-NEXT: vmv1r.v v18, v24
-; CHECK-NEXT: vmv1r.v v24, v15
+; CHECK-NEXT: vmv1r.v v18, v26
+; CHECK-NEXT: vmv1r.v v26, v23
; CHECK-NEXT: add a5, a2, a1
-; CHECK-NEXT: vmv1r.v v19, v20
-; CHECK-NEXT: vmv1r.v v26, v21
+; CHECK-NEXT: vmv1r.v v19, v12
+; CHECK-NEXT: vmv1r.v v28, v13
; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: vmerge.vim v20, v12, 1, v0
+; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
; CHECK-NEXT: vsetvli a6, zero, e8, m1, ta, ma
; CHECK-NEXT: vsseg5e8.v v16, (a4)
-; CHECK-NEXT: vmv1r.v v27, v21
-; CHECK-NEXT: vsseg5e8.v v23, (a0)
+; CHECK-NEXT: vmv1r.v v29, v21
+; CHECK-NEXT: vsseg5e8.v v25, (a0)
; CHECK-NEXT: vl1r.v v8, (a5)
; CHECK-NEXT: add a5, a5, a1
; CHECK-NEXT: vl1r.v v10, (a4)
@@ -1166,7 +1166,15 @@ define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: mul a0, a0, a1
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; ZVBB-NEXT: vmv.v.i v12, 0
+; ZVBB-NEXT: vmv.v.i v14, 0
+; ZVBB-NEXT: vmerge.vim v24, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v8
+; ZVBB-NEXT: vmerge.vim v22, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v10
+; ZVBB-NEXT: vmerge.vim v12, v14, 1, v0
+; ZVBB-NEXT: vmv4r.v v16, v24
+; ZVBB-NEXT: vmv1r.v v0, v9
+; ZVBB-NEXT: vmerge.vim v26, v14, 1, v0
; ZVBB-NEXT: addi a4, sp, 16
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 2
@@ -1174,28 +1182,20 @@ define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: add a0, sp, a0
; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: vmerge.vim v22, v12, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v8
-; ZVBB-NEXT: vmerge.vim v14, v12, 1, v0
-; ZVBB-NEXT: vmv2r.v v16, v22
-; ZVBB-NEXT: vmv1r.v v0, v9
-; ZVBB-NEXT: vmerge.vim v24, v12, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v10
-; ZVBB-NEXT: vmerge.vim v20, v12, 1, v0
; ZVBB-NEXT: add a2, a4, a1
-; ZVBB-NEXT: vmv1r.v v17, v14
+; ZVBB-NEXT: vmv1r.v v17, v22
; ZVBB-NEXT: srli a3, a1, 1
-; ZVBB-NEXT: vmv1r.v v18, v24
-; ZVBB-NEXT: vmv1r.v v24, v15
+; ZVBB-NEXT: vmv1r.v v18, v26
+; ZVBB-NEXT: vmv1r.v v26, v23
; ZVBB-NEXT: add a5, a2, a1
-; ZVBB-NEXT: vmv1r.v v19, v20
-; ZVBB-NEXT: vmv1r.v v26, v21
+; ZVBB-NEXT: vmv1r.v v19, v12
+; ZVBB-NEXT: vmv1r.v v28, v13
; ZVBB-NEXT: vmv1r.v v0, v11
-; ZVBB-NEXT: vmerge.vim v20, v12, 1, v0
+; ZVBB-NEXT: vmerge.vim v20, v14, 1, v0
; ZVBB-NEXT: vsetvli a6, zero, e8, m1, ta, ma
; ZVBB-NEXT: vsseg5e8.v v16, (a4)
-; ZVBB-NEXT: vmv1r.v v27, v21
-; ZVBB-NEXT: vsseg5e8.v v23, (a0)
+; ZVBB-NEXT: vmv1r.v v29, v21
+; ZVBB-NEXT: vsseg5e8.v v25, (a0)
; ZVBB-NEXT: vl1r.v v8, (a5)
; ZVBB-NEXT: add a5, a5, a1
; ZVBB-NEXT: vl1r.v v10, (a4)
@@ -2312,64 +2312,62 @@ define <vscale x 96 x i1> @vector_interleave_nxv96i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv1r.v v13, v12
-; CHECK-NEXT: vmv1r.v v12, v11
-; CHECK-NEXT: vmv1r.v v11, v10
-; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vmv1r.v v16, v8
+; CHECK-NEXT: vmv1r.v v12, v9
+; CHECK-NEXT: vmv1r.v v17, v8
; CHECK-NEXT: vmv.v.i v14, 0
+; CHECK-NEXT: vmerge.vim v8, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmerge.vim v24, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmerge.vim v22, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vim v16, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vmerge.vim v18, v14, 1, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a0, 6
; CHECK-NEXT: mul a1, a1, a0
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vmv1r.v v10, v25
+; CHECK-NEXT: addi a5, sp, 16
+; CHECK-NEXT: vmv1r.v v11, v23
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v8, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: vmerge.vim v18, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v10, v19
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: vmerge.vim v22, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v11, v21
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmerge.vim v24, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v12, v23
+; CHECK-NEXT: vmv1r.v v12, v17
; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: vmerge.vim v16, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v13, v25
-; CHECK-NEXT: add a3, a1, a0
-; CHECK-NEXT: vmv1r.v v14, v17
-; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v13, v19
+; CHECK-NEXT: add a2, a1, a0
+; CHECK-NEXT: vmv1r.v v14, v21
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vsseg6e8.v v9, (a1)
-; CHECK-NEXT: vmv1r.v v9, v18
-; CHECK-NEXT: add a5, a2, a0
-; CHECK-NEXT: vmv1r.v v10, v20
-; CHECK-NEXT: srli a4, a0, 1
-; CHECK-NEXT: vmv1r.v v11, v22
-; CHECK-NEXT: add a6, a5, a0
-; CHECK-NEXT: vmv1r.v v12, v24
-; CHECK-NEXT: add a7, a3, a0
-; CHECK-NEXT: vmv1r.v v13, v16
-; CHECK-NEXT: vsseg6e8.v v8, (a2)
+; CHECK-NEXT: vmv1r.v v9, v24
+; CHECK-NEXT: add a4, a5, a0
+; CHECK-NEXT: vmv1r.v v10, v22
+; CHECK-NEXT: srli a3, a0, 1
+; CHECK-NEXT: vmv1r.v v11, v16
+; CHECK-NEXT: add a6, a4, a0
+; CHECK-NEXT: vmv1r.v v12, v18
+; CHECK-NEXT: add a7, a2, a0
+; CHECK-NEXT: vmv1r.v v13, v20
+; CHECK-NEXT: vsseg6e8.v v8, (a5)
; CHECK-NEXT: vl1r.v v8, (a1)
; CHECK-NEXT: add a1, a6, a0
; CHECK-NEXT: vl1r.v v10, (a6)
; CHECK-NEXT: add a6, a7, a0
-; CHECK-NEXT: vl1r.v v12, (a2)
-; CHECK-NEXT: add a2, a1, a0
+; CHECK-NEXT: vl1r.v v12, (a5)
+; CHECK-NEXT: add a5, a1, a0
; CHECK-NEXT: vl1r.v v14, (a7)
; CHECK-NEXT: add a7, a6, a0
-; CHECK-NEXT: vl1r.v v16, (a2)
-; CHECK-NEXT: add a2, a2, a0
+; CHECK-NEXT: vl1r.v v16, (a5)
+; CHECK-NEXT: add a5, a5, a0
; CHECK-NEXT: vl1r.v v18, (a7)
; CHECK-NEXT: add a7, a7, a0
; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: vl1r.v v9, (a3)
-; CHECK-NEXT: vl1r.v v17, (a2)
+; CHECK-NEXT: vl1r.v v9, (a2)
+; CHECK-NEXT: vl1r.v v17, (a5)
; CHECK-NEXT: vl1r.v v11, (a1)
-; CHECK-NEXT: vl1r.v v13, (a5)
+; CHECK-NEXT: vl1r.v v13, (a4)
; CHECK-NEXT: vl1r.v v19, (a7)
; CHECK-NEXT: vl1r.v v15, (a6)
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
@@ -2383,7 +2381,7 @@ define <vscale x 96 x i1> @vector_interleave_nxv96i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: vslideup.vx v9, v20, a0
; CHECK-NEXT: vslideup.vx v0, v16, a0
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslideup.vx v0, v9, a4
+; CHECK-NEXT: vslideup.vx v0, v9, a3
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslideup.vx v8, v10, a0
; CHECK-NEXT: csrr a0, vlenb
@@ -2402,64 +2400,62 @@ define <vscale x 96 x i1> @vector_interleave_nxv96i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmv1r.v v13, v12
-; ZVBB-NEXT: vmv1r.v v12, v11
-; ZVBB-NEXT: vmv1r.v v11, v10
-; ZVBB-NEXT: vmv1r.v v10, v9
-; ZVBB-NEXT: vmv1r.v v16, v8
+; ZVBB-NEXT: vmv1r.v v12, v9
+; ZVBB-NEXT: vmv1r.v v17, v8
; ZVBB-NEXT: vmv.v.i v14, 0
+; ZVBB-NEXT: vmerge.vim v8, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v17
+; ZVBB-NEXT: vmerge.vim v24, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v12
+; ZVBB-NEXT: vmerge.vim v22, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v10
+; ZVBB-NEXT: vmerge.vim v16, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v11
+; ZVBB-NEXT: vmerge.vim v18, v14, 1, v0
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: li a0, 6
; ZVBB-NEXT: mul a1, a1, a0
; ZVBB-NEXT: add a1, sp, a1
; ZVBB-NEXT: addi a1, a1, 16
-; ZVBB-NEXT: addi a2, sp, 16
+; ZVBB-NEXT: vmv1r.v v10, v25
+; ZVBB-NEXT: addi a5, sp, 16
+; ZVBB-NEXT: vmv1r.v v11, v23
; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: vmerge.vim v8, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v16
-; ZVBB-NEXT: vmerge.vim v18, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v10
-; ZVBB-NEXT: vmerge.vim v20, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v10, v19
-; ZVBB-NEXT: vmv1r.v v0, v11
-; ZVBB-NEXT: vmerge.vim v22, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v11, v21
-; ZVBB-NEXT: vmv1r.v v0, v12
-; ZVBB-NEXT: vmerge.vim v24, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v12, v23
+; ZVBB-NEXT: vmv1r.v v12, v17
; ZVBB-NEXT: vmv1r.v v0, v13
-; ZVBB-NEXT: vmerge.vim v16, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v13, v25
-; ZVBB-NEXT: add a3, a1, a0
-; ZVBB-NEXT: vmv1r.v v14, v17
-; ZVBB-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; ZVBB-NEXT: vmerge.vim v20, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v13, v19
+; ZVBB-NEXT: add a2, a1, a0
+; ZVBB-NEXT: vmv1r.v v14, v21
+; ZVBB-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; ZVBB-NEXT: vsseg6e8.v v9, (a1)
-; ZVBB-NEXT: vmv1r.v v9, v18
-; ZVBB-NEXT: add a5, a2, a0
-; ZVBB-NEXT: vmv1r.v v10, v20
-; ZVBB-NEXT: srli a4, a0, 1
-; ZVBB-NEXT: vmv1r.v v11, v22
-; ZVBB-NEXT: add a6, a5, a0
-; ZVBB-NEXT: vmv1r.v v12, v24
-; ZVBB-NEXT: add a7, a3, a0
-; ZVBB-NEXT: vmv1r.v v13, v16
-; ZVBB-NEXT: vsseg6e8.v v8, (a2)
+; ZVBB-NEXT: vmv1r.v v9, v24
+; ZVBB-NEXT: add a4, a5, a0
+; ZVBB-NEXT: vmv1r.v v10, v22
+; ZVBB-NEXT: srli a3, a0, 1
+; ZVBB-NEXT: vmv1r.v v11, v16
+; ZVBB-NEXT: add a6, a4, a0
+; ZVBB-NEXT: vmv1r.v v12, v18
+; ZVBB-NEXT: add a7, a2, a0
+; ZVBB-NEXT: vmv1r.v v13, v20
+; ZVBB-NEXT: vsseg6e8.v v8, (a5)
; ZVBB-NEXT: vl1r.v v8, (a1)
; ZVBB-NEXT: add a1, a6, a0
; ZVBB-NEXT: vl1r.v v10, (a6)
; ZVBB-NEXT: add a6, a7, a0
-; ZVBB-NEXT: vl1r.v v12, (a2)
-; ZVBB-NEXT: add a2, a1, a0
+; ZVBB-NEXT: vl1r.v v12, (a5)
+; ZVBB-NEXT: add a5, a1, a0
; ZVBB-NEXT: vl1r.v v14, (a7)
; ZVBB-NEXT: add a7, a6, a0
-; ZVBB-NEXT: vl1r.v v16, (a2)
-; ZVBB-NEXT: add a2, a2, a0
+; ZVBB-NEXT: vl1r.v v16, (a5)
+; ZVBB-NEXT: add a5, a5, a0
; ZVBB-NEXT: vl1r.v v18, (a7)
; ZVBB-NEXT: add a7, a7, a0
; ZVBB-NEXT: srli a0, a0, 2
-; ZVBB-NEXT: vl1r.v v9, (a3)
-; ZVBB-NEXT: vl1r.v v17, (a2)
+; ZVBB-NEXT: vl1r.v v9, (a2)
+; ZVBB-NEXT: vl1r.v v17, (a5)
; ZVBB-NEXT: vl1r.v v11, (a1)
-; ZVBB-NEXT: vl1r.v v13, (a5)
+; ZVBB-NEXT: vl1r.v v13, (a4)
; ZVBB-NEXT: vl1r.v v19, (a7)
; ZVBB-NEXT: vl1r.v v15, (a6)
; ZVBB-NEXT: vsetvli a1, zero, e8, m2, ta, ma
@@ -2473,7 +2469,7 @@ define <vscale x 96 x i1> @vector_interleave_nxv96i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: vslideup.vx v9, v20, a0
; ZVBB-NEXT: vslideup.vx v0, v16, a0
; ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vslideup.vx v0, v9, a4
+; ZVBB-NEXT: vslideup.vx v0, v9, a3
; ZVBB-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; ZVBB-NEXT: vslideup.vx v8, v10, a0
; ZVBB-NEXT: csrr a0, vlenb
@@ -3667,11 +3663,25 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v28, v13
-; CHECK-NEXT: vmv1r.v v26, v12
-; CHECK-NEXT: vmv1r.v v14, v11
-; CHECK-NEXT: vmv1r.v v15, v10
-; CHECK-NEXT: vmv.v.i v30, 0
+; CHECK-NEXT: vmv1r.v v23, v13
+; CHECK-NEXT: vmv1r.v v13, v11
+; CHECK-NEXT: vmv1r.v v11, v9
+; CHECK-NEXT: vmv1r.v v17, v8
+; CHECK-NEXT: vmv.v.i v14, 0
+; CHECK-NEXT: vmerge.vim v8, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmerge.vim v28, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vim v26, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmerge.vim v24, v14, 1, v0
+; CHECK-NEXT: vmv4r.v v16, v8
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vmerge.vim v10, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v17, v28
+; CHECK-NEXT: vmv1r.v v18, v10
+; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmerge.vim v12, v14, 1, v0
; CHECK-NEXT: addi a3, sp, 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 3
@@ -3679,35 +3689,21 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vmerge.vim v10, v30, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v16, v30, 1, v0
-; CHECK-NEXT: vmv2r.v v18, v10
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v12, v30, 1, v0
-; CHECK-NEXT: vmv1r.v v19, v16
-; CHECK-NEXT: vmv1r.v v0, v15
-; CHECK-NEXT: vmerge.vim v24, v30, 1, v0
-; CHECK-NEXT: vmv1r.v v20, v12
-; CHECK-NEXT: vmv1r.v v0, v14
-; CHECK-NEXT: vmerge.vim v14, v30, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v26
-; CHECK-NEXT: vmerge.vim v26, v30, 1, v0
; CHECK-NEXT: add a2, a3, a1
-; CHECK-NEXT: vmv1r.v v21, v24
+; CHECK-NEXT: vmv1r.v v19, v26
; CHECK-NEXT: add a4, a2, a1
-; CHECK-NEXT: vmv1r.v v22, v14
-; CHECK-NEXT: vmv1r.v v12, v17
+; CHECK-NEXT: vmv1r.v v20, v12
+; CHECK-NEXT: vmv1r.v v10, v29
; CHECK-NEXT: add a5, a4, a1
-; CHECK-NEXT: vmv1r.v v23, v26
+; CHECK-NEXT: vmv1r.v v21, v24
+; CHECK-NEXT: vmv1r.v v12, v27
+; CHECK-NEXT: vmv1r.v v0, v23
+; CHECK-NEXT: vmerge.vim v22, v14, 1, v0
; CHECK-NEXT: vmv1r.v v14, v25
-; CHECK-NEXT: vmv1r.v v0, v28
-; CHECK-NEXT: vmerge.vim v24, v30, 1, v0
-; CHECK-NEXT: vmv1r.v v16, v27
; CHECK-NEXT: vsetvli a6, zero, e8, m1, ta, ma
-; CHECK-NEXT: vsseg7e8.v v18, (a3)
-; CHECK-NEXT: vmv1r.v v17, v25
-; CHECK-NEXT: vsseg7e8.v v11, (a0)
+; CHECK-NEXT: vsseg7e8.v v16, (a3)
+; CHECK-NEXT: vmv1r.v v15, v23
+; CHECK-NEXT: vsseg7e8.v v9, (a0)
; CHECK-NEXT: vl1r.v v8, (a4)
; CHECK-NEXT: add a4, a5, a1
; CHECK-NEXT: vl1r.v v10, (a3)
@@ -3763,11 +3759,25 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; ZVBB-NEXT: mul a0, a0, a1
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; ZVBB-NEXT: vmv1r.v v28, v13
-; ZVBB-NEXT: vmv1r.v v26, v12
-; ZVBB-NEXT: vmv1r.v v14, v11
-; ZVBB-NEXT: vmv1r.v v15, v10
-; ZVBB-NEXT: vmv.v.i v30, 0
+; ZVBB-NEXT: vmv1r.v v23, v13
+; ZVBB-NEXT: vmv1r.v v13, v11
+; ZVBB-NEXT: vmv1r.v v11, v9
+; ZVBB-NEXT: vmv1r.v v17, v8
+; ZVBB-NEXT: vmv.v.i v14, 0
+; ZVBB-NEXT: vmerge.vim v8, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v17
+; ZVBB-NEXT: vmerge.vim v28, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v10
+; ZVBB-NEXT: vmerge.vim v26, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v12
+; ZVBB-NEXT: vmerge.vim v24, v14, 1, v0
+; ZVBB-NEXT: vmv4r.v v16, v8
+; ZVBB-NEXT: vmv1r.v v0, v11
+; ZVBB-NEXT: vmerge.vim v10, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v17, v28
+; ZVBB-NEXT: vmv1r.v v18, v10
+; ZVBB-NEXT: vmv1r.v v0, v13
+; ZVBB-NEXT: vmerge.vim v12, v14, 1, v0
; ZVBB-NEXT: addi a3, sp, 16
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 3
@@ -3775,35 +3785,21 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; ZVBB-NEXT: add a0, sp, a0
; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: vmerge.vim v10, v30, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v8
-; ZVBB-NEXT: vmerge.vim v16, v30, 1, v0
-; ZVBB-NEXT: vmv2r.v v18, v10
-; ZVBB-NEXT: vmv1r.v v0, v9
-; ZVBB-NEXT: vmerge.vim v12, v30, 1, v0
-; ZVBB-NEXT: vmv1r.v v19, v16
-; ZVBB-NEXT: vmv1r.v v0, v15
-; ZVBB-NEXT: vmerge.vim v24, v30, 1, v0
-; ZVBB-NEXT: vmv1r.v v20, v12
-; ZVBB-NEXT: vmv1r.v v0, v14
-; ZVBB-NEXT: vmerge.vim v14, v30, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v26
-; ZVBB-NEXT: vmerge.vim v26, v30, 1, v0
; ZVBB-NEXT: add a2, a3, a1
-; ZVBB-NEXT: vmv1r.v v21, v24
+; ZVBB-NEXT: vmv1r.v v19, v26
; ZVBB-NEXT: add a4, a2, a1
-; ZVBB-NEXT: vmv1r.v v22, v14
-; ZVBB-NEXT: vmv1r.v v12, v17
+; ZVBB-NEXT: vmv1r.v v20, v12
+; ZVBB-NEXT: vmv1r.v v10, v29
; ZVBB-NEXT: add a5, a4, a1
-; ZVBB-NEXT: vmv1r.v v23, v26
+; ZVBB-NEXT: vmv1r.v v21, v24
+; ZVBB-NEXT: vmv1r.v v12, v27
+; ZVBB-NEXT: vmv1r.v v0, v23
+; ZVBB-NEXT: vmerge.vim v22, v14, 1, v0
; ZVBB-NEXT: vmv1r.v v14, v25
-; ZVBB-NEXT: vmv1r.v v0, v28
-; ZVBB-NEXT: vmerge.vim v24, v30, 1, v0
-; ZVBB-NEXT: vmv1r.v v16, v27
; ZVBB-NEXT: vsetvli a6, zero, e8, m1, ta, ma
-; ZVBB-NEXT: vsseg7e8.v v18, (a3)
-; ZVBB-NEXT: vmv1r.v v17, v25
-; ZVBB-NEXT: vsseg7e8.v v11, (a0)
+; ZVBB-NEXT: vsseg7e8.v v16, (a3)
+; ZVBB-NEXT: vmv1r.v v15, v23
+; ZVBB-NEXT: vsseg7e8.v v9, (a0)
; ZVBB-NEXT: vl1r.v v8, (a4)
; ZVBB-NEXT: add a4, a5, a1
; ZVBB-NEXT: vl1r.v v10, (a3)
@@ -5505,34 +5501,32 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv16i1(<vscale x 16 x i1
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v15, v13
-; CHECK-NEXT: vmv1r.v v13, v11
-; CHECK-NEXT: vmv1r.v v11, v9
+; CHECK-NEXT: vmv1r.v v16, v9
; CHECK-NEXT: vmv.v.i v6, 0
; CHECK-NEXT: vmerge.vim v22, v6, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v6, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vmerge.vim v20, v6, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vmerge.vim v18, v6, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmerge.vim v16, v6, 1, v0
; CHECK-NEXT: vmv2r.v v28, v26
; CHECK-NEXT: vmv2r.v v26, v24
; CHECK-NEXT: vmv2r.v v24, v22
; CHECK-NEXT: vmv1r.v v25, v8
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: vmerge.vim v20, v6, 1, v0
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vim v10, v6, 1, v0
; CHECK-NEXT: vmv1r.v v26, v20
; CHECK-NEXT: vmv1r.v v27, v10
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: vmerge.vim v16, v6, 1, v0
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmerge.vim v12, v6, 1, v0
-; CHECK-NEXT: vmv1r.v v28, v16
+; CHECK-NEXT: vmv1r.v v28, v18
; CHECK-NEXT: vmv1r.v v29, v12
-; CHECK-NEXT: vmv1r.v v0, v15
-; CHECK-NEXT: vmerge.vim v18, v6, 1, v0
; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmerge.vim v14, v6, 1, v0
-; CHECK-NEXT: vmv1r.v v30, v18
+; CHECK-NEXT: vmv1r.v v30, v16
; CHECK-NEXT: vmv1r.v v31, v14
; CHECK-NEXT: vmv1r.v v8, v23
; CHECK-NEXT: addi a2, sp, 16
@@ -5550,9 +5544,9 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv16i1(<vscale x 16 x i1
; CHECK-NEXT: add a6, a4, a0
; CHECK-NEXT: add a7, a5, a0
; CHECK-NEXT: add t0, a6, a0
-; CHECK-NEXT: vmv1r.v v12, v17
+; CHECK-NEXT: vmv1r.v v12, v19
; CHECK-NEXT: add t1, a7, a0
-; CHECK-NEXT: vmv1r.v v14, v19
+; CHECK-NEXT: vmv1r.v v14, v17
; CHECK-NEXT: vsseg8e8.v v8, (a1)
; CHECK-NEXT: vl1r.v v8, (a5)
; CHECK-NEXT: add a5, t0, a0
@@ -5609,34 +5603,32 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv16i1(<vscale x 16 x i1
; ZVBB-NEXT: slli a0, a0, 4
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; ZVBB-NEXT: vmv1r.v v15, v13
-; ZVBB-NEXT: vmv1r.v v13, v11
-; ZVBB-NEXT: vmv1r.v v11, v9
+; ZVBB-NEXT: vmv1r.v v16, v9
; ZVBB-NEXT: vmv.v.i v6, 0
; ZVBB-NEXT: vmerge.vim v22, v6, 1, v0
; ZVBB-NEXT: vmv1r.v v0, v8
; ZVBB-NEXT: vmerge.vim v8, v6, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v16
+; ZVBB-NEXT: vmerge.vim v20, v6, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v11
+; ZVBB-NEXT: vmerge.vim v18, v6, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v13
+; ZVBB-NEXT: vmerge.vim v16, v6, 1, v0
; ZVBB-NEXT: vmv2r.v v28, v26
; ZVBB-NEXT: vmv2r.v v26, v24
; ZVBB-NEXT: vmv2r.v v24, v22
; ZVBB-NEXT: vmv1r.v v25, v8
-; ZVBB-NEXT: vmv1r.v v0, v11
-; ZVBB-NEXT: vmerge.vim v20, v6, 1, v0
; ZVBB-NEXT: vmv1r.v v0, v10
; ZVBB-NEXT: vmerge.vim v10, v6, 1, v0
; ZVBB-NEXT: vmv1r.v v26, v20
; ZVBB-NEXT: vmv1r.v v27, v10
-; ZVBB-NEXT: vmv1r.v v0, v13
-; ZVBB-NEXT: vmerge.vim v16, v6, 1, v0
; ZVBB-NEXT: vmv1r.v v0, v12
; ZVBB-NEXT: vmerge.vim v12, v6, 1, v0
-; ZVBB-NEXT: vmv1r.v v28, v16
+; ZVBB-NEXT: vmv1r.v v28, v18
; ZVBB-NEXT: vmv1r.v v29, v12
-; ZVBB-NEXT: vmv1r.v v0, v15
-; ZVBB-NEXT: vmerge.vim v18, v6, 1, v0
; ZVBB-NEXT: vmv1r.v v0, v14
; ZVBB-NEXT: vmerge.vim v14, v6, 1, v0
-; ZVBB-NEXT: vmv1r.v v30, v18
+; ZVBB-NEXT: vmv1r.v v30, v16
; ZVBB-NEXT: vmv1r.v v31, v14
; ZVBB-NEXT: vmv1r.v v8, v23
; ZVBB-NEXT: addi a2, sp, 16
@@ -5654,9 +5646,9 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv16i1(<vscale x 16 x i1
; ZVBB-NEXT: add a6, a4, a0
; ZVBB-NEXT: add a7, a5, a0
; ZVBB-NEXT: add t0, a6, a0
-; ZVBB-NEXT: vmv1r.v v12, v17
+; ZVBB-NEXT: vmv1r.v v12, v19
; ZVBB-NEXT: add t1, a7, a0
-; ZVBB-NEXT: vmv1r.v v14, v19
+; ZVBB-NEXT: vmv1r.v v14, v17
; ZVBB-NEXT: vsseg8e8.v v8, (a1)
; ZVBB-NEXT: vl1r.v v8, (a5)
; ZVBB-NEXT: add a5, t0, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
index b619a4d5a2eba..168b9470f3e83 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
@@ -14,13 +14,13 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_negone(<vscale x 1 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv1i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 3
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
@@ -32,13 +32,13 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_negone(<vscale x 1 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv1i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: srli a0, a0, 3
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
@@ -56,13 +56,13 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_max(<vscale x 1 x i1> %a, <vscale
; NOVLDEP-LABEL: splice_nxv1i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 3
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 1
; NOVLDEP-NEXT: addi a0, a0, -1
@@ -74,13 +74,13 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_max(<vscale x 1 x i1> %a, <vscale
; VLDEP-LABEL: splice_nxv1i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: srli a0, a0, 3
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -98,13 +98,13 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_negone(<vscale x 2 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv2i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 2
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
@@ -116,13 +116,13 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_negone(<vscale x 2 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv2i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: srli a0, a0, 2
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
@@ -140,13 +140,13 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_max(<vscale x 2 x i1> %a, <vscale
; NOVLDEP-LABEL: splice_nxv2i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 2
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3
; NOVLDEP-NEXT: addi a0, a0, -3
@@ -158,13 +158,13 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_max(<vscale x 2 x i1> %a, <vscale
; VLDEP-LABEL: splice_nxv2i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: srli a0, a0, 2
; VLDEP-NEXT: addi a0, a0, -3
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -182,13 +182,13 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_negone(<vscale x 4 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv4i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 1
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
@@ -200,13 +200,13 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_negone(<vscale x 4 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv4i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: srli a0, a0, 1
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
@@ -224,13 +224,13 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_max(<vscale x 4 x i1> %a, <vscale
; NOVLDEP-LABEL: splice_nxv4i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 1
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 7
; NOVLDEP-NEXT: addi a0, a0, -7
@@ -242,13 +242,13 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_max(<vscale x 4 x i1> %a, <vscale
; VLDEP-LABEL: splice_nxv4i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: srli a0, a0, 1
; VLDEP-NEXT: addi a0, a0, -7
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -266,13 +266,13 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_negone(<vscale x 8 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv8i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
@@ -283,13 +283,13 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_negone(<vscale x 8 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv8i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; VLDEP-NEXT: vslidedown.vx v8, v8, a0
@@ -306,13 +306,13 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_max(<vscale x 8 x i1> %a, <vscale
; NOVLDEP-LABEL: splice_nxv8i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 15
; NOVLDEP-NEXT: addi a0, a0, -15
; NOVLDEP-NEXT: vslideup.vx v8, v9, a0
@@ -323,13 +323,13 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_max(<vscale x 8 x i1> %a, <vscale
; VLDEP-LABEL: splice_nxv8i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: addi a0, a0, -15
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; VLDEP-NEXT: vslidedown.vi v8, v8, 15
@@ -346,13 +346,13 @@ define <vscale x 16 x i1> @splice_nxv16i1_offset_negone(<vscale x 16 x i1> %a, <
; NOVLDEP-LABEL: splice_nxv16i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv.v.i v12, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v12, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v10, v12, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v12
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: slli a0, a0, 1
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
@@ -364,13 +364,13 @@ define <vscale x 16 x i1> @splice_nxv16i1_offset_negone(<vscale x 16 x i1> %a, <
; VLDEP-LABEL: splice_nxv16i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv.v.i v12, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v12, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v10, v12, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v12
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: slli a0, a0, 1
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, m2, ta, ma
@@ -388,13 +388,13 @@ define <vscale x 16 x i1> @splice_nxv16i1_offset_max(<vscale x 16 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv16i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv.v.i v12, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v12, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v10, v12, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v12
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: slli a0, a0, 1
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 31
; NOVLDEP-NEXT: addi a0, a0, -31
@@ -406,13 +406,13 @@ define <vscale x 16 x i1> @splice_nxv16i1_offset_max(<vscale x 16 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv16i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv.v.i v12, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v12, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v10, v12, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v12
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: slli a0, a0, 1
; VLDEP-NEXT: addi a0, a0, -31
; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -430,13 +430,13 @@ define <vscale x 32 x i1> @splice_nxv32i1_offset_negone(<vscale x 32 x i1> %a, <
; NOVLDEP-LABEL: splice_nxv32i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv.v.i v16, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v16, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v12, v16, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v12, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v16
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: slli a0, a0, 2
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
@@ -448,13 +448,13 @@ define <vscale x 32 x i1> @splice_nxv32i1_offset_negone(<vscale x 32 x i1> %a, <
; VLDEP-LABEL: splice_nxv32i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv.v.i v16, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v16, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v12, v16, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v12, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v16
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: slli a0, a0, 2
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, m4, ta, ma
@@ -473,8 +473,8 @@ define <vscale x 32 x i1> @splice_nxv32i1_offset_max(<vscale x 32 x i1> %a, <vsc
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v16, 0
-; NOVLDEP-NEXT: li a0, 63
; NOVLDEP-NEXT: vmerge.vim v12, v16, 1, v0
+; NOVLDEP-NEXT: li a0, 63
; NOVLDEP-NEXT: vslidedown.vx v12, v12, a0
; NOVLDEP-NEXT: csrr a0, vlenb
; NOVLDEP-NEXT: vmv1r.v v0, v8
@@ -490,9 +490,9 @@ define <vscale x 32 x i1> @splice_nxv32i1_offset_max(<vscale x 32 x i1> %a, <vsc
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; VLDEP-NEXT: vmv.v.i v16, 0
+; VLDEP-NEXT: vmerge.vim v12, v16, 1, v0
; VLDEP-NEXT: csrr a0, vlenb
; VLDEP-NEXT: li a1, 63
-; VLDEP-NEXT: vmerge.vim v12, v16, 1, v0
; VLDEP-NEXT: slli a0, a0, 2
; VLDEP-NEXT: addi a0, a0, -63
; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -512,38 +512,38 @@ define <vscale x 64 x i1> @splice_nxv64i1_offset_negone(<vscale x 64 x i1> %a, <
; NOVLDEP-LABEL: splice_nxv64i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv.v.i v24, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v24, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v16, v24, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v24, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v16, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v24
+; NOVLDEP-NEXT: vmerge.vim v16, v16, 1, v0
; NOVLDEP-NEXT: slli a0, a0, 3
; NOVLDEP-NEXT: addi a0, a0, -1
-; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
-; NOVLDEP-NEXT: vslideup.vi v8, v16, 1
-; NOVLDEP-NEXT: vand.vi v8, v8, 1
+; NOVLDEP-NEXT: vslidedown.vx v16, v16, a0
+; NOVLDEP-NEXT: vslideup.vi v16, v8, 1
+; NOVLDEP-NEXT: vand.vi v8, v16, 1
; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: splice_nxv64i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv.v.i v24, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v24, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v16, v24, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v24, 1, v0
+; VLDEP-NEXT: vmv.v.i v16, 0
+; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v24
+; VLDEP-NEXT: vmerge.vim v16, v16, 1, v0
; VLDEP-NEXT: slli a0, a0, 3
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vslidedown.vx v16, v16, a0
; VLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; VLDEP-NEXT: vslideup.vi v8, v16, 1
-; VLDEP-NEXT: vand.vi v8, v8, 1
+; VLDEP-NEXT: vslideup.vi v16, v8, 1
+; VLDEP-NEXT: vand.vi v8, v16, 1
; VLDEP-NEXT: vmsne.vi v0, v8, 0
; VLDEP-NEXT: ret
%res = call <vscale x 64 x i1> @llvm.vector.splice.nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b, i32 -1)
@@ -555,8 +555,8 @@ define <vscale x 64 x i1> @splice_nxv64i1_offset_max(<vscale x 64 x i1> %a, <vsc
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v24, 0
-; NOVLDEP-NEXT: li a0, 127
; NOVLDEP-NEXT: vmerge.vim v16, v24, 1, v0
+; NOVLDEP-NEXT: li a0, 127
; NOVLDEP-NEXT: vslidedown.vx v16, v16, a0
; NOVLDEP-NEXT: csrr a0, vlenb
; NOVLDEP-NEXT: vmv1r.v v0, v8
@@ -572,9 +572,9 @@ define <vscale x 64 x i1> @splice_nxv64i1_offset_max(<vscale x 64 x i1> %a, <vsc
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; VLDEP-NEXT: vmv.v.i v24, 0
+; VLDEP-NEXT: vmerge.vim v16, v24, 1, v0
; VLDEP-NEXT: csrr a0, vlenb
; VLDEP-NEXT: li a1, 127
-; VLDEP-NEXT: vmerge.vim v16, v24, 1, v0
; VLDEP-NEXT: slli a0, a0, 3
; VLDEP-NEXT: addi a0, a0, -127
; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
index 00cfcde16969f..1155e95c09ee1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
@@ -746,14 +746,14 @@ define <vscale x 16 x double> @vfabs_vv_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-LABEL: vfabs_vv_nxv16f64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vfabs.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB44_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
index 16de0a036d65e..b83bebb87182a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
@@ -933,22 +933,22 @@ define <vscale x 32 x bfloat> @vfadd_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; ZVFH-NEXT: slli a1, a2, 1
; ZVFH-NEXT: srli a2, a2, 2
; ZVFH-NEXT: sub a3, a0, a1
+; ZVFH-NEXT: sltu a4, a0, a3
+; ZVFH-NEXT: addi a4, a4, -1
+; ZVFH-NEXT: and a3, a4, a3
; ZVFH-NEXT: csrr a4, vlenb
; ZVFH-NEXT: slli a4, a4, 4
; ZVFH-NEXT: add a4, sp, a4
; ZVFH-NEXT: addi a4, a4, 16
; ZVFH-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFH-NEXT: vslidedown.vx v7, v0, a2
-; ZVFH-NEXT: sltu a2, a0, a3
-; ZVFH-NEXT: addi a2, a2, -1
-; ZVFH-NEXT: and a2, a2, a3
; ZVFH-NEXT: vmv1r.v v0, v7
-; ZVFH-NEXT: csrr a3, vlenb
-; ZVFH-NEXT: slli a3, a3, 3
-; ZVFH-NEXT: add a3, sp, a3
-; ZVFH-NEXT: addi a3, a3, 16
-; ZVFH-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a2, a2, 3
+; ZVFH-NEXT: add a2, sp, a2
+; ZVFH-NEXT: addi a2, a2, 16
+; ZVFH-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFH-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFH-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
; ZVFH-NEXT: csrr a2, vlenb
; ZVFH-NEXT: slli a3, a2, 4
@@ -1024,22 +1024,22 @@ define <vscale x 32 x bfloat> @vfadd_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
@@ -1115,22 +1115,22 @@ define <vscale x 32 x bfloat> @vfadd_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
+; ZVFBFA-NEXT: sltu a4, a0, a3
+; ZVFBFA-NEXT: addi a4, a4, -1
+; ZVFBFA-NEXT: and a3, a4, a3
; ZVFBFA-NEXT: csrr a4, vlenb
; ZVFBFA-NEXT: slli a4, a4, 4
; ZVFBFA-NEXT: add a4, sp, a4
; ZVFBFA-NEXT: addi a4, a4, 16
; ZVFBFA-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFBFA-NEXT: vslidedown.vx v7, v0, a2
-; ZVFBFA-NEXT: sltu a2, a0, a3
-; ZVFBFA-NEXT: addi a2, a2, -1
-; ZVFBFA-NEXT: and a2, a2, a3
; ZVFBFA-NEXT: vmv1r.v v0, v7
-; ZVFBFA-NEXT: csrr a3, vlenb
-; ZVFBFA-NEXT: slli a3, a3, 3
-; ZVFBFA-NEXT: add a3, sp, a3
-; ZVFBFA-NEXT: addi a3, a3, 16
-; ZVFBFA-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFBFA-NEXT: vsetvli zero, a2, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 3
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vsetvli zero, a3, e16alt, m4, ta, ma
; ZVFBFA-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFBFA-NEXT: csrr a2, vlenb
; ZVFBFA-NEXT: slli a3, a2, 4
@@ -1474,19 +1474,19 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; ZVFH-NEXT: slli a1, a2, 1
; ZVFH-NEXT: srli a2, a2, 2
; ZVFH-NEXT: sub a3, a0, a1
+; ZVFH-NEXT: sltu a4, a0, a3
+; ZVFH-NEXT: addi a4, a4, -1
+; ZVFH-NEXT: and a3, a4, a3
; ZVFH-NEXT: vmv1r.v v7, v0
; ZVFH-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFH-NEXT: vslidedown.vx v6, v0, a2
-; ZVFH-NEXT: sltu a2, a0, a3
-; ZVFH-NEXT: addi a2, a2, -1
-; ZVFH-NEXT: and a2, a2, a3
-; ZVFH-NEXT: csrr a3, vlenb
-; ZVFH-NEXT: slli a3, a3, 3
-; ZVFH-NEXT: add a3, sp, a3
-; ZVFH-NEXT: addi a3, a3, 16
-; ZVFH-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a2, a2, 3
+; ZVFH-NEXT: add a2, sp, a2
+; ZVFH-NEXT: addi a2, a2, 16
+; ZVFH-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFH-NEXT: vmv1r.v v0, v6
-; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFH-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFH-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
; ZVFH-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -1538,19 +1538,19 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -1601,16 +1601,16 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
+; ZVFBFA-NEXT: sltu a4, a0, a3
+; ZVFBFA-NEXT: addi a4, a4, -1
+; ZVFBFA-NEXT: and a3, a4, a3
; ZVFBFA-NEXT: vmv1r.v v7, v0
; ZVFBFA-NEXT: vsetvli a4, zero, e8alt, mf2, ta, ma
; ZVFBFA-NEXT: vslidedown.vx v6, v0, a2
-; ZVFBFA-NEXT: sltu a2, a0, a3
-; ZVFBFA-NEXT: addi a2, a2, -1
-; ZVFBFA-NEXT: and a2, a2, a3
-; ZVFBFA-NEXT: addi a3, sp, 16
-; ZVFBFA-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: addi a2, sp, 16
+; ZVFBFA-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFBFA-NEXT: vmv1r.v v0, v6
-; ZVFBFA-NEXT: vsetvli zero, a2, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vsetvli zero, a3, e16alt, m4, ta, ma
; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -2730,22 +2730,22 @@ define <vscale x 32 x half> @vfadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
@@ -2821,22 +2821,22 @@ define <vscale x 32 x half> @vfadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
+; ZVFBFA-NEXT: sltu a4, a0, a3
+; ZVFBFA-NEXT: addi a4, a4, -1
+; ZVFBFA-NEXT: and a3, a4, a3
; ZVFBFA-NEXT: csrr a4, vlenb
; ZVFBFA-NEXT: slli a4, a4, 4
; ZVFBFA-NEXT: add a4, sp, a4
; ZVFBFA-NEXT: addi a4, a4, 16
; ZVFBFA-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFBFA-NEXT: vslidedown.vx v7, v0, a2
-; ZVFBFA-NEXT: sltu a2, a0, a3
-; ZVFBFA-NEXT: addi a2, a2, -1
-; ZVFBFA-NEXT: and a2, a2, a3
; ZVFBFA-NEXT: vmv1r.v v0, v7
-; ZVFBFA-NEXT: csrr a3, vlenb
-; ZVFBFA-NEXT: slli a3, a3, 3
-; ZVFBFA-NEXT: add a3, sp, a3
-; ZVFBFA-NEXT: addi a3, a3, 16
-; ZVFBFA-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFBFA-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 3
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFBFA-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFBFA-NEXT: csrr a2, vlenb
; ZVFBFA-NEXT: slli a3, a2, 4
@@ -3104,19 +3104,19 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -3168,19 +3168,19 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
+; ZVFBFA-NEXT: sltu a4, a0, a3
+; ZVFBFA-NEXT: addi a4, a4, -1
+; ZVFBFA-NEXT: and a3, a4, a3
; ZVFBFA-NEXT: vmv1r.v v7, v0
; ZVFBFA-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFBFA-NEXT: vslidedown.vx v6, v0, a2
-; ZVFBFA-NEXT: sltu a2, a0, a3
-; ZVFBFA-NEXT: addi a2, a2, -1
-; ZVFBFA-NEXT: and a2, a2, a3
-; ZVFBFA-NEXT: csrr a3, vlenb
-; ZVFBFA-NEXT: slli a3, a3, 3
-; ZVFBFA-NEXT: add a3, sp, a3
-; ZVFBFA-NEXT: addi a3, a3, 16
-; ZVFBFA-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 3
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFBFA-NEXT: vmv1r.v v0, v6
-; ZVFBFA-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFBFA-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
index fb4eca7837738..f80be5de3bbfd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
@@ -372,22 +372,22 @@ define <vscale x 32 x bfloat> @vfdiv_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
; CHECK-NEXT: addi a4, a4, 16
; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vslidedown.vx v7, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a3, a2, 4
@@ -555,19 +555,19 @@ define <vscale x 32 x bfloat> @vfdiv_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v6, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -1194,22 +1194,22 @@ define <vscale x 32 x half> @vfdiv_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
@@ -1389,19 +1389,19 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
index 48b0bfd21bdba..c44ae411f6982 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
@@ -613,6 +613,9 @@ define <vscale x 32 x bfloat> @vfma_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vs
; CHECK-NEXT: slli a0, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a1, a0
+; CHECK-NEXT: sltu a4, a1, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 3
; CHECK-NEXT: mv a5, a4
@@ -628,21 +631,18 @@ define <vscale x 32 x bfloat> @vfma_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vs
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: sltu a2, a1, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a4, a3, 5
-; CHECK-NEXT: add a3, a4, a3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a4, a2, 5
+; CHECK-NEXT: add a2, a4, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
@@ -914,6 +914,9 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bfl
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: mv a5, a4
@@ -932,18 +935,15 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bfl
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: mv a4, a3
-; CHECK-NEXT: slli a3, a3, 1
-; CHECK-NEXT: add a3, a3, a4
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: mv a4, a2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: add a2, a2, a4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
@@ -954,7 +954,7 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bfl
; CHECK-NEXT: slli a2, a2, 5
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: mv a3, a2
@@ -963,12 +963,12 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bfl
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v28, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a2, vlenb
@@ -1136,6 +1136,9 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_commute(<vscale x 32 x bfloat>
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 5
; CHECK-NEXT: add a4, sp, a4
@@ -1149,21 +1152,18 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_commute(<vscale x 32 x bfloat>
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 4
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a4, a3, 5
-; CHECK-NEXT: add a3, a4, a3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a4, a2, 5
+; CHECK-NEXT: add a2, a4, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
@@ -2363,6 +2363,9 @@ define <vscale x 32 x half> @vfma_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a0, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a1, a0
+; ZVFHMIN-NEXT: sltu a4, a1, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 3
; ZVFHMIN-NEXT: mv a5, a4
@@ -2378,21 +2381,18 @@ define <vscale x 32 x half> @vfma_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a2, a1, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a4, a3, 5
-; ZVFHMIN-NEXT: add a3, a4, a3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a4, a2, 5
+; ZVFHMIN-NEXT: add a2, a4, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
@@ -2677,6 +2677,9 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16(<vscale x 32 x half> %va, half %b,
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: mv a5, a4
@@ -2695,18 +2698,15 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16(<vscale x 32 x half> %va, half %b,
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: mv a4, a3
-; ZVFHMIN-NEXT: slli a3, a3, 1
-; ZVFHMIN-NEXT: add a3, a3, a4
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a4, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
@@ -2717,7 +2717,7 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16(<vscale x 32 x half> %va, half %b,
; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -2726,12 +2726,12 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16(<vscale x 32 x half> %va, half %b,
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
@@ -2905,6 +2905,9 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_commute(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -2918,21 +2921,18 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_commute(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 4
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a4, a3, 5
-; ZVFHMIN-NEXT: add a3, a4, a3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a4, a2, 5
+; ZVFHMIN-NEXT: add a2, a4, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
@@ -8564,30 +8564,24 @@ define <vscale x 32 x half> @vfmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscal
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 4
-; ZVFHMIN-NEXT: add a3, a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: slli a2, a2, 1
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: vmv8r.v v16, v8
; ZVFHMIN-NEXT: vl8re16.v v24, (a0)
; ZVFHMIN-NEXT: lui a2, 8
@@ -8596,129 +8590,79 @@ define <vscale x 32 x half> @vfmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscal
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a4, a1, a0
; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 4
-; ZVFHMIN-NEXT: mv a6, a5
-; ZVFHMIN-NEXT: slli a5, a5, 1
-; ZVFHMIN-NEXT: add a5, a5, a6
-; ZVFHMIN-NEXT: add a5, sp, a5
-; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl1r.v v8, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
-; ZVFHMIN-NEXT: sltu a3, a1, a4
-; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 4
-; ZVFHMIN-NEXT: mv a6, a5
-; ZVFHMIN-NEXT: slli a5, a5, 1
-; ZVFHMIN-NEXT: add a5, a5, a6
+; ZVFHMIN-NEXT: slli a5, a5, 5
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: sltu a2, a1, a4
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a4
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
; ZVFHMIN-NEXT: vmv4r.v v8, v24
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: slli a2, a2, 1
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a1, a0, .LBB280_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB280_2:
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: mv a2, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a2
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 2
-; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -8726,27 +8670,22 @@ define <vscale x 32 x half> @vfmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscal
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: add a1, a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -8995,6 +8934,9 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16(<vscale x 32 x half> %va, half %
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -9008,9 +8950,6 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16(<vscale x 32 x half> %va, half %
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
@@ -9175,6 +9114,9 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16_commute(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -9182,9 +9124,6 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16_commute(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a3
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
@@ -9561,145 +9500,247 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a3, a2, 5
-; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a3, a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vl8re16.v v8, (a0)
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8re16.v v24, (a0)
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a4, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vxor.vx v8, v16, a2, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a0, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a4, a1, a0
; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 5
-; ZVFHMIN-NEXT: add a5, sp, a5
-; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl1r.v v24, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v7, v24, a3
-; ZVFHMIN-NEXT: sltu a3, a1, a4
-; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 5
-; ZVFHMIN-NEXT: add a5, sp, a5
-; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: csrr a5, vlenb
; ZVFHMIN-NEXT: slli a5, a5, 4
+; ZVFHMIN-NEXT: mv a6, a5
+; ZVFHMIN-NEXT: slli a5, a5, 1
+; ZVFHMIN-NEXT: add a5, a5, a6
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
+; ZVFHMIN-NEXT: sltu a2, a1, a4
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a4
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 4
+; ZVFHMIN-NEXT: mv a5, a4
+; ZVFHMIN-NEXT: slli a4, a4, 1
+; ZVFHMIN-NEXT: add a4, a4, a5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: mv a4, a3
+; ZVFHMIN-NEXT: slli a3, a3, 2
+; ZVFHMIN-NEXT: add a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vmv4r.v v8, v24
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: mv a4, a3
+; ZVFHMIN-NEXT: slli a3, a3, 2
+; ZVFHMIN-NEXT: add a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v8, v7
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: slli a2, a2, 2
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a1, a0, .LBB286_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB286_2:
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a2
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a2
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: slli a0, a0, 2
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv.v.v v16, v8
-; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a1, a0, 5
-; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -9740,7 +9781,10 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
@@ -9767,36 +9811,57 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a5, a5, a6
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl1r.v v8, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
-; ZVFHMIN-NEXT: sltu a3, a1, a4
-; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 3
-; ZVFHMIN-NEXT: mv a6, a5
-; ZVFHMIN-NEXT: slli a5, a5, 2
-; ZVFHMIN-NEXT: add a5, a5, a6
-; ZVFHMIN-NEXT: add a5, sp, a5
-; ZVFHMIN-NEXT: addi a5, a5, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: sltu a2, a1, a4
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a4
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 3
+; ZVFHMIN-NEXT: mv a5, a4
+; ZVFHMIN-NEXT: slli a4, a4, 2
+; ZVFHMIN-NEXT: add a4, a4, a5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vmv4r.v v8, v24
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -9804,23 +9869,22 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v16, v0
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vmv1r.v v0, v16
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
@@ -9838,17 +9902,14 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a2, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a2
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
@@ -9856,16 +9917,19 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -9878,7 +9942,7 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
@@ -9890,7 +9954,7 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: slli a0, a0, 3
@@ -10238,11 +10302,12 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v16, a1
+; ZVFHMIN-NEXT: vmv.v.x v8, a1
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: mv a4, a1
@@ -10250,14 +10315,14 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: add a1, a1, a4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v24, v8, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v24, v16, a2, v0.t
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
@@ -10268,32 +10333,32 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: add a1, a4, a1
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a2, v0.t
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vl1r.v v16, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a3
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a4, a3, 5
; ZVFHMIN-NEXT: add a3, a4, a3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a4, a3, 5
; ZVFHMIN-NEXT: add a3, a4, a3
@@ -10301,11 +10366,11 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
@@ -10316,7 +10381,6 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
-; ZVFHMIN-NEXT: vmv8r.v v24, v8
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -10330,8 +10394,8 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -10339,9 +10403,9 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -10362,7 +10426,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
@@ -10375,13 +10439,13 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
@@ -10401,7 +10465,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -10454,17 +10518,12 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a2, a1, 5
-; ZVFHMIN-NEXT: add a1, a2, a1
-; ZVFHMIN-NEXT: add a1, sp, a1
-; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv8r.v v24, v8
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v16, a1
+; ZVFHMIN-NEXT: vmv.v.x v8, a1
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: mv a4, a1
@@ -10472,50 +10531,44 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a1, a1, a4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v24, v8, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a4, a1, 5
-; ZVFHMIN-NEXT: add a1, a4, a1
-; ZVFHMIN-NEXT: add a1, sp, a1
-; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vl1r.v v16, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a3
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a4, a3, 5
; ZVFHMIN-NEXT: add a3, a4, a3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a4, a3, 5
; ZVFHMIN-NEXT: add a3, a4, a3
@@ -10523,11 +10576,12 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv8r.v v8, v24
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
@@ -10537,7 +10591,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -10551,8 +10605,8 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -10560,9 +10614,9 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -10570,7 +10624,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a0, a1, .LBB291_2
@@ -10583,7 +10637,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
@@ -10596,7 +10650,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
@@ -10997,6 +11051,9 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -11010,9 +11067,6 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
@@ -11197,6 +11251,9 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -11210,9 +11267,6 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
@@ -11669,145 +11723,247 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a3, a2, 5
-; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a3, a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vl8re16.v v8, (a0)
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8re16.v v24, (a0)
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a4, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vxor.vx v8, v16, a2, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a0, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a4, a1, a0
; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 5
-; ZVFHMIN-NEXT: add a5, sp, a5
-; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl1r.v v24, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v7, v24, a3
-; ZVFHMIN-NEXT: sltu a3, a1, a4
-; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 5
-; ZVFHMIN-NEXT: add a5, sp, a5
-; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: csrr a5, vlenb
; ZVFHMIN-NEXT: slli a5, a5, 4
+; ZVFHMIN-NEXT: mv a6, a5
+; ZVFHMIN-NEXT: slli a5, a5, 1
+; ZVFHMIN-NEXT: add a5, a5, a6
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
+; ZVFHMIN-NEXT: sltu a2, a1, a4
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a4
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 4
+; ZVFHMIN-NEXT: mv a5, a4
+; ZVFHMIN-NEXT: slli a4, a4, 1
+; ZVFHMIN-NEXT: add a4, a4, a5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: mv a4, a3
+; ZVFHMIN-NEXT: slli a3, a3, 2
+; ZVFHMIN-NEXT: add a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vmv4r.v v8, v24
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: mv a4, a3
+; ZVFHMIN-NEXT: slli a3, a3, 2
+; ZVFHMIN-NEXT: add a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v8, v7
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: slli a2, a2, 2
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a1, a0, .LBB298_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB298_2:
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a2
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a2
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv.v.v v16, v8
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a1, a0, 5
-; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -11848,7 +12004,10 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
@@ -11875,36 +12034,57 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a5, a5, a6
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl1r.v v8, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
-; ZVFHMIN-NEXT: sltu a3, a1, a4
-; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 3
-; ZVFHMIN-NEXT: mv a6, a5
-; ZVFHMIN-NEXT: slli a5, a5, 2
-; ZVFHMIN-NEXT: add a5, a5, a6
-; ZVFHMIN-NEXT: add a5, sp, a5
-; ZVFHMIN-NEXT: addi a5, a5, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: sltu a2, a1, a4
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a4
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 3
+; ZVFHMIN-NEXT: mv a5, a4
+; ZVFHMIN-NEXT: slli a4, a4, 2
+; ZVFHMIN-NEXT: add a4, a4, a5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vmv4r.v v8, v24
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -11912,23 +12092,22 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v16, v0
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vmv1r.v v0, v16
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
@@ -11946,17 +12125,14 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a2, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a2
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
@@ -11964,16 +12140,19 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -11986,7 +12165,7 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
@@ -11998,7 +12177,7 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: slli a0, a0, 3
@@ -12340,50 +12519,50 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: fmv.x.h a1, fa0
-; ZVFHMIN-NEXT: lui a2, 8
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v24, a1
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
-; ZVFHMIN-NEXT: mv a4, a1
+; ZVFHMIN-NEXT: mv a2, a1
; ZVFHMIN-NEXT: slli a1, a1, 1
-; ZVFHMIN-NEXT: add a1, a1, a4
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: fmv.x.h a1, fa0
+; ZVFHMIN-NEXT: lui a2, 8
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v24, a1
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v16, v8, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vl1r.v v24, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v24, v24, a3
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a4, a3, 5
; ZVFHMIN-NEXT: add a3, a4, a3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a4, a3, 5
; ZVFHMIN-NEXT: add a3, a4, a3
@@ -12391,14 +12570,17 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -12414,12 +12596,9 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
@@ -12451,14 +12630,17 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
@@ -12471,9 +12653,6 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -12535,16 +12714,24 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v24, a1
+; ZVFHMIN-NEXT: vmv.v.x v16, a1
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: mv a4, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: mv a4, a1
@@ -12554,10 +12741,13 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v16, v8, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: mv a5, a4
@@ -12565,9 +12755,9 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a4, a4, a5
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vl1r.v v24, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v24, v24, a3
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: mv a4, a3
@@ -12575,15 +12765,12 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a3, a3, a4
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: mv a4, a3
@@ -12593,15 +12780,12 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -12625,7 +12809,10 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
@@ -12682,10 +12869,7 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
@@ -12699,7 +12883,10 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
@@ -13114,6 +13301,9 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v16, v24, a2, v0.t
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 3
; ZVFHMIN-NEXT: mv a5, a4
@@ -13124,9 +13314,6 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
@@ -13302,6 +13489,9 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -13309,9 +13499,6 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: vmv4r.v v8, v24
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
index 42dd2dd28f614..1d32049f930cc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
@@ -182,22 +182,22 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
; CHECK-NEXT: addi a4, a4, 16
; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vslidedown.vx v7, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a3, a2, 4
@@ -585,22 +585,22 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
index 91b9d2d4e3258..0d10760e53e2b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
@@ -182,22 +182,22 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
; CHECK-NEXT: addi a4, a4, 16
; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vslidedown.vx v7, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a3, a2, 4
@@ -585,22 +585,22 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
index 92127a8e2f664..b32346ffc2df3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
@@ -494,22 +494,22 @@ define <vscale x 32 x half> @vfmul_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
@@ -689,19 +689,19 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
index 6213a190e5c12..d8e8d12e3d86c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
@@ -710,14 +710,14 @@ define <vscale x 16 x double> @vfneg_vv_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-LABEL: vfneg_vv_nxv16f64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vfneg.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB44_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
index 622fbaade9e95..533cb96560a49 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
@@ -86,17 +86,17 @@ define <vscale x 7 x double> @vfpext_nxv7f32_nxv7f64(<vscale x 7 x float> %a, <v
define <vscale x 32 x float> @vfpext_nxv32f16_nxv32f32(<vscale x 32 x half> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vfpext_nxv32f16_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB7_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
index 14753384b6460..2dc3ced5e3081 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
@@ -462,17 +462,17 @@ define <vscale x 2 x i64> @vfptosi_nxv2i64_nxv2f64_unmasked(<vscale x 2 x double
define <vscale x 32 x i16> @vfptosi_nxv32i16_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptosi_nxv32i16_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB34_2
; CHECK-NEXT: # %bb.1:
@@ -490,17 +490,17 @@ define <vscale x 32 x i16> @vfptosi_nxv32i16_nxv32f32(<vscale x 32 x float> %va,
define <vscale x 32 x i32> @vfptosi_nxv32i32_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptosi_nxv32i32_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB35_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
index 5073a806cc2a5..ddd67b356540b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
@@ -462,17 +462,17 @@ define <vscale x 2 x i64> @vfptoui_nxv2i64_nxv2f64_unmasked(<vscale x 2 x double
define <vscale x 32 x i16> @vfptoui_nxv32i16_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptoui_nxv32i16_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB34_2
; CHECK-NEXT: # %bb.1:
@@ -490,17 +490,17 @@ define <vscale x 32 x i16> @vfptoui_nxv32i16_nxv32f32(<vscale x 32 x float> %va,
define <vscale x 32 x i32> @vfptoui_nxv32i32_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptoui_nxv32i32_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.rtz.xu.f.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB35_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
index 475707f27d7e9..359a534508522 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
@@ -87,14 +87,14 @@ define <vscale x 16 x float> @vfptrunc_nxv16f32_nxv16f64(<vscale x 16 x double>
; CHECK-LABEL: vfptrunc_nxv16f32_nxv16f64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v28, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB7_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
index 63651bd3955bb..365396a684fd7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
@@ -710,14 +710,14 @@ define <vscale x 16 x double> @vfsqrt_vv_nxv16f64(<vscale x 16 x double> %va, <v
; CHECK-LABEL: vfsqrt_vv_nxv16f64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vfsqrt.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB44_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
index 54d42930ed724..9b7017f323bfd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
@@ -372,22 +372,22 @@ define <vscale x 32 x bfloat> @vfsub_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
; CHECK-NEXT: addi a4, a4, 16
; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vslidedown.vx v7, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a3, a2, 4
@@ -555,19 +555,19 @@ define <vscale x 32 x bfloat> @vfsub_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v6, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -1194,22 +1194,22 @@ define <vscale x 32 x half> @vfsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
@@ -1389,19 +1389,19 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
index 7944afbbbb892..719226503e7b2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
@@ -392,18 +392,18 @@ define <vscale x 128 x i8> @vmax_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: sub a3, a2, a1
-; CHECK-NEXT: sltu a4, a2, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmax.vx v16, v16, a0, v0.t
-; CHECK-NEXT: bltu a2, a1, .LBB34_2
+; CHECK-NEXT: bltu a2, a3, .LBB34_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -928,17 +928,17 @@ define <vscale x 16 x i32> @vmax_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i
define <vscale x 32 x i32> @vmax_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vmax_vx_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: srli a3, a2, 2
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a2, a3, 1
+; CHECK-NEXT: sub a4, a1, a2
+; CHECK-NEXT: sltu a5, a1, a4
+; CHECK-NEXT: addi a5, a5, -1
+; CHECK-NEXT: and a4, a5, a4
+; CHECK-NEXT: srli a3, a3, 2
+; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: sub a3, a1, a2
-; CHECK-NEXT: sltu a4, a1, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vmax.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB80_2
; CHECK-NEXT: # %bb.1:
@@ -1001,15 +1001,15 @@ define <vscale x 32 x i32> @vmax_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i3
; RV64-LABEL: vmax_vx_nxv32i32_evl_nx8:
; RV64: # %bb.0:
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: srli a3, a1, 2
; RV64-NEXT: slli a2, a1, 1
-; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
-; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: sub a3, a1, a2
; RV64-NEXT: sltu a4, a1, a3
; RV64-NEXT: addi a4, a4, -1
; RV64-NEXT: and a3, a4, a3
+; RV64-NEXT: srli a4, a1, 2
+; RV64-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a4
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vmax.vx v16, v16, a0, v0.t
; RV64-NEXT: bltu a1, a2, .LBB82_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
index 0a3190f84c748..0acaa40ec8a16 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
@@ -391,18 +391,18 @@ define <vscale x 128 x i8> @vmaxu_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: sub a3, a2, a1
-; CHECK-NEXT: sltu a4, a2, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmaxu.vx v16, v16, a0, v0.t
-; CHECK-NEXT: bltu a2, a1, .LBB34_2
+; CHECK-NEXT: bltu a2, a3, .LBB34_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -927,17 +927,17 @@ define <vscale x 16 x i32> @vmaxu_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vmaxu_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vmaxu_vx_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: srli a3, a2, 2
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a2, a3, 1
+; CHECK-NEXT: sub a4, a1, a2
+; CHECK-NEXT: sltu a5, a1, a4
+; CHECK-NEXT: addi a5, a5, -1
+; CHECK-NEXT: and a4, a5, a4
+; CHECK-NEXT: srli a3, a3, 2
+; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: sub a3, a1, a2
-; CHECK-NEXT: sltu a4, a1, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vmaxu.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB80_2
; CHECK-NEXT: # %bb.1:
@@ -1000,15 +1000,15 @@ define <vscale x 32 x i32> @vmaxu_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i
; RV64-LABEL: vmaxu_vx_nxv32i32_evl_nx8:
; RV64: # %bb.0:
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: srli a3, a1, 2
; RV64-NEXT: slli a2, a1, 1
-; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
-; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: sub a3, a1, a2
; RV64-NEXT: sltu a4, a1, a3
; RV64-NEXT: addi a4, a4, -1
; RV64-NEXT: and a3, a4, a3
+; RV64-NEXT: srli a4, a1, 2
+; RV64-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a4
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vmaxu.vx v16, v16, a0, v0.t
; RV64-NEXT: bltu a1, a2, .LBB82_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
index ef94044613c6a..0cb5dc152e635 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
@@ -392,18 +392,18 @@ define <vscale x 128 x i8> @vmin_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: sub a3, a2, a1
-; CHECK-NEXT: sltu a4, a2, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmin.vx v16, v16, a0, v0.t
-; CHECK-NEXT: bltu a2, a1, .LBB34_2
+; CHECK-NEXT: bltu a2, a3, .LBB34_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -928,17 +928,17 @@ define <vscale x 16 x i32> @vmin_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i
define <vscale x 32 x i32> @vmin_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vmin_vx_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: srli a3, a2, 2
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a2, a3, 1
+; CHECK-NEXT: sub a4, a1, a2
+; CHECK-NEXT: sltu a5, a1, a4
+; CHECK-NEXT: addi a5, a5, -1
+; CHECK-NEXT: and a4, a5, a4
+; CHECK-NEXT: srli a3, a3, 2
+; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: sub a3, a1, a2
-; CHECK-NEXT: sltu a4, a1, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vmin.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB80_2
; CHECK-NEXT: # %bb.1:
@@ -1001,15 +1001,15 @@ define <vscale x 32 x i32> @vmin_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i3
; RV64-LABEL: vmin_vx_nxv32i32_evl_nx8:
; RV64: # %bb.0:
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: srli a3, a1, 2
; RV64-NEXT: slli a2, a1, 1
-; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
-; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: sub a3, a1, a2
; RV64-NEXT: sltu a4, a1, a3
; RV64-NEXT: addi a4, a4, -1
; RV64-NEXT: and a3, a4, a3
+; RV64-NEXT: srli a4, a1, 2
+; RV64-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a4
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vmin.vx v16, v16, a0, v0.t
; RV64-NEXT: bltu a1, a2, .LBB82_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
index 40c2375849548..56dcba4d4b347 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
@@ -391,18 +391,18 @@ define <vscale x 128 x i8> @vminu_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: sub a3, a2, a1
-; CHECK-NEXT: sltu a4, a2, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vminu.vx v16, v16, a0, v0.t
-; CHECK-NEXT: bltu a2, a1, .LBB34_2
+; CHECK-NEXT: bltu a2, a3, .LBB34_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -927,17 +927,17 @@ define <vscale x 16 x i32> @vminu_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vminu_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vminu_vx_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: srli a3, a2, 2
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a2, a3, 1
+; CHECK-NEXT: sub a4, a1, a2
+; CHECK-NEXT: sltu a5, a1, a4
+; CHECK-NEXT: addi a5, a5, -1
+; CHECK-NEXT: and a4, a5, a4
+; CHECK-NEXT: srli a3, a3, 2
+; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: sub a3, a1, a2
-; CHECK-NEXT: sltu a4, a1, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vminu.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB80_2
; CHECK-NEXT: # %bb.1:
@@ -1000,15 +1000,15 @@ define <vscale x 32 x i32> @vminu_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i
; RV64-LABEL: vminu_vx_nxv32i32_evl_nx8:
; RV64: # %bb.0:
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: srli a3, a1, 2
; RV64-NEXT: slli a2, a1, 1
-; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
-; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: sub a3, a1, a2
; RV64-NEXT: sltu a4, a1, a3
; RV64-NEXT: addi a4, a4, -1
; RV64-NEXT: and a3, a4, a3
+; RV64-NEXT: srli a4, a1, 2
+; RV64-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a4
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vminu.vx v16, v16, a0, v0.t
; RV64-NEXT: bltu a1, a2, .LBB82_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmseq.ll b/llvm/test/CodeGen/RISCV/rvv/vmseq.ll
index 4dadaaec903f4..003b7193e7873 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmseq.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmseq.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmseq.vv v10, v8, v11, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmseq.vv v11, v8, v10, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmseq_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmseq.vv v12, v8, v14, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmseq.vv v11, v8, v12, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmseq_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmseq.vv v16, v8, v20, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmseq.vv v13, v8, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsge.ll b/llvm/test/CodeGen/RISCV/rvv/vmsge.ll
index 987271cf9e3a6..e892388079303 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsge.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsge.ll
@@ -819,8 +819,8 @@ define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i8_i8_1(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: li a0, 99
; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: li a0, 99
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
@@ -1316,15 +1316,15 @@ define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsle.vv v10, v11, v8, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmsle.vv v11, v10, v8, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1379,15 +1379,15 @@ define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsle.vv v12, v14, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmsle.vv v11, v12, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1442,15 +1442,15 @@ define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsle.vv v16, v20, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmsle.vv v13, v16, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
index f4f4e884e0cdb..db06aac7cec4f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
@@ -1278,15 +1278,15 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsleu.vv v10, v11, v8, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmsleu.vv v11, v10, v8, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1341,15 +1341,15 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsleu.vv v12, v14, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmsleu.vv v11, v12, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1404,15 +1404,15 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsleu.vv v16, v20, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmsleu.vv v13, v16, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1545,8 +1545,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i8_i8_1(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: li a0, 99
; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: li a0, 99
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
index 23d117a02505b..68f9ad8325bf4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsgt_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmslt.vv v10, v11, v8, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmslt.vv v11, v10, v8, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsgt_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmslt.vv v12, v14, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmslt.vv v11, v12, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsgt_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmslt.vv v16, v20, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmslt.vv v13, v16, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
index f546196038252..82748be39bf1d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsltu.vv v10, v11, v8, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmsltu.vv v11, v10, v8, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsltu.vv v12, v14, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmsltu.vv v11, v12, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsltu.vv v16, v20, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmsltu.vv v13, v16, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsle.ll b/llvm/test/CodeGen/RISCV/rvv/vmsle.ll
index 02c6e644df646..7598e87d34357 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsle.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsle.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsle_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsle.vv v10, v8, v11, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmsle.vv v11, v8, v10, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsle_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsle.vv v12, v8, v14, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmsle.vv v11, v8, v12, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsle_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsle.vv v16, v8, v20, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmsle.vv v13, v8, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
index 76989d2994749..df4db27660499 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsleu_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsleu.vv v10, v8, v11, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmsleu.vv v11, v8, v10, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsleu_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsleu.vv v12, v8, v14, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmsleu.vv v11, v8, v12, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsleu_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsleu.vv v16, v8, v20, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmsleu.vv v13, v8, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmslt.ll b/llvm/test/CodeGen/RISCV/rvv/vmslt.ll
index 6f6a07e6c02bc..3f6b8c709f700 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmslt.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmslt.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmslt_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmslt.vv v10, v8, v11, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmslt.vv v11, v8, v10, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmslt_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmslt.vv v12, v8, v14, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmslt.vv v11, v8, v12, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmslt_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmslt.vv v16, v8, v20, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmslt.vv v13, v8, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
index 82ad07fc5b9ab..f1e055cf478ee 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsltu_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsltu.vv v10, v8, v11, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmsltu.vv v11, v8, v10, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsltu_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsltu.vv v12, v8, v14, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmsltu.vv v11, v8, v12, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsltu_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsltu.vv v16, v8, v20, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmsltu.vv v13, v8, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsne.ll b/llvm/test/CodeGen/RISCV/rvv/vmsne.ll
index a485fdf4e505f..fff1815df2c8e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsne.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsne.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsne_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsne.vv v10, v8, v11, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmsne.vv v11, v8, v10, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsne_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsne.vv v12, v8, v14, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmsne.vv v11, v8, v12, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsne_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsne.vv v16, v8, v20, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmsne.vv v13, v8, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll b/llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
index 8e8622b3d71d4..0bb0339e1ded4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
@@ -19,9 +19,9 @@ define iXLen @bool_vec(<vscale x 2 x i1> %src, <vscale x 2 x i1> %m, i32 %evl) {
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64-NEXT: vmv1r.v v9, v0
+; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32
-; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; RV64-NEXT: vfirst.m a1, v9, v0.t
; RV64-NEXT: bltz a1, .LBB0_2
@@ -46,9 +46,9 @@ define iXLen @bool_vec_zero_poison(<vscale x 2 x i1> %src, <vscale x 2 x i1> %m,
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64-NEXT: vmv1r.v v9, v0
+; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32
-; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; RV64-NEXT: vfirst.m a0, v9, v0.t
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
index 3e81dcb29e559..b140166415d0e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
@@ -6,8 +6,8 @@ define <2 x i1> @test_vp_reverse_v2i1_masked(<2 x i1> %src, <2 x i1> %mask, i32
; CHECK-LABEL: test_vp_reverse_v2i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v11, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v9, v0.t
@@ -45,8 +45,8 @@ define <4 x i1> @test_vp_reverse_v4i1_masked(<4 x i1> %src, <4 x i1> %mask, i32
; CHECK-LABEL: test_vp_reverse_v4i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v11, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vid.v v9, v0.t
@@ -84,8 +84,8 @@ define <8 x i1> @test_vp_reverse_v8i1_masked(<8 x i1> %src, <8 x i1> %mask, i32
; CHECK-LABEL: test_vp_reverse_v8i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v11, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vid.v v9, v0.t
@@ -123,8 +123,8 @@ define <16 x i1> @test_vp_reverse_v16i1_masked(<16 x i1> %src, <16 x i1> %mask,
; CHECK-LABEL: test_vp_reverse_v16i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vid.v v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
index 510a18d8b756f..9ab5e98ea7f3f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
@@ -5,8 +5,8 @@ define <vscale x 1 x i1> @test_vp_reverse_nxv1i1_masked(<vscale x 1 x i1> %src,
; CHECK-LABEL: test_vp_reverse_nxv1i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v11, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v9, v0.t
@@ -44,8 +44,8 @@ define <vscale x 2 x i1> @test_vp_reverse_nxv2i1_masked(<vscale x 2 x i1> %src,
; CHECK-LABEL: test_vp_reverse_nxv2i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v11, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vid.v v9, v0.t
@@ -83,8 +83,8 @@ define <vscale x 4 x i1> @test_vp_reverse_nxv4i1_masked(<vscale x 4 x i1> %src,
; CHECK-LABEL: test_vp_reverse_nxv4i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v11, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vid.v v9, v0.t
@@ -122,8 +122,8 @@ define <vscale x 8 x i1> @test_vp_reverse_nxv8i1_masked(<vscale x 8 x i1> %src,
; CHECK-LABEL: test_vp_reverse_nxv8i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vid.v v8, v0.t
@@ -161,8 +161,8 @@ define <vscale x 16 x i1> @test_vp_reverse_nxv16i1_masked(<vscale x 16 x i1> %sr
; CHECK-LABEL: test_vp_reverse_nxv16i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmerge.vim v12, v10, 1, v0
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vid.v v8, v0.t
@@ -201,8 +201,8 @@ define <vscale x 32 x i1> @test_vp_reverse_nxv32i1_masked(<vscale x 32 x i1> %sr
; CHECK-LABEL: test_vp_reverse_nxv32i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vmerge.vim v16, v12, 1, v0
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
; CHECK-NEXT: vid.v v8, v0.t
@@ -243,14 +243,12 @@ define <vscale x 64 x i1> @test_vp_reverse_nxv64i1_masked(<vscale x 64 x i1> %sr
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v26, v8
; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, ma
; CHECK-NEXT: vid.v v16
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: addi a2, a1, -1
; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: vsetvli a3, zero, e16, m2, ta, ma
; CHECK-NEXT: vrsub.vx v24, v16, a2
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vrgatherei16.vv v23, v8, v24
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
index d2e6b0e6ae526..fc6a96d00cdc2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
@@ -9,9 +9,9 @@ define <2 x i1> @test_vp_splice_v2i1(<2 x i1> %va, <2 x i1> %vb, i32 zeroext %ev
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -27,9 +27,9 @@ define <2 x i1> @test_vp_splice_v2i1(<2 x i1> %va, <2 x i1> %vb, i32 zeroext %ev
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -51,9 +51,9 @@ define <2 x i1> @test_vp_splice_v2i1_negative_offset(<2 x i1> %va, <2 x i1> %vb,
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -69,9 +69,9 @@ define <2 x i1> @test_vp_splice_v2i1_negative_offset(<2 x i1> %va, <2 x i1> %vb,
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -92,14 +92,14 @@ define <2 x i1> @test_vp_splice_v2i1_masked(<2 x i1> %va, <2 x i1> %vb, <2 x i1>
; NOVLDEP-LABEL: test_vp_splice_v2i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v11, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v10, v11, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v9, v10, 1, v0.t
@@ -113,14 +113,14 @@ define <2 x i1> @test_vp_splice_v2i1_masked(<2 x i1> %va, <2 x i1> %vb, <2 x i1>
; VLDEP-LABEL: test_vp_splice_v2i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v11, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v10, v11, 1, v0
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -139,9 +139,9 @@ define <4 x i1> @test_vp_splice_v4i1(<4 x i1> %va, <4 x i1> %vb, i32 zeroext %ev
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -157,9 +157,9 @@ define <4 x i1> @test_vp_splice_v4i1(<4 x i1> %va, <4 x i1> %vb, i32 zeroext %ev
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -181,9 +181,9 @@ define <4 x i1> @test_vp_splice_v4i1_negative_offset(<4 x i1> %va, <4 x i1> %vb,
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -199,9 +199,9 @@ define <4 x i1> @test_vp_splice_v4i1_negative_offset(<4 x i1> %va, <4 x i1> %vb,
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -222,14 +222,14 @@ define <4 x i1> @test_vp_splice_v4i1_masked(<4 x i1> %va, <4 x i1> %vb, <4 x i1>
; NOVLDEP-LABEL: test_vp_splice_v4i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v11, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v10, v11, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v9, v10, 3, v0.t
@@ -243,14 +243,14 @@ define <4 x i1> @test_vp_splice_v4i1_masked(<4 x i1> %va, <4 x i1> %vb, <4 x i1>
; VLDEP-LABEL: test_vp_splice_v4i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v11, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v10, v11, 1, v0
; VLDEP-NEXT: addi a0, a0, -3
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -269,9 +269,9 @@ define <8 x i1> @test_vp_splice_v8i1(<8 x i1> %va, <8 x i1> %vb, i32 zeroext %ev
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -287,9 +287,9 @@ define <8 x i1> @test_vp_splice_v8i1(<8 x i1> %va, <8 x i1> %vb, i32 zeroext %ev
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -311,9 +311,9 @@ define <8 x i1> @test_vp_splice_v8i1_negative_offset(<8 x i1> %va, <8 x i1> %vb,
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -329,9 +329,9 @@ define <8 x i1> @test_vp_splice_v8i1_negative_offset(<8 x i1> %va, <8 x i1> %vb,
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -352,14 +352,14 @@ define <8 x i1> @test_vp_splice_v8i1_masked(<8 x i1> %va, <8 x i1> %vb, <8 x i1>
; NOVLDEP-LABEL: test_vp_splice_v8i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v11, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v10, v11, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v9, v10, 5, v0.t
@@ -373,14 +373,14 @@ define <8 x i1> @test_vp_splice_v8i1_masked(<8 x i1> %va, <8 x i1> %vb, <8 x i1>
; VLDEP-LABEL: test_vp_splice_v8i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v11, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v10, v11, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -399,9 +399,9 @@ define <16 x i1> @test_vp_splice_v16i1(<16 x i1> %va, <16 x i1> %vb, i32 zeroext
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -417,9 +417,9 @@ define <16 x i1> @test_vp_splice_v16i1(<16 x i1> %va, <16 x i1> %vb, i32 zeroext
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -441,9 +441,9 @@ define <16 x i1> @test_vp_splice_v16i1_negative_offset(<16 x i1> %va, <16 x i1>
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -459,9 +459,9 @@ define <16 x i1> @test_vp_splice_v16i1_negative_offset(<16 x i1> %va, <16 x i1>
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -482,14 +482,14 @@ define <16 x i1> @test_vp_splice_v16i1_masked(<16 x i1> %va, <16 x i1> %vb, <16
; NOVLDEP-LABEL: test_vp_splice_v16i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v11, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v10, v11, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v9, v10, 5, v0.t
@@ -503,14 +503,14 @@ define <16 x i1> @test_vp_splice_v16i1_masked(<16 x i1> %va, <16 x i1> %vb, <16
; VLDEP-LABEL: test_vp_splice_v16i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v11, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v10, v11, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
index 100d03580dc0b..bd54f34554d4d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
@@ -7,9 +7,9 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1(<vscale x 1 x i1> %va, <vscale x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -25,9 +25,9 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1(<vscale x 1 x i1> %va, <vscale x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -49,9 +49,9 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1_negative_offset(<vscale x 1 x i1
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -67,9 +67,9 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1_negative_offset(<vscale x 1 x i1
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -90,14 +90,14 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1_masked(<vscale x 1 x i1> %va, <v
; NOVLDEP-LABEL: test_vp_splice_nxv1i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v11, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v10, v11, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v9, v10, 1, v0.t
@@ -111,14 +111,14 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1_masked(<vscale x 1 x i1> %va, <v
; VLDEP-LABEL: test_vp_splice_nxv1i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v11, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v10, v11, 1, v0
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -137,9 +137,9 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1(<vscale x 2 x i1> %va, <vscale x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -155,9 +155,9 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1(<vscale x 2 x i1> %va, <vscale x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -179,9 +179,9 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1_negative_offset(<vscale x 2 x i1
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -197,9 +197,9 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1_negative_offset(<vscale x 2 x i1
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -220,14 +220,14 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1_masked(<vscale x 2 x i1> %va, <v
; NOVLDEP-LABEL: test_vp_splice_nxv2i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v11, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v10, v11, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v9, v10, 3, v0.t
@@ -241,14 +241,14 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1_masked(<vscale x 2 x i1> %va, <v
; VLDEP-LABEL: test_vp_splice_nxv2i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v11, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v10, v11, 1, v0
; VLDEP-NEXT: addi a0, a0, -3
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -267,9 +267,9 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1(<vscale x 4 x i1> %va, <vscale x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -285,9 +285,9 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1(<vscale x 4 x i1> %va, <vscale x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -309,9 +309,9 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1_negative_offset(<vscale x 4 x i1
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -327,9 +327,9 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1_negative_offset(<vscale x 4 x i1
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -350,14 +350,14 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1_masked(<vscale x 4 x i1> %va, <v
; NOVLDEP-LABEL: test_vp_splice_nxv4i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v11, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v10, v11, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v9, v10, 5, v0.t
@@ -371,14 +371,14 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1_masked(<vscale x 4 x i1> %va, <v
; VLDEP-LABEL: test_vp_splice_nxv4i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v11, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v10, v11, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -397,9 +397,9 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1(<vscale x 8 x i1> %va, <vscale x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -415,9 +415,9 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1(<vscale x 8 x i1> %va, <vscale x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -439,9 +439,9 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1_negative_offset(<vscale x 8 x i1
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -457,9 +457,9 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1_negative_offset(<vscale x 8 x i1
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -480,14 +480,14 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1_masked(<vscale x 8 x i1> %va, <v
; NOVLDEP-LABEL: test_vp_splice_nxv8i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v11, 0
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v10, v11, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v9, v10, 5, v0.t
@@ -501,14 +501,14 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1_masked(<vscale x 8 x i1> %va, <v
; VLDEP-LABEL: test_vp_splice_nxv8i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v11, 0
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v10, v11, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
@@ -527,9 +527,9 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1(<vscale x 16 x i1> %va, <vscal
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v12, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v12
@@ -545,9 +545,9 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1(<vscale x 16 x i1> %va, <vscal
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; VLDEP-NEXT: vmv1r.v v12, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v12
@@ -569,9 +569,9 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1_negative_offset(<vscale x 16 x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v12, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v12
@@ -587,9 +587,9 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1_negative_offset(<vscale x 16 x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; VLDEP-NEXT: vmv1r.v v12, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v12
@@ -610,20 +610,20 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1_masked(<vscale x 16 x i1> %va,
; NOVLDEP-LABEL: test_vp_splice_nxv16i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v14, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmv1r.v v12, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v12, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
+; NOVLDEP-NEXT: vmerge.vim v14, v10, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v14
+; NOVLDEP-NEXT: vmv1r.v v0, v12
; NOVLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v10, v10, 5, v0.t
; NOVLDEP-NEXT: addi a0, a0, -5
; NOVLDEP-NEXT: vsetvli zero, zero, e8, m2, ta, mu
-; NOVLDEP-NEXT: vslideup.vx v10, v12, a0, v0.t
+; NOVLDEP-NEXT: vslideup.vx v10, v14, a0, v0.t
; NOVLDEP-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; NOVLDEP-NEXT: vmsne.vi v8, v10, 0, v0.t
; NOVLDEP-NEXT: vmv1r.v v0, v8
@@ -632,20 +632,20 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1_masked(<vscale x 16 x i1> %va,
; VLDEP-LABEL: test_vp_splice_nxv16i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; VLDEP-NEXT: vmv1r.v v14, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmv1r.v v12, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v12, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
+; VLDEP-NEXT: vmerge.vim v14, v10, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: vmv1r.v v0, v14
+; VLDEP-NEXT: vmv1r.v v0, v12
; VLDEP-NEXT: vmerge.vim v10, v10, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; VLDEP-NEXT: vslidedown.vi v10, v10, 5, v0.t
; VLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; VLDEP-NEXT: vslideup.vx v10, v12, a0, v0.t
+; VLDEP-NEXT: vslideup.vx v10, v14, a0, v0.t
; VLDEP-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; VLDEP-NEXT: vmsne.vi v8, v10, 0, v0.t
; VLDEP-NEXT: vmv1r.v v0, v8
@@ -659,9 +659,9 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1(<vscale x 32 x i1> %va, <vscal
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v16, v0
-; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: vmv1r.v v0, v16
@@ -677,9 +677,9 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1(<vscale x 32 x i1> %va, <vscal
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; VLDEP-NEXT: vmv1r.v v16, v0
-; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: vmv1r.v v0, v16
@@ -701,9 +701,9 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1_negative_offset(<vscale x 32 x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v16, v0
-; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: vmv1r.v v0, v16
@@ -719,9 +719,9 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1_negative_offset(<vscale x 32 x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; VLDEP-NEXT: vmv1r.v v16, v0
-; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: vmv1r.v v0, v16
@@ -742,20 +742,20 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1_masked(<vscale x 32 x i1> %va,
; NOVLDEP-LABEL: test_vp_splice_nxv32i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v12, 0
+; NOVLDEP-NEXT: vmv1r.v v16, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v16, v12, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v12, 0
+; NOVLDEP-NEXT: vmerge.vim v20, v12, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v12, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmv1r.v v0, v16
; NOVLDEP-NEXT: vmerge.vim v12, v12, 1, v0
; NOVLDEP-NEXT: vmv1r.v v0, v9
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v12, v12, 5, v0.t
; NOVLDEP-NEXT: addi a0, a0, -5
; NOVLDEP-NEXT: vsetvli zero, zero, e8, m4, ta, mu
-; NOVLDEP-NEXT: vslideup.vx v12, v16, a0, v0.t
+; NOVLDEP-NEXT: vslideup.vx v12, v20, a0, v0.t
; NOVLDEP-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; NOVLDEP-NEXT: vmsne.vi v8, v12, 0, v0.t
; NOVLDEP-NEXT: vmv1r.v v0, v8
@@ -764,20 +764,20 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1_masked(<vscale x 32 x i1> %va,
; VLDEP-LABEL: test_vp_splice_nxv32i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v12, 0
+; VLDEP-NEXT: vmv1r.v v16, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v16, v12, 1, v0
+; VLDEP-NEXT: vmv.v.i v12, 0
+; VLDEP-NEXT: vmerge.vim v20, v12, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; VLDEP-NEXT: vmv.v.i v12, 0
-; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmv1r.v v0, v16
; VLDEP-NEXT: vmerge.vim v12, v12, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
; VLDEP-NEXT: vmv1r.v v0, v9
; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; VLDEP-NEXT: vslidedown.vi v12, v12, 5, v0.t
; VLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; VLDEP-NEXT: vslideup.vx v12, v16, a0, v0.t
+; VLDEP-NEXT: vslideup.vx v12, v20, a0, v0.t
; VLDEP-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; VLDEP-NEXT: vmsne.vi v8, v12, 0, v0.t
; VLDEP-NEXT: vmv1r.v v0, v8
@@ -791,9 +791,9 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1(<vscale x 64 x i1> %va, <vscal
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v24, v0
-; NOVLDEP-NEXT: vmv.v.i v16, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v16, 0
; NOVLDEP-NEXT: vmv1r.v v0, v24
@@ -809,9 +809,9 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1(<vscale x 64 x i1> %va, <vscal
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; VLDEP-NEXT: vmv1r.v v24, v0
-; VLDEP-NEXT: vmv.v.i v16, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; VLDEP-NEXT: vmv.v.i v16, 0
; VLDEP-NEXT: vmv1r.v v0, v24
@@ -833,9 +833,9 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1_negative_offset(<vscale x 64 x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v24, v0
-; NOVLDEP-NEXT: vmv.v.i v16, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v16, 0
; NOVLDEP-NEXT: vmv1r.v v0, v24
@@ -851,9 +851,9 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1_negative_offset(<vscale x 64 x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; VLDEP-NEXT: vmv1r.v v24, v0
-; VLDEP-NEXT: vmv.v.i v16, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; VLDEP-NEXT: vmv.v.i v16, 0
; VLDEP-NEXT: vmv1r.v v0, v24
@@ -874,20 +874,21 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1_masked(<vscale x 64 x i1> %va,
; NOVLDEP-LABEL: test_vp_splice_nxv64i1_masked:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v16, 0
+; NOVLDEP-NEXT: vmv1r.v v24, v0
+; NOVLDEP-NEXT: vmv1r.v v25, v9
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v24, v16, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v16, 0
-; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmv1r.v v0, v24
; NOVLDEP-NEXT: vmerge.vim v16, v16, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
+; NOVLDEP-NEXT: vmv1r.v v0, v25
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; NOVLDEP-NEXT: vslidedown.vi v16, v16, 5, v0.t
; NOVLDEP-NEXT: addi a0, a0, -5
; NOVLDEP-NEXT: vsetvli zero, zero, e8, m8, ta, mu
-; NOVLDEP-NEXT: vslideup.vx v16, v24, a0, v0.t
+; NOVLDEP-NEXT: vslideup.vx v16, v8, a0, v0.t
; NOVLDEP-NEXT: vsetvli zero, zero, e8, m8, ta, ma
; NOVLDEP-NEXT: vmsne.vi v8, v16, 0, v0.t
; NOVLDEP-NEXT: vmv1r.v v0, v8
@@ -896,20 +897,21 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1_masked(<vscale x 64 x i1> %va,
; VLDEP-LABEL: test_vp_splice_nxv64i1_masked:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v16, 0
+; VLDEP-NEXT: vmv1r.v v24, v0
+; VLDEP-NEXT: vmv1r.v v25, v9
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v24, v16, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; VLDEP-NEXT: vmv.v.i v16, 0
-; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmv1r.v v0, v24
; VLDEP-NEXT: vmerge.vim v16, v16, 1, v0
; VLDEP-NEXT: addi a0, a0, -5
-; VLDEP-NEXT: vmv1r.v v0, v9
+; VLDEP-NEXT: vmv1r.v v0, v25
; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; VLDEP-NEXT: vslidedown.vi v16, v16, 5, v0.t
; VLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; VLDEP-NEXT: vslideup.vx v16, v24, a0, v0.t
+; VLDEP-NEXT: vslideup.vx v16, v8, a0, v0.t
; VLDEP-NEXT: vsetvli zero, zero, e8, m8, ta, ma
; VLDEP-NEXT: vmsne.vi v8, v16, 0, v0.t
; VLDEP-NEXT: vmv1r.v v0, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll b/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
index 77808ad541088..d569dc84ac174 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
@@ -363,18 +363,18 @@ define i32 @masked_load_store_factor2_v2_shared_mask_extract(<vscale x 2 x i1> %
; RV32-NEXT: li a3, -1
; RV32-NEXT: vmerge.vim v9, v8, 1, v0
; RV32-NEXT: vmv1r.v v12, v0
-; RV32-NEXT: vwaddu.vv v10, v9, v9
-; RV32-NEXT: vwmaccu.vx v10, a3, v9
-; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma
-; RV32-NEXT: vmv.v.i v9, 0
-; RV32-NEXT: srli a3, a3, 2
+; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV32-NEXT: vmsne.vi v0, v10, 0
-; RV32-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; RV32-NEXT: vslidedown.vx v10, v10, a3
+; RV32-NEXT: vwaddu.vv v11, v9, v9
+; RV32-NEXT: vwmaccu.vx v11, a3, v9
+; RV32-NEXT: vmsne.vi v0, v11, 0
; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma
-; RV32-NEXT: vmerge.vim v9, v9, 1, v0
+; RV32-NEXT: vmerge.vim v9, v10, 1, v0
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: srli a3, a3, 2
+; RV32-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; RV32-NEXT: vslidedown.vx v10, v11, a3
; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; RV32-NEXT: vmsne.vi v0, v10, 0
; RV32-NEXT: vmerge.vim v8, v8, 1, v0
@@ -404,12 +404,12 @@ define i32 @masked_load_store_factor2_v2_shared_mask_extract(<vscale x 2 x i1> %
; RV64-NEXT: vmv1r.v v12, v0
; RV64-NEXT: vwaddu.vv v11, v10, v10
; RV64-NEXT: vwmaccu.vx v11, a2, v10
+; RV64-NEXT: vmsne.vi v0, v11, 0
+; RV64-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: srli a2, a2, 2
-; RV64-NEXT: vmsne.vi v0, v11, 0
-; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vx v10, v11, a2
-; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV64-NEXT: vmsne.vi v0, v10, 0
; RV64-NEXT: vmerge.vim v8, v8, 1, v0
@@ -502,13 +502,13 @@ define {<vscale x 2 x i32>, <vscale x 2 x i32>} @not_same_mask(<vscale x 2 x i1>
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vmv1r.v v0, v8
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vmerge.vim v9, v8, 1, v0
; RV32-NEXT: slli a1, a1, 1
-; RV32-NEXT: vmv.v.i v12, 0
; RV32-NEXT: li a2, -1
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vmerge.vim v9, v12, 1, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmerge.vim v10, v12, 1, v0
+; RV32-NEXT: vmerge.vim v10, v8, 1, v0
; RV32-NEXT: vwaddu.vv v11, v10, v9
; RV32-NEXT: vwmaccu.vx v11, a2, v9
; RV32-NEXT: csrr a2, vlenb
@@ -523,7 +523,7 @@ define {<vscale x 2 x i32>, <vscale x 2 x i32>} @not_same_mask(<vscale x 2 x i1>
; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV32-NEXT: vmsne.vi v0, v10, 0
-; RV32-NEXT: vmerge.vim v8, v12, 1, v0
+; RV32-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; RV32-NEXT: vslideup.vx v9, v8, a2
; RV32-NEXT: vmsne.vi v0, v9, 0
@@ -538,31 +538,31 @@ define {<vscale x 2 x i32>, <vscale x 2 x i32>} @not_same_mask(<vscale x 2 x i1>
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
; RV64-NEXT: vmv1r.v v11, v0
-; RV64-NEXT: vmv.v.i v13, 0
+; RV64-NEXT: vmv1r.v v0, v8
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: vmerge.vim v9, v8, 1, v0
; RV64-NEXT: li a2, -1
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv.v.i v9, 0
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmerge.vim v10, v13, 1, v0
+; RV64-NEXT: vmv.v.i v10, 0
; RV64-NEXT: vmv1r.v v0, v11
-; RV64-NEXT: vmerge.vim v11, v13, 1, v0
-; RV64-NEXT: vwaddu.vv v12, v11, v10
-; RV64-NEXT: vwmaccu.vx v12, a2, v10
+; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
+; RV64-NEXT: vmerge.vim v11, v8, 1, v0
+; RV64-NEXT: vwaddu.vv v12, v11, v9
+; RV64-NEXT: vwmaccu.vx v12, a2, v9
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a1, a1, 33
; RV64-NEXT: srli a2, a2, 2
; RV64-NEXT: srli a1, a1, 32
; RV64-NEXT: vmsne.vi v0, v12, 0
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vslidedown.vx v10, v12, a2
-; RV64-NEXT: vmerge.vim v9, v9, 1, v0
+; RV64-NEXT: vslidedown.vx v9, v12, a2
+; RV64-NEXT: vmerge.vim v10, v10, 1, v0
; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmsne.vi v0, v10, 0
-; RV64-NEXT: vmerge.vim v8, v13, 1, v0
-; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vslideup.vx v9, v8, a2
; RV64-NEXT: vmsne.vi v0, v9, 0
+; RV64-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; RV64-NEXT: vslideup.vx v10, v8, a2
+; RV64-NEXT: vmsne.vi v0, v10, 0
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma
; RV64-NEXT: vle32.v v10, (a0), v0.t
; RV64-NEXT: li a0, 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
index 40d781f403952..258014a023105 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
@@ -255,12 +255,12 @@ define <vscale x 32 x i8> @vpgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8
; RV32-NEXT: sltu a5, a1, a4
; RV32-NEXT: addi a5, a5, -1
; RV32-NEXT: and a4, a5, a4
-; RV32-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; RV32-NEXT: vmv1r.v v12, v0
-; RV32-NEXT: vslidedown.vx v0, v0, a3
; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vsext.vf4 v16, v10
-; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, ma
+; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; RV32-NEXT: vslidedown.vx v0, v0, a3
+; RV32-NEXT: vsetvli zero, a4, e8, m2, ta, ma
; RV32-NEXT: vluxei32.v v10, (a0), v16, v0.t
; RV32-NEXT: bltu a1, a2, .LBB12_2
; RV32-NEXT: # %bb.1:
@@ -277,33 +277,33 @@ define <vscale x 32 x i8> @vpgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8
; RV64: # %bb.0:
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a3, a2, 1
-; RV64-NEXT: srli a4, a2, 2
-; RV64-NEXT: sub a5, a1, a3
-; RV64-NEXT: vsetvli a6, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v12, v0
-; RV64-NEXT: vslidedown.vx v13, v0, a4
-; RV64-NEXT: sltu a4, a1, a5
-; RV64-NEXT: addi a4, a4, -1
-; RV64-NEXT: and a5, a4, a5
+; RV64-NEXT: srli a7, a2, 2
+; RV64-NEXT: sub a4, a1, a3
+; RV64-NEXT: sltu a5, a1, a4
+; RV64-NEXT: addi a5, a5, -1
+; RV64-NEXT: and a5, a5, a4
; RV64-NEXT: sub a4, a5, a2
; RV64-NEXT: sltu a6, a5, a4
; RV64-NEXT: addi a6, a6, -1
; RV64-NEXT: and a6, a6, a4
; RV64-NEXT: srli a4, a2, 3
-; RV64-NEXT: vmv1r.v v14, v13
-; RV64-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v0, v13, a4
; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v11
+; RV64-NEXT: vmv1r.v v12, v0
+; RV64-NEXT: vsetvli t0, zero, e8, mf2, ta, ma
+; RV64-NEXT: vslidedown.vx v11, v0, a7
+; RV64-NEXT: vmv1r.v v13, v11
+; RV64-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vx v0, v11, a4
; RV64-NEXT: bltu a5, a2, .LBB12_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a5, a2
; RV64-NEXT: .LBB12_2:
-; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, ma
+; RV64-NEXT: vsetvli zero, a6, e8, m1, ta, ma
; RV64-NEXT: vluxei64.v v11, (a0), v16, v0.t
; RV64-NEXT: vsetvli zero, a5, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v10
-; RV64-NEXT: vmv1r.v v0, v14
+; RV64-NEXT: vmv1r.v v0, v13
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; RV64-NEXT: vluxei64.v v10, (a0), v16, v0.t
; RV64-NEXT: bltu a1, a3, .LBB12_4
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
index 26e9bc1c97aa8..6ba9684228449 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
@@ -189,44 +189,44 @@ define <vscale x 128 x i1> @vpmerge_nxv128i1(<vscale x 128 x i1> %va, <vscale x
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v7, v12
; CHECK-NEXT: vmv1r.v v4, v11
-; CHECK-NEXT: vmv1r.v v6, v10
-; CHECK-NEXT: vmv1r.v v24, v9
-; CHECK-NEXT: vmv1r.v v5, v8
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: bltu a0, a2, .LBB7_2
+; CHECK-NEXT: vmv1r.v v5, v10
+; CHECK-NEXT: vmv1r.v v16, v9
+; CHECK-NEXT: vmv1r.v v6, v8
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: mv a2, a0
+; CHECK-NEXT: bltu a0, a1, .LBB7_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a2
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: sub a2, a0, a2
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
-; CHECK-NEXT: sltu a0, a0, a2
+; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
; CHECK-NEXT: vmv1r.v v0, v4
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
-; CHECK-NEXT: vmerge.vvm v24, v24, v16, v0
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmsne.vi v4, v24, 0
-; CHECK-NEXT: and a0, a0, a2
+; CHECK-NEXT: vsetvli zero, a2, e8, m8, tu, ma
+; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: vmv1r.v v0, v5
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
+; CHECK-NEXT: sub a1, a0, a1
+; CHECK-NEXT: sltu a0, a0, a1
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
+; CHECK-NEXT: vmsne.vi v6, v16, 0
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, ma
-; CHECK-NEXT: vmerge.vvm v24, v24, v16, v0
+; CHECK-NEXT: vmerge.vvm v24, v24, v8, v0
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vmsne.vi v8, v24, 0
-; CHECK-NEXT: vmv1r.v v0, v4
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: ret
%v = call <vscale x 128 x i1> @llvm.vp.merge.nxv128i1(<vscale x 128 x i1> %m, <vscale x 128 x i1> %va, <vscale x 128 x i1> %vb, i32 %evl)
ret <vscale x 128 x i1> %v
@@ -540,30 +540,30 @@ define <vscale x 128 x i8> @vpmerge_vv_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v6, v0
+; CHECK-NEXT: vmv8r.v v24, v16
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: sub a4, a3, a1
-; CHECK-NEXT: vl8r.v v24, (a2)
-; CHECK-NEXT: sltu a2, a3, a4
+; CHECK-NEXT: add a4, a0, a1
+; CHECK-NEXT: sub a5, a3, a1
+; CHECK-NEXT: vl8r.v v16, (a4)
+; CHECK-NEXT: sltu a4, a3, a5
+; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vl8r.v v8, (a0)
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a4
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, tu, ma
-; CHECK-NEXT: vmerge.vvm v24, v24, v16, v0
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a4, a4, a5
+; CHECK-NEXT: vsetvli zero, a4, e8, m8, tu, ma
+; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: bltu a3, a1, .LBB35_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: .LBB35_2:
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
-; CHECK-NEXT: vmv8r.v v16, v24
+; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -580,18 +580,18 @@ define <vscale x 128 x i8> @vpmerge_vx_nxv128i8(i8 %a, <vscale x 128 x i8> %vb,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: sub a3, a2, a1
-; CHECK-NEXT: sltu a4, a2, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, tu, ma
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0
-; CHECK-NEXT: bltu a2, a1, .LBB36_2
+; CHECK-NEXT: bltu a2, a3, .LBB36_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB36_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, tu, ma
@@ -608,18 +608,18 @@ define <vscale x 128 x i8> @vpmerge_vi_nxv128i8(<vscale x 128 x i8> %vb, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub a2, a1, a0
-; CHECK-NEXT: sltu a3, a1, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, tu, ma
+; CHECK-NEXT: sltu a0, a1, a3
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a3
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, ma
; CHECK-NEXT: vmerge.vim v16, v16, 2, v0
-; CHECK-NEXT: bltu a1, a0, .LBB37_2
+; CHECK-NEXT: bltu a1, a2, .LBB37_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: .LBB37_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
index 15b3508d8e20d..25e4f2cba1edf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
@@ -85,15 +85,15 @@ define half @vpreduce_ord_fadd_nxv4f16(half %s, <vscale x 4 x half> %v, <vscale
define half @vpreduce_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_fadd_nxv64f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: srli a1, a2, 1
-; CHECK-NEXT: slli a2, a2, 2
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v25, v0, a1
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a2, a3, 2
; CHECK-NEXT: sub a1, a0, a2
-; CHECK-NEXT: sltu a3, a0, a1
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a1, a3, a1
+; CHECK-NEXT: sltu a4, a0, a1
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a1, a4, a1
+; CHECK-NEXT: srli a3, a3, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v25, v0, a3
; CHECK-NEXT: bltu a0, a2, .LBB6_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
@@ -114,15 +114,15 @@ define half @vpreduce_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x
define half @vpreduce_ord_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_ord_fadd_nxv64f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: srli a1, a2, 1
-; CHECK-NEXT: slli a2, a2, 2
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v25, v0, a1
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a2, a3, 2
; CHECK-NEXT: sub a1, a0, a2
-; CHECK-NEXT: sltu a3, a0, a1
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a1, a3, a1
+; CHECK-NEXT: sltu a4, a0, a1
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a1, a4, a1
+; CHECK-NEXT: srli a3, a3, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v25, v0, a3
; CHECK-NEXT: bltu a0, a2, .LBB7_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
index 295d146ea7a7a..dcd1af0c12879 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
@@ -878,15 +878,15 @@ define signext i32 @vpreduce_umax_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v,
define signext i32 @vpreduce_umax_nxv32i32(i32 signext %s, <vscale x 32 x i32> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_umax_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: srli a2, a3, 2
-; CHECK-NEXT: slli a3, a3, 1
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v25, v0, a2
+; CHECK-NEXT: csrr a4, vlenb
+; CHECK-NEXT: slli a3, a4, 1
; CHECK-NEXT: sub a2, a1, a3
-; CHECK-NEXT: sltu a4, a1, a2
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a2, a4, a2
+; CHECK-NEXT: sltu a5, a1, a2
+; CHECK-NEXT: addi a5, a5, -1
+; CHECK-NEXT: and a2, a5, a2
+; CHECK-NEXT: srli a4, a4, 2
+; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v25, v0, a4
; CHECK-NEXT: bltu a1, a3, .LBB67_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, a3
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
index 1e629e9d20530..5c5293fcee622 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll
@@ -315,26 +315,26 @@ define zeroext i1 @vpreduce_or_nxv128i1(i1 zeroext %s, <vscale x 128 x i1> %v, <
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: sub a3, a1, a2
-; CHECK-NEXT: sltu a4, a1, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-NEXT: vcpop.m a3, v8, v0.t
-; CHECK-NEXT: snez a3, a3
-; CHECK-NEXT: bltu a1, a2, .LBB22_2
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: sub a2, a1, a3
+; CHECK-NEXT: sltu a4, a1, a2
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a2, a4, a2
+; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-NEXT: vcpop.m a2, v8, v0.t
+; CHECK-NEXT: snez a2, a2
+; CHECK-NEXT: bltu a1, a3, .LBB22_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a2
+; CHECK-NEXT: mv a1, a3
; CHECK-NEXT: .LBB22_2:
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vcpop.m a1, v11, v0.t
; CHECK-NEXT: snez a1, a1
; CHECK-NEXT: or a0, a1, a0
-; CHECK-NEXT: or a0, a3, a0
+; CHECK-NEXT: or a0, a2, a0
; CHECK-NEXT: ret
%r = call i1 @llvm.vp.reduce.or.nxv128i1(i1 %s, <vscale x 128 x i1> %v, <vscale x 128 x i1> %m, i32 %evl)
ret i1 %r
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
index e197ada5706ab..04dfcbe2945aa 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
@@ -553,18 +553,18 @@ define <vscale x 128 x i8> @vsadd_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub a2, a1, a0
-; CHECK-NEXT: sltu a3, a1, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-NEXT: sltu a0, a1, a3
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a3
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
-; CHECK-NEXT: bltu a1, a0, .LBB50_2
+; CHECK-NEXT: bltu a1, a2, .LBB50_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
@@ -1305,17 +1305,17 @@ define <vscale x 16 x i32> @vsadd_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vsadd_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB118_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
index c35b8af7ffc4f..cf6899fa4933b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
@@ -552,18 +552,18 @@ define <vscale x 128 x i8> @vsaddu_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub a2, a1, a0
-; CHECK-NEXT: sltu a3, a1, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-NEXT: sltu a0, a1, a3
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a3
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
-; CHECK-NEXT: bltu a1, a0, .LBB50_2
+; CHECK-NEXT: bltu a1, a2, .LBB50_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
@@ -1304,17 +1304,17 @@ define <vscale x 16 x i32> @vsaddu_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vsaddu_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB118_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll b/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
index 2a1bd8dd35a55..373044da3e02a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
@@ -436,16 +436,16 @@ define <vscale x 2 x i32> @vwop_vscale_zext_i1i32_multiple_users(ptr %x, ptr %y,
; NO_FOLDING: # %bb.0:
; NO_FOLDING-NEXT: vsetvli a3, zero, e32, m1, ta, mu
; NO_FOLDING-NEXT: vlm.v v0, (a0)
-; NO_FOLDING-NEXT: vlm.v v10, (a1)
-; NO_FOLDING-NEXT: vlm.v v11, (a2)
; NO_FOLDING-NEXT: vmv.v.i v8, 0
+; NO_FOLDING-NEXT: vlm.v v10, (a2)
+; NO_FOLDING-NEXT: vlm.v v11, (a1)
; NO_FOLDING-NEXT: vmerge.vim v8, v8, 1, v0
; NO_FOLDING-NEXT: vmv.v.v v9, v8
-; NO_FOLDING-NEXT: vmv.v.v v0, v11
-; NO_FOLDING-NEXT: vadd.vi v9, v8, 1, v0.t
; NO_FOLDING-NEXT: vmv.v.v v0, v10
-; NO_FOLDING-NEXT: vor.vv v9, v9, v8, v0.t
+; NO_FOLDING-NEXT: vadd.vi v9, v8, 1, v0.t
; NO_FOLDING-NEXT: vmv.v.v v0, v11
+; NO_FOLDING-NEXT: vor.vv v9, v9, v8, v0.t
+; NO_FOLDING-NEXT: vmv.v.v v0, v10
; NO_FOLDING-NEXT: vadd.vi v8, v8, -1, v0.t
; NO_FOLDING-NEXT: vor.vv v8, v9, v8
; NO_FOLDING-NEXT: ret
@@ -454,16 +454,16 @@ define <vscale x 2 x i32> @vwop_vscale_zext_i1i32_multiple_users(ptr %x, ptr %y,
; FOLDING: # %bb.0:
; FOLDING-NEXT: vsetvli a3, zero, e32, m1, ta, mu
; FOLDING-NEXT: vlm.v v0, (a0)
-; FOLDING-NEXT: vlm.v v10, (a1)
-; FOLDING-NEXT: vlm.v v11, (a2)
; FOLDING-NEXT: vmv.v.i v8, 0
+; FOLDING-NEXT: vlm.v v10, (a2)
+; FOLDING-NEXT: vlm.v v11, (a1)
; FOLDING-NEXT: vmerge.vim v8, v8, 1, v0
; FOLDING-NEXT: vmv.v.v v9, v8
-; FOLDING-NEXT: vmv.v.v v0, v11
-; FOLDING-NEXT: vadd.vi v9, v8, 1, v0.t
; FOLDING-NEXT: vmv.v.v v0, v10
-; FOLDING-NEXT: vor.vv v9, v9, v8, v0.t
+; FOLDING-NEXT: vadd.vi v9, v8, 1, v0.t
; FOLDING-NEXT: vmv.v.v v0, v11
+; FOLDING-NEXT: vor.vv v9, v9, v8, v0.t
+; FOLDING-NEXT: vmv.v.v v0, v10
; FOLDING-NEXT: vadd.vi v8, v8, -1, v0.t
; FOLDING-NEXT: vor.vv v8, v9, v8
; FOLDING-NEXT: ret
@@ -486,16 +486,16 @@ define <vscale x 2 x i8> @vwop_vscale_zext_i1i8_multiple_users(ptr %x, ptr %y, p
; NO_FOLDING: # %bb.0:
; NO_FOLDING-NEXT: vsetvli a3, zero, e8, mf4, ta, mu
; NO_FOLDING-NEXT: vlm.v v0, (a0)
-; NO_FOLDING-NEXT: vlm.v v10, (a1)
-; NO_FOLDING-NEXT: vlm.v v11, (a2)
; NO_FOLDING-NEXT: vmv.v.i v8, 0
+; NO_FOLDING-NEXT: vlm.v v10, (a2)
+; NO_FOLDING-NEXT: vlm.v v11, (a1)
; NO_FOLDING-NEXT: vmerge.vim v8, v8, 1, v0
; NO_FOLDING-NEXT: vmv1r.v v9, v8
-; NO_FOLDING-NEXT: vmv1r.v v0, v11
-; NO_FOLDING-NEXT: vadd.vi v9, v8, 1, v0.t
; NO_FOLDING-NEXT: vmv1r.v v0, v10
-; NO_FOLDING-NEXT: vor.vv v9, v9, v8, v0.t
+; NO_FOLDING-NEXT: vadd.vi v9, v8, 1, v0.t
; NO_FOLDING-NEXT: vmv1r.v v0, v11
+; NO_FOLDING-NEXT: vor.vv v9, v9, v8, v0.t
+; NO_FOLDING-NEXT: vmv1r.v v0, v10
; NO_FOLDING-NEXT: vadd.vi v8, v8, -1, v0.t
; NO_FOLDING-NEXT: vor.vv v8, v9, v8
; NO_FOLDING-NEXT: ret
@@ -504,16 +504,16 @@ define <vscale x 2 x i8> @vwop_vscale_zext_i1i8_multiple_users(ptr %x, ptr %y, p
; FOLDING: # %bb.0:
; FOLDING-NEXT: vsetvli a3, zero, e8, mf4, ta, mu
; FOLDING-NEXT: vlm.v v0, (a0)
-; FOLDING-NEXT: vlm.v v10, (a1)
-; FOLDING-NEXT: vlm.v v11, (a2)
; FOLDING-NEXT: vmv.v.i v8, 0
+; FOLDING-NEXT: vlm.v v10, (a2)
+; FOLDING-NEXT: vlm.v v11, (a1)
; FOLDING-NEXT: vmerge.vim v8, v8, 1, v0
; FOLDING-NEXT: vmv1r.v v9, v8
-; FOLDING-NEXT: vmv1r.v v0, v11
-; FOLDING-NEXT: vadd.vi v9, v8, 1, v0.t
; FOLDING-NEXT: vmv1r.v v0, v10
-; FOLDING-NEXT: vor.vv v9, v9, v8, v0.t
+; FOLDING-NEXT: vadd.vi v9, v8, 1, v0.t
; FOLDING-NEXT: vmv1r.v v0, v11
+; FOLDING-NEXT: vor.vv v9, v9, v8, v0.t
+; FOLDING-NEXT: vmv1r.v v0, v10
; FOLDING-NEXT: vadd.vi v8, v8, -1, v0.t
; FOLDING-NEXT: vor.vv v8, v9, v8
; FOLDING-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
index 1391f0a564708..759880629ecff 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
@@ -494,17 +494,17 @@ define <vscale x 8 x double> @vfmerge_nzv_nxv8f64(<vscale x 8 x double> %va, <vs
define <vscale x 16 x double> @vselect_combine_regression(<vscale x 16 x i64> %va, <vscale x 16 x double> %vb) {
; CHECK-LABEL: vselect_combine_regression:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmseq.vi v24, v16, 0
-; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; CHECK-NEXT: vmv8r.v v24, v16
; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: vle64.v v8, (a0), v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vle64.v v16, (a1), v0.t
+; CHECK-NEXT: vmseq.vi v0, v24, 0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vle64.v v16, (a0), v0.t
; CHECK-NEXT: ret
%cond = icmp eq <vscale x 16 x i64> %va, zeroinitializer
%sel = select <vscale x 16 x i1> %cond, <vscale x 16 x double> %vb, <vscale x 16 x double> zeroinitializer
@@ -523,11 +523,11 @@ define void @vselect_legalize_regression(<vscale x 16 x double> %a, <vscale x 16
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
; CHECK-NEXT: vmand.mm v0, v0, v7
+; CHECK-NEXT: vsetvli a3, zero, e64, m8, ta, ma
+; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vx v7, v0, a2
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: add a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
index 61de230f9c8d1..7f594f398288a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
@@ -137,17 +137,17 @@ define <vscale x 2 x i64> @vsext_nxv2i32_nxv2i64_unmasked(<vscale x 2 x i32> %a,
define <vscale x 32 x i32> @vsext_nxv32i8_nxv32i32(<vscale x 32 x i8> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vsext_nxv32i8_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vsext.vf4 v16, v10, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB12_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
index 6a96645620d0c..2f79cf0df6645 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
@@ -471,17 +471,17 @@ define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i64_unmasked(<vscale x 2 x i64
define <vscale x 32 x half> @vsitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: vsitofp_nxv32f16_nxv32i32:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: csrr a1, vlenb
-; ZVFH-NEXT: srli a2, a1, 2
-; ZVFH-NEXT: slli a1, a1, 1
-; ZVFH-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a1, a2, 1
+; ZVFH-NEXT: sub a3, a0, a1
+; ZVFH-NEXT: sltu a4, a0, a3
+; ZVFH-NEXT: addi a4, a4, -1
+; ZVFH-NEXT: and a3, a4, a3
+; ZVFH-NEXT: srli a2, a2, 2
+; ZVFH-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFH-NEXT: vmv1r.v v24, v0
; ZVFH-NEXT: vslidedown.vx v0, v0, a2
-; ZVFH-NEXT: sub a2, a0, a1
-; ZVFH-NEXT: sltu a3, a0, a2
-; ZVFH-NEXT: addi a3, a3, -1
-; ZVFH-NEXT: and a2, a3, a2
-; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFH-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFH-NEXT: vfncvt.f.x.w v28, v16, v0.t
; ZVFH-NEXT: bltu a0, a1, .LBB34_2
; ZVFH-NEXT: # %bb.1:
@@ -495,17 +495,17 @@ define <vscale x 32 x half> @vsitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va,
;
; ZVFHMIN-LABEL: vsitofp_nxv32f16_nxv32i32:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: srli a2, a1, 2
-; ZVFHMIN-NEXT: slli a1, a1, 1
-; ZVFHMIN-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a1, a2, 1
+; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
+; ZVFHMIN-NEXT: srli a2, a2, 2
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
-; ZVFHMIN-NEXT: sub a2, a0, a1
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
-; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v24
@@ -527,17 +527,17 @@ define <vscale x 32 x half> @vsitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va,
define <vscale x 32 x float> @vsitofp_nxv32f32_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_nxv32f32_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB35_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
index 6c0160591f245..2acc910226174 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
@@ -570,23 +570,23 @@ define <vscale x 128 x i8> @vssub_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: sub a3, a1, a2
+; CHECK-NEXT: sltu a4, a1, a3
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub a2, a1, a0
-; CHECK-NEXT: sltu a3, a1, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a3, a3, a2
-; CHECK-NEXT: li a2, -1
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v16, v16, a2, v0.t
-; CHECK-NEXT: bltu a1, a0, .LBB50_2
+; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t
+; CHECK-NEXT: bltu a1, a2, .LBB50_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a2, v0.t
+; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 128 x i8> @llvm.vp.ssub.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> %m, i32 %evl)
ret <vscale x 128 x i8> %v
@@ -1346,18 +1346,18 @@ define <vscale x 16 x i32> @vssub_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vssub_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a1, a3, 1
; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a3, a3, a2
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a4, a4, a2
; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: srli a3, a3, 2
+; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vssub.vx v16, v16, a2, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB118_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
index a041b8478b0bb..3d2fb62ef39a5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
@@ -568,23 +568,23 @@ define <vscale x 128 x i8> @vssubu_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: sub a3, a1, a2
+; CHECK-NEXT: sltu a4, a1, a3
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub a2, a1, a0
-; CHECK-NEXT: sltu a3, a1, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a3, a3, a2
-; CHECK-NEXT: li a2, -1
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v16, v16, a2, v0.t
-; CHECK-NEXT: bltu a1, a0, .LBB50_2
+; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t
+; CHECK-NEXT: bltu a1, a2, .LBB50_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a2, v0.t
+; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 128 x i8> @llvm.vp.usub.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> %m, i32 %evl)
ret <vscale x 128 x i8> %v
@@ -1344,18 +1344,18 @@ define <vscale x 16 x i32> @vssubu_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vssubu_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a1, a3, 1
; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a3, a3, a2
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a4, a4, a2
; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: srli a3, a3, 2
+; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vssubu.vx v16, v16, a2, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB118_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
index 63f6cadbc123c..12d2f73f7baa9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
@@ -142,14 +142,14 @@ define <vscale x 15 x i16> @vtrunc_nxv15i16_nxv15i64(<vscale x 15 x i64> %a, <vs
; CHECK-LABEL: vtrunc_nxv15i16_nxv15i64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v28, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
@@ -194,17 +194,17 @@ define <vscale x 2 x i32> @vtrunc_nxv2i32_nxv2i64_unmasked(<vscale x 2 x i64> %a
define <vscale x 32 x i7> @vtrunc_nxv32i7_nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv32i7_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v28, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v18, v24, 0, v0.t
@@ -226,17 +226,17 @@ define <vscale x 32 x i7> @vtrunc_nxv32i7_nxv32i32(<vscale x 32 x i32> %a, <vsca
define <vscale x 32 x i8> @vtrunc_nxv32i8_nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv32i8_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v28, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v18, v24, 0, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
index a23fb0c7db18b..ef376162a8022 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
@@ -471,17 +471,17 @@ define <vscale x 2 x double> @vuitofp_nxv2f64_nxv2i64_unmasked(<vscale x 2 x i64
define <vscale x 32 x half> @vuitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: vuitofp_nxv32f16_nxv32i32:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: csrr a1, vlenb
-; ZVFH-NEXT: srli a2, a1, 2
-; ZVFH-NEXT: slli a1, a1, 1
-; ZVFH-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a1, a2, 1
+; ZVFH-NEXT: sub a3, a0, a1
+; ZVFH-NEXT: sltu a4, a0, a3
+; ZVFH-NEXT: addi a4, a4, -1
+; ZVFH-NEXT: and a3, a4, a3
+; ZVFH-NEXT: srli a2, a2, 2
+; ZVFH-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFH-NEXT: vmv1r.v v24, v0
; ZVFH-NEXT: vslidedown.vx v0, v0, a2
-; ZVFH-NEXT: sub a2, a0, a1
-; ZVFH-NEXT: sltu a3, a0, a2
-; ZVFH-NEXT: addi a3, a3, -1
-; ZVFH-NEXT: and a2, a3, a2
-; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFH-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFH-NEXT: vfncvt.f.xu.w v28, v16, v0.t
; ZVFH-NEXT: bltu a0, a1, .LBB34_2
; ZVFH-NEXT: # %bb.1:
@@ -495,17 +495,17 @@ define <vscale x 32 x half> @vuitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va,
;
; ZVFHMIN-LABEL: vuitofp_nxv32f16_nxv32i32:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: srli a2, a1, 2
-; ZVFHMIN-NEXT: slli a1, a1, 1
-; ZVFHMIN-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a1, a2, 1
+; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
+; ZVFHMIN-NEXT: srli a2, a2, 2
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
-; ZVFHMIN-NEXT: sub a2, a0, a1
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
-; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.f.xu.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v24
@@ -527,17 +527,17 @@ define <vscale x 32 x half> @vuitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va,
define <vscale x 32 x float> @vuitofp_nxv32f32_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_nxv32f32_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB35_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
index d3ec428c825ee..78ec7457e4064 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
@@ -137,17 +137,17 @@ define <vscale x 2 x i64> @vzext_nxv2i32_nxv2i64_unmasked(<vscale x 2 x i32> %a,
define <vscale x 32 x i32> @vzext_nxv32i8_nxv32i32(<vscale x 32 x i8> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vzext_nxv32i8_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vzext.vf4 v16, v10, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB12_2
; CHECK-NEXT: # %bb.1:
>From 5f8019be5952efa8cc70f90991311df9e6afc97f Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Wed, 21 Jan 2026 19:28:59 +0800
Subject: [PATCH 4/5] [RISCV] Change the limit of register pressure VMV0 to 2
---
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 2 +-
.../CodeGen/RISCV/combine-storetomstore.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/abs-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll | 60 +-
llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll | 8 +-
.../RISCV/rvv/combine-reduce-add-to-vcpop.ll | 374 ++---
.../RISCV/rvv/constant-folding-crash.ll | 10 +-
llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll | 72 +-
llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll | 187 +--
llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll | 88 +-
llvm/test/CodeGen/RISCV/rvv/expandload.ll | 309 ++--
llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll | 42 +-
.../CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-bitreverse-vp.ll | 61 +-
.../RISCV/rvv/fixed-vectors-bswap-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-ceil-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-ctlz-vp.ll | 1034 +++++++++-----
.../RISCV/rvv/fixed-vectors-ctpop-vp.ll | 362 ++---
.../RISCV/rvv/fixed-vectors-cttz-vp.ll | 888 +++++++-----
.../RISCV/rvv/fixed-vectors-extract-i1.ll | 108 +-
.../RISCV/rvv/fixed-vectors-floor-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-fmaximum-vp.ll | 27 +-
.../RISCV/rvv/fixed-vectors-fminimum-vp.ll | 27 +-
.../RISCV/rvv/fixed-vectors-fpext-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-fptosi-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-fptoui-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-fptrunc-vp.ll | 2 +-
.../rvv/fixed-vectors-interleaved-access.ll | 593 ++++----
.../rvv/fixed-vectors-reduction-fp-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-reduction-fp.ll | 150 +-
.../rvv/fixed-vectors-reduction-int-vp.ll | 4 +-
.../rvv/fixed-vectors-reduction-mask-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-round-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-roundeven-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-roundtozero-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-setcc-int-vp.ll | 30 +-
.../RISCV/rvv/fixed-vectors-sext-vp.ll | 2 +-
.../rvv/fixed-vectors-shuffle-deinterleave.ll | 6 +-
.../fixed-vectors-shuffle-deinterleave2.ll | 13 +-
.../RISCV/rvv/fixed-vectors-sitofp-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-strided-vpload.ll | 29 +-
.../RISCV/rvv/fixed-vectors-trunc-vp.ll | 566 ++++----
.../RISCV/rvv/fixed-vectors-uitofp-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-vadd-vp.ll | 15 +-
.../RISCV/rvv/fixed-vectors-vfabs-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-vfneg-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-vfsqrt-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-vmax-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-vmaxu-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-vmin-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-vminu-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-vsadd-vp.ll | 15 +-
.../RISCV/rvv/fixed-vectors-vsaddu-vp.ll | 15 +-
.../RISCV/rvv/fixed-vectors-vselect-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-vssub-vp.ll | 13 +-
.../RISCV/rvv/fixed-vectors-vssubu-vp.ll | 13 +-
.../RISCV/rvv/fixed-vectors-zext-vp.ll | 2 +-
llvm/test/CodeGen/RISCV/rvv/floor-vp.ll | 8 +-
.../test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll | 66 +-
llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll | 121 +-
.../test/CodeGen/RISCV/rvv/fminimum-sdnode.ll | 66 +-
llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll | 121 +-
llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll | 141 +-
.../CodeGen/RISCV/rvv/insert-subvector.ll | 2 +-
llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll | 10 +-
.../test/CodeGen/RISCV/rvv/mscatter-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll | 16 +-
llvm/test/CodeGen/RISCV/rvv/pr165232.ll | 309 ++--
.../CodeGen/RISCV/rvv/reproducer-pr146855.ll | 3 +-
llvm/test/CodeGen/RISCV/rvv/round-vp.ll | 8 +-
llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll | 8 +-
llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll | 8 +-
llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll | 72 +-
llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll | 64 +-
llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll | 44 +-
.../RISCV/rvv/vector-deinterleave-fixed.ll | 18 +-
.../CodeGen/RISCV/rvv/vector-deinterleave.ll | 170 +--
.../RISCV/rvv/vector-interleave-store.ll | 12 +-
.../CodeGen/RISCV/rvv/vector-interleave.ll | 268 ++--
llvm/test/CodeGen/RISCV/rvv/vector-splice.ll | 308 ++--
llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll | 174 +--
llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll | 72 +-
llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll | 1269 +++++++----------
llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll | 18 +-
llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll | 72 +-
llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll | 44 +-
llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll | 44 +-
llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll | 44 +-
llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll | 44 +-
llvm/test/CodeGen/RISCV/rvv/vmseq.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmsge.ll | 32 +-
llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll | 32 +-
llvm/test/CodeGen/RISCV/rvv/vmsgt.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmsle.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmsleu.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmslt.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmsltu.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmsne.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll | 4 +-
.../rvv/vp-reverse-mask-fixed-vectors.ll | 16 +-
.../test/CodeGen/RISCV/rvv/vp-reverse-mask.ll | 28 +-
.../RISCV/rvv/vp-splice-mask-fixed-vectors.ll | 64 +-
.../RISCV/rvv/vp-splice-mask-vectors.ll | 112 +-
.../RISCV/rvv/vp-vector-interleaved-access.ll | 62 +-
.../test/CodeGen/RISCV/rvv/vpgather-sdnode.ll | 28 +-
llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll | 60 +-
.../CodeGen/RISCV/rvv/vreductions-fp-vp.ll | 32 +-
.../CodeGen/RISCV/rvv/vreductions-int-vp.ll | 16 +-
llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll | 36 +-
.../RISCV/rvv/vscale-vw-web-simplification.ll | 8 +-
llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll | 22 +-
llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll | 18 +-
llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll | 54 +-
llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll | 42 +-
llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll | 42 +-
llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll | 48 +-
llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll | 54 +-
llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll | 18 +-
133 files changed, 5430 insertions(+), 4849 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 7535da24d8524..eeba182d1ad30 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -862,7 +862,7 @@ float RISCVRegisterInfo::getSpillWeightScaleFactor(
unsigned RISCVRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF,
unsigned Idx) const {
if (Idx == RISCV::RegisterPressureSets::VMV0)
- return 1;
+ return 2;
return RISCVGenRegisterInfo::getRegPressureSetLimit(MF, Idx);
}
diff --git a/llvm/test/CodeGen/RISCV/combine-storetomstore.ll b/llvm/test/CodeGen/RISCV/combine-storetomstore.ll
index ad0bcf57c78a9..19882d41b5445 100644
--- a/llvm/test/CodeGen/RISCV/combine-storetomstore.ll
+++ b/llvm/test/CodeGen/RISCV/combine-storetomstore.ll
@@ -212,10 +212,10 @@ define void @test_masked_store_success_v8f16(<8 x half> %x, ptr %ptr, <8 x i1> %
; RISCV-NEXT: vmv1r.v v13, v0
; RISCV-NEXT: vmerge.vim v8, v9, 1, v0
; RISCV-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RISCV-NEXT: vslidedown.vi v10, v8, 2
+; RISCV-NEXT: vslidedown.vi v8, v8, 2
; RISCV-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
+; RISCV-NEXT: vmsne.vi v0, v8, 0
; RISCV-NEXT: vmv.v.i v8, 0
-; RISCV-NEXT: vmsne.vi v0, v10, 0
; RISCV-NEXT: vmv1r.v v12, v0
; RISCV-NEXT: vmerge.vim v10, v8, 1, v0
; RISCV-NEXT: vslidedown.vi v10, v10, 1
@@ -567,10 +567,10 @@ define void @test_masked_store_multiple_v8i32(<8 x i32> %x, <8 x i32> %y, ptr %p
; RISCV-LABEL: test_masked_store_multiple_v8i32:
; RISCV: # %bb.0:
; RISCV-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RISCV-NEXT: vle32.v v16, (a1)
+; RISCV-NEXT: vle32.v v14, (a1)
; RISCV-NEXT: vse32.v v8, (a0), v0.t
; RISCV-NEXT: vmv1r.v v0, v12
-; RISCV-NEXT: vmerge.vvm v8, v16, v10, v0
+; RISCV-NEXT: vmerge.vvm v8, v14, v10, v0
; RISCV-NEXT: vse32.v v8, (a1)
; RISCV-NEXT: ret
%load = load <8 x i32>, ptr %ptr1, align 32
@@ -586,10 +586,10 @@ define void @test_masked_store_multiple_v8i64(<8 x i64> %x, <8 x i64> %y, ptr %p
; RISCV-LABEL: test_masked_store_multiple_v8i64:
; RISCV: # %bb.0:
; RISCV-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RISCV-NEXT: vle64.v v24, (a1)
+; RISCV-NEXT: vle64.v v20, (a1)
; RISCV-NEXT: vse64.v v8, (a0), v0.t
; RISCV-NEXT: vmv1r.v v0, v16
-; RISCV-NEXT: vmerge.vvm v8, v24, v12, v0
+; RISCV-NEXT: vmerge.vvm v8, v20, v12, v0
; RISCV-NEXT: vse64.v v8, (a1)
; RISCV-NEXT: ret
%load = load <8 x i64>, ptr %ptr1, align 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
index 77fcd3f4a3506..dbe3609d61934 100644
--- a/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
@@ -514,14 +514,14 @@ define <vscale x 16 x i64> @vp_abs_nxv16i64(<vscale x 16 x i64> %va, <vscale x 1
; CHECK-LABEL: vp_abs_nxv16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: srli a3, a1, 3
+; CHECK-NEXT: srli a2, a1, 3
+; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v16, 0, v0.t
; CHECK-NEXT: vmax.vv v16, v16, v24, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
index a13ab90bfb8f4..5c7667b902863 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
@@ -3327,23 +3327,23 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64_unmasked(<vscale x 8 x i64> %va
define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv64i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: lui a2, 1
-; CHECK-NEXT: lui a5, 3
-; CHECK-NEXT: slli a3, a1, 2
-; CHECK-NEXT: sub a4, a0, a3
-; CHECK-NEXT: sltu a6, a0, a4
-; CHECK-NEXT: addi a6, a6, -1
-; CHECK-NEXT: and a6, a6, a4
-; CHECK-NEXT: lui a7, 5
-; CHECK-NEXT: srli t0, a1, 1
-; CHECK-NEXT: addi a4, a2, -241
-; CHECK-NEXT: addi a2, a5, 819
-; CHECK-NEXT: addi a1, a7, 1365
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: lui a1, 1
+; CHECK-NEXT: lui a3, 3
+; CHECK-NEXT: srli a4, a2, 1
+; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: vsetvli a5, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, t0
-; CHECK-NEXT: vsetvli zero, a6, e16, m8, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a4
+; CHECK-NEXT: sub a4, a0, a2
+; CHECK-NEXT: sltu a5, a0, a4
+; CHECK-NEXT: addi a5, a5, -1
+; CHECK-NEXT: and a5, a5, a4
+; CHECK-NEXT: lui a6, 5
+; CHECK-NEXT: addi a4, a1, -241
+; CHECK-NEXT: addi a3, a3, 819
+; CHECK-NEXT: addi a1, a6, 1365
+; CHECK-NEXT: vsetvli zero, a5, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
@@ -3353,8 +3353,8 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: vsrl.vi v24, v16, 2, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a2, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a3, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a3, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: vsrl.vi v24, v16, 1, v0.t
@@ -3362,9 +3362,9 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 1, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
-; CHECK-NEXT: bltu a0, a3, .LBB46_2
+; CHECK-NEXT: bltu a0, a2, .LBB46_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a3
+; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: .LBB46_2:
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -3377,8 +3377,8 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
; CHECK-NEXT: vsrl.vi v24, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a2, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a3, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
; CHECK-NEXT: vsrl.vi v24, v8, 1, v0.t
@@ -3390,17 +3390,17 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv64i16:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: csrr a2, vlenb
-; CHECK-ZVBB-NEXT: slli a1, a2, 2
-; CHECK-ZVBB-NEXT: sub a3, a0, a1
-; CHECK-ZVBB-NEXT: sltu a4, a0, a3
-; CHECK-ZVBB-NEXT: addi a4, a4, -1
-; CHECK-ZVBB-NEXT: and a3, a4, a3
-; CHECK-ZVBB-NEXT: srli a2, a2, 1
-; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; CHECK-ZVBB-NEXT: csrr a1, vlenb
+; CHECK-ZVBB-NEXT: srli a2, a1, 1
+; CHECK-ZVBB-NEXT: slli a1, a1, 2
+; CHECK-ZVBB-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-ZVBB-NEXT: vsetvli zero, a3, e16, m8, ta, ma
+; CHECK-ZVBB-NEXT: sub a2, a0, a1
+; CHECK-ZVBB-NEXT: sltu a3, a0, a2
+; CHECK-ZVBB-NEXT: addi a3, a3, -1
+; CHECK-ZVBB-NEXT: and a2, a3, a2
+; CHECK-ZVBB-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v16, v16, v0.t
; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB46_2
; CHECK-ZVBB-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
index 8ef3c228b3f29..fc2940e1649b2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
@@ -1819,17 +1819,17 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32
define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv64i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a1, a2, 2
-; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: srli a2, a2, 1
-; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a2, a1, 1
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
@@ -1846,17 +1846,17 @@ define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv64i16:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: csrr a2, vlenb
-; CHECK-ZVKB-NEXT: slli a1, a2, 2
-; CHECK-ZVKB-NEXT: sub a3, a0, a1
-; CHECK-ZVKB-NEXT: sltu a4, a0, a3
-; CHECK-ZVKB-NEXT: addi a4, a4, -1
-; CHECK-ZVKB-NEXT: and a3, a4, a3
-; CHECK-ZVKB-NEXT: srli a2, a2, 1
-; CHECK-ZVKB-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; CHECK-ZVKB-NEXT: csrr a1, vlenb
+; CHECK-ZVKB-NEXT: srli a2, a1, 1
+; CHECK-ZVKB-NEXT: slli a1, a1, 2
+; CHECK-ZVKB-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-ZVKB-NEXT: vmv1r.v v24, v0
; CHECK-ZVKB-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-ZVKB-NEXT: vsetvli zero, a3, e16, m8, ta, ma
+; CHECK-ZVKB-NEXT: sub a2, a0, a1
+; CHECK-ZVKB-NEXT: sltu a3, a0, a2
+; CHECK-ZVKB-NEXT: addi a3, a3, -1
+; CHECK-ZVKB-NEXT: and a2, a3, a2
+; CHECK-ZVKB-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v16, v16, v0.t
; CHECK-ZVKB-NEXT: bltu a0, a1, .LBB32_2
; CHECK-ZVKB-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
index 2af49bd353f68..b84878f227a7a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
@@ -17,12 +17,12 @@ define <vscale x 1 x bfloat> @vp_ceil_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -67,12 +67,12 @@ define <vscale x 2 x bfloat> @vp_ceil_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
@@ -410,12 +410,12 @@ define <vscale x 1 x half> @vp_ceil_vv_nxv1f16(<vscale x 1 x half> %va, <vscale
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -494,12 +494,12 @@ define <vscale x 2 x half> @vp_ceil_vv_nxv2f16(<vscale x 2 x half> %va, <vscale
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll b/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
index dfd057c9d7dea..d963665f50028 100644
--- a/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
@@ -95,40 +95,25 @@ define i32 @test_v256i1(<256 x i1> %x) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a1, a1, a0
-; CHECK-NEXT: slli a0, a0, 2
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x22, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 34 * vlenb
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vmv1r.v v16, v8
+; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v26, v16, 8
-; CHECK-NEXT: vmv1r.v v25, v16
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v26, 4
-; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a2, a1, 5
-; CHECK-NEXT: add a1, a2, a1
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v25, 4
+; CHECK-NEXT: vslidedown.vi v0, v7, 4
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
@@ -139,85 +124,101 @@ define i32 @test_v256i1(<256 x i1> %x) {
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a2, a1, 4
-; CHECK-NEXT: add a1, a2, a1
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v26
-; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a2, a1, 3
-; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v25
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
; CHECK-NEXT: vadd.vv v16, v24, v16
; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v0, 8
-; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vslidedown.vi v16, v7, 8
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a2, a1, 5
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs1r.v v16, (a1) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vslidedown.vi v16, v0, 8
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 5
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs1r.v v16, (a1) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a2, a1, 5
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a2, a1, 3
-; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: slli a1, a1, 5
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vv v24, v24, v16
+; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT: vadd.vv v16, v16, v24
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a2, a1, 4
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v24, v24, v16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a2, a1, 5
; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vv v16, v0, v16
-; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vl1r.v v7, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vl1r.v v16, (a1) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v7, 4
+; CHECK-NEXT: vslidedown.vi v0, v16, 4
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 5
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl1r.v v16, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vslidedown.vi v7, v16, 4
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a1, a0, 5
-; CHECK-NEXT: add a0, a1, a0
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vv v8, v8, v0
-; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vv v24, v0, v24
-; CHECK-NEXT: vadd.vv v8, v16, v8
+; CHECK-NEXT: vadd.vv v16, v16, v0
; CHECK-NEXT: vadd.vv v8, v24, v8
+; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vmv.s.x v16, zero
; CHECK-NEXT: vredsum.vs v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add sp, sp, a1
; CHECK-NEXT: .cfi_def_cfa sp, 16
@@ -336,9 +337,9 @@ define i32 @test_nxv128i1(<vscale x 128 x i1> %x) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vmv1r.v v7, v8
@@ -349,63 +350,45 @@ define i32 @test_nxv128i1(<vscale x 128 x i1> %x) {
; CHECK-NEXT: vslidedown.vx v0, v0, a1
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a0
+; CHECK-NEXT: vslidedown.vx v0, v9, a0
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a1
-; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v7, a1
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v7, a0
+; CHECK-NEXT: vslidedown.vx v7, v7, a0
+; CHECK-NEXT: vmv1r.v v6, v0
+; CHECK-NEXT: vmv.v.v v0, v7
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
; CHECK-NEXT: vadd.vv v8, v24, v8
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a1
+; CHECK-NEXT: vslidedown.vx v0, v6, a1
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
+; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
+; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v7, a1
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vadd.vv v16, v24, v16
; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vmv.s.x v16, zero
; CHECK-NEXT: vredsum.vs v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add sp, sp, a1
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -423,110 +406,128 @@ define i32 @test_nxv256i1(<vscale x 256 x i1> %x) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a1, a1, a0
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x32, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 50 * vlenb
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v6, v10
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 5
+; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs1r.v v10, (a0) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vmv1r.v v7, v9
-; CHECK-NEXT: vmv.v.i v24, 0
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a0, a1, 2
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a0
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
+; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: add a3, a3, a2
; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, a0
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
+; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a3, a2, 5
-; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: srli a1, a1, 1
; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
+; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v11, a1
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
+; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: slli a3, a2, 4
; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a0
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
+; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a3, a2, 4
-; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a3, a3, a2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v8, v24, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
+; CHECK-NEXT: vmv8r.v v24, v16
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a1
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
+; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a0
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v24, v24, 1, v0
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a3, a3, a2
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: slli a3, a2, 3
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v6, a0
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a3, a2, 5
-; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a3, a2, 5
-; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v7, a0
; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: add a3, a3, a2
; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: add a2, a2, a3
@@ -536,99 +537,96 @@ define i32 @test_nxv256i1(<vscale x 256 x i1> %x) {
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: add a3, a3, a2
; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v6, a1
-; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
-; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a0
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a3, a3, a2
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
+; CHECK-NEXT: vadd.vv v8, v24, v8
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a3, a3, a2
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vs1r.v v7, (a2) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
-; CHECK-NEXT: vadd.vv v8, v24, v8
+; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: add a3, a3, a2
; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v8, v24, v8
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a3, a2, 5
-; CHECK-NEXT: add a2, a3, a2
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vv v24, v24, v0
-; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: add a3, a3, a2
; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vl1r.v v24, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v24, a1
+; CHECK-NEXT: vslidedown.vx v7, v0, a1
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v8, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vslidedown.vx v0, v8, a1
+; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
+; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
+; CHECK-NEXT: vmv1r.v v6, v0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a2, a1, 4
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
+; CHECK-NEXT: vadd.vv v24, v8, v16
+; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v6, a0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a2, a1, 3
; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
-; CHECK-NEXT: vadd.vv v16, v24, v16
+; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a0
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a1, a0, 4
-; CHECK-NEXT: add a0, a1, a0
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
+; CHECK-NEXT: vslidedown.vx v0, v7, a0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: slli a0, a0, 3
@@ -637,26 +635,34 @@ define i32 @test_nxv256i1(<vscale x 256 x i1> %x) {
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vv v24, v24, v0
-; CHECK-NEXT: vadd.vv v8, v8, v16
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
+; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
+; CHECK-NEXT: vadd.vv v0, v8, v16
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v16, v8, v24
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add a1, a1, a0
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vv v16, v16, v24
-; CHECK-NEXT: vadd.vv v8, v8, v16
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v8, v8, v0
+; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vmv.s.x v16, zero
; CHECK-NEXT: vredsum.vs v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a2, a2, a1
; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a1, a1, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll b/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
index 4572658c5985f..f05f07eacaf4c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
@@ -23,17 +23,16 @@ define void @constant_folding_crash(ptr %v54, <4 x ptr> %lanes.a, <4 x ptr> %lan
; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vmerge.vim v10, v10, 1, v0
; RV32-NEXT: vrgather.vi v11, v10, 0
+; RV32-NEXT: vmsne.vi v11, v11, 0
; RV32-NEXT: andi a0, a0, 1
; RV32-NEXT: seqz a0, a0
; RV32-NEXT: vmv.v.x v10, a0
; RV32-NEXT: vmsne.vi v0, v10, 0
; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
-; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; RV32-NEXT: vmsne.vi v0, v11, 0
-; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: vmv.v.i v8, 10
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: vse32.v v8, (a0), v0.t
; RV32-NEXT: ret
;
@@ -44,18 +43,17 @@ define void @constant_folding_crash(ptr %v54, <4 x ptr> %lanes.a, <4 x ptr> %lan
; RV64-NEXT: vmv.v.i v12, 0
; RV64-NEXT: vmerge.vim v12, v12, 1, v0
; RV64-NEXT: vrgather.vi v13, v12, 0
+; RV64-NEXT: vmsne.vi v13, v13, 0
; RV64-NEXT: andi a0, a0, 1
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vmsne.vi v0, v12, 0
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vmerge.vvm v8, v10, v8, v0
-; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmsne.vi v0, v13, 0
-; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV64-NEXT: vmv.v.i v8, 10
+; RV64-NEXT: vmv1r.v v0, v13
; RV64-NEXT: vse32.v v8, (a0), v0.t
; RV64-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
index 5a465219b2124..b2d5fb276ba66 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
@@ -1188,24 +1188,24 @@ define <vscale x 16 x i64> @vp_ctlz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; CHECK-LABEL: vp_ctlz_nxv16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: fsrmi a5, 1
+; CHECK-NEXT: fsrmi a4, 1
; CHECK-NEXT: li a2, 52
-; CHECK-NEXT: li a3, 1086
-; CHECK-NEXT: li a4, 64
-; CHECK-NEXT: sub a6, a0, a1
-; CHECK-NEXT: sltu a7, a0, a6
-; CHECK-NEXT: addi a7, a7, -1
-; CHECK-NEXT: and a6, a7, a6
-; CHECK-NEXT: srli a7, a1, 3
-; CHECK-NEXT: vsetvli t0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: srli a3, a1, 3
+; CHECK-NEXT: sub a5, a0, a1
+; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a7
-; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-NEXT: sltu a3, a0, a5
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a5, a3, a5
+; CHECK-NEXT: li a3, 1086
+; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma
; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t
+; CHECK-NEXT: fsrm a4
; CHECK-NEXT: vsrl.vx v16, v16, a2, v0.t
; CHECK-NEXT: vrsub.vx v16, v16, a3, v0.t
+; CHECK-NEXT: li a4, 64
; CHECK-NEXT: vminu.vx v16, v16, a4, v0.t
-; CHECK-NEXT: fsrm a5
; CHECK-NEXT: bltu a0, a1, .LBB46_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -1223,14 +1223,14 @@ define <vscale x 16 x i64> @vp_ctlz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; CHECK-ZVBB-LABEL: vp_ctlz_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: sub a2, a0, a1
-; CHECK-ZVBB-NEXT: sltu a3, a0, a2
-; CHECK-ZVBB-NEXT: addi a3, a3, -1
-; CHECK-ZVBB-NEXT: and a2, a3, a2
-; CHECK-ZVBB-NEXT: srli a3, a1, 3
+; CHECK-ZVBB-NEXT: srli a2, a1, 3
+; CHECK-ZVBB-NEXT: sub a3, a0, a1
; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
-; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-ZVBB-NEXT: sltu a2, a0, a3
+; CHECK-ZVBB-NEXT: addi a2, a2, -1
+; CHECK-ZVBB-NEXT: and a2, a2, a3
; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v16, v16, v0.t
; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB46_2
@@ -2396,22 +2396,22 @@ define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: fsrmi a4, 1
-; CHECK-NEXT: li a2, 52
-; CHECK-NEXT: li a3, 1086
-; CHECK-NEXT: sub a5, a0, a1
-; CHECK-NEXT: sltu a6, a0, a5
-; CHECK-NEXT: addi a6, a6, -1
-; CHECK-NEXT: and a5, a6, a5
-; CHECK-NEXT: srli a6, a1, 3
-; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
+; CHECK-NEXT: fsrmi a3, 1
+; CHECK-NEXT: srli a2, a1, 3
+; CHECK-NEXT: sub a4, a0, a1
+; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a6
-; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: sltu a2, a0, a4
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a4, a2, a4
+; CHECK-NEXT: li a2, 52
+; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t
+; CHECK-NEXT: fsrm a3
; CHECK-NEXT: vsrl.vx v16, v16, a2, v0.t
+; CHECK-NEXT: li a3, 1086
; CHECK-NEXT: vrsub.vx v16, v16, a3, v0.t
-; CHECK-NEXT: fsrm a4
; CHECK-NEXT: bltu a0, a1, .LBB94_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -2428,14 +2428,14 @@ define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: sub a2, a0, a1
-; CHECK-ZVBB-NEXT: sltu a3, a0, a2
-; CHECK-ZVBB-NEXT: addi a3, a3, -1
-; CHECK-ZVBB-NEXT: and a2, a3, a2
-; CHECK-ZVBB-NEXT: srli a3, a1, 3
+; CHECK-ZVBB-NEXT: srli a2, a1, 3
+; CHECK-ZVBB-NEXT: sub a3, a0, a1
; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
-; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-ZVBB-NEXT: sltu a2, a0, a3
+; CHECK-ZVBB-NEXT: addi a2, a2, -1
+; CHECK-ZVBB-NEXT: and a2, a2, a3
; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v16, v16, v0.t
; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB94_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
index 37adb42ad3e9a..1b03694ee3b36 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
@@ -1985,63 +1985,63 @@ define <vscale x 16 x i64> @vp_ctpop_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV32-NEXT: srli a3, a1, 3
; RV32-NEXT: sub a4, a0, a1
; RV32-NEXT: addi a2, a2, 1365
+; RV32-NEXT: csrr a5, vlenb
+; RV32-NEXT: li a6, 48
+; RV32-NEXT: mul a5, a5, a6
+; RV32-NEXT: add a5, sp, a5
+; RV32-NEXT: addi a5, a5, 16
+; RV32-NEXT: vs1r.v v0, (a5) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vx v0, v0, a3
+; RV32-NEXT: sltu a3, a0, a4
; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a2
-; RV32-NEXT: sltu a2, a0, a4
-; RV32-NEXT: addi a2, a2, -1
-; RV32-NEXT: and a2, a2, a4
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: li a5, 48
-; RV32-NEXT: mul a4, a4, a5
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
-; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vx v0, v0, a3
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: addi a3, a3, -1
+; RV32-NEXT: and a3, a3, a4
+; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 5
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 5
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vsub.vv v8, v16, v8, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: addi a3, a3, 819
+; RV32-NEXT: lui a2, 209715
+; RV32-NEXT: addi a2, a2, 819
; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a3
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vmv.v.x v24, a2
+; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v8, v24, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: addi a3, sp, 16
-; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a3, 61681
+; RV32-NEXT: lui a2, 61681
; RV32-NEXT: lui a4, 4112
-; RV32-NEXT: addi a3, a3, -241
+; RV32-NEXT: addi a2, a2, -241
; RV32-NEXT: addi a4, a4, 257
; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
-; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: li a5, 24
-; RV32-NEXT: mul a3, a3, a5
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: mul a2, a2, a5
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a4
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV32-NEXT: vmul.vv v16, v16, v8, v0.t
; RV32-NEXT: li a2, 56
; RV32-NEXT: vsrl.vx v8, v16, a2, v0.t
@@ -2124,76 +2124,97 @@ define <vscale x 16 x i64> @vp_ctpop_nxv16i64(<vscale x 16 x i64> %va, <vscale x
;
; RV64-LABEL: vp_ctpop_nxv16i64:
; RV64: # %bb.0:
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: srli a3, a1, 3
-; RV64-NEXT: mv a2, a0
-; RV64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v7, v0, a3
-; RV64-NEXT: bltu a0, a1, .LBB46_2
+; RV64-NEXT: csrr a5, vlenb
+; RV64-NEXT: srli a1, a5, 3
+; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vx v7, v0, a1
+; RV64-NEXT: mv a1, a0
+; RV64-NEXT: bltu a0, a5, .LBB46_2
; RV64-NEXT: # %bb.1:
-; RV64-NEXT: mv a2, a1
+; RV64-NEXT: mv a1, a5
; RV64-NEXT: .LBB46_2:
-; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
-; RV64-NEXT: lui a5, 4112
+; RV64-NEXT: lui a6, 4112
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: addi a3, a3, 819
; RV64-NEXT: addi a4, a4, -241
-; RV64-NEXT: addi a5, a5, 257
-; RV64-NEXT: slli a6, a2, 32
-; RV64-NEXT: add a2, a2, a6
-; RV64-NEXT: slli a6, a3, 32
-; RV64-NEXT: add a3, a3, a6
-; RV64-NEXT: slli a6, a4, 32
-; RV64-NEXT: add a4, a4, a6
-; RV64-NEXT: slli a6, a5, 32
-; RV64-NEXT: add a5, a5, a6
-; RV64-NEXT: li a6, 56
-; RV64-NEXT: vand.vx v24, v24, a2, v0.t
-; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v8, v8, a4, v0.t
-; RV64-NEXT: vmul.vx v8, v8, a5, v0.t
-; RV64-NEXT: vsrl.vx v8, v8, a6, v0.t
-; RV64-NEXT: sub a1, a0, a1
-; RV64-NEXT: sltu a0, a0, a1
+; RV64-NEXT: addi a6, a6, 257
+; RV64-NEXT: slli a7, a2, 32
+; RV64-NEXT: add a7, a2, a7
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: add t0, a3, a2
+; RV64-NEXT: slli a2, a4, 32
+; RV64-NEXT: add a4, a4, a2
+; RV64-NEXT: slli a2, a6, 32
+; RV64-NEXT: add a2, a6, a2
+; RV64-NEXT: li a3, 56
+; RV64-NEXT: sub a5, a0, a5
+; RV64-NEXT: sltu a0, a0, a5
; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a0, a0, a1
+; RV64-NEXT: and a0, a0, a5
+; RV64-NEXT: vand.vx v24, v24, a7, v0.t
+; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v6, v0
; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a2, v0.t
+; RV64-NEXT: vand.vx v24, v24, a7, v0.t
; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vand.vx v24, v16, a3, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v8, t0, v0.t
+; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV64-NEXT: vand.vx v8, v8, t0, v0.t
+; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v16, t0, v0.t
; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a3, v0.t
+; RV64-NEXT: vand.vx v16, v16, t0, v0.t
; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v8, v8, a4, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vmul.vx v8, v8, a2, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v16, a4, v0.t
-; RV64-NEXT: vmul.vx v16, v16, a5, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a6, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v8, v8, a3, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vmul.vx v16, v16, a2, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a3, v0.t
; RV64-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_ctpop_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: sub a2, a0, a1
-; CHECK-ZVBB-NEXT: sltu a3, a0, a2
-; CHECK-ZVBB-NEXT: addi a3, a3, -1
-; CHECK-ZVBB-NEXT: and a2, a3, a2
-; CHECK-ZVBB-NEXT: srli a3, a1, 3
+; CHECK-ZVBB-NEXT: srli a2, a1, 3
+; CHECK-ZVBB-NEXT: sub a3, a0, a1
; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
-; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-ZVBB-NEXT: sltu a2, a0, a3
+; CHECK-ZVBB-NEXT: addi a2, a2, -1
+; CHECK-ZVBB-NEXT: and a2, a2, a3
; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vcpop.v v16, v16, v0.t
; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB46_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
index ed2dc76750466..bf003ef675a36 100644
--- a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
@@ -2150,11 +2150,8 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: lui a2, 349525
-; RV32-NEXT: sub a3, a0, a1
-; RV32-NEXT: sltu a4, a0, a3
-; RV32-NEXT: addi a4, a4, -1
-; RV32-NEXT: and a3, a4, a3
-; RV32-NEXT: srli a4, a1, 3
+; RV32-NEXT: srli a3, a1, 3
+; RV32-NEXT: sub a4, a0, a1
; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: li a6, 48
@@ -2163,7 +2160,10 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs1r.v v0, (a5) # vscale x 8-byte Folded Spill
; RV32-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vx v0, v0, a4
+; RV32-NEXT: vslidedown.vx v0, v0, a3
+; RV32-NEXT: sltu a3, a0, a4
+; RV32-NEXT: addi a3, a3, -1
+; RV32-NEXT: and a3, a3, a4
; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV32-NEXT: vadd.vi v8, v16, -1, v0.t
; RV32-NEXT: vnot.v v16, v16, v0.t
@@ -2304,26 +2304,26 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
; RV64-NEXT: lui a5, 4112
-; RV64-NEXT: sub a6, a0, a1
+; RV64-NEXT: srli a6, a1, 3
+; RV64-NEXT: sub a7, a0, a1
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: addi a3, a3, 819
-; RV64-NEXT: addi a7, a4, -241
-; RV64-NEXT: addi t0, a5, 257
+; RV64-NEXT: addi t0, a4, -241
+; RV64-NEXT: addi t1, a5, 257
+; RV64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; RV64-NEXT: vmv1r.v v7, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a6
; RV64-NEXT: slli a5, a2, 32
; RV64-NEXT: add a5, a2, a5
; RV64-NEXT: slli a4, a3, 32
; RV64-NEXT: add a4, a3, a4
-; RV64-NEXT: slli a2, a7, 32
-; RV64-NEXT: add a2, a7, a2
-; RV64-NEXT: slli a3, t0, 32
-; RV64-NEXT: add a3, t0, a3
-; RV64-NEXT: sltu a7, a0, a6
-; RV64-NEXT: addi a7, a7, -1
-; RV64-NEXT: and a6, a7, a6
-; RV64-NEXT: srli a7, a1, 3
-; RV64-NEXT: vsetvli t0, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v7, v0
-; RV64-NEXT: vslidedown.vx v0, v0, a7
+; RV64-NEXT: slli a2, t0, 32
+; RV64-NEXT: add a2, t0, a2
+; RV64-NEXT: slli a3, t1, 32
+; RV64-NEXT: add a3, t1, a3
+; RV64-NEXT: sltu a6, a0, a7
+; RV64-NEXT: addi a6, a6, -1
+; RV64-NEXT: and a6, a6, a7
; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; RV64-NEXT: vadd.vi v24, v16, -1, v0.t
; RV64-NEXT: vnot.v v16, v16, v0.t
@@ -2367,14 +2367,14 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; CHECK-ZVBB-LABEL: vp_cttz_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: sub a2, a0, a1
-; CHECK-ZVBB-NEXT: sltu a3, a0, a2
-; CHECK-ZVBB-NEXT: addi a3, a3, -1
-; CHECK-ZVBB-NEXT: and a2, a3, a2
-; CHECK-ZVBB-NEXT: srli a3, a1, 3
+; CHECK-ZVBB-NEXT: srli a2, a1, 3
+; CHECK-ZVBB-NEXT: sub a3, a0, a1
; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
-; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-ZVBB-NEXT: sltu a2, a0, a3
+; CHECK-ZVBB-NEXT: addi a2, a2, -1
+; CHECK-ZVBB-NEXT: and a2, a2, a3
; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v16, v16, v0.t
; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB46_2
@@ -3747,24 +3747,24 @@ define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
; CHECK-LABEL: vp_cttz_zero_undef_nxv16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: fsrmi a4, 1
-; CHECK-NEXT: li a2, 52
-; CHECK-NEXT: li a3, 1023
-; CHECK-NEXT: sub a5, a0, a1
-; CHECK-NEXT: sltu a6, a0, a5
-; CHECK-NEXT: addi a6, a6, -1
-; CHECK-NEXT: and a5, a6, a5
-; CHECK-NEXT: srli a6, a1, 3
-; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
+; CHECK-NEXT: fsrmi a3, 1
+; CHECK-NEXT: srli a2, a1, 3
+; CHECK-NEXT: sub a4, a0, a1
+; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a6
-; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: sltu a2, a0, a4
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a4, a2, a4
+; CHECK-NEXT: li a2, 52
+; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v16, 0, v0.t
; CHECK-NEXT: vand.vv v16, v16, v24, v0.t
; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t
+; CHECK-NEXT: fsrm a3
; CHECK-NEXT: vsrl.vx v16, v16, a2, v0.t
+; CHECK-NEXT: li a3, 1023
; CHECK-NEXT: vsub.vx v16, v16, a3, v0.t
-; CHECK-NEXT: fsrm a4
; CHECK-NEXT: bltu a0, a1, .LBB94_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -3783,14 +3783,14 @@ define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: sub a2, a0, a1
-; CHECK-ZVBB-NEXT: sltu a3, a0, a2
-; CHECK-ZVBB-NEXT: addi a3, a3, -1
-; CHECK-ZVBB-NEXT: and a2, a3, a2
-; CHECK-ZVBB-NEXT: srli a3, a1, 3
+; CHECK-ZVBB-NEXT: srli a2, a1, 3
+; CHECK-ZVBB-NEXT: sub a3, a0, a1
; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
-; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-ZVBB-NEXT: sltu a2, a0, a3
+; CHECK-ZVBB-NEXT: addi a2, a2, -1
+; CHECK-ZVBB-NEXT: and a2, a2, a3
; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v16, v16, v0.t
; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB94_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/expandload.ll b/llvm/test/CodeGen/RISCV/rvv/expandload.ll
index 0a2c8c9693b47..f13a9d0764c8b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/expandload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/expandload.ll
@@ -218,31 +218,24 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: csrr a2, vlenb
-; CHECK-RV32-NEXT: li a3, 34
-; CHECK-RV32-NEXT: mul a2, a2, a3
+; CHECK-RV32-NEXT: slli a3, a2, 5
+; CHECK-RV32-NEXT: add a2, a3, a2
; CHECK-RV32-NEXT: sub sp, sp, a2
-; CHECK-RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x22, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 34 * vlenb
+; CHECK-RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; CHECK-RV32-NEXT: csrr a2, vlenb
-; CHECK-RV32-NEXT: li a3, 26
+; CHECK-RV32-NEXT: li a3, 24
; CHECK-RV32-NEXT: mul a2, a2, a3
; CHECK-RV32-NEXT: add a2, sp, a2
; CHECK-RV32-NEXT: addi a2, a2, 16
; CHECK-RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: csrr a2, vlenb
-; CHECK-RV32-NEXT: li a3, 25
-; CHECK-RV32-NEXT: mul a2, a2, a3
-; CHECK-RV32-NEXT: add a2, sp, a2
-; CHECK-RV32-NEXT: addi a2, a2, 16
-; CHECK-RV32-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
-; CHECK-RV32-NEXT: csrr a2, vlenb
-; CHECK-RV32-NEXT: li a3, 24
-; CHECK-RV32-NEXT: mul a2, a2, a3
+; CHECK-RV32-NEXT: slli a2, a2, 5
; CHECK-RV32-NEXT: add a2, sp, a2
; CHECK-RV32-NEXT: addi a2, a2, 16
; CHECK-RV32-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: li a2, 128
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v11, v0, 1
+; CHECK-RV32-NEXT: vslidedown.vi v8, v0, 1
; CHECK-RV32-NEXT: li a3, 32
; CHECK-RV32-NEXT: vmv.x.s a4, v0
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -253,9 +246,9 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV32-NEXT: addi a1, a1, 16
; CHECK-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vsrl.vx v9, v11, a3
+; CHECK-RV32-NEXT: vsrl.vx v9, v8, a3
; CHECK-RV32-NEXT: vsrl.vx v10, v0, a3
-; CHECK-RV32-NEXT: vmv.x.s a1, v11
+; CHECK-RV32-NEXT: vmv.x.s a1, v8
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV32-NEXT: vcpop.m a3, v0
; CHECK-RV32-NEXT: cpop a4, a4
@@ -263,12 +256,12 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV32-NEXT: vmv.x.s a5, v9
; CHECK-RV32-NEXT: vmv.x.s a6, v10
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-RV32-NEXT: vle8.v v24, (a0)
+; CHECK-RV32-NEXT: vle8.v v8, (a0)
; CHECK-RV32-NEXT: csrr a3, vlenb
; CHECK-RV32-NEXT: slli a3, a3, 4
; CHECK-RV32-NEXT: add a3, sp, a3
; CHECK-RV32-NEXT: addi a3, a3, 16
-; CHECK-RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: cpop a1, a1
; CHECK-RV32-NEXT: cpop a3, a6
; CHECK-RV32-NEXT: cpop a5, a5
@@ -276,75 +269,65 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV32-NEXT: add a1, a1, a5
; CHECK-RV32-NEXT: add a1, a3, a1
; CHECK-RV32-NEXT: add a0, a0, a1
+; CHECK-RV32-NEXT: csrr a1, vlenb
+; CHECK-RV32-NEXT: slli a1, a1, 5
+; CHECK-RV32-NEXT: add a1, sp, a1
+; CHECK-RV32-NEXT: addi a1, a1, 16
+; CHECK-RV32-NEXT: vl1r.v v8, (a1) # vscale x 8-byte Folded Reload
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV32-NEXT: vcpop.m a1, v8
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-RV32-NEXT: vle8.v v8, (a0)
; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: li a1, 25
-; CHECK-RV32-NEXT: mul a0, a0, a1
-; CHECK-RV32-NEXT: add a0, sp, a0
-; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, mu
-; CHECK-RV32-NEXT: viota.m v8, v24
-; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: li a1, 25
-; CHECK-RV32-NEXT: mul a0, a0, a1
-; CHECK-RV32-NEXT: add a0, sp, a0
-; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: li a1, 26
-; CHECK-RV32-NEXT: mul a0, a0, a1
-; CHECK-RV32-NEXT: add a0, sp, a0
-; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: viota.m v16, v0
; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: slli a0, a0, 4
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: vrgather.vv v16, v24, v8, v0.t
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: li a1, 26
+; CHECK-RV32-NEXT: li a1, 24
; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vrgather.vv v8, v24, v16, v0.t
; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: li a1, 24
; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
-; CHECK-RV32-NEXT: viota.m v16, v8
+; CHECK-RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 3
+; CHECK-RV32-NEXT: slli a0, a0, 5
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV32-NEXT: viota.m v8, v24
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: li a1, 24
-; CHECK-RV32-NEXT: mul a0, a0, a1
+; CHECK-RV32-NEXT: slli a0, a0, 5
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
; CHECK-RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV32-NEXT: csrr a0, vlenb
+; CHECK-RV32-NEXT: slli a0, a0, 3
+; CHECK-RV32-NEXT: add a0, sp, a0
+; CHECK-RV32-NEXT: addi a0, a0, 16
+; CHECK-RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: addi a0, sp, 16
-; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: vrgather.vv v24, v8, v16, v0.t
+; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vrgather.vv v16, v24, v8, v0.t
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: li a1, 26
+; CHECK-RV32-NEXT: li a1, 24
; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: vmv.v.v v16, v24
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: li a1, 34
-; CHECK-RV32-NEXT: mul a0, a0, a1
+; CHECK-RV32-NEXT: slli a1, a0, 5
+; CHECK-RV32-NEXT: add a0, a1, a0
; CHECK-RV32-NEXT: add sp, sp, a0
; CHECK-RV32-NEXT: .cfi_def_cfa sp, 16
; CHECK-RV32-NEXT: addi sp, sp, 16
@@ -356,31 +339,24 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV64-NEXT: addi sp, sp, -16
; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV64-NEXT: csrr a2, vlenb
-; CHECK-RV64-NEXT: li a3, 34
-; CHECK-RV64-NEXT: mul a2, a2, a3
+; CHECK-RV64-NEXT: slli a3, a2, 5
+; CHECK-RV64-NEXT: add a2, a3, a2
; CHECK-RV64-NEXT: sub sp, sp, a2
-; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x22, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 34 * vlenb
+; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; CHECK-RV64-NEXT: csrr a2, vlenb
-; CHECK-RV64-NEXT: li a3, 26
+; CHECK-RV64-NEXT: li a3, 24
; CHECK-RV64-NEXT: mul a2, a2, a3
; CHECK-RV64-NEXT: add a2, sp, a2
; CHECK-RV64-NEXT: addi a2, a2, 16
; CHECK-RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: csrr a2, vlenb
-; CHECK-RV64-NEXT: li a3, 25
-; CHECK-RV64-NEXT: mul a2, a2, a3
-; CHECK-RV64-NEXT: add a2, sp, a2
-; CHECK-RV64-NEXT: addi a2, a2, 16
-; CHECK-RV64-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
-; CHECK-RV64-NEXT: csrr a2, vlenb
-; CHECK-RV64-NEXT: li a3, 24
-; CHECK-RV64-NEXT: mul a2, a2, a3
+; CHECK-RV64-NEXT: slli a2, a2, 5
; CHECK-RV64-NEXT: add a2, sp, a2
; CHECK-RV64-NEXT: addi a2, a2, 16
; CHECK-RV64-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: li a2, 128
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v9, v0, 1
+; CHECK-RV64-NEXT: vslidedown.vi v8, v0, 1
; CHECK-RV64-NEXT: vmv.x.s a3, v0
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV64-NEXT: vle8.v v16, (a1)
@@ -390,16 +366,21 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV64-NEXT: addi a1, a1, 16
; CHECK-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a2, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vmv.x.s a1, v9
+; CHECK-RV64-NEXT: vmv.x.s a1, v8
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV64-NEXT: vcpop.m a4, v0
; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; CHECK-RV64-NEXT: vle8.v v24, (a0)
+; CHECK-RV64-NEXT: vle8.v v8, (a0)
; CHECK-RV64-NEXT: csrr a4, vlenb
; CHECK-RV64-NEXT: slli a4, a4, 4
; CHECK-RV64-NEXT: add a4, sp, a4
; CHECK-RV64-NEXT: addi a4, a4, 16
-; CHECK-RV64-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: csrr a4, vlenb
+; CHECK-RV64-NEXT: slli a4, a4, 5
+; CHECK-RV64-NEXT: add a4, sp, a4
+; CHECK-RV64-NEXT: addi a4, a4, 16
+; CHECK-RV64-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV64-NEXT: vcpop.m a4, v8
; CHECK-RV64-NEXT: cpop a3, a3
@@ -410,68 +391,54 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV64-NEXT: vle8.v v8, (a0)
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 25
-; CHECK-RV64-NEXT: mul a0, a0, a1
-; CHECK-RV64-NEXT: add a0, sp, a0
-; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, mu
-; CHECK-RV64-NEXT: viota.m v24, v8
+; CHECK-RV64-NEXT: viota.m v16, v0
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 25
-; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: slli a0, a0, 4
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 26
+; CHECK-RV64-NEXT: li a1, 24
; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vrgather.vv v8, v24, v16, v0.t
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 4
-; CHECK-RV64-NEXT: add a0, sp, a0
-; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV64-NEXT: vrgather.vv v8, v16, v24, v0.t
-; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 26
+; CHECK-RV64-NEXT: li a1, 24
; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 24
-; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: slli a0, a0, 5
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl1r.v v16, (a0) # vscale x 8-byte Folded Reload
-; CHECK-RV64-NEXT: viota.m v24, v16
+; CHECK-RV64-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV64-NEXT: viota.m v24, v8
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 3
+; CHECK-RV64-NEXT: slli a0, a0, 5
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 24
-; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: slli a0, a0, 3
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vrgather.vv v16, v8, v24, v0.t
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 26
+; CHECK-RV64-NEXT: li a1, 24
; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 34
-; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: slli a1, a0, 5
+; CHECK-RV64-NEXT: add a0, a1, a0
; CHECK-RV64-NEXT: add sp, sp, a0
; CHECK-RV64-NEXT: .cfi_def_cfa sp, 16
; CHECK-RV64-NEXT: addi sp, sp, 16
@@ -727,22 +694,22 @@ define <128 x i16> @test_expandload_v128i16(ptr %base, <128 x i1> %mask, <128 x
; CHECK-RV32-NEXT: add a1, sp, a1
; CHECK-RV32-NEXT: addi a1, a1, 16
; CHECK-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m8, ta, ma
+; CHECK-RV32-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-RV32-NEXT: vmv8r.v v16, v8
; CHECK-RV32-NEXT: li a1, 64
+; CHECK-RV32-NEXT: vslidedown.vi v8, v0, 8
+; CHECK-RV32-NEXT: csrr a2, vlenb
+; CHECK-RV32-NEXT: slli a2, a2, 5
+; CHECK-RV32-NEXT: add a2, sp, a2
+; CHECK-RV32-NEXT: addi a2, a2, 16
+; CHECK-RV32-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: li a2, 32
+; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-RV32-NEXT: vmv.x.s a3, v0
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-RV32-NEXT: vcpop.m a4, v0
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV32-NEXT: vsrl.vx v8, v0, a2
-; CHECK-RV32-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v9, v0, 8
-; CHECK-RV32-NEXT: csrr a2, vlenb
-; CHECK-RV32-NEXT: slli a2, a2, 5
-; CHECK-RV32-NEXT: add a2, sp, a2
-; CHECK-RV32-NEXT: addi a2, a2, 16
-; CHECK-RV32-NEXT: vs1r.v v9, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: csrr a2, vlenb
; CHECK-RV32-NEXT: slli a2, a2, 5
; CHECK-RV32-NEXT: add a2, sp, a2
@@ -831,21 +798,20 @@ define <128 x i16> @test_expandload_v128i16(ptr %base, <128 x i1> %mask, <128 x
; CHECK-RV64-NEXT: addi a1, a1, 16
; CHECK-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: li a1, 64
-; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
-; CHECK-RV64-NEXT: vcpop.m a2, v0
; CHECK-RV64-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 8
-; CHECK-RV64-NEXT: csrr a3, vlenb
-; CHECK-RV64-NEXT: slli a3, a3, 5
-; CHECK-RV64-NEXT: add a3, sp, a3
-; CHECK-RV64-NEXT: addi a3, a3, 16
-; CHECK-RV64-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
+; CHECK-RV64-NEXT: csrr a2, vlenb
+; CHECK-RV64-NEXT: slli a2, a2, 5
+; CHECK-RV64-NEXT: add a2, sp, a2
+; CHECK-RV64-NEXT: addi a2, a2, 16
+; CHECK-RV64-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
+; CHECK-RV64-NEXT: vcpop.m a2, v0
; CHECK-RV64-NEXT: csrr a3, vlenb
; CHECK-RV64-NEXT: slli a3, a3, 5
; CHECK-RV64-NEXT: add a3, sp, a3
; CHECK-RV64-NEXT: addi a3, a3, 16
; CHECK-RV64-NEXT: vl1r.v v24, (a3) # vscale x 8-byte Folded Reload
-; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-RV64-NEXT: vcpop.m a3, v24
; CHECK-RV64-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-RV64-NEXT: vle16.v v24, (a0)
@@ -1118,21 +1084,20 @@ define <64 x i32> @test_expandload_v64i32(ptr %base, <64 x i1> %mask, <64 x i32>
; CHECK-RV32-NEXT: addi a1, a1, 16
; CHECK-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: li a1, 32
-; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
-; CHECK-RV32-NEXT: vcpop.m a2, v0
; CHECK-RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-RV32-NEXT: vslidedown.vi v24, v0, 4
-; CHECK-RV32-NEXT: csrr a3, vlenb
-; CHECK-RV32-NEXT: slli a3, a3, 5
-; CHECK-RV32-NEXT: add a3, sp, a3
-; CHECK-RV32-NEXT: addi a3, a3, 16
-; CHECK-RV32-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
+; CHECK-RV32-NEXT: csrr a2, vlenb
+; CHECK-RV32-NEXT: slli a2, a2, 5
+; CHECK-RV32-NEXT: add a2, sp, a2
+; CHECK-RV32-NEXT: addi a2, a2, 16
+; CHECK-RV32-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
+; CHECK-RV32-NEXT: vcpop.m a2, v0
; CHECK-RV32-NEXT: csrr a3, vlenb
; CHECK-RV32-NEXT: slli a3, a3, 5
; CHECK-RV32-NEXT: add a3, sp, a3
; CHECK-RV32-NEXT: addi a3, a3, 16
; CHECK-RV32-NEXT: vl1r.v v24, (a3) # vscale x 8-byte Folded Reload
-; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vcpop.m a3, v24
; CHECK-RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-RV32-NEXT: vle32.v v24, (a0)
@@ -1201,33 +1166,37 @@ define <64 x i32> @test_expandload_v64i32(ptr %base, <64 x i1> %mask, <64 x i32>
; CHECK-RV64-NEXT: addi sp, sp, -16
; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV64-NEXT: csrr a1, vlenb
-; CHECK-RV64-NEXT: li a2, 25
-; CHECK-RV64-NEXT: mul a1, a1, a2
+; CHECK-RV64-NEXT: slli a2, a1, 5
+; CHECK-RV64-NEXT: add a1, a2, a1
; CHECK-RV64-NEXT: sub sp, sp, a1
-; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
+; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; CHECK-RV64-NEXT: csrr a1, vlenb
-; CHECK-RV64-NEXT: slli a1, a1, 4
+; CHECK-RV64-NEXT: li a2, 24
+; CHECK-RV64-NEXT: mul a1, a1, a2
; CHECK-RV64-NEXT: add a1, sp, a1
; CHECK-RV64-NEXT: addi a1, a1, 16
; CHECK-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: li a1, 32
-; CHECK-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 4
+; CHECK-RV64-NEXT: csrr a2, vlenb
+; CHECK-RV64-NEXT: slli a2, a2, 5
+; CHECK-RV64-NEXT: add a2, sp, a2
+; CHECK-RV64-NEXT: addi a2, a2, 16
+; CHECK-RV64-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
+; CHECK-RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-RV64-NEXT: vmv.x.s a2, v0
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vcpop.m a3, v0
; CHECK-RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; CHECK-RV64-NEXT: vle32.v v16, (a0)
-; CHECK-RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 4
+; CHECK-RV64-NEXT: vle32.v v24, (a0)
; CHECK-RV64-NEXT: csrr a3, vlenb
-; CHECK-RV64-NEXT: li a4, 24
-; CHECK-RV64-NEXT: mul a3, a3, a4
+; CHECK-RV64-NEXT: slli a3, a3, 4
; CHECK-RV64-NEXT: add a3, sp, a3
; CHECK-RV64-NEXT: addi a3, a3, 16
-; CHECK-RV64-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
+; CHECK-RV64-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: csrr a3, vlenb
-; CHECK-RV64-NEXT: li a4, 24
-; CHECK-RV64-NEXT: mul a3, a3, a4
+; CHECK-RV64-NEXT: slli a3, a3, 5
; CHECK-RV64-NEXT: add a3, sp, a3
; CHECK-RV64-NEXT: addi a3, a3, 16
; CHECK-RV64-NEXT: vl1r.v v24, (a3) # vscale x 8-byte Folded Reload
@@ -1245,24 +1214,28 @@ define <64 x i32> @test_expandload_v64i32(ptr %base, <64 x i1> %mask, <64 x i32>
; CHECK-RV64-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-RV64-NEXT: viota.m v24, v0
+; CHECK-RV64-NEXT: csrr a0, vlenb
+; CHECK-RV64-NEXT: slli a0, a0, 4
+; CHECK-RV64-NEXT: add a0, sp, a0
+; CHECK-RV64-NEXT: addi a0, a0, 16
+; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 24
-; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: slli a0, a0, 5
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: viota.m v16, v24
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 24
-; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: slli a0, a0, 5
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 4
+; CHECK-RV64-NEXT: li a1, 24
+; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -1276,8 +1249,8 @@ define <64 x i32> @test_expandload_v64i32(ptr %base, <64 x i1> %mask, <64 x i32>
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 25
-; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: slli a1, a0, 5
+; CHECK-RV64-NEXT: add a0, a1, a0
; CHECK-RV64-NEXT: add sp, sp, a0
; CHECK-RV64-NEXT: .cfi_def_cfa sp, 16
; CHECK-RV64-NEXT: addi sp, sp, 16
@@ -1465,17 +1438,17 @@ define <32 x i64> @test_expandload_v32i64(ptr %base, <32 x i1> %mask, <32 x i64>
; CHECK-RV32-NEXT: addi a1, a1, 16
; CHECK-RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: vmv.x.s a1, v0
+; CHECK-RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-RV32-NEXT: csrr a2, vlenb
+; CHECK-RV32-NEXT: slli a2, a2, 5
+; CHECK-RV32-NEXT: add a2, sp, a2
+; CHECK-RV32-NEXT: addi a2, a2, 16
+; CHECK-RV32-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: zext.h a1, a1
; CHECK-RV32-NEXT: cpop a1, a1
; CHECK-RV32-NEXT: slli a1, a1, 3
; CHECK-RV32-NEXT: add a0, a0, a1
-; CHECK-RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-RV32-NEXT: csrr a1, vlenb
-; CHECK-RV32-NEXT: slli a1, a1, 5
-; CHECK-RV32-NEXT: add a1, sp, a1
-; CHECK-RV32-NEXT: addi a1, a1, 16
-; CHECK-RV32-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: csrr a1, vlenb
; CHECK-RV32-NEXT: slli a1, a1, 5
; CHECK-RV32-NEXT: add a1, sp, a1
@@ -1506,23 +1479,24 @@ define <32 x i64> @test_expandload_v32i64(ptr %base, <32 x i1> %mask, <32 x i64>
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
; CHECK-RV32-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
-; CHECK-RV32-NEXT: viota.m v8, v24
+; CHECK-RV32-NEXT: viota.m v16, v24
; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: slli a0, a0, 5
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
; CHECK-RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 3
+; CHECK-RV32-NEXT: slli a0, a0, 4
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 4
+; CHECK-RV32-NEXT: slli a0, a0, 3
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: vrgather.vv v16, v24, v8, v0.t
+; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vrgather.vv v8, v24, v16, v0.t
+; CHECK-RV32-NEXT: vmv.v.v v16, v8
; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
@@ -1559,17 +1533,17 @@ define <32 x i64> @test_expandload_v32i64(ptr %base, <32 x i1> %mask, <32 x i64>
; CHECK-RV64-NEXT: addi a1, a1, 16
; CHECK-RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: vmv.x.s a1, v0
+; CHECK-RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-RV64-NEXT: csrr a2, vlenb
+; CHECK-RV64-NEXT: slli a2, a2, 5
+; CHECK-RV64-NEXT: add a2, sp, a2
+; CHECK-RV64-NEXT: addi a2, a2, 16
+; CHECK-RV64-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: zext.h a1, a1
; CHECK-RV64-NEXT: cpopw a1, a1
; CHECK-RV64-NEXT: slli a1, a1, 3
; CHECK-RV64-NEXT: add a0, a0, a1
-; CHECK-RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-RV64-NEXT: csrr a1, vlenb
-; CHECK-RV64-NEXT: slli a1, a1, 5
-; CHECK-RV64-NEXT: add a1, sp, a1
-; CHECK-RV64-NEXT: addi a1, a1, 16
-; CHECK-RV64-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: csrr a1, vlenb
; CHECK-RV64-NEXT: slli a1, a1, 5
; CHECK-RV64-NEXT: add a1, sp, a1
@@ -1600,23 +1574,24 @@ define <32 x i64> @test_expandload_v32i64(ptr %base, <32 x i1> %mask, <32 x i64>
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
-; CHECK-RV64-NEXT: viota.m v8, v24
+; CHECK-RV64-NEXT: viota.m v16, v24
; CHECK-RV64-NEXT: csrr a0, vlenb
; CHECK-RV64-NEXT: slli a0, a0, 5
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 3
+; CHECK-RV64-NEXT: slli a0, a0, 4
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 4
+; CHECK-RV64-NEXT: slli a0, a0, 3
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV64-NEXT: vrgather.vv v16, v24, v8, v0.t
+; CHECK-RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vrgather.vv v8, v24, v16, v0.t
+; CHECK-RV64-NEXT: vmv.v.v v16, v8
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
index e0edf68e949b6..62dadfe936e44 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
@@ -139,21 +139,22 @@ define i1 @extractelt_nxv128i1(ptr %x, i64 %idx) nounwind {
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: sub sp, sp, a3
; RV32-NEXT: andi sp, sp, -64
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: addi a3, sp, 64
; RV32-NEXT: vl8r.v v8, (a0)
+; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a0, a0, a2
; RV32-NEXT: vl8r.v v16, (a0)
; RV32-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: vmseq.vi v0, v8, 0
-; RV32-NEXT: vmerge.vim v8, v24, 1, v0
-; RV32-NEXT: vmseq.vi v0, v16, 0
-; RV32-NEXT: vmerge.vim v16, v24, 1, v0
-; RV32-NEXT: addi a0, sp, 64
-; RV32-NEXT: add a1, a0, a1
-; RV32-NEXT: vs8r.v v8, (a0)
-; RV32-NEXT: add a0, a0, a2
-; RV32-NEXT: vs8r.v v16, (a0)
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: add a1, a3, a1
+; RV32-NEXT: vmseq.vi v25, v16, 0
+; RV32-NEXT: vmerge.vim v16, v8, 1, v0
+; RV32-NEXT: vs8r.v v16, (a3)
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: vmv1r.v v0, v25
+; RV32-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-NEXT: vs8r.v v8, (a2)
; RV32-NEXT: lbu a0, 0(a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -178,21 +179,22 @@ define i1 @extractelt_nxv128i1(ptr %x, i64 %idx) nounwind {
; RV64-NEXT: slli a3, a3, 4
; RV64-NEXT: sub sp, sp, a3
; RV64-NEXT: andi sp, sp, -64
-; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: addi a3, sp, 64
; RV64-NEXT: vl8r.v v8, (a0)
+; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: add a0, a0, a2
; RV64-NEXT: vl8r.v v16, (a0)
; RV64-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; RV64-NEXT: vmv.v.i v24, 0
; RV64-NEXT: vmseq.vi v0, v8, 0
-; RV64-NEXT: vmerge.vim v8, v24, 1, v0
-; RV64-NEXT: vmseq.vi v0, v16, 0
-; RV64-NEXT: vmerge.vim v16, v24, 1, v0
-; RV64-NEXT: addi a0, sp, 64
-; RV64-NEXT: add a1, a0, a1
-; RV64-NEXT: vs8r.v v8, (a0)
-; RV64-NEXT: add a0, a0, a2
-; RV64-NEXT: vs8r.v v16, (a0)
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: add a1, a3, a1
+; RV64-NEXT: vmseq.vi v25, v16, 0
+; RV64-NEXT: vmerge.vim v16, v8, 1, v0
+; RV64-NEXT: vs8r.v v16, (a3)
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: vmv1r.v v0, v25
+; RV64-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-NEXT: vs8r.v v8, (a2)
; RV64-NEXT: lbu a0, 0(a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
index 836883c002b8b..fa81e1f6f3514 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
@@ -382,9 +382,9 @@ define <32 x i64> @vp_abs_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl)
; CHECK-LABEL: vp_abs_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v7, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB34_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
index ddc0cba841fec..faf9e630b0e10 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
@@ -2696,9 +2696,9 @@ define <128 x i16> @vp_bitreverse_v128i16(<128 x i16> %va, <128 x i1> %m, i32 ze
; CHECK-LABEL: vp_bitreverse_v128i16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 64
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v7, v0, 8
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB34_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 64
@@ -2706,50 +2706,59 @@ define <128 x i16> @vp_bitreverse_v128i16(<128 x i16> %va, <128 x i1> %m, i32 ze
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v8, 8, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: lui a1, 1
-; CHECK-NEXT: lui a2, 3
-; CHECK-NEXT: lui a3, 5
+; CHECK-NEXT: lui a2, 1
+; CHECK-NEXT: lui a4, 3
+; CHECK-NEXT: addi a3, a0, -64
+; CHECK-NEXT: sltu a0, a0, a3
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a3, a0, a3
+; CHECK-NEXT: lui a0, 5
; CHECK-NEXT: vor.vv v8, v8, v24, v0.t
-; CHECK-NEXT: addi a1, a1, -241
-; CHECK-NEXT: addi a2, a2, 819
-; CHECK-NEXT: addi a3, a3, 1365
+; CHECK-NEXT: addi a5, a2, -241
+; CHECK-NEXT: addi a2, a4, 819
+; CHECK-NEXT: addi a0, a0, 1365
; CHECK-NEXT: vsrl.vi v24, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a5, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a5, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
+; CHECK-NEXT: vmv1r.v v6, v0
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma
+; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
+; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
+; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
+; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a2, v0.t
; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
-; CHECK-NEXT: vsrl.vi v24, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a3, v0.t
-; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
-; CHECK-NEXT: addi a4, a0, -64
-; CHECK-NEXT: sltu a0, a0, a4
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a4
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
-; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
+; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v16, 4, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a5, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a5, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
+; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; CHECK-NEXT: vsrl.vi v24, v8, 1, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a0, v0.t
+; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
+; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v16, 2, v0.t
; CHECK-NEXT: vand.vx v16, v16, a2, v0.t
; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: vsrl.vi v24, v16, 1, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a3, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a3, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a0, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 1, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
index 83f08ec191d91..d8b109fcbf77f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
@@ -1556,9 +1556,9 @@ define <128 x i16> @vp_bswap_v128i16(<128 x i16> %va, <128 x i1> %m, i32 zeroext
; CHECK-LABEL: vp_bswap_v128i16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 64
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v7, v0, 8
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB26_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 64
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
index f4d1c2e291ee6..5d1a22368ddef 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
@@ -31,12 +31,12 @@ define <2 x half> @vp_ceil_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl)
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -115,12 +115,12 @@ define <4 x half> @vp_ceil_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl)
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
index a70aefd2bacf0..0a1dcd4c6abb7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
@@ -1887,183 +1887,301 @@ define <16 x i64> @vp_ctlz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v32i64:
; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 49
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 5
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: li a1, 16
-; RV32-NEXT: mv a2, a0
+; RV32-NEXT: li a2, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v16, v0, 2
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 5
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
-; RV32-NEXT: bltu a0, a1, .LBB34_2
+; RV32-NEXT: vmv1r.v v24, v0
+; RV32-NEXT: vslidedown.vi v7, v0, 2
+; RV32-NEXT: mv a1, a0
+; RV32-NEXT: bltu a0, a2, .LBB34_2
; RV32-NEXT: # %bb.1:
-; RV32-NEXT: li a2, 16
+; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB34_2:
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV32-NEXT: li a1, 32
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 26
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: sub sp, sp, a2
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
+; RV32-NEXT: vmv1r.v v0, v24
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: li a2, 32
+; RV32-NEXT: addi a3, a0, -16
+; RV32-NEXT: sltu a0, a0, a3
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: and a0, a0, a3
; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: addi a3, a3, 1365
-; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v6, v0
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v16, 2, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v16, 8, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v16, 16, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: slli a5, a4, 3
+; RV32-NEXT: add a4, a5, a4
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: li a5, 25
+; RV32-NEXT: mul a4, a4, a5
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs1r.v v6, (a4) # vscale x 8-byte Folded Spill
; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a3
+; RV32-NEXT: vmv.v.x v16, a3
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a4, a3, 4
+; RV32-NEXT: add a3, a4, a3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 24
+; RV32-NEXT: li a4, 25
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: addi a3, a3, 819
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 41
+; RV32-NEXT: li a4, 25
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 41
+; RV32-NEXT: li a4, 25
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a4, a3, 4
+; RV32-NEXT: add a3, a4, a3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 41
+; RV32-NEXT: li a4, 25
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a4, 61681
-; RV32-NEXT: lui a5, 4112
-; RV32-NEXT: li a3, 56
-; RV32-NEXT: addi a4, a4, -241
-; RV32-NEXT: addi a5, a5, 257
-; RV32-NEXT: vsetvli a6, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a4
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a4, a4, 3
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a4, a3, 3
+; RV32-NEXT: add a3, a4, a3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v24, v16, a2, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: lui a2, 209715
+; RV32-NEXT: addi a2, a2, 819
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v8, v16, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a5
-; RV32-NEXT: addi a4, sp, 16
-; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a3, v0.t
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 3
+; RV32-NEXT: add a2, a3, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: addi a2, a0, -16
-; RV32-NEXT: sltu a0, a0, a2
-; RV32-NEXT: addi a0, a0, -1
-; RV32-NEXT: and a0, a0, a2
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs1r.v v7, (a2) # vscale x 8-byte Folded Spill
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 4
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 5
+; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a4, a2, 5
-; RV32-NEXT: add a2, a4, a2
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
+; RV32-NEXT: vmv1r.v v7, v0
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 3
+; RV32-NEXT: add a2, a3, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v24, 4, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 3
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vadd.vv v24, v8, v24, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 4
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v8, v24, 1, v0.t
-; RV32-NEXT: vor.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 41
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a2, 61681
+; RV32-NEXT: lui a3, 4112
+; RV32-NEXT: addi a2, a2, -241
+; RV32-NEXT: addi a3, a3, 257
; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a4, 25
+; RV32-NEXT: mul a2, a2, a4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a4, a2, 4
+; RV32-NEXT: add a2, a4, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a3, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a3
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
+; RV32-NEXT: li a2, 56
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 25
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 49
+; RV32-NEXT: li a1, 26
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -2074,88 +2192,133 @@ define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV64-LABEL: vp_ctlz_v32i64:
; RV64: # %bb.0:
; RV64-NEXT: li a2, 16
-; RV64-NEXT: mv a1, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v7, v0, 2
+; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB34_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB34_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: li a1, 32
+; RV64-NEXT: li a6, 32
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
; RV64-NEXT: lui a5, 4112
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: addi a3, a3, 819
-; RV64-NEXT: addi a4, a4, -241
-; RV64-NEXT: addi a5, a5, 257
-; RV64-NEXT: slli a6, a2, 32
-; RV64-NEXT: add a6, a2, a6
+; RV64-NEXT: addi a7, a2, 1365
+; RV64-NEXT: addi a2, a3, 819
+; RV64-NEXT: addi a3, a4, -241
+; RV64-NEXT: addi a4, a5, 257
+; RV64-NEXT: slli a5, a7, 32
+; RV64-NEXT: add a7, a7, a5
+; RV64-NEXT: slli a5, a2, 32
+; RV64-NEXT: add a5, a2, a5
; RV64-NEXT: slli a2, a3, 32
-; RV64-NEXT: add a3, a3, a2
-; RV64-NEXT: slli a2, a4, 32
-; RV64-NEXT: add a2, a4, a2
-; RV64-NEXT: slli a4, a5, 32
-; RV64-NEXT: add a4, a5, a4
-; RV64-NEXT: li a5, 56
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a4, 32
+; RV64-NEXT: add a3, a4, a3
+; RV64-NEXT: addi a4, a0, -16
+; RV64-NEXT: sltu a0, a0, a4
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a4, a0, a4
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 2, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 8, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 16, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vsrl.vx v24, v8, a1, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a6, v0.t
-; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
-; RV64-NEXT: vsrl.vx v8, v8, a5, v0.t
-; RV64-NEXT: addi a7, a0, -16
-; RV64-NEXT: sltu a0, a0, a7
-; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a0, a0, a7
+; RV64-NEXT: vmv1r.v v6, v0
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 8, v0.t
+; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 2, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 16, v0.t
+; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v24, v8, a6, v0.t
+; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 8, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 16, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vsrl.vx v24, v16, a1, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a7, v0.t
+; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v24, v16, a6, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v8, a5, v0.t
+; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vnot.v v16, v16, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v8, v8, a5, v0.t
+; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: vand.vx v24, v24, a7, v0.t
; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vand.vx v24, v16, a3, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v16, a5, v0.t
; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a3, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v16, v16, a5, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vmul.vx v16, v16, a4, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a5, v0.t
+; RV64-NEXT: vmul.vx v16, v16, a3, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t
; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
@@ -4285,183 +4448,301 @@ define <16 x i64> @vp_ctlz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroex
define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_zero_undef_v32i64:
; RV32: # %bb.0:
-; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 49
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 5
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: li a1, 16
-; RV32-NEXT: mv a2, a0
+; RV32-NEXT: li a2, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v16, v0, 2
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 5
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
-; RV32-NEXT: bltu a0, a1, .LBB70_2
+; RV32-NEXT: vmv1r.v v24, v0
+; RV32-NEXT: vslidedown.vi v7, v0, 2
+; RV32-NEXT: mv a1, a0
+; RV32-NEXT: bltu a0, a2, .LBB70_2
; RV32-NEXT: # %bb.1:
-; RV32-NEXT: li a2, 16
+; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB70_2:
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV32-NEXT: li a1, 32
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 26
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: sub sp, sp, a2
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
+; RV32-NEXT: vmv1r.v v0, v24
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: li a2, 32
+; RV32-NEXT: addi a3, a0, -16
+; RV32-NEXT: sltu a0, a0, a3
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: and a0, a0, a3
; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: addi a3, a3, 1365
-; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
-; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v6, v0
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v16, 2, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v16, 8, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v16, 16, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: slli a5, a4, 3
+; RV32-NEXT: add a4, a5, a4
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: li a5, 25
+; RV32-NEXT: mul a4, a4, a5
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs1r.v v6, (a4) # vscale x 8-byte Folded Spill
; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a3
+; RV32-NEXT: vmv.v.x v16, a3
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a4, a3, 4
+; RV32-NEXT: add a3, a4, a3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 24
+; RV32-NEXT: li a4, 25
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a3, 209715
-; RV32-NEXT: addi a3, a3, 819
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 41
+; RV32-NEXT: li a4, 25
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 41
+; RV32-NEXT: li a4, 25
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a4, a3, 4
+; RV32-NEXT: add a3, a4, a3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 41
+; RV32-NEXT: li a4, 25
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a4, 61681
-; RV32-NEXT: lui a5, 4112
-; RV32-NEXT: li a3, 56
-; RV32-NEXT: addi a4, a4, -241
-; RV32-NEXT: addi a5, a5, 257
-; RV32-NEXT: vsetvli a6, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a4
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a4, a4, 3
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a4, a3, 3
+; RV32-NEXT: add a3, a4, a3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v24, v16, a2, v0.t
+; RV32-NEXT: vor.vv v16, v16, v24, v0.t
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: lui a2, 209715
+; RV32-NEXT: addi a2, a2, 819
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v8, v16, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a5
-; RV32-NEXT: addi a4, sp, 16
-; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a3, v0.t
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 3
+; RV32-NEXT: add a2, a3, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: addi a2, a0, -16
-; RV32-NEXT: sltu a0, a0, a2
-; RV32-NEXT: addi a0, a0, -1
-; RV32-NEXT: and a0, a0, a2
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs1r.v v7, (a2) # vscale x 8-byte Folded Spill
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 4
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 5
+; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a4, a2, 5
-; RV32-NEXT: add a2, a4, a2
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
+; RV32-NEXT: vmv1r.v v7, v0
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 3
+; RV32-NEXT: add a2, a3, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v24, 4, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 3
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vadd.vv v24, v8, v24, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a3, a2, 4
+; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v8, v24, 1, v0.t
-; RV32-NEXT: vor.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 41
-; RV32-NEXT: mul a0, a0, a1
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a2, 61681
+; RV32-NEXT: lui a3, 4112
+; RV32-NEXT: addi a2, a2, -241
+; RV32-NEXT: addi a3, a3, 257
; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a4, 25
+; RV32-NEXT: mul a2, a2, a4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a4, a2, 4
+; RV32-NEXT: add a2, a4, a2
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a3, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a3
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
+; RV32-NEXT: li a2, 56
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 25
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 49
+; RV32-NEXT: li a1, 26
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -4472,88 +4753,133 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV64-LABEL: vp_ctlz_zero_undef_v32i64:
; RV64: # %bb.0:
; RV64-NEXT: li a2, 16
-; RV64-NEXT: mv a1, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v7, v0, 2
+; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB70_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB70_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: li a1, 32
+; RV64-NEXT: li a6, 32
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
; RV64-NEXT: lui a5, 4112
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: addi a3, a3, 819
-; RV64-NEXT: addi a4, a4, -241
-; RV64-NEXT: addi a5, a5, 257
-; RV64-NEXT: slli a6, a2, 32
-; RV64-NEXT: add a6, a2, a6
+; RV64-NEXT: addi a7, a2, 1365
+; RV64-NEXT: addi a2, a3, 819
+; RV64-NEXT: addi a3, a4, -241
+; RV64-NEXT: addi a4, a5, 257
+; RV64-NEXT: slli a5, a7, 32
+; RV64-NEXT: add a7, a7, a5
+; RV64-NEXT: slli a5, a2, 32
+; RV64-NEXT: add a5, a2, a5
; RV64-NEXT: slli a2, a3, 32
-; RV64-NEXT: add a3, a3, a2
-; RV64-NEXT: slli a2, a4, 32
-; RV64-NEXT: add a2, a4, a2
-; RV64-NEXT: slli a4, a5, 32
-; RV64-NEXT: add a4, a5, a4
-; RV64-NEXT: li a5, 56
+; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a3, a4, 32
+; RV64-NEXT: add a3, a4, a3
+; RV64-NEXT: addi a4, a0, -16
+; RV64-NEXT: sltu a0, a0, a4
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a4, a0, a4
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 2, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 8, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 16, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vsrl.vx v24, v8, a1, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vnot.v v8, v8, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a6, v0.t
-; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a3, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
-; RV64-NEXT: vsrl.vx v8, v8, a5, v0.t
-; RV64-NEXT: addi a7, a0, -16
-; RV64-NEXT: sltu a0, a0, a7
-; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a0, a0, a7
+; RV64-NEXT: vmv1r.v v6, v0
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 8, v0.t
+; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 2, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 16, v0.t
+; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v24, v8, a6, v0.t
+; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 8, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 16, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vsrl.vx v24, v16, a1, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a7, v0.t
+; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v24, v16, a6, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v8, a5, v0.t
+; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vnot.v v16, v16, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v8, v8, a5, v0.t
+; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: vand.vx v24, v24, a7, v0.t
; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vand.vx v24, v16, a3, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v16, a5, v0.t
; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a3, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v16, v16, a5, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vmul.vx v16, v16, a4, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a5, v0.t
+; RV64-NEXT: vmul.vx v16, v16, a3, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t
; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
index 289948dbbf87d..ec6b0290a18ce 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
@@ -1394,219 +1394,122 @@ define <32 x i64> @vp_ctpop_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 49
+; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: li a1, 16
-; RV32-NEXT: mv a2, a0
+; RV32-NEXT: li a2, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v16, v0, 2
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 48
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
-; RV32-NEXT: bltu a0, a1, .LBB34_2
+; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vslidedown.vi v7, v0, 2
+; RV32-NEXT: mv a1, a0
+; RV32-NEXT: bltu a0, a2, .LBB34_2
; RV32-NEXT: # %bb.1:
-; RV32-NEXT: li a2, 16
+; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB34_2:
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV32-NEXT: lui a1, 349525
-; RV32-NEXT: addi a1, a1, 1365
+; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a1
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a1, a1, a3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vmv.v.x v24, a2
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24, v0.t
; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a1, 209715
-; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a1
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 40
-; RV32-NEXT: mul a1, a1, a3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 40
-; RV32-NEXT: mul a1, a1, a3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 40
-; RV32-NEXT: mul a1, a1, a3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a3, 61681
-; RV32-NEXT: lui a4, 4112
-; RV32-NEXT: li a1, 56
-; RV32-NEXT: addi a3, a3, -241
-; RV32-NEXT: addi a4, a4, 257
-; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a4
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
-; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v6, v0
; RV32-NEXT: addi a2, a0, -16
; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a2
+; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 5
+; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v16, v16, v24, v0.t
+; RV32-NEXT: lui a2, 209715
+; RV32-NEXT: addi a2, a2, 819
+; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
+; RV32-NEXT: addi a3, sp, 16
+; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: vmv1r.v v0, v6
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 48
-; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v8, v24, 1, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 48
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 48
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 40
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 48
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 48
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 48
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 48
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 48
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 48
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 48
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a2, 61681
+; RV32-NEXT: addi a2, a2, -241
+; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: lui a2, 4112
+; RV32-NEXT: addi a2, a2, 257
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
+; RV32-NEXT: li a2, 56
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 48
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 48
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 49
+; RV32-NEXT: li a1, 24
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -1617,61 +1520,82 @@ define <32 x i64> @vp_ctpop_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; RV64-LABEL: vp_ctpop_v32i64:
; RV64: # %bb.0:
; RV64-NEXT: li a2, 16
-; RV64-NEXT: mv a1, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v7, v0, 2
+; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB34_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB34_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: lui a1, 349525
-; RV64-NEXT: lui a2, 209715
-; RV64-NEXT: lui a3, 61681
-; RV64-NEXT: lui a4, 4112
-; RV64-NEXT: addi a1, a1, 1365
-; RV64-NEXT: addi a2, a2, 819
-; RV64-NEXT: addi a3, a3, -241
-; RV64-NEXT: addi a4, a4, 257
-; RV64-NEXT: slli a5, a1, 32
-; RV64-NEXT: add a1, a1, a5
-; RV64-NEXT: slli a5, a2, 32
-; RV64-NEXT: add a2, a2, a5
-; RV64-NEXT: slli a5, a3, 32
-; RV64-NEXT: add a3, a3, a5
-; RV64-NEXT: slli a5, a4, 32
-; RV64-NEXT: add a4, a4, a5
-; RV64-NEXT: li a5, 56
-; RV64-NEXT: vand.vx v24, v24, a1, v0.t
-; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
-; RV64-NEXT: vsrl.vx v8, v8, a5, v0.t
-; RV64-NEXT: addi a6, a0, -16
-; RV64-NEXT: sltu a0, a0, a6
+; RV64-NEXT: lui a2, 349525
+; RV64-NEXT: lui a3, 209715
+; RV64-NEXT: lui a4, 61681
+; RV64-NEXT: lui a5, 4112
+; RV64-NEXT: addi a2, a2, 1365
+; RV64-NEXT: addi a3, a3, 819
+; RV64-NEXT: addi a4, a4, -241
+; RV64-NEXT: addi a5, a5, 257
+; RV64-NEXT: slli a6, a2, 32
+; RV64-NEXT: add a6, a2, a6
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: add a7, a3, a2
+; RV64-NEXT: slli a3, a4, 32
+; RV64-NEXT: add a3, a4, a3
+; RV64-NEXT: slli a2, a5, 32
+; RV64-NEXT: add a2, a5, a2
+; RV64-NEXT: addi a4, a0, -16
+; RV64-NEXT: sltu a0, a0, a4
; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a0, a0, a6
+; RV64-NEXT: and a4, a0, a4
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v6, v0
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a6, v0.t
; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vand.vx v24, v16, a2, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v8, a7, v0.t
+; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV64-NEXT: vand.vx v8, v8, a7, v0.t
+; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v16, a7, v0.t
; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a2, v0.t
+; RV64-NEXT: vand.vx v16, v16, a7, v0.t
; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v8, v8, a3, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vmul.vx v8, v8, a2, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v16, a3, v0.t
-; RV64-NEXT: vmul.vx v16, v16, a4, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a5, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vmul.vx v16, v16, a2, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t
; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.ctpop.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
index 46d62f48e7ef8..5ad84a7fe96c5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
@@ -1526,160 +1526,253 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 49
+; RV32-NEXT: li a2, 26
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 5
-; RV32-NEXT: add a1, a2, a1
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: li a1, 16
-; RV32-NEXT: mv a2, a0
-; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v16, v0, 2
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 5
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
-; RV32-NEXT: bltu a0, a1, .LBB34_2
-; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16
-; RV32-NEXT: .LBB34_2:
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vadd.vi v16, v8, -1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: lui a1, 349525
-; RV32-NEXT: vand.vv v24, v8, v16, v0.t
-; RV32-NEXT: addi a1, a1, 1365
-; RV32-NEXT: vsrl.vi v16, v24, 1, v0.t
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vi v24, v0, 2
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a3, 24
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v16, v16, v8, v0.t
-; RV32-NEXT: vsub.vv v8, v24, v16, v0.t
-; RV32-NEXT: lui a1, 209715
-; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a1
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 41
-; RV32-NEXT: mul a1, a1, a3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 41
-; RV32-NEXT: mul a1, a1, a3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 41
-; RV32-NEXT: mul a1, a1, a3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
+; RV32-NEXT: mv a1, a0
+; RV32-NEXT: bltu a0, a2, .LBB34_2
+; RV32-NEXT: # %bb.1:
+; RV32-NEXT: li a1, 16
+; RV32-NEXT: .LBB34_2:
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vadd.vi v24, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: lui a2, 349525
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a3, 61681
-; RV32-NEXT: lui a4, 4112
-; RV32-NEXT: li a1, 56
-; RV32-NEXT: addi a3, a3, -241
-; RV32-NEXT: addi a4, a4, 257
-; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
+; RV32-NEXT: addi a2, a2, 1365
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
+; RV32-NEXT: li a4, 25
+; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a4
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.v.x v24, a2
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v16, v24, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
; RV32-NEXT: addi a2, a0, -16
; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 5
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v7, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 5
-; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vi v8, v24, -1, v0.t
-; RV32-NEXT: vnot.v v24, v24, v0.t
-; RV32-NEXT: vand.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vadd.vi v8, v16, -1, v0.t
+; RV32-NEXT: vnot.v v16, v16, v0.t
+; RV32-NEXT: vand.vv v8, v16, v8, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: lui a2, 209715
+; RV32-NEXT: addi a2, a2, 819
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v8, v24, v16, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 41
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v24, 4, v0.t
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vadd.vv v24, v8, v24, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v7, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a2, 61681
+; RV32-NEXT: addi a2, a2, -241
; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vmv1r.v v6, v0
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: lui a2, 4112
+; RV32-NEXT: addi a2, a2, 257
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
+; RV32-NEXT: li a2, 56
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 49
+; RV32-NEXT: li a1, 26
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -1690,9 +1783,9 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV64-LABEL: vp_cttz_v32i64:
; RV64: # %bb.0:
; RV64-NEXT: li a2, 16
-; RV64-NEXT: mv a1, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v7, v0, 2
+; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB34_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
@@ -1700,57 +1793,78 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vadd.vi v24, v8, -1, v0.t
; RV64-NEXT: vnot.v v8, v8, v0.t
-; RV64-NEXT: lui a1, 349525
-; RV64-NEXT: lui a2, 209715
-; RV64-NEXT: lui a3, 61681
-; RV64-NEXT: lui a4, 4112
-; RV64-NEXT: addi a1, a1, 1365
-; RV64-NEXT: addi a2, a2, 819
-; RV64-NEXT: addi a3, a3, -241
-; RV64-NEXT: addi a4, a4, 257
-; RV64-NEXT: slli a5, a1, 32
-; RV64-NEXT: add a1, a1, a5
-; RV64-NEXT: slli a5, a2, 32
-; RV64-NEXT: add a2, a2, a5
-; RV64-NEXT: slli a5, a3, 32
-; RV64-NEXT: add a3, a3, a5
-; RV64-NEXT: slli a5, a4, 32
-; RV64-NEXT: add a4, a4, a5
-; RV64-NEXT: li a5, 56
+; RV64-NEXT: lui a2, 349525
+; RV64-NEXT: lui a3, 209715
+; RV64-NEXT: lui a4, 61681
+; RV64-NEXT: lui a5, 4112
+; RV64-NEXT: addi a2, a2, 1365
+; RV64-NEXT: addi a3, a3, 819
+; RV64-NEXT: addi a4, a4, -241
+; RV64-NEXT: addi a5, a5, 257
+; RV64-NEXT: slli a6, a2, 32
+; RV64-NEXT: add a6, a2, a6
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: add a7, a3, a2
+; RV64-NEXT: slli a2, a4, 32
+; RV64-NEXT: add a2, a4, a2
+; RV64-NEXT: slli a3, a5, 32
+; RV64-NEXT: add a3, a5, a3
+; RV64-NEXT: addi a4, a0, -16
+; RV64-NEXT: sltu a0, a0, a4
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a4, a0, a4
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vand.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a1, v0.t
-; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
-; RV64-NEXT: vsrl.vx v8, v8, a5, v0.t
-; RV64-NEXT: addi a6, a0, -16
-; RV64-NEXT: sltu a0, a0, a6
-; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a0, a0, a6
+; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v6, v0
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vadd.vi v24, v16, -1, v0.t
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vadd.vi v8, v16, -1, v0.t
; RV64-NEXT: vnot.v v16, v16, v0.t
-; RV64-NEXT: vand.vv v16, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a1, v0.t
-; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vand.vx v24, v16, a2, v0.t
-; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vand.vv v8, v16, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v16, v24, a7, v0.t
+; RV64-NEXT: vsrl.vi v24, v24, 2, v0.t
+; RV64-NEXT: vand.vx v24, v24, a7, v0.t
+; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a3, v0.t
-; RV64-NEXT: vmul.vx v16, v16, a4, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a5, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v8, a7, v0.t
+; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV64-NEXT: vand.vx v8, v8, a7, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v16, v16, a2, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vadd.vv v24, v24, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vmul.vx v8, v16, a3, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v16, v24, 4, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vand.vx v16, v16, a2, v0.t
+; RV64-NEXT: vmul.vx v16, v16, a3, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t
; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
@@ -3455,160 +3569,253 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 49
+; RV32-NEXT: li a2, 26
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 5
-; RV32-NEXT: add a1, a2, a1
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: li a1, 16
-; RV32-NEXT: mv a2, a0
-; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v16, v0, 2
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 5
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
-; RV32-NEXT: bltu a0, a1, .LBB70_2
-; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16
-; RV32-NEXT: .LBB70_2:
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vadd.vi v16, v8, -1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: lui a1, 349525
-; RV32-NEXT: vand.vv v24, v8, v16, v0.t
-; RV32-NEXT: addi a1, a1, 1365
-; RV32-NEXT: vsrl.vi v16, v24, 1, v0.t
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v8, a1
+; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vi v24, v0, 2
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a3, 24
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v16, v16, v8, v0.t
-; RV32-NEXT: vsub.vv v8, v24, v16, v0.t
-; RV32-NEXT: lui a1, 209715
-; RV32-NEXT: addi a1, a1, 819
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a1
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 41
-; RV32-NEXT: mul a1, a1, a3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 41
-; RV32-NEXT: mul a1, a1, a3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 41
-; RV32-NEXT: mul a1, a1, a3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
+; RV32-NEXT: mv a1, a0
+; RV32-NEXT: bltu a0, a2, .LBB70_2
+; RV32-NEXT: # %bb.1:
+; RV32-NEXT: li a1, 16
+; RV32-NEXT: .LBB70_2:
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vadd.vi v24, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: lui a2, 349525
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a3, 61681
-; RV32-NEXT: lui a4, 4112
-; RV32-NEXT: li a1, 56
-; RV32-NEXT: addi a3, a3, -241
-; RV32-NEXT: addi a4, a4, 257
-; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
+; RV32-NEXT: addi a2, a2, 1365
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
+; RV32-NEXT: li a4, 25
+; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a4
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.v.x v24, a2
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v16, v24, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
; RV32-NEXT: addi a2, a0, -16
; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 5
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v7, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 5
-; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vi v8, v24, -1, v0.t
-; RV32-NEXT: vnot.v v24, v24, v0.t
-; RV32-NEXT: vand.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 24
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vadd.vi v8, v16, -1, v0.t
+; RV32-NEXT: vnot.v v16, v16, v0.t
+; RV32-NEXT: vand.vv v8, v16, v8, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: lui a2, 209715
+; RV32-NEXT: addi a2, a2, 819
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v8, v24, v16, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a2, 41
-; RV32-NEXT: mul a0, a0, a2
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v24, 4, v0.t
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vadd.vv v24, v8, v24, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 25
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v7, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a2, 61681
+; RV32-NEXT: addi a2, a2, -241
; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 4
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: vmv1r.v v6, v0
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: lui a2, 4112
+; RV32-NEXT: addi a2, a2, 257
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a2
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
+; RV32-NEXT: li a2, 56
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: slli a0, a0, 3
-; RV32-NEXT: add a0, sp, a0
-; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 49
+; RV32-NEXT: li a1, 26
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -3619,9 +3826,9 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV64-LABEL: vp_cttz_zero_undef_v32i64:
; RV64: # %bb.0:
; RV64-NEXT: li a2, 16
-; RV64-NEXT: mv a1, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v7, v0, 2
+; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB70_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
@@ -3629,57 +3836,78 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vadd.vi v24, v8, -1, v0.t
; RV64-NEXT: vnot.v v8, v8, v0.t
-; RV64-NEXT: lui a1, 349525
-; RV64-NEXT: lui a2, 209715
-; RV64-NEXT: lui a3, 61681
-; RV64-NEXT: lui a4, 4112
-; RV64-NEXT: addi a1, a1, 1365
-; RV64-NEXT: addi a2, a2, 819
-; RV64-NEXT: addi a3, a3, -241
-; RV64-NEXT: addi a4, a4, 257
-; RV64-NEXT: slli a5, a1, 32
-; RV64-NEXT: add a1, a1, a5
-; RV64-NEXT: slli a5, a2, 32
-; RV64-NEXT: add a2, a2, a5
-; RV64-NEXT: slli a5, a3, 32
-; RV64-NEXT: add a3, a3, a5
-; RV64-NEXT: slli a5, a4, 32
-; RV64-NEXT: add a4, a4, a5
-; RV64-NEXT: li a5, 56
+; RV64-NEXT: lui a2, 349525
+; RV64-NEXT: lui a3, 209715
+; RV64-NEXT: lui a4, 61681
+; RV64-NEXT: lui a5, 4112
+; RV64-NEXT: addi a2, a2, 1365
+; RV64-NEXT: addi a3, a3, 819
+; RV64-NEXT: addi a4, a4, -241
+; RV64-NEXT: addi a5, a5, 257
+; RV64-NEXT: slli a6, a2, 32
+; RV64-NEXT: add a6, a2, a6
+; RV64-NEXT: slli a2, a3, 32
+; RV64-NEXT: add a7, a3, a2
+; RV64-NEXT: slli a2, a4, 32
+; RV64-NEXT: add a2, a4, a2
+; RV64-NEXT: slli a3, a5, 32
+; RV64-NEXT: add a3, a5, a3
+; RV64-NEXT: addi a4, a0, -16
+; RV64-NEXT: sltu a0, a0, a4
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a4, a0, a4
+; RV64-NEXT: li a0, 56
; RV64-NEXT: vand.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a1, v0.t
-; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v24, v8, a2, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vand.vx v8, v8, a3, v0.t
-; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
-; RV64-NEXT: vsrl.vx v8, v8, a5, v0.t
-; RV64-NEXT: addi a6, a0, -16
-; RV64-NEXT: sltu a0, a0, a6
-; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a0, a0, a6
+; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v6, v0
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vadd.vi v24, v16, -1, v0.t
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vadd.vi v8, v16, -1, v0.t
; RV64-NEXT: vnot.v v16, v16, v0.t
-; RV64-NEXT: vand.vv v16, v16, v24, v0.t
-; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a1, v0.t
-; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vand.vx v24, v16, a2, v0.t
-; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vand.vv v8, v16, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v16, v24, a7, v0.t
+; RV64-NEXT: vsrl.vi v24, v24, 2, v0.t
+; RV64-NEXT: vand.vx v24, v24, a7, v0.t
+; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV64-NEXT: vand.vx v16, v16, a3, v0.t
-; RV64-NEXT: vmul.vx v16, v16, a4, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a5, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v24, v8, a7, v0.t
+; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV64-NEXT: vand.vx v8, v8, a7, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v16, v16, a2, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vadd.vv v24, v24, v8, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vmul.vx v8, v16, a3, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v16, v24, 4, v0.t
+; RV64-NEXT: vmv1r.v v0, v6
+; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vand.vx v16, v16, a2, v0.t
+; RV64-NEXT: vmul.vx v16, v16, a3, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t
; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
index 5060e01cf9ee6..f37a3cf5e6bb2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
@@ -324,23 +324,24 @@ define i1 @extractelt_v256i1(ptr %x, i64 %idx) nounwind {
; RV32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
; RV32-NEXT: addi s0, sp, 384
; RV32-NEXT: andi sp, sp, -128
+; RV32-NEXT: zext.b a1, a1
; RV32-NEXT: li a2, 128
+; RV32-NEXT: addi a3, a0, 128
; RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; RV32-NEXT: vle8.v v16, (a3)
+; RV32-NEXT: mv a2, sp
; RV32-NEXT: vle8.v v8, (a0)
-; RV32-NEXT: addi a0, a0, 128
-; RV32-NEXT: vle8.v v16, (a0)
-; RV32-NEXT: vmv.v.i v24, 0
+; RV32-NEXT: addi a0, sp, 128
+; RV32-NEXT: add a1, a2, a1
+; RV32-NEXT: vmseq.vi v24, v16, 0
+; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: vmseq.vi v0, v8, 0
-; RV32-NEXT: vmerge.vim v8, v24, 1, v0
-; RV32-NEXT: vmseq.vi v0, v16, 0
-; RV32-NEXT: vmerge.vim v16, v24, 1, v0
-; RV32-NEXT: zext.b a0, a1
-; RV32-NEXT: mv a1, sp
-; RV32-NEXT: addi a2, sp, 128
-; RV32-NEXT: add a0, a1, a0
-; RV32-NEXT: vse8.v v8, (a1)
-; RV32-NEXT: vse8.v v16, (a2)
-; RV32-NEXT: lbu a0, 0(a0)
+; RV32-NEXT: vmerge.vim v8, v16, 1, v0
+; RV32-NEXT: vmv1r.v v0, v24
+; RV32-NEXT: vmerge.vim v16, v16, 1, v0
+; RV32-NEXT: vse8.v v8, (a2)
+; RV32-NEXT: vse8.v v16, (a0)
+; RV32-NEXT: lbu a0, 0(a1)
; RV32-NEXT: addi sp, s0, -384
; RV32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
@@ -354,23 +355,24 @@ define i1 @extractelt_v256i1(ptr %x, i64 %idx) nounwind {
; RV64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
; RV64-NEXT: addi s0, sp, 384
; RV64-NEXT: andi sp, sp, -128
+; RV64-NEXT: zext.b a1, a1
; RV64-NEXT: li a2, 128
+; RV64-NEXT: addi a3, a0, 128
; RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; RV64-NEXT: vle8.v v16, (a3)
+; RV64-NEXT: mv a2, sp
; RV64-NEXT: vle8.v v8, (a0)
-; RV64-NEXT: addi a0, a0, 128
-; RV64-NEXT: vle8.v v16, (a0)
-; RV64-NEXT: vmv.v.i v24, 0
+; RV64-NEXT: addi a0, sp, 128
+; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: vmseq.vi v24, v16, 0
+; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: vmseq.vi v0, v8, 0
-; RV64-NEXT: vmerge.vim v8, v24, 1, v0
-; RV64-NEXT: vmseq.vi v0, v16, 0
-; RV64-NEXT: vmerge.vim v16, v24, 1, v0
-; RV64-NEXT: zext.b a0, a1
-; RV64-NEXT: mv a1, sp
-; RV64-NEXT: addi a2, sp, 128
-; RV64-NEXT: add a0, a1, a0
-; RV64-NEXT: vse8.v v8, (a1)
-; RV64-NEXT: vse8.v v16, (a2)
-; RV64-NEXT: lbu a0, 0(a0)
+; RV64-NEXT: vmerge.vim v8, v16, 1, v0
+; RV64-NEXT: vmv1r.v v0, v24
+; RV64-NEXT: vmerge.vim v16, v16, 1, v0
+; RV64-NEXT: vse8.v v8, (a2)
+; RV64-NEXT: vse8.v v16, (a0)
+; RV64-NEXT: lbu a0, 0(a1)
; RV64-NEXT: addi sp, s0, -384
; RV64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
@@ -384,23 +386,24 @@ define i1 @extractelt_v256i1(ptr %x, i64 %idx) nounwind {
; RV32ZBS-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
; RV32ZBS-NEXT: addi s0, sp, 384
; RV32ZBS-NEXT: andi sp, sp, -128
+; RV32ZBS-NEXT: zext.b a1, a1
; RV32ZBS-NEXT: li a2, 128
+; RV32ZBS-NEXT: addi a3, a0, 128
; RV32ZBS-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; RV32ZBS-NEXT: vle8.v v16, (a3)
+; RV32ZBS-NEXT: mv a2, sp
; RV32ZBS-NEXT: vle8.v v8, (a0)
-; RV32ZBS-NEXT: addi a0, a0, 128
-; RV32ZBS-NEXT: vle8.v v16, (a0)
-; RV32ZBS-NEXT: vmv.v.i v24, 0
+; RV32ZBS-NEXT: addi a0, sp, 128
+; RV32ZBS-NEXT: add a1, a2, a1
+; RV32ZBS-NEXT: vmseq.vi v24, v16, 0
+; RV32ZBS-NEXT: vmv.v.i v16, 0
; RV32ZBS-NEXT: vmseq.vi v0, v8, 0
-; RV32ZBS-NEXT: vmerge.vim v8, v24, 1, v0
-; RV32ZBS-NEXT: vmseq.vi v0, v16, 0
-; RV32ZBS-NEXT: vmerge.vim v16, v24, 1, v0
-; RV32ZBS-NEXT: zext.b a0, a1
-; RV32ZBS-NEXT: mv a1, sp
-; RV32ZBS-NEXT: addi a2, sp, 128
-; RV32ZBS-NEXT: add a0, a1, a0
-; RV32ZBS-NEXT: vse8.v v8, (a1)
-; RV32ZBS-NEXT: vse8.v v16, (a2)
-; RV32ZBS-NEXT: lbu a0, 0(a0)
+; RV32ZBS-NEXT: vmerge.vim v8, v16, 1, v0
+; RV32ZBS-NEXT: vmv1r.v v0, v24
+; RV32ZBS-NEXT: vmerge.vim v16, v16, 1, v0
+; RV32ZBS-NEXT: vse8.v v8, (a2)
+; RV32ZBS-NEXT: vse8.v v16, (a0)
+; RV32ZBS-NEXT: lbu a0, 0(a1)
; RV32ZBS-NEXT: addi sp, s0, -384
; RV32ZBS-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
; RV32ZBS-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
@@ -414,23 +417,24 @@ define i1 @extractelt_v256i1(ptr %x, i64 %idx) nounwind {
; RV64ZBS-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
; RV64ZBS-NEXT: addi s0, sp, 384
; RV64ZBS-NEXT: andi sp, sp, -128
+; RV64ZBS-NEXT: zext.b a1, a1
; RV64ZBS-NEXT: li a2, 128
+; RV64ZBS-NEXT: addi a3, a0, 128
; RV64ZBS-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; RV64ZBS-NEXT: vle8.v v16, (a3)
+; RV64ZBS-NEXT: mv a2, sp
; RV64ZBS-NEXT: vle8.v v8, (a0)
-; RV64ZBS-NEXT: addi a0, a0, 128
-; RV64ZBS-NEXT: vle8.v v16, (a0)
-; RV64ZBS-NEXT: vmv.v.i v24, 0
+; RV64ZBS-NEXT: addi a0, sp, 128
+; RV64ZBS-NEXT: add a1, a2, a1
+; RV64ZBS-NEXT: vmseq.vi v24, v16, 0
+; RV64ZBS-NEXT: vmv.v.i v16, 0
; RV64ZBS-NEXT: vmseq.vi v0, v8, 0
-; RV64ZBS-NEXT: vmerge.vim v8, v24, 1, v0
-; RV64ZBS-NEXT: vmseq.vi v0, v16, 0
-; RV64ZBS-NEXT: vmerge.vim v16, v24, 1, v0
-; RV64ZBS-NEXT: zext.b a0, a1
-; RV64ZBS-NEXT: mv a1, sp
-; RV64ZBS-NEXT: addi a2, sp, 128
-; RV64ZBS-NEXT: add a0, a1, a0
-; RV64ZBS-NEXT: vse8.v v8, (a1)
-; RV64ZBS-NEXT: vse8.v v16, (a2)
-; RV64ZBS-NEXT: lbu a0, 0(a0)
+; RV64ZBS-NEXT: vmerge.vim v8, v16, 1, v0
+; RV64ZBS-NEXT: vmv1r.v v0, v24
+; RV64ZBS-NEXT: vmerge.vim v16, v16, 1, v0
+; RV64ZBS-NEXT: vse8.v v8, (a2)
+; RV64ZBS-NEXT: vse8.v v16, (a0)
+; RV64ZBS-NEXT: lbu a0, 0(a1)
; RV64ZBS-NEXT: addi sp, s0, -384
; RV64ZBS-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; RV64ZBS-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
index de4cff9b4c3e0..b5ec8d73c48de 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
@@ -31,12 +31,12 @@ define <2 x half> @vp_floor_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl)
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -115,12 +115,12 @@ define <4 x half> @vp_floor_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl)
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
index 21dab2385a796..5f8272ef76ef9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
@@ -612,16 +612,13 @@ define <32 x double> @vfmax_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a1)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
@@ -634,25 +631,26 @@ define <32 x double> @vfmax_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: .LBB25_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vmfeq.vv v7, v24, v24
; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
-; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
; CHECK-NEXT: vfmax.vv v8, v8, v16
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -660,7 +658,10 @@ define <32 x double> @vfmax_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
; CHECK-NEXT: vfmax.vv v16, v16, v24
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
index 45c047b12f704..c173443acb20a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
@@ -612,16 +612,13 @@ define <32 x double> @vfmin_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a1)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
@@ -634,25 +631,26 @@ define <32 x double> @vfmin_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: .LBB25_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vmfeq.vv v7, v24, v24
; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
-; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
; CHECK-NEXT: vfmin.vv v8, v8, v16
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -660,7 +658,10 @@ define <32 x double> @vfmin_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
; CHECK-NEXT: vfmin.vv v16, v16, v24
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
index 19bedd47808fd..135088631abac 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
@@ -87,9 +87,9 @@ define <32 x double> @vfpext_v32f32_v32f64(<32 x float> %a, <32 x i1> %m, i32 ze
; CHECK-LABEL: vfpext_v32f32_v32f64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB7_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
index b298a37655a2f..96eda109e1c70 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
@@ -367,9 +367,9 @@ define <32 x i64> @vfptosi_v32i64_v32f64(<32 x double> %va, <32 x i1> %m, i32 ze
; CHECK-LABEL: vfptosi_v32i64_v32f64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB25_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
index ac83f1e630ce3..4020100bf364b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
@@ -367,9 +367,9 @@ define <32 x i64> @vfptoui_v32i64_v32f64(<32 x double> %va, <32 x i1> %m, i32 ze
; CHECK-LABEL: vfptoui_v32i64_v32f64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB25_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
index 472ed89cce10c..e509722b623a2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
@@ -89,8 +89,8 @@ define <32 x float> @vfptrunc_v32f32_v32f64(<32 x double> %a, <32 x i1> %m, i32
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vslidedown.vi v12, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB7_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
index e1fbf9c511d81..488a076c316be 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
@@ -530,187 +530,214 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 76
+; RV32-NEXT: li a3, 74
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: sub sp, sp, a2
-; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xcc, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 76 * vlenb
-; RV32-NEXT: addi a5, a1, 128
-; RV32-NEXT: li a6, 32
-; RV32-NEXT: lui a4, 12291
-; RV32-NEXT: lui a3, 49164
-; RV32-NEXT: lui a2, 196656
-; RV32-NEXT: vsetvli zero, a6, e32, m8, ta, ma
-; RV32-NEXT: vle32.v v8, (a5)
+; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xca, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 74 * vlenb
+; RV32-NEXT: addi a4, a1, 128
+; RV32-NEXT: li a2, 32
+; RV32-NEXT: lui a5, 12291
+; RV32-NEXT: lui a3, %hi(.LCPI27_0)
+; RV32-NEXT: addi a3, a3, %lo(.LCPI27_0)
+; RV32-NEXT: lui a6, 49164
+; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; RV32-NEXT: vle32.v v8, (a4)
+; RV32-NEXT: lui a4, 196656
+; RV32-NEXT: addi a5, a5, 3
+; RV32-NEXT: vmv.s.x v0, a5
; RV32-NEXT: lui a5, 786624
-; RV32-NEXT: vle32.v v24, (a1)
-; RV32-NEXT: addi a4, a4, 3
-; RV32-NEXT: vmv.s.x v0, a4
-; RV32-NEXT: lui a4, 768
-; RV32-NEXT: addi a3, a3, 12
-; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
-; RV32-NEXT: csrr a6, vlenb
-; RV32-NEXT: li a7, 48
-; RV32-NEXT: mul a6, a6, a7
-; RV32-NEXT: add a6, sp, a6
-; RV32-NEXT: addi a6, a6, 16
-; RV32-NEXT: vs8r.v v16, (a6) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv.s.x v0, a3
-; RV32-NEXT: lui a3, 3073
-; RV32-NEXT: addi a2, a2, 48
+; RV32-NEXT: vle32.v v16, (a1)
+; RV32-NEXT: addi a6, a6, 12
+; RV32-NEXT: vmv.s.x v7, a6
+; RV32-NEXT: lui a6, 768
+; RV32-NEXT: addi a4, a4, 48
+; RV32-NEXT: vmerge.vvm v24, v8, v16, v0
+; RV32-NEXT: csrr a7, vlenb
+; RV32-NEXT: li t0, 66
+; RV32-NEXT: mul a7, a7, t0
+; RV32-NEXT: add a7, sp, a7
+; RV32-NEXT: addi a7, a7, 16
+; RV32-NEXT: vs8r.v v24, (a7) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.s.x v6, a4
+; RV32-NEXT: lui a4, 3073
; RV32-NEXT: addi a5, a5, 192
-; RV32-NEXT: addi a4, a4, 768
-; RV32-NEXT: addi a3, a3, -1024
-; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
-; RV32-NEXT: csrr a6, vlenb
-; RV32-NEXT: li a7, 20
-; RV32-NEXT: mul a6, a6, a7
-; RV32-NEXT: add a6, sp, a6
-; RV32-NEXT: addi a6, a6, 16
-; RV32-NEXT: vs8r.v v16, (a6) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv.s.x v0, a2
-; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 5
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv.s.x v0, a5
-; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a5, 40
-; RV32-NEXT: mul a2, a2, a5
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv.s.x v0, a4
-; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a4, 56
-; RV32-NEXT: mul a2, a2, a4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv.s.x v0, a3
-; RV32-NEXT: vmerge.vvm v8, v8, v24, v0
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 6
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: addi a6, a6, 768
+; RV32-NEXT: addi a4, a4, -1024
+; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vmerge.vvm v24, v8, v16, v0
+; RV32-NEXT: csrr a7, vlenb
+; RV32-NEXT: li t0, 26
+; RV32-NEXT: mul a7, a7, t0
+; RV32-NEXT: add a7, sp, a7
+; RV32-NEXT: addi a7, a7, 16
+; RV32-NEXT: vs8r.v v24, (a7) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.s.x v5, a5
+; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vmerge.vvm v24, v8, v16, v0
+; RV32-NEXT: csrr a5, vlenb
+; RV32-NEXT: li a7, 34
+; RV32-NEXT: mul a5, a5, a7
+; RV32-NEXT: add a5, sp, a5
+; RV32-NEXT: addi a5, a5, 16
+; RV32-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.s.x v4, a6
+; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; RV32-NEXT: vle16.v v6, (a3)
+; RV32-NEXT: vmv1r.v v0, v5
+; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; RV32-NEXT: vmerge.vvm v24, v8, v16, v0
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a5, 42
+; RV32-NEXT: mul a3, a3, a5
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.s.x v5, a4
+; RV32-NEXT: vmv1r.v v0, v4
+; RV32-NEXT: vmerge.vvm v24, v8, v16, v0
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 50
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v5
+; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 58
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 66
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vl8r.v v8, (a3) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV32-NEXT: vrgatherei16.vv v16, v8, v6
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 10
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: addi a1, a1, 256
-; RV32-NEXT: lui a2, 12
-; RV32-NEXT: lui a3, 3
-; RV32-NEXT: li a4, 48
-; RV32-NEXT: li a5, 192
+; RV32-NEXT: lui a3, 12
+; RV32-NEXT: lui a4, 3
+; RV32-NEXT: li a5, 48
+; RV32-NEXT: li a6, 192
+; RV32-NEXT: addi a4, a4, 3
+; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vle32.v v8, (a1)
-; RV32-NEXT: addi a3, a3, 3
-; RV32-NEXT: addi a1, a2, 12
-; RV32-NEXT: vmv.s.x v0, a3
+; RV32-NEXT: addi a1, a3, 12
+; RV32-NEXT: vmv.s.x v16, a5
+; RV32-NEXT: vmv.s.x v0, a4
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v8, 16
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; RV32-NEXT: vmerge.vvm v12, v24, v8, v0
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs4r.v v12, (a3) # vscale x 32-byte Folded Spill
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 1
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs4r.v v12, (a2) # vscale x 32-byte Folded Spill
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: vmerge.vvm v12, v24, v8, v0
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 12
-; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: li a2, 6
+; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
-; RV32-NEXT: vmv.s.x v0, a4
+; RV32-NEXT: vmv.s.x v17, a6
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: vmerge.vvm v12, v24, v8, v0
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 28
-; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: li a2, 22
+; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
-; RV32-NEXT: vmv.s.x v0, a5
-; RV32-NEXT: vslideup.vi v12, v8, 4
-; RV32-NEXT: vslideup.vi v4, v8, 2
+; RV32-NEXT: vslideup.vi v4, v8, 4
+; RV32-NEXT: vslideup.vi v12, v8, 2
+; RV32-NEXT: vmv1r.v v0, v17
; RV32-NEXT: vmerge.vvm v8, v24, v8, v0
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
+; RV32-NEXT: li a2, 18
+; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
-; RV32-NEXT: lui a1, %hi(.LCPI27_0)
-; RV32-NEXT: addi a1, a1, %lo(.LCPI27_0)
-; RV32-NEXT: vmv.s.x v0, a2
-; RV32-NEXT: vslideup.vi v12, v24, 10, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 72
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs4r.v v12, (a2) # vscale x 32-byte Folded Spill
-; RV32-NEXT: vle16.v v8, (a1)
-; RV32-NEXT: vslideup.vi v4, v24, 8, v0.t
; RV32-NEXT: lui a1, %hi(.LCPI27_1)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_1)
-; RV32-NEXT: vle16.v v10, (a1)
+; RV32-NEXT: vmv.s.x v0, a3
+; RV32-NEXT: vslideup.vi v4, v24, 10, v0.t
+; RV32-NEXT: vle16.v v8, (a1)
+; RV32-NEXT: vslideup.vi v12, v24, 8, v0.t
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 48
+; RV32-NEXT: li a2, 66
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32-NEXT: vrgatherei16.vv v24, v16, v8
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
; RV32-NEXT: lui a1, %hi(.LCPI27_3)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_3)
-; RV32-NEXT: vle16.v v2, (a1)
+; RV32-NEXT: vle16.v v10, (a1)
+; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: vs2r.v v10, (a1) # vscale x 16-byte Folded Spill
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 20
+; RV32-NEXT: li a2, 26
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vrgatherei16.vv v16, v24, v10
+; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32-NEXT: vrgatherei16.vv v16, v24, v8
; RV32-NEXT: lui a1, %hi(.LCPI27_2)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_2)
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vle16.v v20, (a1)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 5
+; RV32-NEXT: li a2, 34
+; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: vl2r.v v22, (a1) # vscale x 16-byte Folded Reload
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vrgatherei16.vv v8, v24, v2
+; RV32-NEXT: vrgatherei16.vv v8, v24, v22
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 72
+; RV32-NEXT: li a2, 10
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
-; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetivli zero, 12, e32, m4, tu, ma
-; RV32-NEXT: vmv.v.v v12, v24
+; RV32-NEXT: vmv.v.v v4, v24
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 72
+; RV32-NEXT: li a2, 34
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
-; RV32-NEXT: vmv.v.v v4, v16
+; RV32-NEXT: vs4r.v v4, (a1) # vscale x 32-byte Folded Spill
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 48
+; RV32-NEXT: li a2, 66
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs4r.v v4, (a1) # vscale x 32-byte Folded Spill
+; RV32-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
+; RV32-NEXT: vmv.v.v v12, v16
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 66
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: slli a1, a1, 1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
@@ -725,36 +752,48 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV32-NEXT: vle16.v v20, (a2)
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT: vle16.v v26, (a1)
+; RV32-NEXT: vle16.v v8, (a1)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 26
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
; RV32-NEXT: lui a1, %hi(.LCPI27_7)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_7)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vle16.v v24, (a1)
+; RV32-NEXT: vle16.v v22, (a1)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 40
+; RV32-NEXT: li a2, 42
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vrgatherei16.vv v8, v0, v20
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 12
+; RV32-NEXT: li a2, 6
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 26
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v20, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vrgatherei16.vv v20, v12, v26
+; RV32-NEXT: vrgatherei16.vv v24, v12, v20
; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
-; RV32-NEXT: vmv.v.v v20, v8
+; RV32-NEXT: vmv.v.v v24, v8
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 56
+; RV32-NEXT: li a2, 50
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vrgatherei16.vv v8, v0, v24
+; RV32-NEXT: vrgatherei16.vv v8, v0, v22
; RV32-NEXT: lui a1, %hi(.LCPI27_6)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_6)
; RV32-NEXT: lui a2, %hi(.LCPI27_8)
@@ -764,60 +803,86 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: lui a1, %hi(.LCPI27_9)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_9)
; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; RV32-NEXT: vle16.v v28, (a1)
+; RV32-NEXT: vle16.v v14, (a1)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 42
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs2r.v v14, (a1) # vscale x 16-byte Folded Spill
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vle16.v v30, (a2)
+; RV32-NEXT: vle16.v v13, (a2)
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 50
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs1r.v v13, (a1) # vscale x 8-byte Folded Spill
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 28
+; RV32-NEXT: li a2, 22
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v4, (a1) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vrgatherei16.vv v24, v4, v12
+; RV32-NEXT: vrgatherei16.vv v20, v4, v12
; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
-; RV32-NEXT: vmv.v.v v24, v8
+; RV32-NEXT: vmv.v.v v20, v8
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 6
+; RV32-NEXT: li a2, 58
+; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 42
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl2r.v v28, (a1) # vscale x 16-byte Folded Reload
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vrgatherei16.vv v8, v0, v28
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
+; RV32-NEXT: li a2, 18
+; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v4, (a1) # vscale x 32-byte Folded Reload
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 50
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v3, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vrgatherei16.vv v12, v4, v30
+; RV32-NEXT: vrgatherei16.vv v12, v4, v3
; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
; RV32-NEXT: vmv.v.v v12, v8
; RV32-NEXT: addi a1, a0, 320
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vse32.v v12, (a1)
; RV32-NEXT: addi a1, a0, 256
-; RV32-NEXT: vse32.v v24, (a1)
-; RV32-NEXT: addi a1, a0, 192
; RV32-NEXT: vse32.v v20, (a1)
+; RV32-NEXT: addi a1, a0, 192
+; RV32-NEXT: vse32.v v24, (a1)
; RV32-NEXT: addi a1, a0, 128
; RV32-NEXT: vse32.v v16, (a1)
; RV32-NEXT: addi a1, a0, 64
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 48
+; RV32-NEXT: li a3, 66
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 72
+; RV32-NEXT: li a2, 34
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 76
+; RV32-NEXT: li a1, 74
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -830,87 +895,90 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 68
+; RV64-NEXT: li a3, 62
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: sub sp, sp, a2
-; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc4, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 68 * vlenb
+; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x3e, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 62 * vlenb
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vle64.v v8, (a1)
-; RV64-NEXT: addi a4, a1, 128
+; RV64-NEXT: addi a5, a1, 128
; RV64-NEXT: lui a3, 1
; RV64-NEXT: lui a2, %hi(.LCPI27_0)
; RV64-NEXT: addi a2, a2, %lo(.LCPI27_0)
-; RV64-NEXT: lui a5, 2
-; RV64-NEXT: lui a6, 4
-; RV64-NEXT: vle64.v v16, (a4)
-; RV64-NEXT: addi a4, a3, 65
+; RV64-NEXT: lui a4, 2
+; RV64-NEXT: vle64.v v16, (a5)
+; RV64-NEXT: li a5, 1040
+; RV64-NEXT: vmv.s.x v5, a5
+; RV64-NEXT: addi a5, a3, 65
+; RV64-NEXT: vmv.s.x v0, a5
+; RV64-NEXT: lui a5, 4
+; RV64-NEXT: addi a4, a4, 130
+; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV64-NEXT: csrr a6, vlenb
+; RV64-NEXT: li a7, 22
+; RV64-NEXT: mul a6, a6, a7
+; RV64-NEXT: add a6, sp, a6
+; RV64-NEXT: addi a6, a6, 16
+; RV64-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
; RV64-NEXT: vmv.s.x v0, a4
; RV64-NEXT: lui a4, 8
-; RV64-NEXT: addi a5, a5, 130
-; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
-; RV64-NEXT: csrr a7, vlenb
-; RV64-NEXT: li t0, 60
-; RV64-NEXT: mul a7, a7, t0
-; RV64-NEXT: add a7, sp, a7
-; RV64-NEXT: addi a7, a7, 16
-; RV64-NEXT: vs8r.v v24, (a7) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv.s.x v0, a5
-; RV64-NEXT: li a5, 1040
-; RV64-NEXT: addi a6, a6, 260
+; RV64-NEXT: addi a5, a5, 260
; RV64-NEXT: addi a4, a4, 520
; RV64-NEXT: addi a3, a3, -2016
; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
-; RV64-NEXT: csrr a7, vlenb
-; RV64-NEXT: li t0, 12
-; RV64-NEXT: mul a7, a7, t0
-; RV64-NEXT: add a7, sp, a7
-; RV64-NEXT: addi a7, a7, 16
-; RV64-NEXT: vs8r.v v24, (a7) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv.s.x v0, a6
-; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
; RV64-NEXT: csrr a6, vlenb
-; RV64-NEXT: slli a6, a6, 2
+; RV64-NEXT: li a7, 14
+; RV64-NEXT: mul a6, a6, a7
; RV64-NEXT: add a6, sp, a6
; RV64-NEXT: addi a6, a6, 16
; RV64-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv.s.x v0, a4
-; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
-; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: li a6, 36
-; RV64-NEXT: mul a4, a4, a6
-; RV64-NEXT: add a4, sp, a4
-; RV64-NEXT: addi a4, a4, 16
-; RV64-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; RV64-NEXT: vmv.s.x v0, a5
+; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV64-NEXT: csrr a5, vlenb
+; RV64-NEXT: li a6, 6
+; RV64-NEXT: mul a5, a5, a6
+; RV64-NEXT: add a5, sp, a5
+; RV64-NEXT: addi a5, a5, 16
+; RV64-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv.s.x v0, a4
; RV64-NEXT: vle16.v v6, (a2)
; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a4, 44
+; RV64-NEXT: li a4, 54
; RV64-NEXT: mul a2, a2, a4
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv.s.x v0, a3
+; RV64-NEXT: vmv.s.x v4, a3
+; RV64-NEXT: vmv1r.v v0, v5
+; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV64-NEXT: csrr a2, vlenb
+; RV64-NEXT: li a3, 38
+; RV64-NEXT: mul a2, a2, a3
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: addi a2, a2, 16
+; RV64-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv1r.v v0, v4
; RV64-NEXT: vmerge.vvm v8, v16, v8, v0
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 52
+; RV64-NEXT: li a3, 46
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 60
+; RV64-NEXT: li a3, 22
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vrgatherei16.vv v16, v8, v6
+; RV64-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vrgatherei16.vv v8, v16, v6
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 28
+; RV64-NEXT: li a3, 30
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; RV64-NEXT: lui a2, %hi(.LCPI27_1)
; RV64-NEXT: addi a2, a2, %lo(.LCPI27_1)
; RV64-NEXT: lui a3, %hi(.LCPI27_2)
@@ -920,26 +988,27 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: addi a1, a1, 256
; RV64-NEXT: vle64.v v16, (a1)
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 12
+; RV64-NEXT: li a2, 14
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vrgatherei16.vv v24, v0, v8
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 20
+; RV64-NEXT: li a2, 22
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 2
+; RV64-NEXT: li a2, 6
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vrgatherei16.vv v24, v0, v10
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 12
+; RV64-NEXT: li a2, 14
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
@@ -949,198 +1018,194 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: vmv4r.v v8, v16
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vslideup.vi v8, v16, 5, v0.t
+; RV64-NEXT: vmv.v.v v24, v8
; RV64-NEXT: vslidedown.vi v4, v16, 1
; RV64-NEXT: vslideup.vi v4, v16, 4, v0.t
; RV64-NEXT: li a1, 128
; RV64-NEXT: vmv.s.x v0, a1
-; RV64-NEXT: vslideup.vi v12, v16, 2
+; RV64-NEXT: vslideup.vi v28, v16, 2
; RV64-NEXT: vsetivli zero, 8, e64, m8, ta, ma
-; RV64-NEXT: vslidedown.vi v24, v16, 8
+; RV64-NEXT: vslidedown.vi v8, v16, 8
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vslideup.vi v12, v24, 5, v0.t
-; RV64-NEXT: vslideup.vi v20, v16, 1
-; RV64-NEXT: vslideup.vi v20, v24, 4, v0.t
-; RV64-NEXT: vmv.v.v v28, v20
-; RV64-NEXT: vrgather.vi v8, v24, 4, v0.t
-; RV64-NEXT: vrgather.vi v4, v24, 5, v0.t
+; RV64-NEXT: vslideup.vi v28, v8, 5, v0.t
+; RV64-NEXT: vslideup.vi v12, v16, 1
+; RV64-NEXT: vslideup.vi v12, v8, 4, v0.t
+; RV64-NEXT: vrgather.vi v24, v8, 4, v0.t
+; RV64-NEXT: vrgather.vi v4, v8, 5, v0.t
+; RV64-NEXT: vmv.v.v v20, v4
+; RV64-NEXT: vslideup.vi v4, v8, 6
+; RV64-NEXT: vslideup.vi v4, v8, 1, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 60
+; RV64-NEXT: li a2, 6
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v4, (a1) # vscale x 32-byte Folded Spill
-; RV64-NEXT: vslideup.vi v20, v24, 6
-; RV64-NEXT: vslideup.vi v20, v24, 1, v0.t
+; RV64-NEXT: li a1, 64
+; RV64-NEXT: vmv.s.x v0, a1
+; RV64-NEXT: vmv4r.v v4, v8
+; RV64-NEXT: vslideup.vi v4, v8, 5, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 2
+; RV64-NEXT: slli a1, a1, 1
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v20, (a1) # vscale x 32-byte Folded Spill
-; RV64-NEXT: li a1, 64
-; RV64-NEXT: vmv.s.x v0, a1
-; RV64-NEXT: vmv4r.v v20, v24
-; RV64-NEXT: vslideup.vi v20, v24, 5, v0.t
+; RV64-NEXT: vs4r.v v4, (a1) # vscale x 32-byte Folded Spill
; RV64-NEXT: lui a1, %hi(.LCPI27_3)
; RV64-NEXT: addi a1, a1, %lo(.LCPI27_3)
; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; RV64-NEXT: vle16.v v24, (a1)
+; RV64-NEXT: vle16.v v8, (a1)
+; RV64-NEXT: addi a1, sp, 16
+; RV64-NEXT: vs2r.v v8, (a1) # vscale x 16-byte Folded Spill
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 28
+; RV64-NEXT: li a2, 30
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
-; RV64-NEXT: vmv.v.v v12, v0
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 28
-; RV64-NEXT: mul a1, a1, a2
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
+; RV64-NEXT: vmv.v.v v28, v0
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 20
+; RV64-NEXT: li a2, 30
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmv.v.v v28, v0
-; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vs4r.v v28, (a1) # vscale x 32-byte Folded Spill
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 12
+; RV64-NEXT: li a2, 22
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
-; RV64-NEXT: vmv.v.v v8, v0
+; RV64-NEXT: vmv.v.v v12, v0
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 20
+; RV64-NEXT: li a2, 22
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
+; RV64-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 36
+; RV64-NEXT: li a2, 14
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vrgatherei16.vv v0, v8, v24
+; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
+; RV64-NEXT: vmv.v.v v24, v8
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 60
+; RV64-NEXT: li a2, 14
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
-; RV64-NEXT: vmv.v.v v8, v0
+; RV64-NEXT: vs4r.v v24, (a1) # vscale x 32-byte Folded Spill
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 60
+; RV64-NEXT: li a2, 54
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
+; RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: addi a1, sp, 16
+; RV64-NEXT: vl2r.v v6, (a1) # vscale x 16-byte Folded Reload
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: vrgatherei16.vv v8, v24, v6
+; RV64-NEXT: vmv4r.v v4, v20
+; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
+; RV64-NEXT: vmv.v.v v4, v8
; RV64-NEXT: li a1, 192
; RV64-NEXT: lui a2, %hi(.LCPI27_4)
; RV64-NEXT: addi a2, a2, %lo(.LCPI27_4)
; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; RV64-NEXT: vle16.v v8, (a2)
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 12
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs2r.v v8, (a2) # vscale x 16-byte Folded Spill
-; RV64-NEXT: vmv.s.x v0, a1
+; RV64-NEXT: vle16.v v2, (a2)
+; RV64-NEXT: vmv.s.x v8, a1
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 36
+; RV64-NEXT: li a2, 54
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
+; RV64-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vrgather.vi v8, v16, 2
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 2
+; RV64-NEXT: li a2, 6
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v24, v8, v12, v0
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 44
+; RV64-NEXT: li a2, 54
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vmerge.vvm v20, v8, v12, v0
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 12
+; RV64-NEXT: li a2, 38
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl2r.v v28, (a1) # vscale x 16-byte Folded Reload
+; RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vrgatherei16.vv v8, v0, v28
+; RV64-NEXT: vrgatherei16.vv v8, v24, v2
; RV64-NEXT: lui a1, %hi(.LCPI27_5)
; RV64-NEXT: addi a1, a1, %lo(.LCPI27_5)
-; RV64-NEXT: vle16.v v28, (a1)
+; RV64-NEXT: vle16.v v2, (a1)
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
-; RV64-NEXT: vmv.v.v v24, v8
+; RV64-NEXT: vmv.v.v v20, v8
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vrgather.vi v8, v16, 3
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 36
+; RV64-NEXT: slli a1, a1, 1
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 54
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v16, v8, v20, v0
+; RV64-NEXT: vmerge.vvm v16, v8, v12, v0
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 52
+; RV64-NEXT: li a2, 46
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vrgatherei16.vv v8, v0, v28
+; RV64-NEXT: vrgatherei16.vv v8, v24, v2
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
; RV64-NEXT: vmv.v.v v16, v8
; RV64-NEXT: addi a1, a0, 320
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vse64.v v16, (a1)
; RV64-NEXT: addi a1, a0, 256
-; RV64-NEXT: vse64.v v24, (a1)
+; RV64-NEXT: vse64.v v20, (a1)
; RV64-NEXT: addi a1, a0, 192
+; RV64-NEXT: vse64.v v4, (a1)
+; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 60
+; RV64-NEXT: li a3, 14
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
; RV64-NEXT: vse64.v v8, (a1)
-; RV64-NEXT: addi a1, a0, 128
+; RV64-NEXT: addi a1, a0, 64
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 20
+; RV64-NEXT: li a3, 22
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
; RV64-NEXT: vse64.v v8, (a1)
-; RV64-NEXT: addi a1, a0, 64
-; RV64-NEXT: addi a2, sp, 16
-; RV64-NEXT: vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
-; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 28
+; RV64-NEXT: li a2, 30
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 68
+; RV64-NEXT: li a1, 62
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
index 6887f11fe38c7..58826b4f67bf1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
@@ -112,9 +112,9 @@ define float @vpreduce_fadd_v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32
; CHECK-LABEL: vpreduce_fadd_v64f32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 32
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v25, v0, 4
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB8_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 32
@@ -140,9 +140,9 @@ define float @vpreduce_ord_fadd_v64f32(float %s, <64 x float> %v, <64 x i1> %m,
; CHECK-LABEL: vpreduce_ord_fadd_v64f32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 32
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v25, v0, 4
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB9_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
index 0401fe04556a9..52be38834661d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
@@ -1891,53 +1891,58 @@ define float @vreduce_fminimum_v128f32(ptr %x) {
; CHECK-NEXT: addi a1, a0, 384
; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: addi a1, a0, 256
-; CHECK-NEXT: vle32.v v24, (a1)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v24, v16, v16
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v7, v8, v8
+; CHECK-NEXT: vle32.v v24, (a1)
+; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v0, v24, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vmfeq.vv v7, v24, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v24, v8, v24, v0
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmerge.vvm v24, v24, v8, v0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
@@ -2302,22 +2307,26 @@ define double @vreduce_fminimum_v64f64(ptr %x) {
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmfeq.vv v0, v16, v16
+; RV32-NEXT: vmfeq.vv v24, v16, v16
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vmfeq.vv v7, v8, v8
; RV32-NEXT: vle64.v v24, (a1)
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmerge.vvm v16, v16, v8, v0
; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vmerge.vvm v16, v16, v8, v0
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmfeq.vv v0, v8, v8
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
@@ -2328,20 +2337,21 @@ define double @vreduce_fminimum_v64f64(ptr %x) {
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmfeq.vv v0, v16, v16
+; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmfeq.vv v0, v8, v8
+; RV32-NEXT: vmfeq.vv v7, v24, v24
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmerge.vvm v16, v16, v24, v0
-; RV32-NEXT: vmfeq.vv v0, v24, v24
+; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vmerge.vvm v24, v24, v8, v0
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -2407,22 +2417,26 @@ define double @vreduce_fminimum_v64f64(ptr %x) {
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmfeq.vv v0, v16, v16
+; RV64-NEXT: vmfeq.vv v24, v16, v16
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
+; RV64-NEXT: vmfeq.vv v7, v8, v8
; RV64-NEXT: vle64.v v24, (a1)
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v16, v16, v8, v0
; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vmerge.vvm v16, v16, v8, v0
; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmfeq.vv v0, v8, v8
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vmerge.vvm v8, v8, v16, v0
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
@@ -2433,20 +2447,21 @@ define double @vreduce_fminimum_v64f64(ptr %x) {
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmfeq.vv v0, v16, v16
+; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmfeq.vv v0, v8, v8
+; RV64-NEXT: vmfeq.vv v7, v24, v24
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v16, v16, v24, v0
-; RV64-NEXT: vmfeq.vv v0, v24, v24
+; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmerge.vvm v16, v8, v24, v0
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vmerge.vvm v24, v24, v8, v0
; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -2791,53 +2806,58 @@ define float @vreduce_fmaximum_v128f32(ptr %x) {
; CHECK-NEXT: addi a1, a0, 384
; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: addi a1, a0, 256
-; CHECK-NEXT: vle32.v v24, (a1)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v24, v16, v16
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v7, v8, v8
+; CHECK-NEXT: vle32.v v24, (a1)
+; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v0, v24, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vmfeq.vv v7, v24, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v24, v8, v24, v0
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmerge.vvm v24, v24, v8, v0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
@@ -3202,22 +3222,26 @@ define double @vreduce_fmaximum_v64f64(ptr %x) {
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmfeq.vv v0, v16, v16
+; RV32-NEXT: vmfeq.vv v24, v16, v16
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vmfeq.vv v7, v8, v8
; RV32-NEXT: vle64.v v24, (a1)
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmerge.vvm v16, v16, v8, v0
; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vmerge.vvm v16, v16, v8, v0
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmfeq.vv v0, v8, v8
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
@@ -3228,20 +3252,21 @@ define double @vreduce_fmaximum_v64f64(ptr %x) {
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmfeq.vv v0, v16, v16
+; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmfeq.vv v0, v8, v8
+; RV32-NEXT: vmfeq.vv v7, v24, v24
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmerge.vvm v16, v16, v24, v0
-; RV32-NEXT: vmfeq.vv v0, v24, v24
+; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vmerge.vvm v24, v24, v8, v0
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -3307,22 +3332,26 @@ define double @vreduce_fmaximum_v64f64(ptr %x) {
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmfeq.vv v0, v16, v16
+; RV64-NEXT: vmfeq.vv v24, v16, v16
+; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
+; RV64-NEXT: vmfeq.vv v7, v8, v8
; RV64-NEXT: vle64.v v24, (a1)
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v16, v16, v8, v0
; RV64-NEXT: addi a0, sp, 16
+; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vmerge.vvm v16, v16, v8, v0
; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmfeq.vv v0, v8, v8
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vmerge.vvm v8, v8, v16, v0
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
@@ -3333,20 +3362,21 @@ define double @vreduce_fmaximum_v64f64(ptr %x) {
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmfeq.vv v0, v16, v16
+; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmfeq.vv v0, v8, v8
+; RV64-NEXT: vmfeq.vv v7, v24, v24
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v16, v16, v24, v0
-; RV64-NEXT: vmfeq.vv v0, v24, v24
+; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmerge.vvm v16, v8, v24, v0
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vmerge.vvm v24, v24, v8, v0
; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
index 564c4fb40a70b..4b5d581e7b668 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
@@ -645,18 +645,18 @@ define signext i32 @vpreduce_xor_v64i32(i32 signext %s, <64 x i32> %v, <64 x i1>
; CHECK-LABEL: vpreduce_xor_v64i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32
-; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v25, v0, 4
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bltu a1, a3, .LBB49_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: .LBB49_2:
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vmv.s.x v24, a0
+; CHECK-NEXT: addi a0, a1, -32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vredxor.vs v24, v8, v24, v0.t
-; CHECK-NEXT: addi a0, a1, -32
; CHECK-NEXT: sltu a1, a1, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
index 3e88d19fb95e7..e527169a07d96 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
@@ -213,16 +213,16 @@ define zeroext i1 @vpreduce_and_v256i1(i1 zeroext %s, <256 x i1> %v, <256 x i1>
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vmnot.m v9, v11
; CHECK-NEXT: vcpop.m a2, v9, v0.t
-; CHECK-NEXT: addi a3, a1, -128
-; CHECK-NEXT: sltu a1, a1, a3
+; CHECK-NEXT: seqz a2, a2
+; CHECK-NEXT: and a0, a2, a0
+; CHECK-NEXT: addi a2, a1, -128
+; CHECK-NEXT: sltu a1, a1, a2
; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a1, a1, a3
+; CHECK-NEXT: and a1, a1, a2
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmnot.m v8, v8
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vcpop.m a1, v8, v0.t
-; CHECK-NEXT: seqz a2, a2
-; CHECK-NEXT: and a0, a2, a0
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
index 9af900ce005e5..dcb2fde553d58 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
@@ -31,12 +31,12 @@ define <2 x half> @vp_round_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl)
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -115,12 +115,12 @@ define <4 x half> @vp_round_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl)
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
index 656a62a693da8..f398cb306559b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
@@ -31,12 +31,12 @@ define <2 x half> @vp_roundeven_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -115,12 +115,12 @@ define <4 x half> @vp_roundeven_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
index 0a06067a65782..bfbf6c8371a4e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
@@ -31,12 +31,12 @@ define <2 x half> @vp_roundtozero_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -115,12 +115,12 @@ define <4 x half> @vp_roundtozero_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
index f76c7fcb628b5..f9b97da6d02aa 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
@@ -596,15 +596,15 @@ define <256 x i1> @icmp_eq_vv_v256i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1>
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: li a1, 128
; CHECK-NEXT: addi a4, a0, 128
-; CHECK-NEXT: addi a5, a3, -128
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vle8.v v24, (a4)
-; CHECK-NEXT: sltu a4, a3, a5
; CHECK-NEXT: vlm.v v0, (a2)
+; CHECK-NEXT: addi a2, a3, -128
+; CHECK-NEXT: vle8.v v24, (a4)
+; CHECK-NEXT: sltu a4, a3, a2
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a4, a4, a5
-; CHECK-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-NEXT: and a2, a4, a2
+; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vv v7, v16, v24, v0.t
; CHECK-NEXT: bltu a3, a1, .LBB51_2
; CHECK-NEXT: # %bb.1:
@@ -634,12 +634,12 @@ define <256 x i1> @icmp_eq_vx_v256i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 z
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
-; CHECK-NEXT: addi a4, a2, -128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: sltu a1, a2, a4
-; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: addi a1, a2, -128
+; CHECK-NEXT: sltu a4, a2, a1
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a1, a4, a1
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB52_2
@@ -664,12 +664,12 @@ define <256 x i1> @icmp_eq_vx_swap_v256i8(<256 x i8> %va, i8 %b, <256 x i1> %m,
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
-; CHECK-NEXT: addi a4, a2, -128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: sltu a1, a2, a4
-; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: addi a1, a2, -128
+; CHECK-NEXT: sltu a4, a2, a1
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a1, a4, a1
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB53_2
@@ -1289,9 +1289,9 @@ define <64 x i1> @icmp_eq_vx_v64i32(<64 x i32> %va, i32 %b, <64 x i1> %m, i32 ze
; CHECK-LABEL: icmp_eq_vx_v64i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32
-; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v25, v0, 4
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bltu a1, a3, .LBB100_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 32
@@ -1319,9 +1319,9 @@ define <64 x i1> @icmp_eq_vx_swap_v64i32(<64 x i32> %va, i32 %b, <64 x i1> %m, i
; CHECK-LABEL: icmp_eq_vx_swap_v64i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32
-; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v25, v0, 4
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bltu a1, a3, .LBB101_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
index 6dc54bce9aaa0..b03415e1a8550 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
@@ -138,9 +138,9 @@ define <32 x i64> @vsext_v32i64_v32i32(<32 x i32> %va, <32 x i1> %m, i32 zeroext
; CHECK-LABEL: vsext_v32i64_v32i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB12_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
index 33583a4b5beca..03bde17b1230a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
@@ -145,11 +145,12 @@ define void @deinterleave6_0_i8(ptr %in, ptr %out) {
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.v.i v0, 2
+; CHECK-NEXT: vmv.v.i v10, 4
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 8
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 5, v0.t
-; CHECK-NEXT: vmv.v.i v0, 4
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vrgather.vi v8, v9, 4, v0.t
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -189,11 +190,12 @@ define void @deinterleave7_0_i8(ptr %in, ptr %out) {
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.v.i v0, 2
+; CHECK-NEXT: vmv.v.i v10, 4
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 8
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 6, v0.t
-; CHECK-NEXT: vmv.v.i v0, 4
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vrgather.vi v8, v9, 6, v0.t
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
index cb0cc43389b6b..1a018ecb190e1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
@@ -1612,21 +1612,22 @@ define <16 x i64> @unzip2a_dual_v16i64_exact(<16 x i64> %a, <16 x i64> %b) vscal
; V-NEXT: vsetivli zero, 4, e64, m1, ta, mu
; V-NEXT: vslideup.vi v16, v15, 2
; V-NEXT: vmv.v.i v0, 8
+; V-NEXT: vmv.v.i v18, 2
; V-NEXT: vslideup.vi v17, v11, 2
; V-NEXT: vslideup.vi v16, v15, 1, v0.t
-; V-NEXT: vmv.v.v v15, v0
-; V-NEXT: vmv.v.i v0, 2
+; V-NEXT: vmv.v.v v19, v0
+; V-NEXT: vmv.v.v v0, v18
; V-NEXT: vslidedown.vi v14, v14, 1, v0.t
-; V-NEXT: vmv.v.v v18, v0
-; V-NEXT: vmv.v.v v0, v15
+; V-NEXT: vmv.v.v v15, v18
+; V-NEXT: vmv.v.v v0, v19
; V-NEXT: vslideup.vi v17, v11, 1, v0.t
-; V-NEXT: vmv.v.v v11, v15
+; V-NEXT: vmv.v.v v20, v19
; V-NEXT: vmv.v.v v0, v18
; V-NEXT: vslidedown.vi v10, v10, 1, v0.t
; V-NEXT: vmv.v.v v19, v18
; V-NEXT: vslideup.vi v15, v13, 2
; V-NEXT: vslideup.vi v18, v9, 2
-; V-NEXT: vmv.v.v v0, v11
+; V-NEXT: vmv.v.v v0, v20
; V-NEXT: vslideup.vi v15, v13, 1, v0.t
; V-NEXT: vslideup.vi v18, v9, 1, v0.t
; V-NEXT: vmv.v.i v0, 12
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
index feec2470461de..afa8f2fda2ed4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
@@ -363,9 +363,9 @@ define <32 x double> @vsitofp_v32f64_v32i64(<32 x i64> %va, <32 x i1> %m, i32 ze
; CHECK-LABEL: vsitofp_v32f64_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB25_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
index 95f110f0e1a2c..f44f90085eabd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
@@ -493,16 +493,17 @@ define <32 x double> @strided_vpload_v32f64(ptr %ptr, i32 signext %stride, <32 x
; CHECK-NEXT: .LBB45_2:
; CHECK-NEXT: mul a4, a3, a1
; CHECK-NEXT: addi a5, a2, -16
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v8, v0, 2
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: add a4, a0, a4
; CHECK-NEXT: sltu a2, a2, a5
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a5
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: vslidedown.vi v0, v0, 2
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vlse64.v v16, (a4), a1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t
; CHECK-NEXT: ret
@@ -538,6 +539,8 @@ define <32 x double> @strided_vpload_v32f64_allones_mask(ptr %ptr, i32 signext %
define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask, i32 zeroext %evl) {
; CHECK-RV32-LABEL: strided_load_v33f64:
; CHECK-RV32: # %bb.0:
+; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-RV32-NEXT: vmv1r.v v16, v0
; CHECK-RV32-NEXT: li a5, 32
; CHECK-RV32-NEXT: mv a3, a4
; CHECK-RV32-NEXT: bltu a4, a5, .LBB47_2
@@ -556,8 +559,7 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
; CHECK-RV32-NEXT: li a7, 16
; CHECK-RV32-NEXT: .LBB47_4:
; CHECK-RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-RV32-NEXT: vmv1r.v v16, v0
-; CHECK-RV32-NEXT: vslidedown.vi v0, v0, 4
+; CHECK-RV32-NEXT: vslidedown.vi v0, v16, 4
; CHECK-RV32-NEXT: vsetvli zero, a7, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v8, (a6), a2, v0.t
; CHECK-RV32-NEXT: addi a6, a3, -16
@@ -570,11 +572,12 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
; CHECK-RV32-NEXT: .LBB47_6:
; CHECK-RV32-NEXT: mul a5, a4, a2
; CHECK-RV32-NEXT: vmv1r.v v0, v16
+; CHECK-RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vi v9, v16, 2
; CHECK-RV32-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v16, (a1), a2, v0.t
-; CHECK-RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v0, v0, 2
; CHECK-RV32-NEXT: add a1, a1, a5
+; CHECK-RV32-NEXT: vmv1r.v v0, v9
; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v24, (a1), a2, v0.t
; CHECK-RV32-NEXT: addi a1, a0, 128
@@ -588,6 +591,8 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
;
; CHECK-RV64-LABEL: strided_load_v33f64:
; CHECK-RV64: # %bb.0:
+; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-RV64-NEXT: vmv1r.v v16, v0
; CHECK-RV64-NEXT: li a5, 32
; CHECK-RV64-NEXT: mv a4, a3
; CHECK-RV64-NEXT: bltu a3, a5, .LBB47_2
@@ -606,8 +611,7 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
; CHECK-RV64-NEXT: li a7, 16
; CHECK-RV64-NEXT: .LBB47_4:
; CHECK-RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-RV64-NEXT: vmv1r.v v16, v0
-; CHECK-RV64-NEXT: vslidedown.vi v0, v0, 4
+; CHECK-RV64-NEXT: vslidedown.vi v0, v16, 4
; CHECK-RV64-NEXT: vsetvli zero, a7, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v8, (a6), a2, v0.t
; CHECK-RV64-NEXT: addi a6, a4, -16
@@ -620,11 +624,12 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
; CHECK-RV64-NEXT: .LBB47_6:
; CHECK-RV64-NEXT: mul a5, a3, a2
; CHECK-RV64-NEXT: vmv1r.v v0, v16
+; CHECK-RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vi v9, v16, 2
; CHECK-RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v16, (a1), a2, v0.t
-; CHECK-RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v0, v0, 2
; CHECK-RV64-NEXT: add a1, a1, a5
+; CHECK-RV64-NEXT: vmv1r.v v0, v9
; CHECK-RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v24, (a1), a2, v0.t
; CHECK-RV64-NEXT: addi a1, a0, 128
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
index 32ace86a0d1fc..20ff862320466 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
@@ -48,8 +48,8 @@ define <128 x i7> @vtrunc_v128i7_v128i16(<128 x i16> %a, <128 x i1> %m, i32 zero
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: li a1, 64
-; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: vslidedown.vi v12, v0, 8
+; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: bltu a0, a1, .LBB4_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 64
@@ -207,21 +207,24 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: sw s0, 28(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset s0, -4
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 73
+; RV32-NEXT: li a3, 74
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: sub sp, sp, a2
-; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0xc9, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 73 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0xca, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 74 * vlenb
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 5
+; RV32-NEXT: slli a3, a2, 5
+; RV32-NEXT: add a2, a3, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 40
+; RV32-NEXT: li a3, 41
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; RV32-NEXT: vslidedown.vi v8, v0, 8
; RV32-NEXT: addi a3, a7, -64
; RV32-NEXT: li a2, 16
; RV32-NEXT: sltu a4, a7, a3
@@ -231,177 +234,186 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: sltu a5, a4, a3
; RV32-NEXT: addi a5, a5, -1
; RV32-NEXT: and a3, a5, a3
-; RV32-NEXT: addi a6, a3, -16
+; RV32-NEXT: addi t0, a3, -16
; RV32-NEXT: mv a5, a3
-; RV32-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; RV32-NEXT: vslidedown.vi v8, v0, 8
-; RV32-NEXT: csrr t0, vlenb
-; RV32-NEXT: li t1, 48
-; RV32-NEXT: mul t0, t0, t1
-; RV32-NEXT: add t0, sp, t0
-; RV32-NEXT: addi t0, t0, 16
-; RV32-NEXT: vs1r.v v0, (t0) # vscale x 8-byte Folded Spill
+; RV32-NEXT: csrr a6, vlenb
+; RV32-NEXT: li t1, 49
+; RV32-NEXT: mul a6, a6, t1
+; RV32-NEXT: add a6, sp, a6
+; RV32-NEXT: addi a6, a6, 16
+; RV32-NEXT: vs1r.v v0, (a6) # vscale x 8-byte Folded Spill
; RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; RV32-NEXT: vslidedown.vi v9, v0, 4
-; RV32-NEXT: vmv1r.v v13, v8
-; RV32-NEXT: vslidedown.vi v10, v8, 4
+; RV32-NEXT: vmv1r.v v28, v8
+; RV32-NEXT: vslidedown.vi v8, v8, 4
; RV32-NEXT: bltu a3, a2, .LBB16_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a5, 16
; RV32-NEXT: .LBB16_2:
; RV32-NEXT: li t2, 64
-; RV32-NEXT: sltu t1, a3, a6
-; RV32-NEXT: mv t0, a7
+; RV32-NEXT: sltu t1, a3, t0
+; RV32-NEXT: mv a6, a7
; RV32-NEXT: bltu a7, t2, .LBB16_4
; RV32-NEXT: # %bb.3:
-; RV32-NEXT: li t0, 64
+; RV32-NEXT: li a6, 64
; RV32-NEXT: .LBB16_4:
-; RV32-NEXT: addi t3, a1, 128
-; RV32-NEXT: vmv1r.v v12, v9
+; RV32-NEXT: addi t2, a1, 128
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li t3, 24
+; RV32-NEXT: mul a3, a3, t3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs1r.v v9, (a3) # vscale x 8-byte Folded Spill
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v14, v9, 2
+; RV32-NEXT: vslidedown.vi v31, v9, 2
; RV32-NEXT: addi s0, a1, 512
; RV32-NEXT: addi t6, a1, 640
+; RV32-NEXT: vmv1r.v v30, v8
+; RV32-NEXT: vslidedown.vi v0, v8, 2
; RV32-NEXT: addi t1, t1, -1
-; RV32-NEXT: addi t2, a1, 384
+; RV32-NEXT: addi t3, a1, 384
; RV32-NEXT: li a3, 32
-; RV32-NEXT: addi t4, t0, -32
-; RV32-NEXT: sltu t0, t0, t4
-; RV32-NEXT: addi t0, t0, -1
-; RV32-NEXT: and t0, t0, t4
-; RV32-NEXT: addi t4, t0, -16
-; RV32-NEXT: sltu t5, t0, t4
+; RV32-NEXT: addi t4, a6, -32
+; RV32-NEXT: sltu a6, a6, t4
+; RV32-NEXT: addi a6, a6, -1
+; RV32-NEXT: and a6, a6, t4
+; RV32-NEXT: addi t4, a6, -16
+; RV32-NEXT: sltu t5, a6, t4
; RV32-NEXT: addi t5, t5, -1
-; RV32-NEXT: vslidedown.vi v0, v10, 2
-; RV32-NEXT: vslidedown.vi v15, v13, 2
-; RV32-NEXT: bltu t0, a2, .LBB16_6
+; RV32-NEXT: vslidedown.vi v29, v28, 2
+; RV32-NEXT: bltu a6, a2, .LBB16_6
; RV32-NEXT: # %bb.5:
-; RV32-NEXT: li t0, 16
+; RV32-NEXT: li a6, 16
; RV32-NEXT: .LBB16_6:
-; RV32-NEXT: vmv1r.v v7, v10
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vle64.v v16, (s0)
+; RV32-NEXT: vle64.v v8, (s0)
; RV32-NEXT: csrr s0, vlenb
; RV32-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
-; RV32-NEXT: li a0, 57
+; RV32-NEXT: li a0, 58
; RV32-NEXT: mul s0, s0, a0
; RV32-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
; RV32-NEXT: add s0, sp, s0
; RV32-NEXT: addi s0, s0, 16
-; RV32-NEXT: vs8r.v v16, (s0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vle64.v v24, (t6)
-; RV32-NEXT: vle64.v v16, (t3)
-; RV32-NEXT: csrr t3, vlenb
-; RV32-NEXT: slli t3, t3, 4
-; RV32-NEXT: add t3, sp, t3
-; RV32-NEXT: addi t3, t3, 16
-; RV32-NEXT: vs8r.v v16, (t3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vle64.v v16, (a1)
-; RV32-NEXT: csrr t3, vlenb
-; RV32-NEXT: slli t3, t3, 3
-; RV32-NEXT: add t3, sp, t3
-; RV32-NEXT: addi t3, t3, 16
-; RV32-NEXT: vs8r.v v16, (t3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vle64.v v16, (t2)
+; RV32-NEXT: vs8r.v v8, (s0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vle64.v v16, (t6)
+; RV32-NEXT: vle64.v v8, (t2)
; RV32-NEXT: csrr t2, vlenb
-; RV32-NEXT: li t3, 49
-; RV32-NEXT: mul t2, t2, t3
+; RV32-NEXT: slli t2, t2, 3
; RV32-NEXT: add t2, sp, t2
; RV32-NEXT: addi t2, t2, 16
-; RV32-NEXT: vs8r.v v16, (t2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: and t2, t1, a6
+; RV32-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vle64.v v8, (a1)
+; RV32-NEXT: csrr t2, vlenb
+; RV32-NEXT: li t6, 50
+; RV32-NEXT: mul t2, t2, t6
+; RV32-NEXT: add t2, sp, t2
+; RV32-NEXT: addi t2, t2, 16
+; RV32-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vle64.v v8, (t3)
+; RV32-NEXT: csrr t2, vlenb
+; RV32-NEXT: slli t2, t2, 4
+; RV32-NEXT: add t2, sp, t2
+; RV32-NEXT: addi t2, t2, 16
+; RV32-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: and t2, t1, t0
; RV32-NEXT: and t1, t5, t4
; RV32-NEXT: addi a1, a1, 256
-; RV32-NEXT: mv a6, a4
+; RV32-NEXT: mv t0, a4
; RV32-NEXT: bltu a4, a3, .LBB16_8
; RV32-NEXT: # %bb.7:
-; RV32-NEXT: li a6, 32
+; RV32-NEXT: li t0, 32
; RV32-NEXT: .LBB16_8:
; RV32-NEXT: vsetvli zero, t2, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v8, v24, 0, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
+; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; RV32-NEXT: addi t2, sp, 16
+; RV32-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v30
; RV32-NEXT: csrr t2, vlenb
-; RV32-NEXT: li t3, 57
+; RV32-NEXT: li t3, 58
; RV32-NEXT: mul t2, t2, t3
; RV32-NEXT: add t2, sp, t2
; RV32-NEXT: addi t2, t2, 16
; RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a5, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v24, v16, 0, v0.t
+; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli t2, a5, 6
-; RV32-NEXT: add a5, t2, a5
+; RV32-NEXT: li t2, 66
+; RV32-NEXT: mul a5, a5, t2
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v14
+; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v31
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 4
+; RV32-NEXT: slli a5, a5, 3
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, t1, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v24, v16, 0, v0.t
+; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li t1, 24
+; RV32-NEXT: li t1, 25
; RV32-NEXT: mul a5, a5, t1
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 3
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, t0, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v16, v24, 0, v0.t
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li t0, 57
-; RV32-NEXT: mul a5, a5, t0
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: addi a5, a6, -16
-; RV32-NEXT: sltu a6, a6, a5
-; RV32-NEXT: addi a6, a6, -1
+; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; RV32-NEXT: addi a5, t0, -16
+; RV32-NEXT: sltu t0, t0, a5
+; RV32-NEXT: addi t0, t0, -1
+; RV32-NEXT: and a5, t0, a5
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vle64.v v16, (a1)
+; RV32-NEXT: vle64.v v8, (a1)
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: and a1, a6, a5
-; RV32-NEXT: vmv1r.v v0, v15
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 49
-; RV32-NEXT: mul a5, a5, a6
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v24, v16, 0, v0.t
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li t0, 50
+; RV32-NEXT: mul a1, a1, t0
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a5, 48
-; RV32-NEXT: mul a1, a1, a5
+; RV32-NEXT: li t0, 24
+; RV32-NEXT: mul a1, a1, t0
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl1r.v v12, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a6, e32, m4, ta, ma
+; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a6, 58
+; RV32-NEXT: mul a1, a1, a6
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a6, 49
+; RV32-NEXT: mul a1, a1, a6
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl1r.v v8, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v12, v12, 2
+; RV32-NEXT: vslidedown.vi v8, v8, 2
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a6, 24
+; RV32-NEXT: mul a1, a1, a6
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v29
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs1r.v v12, (a1) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a5, e32, m4, ta, ma
+; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
; RV32-NEXT: bltu a4, a2, .LBB16_10
; RV32-NEXT: # %bb.9:
; RV32-NEXT: li a4, 16
; RV32-NEXT: .LBB16_10:
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmv1r.v v0, v28
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
@@ -410,7 +422,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: vsetvli zero, a4, e32, m4, ta, ma
; RV32-NEXT: vnsrl.wi v16, v24, 0, v0.t
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a4, 49
+; RV32-NEXT: li a4, 50
; RV32-NEXT: mul a1, a1, a4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
@@ -420,65 +432,68 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: # %bb.11:
; RV32-NEXT: li a1, 32
; RV32-NEXT: .LBB16_12:
+; RV32-NEXT: addi a4, sp, 16
+; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmv4r.v v24, v16
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: li a5, 24
+; RV32-NEXT: li a5, 25
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
-; RV32-NEXT: addi a4, sp, 16
-; RV32-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a5, a4, 6
-; RV32-NEXT: add a4, a5, a4
+; RV32-NEXT: li a5, 66
+; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; RV32-NEXT: vslideup.vi v16, v8, 16
+; RV32-NEXT: vslideup.vi v16, v24, 16
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a5, a4, 6
-; RV32-NEXT: add a4, a5, a4
+; RV32-NEXT: li a5, 66
+; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32-NEXT: addi a4, a1, -16
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 57
+; RV32-NEXT: li a6, 58
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vslideup.vi v8, v0, 16
+; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vslideup.vi v16, v0, 16
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 57
+; RV32-NEXT: li a6, 58
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 49
+; RV32-NEXT: li a6, 50
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vslideup.vi v8, v24, 16
+; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vslideup.vi v16, v8, 16
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 49
+; RV32-NEXT: li a6, 50
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV32-NEXT: sltu a1, a1, a4
; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a4
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a4, a4, 5
+; RV32-NEXT: slli a5, a4, 5
+; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a4, a4, 4
+; RV32-NEXT: li a5, 24
+; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
@@ -489,13 +504,13 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: li a7, 16
; RV32-NEXT: .LBB16_14:
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 48
+; RV32-NEXT: li a2, 49
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 40
+; RV32-NEXT: li a2, 41
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
@@ -507,7 +522,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: vse32.v v24, (a0)
; RV32-NEXT: addi a1, a0, 256
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 49
+; RV32-NEXT: li a3, 50
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
@@ -515,7 +530,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: addi a1, a0, 128
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 57
+; RV32-NEXT: li a3, 58
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
@@ -523,14 +538,14 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: addi a0, a0, 384
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a2, a1, 6
-; RV32-NEXT: add a1, a2, a1
+; RV32-NEXT: li a2, 66
+; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 73
+; RV32-NEXT: li a1, 74
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 32
@@ -547,21 +562,24 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: sd s0, 40(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset s0, -8
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 73
+; RV64-NEXT: li a3, 74
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: sub sp, sp, a2
-; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0xc9, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 73 * vlenb
+; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0xca, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 74 * vlenb
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: slli a2, a2, 5
+; RV64-NEXT: slli a3, a2, 5
+; RV64-NEXT: add a2, a3, a2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 32
; RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 40
+; RV64-NEXT: li a3, 41
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 32
; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; RV64-NEXT: vslidedown.vi v8, v0, 8
; RV64-NEXT: addi a3, a7, -64
; RV64-NEXT: li a2, 16
; RV64-NEXT: sltu a4, a7, a3
@@ -571,177 +589,186 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: sltu a5, a4, a3
; RV64-NEXT: addi a5, a5, -1
; RV64-NEXT: and a3, a5, a3
-; RV64-NEXT: addi a6, a3, -16
+; RV64-NEXT: addi t0, a3, -16
; RV64-NEXT: mv a5, a3
-; RV64-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; RV64-NEXT: vslidedown.vi v8, v0, 8
-; RV64-NEXT: csrr t0, vlenb
-; RV64-NEXT: li t1, 48
-; RV64-NEXT: mul t0, t0, t1
-; RV64-NEXT: add t0, sp, t0
-; RV64-NEXT: addi t0, t0, 32
-; RV64-NEXT: vs1r.v v0, (t0) # vscale x 8-byte Folded Spill
+; RV64-NEXT: csrr a6, vlenb
+; RV64-NEXT: li t1, 49
+; RV64-NEXT: mul a6, a6, t1
+; RV64-NEXT: add a6, sp, a6
+; RV64-NEXT: addi a6, a6, 32
+; RV64-NEXT: vs1r.v v0, (a6) # vscale x 8-byte Folded Spill
; RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vi v9, v0, 4
-; RV64-NEXT: vmv1r.v v13, v8
-; RV64-NEXT: vslidedown.vi v10, v8, 4
+; RV64-NEXT: vmv1r.v v28, v8
+; RV64-NEXT: vslidedown.vi v8, v8, 4
; RV64-NEXT: bltu a3, a2, .LBB16_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a5, 16
; RV64-NEXT: .LBB16_2:
; RV64-NEXT: li t2, 64
-; RV64-NEXT: sltu t1, a3, a6
-; RV64-NEXT: mv t0, a7
+; RV64-NEXT: sltu t1, a3, t0
+; RV64-NEXT: mv a6, a7
; RV64-NEXT: bltu a7, t2, .LBB16_4
; RV64-NEXT: # %bb.3:
-; RV64-NEXT: li t0, 64
+; RV64-NEXT: li a6, 64
; RV64-NEXT: .LBB16_4:
-; RV64-NEXT: addi t3, a1, 128
-; RV64-NEXT: vmv1r.v v12, v9
+; RV64-NEXT: addi t2, a1, 128
+; RV64-NEXT: csrr a3, vlenb
+; RV64-NEXT: li t3, 24
+; RV64-NEXT: mul a3, a3, t3
+; RV64-NEXT: add a3, sp, a3
+; RV64-NEXT: addi a3, a3, 32
+; RV64-NEXT: vs1r.v v9, (a3) # vscale x 8-byte Folded Spill
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vi v14, v9, 2
+; RV64-NEXT: vslidedown.vi v31, v9, 2
; RV64-NEXT: addi s0, a1, 512
; RV64-NEXT: addi t6, a1, 640
+; RV64-NEXT: vmv1r.v v30, v8
+; RV64-NEXT: vslidedown.vi v0, v8, 2
; RV64-NEXT: addi t1, t1, -1
-; RV64-NEXT: addi t2, a1, 384
+; RV64-NEXT: addi t3, a1, 384
; RV64-NEXT: li a3, 32
-; RV64-NEXT: addi t4, t0, -32
-; RV64-NEXT: sltu t0, t0, t4
-; RV64-NEXT: addi t0, t0, -1
-; RV64-NEXT: and t0, t0, t4
-; RV64-NEXT: addi t4, t0, -16
-; RV64-NEXT: sltu t5, t0, t4
+; RV64-NEXT: addi t4, a6, -32
+; RV64-NEXT: sltu a6, a6, t4
+; RV64-NEXT: addi a6, a6, -1
+; RV64-NEXT: and a6, a6, t4
+; RV64-NEXT: addi t4, a6, -16
+; RV64-NEXT: sltu t5, a6, t4
; RV64-NEXT: addi t5, t5, -1
-; RV64-NEXT: vslidedown.vi v0, v10, 2
-; RV64-NEXT: vslidedown.vi v15, v13, 2
-; RV64-NEXT: bltu t0, a2, .LBB16_6
+; RV64-NEXT: vslidedown.vi v29, v28, 2
+; RV64-NEXT: bltu a6, a2, .LBB16_6
; RV64-NEXT: # %bb.5:
-; RV64-NEXT: li t0, 16
+; RV64-NEXT: li a6, 16
; RV64-NEXT: .LBB16_6:
-; RV64-NEXT: vmv1r.v v7, v10
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vle64.v v16, (s0)
+; RV64-NEXT: vle64.v v8, (s0)
; RV64-NEXT: csrr s0, vlenb
; RV64-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT: li a0, 57
+; RV64-NEXT: li a0, 58
; RV64-NEXT: mul s0, s0, a0
; RV64-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: add s0, sp, s0
; RV64-NEXT: addi s0, s0, 32
-; RV64-NEXT: vs8r.v v16, (s0) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vle64.v v24, (t6)
-; RV64-NEXT: vle64.v v16, (t3)
-; RV64-NEXT: csrr t3, vlenb
-; RV64-NEXT: slli t3, t3, 4
-; RV64-NEXT: add t3, sp, t3
-; RV64-NEXT: addi t3, t3, 32
-; RV64-NEXT: vs8r.v v16, (t3) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vle64.v v16, (a1)
-; RV64-NEXT: csrr t3, vlenb
-; RV64-NEXT: slli t3, t3, 3
-; RV64-NEXT: add t3, sp, t3
-; RV64-NEXT: addi t3, t3, 32
-; RV64-NEXT: vs8r.v v16, (t3) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vle64.v v16, (t2)
+; RV64-NEXT: vs8r.v v8, (s0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vle64.v v16, (t6)
+; RV64-NEXT: vle64.v v8, (t2)
; RV64-NEXT: csrr t2, vlenb
-; RV64-NEXT: li t3, 49
-; RV64-NEXT: mul t2, t2, t3
+; RV64-NEXT: slli t2, t2, 3
; RV64-NEXT: add t2, sp, t2
; RV64-NEXT: addi t2, t2, 32
-; RV64-NEXT: vs8r.v v16, (t2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: and t2, t1, a6
+; RV64-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vle64.v v8, (a1)
+; RV64-NEXT: csrr t2, vlenb
+; RV64-NEXT: li t6, 50
+; RV64-NEXT: mul t2, t2, t6
+; RV64-NEXT: add t2, sp, t2
+; RV64-NEXT: addi t2, t2, 32
+; RV64-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vle64.v v8, (t3)
+; RV64-NEXT: csrr t2, vlenb
+; RV64-NEXT: slli t2, t2, 4
+; RV64-NEXT: add t2, sp, t2
+; RV64-NEXT: addi t2, t2, 32
+; RV64-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: and t2, t1, t0
; RV64-NEXT: and t1, t5, t4
; RV64-NEXT: addi a1, a1, 256
-; RV64-NEXT: mv a6, a4
+; RV64-NEXT: mv t0, a4
; RV64-NEXT: bltu a4, a3, .LBB16_8
; RV64-NEXT: # %bb.7:
-; RV64-NEXT: li a6, 32
+; RV64-NEXT: li t0, 32
; RV64-NEXT: .LBB16_8:
; RV64-NEXT: vsetvli zero, t2, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v8, v24, 0, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
+; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; RV64-NEXT: addi t2, sp, 32
+; RV64-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv1r.v v0, v30
; RV64-NEXT: csrr t2, vlenb
-; RV64-NEXT: li t3, 57
+; RV64-NEXT: li t3, 58
; RV64-NEXT: mul t2, t2, t3
; RV64-NEXT: add t2, sp, t2
; RV64-NEXT: addi t2, t2, 32
; RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, a5, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v24, v16, 0, v0.t
+; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: slli t2, a5, 6
-; RV64-NEXT: add a5, t2, a5
+; RV64-NEXT: li t2, 66
+; RV64-NEXT: mul a5, a5, t2
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v14
+; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv1r.v v0, v31
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: slli a5, a5, 4
+; RV64-NEXT: slli a5, a5, 3
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, t1, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v24, v16, 0, v0.t
+; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li t1, 24
+; RV64-NEXT: li t1, 25
; RV64-NEXT: mul a5, a5, t1
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v12
-; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: slli a5, a5, 3
-; RV64-NEXT: add a5, sp, a5
-; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetvli zero, t0, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v16, v24, 0, v0.t
-; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li t0, 57
-; RV64-NEXT: mul a5, a5, t0
-; RV64-NEXT: add a5, sp, a5
-; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
-; RV64-NEXT: addi a5, a6, -16
-; RV64-NEXT: sltu a6, a6, a5
-; RV64-NEXT: addi a6, a6, -1
+; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; RV64-NEXT: addi a5, t0, -16
+; RV64-NEXT: sltu t0, t0, a5
+; RV64-NEXT: addi t0, t0, -1
+; RV64-NEXT: and a5, t0, a5
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vle64.v v16, (a1)
+; RV64-NEXT: vle64.v v8, (a1)
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV64-NEXT: and a1, a6, a5
-; RV64-NEXT: vmv1r.v v0, v15
-; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 49
-; RV64-NEXT: mul a5, a5, a6
-; RV64-NEXT: add a5, sp, a5
-; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetvli zero, a1, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v24, v16, 0, v0.t
-; RV64-NEXT: addi a1, sp, 32
-; RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li t0, 50
+; RV64-NEXT: mul a1, a1, t0
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 32
+; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a5, 48
-; RV64-NEXT: mul a1, a1, a5
+; RV64-NEXT: li t0, 24
+; RV64-NEXT: mul a1, a1, t0
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vl1r.v v12, (a1) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsetvli zero, a6, e32, m4, ta, ma
+; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a6, 58
+; RV64-NEXT: mul a1, a1, a6
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 32
+; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a6, 49
+; RV64-NEXT: mul a1, a1, a6
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 32
+; RV64-NEXT: vl1r.v v8, (a1) # vscale x 8-byte Folded Reload
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vi v12, v12, 2
+; RV64-NEXT: vslidedown.vi v8, v8, 2
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a6, 24
+; RV64-NEXT: mul a1, a1, a6
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 32
+; RV64-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
+; RV64-NEXT: vmv1r.v v0, v29
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 4
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vs1r.v v12, (a1) # vscale x 8-byte Folded Spill
+; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vsetvli zero, a5, e32, m4, ta, ma
+; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
; RV64-NEXT: bltu a4, a2, .LBB16_10
; RV64-NEXT: # %bb.9:
; RV64-NEXT: li a4, 16
; RV64-NEXT: .LBB16_10:
-; RV64-NEXT: vmv1r.v v0, v13
+; RV64-NEXT: vmv1r.v v0, v28
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, sp, a1
@@ -750,7 +777,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: vsetvli zero, a4, e32, m4, ta, ma
; RV64-NEXT: vnsrl.wi v16, v24, 0, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a4, 49
+; RV64-NEXT: li a4, 50
; RV64-NEXT: mul a1, a1, a4
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
@@ -760,65 +787,68 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: # %bb.11:
; RV64-NEXT: li a1, 32
; RV64-NEXT: .LBB16_12:
+; RV64-NEXT: addi a4, sp, 32
+; RV64-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmv4r.v v24, v16
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: li a5, 24
+; RV64-NEXT: li a5, 25
; RV64-NEXT: mul a4, a4, a5
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
; RV64-NEXT: vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: addi a4, sp, 32
-; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a5, a4, 6
-; RV64-NEXT: add a4, a5, a4
+; RV64-NEXT: li a5, 66
+; RV64-NEXT: mul a4, a4, a5
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
; RV64-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; RV64-NEXT: vslideup.vi v16, v8, 16
+; RV64-NEXT: vslideup.vi v16, v24, 16
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a5, a4, 6
-; RV64-NEXT: add a4, a5, a4
+; RV64-NEXT: li a5, 66
+; RV64-NEXT: mul a4, a4, a5
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64-NEXT: addi a4, a1, -16
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 57
+; RV64-NEXT: li a6, 58
; RV64-NEXT: mul a5, a5, a6
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vslideup.vi v8, v0, 16
+; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vslideup.vi v16, v0, 16
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 57
+; RV64-NEXT: li a6, 58
; RV64-NEXT: mul a5, a5, a6
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 49
+; RV64-NEXT: li a6, 50
; RV64-NEXT: mul a5, a5, a6
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vslideup.vi v8, v24, 16
+; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vslideup.vi v16, v8, 16
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 49
+; RV64-NEXT: li a6, 50
; RV64-NEXT: mul a5, a5, a6
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
; RV64-NEXT: sltu a1, a1, a4
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: and a1, a1, a4
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 5
+; RV64-NEXT: slli a5, a4, 5
+; RV64-NEXT: add a4, a5, a4
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
; RV64-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a4, a4, 4
+; RV64-NEXT: li a5, 24
+; RV64-NEXT: mul a4, a4, a5
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
; RV64-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
@@ -829,13 +859,13 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: li a7, 16
; RV64-NEXT: .LBB16_14:
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 48
+; RV64-NEXT: li a2, 49
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 40
+; RV64-NEXT: li a2, 41
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
@@ -847,7 +877,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: vse32.v v24, (a0)
; RV64-NEXT: addi a1, a0, 256
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 49
+; RV64-NEXT: li a3, 50
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 32
@@ -855,7 +885,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: vse32.v v8, (a1)
; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 57
+; RV64-NEXT: li a3, 58
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 32
@@ -863,14 +893,14 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: vse32.v v8, (a1)
; RV64-NEXT: addi a0, a0, 384
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a2, a1, 6
-; RV64-NEXT: add a1, a2, a1
+; RV64-NEXT: li a2, 66
+; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 73
+; RV64-NEXT: li a1, 74
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 48
@@ -889,8 +919,8 @@ define <32 x i32> @vtrunc_v32i32_v32i64(<32 x i64> %a, <32 x i1> %m, i32 zeroext
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vslidedown.vi v12, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB17_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
index 2b35ad000e6d6..3d1febe95421f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
@@ -363,9 +363,9 @@ define <32 x double> @vuitofp_v32f64_v32i64(<32 x i64> %va, <32 x i1> %m, i32 ze
; CHECK-LABEL: vuitofp_v32f64_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB25_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
index 06a958b4df7d2..1fc4283795075 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
@@ -352,12 +352,12 @@ define <256 x i8> @vadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %ev
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
-; CHECK-NEXT: addi a3, a1, -128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: sltu a0, a1, a3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a3
+; CHECK-NEXT: addi a0, a1, -128
+; CHECK-NEXT: sltu a3, a1, a0
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a0, a3, a0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB32_2
@@ -1319,9 +1319,9 @@ define <32 x i64> @vadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; CHECK-LABEL: vadd_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB108_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
@@ -1375,10 +1375,11 @@ define <32 x i64> @vadd_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
define <32 x i64> @vadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vadd_vx_v32i64_evl27:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v0, 2
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
index d752848664009..671da89366041 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
@@ -548,9 +548,9 @@ define <32 x double> @vfabs_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; CHECK-LABEL: vfabs_vv_v32f64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB34_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
index 58d889860abd2..e94c8278f511a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
@@ -524,9 +524,9 @@ define <32 x double> @vfneg_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; CHECK-LABEL: vfneg_vv_v32f64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB34_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
index ef5497c766e30..b431d4873fa1b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
@@ -352,9 +352,9 @@ define <32 x double> @vfsqrt_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zero
; CHECK-LABEL: vfsqrt_vv_v32f64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB26_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
index 179c303fb3414..eafb52c1c006a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
@@ -256,12 +256,12 @@ define <256 x i8> @vmax_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zero
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
-; CHECK-NEXT: addi a4, a2, -128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: sltu a1, a2, a4
-; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: addi a1, a2, -128
+; CHECK-NEXT: sltu a4, a2, a1
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a1, a4, a1
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmax.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB22_2
@@ -991,9 +991,9 @@ define <32 x i64> @vmax_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; CHECK-LABEL: vmax_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB74_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
index 729621d7c53eb..dd234cb203873 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
@@ -255,12 +255,12 @@ define <256 x i8> @vmaxu_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zer
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
-; CHECK-NEXT: addi a4, a2, -128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: sltu a1, a2, a4
-; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: addi a1, a2, -128
+; CHECK-NEXT: sltu a4, a2, a1
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a1, a4, a1
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmaxu.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB22_2
@@ -990,9 +990,9 @@ define <32 x i64> @vmaxu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; CHECK-LABEL: vmaxu_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB74_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
index e3a3087241e2f..609d1df976dde 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
@@ -256,12 +256,12 @@ define <256 x i8> @vmin_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zero
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
-; CHECK-NEXT: addi a4, a2, -128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: sltu a1, a2, a4
-; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: addi a1, a2, -128
+; CHECK-NEXT: sltu a4, a2, a1
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a1, a4, a1
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmin.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB22_2
@@ -991,9 +991,9 @@ define <32 x i64> @vmin_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; CHECK-LABEL: vmin_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB74_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
index f7a4c11f576ca..7c4efb760393e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
@@ -255,12 +255,12 @@ define <256 x i8> @vminu_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zer
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
-; CHECK-NEXT: addi a4, a2, -128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: sltu a1, a2, a4
-; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: addi a1, a2, -128
+; CHECK-NEXT: sltu a4, a2, a1
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a1, a4, a1
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vminu.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB22_2
@@ -990,9 +990,9 @@ define <32 x i64> @vminu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; CHECK-LABEL: vminu_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB74_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
index bcd4c530334d0..a72ae512b2019 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
@@ -361,12 +361,12 @@ define <256 x i8> @vsadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %e
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
-; CHECK-NEXT: addi a3, a1, -128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: sltu a0, a1, a3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a3
+; CHECK-NEXT: addi a0, a1, -128
+; CHECK-NEXT: sltu a3, a1, a0
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a0, a3, a0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB32_2
@@ -1326,9 +1326,9 @@ define <32 x i64> @vsadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; CHECK-LABEL: vsadd_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB108_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
@@ -1382,10 +1382,11 @@ define <32 x i64> @vsadd_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
define <32 x i64> @vsadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vsadd_vx_v32i64_evl27:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v0, 2
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
index 1c3348f8f5f13..51bab9bcf2997 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
@@ -357,12 +357,12 @@ define <256 x i8> @vsaddu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
-; CHECK-NEXT: addi a3, a1, -128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: sltu a0, a1, a3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a3
+; CHECK-NEXT: addi a0, a1, -128
+; CHECK-NEXT: sltu a3, a1, a0
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a0, a3, a0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB32_2
@@ -1322,9 +1322,9 @@ define <32 x i64> @vsaddu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %e
; CHECK-LABEL: vsaddu_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB108_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
@@ -1378,10 +1378,11 @@ define <32 x i64> @vsaddu_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
define <32 x i64> @vsaddu_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vsaddu_vx_v32i64_evl27:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v0, 2
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
index cbf4c37b70ecb..2db96dca3123d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
@@ -140,8 +140,8 @@ define <256 x i8> @select_v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c, i3
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
+; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: addi a4, a1, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -152,6 +152,7 @@ define <256 x i8> @select_v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c, i3
; CHECK-NEXT: vle8.v v16, (a1)
; CHECK-NEXT: addi a4, a4, -1
; CHECK-NEXT: and a0, a4, a0
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vmerge.vvm v24, v8, v24, v0
; CHECK-NEXT: bltu a3, a2, .LBB11_2
@@ -179,16 +180,17 @@ define <256 x i8> @select_evl_v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c
; CHECK-LABEL: select_evl_v256i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmv1r.v v7, v8
+; CHECK-NEXT: vmv1r.v v6, v0
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: addi a3, a1, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v24, (a3)
; CHECK-NEXT: vle8.v v8, (a1)
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v24, (a0), v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: vmv8r.v v16, v24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
index 1cb1a838a2596..f5aba6885efcc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
@@ -374,11 +374,11 @@ define <256 x i8> @vssub_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %e
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: addi a3, a1, -128
-; CHECK-NEXT: sltu a4, a1, a3
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: sltu a0, a1, a3
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a3, a0, a3
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t
@@ -1366,9 +1366,9 @@ define <32 x i64> @vssub_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; CHECK-LABEL: vssub_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB108_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
@@ -1425,11 +1425,12 @@ define <32 x i64> @vssub_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
define <32 x i64> @vssub_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vssub_vx_v32i64_evl27:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v0, 2
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
index 199a341e12acd..1d74d1f5a6ead 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
@@ -369,11 +369,11 @@ define <256 x i8> @vssubu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: addi a3, a1, -128
-; CHECK-NEXT: sltu a4, a1, a3
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: sltu a0, a1, a3
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a3, a0, a3
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t
@@ -1361,9 +1361,9 @@ define <32 x i64> @vssubu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %e
; CHECK-LABEL: vssubu_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB108_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
@@ -1420,11 +1420,12 @@ define <32 x i64> @vssubu_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
define <32 x i64> @vssubu_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vssubu_vx_v32i64_evl27:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v0, 2
+; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
index 890a537683ba2..714c027fbfa0b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
@@ -138,9 +138,9 @@ define <32 x i64> @vzext_v32i64_v32i32(<32 x i32> %va, <32 x i1> %m, i32 zeroext
; CHECK-LABEL: vzext_v32i64_v32i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v0, 2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB12_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
index 333216423ad63..fe41552c4c984 100644
--- a/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
@@ -17,12 +17,12 @@ define <vscale x 1 x bfloat> @vp_floor_nxv1bf16(<vscale x 1 x bfloat> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -67,12 +67,12 @@ define <vscale x 2 x bfloat> @vp_floor_nxv2bf16(<vscale x 2 x bfloat> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
@@ -410,12 +410,12 @@ define <vscale x 1 x half> @vp_floor_nxv1f16(<vscale x 1 x half> %va, <vscale x
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -494,12 +494,12 @@ define <vscale x 2 x half> @vp_floor_nxv2f16(<vscale x 2 x half> %va, <vscale x
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
index cebc7287c0a7e..c0ddb812f833e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
@@ -169,46 +169,47 @@ define <vscale x 32 x bfloat> @vfmax_nxv32bf16_vv(<vscale x 32 x bfloat> %a, <vs
; ZVFBFMIN-NEXT: slli a0, a0, 4
; ZVFBFMIN-NEXT: sub sp, sp, a0
; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vmv8r.v v24, v16
+; ZVFBFMIN-NEXT: vmv8r.v v0, v16
+; ZVFBFMIN-NEXT: vmv8r.v v24, v8
; ZVFBFMIN-NEXT: addi a0, sp, 16
-; ZVFBFMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; ZVFBFMIN-NEXT: vmv8r.v v0, v8
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v24
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v0
+; ZVFBFMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v0
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v24
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
+; ZVFBFMIN-NEXT: vmfeq.vv v3, v16, v16
; ZVFBFMIN-NEXT: vmerge.vvm v24, v8, v16, v0
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
; ZVFBFMIN-NEXT: addi a0, a0, 16
; ZVFBFMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
+; ZVFBFMIN-NEXT: vmv1r.v v0, v3
; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v8, v0
-; ZVFBFMIN-NEXT: addi a0, sp, 16
-; ZVFBFMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v28
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v24, v4
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
; ZVFBFMIN-NEXT: addi a0, a0, 16
-; ZVFBFMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFBFMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFBFMIN-NEXT: vfmax.vv v8, v8, v24
+; ZVFBFMIN-NEXT: vfmax.vv v8, v8, v16
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
; ZVFBFMIN-NEXT: addi a0, a0, 16
; ZVFBFMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFBFMIN-NEXT: addi a0, sp, 16
+; ZVFBFMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v4
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v20
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmerge.vvm v24, v8, v16, v0
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v8, v0
-; ZVFBFMIN-NEXT: vfmax.vv v16, v8, v24
+; ZVFBFMIN-NEXT: vmerge.vvm v16, v8, v24, v0
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v24, v24
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v24, v8, v0
+; ZVFBFMIN-NEXT: vfmax.vv v16, v8, v16
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
@@ -399,46 +400,47 @@ define <vscale x 32 x half> @vfmax_nxv32f16_vv(<vscale x 32 x half> %a, <vscale
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: sub sp, sp, a0
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: vmv8r.v v0, v16
+; ZVFHMIN-NEXT: vmv8r.v v24, v8
; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vmv8r.v v0, v8
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v0
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
+; ZVFHMIN-NEXT: vmfeq.vv v3, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
+; ZVFHMIN-NEXT: vmv1r.v v0, v3
; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmax.vv v8, v8, v24
+; ZVFHMIN-NEXT: vfmax.vv v8, v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
-; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
-; ZVFHMIN-NEXT: vfmax.vv v16, v8, v24
+; ZVFHMIN-NEXT: vmerge.vvm v16, v8, v24, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24
+; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v8, v0
+; ZVFHMIN-NEXT: vfmax.vv v16, v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
index c5da02c3af05c..6d3d9fecfa0d8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
@@ -237,9 +237,6 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
@@ -252,18 +249,21 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: li a4, 25
-; CHECK-NEXT: mul a2, a2, a4
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; CHECK-NEXT: mul a3, a3, a4
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 25
@@ -392,7 +392,8 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v6, v24, v24, v0.t
+; CHECK-NEXT: vmfeq.vv v8, v24, v24, v0.t
+; CHECK-NEXT: vmv1r.v v5, v8
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2
@@ -402,12 +403,12 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v7, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vmv1r.v v6, v0
+; CHECK-NEXT: vmv1r.v v0, v5
; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
-; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vfmax.vv v16, v8, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
@@ -816,9 +817,6 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -831,18 +829,21 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: sltu a2, a0, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: li a4, 25
-; ZVFHMIN-NEXT: mul a2, a2, a4
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: mul a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: li a3, 25
@@ -981,7 +982,8 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v6, v24, v24, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v5, v8
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
@@ -991,12 +993,12 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v7, v8, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v5, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vmv1r.v v6, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v5
; ZVFHMIN-NEXT: vmerge.vvm v16, v24, v8, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v24, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v5
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vfmax.vv v16, v8, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
@@ -1321,16 +1323,16 @@ define <vscale x 16 x double> @vfmax_vv_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a3, a1, 3
+; CHECK-NEXT: srli a4, a1, 3
+; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v5, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a4
; CHECK-NEXT: sub a4, a2, a1
; CHECK-NEXT: add a3, a0, a3
; CHECK-NEXT: vl8re64.v v24, (a3)
; CHECK-NEXT: sltu a3, a2, a4
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a3, a3, a4
-; CHECK-NEXT: srli a4, a1, 3
-; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a4
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v7, v16, v16, v0.t
; CHECK-NEXT: vmfeq.vv v6, v24, v24, v0.t
@@ -1397,10 +1399,7 @@ define <vscale x 16 x double> @vfmax_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a3, a1, 3
@@ -1411,32 +1410,43 @@ define <vscale x 16 x double> @vfmax_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a3, a3, a4
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v7, v24, v24
; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
-; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: vfmax.vv v8, v16, v8
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: bltu a2, a1, .LBB41_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB41_2:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -1444,7 +1454,10 @@ define <vscale x 16 x double> @vfmax_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: vfmax.vv v8, v8, v24
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
index 13d41efc556bb..02ae0b8032776 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
@@ -169,46 +169,47 @@ define <vscale x 32 x bfloat> @vfmin_nxv32bf16_vv(<vscale x 32 x bfloat> %a, <vs
; ZVFBFMIN-NEXT: slli a0, a0, 4
; ZVFBFMIN-NEXT: sub sp, sp, a0
; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vmv8r.v v24, v16
+; ZVFBFMIN-NEXT: vmv8r.v v0, v16
+; ZVFBFMIN-NEXT: vmv8r.v v24, v8
; ZVFBFMIN-NEXT: addi a0, sp, 16
-; ZVFBFMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; ZVFBFMIN-NEXT: vmv8r.v v0, v8
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v24
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v0
+; ZVFBFMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v0
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v24
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
+; ZVFBFMIN-NEXT: vmfeq.vv v3, v16, v16
; ZVFBFMIN-NEXT: vmerge.vvm v24, v8, v16, v0
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
; ZVFBFMIN-NEXT: addi a0, a0, 16
; ZVFBFMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
+; ZVFBFMIN-NEXT: vmv1r.v v0, v3
; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v8, v0
-; ZVFBFMIN-NEXT: addi a0, sp, 16
-; ZVFBFMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v28
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v24, v4
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
; ZVFBFMIN-NEXT: addi a0, a0, 16
-; ZVFBFMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFBFMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFBFMIN-NEXT: vfmin.vv v8, v8, v24
+; ZVFBFMIN-NEXT: vfmin.vv v8, v8, v16
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
; ZVFBFMIN-NEXT: addi a0, a0, 16
; ZVFBFMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFBFMIN-NEXT: addi a0, sp, 16
+; ZVFBFMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v4
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v20
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmerge.vvm v24, v8, v16, v0
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v8, v0
-; ZVFBFMIN-NEXT: vfmin.vv v16, v8, v24
+; ZVFBFMIN-NEXT: vmerge.vvm v16, v8, v24, v0
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v24, v24
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v24, v8, v0
+; ZVFBFMIN-NEXT: vfmin.vv v16, v8, v16
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
@@ -399,46 +400,47 @@ define <vscale x 32 x half> @vfmin_nxv32f16_vv(<vscale x 32 x half> %a, <vscale
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: sub sp, sp, a0
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: vmv8r.v v0, v16
+; ZVFHMIN-NEXT: vmv8r.v v24, v8
; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vmv8r.v v0, v8
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v0
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
+; ZVFHMIN-NEXT: vmfeq.vv v3, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
+; ZVFHMIN-NEXT: vmv1r.v v0, v3
; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmin.vv v8, v8, v24
+; ZVFHMIN-NEXT: vfmin.vv v8, v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
-; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
-; ZVFHMIN-NEXT: vfmin.vv v16, v8, v24
+; ZVFHMIN-NEXT: vmerge.vvm v16, v8, v24, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24
+; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v8, v0
+; ZVFHMIN-NEXT: vfmin.vv v16, v8, v16
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
index 72cd2ef1d9702..ab0b4fefbb786 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
@@ -237,9 +237,6 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
@@ -252,18 +249,21 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: li a4, 25
-; CHECK-NEXT: mul a2, a2, a4
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; CHECK-NEXT: mul a3, a3, a4
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 25
@@ -392,7 +392,8 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v6, v24, v24, v0.t
+; CHECK-NEXT: vmfeq.vv v8, v24, v24, v0.t
+; CHECK-NEXT: vmv1r.v v5, v8
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2
@@ -402,12 +403,12 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v7, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vmv1r.v v6, v0
+; CHECK-NEXT: vmv1r.v v0, v5
; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
-; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vfmin.vv v16, v8, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
@@ -816,9 +817,6 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -831,18 +829,21 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: sltu a2, a0, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: li a4, 25
-; ZVFHMIN-NEXT: mul a2, a2, a4
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: mul a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: li a3, 25
@@ -981,7 +982,8 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v6, v24, v24, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v5, v8
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
@@ -991,12 +993,12 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v7, v8, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v5, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vmv1r.v v6, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v5
; ZVFHMIN-NEXT: vmerge.vvm v16, v24, v8, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v24, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v5
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vfmin.vv v16, v8, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
@@ -1321,16 +1323,16 @@ define <vscale x 16 x double> @vfmin_vv_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a3, a1, 3
+; CHECK-NEXT: srli a4, a1, 3
+; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v5, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a4
; CHECK-NEXT: sub a4, a2, a1
; CHECK-NEXT: add a3, a0, a3
; CHECK-NEXT: vl8re64.v v24, (a3)
; CHECK-NEXT: sltu a3, a2, a4
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a3, a3, a4
-; CHECK-NEXT: srli a4, a1, 3
-; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a4
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v7, v16, v16, v0.t
; CHECK-NEXT: vmfeq.vv v6, v24, v24, v0.t
@@ -1397,10 +1399,7 @@ define <vscale x 16 x double> @vfmin_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a3, a1, 3
@@ -1411,32 +1410,43 @@ define <vscale x 16 x double> @vfmin_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a3, a3, a4
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v7, v24, v24
; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
-; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: vfmin.vv v8, v16, v8
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: bltu a2, a1, .LBB41_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB41_2:
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -1444,7 +1454,10 @@ define <vscale x 16 x double> @vfmin_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: vfmin.vv v8, v8, v24
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
index 1a0d1431de1d0..5d00204f903fe 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
@@ -1506,69 +1506,104 @@ define <vscale x 16 x i64> @fshl_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a3, 26
-; CHECK-NEXT: mul a1, a1, a3
+; CHECK-NEXT: slli a3, a1, 5
+; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a3, a1, 4
-; CHECK-NEXT: add a1, a3, a1
+; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: li a1, 63
; CHECK-NEXT: slli a5, a3, 3
+; CHECK-NEXT: srli a1, a3, 3
; CHECK-NEXT: sub a6, a4, a3
-; CHECK-NEXT: add a7, a2, a5
-; CHECK-NEXT: vl8re64.v v8, (a7)
-; CHECK-NEXT: sltu a7, a4, a6
-; CHECK-NEXT: addi a7, a7, -1
-; CHECK-NEXT: and a6, a7, a6
-; CHECK-NEXT: srli a7, a3, 3
-; CHECK-NEXT: csrr t0, vlenb
-; CHECK-NEXT: li t1, 25
-; CHECK-NEXT: mul t0, t0, t1
-; CHECK-NEXT: add t0, sp, t0
-; CHECK-NEXT: addi t0, t0, 16
-; CHECK-NEXT: vs1r.v v0, (t0) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vsetvli t0, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a7
-; CHECK-NEXT: addi a7, sp, 16
+; CHECK-NEXT: csrr a7, vlenb
+; CHECK-NEXT: slli a7, a7, 5
+; CHECK-NEXT: add a7, sp, a7
+; CHECK-NEXT: addi a7, a7, 16
; CHECK-NEXT: vs1r.v v0, (a7) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vx v8, v0, a1
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: li a7, 24
+; CHECK-NEXT: mul a1, a1, a7
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: add a1, a2, a5
+; CHECK-NEXT: vl8re64.v v8, (a1)
+; CHECK-NEXT: sltu a1, a4, a6
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a6, a1, a6
+; CHECK-NEXT: li a1, 63
+; CHECK-NEXT: csrr a7, vlenb
+; CHECK-NEXT: li t0, 24
+; CHECK-NEXT: mul a7, a7, t0
+; CHECK-NEXT: add a7, sp, a7
+; CHECK-NEXT: addi a7, a7, 16
+; CHECK-NEXT: vl1r.v v0, (a7) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; CHECK-NEXT: vand.vx v24, v8, a1, v0.t
-; CHECK-NEXT: vsll.vv v16, v16, v24, v0.t
; CHECK-NEXT: csrr a6, vlenb
-; CHECK-NEXT: slli a7, a6, 3
-; CHECK-NEXT: add a6, a7, a6
+; CHECK-NEXT: li a7, 24
+; CHECK-NEXT: mul a6, a6, a7
; CHECK-NEXT: add a6, sp, a6
; CHECK-NEXT: addi a6, a6, 16
+; CHECK-NEXT: vl1r.v v0, (a6) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsll.vv v16, v16, v24, v0.t
+; CHECK-NEXT: addi a6, sp, 16
; CHECK-NEXT: vs8r.v v16, (a6) # vscale x 64-byte Folded Spill
; CHECK-NEXT: add a5, a0, a5
+; CHECK-NEXT: csrr a6, vlenb
+; CHECK-NEXT: li a7, 24
+; CHECK-NEXT: mul a6, a6, a7
+; CHECK-NEXT: add a6, sp, a6
+; CHECK-NEXT: addi a6, a6, 16
+; CHECK-NEXT: vl1r.v v0, (a6) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vnot.v v24, v8, v0.t
; CHECK-NEXT: vl8re64.v v16, (a5)
+; CHECK-NEXT: csrr a5, vlenb
+; CHECK-NEXT: li a6, 24
+; CHECK-NEXT: mul a5, a5, a6
+; CHECK-NEXT: add a5, sp, a5
+; CHECK-NEXT: addi a5, a5, 16
+; CHECK-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vand.vx v8, v24, a1, v0.t
; CHECK-NEXT: vl8re64.v v24, (a0)
-; CHECK-NEXT: vl8re64.v v0, (a2)
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vl8re64.v v24, (a2)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a2, 24
+; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsrl.vi v16, v16, 1, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a2, 24
+; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsrl.vv v8, v16, v8, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a2, a0, 3
-; CHECK-NEXT: add a0, a2, a0
+; CHECK-NEXT: li a2, 24
+; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a2, a0, 3
-; CHECK-NEXT: add a0, a2, a0
+; CHECK-NEXT: li a2, 24
+; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
@@ -1577,74 +1612,68 @@ define <vscale x 16 x i64> @fshl_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
; CHECK-NEXT: mv a4, a3
; CHECK-NEXT: .LBB47_2:
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a2, 25
-; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v16, v24, 1, v0.t
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a2, 25
-; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
+; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vnot.v v24, v8, v0.t
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vnot.v v24, v24, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a2, 25
-; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a2, 25
-; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsrl.vv v16, v16, v24, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a2, 25
-; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vand.vx v24, v8, a1, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a1, a0, 4
-; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 25
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsll.vv v24, v8, v24, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 25
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vor.vv v8, v24, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a1, a0, 3
-; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: li a1, 24
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 26
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a1, a0, 5
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
index e81abda5f301c..0d6d09e8dfa08 100644
--- a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
@@ -453,8 +453,8 @@ define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_2(<vscale x 4 x i1> %v, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: srli a1, a0, 3
diff --git a/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
index 1ac2ee1234d78..d3c3349919ec9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
@@ -52,14 +52,14 @@ define <vscale x 16 x i64> @llrint_nxv16i64_nxv16f32(<vscale x 16 x float> %x, <
; CHECK-LABEL: llrint_nxv16i64_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: srli a3, a1, 3
+; CHECK-NEXT: srli a2, a1, 3
+; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma
; CHECK-NEXT: vfwcvt.x.f.v v16, v12, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB4_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
index a7bd1d379eb43..e672a3a554962 100644
--- a/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
@@ -114,14 +114,14 @@ define <vscale x 16 x iXLen> @lrint_nxv16f32(<vscale x 16 x float> %x, <vscale x
; RV64-i64-LABEL: lrint_nxv16f32:
; RV64-i64: # %bb.0:
; RV64-i64-NEXT: csrr a1, vlenb
-; RV64-i64-NEXT: sub a2, a0, a1
-; RV64-i64-NEXT: sltu a3, a0, a2
-; RV64-i64-NEXT: addi a3, a3, -1
-; RV64-i64-NEXT: and a2, a3, a2
-; RV64-i64-NEXT: srli a3, a1, 3
+; RV64-i64-NEXT: srli a2, a1, 3
+; RV64-i64-NEXT: sub a3, a0, a1
; RV64-i64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; RV64-i64-NEXT: vmv1r.v v24, v0
-; RV64-i64-NEXT: vslidedown.vx v0, v0, a3
+; RV64-i64-NEXT: vslidedown.vx v0, v0, a2
+; RV64-i64-NEXT: sltu a2, a0, a3
+; RV64-i64-NEXT: addi a2, a2, -1
+; RV64-i64-NEXT: and a2, a2, a3
; RV64-i64-NEXT: vsetvli zero, a2, e32, m4, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v16, v12, v0.t
; RV64-i64-NEXT: bltu a0, a1, .LBB4_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
index 792426e96dceb..75b8aa515a717 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
@@ -2284,16 +2284,16 @@ define <vscale x 32 x i8> @mgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8>
; RV64-NEXT: vluxei64.v v13, (a0), v16, v0.t
; RV64-NEXT: srli a1, a1, 2
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vslidedown.vx v8, v8, a1
+; RV64-NEXT: vslidedown.vx v9, v8, a1
+; RV64-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vx v0, v9, a2
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v11
-; RV64-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v0, v8, a2
-; RV64-NEXT: vsetvli a1, zero, e8, m1, ta, mu
+; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v15, (a0), v16, v0.t
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v10
-; RV64-NEXT: vmv1r.v v0, v8
+; RV64-NEXT: vmv1r.v v0, v9
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v14, (a0), v16, v0.t
; RV64-NEXT: vmv4r.v v8, v12
diff --git a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
index a7afdcc817343..639a91535f191 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
@@ -1951,8 +1951,8 @@ define void @mscatter_baseidx_zext_nxv1i1_nxv1i8(<vscale x 1 x i8> %val, ptr %ba
; CHECK-LABEL: mscatter_baseidx_zext_nxv1i1_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v11, 0
-; CHECK-NEXT: vmerge.vim v10, v11, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vsoxei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
index 4e69a2623339d..f7b68ce1f64b8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
@@ -17,10 +17,10 @@ define <vscale x 1 x bfloat> @vp_nearbyint_nxv1bf16(<vscale x 1 x bfloat> %va, <
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
@@ -67,10 +67,10 @@ define <vscale x 2 x bfloat> @vp_nearbyint_nxv2bf16(<vscale x 2 x bfloat> %va, <
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
@@ -296,12 +296,12 @@ define <vscale x 32 x bfloat> @vp_nearbyint_nxv32bf16(<vscale x 32 x bfloat> %va
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
+; CHECK-NEXT: fsflags a2
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
-; CHECK-NEXT: fsflags a2
; CHECK-NEXT: bltu a0, a1, .LBB10_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -359,12 +359,12 @@ define <vscale x 32 x bfloat> @vp_nearbyint_nxv32bf16_unmasked(<vscale x 32 x bf
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
+; CHECK-NEXT: fsflags a2
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
-; CHECK-NEXT: fsflags a2
; CHECK-NEXT: bltu a0, a1, .LBB11_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -410,10 +410,10 @@ define <vscale x 1 x half> @vp_nearbyint_nxv1f16(<vscale x 1 x half> %va, <vscal
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
@@ -494,10 +494,10 @@ define <vscale x 2 x half> @vp_nearbyint_nxv2f16(<vscale x 2 x half> %va, <vscal
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
@@ -865,12 +865,12 @@ define <vscale x 32 x half> @vp_nearbyint_nxv32f16(<vscale x 32 x half> %va, <vs
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
+; ZVFHMIN-NEXT: fsflags a2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
-; ZVFHMIN-NEXT: fsflags a2
; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
@@ -944,12 +944,12 @@ define <vscale x 32 x half> @vp_nearbyint_nxv32f16_unmasked(<vscale x 32 x half>
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
+; ZVFHMIN-NEXT: fsflags a2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
-; ZVFHMIN-NEXT: fsflags a2
; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr165232.ll b/llvm/test/CodeGen/RISCV/rvv/pr165232.ll
index 9c4c293d599b4..39a1b3b6e4559 100644
--- a/llvm/test/CodeGen/RISCV/rvv/pr165232.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/pr165232.ll
@@ -12,183 +12,254 @@ define i1 @main(ptr %var_117, ptr %arrayinit.element3045, ptr %arrayinit.element
; CHECK-NEXT: csrr t0, vlenb
; CHECK-NEXT: slli t0, t0, 1
; CHECK-NEXT: mv t1, t0
-; CHECK-NEXT: slli t0, t0, 3
-; CHECK-NEXT: add t0, t0, t1
-; CHECK-NEXT: sub sp, sp, t0
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x12, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 18 * vlenb
-; CHECK-NEXT: csrr t0, vlenb
-; CHECK-NEXT: slli t0, t0, 1
-; CHECK-NEXT: mv t1, t0
; CHECK-NEXT: slli t0, t0, 2
-; CHECK-NEXT: add t0, t0, t1
-; CHECK-NEXT: add t0, sp, t0
-; CHECK-NEXT: addi t0, t0, 16
-; CHECK-NEXT: vs4r.v v12, (t0) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: csrr t1, vlenb
-; CHECK-NEXT: slli t1, t1, 2
-; CHECK-NEXT: add t0, t0, t1
-; CHECK-NEXT: vs4r.v v16, (t0) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: csrr t0, vlenb
-; CHECK-NEXT: slli t0, t0, 1
-; CHECK-NEXT: mv t1, t0
+; CHECK-NEXT: add t1, t1, t0
; CHECK-NEXT: slli t0, t0, 1
; CHECK-NEXT: add t0, t0, t1
-; CHECK-NEXT: add t0, sp, t0
-; CHECK-NEXT: addi t0, t0, 16
-; CHECK-NEXT: vs4r.v v8, (t0) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: csrr t0, vlenb
-; CHECK-NEXT: slli t0, t0, 1
-; CHECK-NEXT: mv t1, t0
-; CHECK-NEXT: slli t0, t0, 3
-; CHECK-NEXT: add t0, t0, t1
-; CHECK-NEXT: add t0, sp, t0
-; CHECK-NEXT: ld t0, 56(t0)
-; CHECK-NEXT: csrr t1, vlenb
-; CHECK-NEXT: slli t1, t1, 1
-; CHECK-NEXT: mv t2, t1
-; CHECK-NEXT: slli t1, t1, 3
-; CHECK-NEXT: add t1, t1, t2
-; CHECK-NEXT: add t1, sp, t1
-; CHECK-NEXT: ld t1, 48(t1)
+; CHECK-NEXT: sub sp, sp, t0
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
+; CHECK-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd a2, 0(sp) # 8-byte Folded Spill
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: ld t0, 56(a1)
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: ld t1, 48(a1)
; CHECK-NEXT: vsetvli t2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v13, 0
-; CHECK-NEXT: csrr t2, vlenb
-; CHECK-NEXT: slli t2, t2, 1
-; CHECK-NEXT: mv t3, t2
-; CHECK-NEXT: slli t2, t2, 3
-; CHECK-NEXT: add t2, t2, t3
-; CHECK-NEXT: add t2, sp, t2
-; CHECK-NEXT: ld t2, 40(t2)
-; CHECK-NEXT: # kill: def $v14 killed $v13 killed $vtype
-; CHECK-NEXT: csrr t3, vlenb
-; CHECK-NEXT: slli t3, t3, 1
-; CHECK-NEXT: mv t4, t3
-; CHECK-NEXT: slli t3, t3, 3
-; CHECK-NEXT: add t3, t3, t4
-; CHECK-NEXT: add t3, sp, t3
-; CHECK-NEXT: ld t3, 32(t3)
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: ld t2, 40(a1)
+; CHECK-NEXT: # kill: def $v13 killed $v12 killed $vtype
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: ld t3, 32(a1)
+; CHECK-NEXT: vmv.v.i v14, 0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: ld t4, 16(a1)
; CHECK-NEXT: vmv.v.i v15, 0
-; CHECK-NEXT: csrr t4, vlenb
-; CHECK-NEXT: slli t4, t4, 1
-; CHECK-NEXT: mv t5, t4
-; CHECK-NEXT: slli t4, t4, 3
-; CHECK-NEXT: add t4, t4, t5
-; CHECK-NEXT: add t4, sp, t4
-; CHECK-NEXT: ld t4, 16(t4)
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 2
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: ld t5, 24(a1)
; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: csrr t5, vlenb
-; CHECK-NEXT: slli t5, t5, 1
-; CHECK-NEXT: mv t6, t5
-; CHECK-NEXT: slli t5, t5, 3
-; CHECK-NEXT: add t5, t5, t6
-; CHECK-NEXT: add t5, sp, t5
-; CHECK-NEXT: ld t5, 24(t5)
-; CHECK-NEXT: vmv.v.i v17, 0
; CHECK-NEXT: vsetvli t6, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v20, 0
-; CHECK-NEXT: vmv1r.v v18, v13
+; CHECK-NEXT: vmv1r.v v17, v12
; CHECK-NEXT: sd zero, 0(a0)
; CHECK-NEXT: vmv.v.i v22, 0
-; CHECK-NEXT: vmv1r.v v19, v13
-; CHECK-NEXT: vmv1r.v v8, v13
+; CHECK-NEXT: vmv1r.v v18, v12
+; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: li t6, 1023
; CHECK-NEXT: vmv.v.i v24, 0
-; CHECK-NEXT: vmv1r.v v9, v13
+; CHECK-NEXT: vmv1r.v v9, v12
; CHECK-NEXT: slli t6, t6, 52
; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmv1r.v v10, v13
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vs4r.v v20, (a1) # vscale x 32-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: ld a2, 0(sp) # 8-byte Folded Reload
+; CHECK-NEXT: vs4r.v v24, (a1) # vscale x 32-byte Folded Spill
+; CHECK-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v10, v12
; CHECK-NEXT: sd t6, 0(t5)
-; CHECK-NEXT: vmv1r.v v11, v13
+; CHECK-NEXT: vmv1r.v v19, v12
+; CHECK-NEXT: vmv1r.v v20, v13
+; CHECK-NEXT: vmv1r.v v21, v14
+; CHECK-NEXT: vmv1r.v v22, v15
+; CHECK-NEXT: vmv1r.v v23, v16
+; CHECK-NEXT: vmv1r.v v24, v17
+; CHECK-NEXT: vmv1r.v v25, v18
+; CHECK-NEXT: vmv1r.v v11, v12
; CHECK-NEXT: csrr t5, vlenb
; CHECK-NEXT: slli t5, t5, 1
+; CHECK-NEXT: mv t6, t5
+; CHECK-NEXT: slli t5, t5, 2
+; CHECK-NEXT: add t5, t5, t6
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
; CHECK-NEXT: vs4r.v v8, (t5) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 0, e64, m2, ta, ma
; CHECK-NEXT: vmclr.m v8
-; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: csrr t5, vlenb
+; CHECK-NEXT: slli t6, t5, 3
+; CHECK-NEXT: add t5, t6, t5
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
; CHECK-NEXT: vs1r.v v8, (t5) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: addi t5, sp, 16
+; CHECK-NEXT: csrr t5, vlenb
+; CHECK-NEXT: slli t5, t5, 3
+; CHECK-NEXT: add t5, sp, t5
+; CHECK-NEXT: addi t5, t5, 16
; CHECK-NEXT: vs1r.v v8, (t5) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: .LBB0_1: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v6, 0
-; CHECK-NEXT: vmv.v.i v28, 0
-; CHECK-NEXT: vmv1r.v v30, v9
-; CHECK-NEXT: vmv1r.v v12, v9
-; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, ma
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmv.v.i v30, 0
+; CHECK-NEXT: vmv.v.i v31, 0
+; CHECK-NEXT: vmv.v.i v13, 0
+; CHECK-NEXT: vmv.v.i v26, 0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmv.v.i v11, 0
+; CHECK-NEXT: vmv.v.i v18, 0
+; CHECK-NEXT: vmv2r.v v0, v18
+; CHECK-NEXT: vmv2r.v v2, v20
+; CHECK-NEXT: vmv2r.v v4, v22
+; CHECK-NEXT: vmv2r.v v6, v24
+; CHECK-NEXT: vmv2r.v v14, v16
+; CHECK-NEXT: vmv2r.v v28, v16
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: csrr t5, vlenb
+; CHECK-NEXT: slli t6, t5, 3
+; CHECK-NEXT: add t5, t6, t5
+; CHECK-NEXT: add t5, sp, t5
+; CHECK-NEXT: addi t5, t5, 16
+; CHECK-NEXT: vl1r.v v8, (t5) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
+; CHECK-NEXT: vle32.v v30, (t4)
+; CHECK-NEXT: vle32.v v31, (t1)
+; CHECK-NEXT: vle32.v v11, (a7)
; CHECK-NEXT: vle64.v v28, (a4)
-; CHECK-NEXT: vle32.v v30, (a2)
-; CHECK-NEXT: vle32.v v12, (a3)
+; CHECK-NEXT: vle32.v v13, (t2)
+; CHECK-NEXT: vle32.v v26, (t3)
+; CHECK-NEXT: vle32.v v10, (a6)
+; CHECK-NEXT: vmv1r.v v2, v11
; CHECK-NEXT: csrr t5, vlenb
+; CHECK-NEXT: slli t5, t5, 3
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
-; CHECK-NEXT: vl1r.v v10, (t5) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vl1r.v v0, (t5) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v10, v28, v6, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu
-; CHECK-NEXT: vssub.vv v12, v9, v30, v0.t
+; CHECK-NEXT: vmflt.vv v8, v28, v16, v0.t
+; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: vmv1r.v v11, v9
-; CHECK-NEXT: vmv1r.v v28, v9
-; CHECK-NEXT: vmv1r.v v29, v9
-; CHECK-NEXT: vmv1r.v v30, v9
-; CHECK-NEXT: vmv1r.v v31, v9
-; CHECK-NEXT: vle32.v v10, (t4)
-; CHECK-NEXT: vle32.v v31, (a7)
-; CHECK-NEXT: vle32.v v11, (t1)
-; CHECK-NEXT: vle32.v v28, (t2)
-; CHECK-NEXT: vle32.v v29, (t3)
-; CHECK-NEXT: vmv1r.v v2, v13
-; CHECK-NEXT: vmv1r.v v4, v15
-; CHECK-NEXT: vmv1r.v v5, v16
-; CHECK-NEXT: vmv1r.v v6, v17
-; CHECK-NEXT: vmv1r.v v7, v18
-; CHECK-NEXT: vmv1r.v v8, v19
-; CHECK-NEXT: vle32.v v30, (a6)
-; CHECK-NEXT: vmv1r.v v3, v31
-; CHECK-NEXT: vmv1r.v v11, v9
-; CHECK-NEXT: vle32.v v11, (a5)
-; CHECK-NEXT: vmv1r.v v1, v10
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu
+; CHECK-NEXT: vle32.v v12, (a2)
+; CHECK-NEXT: vle32.v v10, (a3)
+; CHECK-NEXT: vle32.v v18, (a5)
+; CHECK-NEXT: vmv1r.v v0, v30
; CHECK-NEXT: csrr t5, vlenb
; CHECK-NEXT: slli t5, t5, 1
+; CHECK-NEXT: mv t6, t5
+; CHECK-NEXT: slli t5, t5, 2
+; CHECK-NEXT: add t5, t5, t6
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
; CHECK-NEXT: vl4r.v v28, (t5) # vscale x 32-byte Folded Reload
; CHECK-NEXT: vsseg4e32.v v28, (zero)
-; CHECK-NEXT: vsseg8e32.v v1, (a1)
+; CHECK-NEXT: vsseg8e32.v v0, (a1)
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vssub.vv v10, v9, v12, v0.t
; CHECK-NEXT: csrr t5, vlenb
; CHECK-NEXT: slli t5, t5, 1
; CHECK-NEXT: mv t6, t5
; CHECK-NEXT: slli t5, t5, 1
+; CHECK-NEXT: add t6, t6, t5
+; CHECK-NEXT: slli t5, t5, 1
; CHECK-NEXT: add t5, t5, t6
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
-; CHECK-NEXT: vl4r.v v28, (t5) # vscale x 32-byte Folded Reload
+; CHECK-NEXT: vl2r.v v2, (t5) # vscale x 16-byte Folded Reload
+; CHECK-NEXT: csrr t6, vlenb
+; CHECK-NEXT: slli t6, t6, 1
+; CHECK-NEXT: add t5, t5, t6
+; CHECK-NEXT: vl2r.v v4, (t5) # vscale x 16-byte Folded Reload
; CHECK-NEXT: vsetvli zero, t0, e64, m2, ta, ma
-; CHECK-NEXT: vsseg2e64.v v28, (zero)
+; CHECK-NEXT: vsseg2e64.v v2, (zero)
; CHECK-NEXT: addi t5, sp, 16
-; CHECK-NEXT: vl1r.v v0, (t5) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vl2r.v v2, (t5) # vscale x 16-byte Folded Reload
+; CHECK-NEXT: csrr t6, vlenb
+; CHECK-NEXT: slli t6, t6, 1
+; CHECK-NEXT: add t5, t5, t6
+; CHECK-NEXT: vl4r.v v4, (t5) # vscale x 32-byte Folded Reload
+; CHECK-NEXT: slli t6, t6, 1
+; CHECK-NEXT: add t5, t5, t6
+; CHECK-NEXT: vl2r.v v8, (t5) # vscale x 16-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vsetivli zero, 0, e64, m2, ta, ma
-; CHECK-NEXT: vsseg4e64.v v20, (zero), v0.t
+; CHECK-NEXT: vsseg4e64.v v2, (zero), v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vsseg8e32.v v12, (a0)
+; CHECK-NEXT: vsseg8e32.v v10, (a0)
; CHECK-NEXT: csrr t5, vlenb
; CHECK-NEXT: slli t5, t5, 1
; CHECK-NEXT: mv t6, t5
-; CHECK-NEXT: slli t5, t5, 2
+; CHECK-NEXT: slli t5, t5, 3
; CHECK-NEXT: add t5, t5, t6
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
-; CHECK-NEXT: vl8r.v v0, (t5) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl2r.v v2, (t5) # vscale x 16-byte Folded Reload
+; CHECK-NEXT: csrr t6, vlenb
+; CHECK-NEXT: slli t6, t6, 1
+; CHECK-NEXT: add t5, t5, t6
+; CHECK-NEXT: vl4r.v v4, (t5) # vscale x 32-byte Folded Reload
+; CHECK-NEXT: slli t6, t6, 1
+; CHECK-NEXT: add t5, t5, t6
+; CHECK-NEXT: vl2r.v v8, (t5) # vscale x 16-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; CHECK-NEXT: vsseg4e64.v v0, (zero)
+; CHECK-NEXT: vsseg4e64.v v2, (zero)
; CHECK-NEXT: j .LBB0_1
entry:
store double 0.000000e+00, ptr %var_117, align 8
diff --git a/llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll b/llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
index b66ef6511a823..bfff09bc35c8e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
@@ -19,12 +19,11 @@ define i32 @_ZN4Mesh12rezone_countESt6vectorIiSaIiEERiS3_(<vscale x 4 x i32> %wi
; CHECK-NEXT: vmv2r.v v14, v8
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vle32.v v14, (a0), v0.t
+; CHECK-NEXT: vor.vi v12, v12, 1, v0.t
; CHECK-NEXT: vand.vi v14, v14, 1
; CHECK-NEXT: vmsne.vi v16, v14, 0
; CHECK-NEXT: vmand.mm v0, v17, v16
; CHECK-NEXT: vmerge.vim v10, v10, -1, v0
-; CHECK-NEXT: vmv1r.v v0, v17
-; CHECK-NEXT: vor.vi v12, v12, 1, v0.t
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: j .LBB0_1
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll
index 7c6074d2dcf5b..c5a3b2252de19 100644
--- a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll
@@ -17,12 +17,12 @@ define <vscale x 1 x bfloat> @vp_round_nxv1bf16(<vscale x 1 x bfloat> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -67,12 +67,12 @@ define <vscale x 2 x bfloat> @vp_round_nxv2bf16(<vscale x 2 x bfloat> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
@@ -410,12 +410,12 @@ define <vscale x 1 x half> @vp_round_nxv1f16(<vscale x 1 x half> %va, <vscale x
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -494,12 +494,12 @@ define <vscale x 2 x half> @vp_round_nxv2f16(<vscale x 2 x half> %va, <vscale x
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll b/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
index 40a4642d51979..443909ba2cc25 100644
--- a/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
@@ -17,12 +17,12 @@ define <vscale x 1 x bfloat> @vp_roundeven_nxv1bf16(<vscale x 1 x bfloat> %va, <
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -67,12 +67,12 @@ define <vscale x 2 x bfloat> @vp_roundeven_nxv2bf16(<vscale x 2 x bfloat> %va, <
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
@@ -410,12 +410,12 @@ define <vscale x 1 x half> @vp_roundeven_nxv1f16(<vscale x 1 x half> %va, <vscal
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -494,12 +494,12 @@ define <vscale x 2 x half> @vp_roundeven_nxv2f16(<vscale x 2 x half> %va, <vscal
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
index 6238d57e7eea5..b81e2d7568ceb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
@@ -17,12 +17,12 @@ define <vscale x 1 x bfloat> @vp_roundtozero_nxv1bf16(<vscale x 1 x bfloat> %va,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -67,12 +67,12 @@ define <vscale x 2 x bfloat> @vp_roundtozero_nxv2bf16(<vscale x 2 x bfloat> %va,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
@@ -410,12 +410,12 @@ define <vscale x 1 x half> @vp_roundtozero_nxv1f16(<vscale x 1 x half> %va, <vsc
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -494,12 +494,12 @@ define <vscale x 2 x half> @vp_roundtozero_nxv2f16(<vscale x 2 x half> %va, <vsc
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
index 6ad291b37f313..7357260229c56 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
@@ -1381,6 +1381,17 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64bf16(<vscale x 64 x bfloat> %va, <vs
; CHECK-NEXT: and a7, a7, a1
; CHECK-NEXT: srli a1, a3, 1
; CHECK-NEXT: srli a3, a3, 2
+; CHECK-NEXT: csrr t0, vlenb
+; CHECK-NEXT: mv t1, t0
+; CHECK-NEXT: slli t0, t0, 3
+; CHECK-NEXT: add t1, t1, t0
+; CHECK-NEXT: slli t0, t0, 2
+; CHECK-NEXT: add t0, t0, t1
+; CHECK-NEXT: add t0, sp, t0
+; CHECK-NEXT: addi t0, t0, 16
+; CHECK-NEXT: vl1r.v v8, (t0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli t0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v6, v8, a1
; CHECK-NEXT: vl8re16.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: mv t0, a0
@@ -1407,21 +1418,9 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64bf16(<vscale x 64 x bfloat> %va, <vs
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20
-; CHECK-NEXT: vmv8r.v v16, v8
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: mv t0, a0
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add t0, t0, a0
-; CHECK-NEXT: slli a0, a0, 2
-; CHECK-NEXT: add a0, a0, t0
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v28, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v28, v28, a1
-; CHECK-NEXT: vmv.v.v v7, v28
+; CHECK-NEXT: vmv1r.v v7, v6
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v28, a3
+; CHECK-NEXT: vslidedown.vx v0, v6, a3
; CHECK-NEXT: bltu a6, a4, .LBB85_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a6, a4
@@ -1430,10 +1429,9 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64bf16(<vscale x 64 x bfloat> %va, <vs
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmv8r.v v24, v16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a7, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v16, v24, v8, v0.t
+; CHECK-NEXT: vmfeq.vv v16, v8, v24, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
@@ -3577,6 +3575,17 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFHMIN-NEXT: and a7, a7, a1
; ZVFHMIN-NEXT: srli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
+; ZVFHMIN-NEXT: csrr t0, vlenb
+; ZVFHMIN-NEXT: mv t1, t0
+; ZVFHMIN-NEXT: slli t0, t0, 3
+; ZVFHMIN-NEXT: add t1, t1, t0
+; ZVFHMIN-NEXT: slli t0, t0, 2
+; ZVFHMIN-NEXT: add t0, t0, t1
+; ZVFHMIN-NEXT: add t0, sp, t0
+; ZVFHMIN-NEXT: addi t0, t0, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (t0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli t0, zero, e8, m1, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v6, v8, a1
; ZVFHMIN-NEXT: vl8re16.v v8, (a0)
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: mv t0, a0
@@ -3603,21 +3612,9 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20
-; ZVFHMIN-NEXT: vmv8r.v v16, v8
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: mv t0, a0
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: add t0, t0, a0
-; ZVFHMIN-NEXT: slli a0, a0, 2
-; ZVFHMIN-NEXT: add a0, a0, t0
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl1r.v v28, (a0) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v28, v28, a1
-; ZVFHMIN-NEXT: vmv.v.v v7, v28
+; ZVFHMIN-NEXT: vmv1r.v v7, v6
; ZVFHMIN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v28, a3
+; ZVFHMIN-NEXT: vslidedown.vx v0, v6, a3
; ZVFHMIN-NEXT: bltu a6, a4, .LBB171_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a6, a4
@@ -3626,10 +3623,9 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a7, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v16, v8, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
@@ -4874,10 +4870,10 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK32-NEXT: vl8re64.v v8, (a2)
; CHECK32-NEXT: slli a5, s0, 4
; CHECK32-NEXT: slli a2, s0, 1
-; CHECK32-NEXT: mv a3, s1
; CHECK32-NEXT: vmv1r.v v7, v16
-; CHECK32-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
+; CHECK32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; CHECK32-NEXT: vslidedown.vx v0, v16, a0
+; CHECK32-NEXT: mv a3, s1
; CHECK32-NEXT: bltu s1, a2, .LBB257_2
; CHECK32-NEXT: # %bb.1:
; CHECK32-NEXT: mv a3, a2
@@ -5085,10 +5081,10 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK64-NEXT: vl8re64.v v8, (a2)
; CHECK64-NEXT: slli a5, s0, 4
; CHECK64-NEXT: slli a2, s0, 1
-; CHECK64-NEXT: mv a3, s1
; CHECK64-NEXT: vmv1r.v v7, v16
-; CHECK64-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
+; CHECK64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; CHECK64-NEXT: vslidedown.vx v0, v16, a0
+; CHECK64-NEXT: mv a3, s1
; CHECK64-NEXT: bltu s1, a2, .LBB257_2
; CHECK64-NEXT: # %bb.1:
; CHECK64-NEXT: mv a3, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
index 2dd99a820b8d3..5de9b5550035f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
@@ -1078,16 +1078,16 @@ define <vscale x 128 x i1> @icmp_eq_vv_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a4, a0, a1
-; CHECK-NEXT: sub a5, a3, a1
-; CHECK-NEXT: vl8r.v v24, (a4)
-; CHECK-NEXT: sltu a4, a3, a5
; CHECK-NEXT: vlm.v v0, (a2)
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: sub a4, a3, a1
+; CHECK-NEXT: vl8r.v v24, (a2)
+; CHECK-NEXT: sltu a2, a3, a4
; CHECK-NEXT: vl8r.v v8, (a0)
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a4, a4, a5
-; CHECK-NEXT: vsetvli zero, a4, e8, m8, ta, ma
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a4
+; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vv v7, v16, v24, v0.t
; CHECK-NEXT: bltu a3, a1, .LBB96_2
; CHECK-NEXT: # %bb.1:
@@ -1116,18 +1116,18 @@ define <vscale x 128 x i1> @icmp_eq_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: sltu a1, a2, a4
-; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a1, a1, a4
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: sub a3, a2, a1
+; CHECK-NEXT: sltu a4, a2, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
-; CHECK-NEXT: bltu a2, a3, .LBB97_2
+; CHECK-NEXT: bltu a2, a1, .LBB97_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a3
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB97_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -1146,18 +1146,18 @@ define <vscale x 128 x i1> @icmp_eq_vx_swap_nxv128i8(<vscale x 128 x i8> %va, i8
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: sltu a1, a2, a4
-; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a1, a1, a4
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: sub a3, a2, a1
+; CHECK-NEXT: sltu a4, a2, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
-; CHECK-NEXT: bltu a2, a3, .LBB98_2
+; CHECK-NEXT: bltu a2, a1, .LBB98_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a3
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB98_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -2250,13 +2250,13 @@ define <vscale x 32 x i1> @icmp_eq_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b,
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: srli a2, a3, 2
; CHECK-NEXT: slli a3, a3, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a4, a1, a3
; CHECK-NEXT: sltu a5, a1, a4
; CHECK-NEXT: addi a5, a5, -1
; CHECK-NEXT: and a4, a5, a4
-; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a3, .LBB190_2
@@ -2282,13 +2282,13 @@ define <vscale x 32 x i1> @icmp_eq_vx_swap_nxv32i32(<vscale x 32 x i32> %va, i32
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: srli a2, a3, 2
; CHECK-NEXT: slli a3, a3, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a4, a1, a3
; CHECK-NEXT: sltu a5, a1, a4
; CHECK-NEXT: addi a5, a5, -1
; CHECK-NEXT: and a4, a5, a4
-; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a3, .LBB191_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll b/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
index 8f519a1d5f7b1..16f373e148bbf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
@@ -709,12 +709,12 @@ define <vscale x 16 x double> @strided_load_nxv17f64(ptr %ptr, i64 %stride, <vsc
; CHECK-RV32-NEXT: .LBB57_4:
; CHECK-RV32-NEXT: mul t1, a5, a1
; CHECK-RV32-NEXT: srli t2, a2, 3
+; CHECK-RV32-NEXT: sub a7, a3, a7
; CHECK-RV32-NEXT: add t1, a0, t1
; CHECK-RV32-NEXT: vsetvli t3, zero, e8, mf4, ta, ma
; CHECK-RV32-NEXT: vslidedown.vx v0, v9, t2
; CHECK-RV32-NEXT: vsetvli zero, t0, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v16, (t1), a1, v0.t
-; CHECK-RV32-NEXT: sub a7, a3, a7
; CHECK-RV32-NEXT: sltu a3, a3, a7
; CHECK-RV32-NEXT: addi a3, a3, -1
; CHECK-RV32-NEXT: and a3, a3, a7
@@ -757,12 +757,12 @@ define <vscale x 16 x double> @strided_load_nxv17f64(ptr %ptr, i64 %stride, <vsc
; CHECK-RV64-NEXT: .LBB57_4:
; CHECK-RV64-NEXT: mul t1, a5, a1
; CHECK-RV64-NEXT: srli t2, a4, 3
+; CHECK-RV64-NEXT: sub a7, a2, a7
; CHECK-RV64-NEXT: add t1, a0, t1
; CHECK-RV64-NEXT: vsetvli t3, zero, e8, mf4, ta, ma
; CHECK-RV64-NEXT: vslidedown.vx v0, v9, t2
; CHECK-RV64-NEXT: vsetvli zero, t0, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v16, (t1), a1, v0.t
-; CHECK-RV64-NEXT: sub a7, a2, a7
; CHECK-RV64-NEXT: sltu a2, a2, a7
; CHECK-RV64-NEXT: addi a2, a2, -1
; CHECK-RV64-NEXT: and a2, a2, a7
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
index eda4c53e32478..f850fb822507c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
@@ -547,18 +547,18 @@ define <vscale x 128 x i8> @vadd_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: sltu a0, a1, a3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a3
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: sub a2, a1, a0
+; CHECK-NEXT: sltu a3, a1, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t
-; CHECK-NEXT: bltu a1, a2, .LBB50_2
+; CHECK-NEXT: bltu a1, a0, .LBB50_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
@@ -1299,17 +1299,17 @@ define <vscale x 16 x i32> @vadd_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va, i
define <vscale x 32 x i32> @vadd_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vadd_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a1, a2, 1
-; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: srli a2, a2, 2
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB118_2
; CHECK-NEXT: # %bb.1:
@@ -1368,15 +1368,15 @@ define <vscale x 32 x i32> @vadd_vi_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, <v
; RV64-LABEL: vadd_vi_nxv32i32_evl_nx8:
; RV64: # %bb.0:
; RV64-NEXT: csrr a0, vlenb
+; RV64-NEXT: srli a2, a0, 2
; RV64-NEXT: slli a1, a0, 1
+; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a2
; RV64-NEXT: sub a2, a0, a1
; RV64-NEXT: sltu a3, a0, a2
; RV64-NEXT: addi a3, a3, -1
; RV64-NEXT: and a2, a3, a2
-; RV64-NEXT: srli a3, a0, 2
-; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
-; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV64-NEXT: vadd.vi v16, v16, -1, v0.t
; RV64-NEXT: bltu a0, a1, .LBB120_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
index 69574cc56742b..93a626e355a6b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
@@ -101,13 +101,16 @@ define {<4 x i64>, <4 x i64>} @vector_deinterleave_v4i64_v8i64(<8 x i64> %vec) {
; V-NEXT: vmv.v.i v0, 8
; V-NEXT: vsetivli zero, 4, e64, m4, ta, ma
; V-NEXT: vslidedown.vi v12, v8, 4
+; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; V-NEXT: vmv.v.i v17, 2
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; V-NEXT: vslideup.vi v10, v12, 2
; V-NEXT: vslideup.vi v10, v12, 1, v0.t
; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; V-NEXT: vmv.v.i v0, 2
+; V-NEXT: vmv.v.i v18, 12
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; V-NEXT: vslidedown.vi v14, v8, 1
+; V-NEXT: vmv1r.v v0, v17
; V-NEXT: vslidedown.vi v14, v8, 2, v0.t
; V-NEXT: vslidedown.vi v8, v8, 1, v0.t
; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
@@ -115,9 +118,7 @@ define {<4 x i64>, <4 x i64>} @vector_deinterleave_v4i64_v8i64(<8 x i64> %vec) {
; V-NEXT: vmv2r.v v16, v12
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; V-NEXT: vslideup.vi v16, v12, 1, v0.t
-; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; V-NEXT: vmv.v.i v0, 12
-; V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; V-NEXT: vmv1r.v v0, v18
; V-NEXT: vmerge.vvm v8, v8, v10, v0
; V-NEXT: vmerge.vvm v10, v14, v16, v0
; V-NEXT: ret
@@ -482,13 +483,16 @@ define {<4 x double>, <4 x double>} @vector_deinterleave_v4f64_v8f64(<8 x double
; V-NEXT: vmv.v.i v0, 8
; V-NEXT: vsetivli zero, 4, e64, m4, ta, ma
; V-NEXT: vslidedown.vi v12, v8, 4
+; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; V-NEXT: vmv.v.i v17, 2
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; V-NEXT: vslideup.vi v10, v12, 2
; V-NEXT: vslideup.vi v10, v12, 1, v0.t
; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; V-NEXT: vmv.v.i v0, 2
+; V-NEXT: vmv.v.i v18, 12
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; V-NEXT: vslidedown.vi v14, v8, 1
+; V-NEXT: vmv1r.v v0, v17
; V-NEXT: vslidedown.vi v14, v8, 2, v0.t
; V-NEXT: vslidedown.vi v8, v8, 1, v0.t
; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
@@ -496,9 +500,7 @@ define {<4 x double>, <4 x double>} @vector_deinterleave_v4f64_v8f64(<8 x double
; V-NEXT: vmv2r.v v16, v12
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; V-NEXT: vslideup.vi v16, v12, 1, v0.t
-; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; V-NEXT: vmv.v.i v0, 12
-; V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; V-NEXT: vmv1r.v v0, v18
; V-NEXT: vmerge.vvm v8, v8, v10, v0
; V-NEXT: vmerge.vvm v10, v14, v16, v0
; V-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
index afe18a9581ea5..6b23ac6998e5e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
@@ -188,8 +188,8 @@ define {<vscale x 64 x i1>, <vscale x 64 x i1>} @vector_deinterleave_nxv64i1_nxv
; ZIP: # %bb.0:
; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZIP-NEXT: vmv1r.v v24, v0
-; ZIP-NEXT: vmv1r.v v0, v8
; ZIP-NEXT: vmv.v.i v16, 0
+; ZIP-NEXT: vmv1r.v v0, v8
; ZIP-NEXT: vmerge.vim v8, v16, 1, v0
; ZIP-NEXT: vmv1r.v v0, v24
; ZIP-NEXT: vmerge.vim v24, v16, 1, v0
@@ -357,18 +357,19 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} @vector_dein
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v8, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v14, v0
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a1
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v10, v12, 1, v0
+; CHECK-NEXT: vslidedown.vx v10, v0, a1
; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v8, v12, 1, v0
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v14, a0
+; CHECK-NEXT: vslidedown.vx v14, v0, a0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v10, v12, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: vlseg3e8.v v8, (a1)
@@ -475,30 +476,32 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v14, v10, 1, v0
+; CHECK-NEXT: vslidedown.vx v9, v0, a2
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmv.v.v v0, v9
+; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v14, v10, 1, v0
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v12, v10, 1, v0
-; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v16, v8, a1
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a1
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
-; CHECK-NEXT: vs8r.v v8, (a0)
-; CHECK-NEXT: vlseg4e8.v v8, (a0)
+; CHECK-NEXT: vs8r.v v8, (a2)
+; CHECK-NEXT: vlseg4e8.v v8, (a2)
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmsne.vi v8, v10, 0
; CHECK-NEXT: vmsne.vi v9, v12, 0
@@ -600,39 +603,36 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vmerge.vim v14, v12, 1, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v8, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v16, v0
+; CHECK-NEXT: vmerge.vim v24, v12, 1, v0
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a1
-; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v10, v12, 1, v0
-; CHECK-NEXT: sub a1, a0, a1
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v16, a1
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: srli a2, a0, 1
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vim v14, v12, 1, v0
+; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v10, a0
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v20, v12, 1, v0
-; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v16, a0
-; CHECK-NEXT: vmv1r.v v18, v21
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v10, a1
+; CHECK-NEXT: vslidedown.vx v8, v10, a2
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
+; CHECK-NEXT: vmerge.vim v26, v12, 1, v0
+; CHECK-NEXT: vmv1r.v v18, v21
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vim v28, v12, 1, v0
; CHECK-NEXT: vmv1r.v v19, v14
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vmv1r.v v16, v13
+; CHECK-NEXT: vmv1r.v v16, v29
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vmv1r.v v17, v20
-; CHECK-NEXT: vs8r.v v8, (a0)
+; CHECK-NEXT: vs8r.v v24, (a0)
; CHECK-NEXT: vmv1r.v v20, v15
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
@@ -835,7 +835,7 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: vmv.v.i v14, 0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vmerge.vim v24, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a1
@@ -843,30 +843,29 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: vmerge.vim v26, v14, 1, v0
; CHECK-NEXT: srli a2, a0, 1
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v9, a2
+; CHECK-NEXT: vslidedown.vx v0, v16, a2
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v28, v14, 1, v0
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vs8r.v v24, (a2)
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v18, v14, 1, v0
+; CHECK-NEXT: vmerge.vim v10, v14, 1, v0
; CHECK-NEXT: sub a0, a0, a1
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v9, a0
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v14, 1, v0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs8r.v v24, (a0)
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a1
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
-; CHECK-NEXT: vs8r.v v16, (a2)
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vlseg6e8.v v16, (a0)
-; CHECK-NEXT: vlseg6e8.v v10, (a2)
+; CHECK-NEXT: vslidedown.vx v12, v8, a1
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vslidedown.vx v0, v16, a0
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v8, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmerge.vim v12, v14, 1, v0
+; CHECK-NEXT: vs8r.v v8, (a1)
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vlseg6e8.v v16, (a2)
+; CHECK-NEXT: vlseg6e8.v v10, (a1)
; CHECK-NEXT: vmv2r.v v8, v16
; CHECK-NEXT: vmv2r.v v22, v18
; CHECK-NEXT: vmv2r.v v24, v20
@@ -1337,47 +1336,48 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vmv.v.i v18, 0
+; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: srli a0, a1, 2
; CHECK-NEXT: sub a2, a1, a0
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v30, v18, 1, v0
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a2
-; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v22, v18, 1, v0
+; CHECK-NEXT: vmerge.vim v30, v16, 1, v0
; CHECK-NEXT: srli a1, a1, 1
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v9, a1
-; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v28, v18, 1, v0
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a1
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v20, v18, 1, v0
+; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v28, v16, 1, v0
+; CHECK-NEXT: addi a3, sp, 16
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v24, v18, 1, v0
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
+; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v9, a0
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v26, v18, 1, v0
-; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vs8r.v v24, (a1)
+; CHECK-NEXT: vsetvli a4, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v26, v16, 1, v0
+; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v8, a2
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a3)
+; CHECK-NEXT: vsetvli a4, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v14, v16, 1, v0
+; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v8, a1
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v12, v16, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v16, v18, 1, v0
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a0
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v10, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v18, v18, 1, v0
-; CHECK-NEXT: vs8r.v v16, (a2)
+; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vim v10, v16, 1, v0
+; CHECK-NEXT: vs8r.v v8, (a2)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vlseg8e8.v v18, (a1)
+; CHECK-NEXT: vlseg8e8.v v18, (a3)
; CHECK-NEXT: vlseg8e8.v v10, (a2)
; CHECK-NEXT: vmv2r.v v8, v18
; CHECK-NEXT: vmv2r.v v26, v20
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
index c2d053b736305..fdf5a42f93502 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
@@ -10,13 +10,13 @@ define void @vector_interleave_store_nxv32i1_nxv16i1(<vscale x 16 x i1> %a, <vsc
; CHECK-LABEL: vector_interleave_store_nxv32i1_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v12, v8, 1, v0
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: li a1, -1
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmerge.vim v14, v8, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vim v12, v10, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vmerge.vim v14, v10, 1, v0
; CHECK-NEXT: vwaddu.vv v8, v14, v12
; CHECK-NEXT: vwmaccu.vx v8, a1, v12
; CHECK-NEXT: csrr a1, vlenb
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
index 84558183dbf64..dabdde5e64615 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
@@ -13,13 +13,13 @@ define <vscale x 32 x i1> @vector_interleave_nxv32i1_nxv16i1(<vscale x 16 x i1>
; V-LABEL: vector_interleave_nxv32i1_nxv16i1:
; V: # %bb.0:
; V-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; V-NEXT: vmv1r.v v10, v0
-; V-NEXT: vmv1r.v v0, v8
-; V-NEXT: vmv.v.i v8, 0
-; V-NEXT: vmerge.vim v12, v8, 1, v0
+; V-NEXT: vmv1r.v v9, v0
+; V-NEXT: vmv.v.i v10, 0
; V-NEXT: li a0, -1
-; V-NEXT: vmv1r.v v0, v10
-; V-NEXT: vmerge.vim v14, v8, 1, v0
+; V-NEXT: vmv1r.v v0, v8
+; V-NEXT: vmerge.vim v12, v10, 1, v0
+; V-NEXT: vmv1r.v v0, v9
+; V-NEXT: vmerge.vim v14, v10, 1, v0
; V-NEXT: vwaddu.vv v8, v14, v12
; V-NEXT: vwmaccu.vx v8, a0, v12
; V-NEXT: csrr a0, vlenb
@@ -34,10 +34,10 @@ define <vscale x 32 x i1> @vector_interleave_nxv32i1_nxv16i1(<vscale x 16 x i1>
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; ZVBB-NEXT: vmv1r.v v14, v0
-; ZVBB-NEXT: vmv1r.v v0, v8
-; ZVBB-NEXT: vmv.v.i v8, 0
-; ZVBB-NEXT: vmerge.vim v12, v8, 1, v0
+; ZVBB-NEXT: vmv.v.i v10, 0
; ZVBB-NEXT: li a0, 1
+; ZVBB-NEXT: vmv1r.v v0, v8
+; ZVBB-NEXT: vmerge.vim v12, v10, 1, v0
; ZVBB-NEXT: vwsll.vi v8, v12, 8
; ZVBB-NEXT: vmv1r.v v0, v14
; ZVBB-NEXT: vwaddu.wx v8, v8, a0, v0.t
@@ -52,13 +52,13 @@ define <vscale x 32 x i1> @vector_interleave_nxv32i1_nxv16i1(<vscale x 16 x i1>
; ZIP-LABEL: vector_interleave_nxv32i1_nxv16i1:
; ZIP: # %bb.0:
; ZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; ZIP-NEXT: vmv1r.v v12, v0
-; ZIP-NEXT: vmv1r.v v0, v8
-; ZIP-NEXT: vmv.v.i v8, 0
-; ZIP-NEXT: vmerge.vim v10, v8, 1, v0
+; ZIP-NEXT: vmv1r.v v9, v0
+; ZIP-NEXT: vmv.v.i v12, 0
; ZIP-NEXT: csrr a0, vlenb
-; ZIP-NEXT: vmv1r.v v0, v12
-; ZIP-NEXT: vmerge.vim v8, v8, 1, v0
+; ZIP-NEXT: vmv1r.v v0, v8
+; ZIP-NEXT: vmerge.vim v10, v12, 1, v0
+; ZIP-NEXT: vmv1r.v v0, v9
+; ZIP-NEXT: vmerge.vim v8, v12, 1, v0
; ZIP-NEXT: ri.vzip2b.vv v12, v8, v10
; ZIP-NEXT: ri.vzip2a.vv v14, v8, v10
; ZIP-NEXT: vmsne.vi v8, v12, 0
@@ -217,21 +217,21 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv64i1(<vscale x 64 x i1
; V: # %bb.0:
; V-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; V-NEXT: vmv1r.v v24, v0
-; V-NEXT: vmv1r.v v0, v8
; V-NEXT: vmv.v.i v16, 0
-; V-NEXT: vmerge.vim v8, v16, 1, v0
; V-NEXT: li a0, -1
+; V-NEXT: vmv1r.v v0, v8
+; V-NEXT: vmerge.vim v8, v16, 1, v0
; V-NEXT: vmv1r.v v0, v24
-; V-NEXT: vmerge.vim v24, v16, 1, v0
+; V-NEXT: vmerge.vim v16, v16, 1, v0
; V-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; V-NEXT: vwaddu.vv v16, v24, v8
-; V-NEXT: vwaddu.vv v0, v28, v12
-; V-NEXT: vwmaccu.vx v16, a0, v8
-; V-NEXT: vwmaccu.vx v0, a0, v12
+; V-NEXT: vwaddu.vv v24, v16, v8
+; V-NEXT: vmv4r.v v4, v20
+; V-NEXT: vwaddu.vv v16, v4, v12
+; V-NEXT: vwmaccu.vx v24, a0, v8
+; V-NEXT: vwmaccu.vx v16, a0, v12
; V-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; V-NEXT: vmsne.vi v9, v16, 0
-; V-NEXT: vmsne.vi v8, v0, 0
-; V-NEXT: vmv1r.v v0, v9
+; V-NEXT: vmsne.vi v0, v24, 0
+; V-NEXT: vmsne.vi v8, v16, 0
; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv128i1_nxv64i1:
@@ -257,8 +257,8 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv64i1(<vscale x 64 x i1
; ZIP: # %bb.0:
; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZIP-NEXT: vmv1r.v v24, v0
-; ZIP-NEXT: vmv1r.v v0, v8
; ZIP-NEXT: vmv.v.i v16, 0
+; ZIP-NEXT: vmv1r.v v0, v8
; ZIP-NEXT: vmerge.vim v8, v16, 1, v0
; ZIP-NEXT: vmv1r.v v0, v24
; ZIP-NEXT: vmerge.vim v16, v16, 1, v0
@@ -495,11 +495,11 @@ define <vscale x 48 x i1> @vector_interleave_nxv48i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmv.v.i v14, 0
; CHECK-NEXT: vmerge.vim v12, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmerge.vim v10, v14, 1, v0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a2, a1, 1
+; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vim v10, v14, 1, v0
; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmerge.vim v14, v14, 1, v0
@@ -536,11 +536,11 @@ define <vscale x 48 x i1> @vector_interleave_nxv48i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: vmv1r.v v0, v8
; ZVBB-NEXT: vmv.v.i v14, 0
; ZVBB-NEXT: vmerge.vim v12, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v10
-; ZVBB-NEXT: vmerge.vim v10, v14, 1, v0
; ZVBB-NEXT: addi a0, sp, 16
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: slli a2, a1, 1
+; ZVBB-NEXT: vmv1r.v v0, v10
+; ZVBB-NEXT: vmerge.vim v10, v14, 1, v0
; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vmv1r.v v0, v9
; ZVBB-NEXT: vmerge.vim v14, v14, 1, v0
@@ -794,12 +794,12 @@ define <vscale x 64 x i1> @vector_interleave_nxv64i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: vmerge.vim v14, v18, 1, v0
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmerge.vim v12, v18, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v16, v18, 1, v0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a2, a1, 1
; CHECK-NEXT: add a3, a0, a2
+; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vmerge.vim v16, v18, 1, v0
; CHECK-NEXT: add a4, a3, a2
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vim v18, v18, 1, v0
@@ -839,12 +839,12 @@ define <vscale x 64 x i1> @vector_interleave_nxv64i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: vmerge.vim v14, v18, 1, v0
; ZVBB-NEXT: vmv1r.v v0, v11
; ZVBB-NEXT: vmerge.vim v12, v18, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v9
-; ZVBB-NEXT: vmerge.vim v16, v18, 1, v0
; ZVBB-NEXT: addi a0, sp, 16
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: slli a2, a1, 1
; ZVBB-NEXT: add a3, a0, a2
+; ZVBB-NEXT: vmv1r.v v0, v9
+; ZVBB-NEXT: vmerge.vim v16, v18, 1, v0
; ZVBB-NEXT: add a4, a3, a2
; ZVBB-NEXT: vmv1r.v v0, v10
; ZVBB-NEXT: vmerge.vim v18, v18, 1, v0
@@ -1093,14 +1093,12 @@ define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v14, 0
-; CHECK-NEXT: vmerge.vim v24, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v22, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v12, v14, 1, v0
-; CHECK-NEXT: vmv4r.v v16, v24
+; CHECK-NEXT: vmv2r.v v16, v22
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v26, v14, 1, v0
+; CHECK-NEXT: vmerge.vim v24, v14, 1, v0
; CHECK-NEXT: addi a4, sp, 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 2
@@ -1108,20 +1106,22 @@ define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
; CHECK-NEXT: add a2, a4, a1
-; CHECK-NEXT: vmv1r.v v17, v22
+; CHECK-NEXT: vmv1r.v v17, v12
; CHECK-NEXT: srli a3, a1, 1
-; CHECK-NEXT: vmv1r.v v18, v26
-; CHECK-NEXT: vmv1r.v v26, v23
+; CHECK-NEXT: vmv1r.v v18, v24
+; CHECK-NEXT: vmv1r.v v24, v13
; CHECK-NEXT: add a5, a2, a1
-; CHECK-NEXT: vmv1r.v v19, v12
-; CHECK-NEXT: vmv1r.v v28, v13
+; CHECK-NEXT: vmv1r.v v19, v20
+; CHECK-NEXT: vmv1r.v v26, v21
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
; CHECK-NEXT: vsetvli a6, zero, e8, m1, ta, ma
; CHECK-NEXT: vsseg5e8.v v16, (a4)
-; CHECK-NEXT: vmv1r.v v29, v21
-; CHECK-NEXT: vsseg5e8.v v25, (a0)
+; CHECK-NEXT: vmv1r.v v27, v21
+; CHECK-NEXT: vsseg5e8.v v23, (a0)
; CHECK-NEXT: vl1r.v v8, (a5)
; CHECK-NEXT: add a5, a5, a1
; CHECK-NEXT: vl1r.v v10, (a4)
@@ -1167,14 +1167,12 @@ define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmv.v.i v14, 0
-; ZVBB-NEXT: vmerge.vim v24, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v8
; ZVBB-NEXT: vmerge.vim v22, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v10
+; ZVBB-NEXT: vmv1r.v v0, v8
; ZVBB-NEXT: vmerge.vim v12, v14, 1, v0
-; ZVBB-NEXT: vmv4r.v v16, v24
+; ZVBB-NEXT: vmv2r.v v16, v22
; ZVBB-NEXT: vmv1r.v v0, v9
-; ZVBB-NEXT: vmerge.vim v26, v14, 1, v0
+; ZVBB-NEXT: vmerge.vim v24, v14, 1, v0
; ZVBB-NEXT: addi a4, sp, 16
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 2
@@ -1182,20 +1180,22 @@ define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: add a0, sp, a0
; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: csrr a1, vlenb
+; ZVBB-NEXT: vmv1r.v v0, v10
+; ZVBB-NEXT: vmerge.vim v20, v14, 1, v0
; ZVBB-NEXT: add a2, a4, a1
-; ZVBB-NEXT: vmv1r.v v17, v22
+; ZVBB-NEXT: vmv1r.v v17, v12
; ZVBB-NEXT: srli a3, a1, 1
-; ZVBB-NEXT: vmv1r.v v18, v26
-; ZVBB-NEXT: vmv1r.v v26, v23
+; ZVBB-NEXT: vmv1r.v v18, v24
+; ZVBB-NEXT: vmv1r.v v24, v13
; ZVBB-NEXT: add a5, a2, a1
-; ZVBB-NEXT: vmv1r.v v19, v12
-; ZVBB-NEXT: vmv1r.v v28, v13
+; ZVBB-NEXT: vmv1r.v v19, v20
+; ZVBB-NEXT: vmv1r.v v26, v21
; ZVBB-NEXT: vmv1r.v v0, v11
; ZVBB-NEXT: vmerge.vim v20, v14, 1, v0
; ZVBB-NEXT: vsetvli a6, zero, e8, m1, ta, ma
; ZVBB-NEXT: vsseg5e8.v v16, (a4)
-; ZVBB-NEXT: vmv1r.v v29, v21
-; ZVBB-NEXT: vsseg5e8.v v25, (a0)
+; ZVBB-NEXT: vmv1r.v v27, v21
+; ZVBB-NEXT: vsseg5e8.v v23, (a0)
; ZVBB-NEXT: vl1r.v v8, (a5)
; ZVBB-NEXT: add a5, a5, a1
; ZVBB-NEXT: vl1r.v v10, (a4)
@@ -2312,62 +2312,63 @@ define <vscale x 96 x i1> @vector_interleave_nxv96i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv1r.v v13, v12
-; CHECK-NEXT: vmv1r.v v12, v9
+; CHECK-NEXT: vmv1r.v v12, v11
+; CHECK-NEXT: vmv1r.v v11, v9
; CHECK-NEXT: vmv1r.v v17, v8
; CHECK-NEXT: vmv.v.i v14, 0
; CHECK-NEXT: vmerge.vim v8, v14, 1, v0
; CHECK-NEXT: vmv1r.v v0, v17
-; CHECK-NEXT: vmerge.vim v24, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmerge.vim v22, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vim v16, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: vmerge.vim v18, v14, 1, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a0, 6
; CHECK-NEXT: mul a1, a1, a0
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vmv1r.v v10, v25
-; CHECK-NEXT: addi a5, sp, 16
-; CHECK-NEXT: vmv1r.v v11, v23
+; CHECK-NEXT: addi a4, sp, 16
+; CHECK-NEXT: vmv1r.v v10, v23
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: vmv1r.v v11, v21
+; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmerge.vim v24, v14, 1, v0
; CHECK-NEXT: vmv1r.v v12, v17
; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v13, v19
+; CHECK-NEXT: vmerge.vim v18, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v13, v25
; CHECK-NEXT: add a2, a1, a0
-; CHECK-NEXT: vmv1r.v v14, v21
+; CHECK-NEXT: vmv1r.v v14, v19
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vsseg6e8.v v9, (a1)
-; CHECK-NEXT: vmv1r.v v9, v24
-; CHECK-NEXT: add a4, a5, a0
-; CHECK-NEXT: vmv1r.v v10, v22
+; CHECK-NEXT: vmv1r.v v9, v22
+; CHECK-NEXT: add a5, a4, a0
+; CHECK-NEXT: vmv1r.v v10, v20
; CHECK-NEXT: srli a3, a0, 1
; CHECK-NEXT: vmv1r.v v11, v16
-; CHECK-NEXT: add a6, a4, a0
-; CHECK-NEXT: vmv1r.v v12, v18
+; CHECK-NEXT: add a6, a5, a0
+; CHECK-NEXT: vmv1r.v v12, v24
; CHECK-NEXT: add a7, a2, a0
-; CHECK-NEXT: vmv1r.v v13, v20
-; CHECK-NEXT: vsseg6e8.v v8, (a5)
+; CHECK-NEXT: vmv1r.v v13, v18
+; CHECK-NEXT: vsseg6e8.v v8, (a4)
; CHECK-NEXT: vl1r.v v8, (a1)
; CHECK-NEXT: add a1, a6, a0
; CHECK-NEXT: vl1r.v v10, (a6)
; CHECK-NEXT: add a6, a7, a0
-; CHECK-NEXT: vl1r.v v12, (a5)
-; CHECK-NEXT: add a5, a1, a0
+; CHECK-NEXT: vl1r.v v12, (a4)
+; CHECK-NEXT: add a4, a1, a0
; CHECK-NEXT: vl1r.v v14, (a7)
; CHECK-NEXT: add a7, a6, a0
-; CHECK-NEXT: vl1r.v v16, (a5)
-; CHECK-NEXT: add a5, a5, a0
+; CHECK-NEXT: vl1r.v v16, (a4)
+; CHECK-NEXT: add a4, a4, a0
; CHECK-NEXT: vl1r.v v18, (a7)
; CHECK-NEXT: add a7, a7, a0
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vl1r.v v9, (a2)
-; CHECK-NEXT: vl1r.v v17, (a5)
+; CHECK-NEXT: vl1r.v v17, (a4)
; CHECK-NEXT: vl1r.v v11, (a1)
-; CHECK-NEXT: vl1r.v v13, (a4)
+; CHECK-NEXT: vl1r.v v13, (a5)
; CHECK-NEXT: vl1r.v v19, (a7)
; CHECK-NEXT: vl1r.v v15, (a6)
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
@@ -2400,62 +2401,63 @@ define <vscale x 96 x i1> @vector_interleave_nxv96i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmv1r.v v13, v12
-; ZVBB-NEXT: vmv1r.v v12, v9
+; ZVBB-NEXT: vmv1r.v v12, v11
+; ZVBB-NEXT: vmv1r.v v11, v9
; ZVBB-NEXT: vmv1r.v v17, v8
; ZVBB-NEXT: vmv.v.i v14, 0
; ZVBB-NEXT: vmerge.vim v8, v14, 1, v0
; ZVBB-NEXT: vmv1r.v v0, v17
-; ZVBB-NEXT: vmerge.vim v24, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v12
; ZVBB-NEXT: vmerge.vim v22, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v11
+; ZVBB-NEXT: vmerge.vim v20, v14, 1, v0
; ZVBB-NEXT: vmv1r.v v0, v10
; ZVBB-NEXT: vmerge.vim v16, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v11
-; ZVBB-NEXT: vmerge.vim v18, v14, 1, v0
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: li a0, 6
; ZVBB-NEXT: mul a1, a1, a0
; ZVBB-NEXT: add a1, sp, a1
; ZVBB-NEXT: addi a1, a1, 16
-; ZVBB-NEXT: vmv1r.v v10, v25
-; ZVBB-NEXT: addi a5, sp, 16
-; ZVBB-NEXT: vmv1r.v v11, v23
+; ZVBB-NEXT: addi a4, sp, 16
+; ZVBB-NEXT: vmv1r.v v10, v23
; ZVBB-NEXT: csrr a0, vlenb
+; ZVBB-NEXT: vmv1r.v v11, v21
+; ZVBB-NEXT: vmv1r.v v0, v12
+; ZVBB-NEXT: vmerge.vim v24, v14, 1, v0
; ZVBB-NEXT: vmv1r.v v12, v17
; ZVBB-NEXT: vmv1r.v v0, v13
-; ZVBB-NEXT: vmerge.vim v20, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v13, v19
+; ZVBB-NEXT: vmerge.vim v18, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v13, v25
; ZVBB-NEXT: add a2, a1, a0
-; ZVBB-NEXT: vmv1r.v v14, v21
+; ZVBB-NEXT: vmv1r.v v14, v19
; ZVBB-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; ZVBB-NEXT: vsseg6e8.v v9, (a1)
-; ZVBB-NEXT: vmv1r.v v9, v24
-; ZVBB-NEXT: add a4, a5, a0
-; ZVBB-NEXT: vmv1r.v v10, v22
+; ZVBB-NEXT: vmv1r.v v9, v22
+; ZVBB-NEXT: add a5, a4, a0
+; ZVBB-NEXT: vmv1r.v v10, v20
; ZVBB-NEXT: srli a3, a0, 1
; ZVBB-NEXT: vmv1r.v v11, v16
-; ZVBB-NEXT: add a6, a4, a0
-; ZVBB-NEXT: vmv1r.v v12, v18
+; ZVBB-NEXT: add a6, a5, a0
+; ZVBB-NEXT: vmv1r.v v12, v24
; ZVBB-NEXT: add a7, a2, a0
-; ZVBB-NEXT: vmv1r.v v13, v20
-; ZVBB-NEXT: vsseg6e8.v v8, (a5)
+; ZVBB-NEXT: vmv1r.v v13, v18
+; ZVBB-NEXT: vsseg6e8.v v8, (a4)
; ZVBB-NEXT: vl1r.v v8, (a1)
; ZVBB-NEXT: add a1, a6, a0
; ZVBB-NEXT: vl1r.v v10, (a6)
; ZVBB-NEXT: add a6, a7, a0
-; ZVBB-NEXT: vl1r.v v12, (a5)
-; ZVBB-NEXT: add a5, a1, a0
+; ZVBB-NEXT: vl1r.v v12, (a4)
+; ZVBB-NEXT: add a4, a1, a0
; ZVBB-NEXT: vl1r.v v14, (a7)
; ZVBB-NEXT: add a7, a6, a0
-; ZVBB-NEXT: vl1r.v v16, (a5)
-; ZVBB-NEXT: add a5, a5, a0
+; ZVBB-NEXT: vl1r.v v16, (a4)
+; ZVBB-NEXT: add a4, a4, a0
; ZVBB-NEXT: vl1r.v v18, (a7)
; ZVBB-NEXT: add a7, a7, a0
; ZVBB-NEXT: srli a0, a0, 2
; ZVBB-NEXT: vl1r.v v9, (a2)
-; ZVBB-NEXT: vl1r.v v17, (a5)
+; ZVBB-NEXT: vl1r.v v17, (a4)
; ZVBB-NEXT: vl1r.v v11, (a1)
-; ZVBB-NEXT: vl1r.v v13, (a4)
+; ZVBB-NEXT: vl1r.v v13, (a5)
; ZVBB-NEXT: vl1r.v v19, (a7)
; ZVBB-NEXT: vl1r.v v15, (a6)
; ZVBB-NEXT: vsetvli a1, zero, e8, m2, ta, ma
@@ -3664,23 +3666,22 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv1r.v v23, v13
-; CHECK-NEXT: vmv1r.v v13, v11
+; CHECK-NEXT: vmv1r.v v28, v12
+; CHECK-NEXT: vmv1r.v v12, v11
; CHECK-NEXT: vmv1r.v v11, v9
-; CHECK-NEXT: vmv1r.v v17, v8
+; CHECK-NEXT: vmv1r.v v13, v8
; CHECK-NEXT: vmv.v.i v14, 0
; CHECK-NEXT: vmerge.vim v8, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v17
-; CHECK-NEXT: vmerge.vim v28, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: vmerge.vim v26, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vim v24, v14, 1, v0
; CHECK-NEXT: vmv4r.v v16, v8
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmerge.vim v10, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v17, v28
+; CHECK-NEXT: vmv1r.v v17, v26
; CHECK-NEXT: vmv1r.v v18, v10
-; CHECK-NEXT: vmv1r.v v0, v13
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmerge.vim v12, v14, 1, v0
; CHECK-NEXT: addi a3, sp, 16
; CHECK-NEXT: csrr a0, vlenb
@@ -3689,17 +3690,19 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: vmv1r.v v0, v28
+; CHECK-NEXT: vmerge.vim v28, v14, 1, v0
; CHECK-NEXT: add a2, a3, a1
-; CHECK-NEXT: vmv1r.v v19, v26
+; CHECK-NEXT: vmv1r.v v19, v24
; CHECK-NEXT: add a4, a2, a1
; CHECK-NEXT: vmv1r.v v20, v12
-; CHECK-NEXT: vmv1r.v v10, v29
+; CHECK-NEXT: vmv1r.v v10, v27
; CHECK-NEXT: add a5, a4, a1
-; CHECK-NEXT: vmv1r.v v21, v24
-; CHECK-NEXT: vmv1r.v v12, v27
+; CHECK-NEXT: vmv1r.v v21, v28
+; CHECK-NEXT: vmv1r.v v12, v25
; CHECK-NEXT: vmv1r.v v0, v23
; CHECK-NEXT: vmerge.vim v22, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v14, v25
+; CHECK-NEXT: vmv1r.v v14, v29
; CHECK-NEXT: vsetvli a6, zero, e8, m1, ta, ma
; CHECK-NEXT: vsseg7e8.v v16, (a3)
; CHECK-NEXT: vmv1r.v v15, v23
@@ -3760,23 +3763,22 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmv1r.v v23, v13
-; ZVBB-NEXT: vmv1r.v v13, v11
+; ZVBB-NEXT: vmv1r.v v28, v12
+; ZVBB-NEXT: vmv1r.v v12, v11
; ZVBB-NEXT: vmv1r.v v11, v9
-; ZVBB-NEXT: vmv1r.v v17, v8
+; ZVBB-NEXT: vmv1r.v v13, v8
; ZVBB-NEXT: vmv.v.i v14, 0
; ZVBB-NEXT: vmerge.vim v8, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v17
-; ZVBB-NEXT: vmerge.vim v28, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v10
+; ZVBB-NEXT: vmv1r.v v0, v13
; ZVBB-NEXT: vmerge.vim v26, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v12
+; ZVBB-NEXT: vmv1r.v v0, v10
; ZVBB-NEXT: vmerge.vim v24, v14, 1, v0
; ZVBB-NEXT: vmv4r.v v16, v8
; ZVBB-NEXT: vmv1r.v v0, v11
; ZVBB-NEXT: vmerge.vim v10, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v17, v28
+; ZVBB-NEXT: vmv1r.v v17, v26
; ZVBB-NEXT: vmv1r.v v18, v10
-; ZVBB-NEXT: vmv1r.v v0, v13
+; ZVBB-NEXT: vmv1r.v v0, v12
; ZVBB-NEXT: vmerge.vim v12, v14, 1, v0
; ZVBB-NEXT: addi a3, sp, 16
; ZVBB-NEXT: csrr a0, vlenb
@@ -3785,17 +3787,19 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; ZVBB-NEXT: add a0, sp, a0
; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: csrr a1, vlenb
+; ZVBB-NEXT: vmv1r.v v0, v28
+; ZVBB-NEXT: vmerge.vim v28, v14, 1, v0
; ZVBB-NEXT: add a2, a3, a1
-; ZVBB-NEXT: vmv1r.v v19, v26
+; ZVBB-NEXT: vmv1r.v v19, v24
; ZVBB-NEXT: add a4, a2, a1
; ZVBB-NEXT: vmv1r.v v20, v12
-; ZVBB-NEXT: vmv1r.v v10, v29
+; ZVBB-NEXT: vmv1r.v v10, v27
; ZVBB-NEXT: add a5, a4, a1
-; ZVBB-NEXT: vmv1r.v v21, v24
-; ZVBB-NEXT: vmv1r.v v12, v27
+; ZVBB-NEXT: vmv1r.v v21, v28
+; ZVBB-NEXT: vmv1r.v v12, v25
; ZVBB-NEXT: vmv1r.v v0, v23
; ZVBB-NEXT: vmerge.vim v22, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v14, v25
+; ZVBB-NEXT: vmv1r.v v14, v29
; ZVBB-NEXT: vsetvli a6, zero, e8, m1, ta, ma
; ZVBB-NEXT: vsseg7e8.v v16, (a3)
; ZVBB-NEXT: vmv1r.v v15, v23
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
index 168b9470f3e83..b619a4d5a2eba 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
@@ -14,13 +14,13 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_negone(<vscale x 1 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv1i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 3
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
@@ -32,13 +32,13 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_negone(<vscale x 1 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv1i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: srli a0, a0, 3
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
@@ -56,13 +56,13 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_max(<vscale x 1 x i1> %a, <vscale
; NOVLDEP-LABEL: splice_nxv1i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 3
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 1
; NOVLDEP-NEXT: addi a0, a0, -1
@@ -74,13 +74,13 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_max(<vscale x 1 x i1> %a, <vscale
; VLDEP-LABEL: splice_nxv1i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: srli a0, a0, 3
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -98,13 +98,13 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_negone(<vscale x 2 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv2i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 2
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
@@ -116,13 +116,13 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_negone(<vscale x 2 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv2i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: srli a0, a0, 2
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
@@ -140,13 +140,13 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_max(<vscale x 2 x i1> %a, <vscale
; NOVLDEP-LABEL: splice_nxv2i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 2
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3
; NOVLDEP-NEXT: addi a0, a0, -3
@@ -158,13 +158,13 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_max(<vscale x 2 x i1> %a, <vscale
; VLDEP-LABEL: splice_nxv2i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: srli a0, a0, 2
; VLDEP-NEXT: addi a0, a0, -3
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -182,13 +182,13 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_negone(<vscale x 4 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv4i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 1
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
@@ -200,13 +200,13 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_negone(<vscale x 4 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv4i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: srli a0, a0, 1
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
@@ -224,13 +224,13 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_max(<vscale x 4 x i1> %a, <vscale
; NOVLDEP-LABEL: splice_nxv4i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 1
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 7
; NOVLDEP-NEXT: addi a0, a0, -7
@@ -242,13 +242,13 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_max(<vscale x 4 x i1> %a, <vscale
; VLDEP-LABEL: splice_nxv4i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: srli a0, a0, 1
; VLDEP-NEXT: addi a0, a0, -7
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -266,13 +266,13 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_negone(<vscale x 8 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv8i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
@@ -283,13 +283,13 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_negone(<vscale x 8 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv8i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; VLDEP-NEXT: vslidedown.vx v8, v8, a0
@@ -306,13 +306,13 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_max(<vscale x 8 x i1> %a, <vscale
; NOVLDEP-LABEL: splice_nxv8i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v11, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmv1r.v v0, v10
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v11
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 15
; NOVLDEP-NEXT: addi a0, a0, -15
; NOVLDEP-NEXT: vslideup.vx v8, v9, a0
@@ -323,13 +323,13 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_max(<vscale x 8 x i1> %a, <vscale
; VLDEP-LABEL: splice_nxv8i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v11, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmv1r.v v0, v10
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v11
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: addi a0, a0, -15
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; VLDEP-NEXT: vslidedown.vi v8, v8, 15
@@ -346,13 +346,13 @@ define <vscale x 16 x i1> @splice_nxv16i1_offset_negone(<vscale x 16 x i1> %a, <
; NOVLDEP-LABEL: splice_nxv16i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v12, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmv1r.v v0, v12
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v10, v12, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v9
+; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
; NOVLDEP-NEXT: slli a0, a0, 1
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
@@ -364,13 +364,13 @@ define <vscale x 16 x i1> @splice_nxv16i1_offset_negone(<vscale x 16 x i1> %a, <
; VLDEP-LABEL: splice_nxv16i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; VLDEP-NEXT: vmv1r.v v12, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmv1r.v v0, v12
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v10, v12, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v9
+; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
; VLDEP-NEXT: slli a0, a0, 1
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, m2, ta, ma
@@ -388,13 +388,13 @@ define <vscale x 16 x i1> @splice_nxv16i1_offset_max(<vscale x 16 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv16i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v12, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmv1r.v v0, v12
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v10, v12, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v9
+; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
; NOVLDEP-NEXT: slli a0, a0, 1
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 31
; NOVLDEP-NEXT: addi a0, a0, -31
@@ -406,13 +406,13 @@ define <vscale x 16 x i1> @splice_nxv16i1_offset_max(<vscale x 16 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv16i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; VLDEP-NEXT: vmv1r.v v12, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmv1r.v v0, v12
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v10, v12, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v9
+; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
; VLDEP-NEXT: slli a0, a0, 1
; VLDEP-NEXT: addi a0, a0, -31
; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -430,13 +430,13 @@ define <vscale x 32 x i1> @splice_nxv32i1_offset_negone(<vscale x 32 x i1> %a, <
; NOVLDEP-LABEL: splice_nxv32i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v16, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v12, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv.v.i v16, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmv1r.v v0, v16
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v12, v16, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v9
+; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
; NOVLDEP-NEXT: slli a0, a0, 2
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
@@ -448,13 +448,13 @@ define <vscale x 32 x i1> @splice_nxv32i1_offset_negone(<vscale x 32 x i1> %a, <
; VLDEP-LABEL: splice_nxv32i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; VLDEP-NEXT: vmv1r.v v16, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v12, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv.v.i v16, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmv1r.v v0, v16
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v12, v16, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v9
+; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
; VLDEP-NEXT: slli a0, a0, 2
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, m4, ta, ma
@@ -473,8 +473,8 @@ define <vscale x 32 x i1> @splice_nxv32i1_offset_max(<vscale x 32 x i1> %a, <vsc
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v16, 0
-; NOVLDEP-NEXT: vmerge.vim v12, v16, 1, v0
; NOVLDEP-NEXT: li a0, 63
+; NOVLDEP-NEXT: vmerge.vim v12, v16, 1, v0
; NOVLDEP-NEXT: vslidedown.vx v12, v12, a0
; NOVLDEP-NEXT: csrr a0, vlenb
; NOVLDEP-NEXT: vmv1r.v v0, v8
@@ -490,9 +490,9 @@ define <vscale x 32 x i1> @splice_nxv32i1_offset_max(<vscale x 32 x i1> %a, <vsc
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; VLDEP-NEXT: vmv.v.i v16, 0
-; VLDEP-NEXT: vmerge.vim v12, v16, 1, v0
; VLDEP-NEXT: csrr a0, vlenb
; VLDEP-NEXT: li a1, 63
+; VLDEP-NEXT: vmerge.vim v12, v16, 1, v0
; VLDEP-NEXT: slli a0, a0, 2
; VLDEP-NEXT: addi a0, a0, -63
; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -512,38 +512,38 @@ define <vscale x 64 x i1> @splice_nxv64i1_offset_negone(<vscale x 64 x i1> %a, <
; NOVLDEP-LABEL: splice_nxv64i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v24, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v16, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v9, v0
+; NOVLDEP-NEXT: vmv.v.i v24, 0
; NOVLDEP-NEXT: csrr a0, vlenb
-; NOVLDEP-NEXT: vmv1r.v v0, v24
-; NOVLDEP-NEXT: vmerge.vim v16, v16, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v8
+; NOVLDEP-NEXT: vmerge.vim v16, v24, 1, v0
+; NOVLDEP-NEXT: vmv1r.v v0, v9
+; NOVLDEP-NEXT: vmerge.vim v8, v24, 1, v0
; NOVLDEP-NEXT: slli a0, a0, 3
; NOVLDEP-NEXT: addi a0, a0, -1
-; NOVLDEP-NEXT: vslidedown.vx v16, v16, a0
-; NOVLDEP-NEXT: vslideup.vi v16, v8, 1
-; NOVLDEP-NEXT: vand.vi v8, v16, 1
+; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
+; NOVLDEP-NEXT: vslideup.vi v8, v16, 1
+; NOVLDEP-NEXT: vand.vi v8, v8, 1
; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: splice_nxv64i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; VLDEP-NEXT: vmv1r.v v24, v0
-; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v16, 0
-; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; VLDEP-NEXT: vmv1r.v v9, v0
+; VLDEP-NEXT: vmv.v.i v24, 0
; VLDEP-NEXT: csrr a0, vlenb
-; VLDEP-NEXT: vmv1r.v v0, v24
-; VLDEP-NEXT: vmerge.vim v16, v16, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v8
+; VLDEP-NEXT: vmerge.vim v16, v24, 1, v0
+; VLDEP-NEXT: vmv1r.v v0, v9
+; VLDEP-NEXT: vmerge.vim v8, v24, 1, v0
; VLDEP-NEXT: slli a0, a0, 3
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; VLDEP-NEXT: vslidedown.vx v16, v16, a0
+; VLDEP-NEXT: vslidedown.vx v8, v8, a0
; VLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; VLDEP-NEXT: vslideup.vi v16, v8, 1
-; VLDEP-NEXT: vand.vi v8, v16, 1
+; VLDEP-NEXT: vslideup.vi v8, v16, 1
+; VLDEP-NEXT: vand.vi v8, v8, 1
; VLDEP-NEXT: vmsne.vi v0, v8, 0
; VLDEP-NEXT: ret
%res = call <vscale x 64 x i1> @llvm.vector.splice.nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b, i32 -1)
@@ -555,8 +555,8 @@ define <vscale x 64 x i1> @splice_nxv64i1_offset_max(<vscale x 64 x i1> %a, <vsc
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v24, 0
-; NOVLDEP-NEXT: vmerge.vim v16, v24, 1, v0
; NOVLDEP-NEXT: li a0, 127
+; NOVLDEP-NEXT: vmerge.vim v16, v24, 1, v0
; NOVLDEP-NEXT: vslidedown.vx v16, v16, a0
; NOVLDEP-NEXT: csrr a0, vlenb
; NOVLDEP-NEXT: vmv1r.v v0, v8
@@ -572,9 +572,9 @@ define <vscale x 64 x i1> @splice_nxv64i1_offset_max(<vscale x 64 x i1> %a, <vsc
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; VLDEP-NEXT: vmv.v.i v24, 0
-; VLDEP-NEXT: vmerge.vim v16, v24, 1, v0
; VLDEP-NEXT: csrr a0, vlenb
; VLDEP-NEXT: li a1, 127
+; VLDEP-NEXT: vmerge.vim v16, v24, 1, v0
; VLDEP-NEXT: slli a0, a0, 3
; VLDEP-NEXT: addi a0, a0, -127
; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
index 1155e95c09ee1..00cfcde16969f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
@@ -746,14 +746,14 @@ define <vscale x 16 x double> @vfabs_vv_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-LABEL: vfabs_vv_nxv16f64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: srli a3, a1, 3
+; CHECK-NEXT: srli a2, a1, 3
+; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vfabs.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB44_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
index b83bebb87182a..16de0a036d65e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
@@ -933,22 +933,22 @@ define <vscale x 32 x bfloat> @vfadd_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; ZVFH-NEXT: slli a1, a2, 1
; ZVFH-NEXT: srli a2, a2, 2
; ZVFH-NEXT: sub a3, a0, a1
-; ZVFH-NEXT: sltu a4, a0, a3
-; ZVFH-NEXT: addi a4, a4, -1
-; ZVFH-NEXT: and a3, a4, a3
; ZVFH-NEXT: csrr a4, vlenb
; ZVFH-NEXT: slli a4, a4, 4
; ZVFH-NEXT: add a4, sp, a4
; ZVFH-NEXT: addi a4, a4, 16
; ZVFH-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFH-NEXT: vslidedown.vx v7, v0, a2
+; ZVFH-NEXT: sltu a2, a0, a3
+; ZVFH-NEXT: addi a2, a2, -1
+; ZVFH-NEXT: and a2, a2, a3
; ZVFH-NEXT: vmv1r.v v0, v7
-; ZVFH-NEXT: csrr a2, vlenb
-; ZVFH-NEXT: slli a2, a2, 3
-; ZVFH-NEXT: add a2, sp, a2
-; ZVFH-NEXT: addi a2, a2, 16
-; ZVFH-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; ZVFH-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFH-NEXT: csrr a3, vlenb
+; ZVFH-NEXT: slli a3, a3, 3
+; ZVFH-NEXT: add a3, sp, a3
+; ZVFH-NEXT: addi a3, a3, 16
+; ZVFH-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFH-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
; ZVFH-NEXT: csrr a2, vlenb
; ZVFH-NEXT: slli a3, a2, 4
@@ -1024,22 +1024,22 @@ define <vscale x 32 x bfloat> @vfadd_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
+; ZVFHMIN-NEXT: sltu a2, a0, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
@@ -1115,22 +1115,22 @@ define <vscale x 32 x bfloat> @vfadd_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
-; ZVFBFA-NEXT: sltu a4, a0, a3
-; ZVFBFA-NEXT: addi a4, a4, -1
-; ZVFBFA-NEXT: and a3, a4, a3
; ZVFBFA-NEXT: csrr a4, vlenb
; ZVFBFA-NEXT: slli a4, a4, 4
; ZVFBFA-NEXT: add a4, sp, a4
; ZVFBFA-NEXT: addi a4, a4, 16
; ZVFBFA-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFBFA-NEXT: vslidedown.vx v7, v0, a2
+; ZVFBFA-NEXT: sltu a2, a0, a3
+; ZVFBFA-NEXT: addi a2, a2, -1
+; ZVFBFA-NEXT: and a2, a2, a3
; ZVFBFA-NEXT: vmv1r.v v0, v7
-; ZVFBFA-NEXT: csrr a2, vlenb
-; ZVFBFA-NEXT: slli a2, a2, 3
-; ZVFBFA-NEXT: add a2, sp, a2
-; ZVFBFA-NEXT: addi a2, a2, 16
-; ZVFBFA-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; ZVFBFA-NEXT: vsetvli zero, a3, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: csrr a3, vlenb
+; ZVFBFA-NEXT: slli a3, a3, 3
+; ZVFBFA-NEXT: add a3, sp, a3
+; ZVFBFA-NEXT: addi a3, a3, 16
+; ZVFBFA-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vsetvli zero, a2, e16alt, m4, ta, ma
; ZVFBFA-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFBFA-NEXT: csrr a2, vlenb
; ZVFBFA-NEXT: slli a3, a2, 4
@@ -1474,19 +1474,19 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; ZVFH-NEXT: slli a1, a2, 1
; ZVFH-NEXT: srli a2, a2, 2
; ZVFH-NEXT: sub a3, a0, a1
-; ZVFH-NEXT: sltu a4, a0, a3
-; ZVFH-NEXT: addi a4, a4, -1
-; ZVFH-NEXT: and a3, a4, a3
; ZVFH-NEXT: vmv1r.v v7, v0
; ZVFH-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFH-NEXT: vslidedown.vx v6, v0, a2
-; ZVFH-NEXT: csrr a2, vlenb
-; ZVFH-NEXT: slli a2, a2, 3
-; ZVFH-NEXT: add a2, sp, a2
-; ZVFH-NEXT: addi a2, a2, 16
-; ZVFH-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFH-NEXT: sltu a2, a0, a3
+; ZVFH-NEXT: addi a2, a2, -1
+; ZVFH-NEXT: and a2, a2, a3
+; ZVFH-NEXT: csrr a3, vlenb
+; ZVFH-NEXT: slli a3, a3, 3
+; ZVFH-NEXT: add a3, sp, a3
+; ZVFH-NEXT: addi a3, a3, 16
+; ZVFH-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFH-NEXT: vmv1r.v v0, v6
-; ZVFH-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFH-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
; ZVFH-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -1538,19 +1538,19 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a2, a0, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -1601,16 +1601,16 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
-; ZVFBFA-NEXT: sltu a4, a0, a3
-; ZVFBFA-NEXT: addi a4, a4, -1
-; ZVFBFA-NEXT: and a3, a4, a3
; ZVFBFA-NEXT: vmv1r.v v7, v0
; ZVFBFA-NEXT: vsetvli a4, zero, e8alt, mf2, ta, ma
; ZVFBFA-NEXT: vslidedown.vx v6, v0, a2
-; ZVFBFA-NEXT: addi a2, sp, 16
-; ZVFBFA-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: sltu a2, a0, a3
+; ZVFBFA-NEXT: addi a2, a2, -1
+; ZVFBFA-NEXT: and a2, a2, a3
+; ZVFBFA-NEXT: addi a3, sp, 16
+; ZVFBFA-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFBFA-NEXT: vmv1r.v v0, v6
-; ZVFBFA-NEXT: vsetvli zero, a3, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vsetvli zero, a2, e16alt, m4, ta, ma
; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -2730,22 +2730,22 @@ define <vscale x 32 x half> @vfadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
+; ZVFHMIN-NEXT: sltu a2, a0, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
@@ -2821,22 +2821,22 @@ define <vscale x 32 x half> @vfadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
-; ZVFBFA-NEXT: sltu a4, a0, a3
-; ZVFBFA-NEXT: addi a4, a4, -1
-; ZVFBFA-NEXT: and a3, a4, a3
; ZVFBFA-NEXT: csrr a4, vlenb
; ZVFBFA-NEXT: slli a4, a4, 4
; ZVFBFA-NEXT: add a4, sp, a4
; ZVFBFA-NEXT: addi a4, a4, 16
; ZVFBFA-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFBFA-NEXT: vslidedown.vx v7, v0, a2
+; ZVFBFA-NEXT: sltu a2, a0, a3
+; ZVFBFA-NEXT: addi a2, a2, -1
+; ZVFBFA-NEXT: and a2, a2, a3
; ZVFBFA-NEXT: vmv1r.v v0, v7
-; ZVFBFA-NEXT: csrr a2, vlenb
-; ZVFBFA-NEXT: slli a2, a2, 3
-; ZVFBFA-NEXT: add a2, sp, a2
-; ZVFBFA-NEXT: addi a2, a2, 16
-; ZVFBFA-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; ZVFBFA-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFBFA-NEXT: csrr a3, vlenb
+; ZVFBFA-NEXT: slli a3, a3, 3
+; ZVFBFA-NEXT: add a3, sp, a3
+; ZVFBFA-NEXT: addi a3, a3, 16
+; ZVFBFA-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFBFA-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFBFA-NEXT: csrr a2, vlenb
; ZVFBFA-NEXT: slli a3, a2, 4
@@ -3104,19 +3104,19 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a2, a0, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -3168,19 +3168,19 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
-; ZVFBFA-NEXT: sltu a4, a0, a3
-; ZVFBFA-NEXT: addi a4, a4, -1
-; ZVFBFA-NEXT: and a3, a4, a3
; ZVFBFA-NEXT: vmv1r.v v7, v0
; ZVFBFA-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFBFA-NEXT: vslidedown.vx v6, v0, a2
-; ZVFBFA-NEXT: csrr a2, vlenb
-; ZVFBFA-NEXT: slli a2, a2, 3
-; ZVFBFA-NEXT: add a2, sp, a2
-; ZVFBFA-NEXT: addi a2, a2, 16
-; ZVFBFA-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: sltu a2, a0, a3
+; ZVFBFA-NEXT: addi a2, a2, -1
+; ZVFBFA-NEXT: and a2, a2, a3
+; ZVFBFA-NEXT: csrr a3, vlenb
+; ZVFBFA-NEXT: slli a3, a3, 3
+; ZVFBFA-NEXT: add a3, sp, a3
+; ZVFBFA-NEXT: addi a3, a3, 16
+; ZVFBFA-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFBFA-NEXT: vmv1r.v v0, v6
-; ZVFBFA-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFBFA-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
index f80be5de3bbfd..fb4eca7837738 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
@@ -372,22 +372,22 @@ define <vscale x 32 x bfloat> @vfdiv_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
; CHECK-NEXT: addi a4, a4, 16
; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vslidedown.vx v7, v0, a2
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a3, a2, 4
@@ -555,19 +555,19 @@ define <vscale x 32 x bfloat> @vfdiv_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v6, v0, a2
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -1194,22 +1194,22 @@ define <vscale x 32 x half> @vfdiv_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
+; ZVFHMIN-NEXT: sltu a2, a0, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
@@ -1389,19 +1389,19 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a2, a0, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
index c44ae411f6982..48b0bfd21bdba 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
@@ -613,9 +613,6 @@ define <vscale x 32 x bfloat> @vfma_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vs
; CHECK-NEXT: slli a0, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a1, a0
-; CHECK-NEXT: sltu a4, a1, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 3
; CHECK-NEXT: mv a5, a4
@@ -631,18 +628,21 @@ define <vscale x 32 x bfloat> @vfma_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vs
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a4, a2, 5
-; CHECK-NEXT: add a2, a4, a2
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; CHECK-NEXT: sltu a2, a1, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a4, a3, 5
+; CHECK-NEXT: add a3, a4, a3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
@@ -914,9 +914,6 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bfl
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: mv a5, a4
@@ -935,15 +932,18 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bfl
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: mv a4, a2
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: add a2, a2, a4
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: mv a4, a3
+; CHECK-NEXT: slli a3, a3, 1
+; CHECK-NEXT: add a3, a3, a4
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
@@ -954,7 +954,7 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bfl
; CHECK-NEXT: slli a2, a2, 5
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: mv a3, a2
@@ -963,12 +963,12 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bfl
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v28, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a2, vlenb
@@ -1136,9 +1136,6 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_commute(<vscale x 32 x bfloat>
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 5
; CHECK-NEXT: add a4, sp, a4
@@ -1152,18 +1149,21 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_commute(<vscale x 32 x bfloat>
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 4
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a4, a2, 5
-; CHECK-NEXT: add a2, a4, a2
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 4
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a4, a3, 5
+; CHECK-NEXT: add a3, a4, a3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
@@ -2363,9 +2363,6 @@ define <vscale x 32 x half> @vfma_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a0, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a1, a0
-; ZVFHMIN-NEXT: sltu a4, a1, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 3
; ZVFHMIN-NEXT: mv a5, a4
@@ -2381,18 +2378,21 @@ define <vscale x 32 x half> @vfma_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a4, a2, 5
-; ZVFHMIN-NEXT: add a2, a4, a2
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: sltu a2, a1, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a4, a3, 5
+; ZVFHMIN-NEXT: add a3, a4, a3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
@@ -2677,9 +2677,6 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16(<vscale x 32 x half> %va, half %b,
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: mv a5, a4
@@ -2698,15 +2695,18 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16(<vscale x 32 x half> %va, half %b,
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a4, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a4
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: sltu a2, a0, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: mv a4, a3
+; ZVFHMIN-NEXT: slli a3, a3, 1
+; ZVFHMIN-NEXT: add a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
@@ -2717,7 +2717,7 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16(<vscale x 32 x half> %va, half %b,
; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -2726,12 +2726,12 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16(<vscale x 32 x half> %va, half %b,
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
@@ -2905,9 +2905,6 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_commute(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -2921,18 +2918,21 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_commute(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a4, a2, 5
-; ZVFHMIN-NEXT: add a2, a4, a2
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: sltu a2, a0, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a4, a3, 5
+; ZVFHMIN-NEXT: add a3, a4, a3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
@@ -8564,24 +8564,30 @@ define <vscale x 32 x half> @vfmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscal
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a3, a2, 5
-; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a3, a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: slli a2, a2, 2
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vmv8r.v v16, v8
; ZVFHMIN-NEXT: vl8re16.v v24, (a0)
; ZVFHMIN-NEXT: lui a2, 8
@@ -8590,102 +8596,157 @@ define <vscale x 32 x half> @vfmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscal
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a4, a1, a0
; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 5
+; ZVFHMIN-NEXT: slli a5, a5, 4
+; ZVFHMIN-NEXT: mv a6, a5
+; ZVFHMIN-NEXT: slli a5, a5, 1
+; ZVFHMIN-NEXT: add a5, a5, a6
+; ZVFHMIN-NEXT: add a5, sp, a5
+; ZVFHMIN-NEXT: addi a5, a5, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a5) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: sltu a3, a1, a4
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: slli a5, a5, 4
+; ZVFHMIN-NEXT: mv a6, a5
+; ZVFHMIN-NEXT: slli a5, a5, 1
+; ZVFHMIN-NEXT: add a5, a5, a6
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
-; ZVFHMIN-NEXT: sltu a2, a1, a4
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a4
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 5
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a3, a3, a4
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vmv4r.v v8, v24
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: slli a2, a2, 2
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a1, a0, .LBB280_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB280_2:
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a2
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: slli a0, a0, 2
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a1, a0, 5
-; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -8934,9 +8995,6 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16(<vscale x 32 x half> %va, half %
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a2
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -8950,6 +9008,9 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16(<vscale x 32 x half> %va, half %
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a3, a0, a2
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
@@ -9114,9 +9175,6 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16_commute(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a2
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -9124,6 +9182,9 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16_commute(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a3
+; ZVFHMIN-NEXT: sltu a3, a0, a2
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
@@ -9500,247 +9561,145 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 4
-; ZVFHMIN-NEXT: add a3, a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vl8re16.v v24, (a0)
+; ZVFHMIN-NEXT: vl8re16.v v8, (a0)
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: mv a4, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a4
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v8, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a0, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a4, a1, a0
; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 4
-; ZVFHMIN-NEXT: mv a6, a5
-; ZVFHMIN-NEXT: slli a5, a5, 1
-; ZVFHMIN-NEXT: add a5, a5, a6
+; ZVFHMIN-NEXT: slli a5, a5, 5
+; ZVFHMIN-NEXT: add a5, sp, a5
+; ZVFHMIN-NEXT: addi a5, a5, 16
+; ZVFHMIN-NEXT: vl1r.v v24, (a5) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v7, v24, a3
+; ZVFHMIN-NEXT: sltu a3, a1, a4
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: slli a5, a5, 5
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: slli a5, a5, 4
+; ZVFHMIN-NEXT: add a5, sp, a5
+; ZVFHMIN-NEXT: addi a5, a5, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
-; ZVFHMIN-NEXT: sltu a2, a1, a4
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a4
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 4
-; ZVFHMIN-NEXT: mv a5, a4
-; ZVFHMIN-NEXT: slli a4, a4, 1
-; ZVFHMIN-NEXT: add a4, a4, a5
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: mv a4, a3
-; ZVFHMIN-NEXT: slli a3, a3, 2
-; ZVFHMIN-NEXT: add a3, a3, a4
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: vmv4r.v v8, v24
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 4
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: mv a4, a3
-; ZVFHMIN-NEXT: slli a3, a3, 2
-; ZVFHMIN-NEXT: add a3, a3, a4
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 2
-; ZVFHMIN-NEXT: add a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a3, a3, a4
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 2
-; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v8, v7
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: slli a2, a2, 1
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 2
-; ZVFHMIN-NEXT: add a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a1, a0, .LBB286_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB286_2:
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: mv a2, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a2
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a2, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a2
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 2
-; ZVFHMIN-NEXT: add a0, a0, a1
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: slli a0, a0, 1
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
+; ZVFHMIN-NEXT: vmv.v.v v16, v8
+; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: add a1, a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -9781,10 +9740,7 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
@@ -9811,57 +9767,36 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a5, a5, a6
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a5) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: sltu a3, a1, a4
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: slli a5, a5, 3
+; ZVFHMIN-NEXT: mv a6, a5
+; ZVFHMIN-NEXT: slli a5, a5, 2
+; ZVFHMIN-NEXT: add a5, a5, a6
+; ZVFHMIN-NEXT: add a5, sp, a5
+; ZVFHMIN-NEXT: addi a5, a5, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
-; ZVFHMIN-NEXT: sltu a2, a1, a4
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a4
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: mv a5, a4
-; ZVFHMIN-NEXT: slli a4, a4, 2
-; ZVFHMIN-NEXT: add a4, a4, a5
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 5
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a3, a3, a4
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vmv4r.v v8, v24
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 5
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -9869,22 +9804,23 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
@@ -9902,14 +9838,17 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a2
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
@@ -9917,19 +9856,16 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -9942,7 +9878,7 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
@@ -9954,7 +9890,7 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: slli a0, a0, 3
@@ -10302,12 +10238,11 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv8r.v v16, v8
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vmv.v.x v8, a1
+; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v16, a1
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: mv a4, a1
@@ -10315,14 +10250,14 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: add a1, a1, a4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v24, v16, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v24, v8, a2, v0.t
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
@@ -10333,32 +10268,32 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: add a1, a4, a1
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
+; ZVFHMIN-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vxor.vx v8, v8, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a2
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v16, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a3
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a4, a3, 5
; ZVFHMIN-NEXT: add a3, a4, a3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a3, a0, a2
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a4, a3, 5
; ZVFHMIN-NEXT: add a3, a4, a3
@@ -10366,11 +10301,11 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
@@ -10381,6 +10316,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: vmv8r.v v24, v8
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -10394,8 +10330,8 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -10403,9 +10339,9 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -10426,7 +10362,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
@@ -10439,13 +10375,13 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
@@ -10465,7 +10401,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -10518,12 +10454,17 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv8r.v v24, v8
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a2, a1, 5
+; ZVFHMIN-NEXT: add a1, a2, a1
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vmv.v.x v8, a1
+; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v16, a1
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: mv a4, a1
@@ -10531,44 +10472,50 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a1, a1, a4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v24, v8, a2, v0.t
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a4, a1, 5
+; ZVFHMIN-NEXT: add a1, a4, a1
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vxor.vx v8, v8, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a2
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v16, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a3
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a4, a3, 5
; ZVFHMIN-NEXT: add a3, a4, a3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a3, a0, a2
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a4, a3, 5
; ZVFHMIN-NEXT: add a3, a4, a3
@@ -10576,12 +10523,11 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vmv8r.v v8, v24
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
@@ -10591,7 +10537,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -10605,8 +10551,8 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -10614,9 +10560,9 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -10624,7 +10570,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a0, a1, .LBB291_2
@@ -10637,7 +10583,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
@@ -10650,7 +10596,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
@@ -11051,9 +10997,6 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: sub a2, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a2
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -11067,6 +11010,9 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a3, a0, a2
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
@@ -11251,9 +11197,6 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: sub a2, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a2
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -11267,6 +11210,9 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a3, a0, a2
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
@@ -11723,247 +11669,145 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 4
-; ZVFHMIN-NEXT: add a3, a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vl8re16.v v24, (a0)
+; ZVFHMIN-NEXT: vl8re16.v v8, (a0)
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: mv a4, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a4
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v8, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a0, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a4, a1, a0
; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 4
-; ZVFHMIN-NEXT: mv a6, a5
-; ZVFHMIN-NEXT: slli a5, a5, 1
-; ZVFHMIN-NEXT: add a5, a5, a6
+; ZVFHMIN-NEXT: slli a5, a5, 5
+; ZVFHMIN-NEXT: add a5, sp, a5
+; ZVFHMIN-NEXT: addi a5, a5, 16
+; ZVFHMIN-NEXT: vl1r.v v24, (a5) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v7, v24, a3
+; ZVFHMIN-NEXT: sltu a3, a1, a4
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: slli a5, a5, 5
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: slli a5, a5, 4
+; ZVFHMIN-NEXT: add a5, sp, a5
+; ZVFHMIN-NEXT: addi a5, a5, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
-; ZVFHMIN-NEXT: sltu a2, a1, a4
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a4
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 4
-; ZVFHMIN-NEXT: mv a5, a4
-; ZVFHMIN-NEXT: slli a4, a4, 1
-; ZVFHMIN-NEXT: add a4, a4, a5
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: mv a4, a3
-; ZVFHMIN-NEXT: slli a3, a3, 2
-; ZVFHMIN-NEXT: add a3, a3, a4
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: vmv4r.v v8, v24
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 4
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: mv a4, a3
-; ZVFHMIN-NEXT: slli a3, a3, 2
-; ZVFHMIN-NEXT: add a3, a3, a4
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 2
-; ZVFHMIN-NEXT: add a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a3, a3, a4
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 2
-; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv1r.v v0, v7
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v8, v7
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: slli a2, a2, 1
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 2
-; ZVFHMIN-NEXT: add a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a1, a0, .LBB298_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB298_2:
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: mv a2, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a2
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a2, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a2
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24, v0.t
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 2
-; ZVFHMIN-NEXT: add a0, a0, a1
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 2
-; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
+; ZVFHMIN-NEXT: vmv.v.v v16, v8
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: add a1, a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -12004,10 +11848,7 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
@@ -12034,57 +11875,36 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a5, a5, a6
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a5) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: sltu a3, a1, a4
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: slli a5, a5, 3
+; ZVFHMIN-NEXT: mv a6, a5
+; ZVFHMIN-NEXT: slli a5, a5, 2
+; ZVFHMIN-NEXT: add a5, a5, a6
+; ZVFHMIN-NEXT: add a5, sp, a5
+; ZVFHMIN-NEXT: addi a5, a5, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
-; ZVFHMIN-NEXT: sltu a2, a1, a4
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a4
-; ZVFHMIN-NEXT: csrr a4, vlenb
-; ZVFHMIN-NEXT: slli a4, a4, 3
-; ZVFHMIN-NEXT: mv a5, a4
-; ZVFHMIN-NEXT: slli a4, a4, 2
-; ZVFHMIN-NEXT: add a4, a4, a5
-; ZVFHMIN-NEXT: add a4, sp, a4
-; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 5
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a3, a3, a4
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
; ZVFHMIN-NEXT: vmv4r.v v8, v24
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 5
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -12092,22 +11912,23 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v0, v16
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
@@ -12125,14 +11946,17 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a2
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
@@ -12140,19 +11964,16 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -12165,7 +11986,7 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
@@ -12177,7 +11998,7 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: slli a0, a0, 3
@@ -12519,50 +12340,50 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
-; ZVFHMIN-NEXT: mv a2, a1
-; ZVFHMIN-NEXT: slli a1, a1, 1
-; ZVFHMIN-NEXT: add a1, a1, a2
-; ZVFHMIN-NEXT: add a1, sp, a1
-; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
; ZVFHMIN-NEXT: vmv.v.x v24, a1
; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: mv a4, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a4
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v16, v8, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v8, v8, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a2
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v24, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: vslidedown.vx v24, v24, a3
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a4, a3, 5
; ZVFHMIN-NEXT: add a3, a4, a3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a3, a0, a2
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a4, a3, 5
; ZVFHMIN-NEXT: add a3, a4, a3
@@ -12570,17 +12391,14 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -12596,9 +12414,12 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
@@ -12630,17 +12451,14 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
@@ -12653,6 +12471,9 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -12714,24 +12535,16 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
-; ZVFHMIN-NEXT: add a1, sp, a1
-; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v16, a1
+; ZVFHMIN-NEXT: vmv.v.x v24, a1
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
-; ZVFHMIN-NEXT: mv a4, a1
-; ZVFHMIN-NEXT: slli a1, a1, 1
-; ZVFHMIN-NEXT: add a1, a1, a4
+; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: mv a4, a1
@@ -12741,13 +12554,10 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v16, v8, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v8, v8, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a2
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: mv a5, a4
@@ -12755,9 +12565,9 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a4, a4, a5
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v24, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: vslidedown.vx v24, v24, a3
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: mv a4, a3
@@ -12765,12 +12575,15 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a3, a3, a4
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a3, a0, a2
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: mv a4, a3
@@ -12780,12 +12593,15 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -12809,10 +12625,7 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
@@ -12869,7 +12682,10 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
@@ -12883,10 +12699,7 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
@@ -13301,9 +13114,6 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v16, v24, a2, v0.t
; ZVFHMIN-NEXT: sub a2, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a2
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 3
; ZVFHMIN-NEXT: mv a5, a4
@@ -13314,6 +13124,9 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
+; ZVFHMIN-NEXT: sltu a3, a0, a2
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
@@ -13489,9 +13302,6 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: sub a2, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a2
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -13499,6 +13309,9 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
+; ZVFHMIN-NEXT: sltu a3, a0, a2
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: vmv4r.v v8, v24
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
index 1d32049f930cc..42dd2dd28f614 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
@@ -182,22 +182,22 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
; CHECK-NEXT: addi a4, a4, 16
; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vslidedown.vx v7, v0, a2
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a3, a2, 4
@@ -585,22 +585,22 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
+; ZVFHMIN-NEXT: sltu a2, a0, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
index 0d10760e53e2b..91b9d2d4e3258 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
@@ -182,22 +182,22 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
; CHECK-NEXT: addi a4, a4, 16
; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vslidedown.vx v7, v0, a2
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a3, a2, 4
@@ -585,22 +585,22 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
+; ZVFHMIN-NEXT: sltu a2, a0, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
index b32346ffc2df3..92127a8e2f664 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
@@ -494,22 +494,22 @@ define <vscale x 32 x half> @vfmul_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
+; ZVFHMIN-NEXT: sltu a2, a0, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
@@ -689,19 +689,19 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a2, a0, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
index d8e8d12e3d86c..6213a190e5c12 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
@@ -710,14 +710,14 @@ define <vscale x 16 x double> @vfneg_vv_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-LABEL: vfneg_vv_nxv16f64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: srli a3, a1, 3
+; CHECK-NEXT: srli a2, a1, 3
+; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vfneg.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB44_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
index 533cb96560a49..622fbaade9e95 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
@@ -86,17 +86,17 @@ define <vscale x 7 x double> @vfpext_nxv7f32_nxv7f64(<vscale x 7 x float> %a, <v
define <vscale x 32 x float> @vfpext_nxv32f16_nxv32f32(<vscale x 32 x half> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vfpext_nxv32f16_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a1, a2, 1
-; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: srli a2, a2, 2
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB7_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
index 2dc3ced5e3081..14753384b6460 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
@@ -462,17 +462,17 @@ define <vscale x 2 x i64> @vfptosi_nxv2i64_nxv2f64_unmasked(<vscale x 2 x double
define <vscale x 32 x i16> @vfptosi_nxv32i16_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptosi_nxv32i16_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a1, a2, 1
-; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: srli a2, a2, 2
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB34_2
; CHECK-NEXT: # %bb.1:
@@ -490,17 +490,17 @@ define <vscale x 32 x i16> @vfptosi_nxv32i16_nxv32f32(<vscale x 32 x float> %va,
define <vscale x 32 x i32> @vfptosi_nxv32i32_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptosi_nxv32i32_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a1, a2, 1
-; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: srli a2, a2, 2
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB35_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
index ddd67b356540b..5073a806cc2a5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
@@ -462,17 +462,17 @@ define <vscale x 2 x i64> @vfptoui_nxv2i64_nxv2f64_unmasked(<vscale x 2 x double
define <vscale x 32 x i16> @vfptoui_nxv32i16_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptoui_nxv32i16_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a1, a2, 1
-; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: srli a2, a2, 2
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB34_2
; CHECK-NEXT: # %bb.1:
@@ -490,17 +490,17 @@ define <vscale x 32 x i16> @vfptoui_nxv32i16_nxv32f32(<vscale x 32 x float> %va,
define <vscale x 32 x i32> @vfptoui_nxv32i32_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptoui_nxv32i32_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a1, a2, 1
-; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: srli a2, a2, 2
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.rtz.xu.f.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB35_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
index 359a534508522..475707f27d7e9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
@@ -87,14 +87,14 @@ define <vscale x 16 x float> @vfptrunc_nxv16f32_nxv16f64(<vscale x 16 x double>
; CHECK-LABEL: vfptrunc_nxv16f32_nxv16f64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: srli a3, a1, 3
+; CHECK-NEXT: srli a2, a1, 3
+; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v28, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB7_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
index 365396a684fd7..63651bd3955bb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
@@ -710,14 +710,14 @@ define <vscale x 16 x double> @vfsqrt_vv_nxv16f64(<vscale x 16 x double> %va, <v
; CHECK-LABEL: vfsqrt_vv_nxv16f64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: srli a3, a1, 3
+; CHECK-NEXT: srli a2, a1, 3
+; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vfsqrt.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB44_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
index 9b7017f323bfd..54d42930ed724 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
@@ -372,22 +372,22 @@ define <vscale x 32 x bfloat> @vfsub_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
; CHECK-NEXT: addi a4, a4, 16
; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vslidedown.vx v7, v0, a2
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a3, a2, 4
@@ -555,19 +555,19 @@ define <vscale x 32 x bfloat> @vfsub_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v6, v0, a2
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: add a3, sp, a3
+; CHECK-NEXT: addi a3, a3, 16
+; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -1194,22 +1194,22 @@ define <vscale x 32 x half> @vfsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
+; ZVFHMIN-NEXT: sltu a2, a0, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
@@ -1389,19 +1389,19 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: sltu a2, a0, a3
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
index 719226503e7b2..7944afbbbb892 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
@@ -392,18 +392,18 @@ define <vscale x 128 x i8> @vmax_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: sltu a1, a2, a4
-; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a1, a1, a4
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: sub a3, a2, a1
+; CHECK-NEXT: sltu a4, a2, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vmax.vx v16, v16, a0, v0.t
-; CHECK-NEXT: bltu a2, a3, .LBB34_2
+; CHECK-NEXT: bltu a2, a1, .LBB34_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a3
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -928,17 +928,17 @@ define <vscale x 16 x i32> @vmax_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i
define <vscale x 32 x i32> @vmax_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vmax_vx_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a2, a3, 1
-; CHECK-NEXT: sub a4, a1, a2
-; CHECK-NEXT: sltu a5, a1, a4
-; CHECK-NEXT: addi a5, a5, -1
-; CHECK-NEXT: and a4, a5, a4
-; CHECK-NEXT: srli a3, a3, 2
-; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a3, a2, 2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
+; CHECK-NEXT: sub a3, a1, a2
+; CHECK-NEXT: sltu a4, a1, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vmax.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB80_2
; CHECK-NEXT: # %bb.1:
@@ -1001,15 +1001,15 @@ define <vscale x 32 x i32> @vmax_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i3
; RV64-LABEL: vmax_vx_nxv32i32_evl_nx8:
; RV64: # %bb.0:
; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: srli a3, a1, 2
; RV64-NEXT: slli a2, a1, 1
+; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: sub a3, a1, a2
; RV64-NEXT: sltu a4, a1, a3
; RV64-NEXT: addi a4, a4, -1
; RV64-NEXT: and a3, a4, a3
-; RV64-NEXT: srli a4, a1, 2
-; RV64-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
-; RV64-NEXT: vslidedown.vx v0, v0, a4
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vmax.vx v16, v16, a0, v0.t
; RV64-NEXT: bltu a1, a2, .LBB82_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
index 0acaa40ec8a16..0a3190f84c748 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
@@ -391,18 +391,18 @@ define <vscale x 128 x i8> @vmaxu_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: sltu a1, a2, a4
-; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a1, a1, a4
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: sub a3, a2, a1
+; CHECK-NEXT: sltu a4, a2, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vmaxu.vx v16, v16, a0, v0.t
-; CHECK-NEXT: bltu a2, a3, .LBB34_2
+; CHECK-NEXT: bltu a2, a1, .LBB34_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a3
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -927,17 +927,17 @@ define <vscale x 16 x i32> @vmaxu_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vmaxu_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vmaxu_vx_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a2, a3, 1
-; CHECK-NEXT: sub a4, a1, a2
-; CHECK-NEXT: sltu a5, a1, a4
-; CHECK-NEXT: addi a5, a5, -1
-; CHECK-NEXT: and a4, a5, a4
-; CHECK-NEXT: srli a3, a3, 2
-; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a3, a2, 2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
+; CHECK-NEXT: sub a3, a1, a2
+; CHECK-NEXT: sltu a4, a1, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vmaxu.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB80_2
; CHECK-NEXT: # %bb.1:
@@ -1000,15 +1000,15 @@ define <vscale x 32 x i32> @vmaxu_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i
; RV64-LABEL: vmaxu_vx_nxv32i32_evl_nx8:
; RV64: # %bb.0:
; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: srli a3, a1, 2
; RV64-NEXT: slli a2, a1, 1
+; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: sub a3, a1, a2
; RV64-NEXT: sltu a4, a1, a3
; RV64-NEXT: addi a4, a4, -1
; RV64-NEXT: and a3, a4, a3
-; RV64-NEXT: srli a4, a1, 2
-; RV64-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
-; RV64-NEXT: vslidedown.vx v0, v0, a4
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vmaxu.vx v16, v16, a0, v0.t
; RV64-NEXT: bltu a1, a2, .LBB82_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
index 0cb5dc152e635..ef94044613c6a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
@@ -392,18 +392,18 @@ define <vscale x 128 x i8> @vmin_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: sltu a1, a2, a4
-; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a1, a1, a4
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: sub a3, a2, a1
+; CHECK-NEXT: sltu a4, a2, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vmin.vx v16, v16, a0, v0.t
-; CHECK-NEXT: bltu a2, a3, .LBB34_2
+; CHECK-NEXT: bltu a2, a1, .LBB34_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a3
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -928,17 +928,17 @@ define <vscale x 16 x i32> @vmin_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i
define <vscale x 32 x i32> @vmin_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vmin_vx_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a2, a3, 1
-; CHECK-NEXT: sub a4, a1, a2
-; CHECK-NEXT: sltu a5, a1, a4
-; CHECK-NEXT: addi a5, a5, -1
-; CHECK-NEXT: and a4, a5, a4
-; CHECK-NEXT: srli a3, a3, 2
-; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a3, a2, 2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
+; CHECK-NEXT: sub a3, a1, a2
+; CHECK-NEXT: sltu a4, a1, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vmin.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB80_2
; CHECK-NEXT: # %bb.1:
@@ -1001,15 +1001,15 @@ define <vscale x 32 x i32> @vmin_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i3
; RV64-LABEL: vmin_vx_nxv32i32_evl_nx8:
; RV64: # %bb.0:
; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: srli a3, a1, 2
; RV64-NEXT: slli a2, a1, 1
+; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: sub a3, a1, a2
; RV64-NEXT: sltu a4, a1, a3
; RV64-NEXT: addi a4, a4, -1
; RV64-NEXT: and a3, a4, a3
-; RV64-NEXT: srli a4, a1, 2
-; RV64-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
-; RV64-NEXT: vslidedown.vx v0, v0, a4
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vmin.vx v16, v16, a0, v0.t
; RV64-NEXT: bltu a1, a2, .LBB82_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
index 56dcba4d4b347..40c2375849548 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
@@ -391,18 +391,18 @@ define <vscale x 128 x i8> @vminu_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: sltu a1, a2, a4
-; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a1, a1, a4
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: sub a3, a2, a1
+; CHECK-NEXT: sltu a4, a2, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vminu.vx v16, v16, a0, v0.t
-; CHECK-NEXT: bltu a2, a3, .LBB34_2
+; CHECK-NEXT: bltu a2, a1, .LBB34_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a3
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -927,17 +927,17 @@ define <vscale x 16 x i32> @vminu_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vminu_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vminu_vx_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a2, a3, 1
-; CHECK-NEXT: sub a4, a1, a2
-; CHECK-NEXT: sltu a5, a1, a4
-; CHECK-NEXT: addi a5, a5, -1
-; CHECK-NEXT: and a4, a5, a4
-; CHECK-NEXT: srli a3, a3, 2
-; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a3, a2, 2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
+; CHECK-NEXT: sub a3, a1, a2
+; CHECK-NEXT: sltu a4, a1, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vminu.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB80_2
; CHECK-NEXT: # %bb.1:
@@ -1000,15 +1000,15 @@ define <vscale x 32 x i32> @vminu_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i
; RV64-LABEL: vminu_vx_nxv32i32_evl_nx8:
; RV64: # %bb.0:
; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: srli a3, a1, 2
; RV64-NEXT: slli a2, a1, 1
+; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: sub a3, a1, a2
; RV64-NEXT: sltu a4, a1, a3
; RV64-NEXT: addi a4, a4, -1
; RV64-NEXT: and a3, a4, a3
-; RV64-NEXT: srli a4, a1, 2
-; RV64-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
-; RV64-NEXT: vslidedown.vx v0, v0, a4
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vminu.vx v16, v16, a0, v0.t
; RV64-NEXT: bltu a1, a2, .LBB82_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmseq.ll b/llvm/test/CodeGen/RISCV/rvv/vmseq.ll
index 003b7193e7873..4dadaaec903f4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmseq.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmseq.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vlse64.v v11, (a0), zero
+; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmseq.vv v11, v8, v10, v0.t
-; RV32-NEXT: vmv.v.v v0, v11
+; RV32-NEXT: vmseq.vv v10, v8, v11, v0.t
+; RV32-NEXT: vmv.v.v v0, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmseq_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmseq.vv v11, v8, v12, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmseq.vv v12, v8, v14, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmseq_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmseq.vv v13, v8, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmseq.vv v16, v8, v20, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsge.ll b/llvm/test/CodeGen/RISCV/rvv/vmsge.ll
index e892388079303..987271cf9e3a6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsge.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsge.ll
@@ -819,8 +819,8 @@ define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i8_i8_1(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: li a0, 99
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
@@ -1316,15 +1316,15 @@ define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vlse64.v v11, (a0), zero
+; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsle.vv v11, v10, v8, v0.t
-; RV32-NEXT: vmv.v.v v0, v11
+; RV32-NEXT: vmsle.vv v10, v11, v8, v0.t
+; RV32-NEXT: vmv.v.v v0, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1379,15 +1379,15 @@ define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsle.vv v11, v12, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmsle.vv v12, v14, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1442,15 +1442,15 @@ define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsle.vv v13, v16, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmsle.vv v16, v20, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
index db06aac7cec4f..f4f4e884e0cdb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
@@ -1278,15 +1278,15 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vlse64.v v11, (a0), zero
+; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsleu.vv v11, v10, v8, v0.t
-; RV32-NEXT: vmv.v.v v0, v11
+; RV32-NEXT: vmsleu.vv v10, v11, v8, v0.t
+; RV32-NEXT: vmv.v.v v0, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1341,15 +1341,15 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsleu.vv v11, v12, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmsleu.vv v12, v14, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1404,15 +1404,15 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsleu.vv v13, v16, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmsleu.vv v16, v20, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1545,8 +1545,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i8_i8_1(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: li a0, 99
+; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
index 68f9ad8325bf4..23d117a02505b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsgt_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vlse64.v v11, (a0), zero
+; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmslt.vv v11, v10, v8, v0.t
-; RV32-NEXT: vmv.v.v v0, v11
+; RV32-NEXT: vmslt.vv v10, v11, v8, v0.t
+; RV32-NEXT: vmv.v.v v0, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsgt_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmslt.vv v11, v12, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmslt.vv v12, v14, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsgt_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmslt.vv v13, v16, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmslt.vv v16, v20, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
index 82748be39bf1d..f546196038252 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vlse64.v v11, (a0), zero
+; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsltu.vv v11, v10, v8, v0.t
-; RV32-NEXT: vmv.v.v v0, v11
+; RV32-NEXT: vmsltu.vv v10, v11, v8, v0.t
+; RV32-NEXT: vmv.v.v v0, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsltu.vv v11, v12, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmsltu.vv v12, v14, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsltu.vv v13, v16, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmsltu.vv v16, v20, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsle.ll b/llvm/test/CodeGen/RISCV/rvv/vmsle.ll
index 7598e87d34357..02c6e644df646 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsle.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsle.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsle_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vlse64.v v11, (a0), zero
+; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsle.vv v11, v8, v10, v0.t
-; RV32-NEXT: vmv.v.v v0, v11
+; RV32-NEXT: vmsle.vv v10, v8, v11, v0.t
+; RV32-NEXT: vmv.v.v v0, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsle_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsle.vv v11, v8, v12, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmsle.vv v12, v8, v14, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsle_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsle.vv v13, v8, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmsle.vv v16, v8, v20, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
index df4db27660499..76989d2994749 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsleu_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vlse64.v v11, (a0), zero
+; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsleu.vv v11, v8, v10, v0.t
-; RV32-NEXT: vmv.v.v v0, v11
+; RV32-NEXT: vmsleu.vv v10, v8, v11, v0.t
+; RV32-NEXT: vmv.v.v v0, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsleu_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsleu.vv v11, v8, v12, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmsleu.vv v12, v8, v14, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsleu_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsleu.vv v13, v8, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmsleu.vv v16, v8, v20, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmslt.ll b/llvm/test/CodeGen/RISCV/rvv/vmslt.ll
index 3f6b8c709f700..6f6a07e6c02bc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmslt.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmslt.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmslt_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vlse64.v v11, (a0), zero
+; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmslt.vv v11, v8, v10, v0.t
-; RV32-NEXT: vmv.v.v v0, v11
+; RV32-NEXT: vmslt.vv v10, v8, v11, v0.t
+; RV32-NEXT: vmv.v.v v0, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmslt_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmslt.vv v11, v8, v12, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmslt.vv v12, v8, v14, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmslt_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmslt.vv v13, v8, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmslt.vv v16, v8, v20, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
index f1e055cf478ee..82ad07fc5b9ab 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsltu_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vlse64.v v11, (a0), zero
+; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsltu.vv v11, v8, v10, v0.t
-; RV32-NEXT: vmv.v.v v0, v11
+; RV32-NEXT: vmsltu.vv v10, v8, v11, v0.t
+; RV32-NEXT: vmv.v.v v0, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsltu_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsltu.vv v11, v8, v12, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmsltu.vv v12, v8, v14, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsltu_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsltu.vv v13, v8, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmsltu.vv v16, v8, v20, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsne.ll b/llvm/test/CodeGen/RISCV/rvv/vmsne.ll
index fff1815df2c8e..a485fdf4e505f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsne.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsne.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsne_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v10, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vlse64.v v11, (a0), zero
+; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsne.vv v11, v8, v10, v0.t
-; RV32-NEXT: vmv.v.v v0, v11
+; RV32-NEXT: vmsne.vv v10, v8, v11, v0.t
+; RV32-NEXT: vmv.v.v v0, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsne_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v12, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vlse64.v v14, (a0), zero
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsne.vv v11, v8, v12, v0.t
-; RV32-NEXT: vmv1r.v v0, v11
+; RV32-NEXT: vmsne.vv v12, v8, v14, v0.t
+; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsne_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vlse64.v v16, (a0), zero
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vlse64.v v20, (a0), zero
+; RV32-NEXT: vmv1r.v v16, v0
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsne.vv v13, v8, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v13
+; RV32-NEXT: vmsne.vv v16, v8, v20, v0.t
+; RV32-NEXT: vmv1r.v v0, v16
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll b/llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
index 0bb0339e1ded4..8e8622b3d71d4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
@@ -19,9 +19,9 @@ define iXLen @bool_vec(<vscale x 2 x i1> %src, <vscale x 2 x i1> %m, i32 %evl) {
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; RV64-NEXT: vfirst.m a1, v9, v0.t
; RV64-NEXT: bltz a1, .LBB0_2
@@ -46,9 +46,9 @@ define iXLen @bool_vec_zero_poison(<vscale x 2 x i1> %src, <vscale x 2 x i1> %m,
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64-NEXT: vmv1r.v v9, v0
-; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32
+; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; RV64-NEXT: vfirst.m a0, v9, v0.t
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
index b140166415d0e..3e81dcb29e559 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
@@ -6,8 +6,8 @@ define <2 x i1> @test_vp_reverse_v2i1_masked(<2 x i1> %src, <2 x i1> %mask, i32
; CHECK-LABEL: test_vp_reverse_v2i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmerge.vim v11, v10, 1, v0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v9, v0.t
@@ -45,8 +45,8 @@ define <4 x i1> @test_vp_reverse_v4i1_masked(<4 x i1> %src, <4 x i1> %mask, i32
; CHECK-LABEL: test_vp_reverse_v4i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmerge.vim v11, v10, 1, v0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vid.v v9, v0.t
@@ -84,8 +84,8 @@ define <8 x i1> @test_vp_reverse_v8i1_masked(<8 x i1> %src, <8 x i1> %mask, i32
; CHECK-LABEL: test_vp_reverse_v8i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmerge.vim v11, v10, 1, v0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vid.v v9, v0.t
@@ -123,8 +123,8 @@ define <16 x i1> @test_vp_reverse_v16i1_masked(<16 x i1> %src, <16 x i1> %mask,
; CHECK-LABEL: test_vp_reverse_v16i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vid.v v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
index 9ab5e98ea7f3f..510a18d8b756f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
@@ -5,8 +5,8 @@ define <vscale x 1 x i1> @test_vp_reverse_nxv1i1_masked(<vscale x 1 x i1> %src,
; CHECK-LABEL: test_vp_reverse_nxv1i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmerge.vim v11, v10, 1, v0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v9, v0.t
@@ -44,8 +44,8 @@ define <vscale x 2 x i1> @test_vp_reverse_nxv2i1_masked(<vscale x 2 x i1> %src,
; CHECK-LABEL: test_vp_reverse_nxv2i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmerge.vim v11, v10, 1, v0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vid.v v9, v0.t
@@ -83,8 +83,8 @@ define <vscale x 4 x i1> @test_vp_reverse_nxv4i1_masked(<vscale x 4 x i1> %src,
; CHECK-LABEL: test_vp_reverse_nxv4i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmerge.vim v11, v10, 1, v0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vid.v v9, v0.t
@@ -122,8 +122,8 @@ define <vscale x 8 x i1> @test_vp_reverse_nxv8i1_masked(<vscale x 8 x i1> %src,
; CHECK-LABEL: test_vp_reverse_nxv8i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
+; CHECK-NEXT: vmv.v.i v9, 0
+; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vid.v v8, v0.t
@@ -161,8 +161,8 @@ define <vscale x 16 x i1> @test_vp_reverse_nxv16i1_masked(<vscale x 16 x i1> %sr
; CHECK-LABEL: test_vp_reverse_nxv16i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v12, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vid.v v8, v0.t
@@ -201,8 +201,8 @@ define <vscale x 32 x i1> @test_vp_reverse_nxv32i1_masked(<vscale x 32 x i1> %sr
; CHECK-LABEL: test_vp_reverse_nxv32i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vim v16, v12, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
; CHECK-NEXT: vid.v v8, v0.t
@@ -243,12 +243,14 @@ define <vscale x 64 x i1> @test_vp_reverse_nxv64i1_masked(<vscale x 64 x i1> %sr
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v26, v8
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, ma
; CHECK-NEXT: vid.v v16
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: addi a2, a1, -1
; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: vsetvli a3, zero, e16, m2, ta, ma
; CHECK-NEXT: vrsub.vx v24, v16, a2
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vrgatherei16.vv v23, v8, v24
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
index fc6a96d00cdc2..e560b1a62197f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
@@ -9,9 +9,9 @@ define <2 x i1> @test_vp_splice_v2i1(<2 x i1> %va, <2 x i1> %vb, i32 zeroext %ev
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -27,9 +27,9 @@ define <2 x i1> @test_vp_splice_v2i1(<2 x i1> %va, <2 x i1> %vb, i32 zeroext %ev
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -51,9 +51,9 @@ define <2 x i1> @test_vp_splice_v2i1_negative_offset(<2 x i1> %va, <2 x i1> %vb,
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -69,9 +69,9 @@ define <2 x i1> @test_vp_splice_v2i1_negative_offset(<2 x i1> %va, <2 x i1> %vb,
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -139,9 +139,9 @@ define <4 x i1> @test_vp_splice_v4i1(<4 x i1> %va, <4 x i1> %vb, i32 zeroext %ev
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -157,9 +157,9 @@ define <4 x i1> @test_vp_splice_v4i1(<4 x i1> %va, <4 x i1> %vb, i32 zeroext %ev
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -181,9 +181,9 @@ define <4 x i1> @test_vp_splice_v4i1_negative_offset(<4 x i1> %va, <4 x i1> %vb,
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -199,9 +199,9 @@ define <4 x i1> @test_vp_splice_v4i1_negative_offset(<4 x i1> %va, <4 x i1> %vb,
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -269,9 +269,9 @@ define <8 x i1> @test_vp_splice_v8i1(<8 x i1> %va, <8 x i1> %vb, i32 zeroext %ev
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -287,9 +287,9 @@ define <8 x i1> @test_vp_splice_v8i1(<8 x i1> %va, <8 x i1> %vb, i32 zeroext %ev
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -311,9 +311,9 @@ define <8 x i1> @test_vp_splice_v8i1_negative_offset(<8 x i1> %va, <8 x i1> %vb,
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -329,9 +329,9 @@ define <8 x i1> @test_vp_splice_v8i1_negative_offset(<8 x i1> %va, <8 x i1> %vb,
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -399,9 +399,9 @@ define <16 x i1> @test_vp_splice_v16i1(<16 x i1> %va, <16 x i1> %vb, i32 zeroext
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -417,9 +417,9 @@ define <16 x i1> @test_vp_splice_v16i1(<16 x i1> %va, <16 x i1> %vb, i32 zeroext
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -441,9 +441,9 @@ define <16 x i1> @test_vp_splice_v16i1_negative_offset(<16 x i1> %va, <16 x i1>
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -459,9 +459,9 @@ define <16 x i1> @test_vp_splice_v16i1_negative_offset(<16 x i1> %va, <16 x i1>
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
index bd54f34554d4d..9e7379f52baf5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
@@ -7,9 +7,9 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1(<vscale x 1 x i1> %va, <vscale x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -25,9 +25,9 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1(<vscale x 1 x i1> %va, <vscale x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -49,9 +49,9 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1_negative_offset(<vscale x 1 x i1
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -67,9 +67,9 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1_negative_offset(<vscale x 1 x i1
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -137,9 +137,9 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1(<vscale x 2 x i1> %va, <vscale x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -155,9 +155,9 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1(<vscale x 2 x i1> %va, <vscale x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -179,9 +179,9 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1_negative_offset(<vscale x 2 x i1
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -197,9 +197,9 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1_negative_offset(<vscale x 2 x i1
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -267,9 +267,9 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1(<vscale x 4 x i1> %va, <vscale x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -285,9 +285,9 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1(<vscale x 4 x i1> %va, <vscale x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -309,9 +309,9 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1_negative_offset(<vscale x 4 x i1
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -327,9 +327,9 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1_negative_offset(<vscale x 4 x i1
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -397,9 +397,9 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1(<vscale x 8 x i1> %va, <vscale x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -415,9 +415,9 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1(<vscale x 8 x i1> %va, <vscale x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -439,9 +439,9 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1_negative_offset(<vscale x 8 x i1
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
+; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -457,9 +457,9 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1_negative_offset(<vscale x 8 x i1
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
+; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -527,9 +527,9 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1(<vscale x 16 x i1> %va, <vscal
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v12, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v12
@@ -545,9 +545,9 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1(<vscale x 16 x i1> %va, <vscal
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; VLDEP-NEXT: vmv1r.v v12, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v12
@@ -569,9 +569,9 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1_negative_offset(<vscale x 16 x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v12, v0
+; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v12
@@ -587,9 +587,9 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1_negative_offset(<vscale x 16 x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; VLDEP-NEXT: vmv1r.v v12, v0
+; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v12
@@ -659,9 +659,9 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1(<vscale x 32 x i1> %va, <vscal
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v16, v0
+; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: vmv1r.v v0, v16
@@ -677,9 +677,9 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1(<vscale x 32 x i1> %va, <vscal
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; VLDEP-NEXT: vmv1r.v v16, v0
+; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: vmv1r.v v0, v16
@@ -701,9 +701,9 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1_negative_offset(<vscale x 32 x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v16, v0
+; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: vmv1r.v v0, v16
@@ -719,9 +719,9 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1_negative_offset(<vscale x 32 x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; VLDEP-NEXT: vmv1r.v v16, v0
+; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: vmv1r.v v0, v16
@@ -791,9 +791,9 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1(<vscale x 64 x i1> %va, <vscal
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v24, v0
+; NOVLDEP-NEXT: vmv.v.i v16, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v16, 0
; NOVLDEP-NEXT: vmv1r.v v0, v24
@@ -809,9 +809,9 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1(<vscale x 64 x i1> %va, <vscal
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; VLDEP-NEXT: vmv1r.v v24, v0
+; VLDEP-NEXT: vmv.v.i v16, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; VLDEP-NEXT: vmv.v.i v16, 0
; VLDEP-NEXT: vmv1r.v v0, v24
@@ -833,9 +833,9 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1_negative_offset(<vscale x 64 x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v24, v0
+; NOVLDEP-NEXT: vmv.v.i v16, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmv.v.i v8, 0
-; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v16, 0
; NOVLDEP-NEXT: vmv1r.v v0, v24
@@ -851,9 +851,9 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1_negative_offset(<vscale x 64 x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; VLDEP-NEXT: vmv1r.v v24, v0
+; VLDEP-NEXT: vmv.v.i v16, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmv.v.i v8, 0
-; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
+; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; VLDEP-NEXT: vmv.v.i v16, 0
; VLDEP-NEXT: vmv1r.v v0, v24
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll b/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
index d569dc84ac174..77808ad541088 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
@@ -363,18 +363,18 @@ define i32 @masked_load_store_factor2_v2_shared_mask_extract(<vscale x 2 x i1> %
; RV32-NEXT: li a3, -1
; RV32-NEXT: vmerge.vim v9, v8, 1, v0
; RV32-NEXT: vmv1r.v v12, v0
-; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma
-; RV32-NEXT: vmv.v.i v10, 0
-; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV32-NEXT: vwaddu.vv v11, v9, v9
-; RV32-NEXT: vwmaccu.vx v11, a3, v9
-; RV32-NEXT: vmsne.vi v0, v11, 0
-; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma
-; RV32-NEXT: vmerge.vim v9, v10, 1, v0
+; RV32-NEXT: vwaddu.vv v10, v9, v9
+; RV32-NEXT: vwmaccu.vx v10, a3, v9
; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma
+; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: srli a3, a3, 2
+; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; RV32-NEXT: vmsne.vi v0, v10, 0
; RV32-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; RV32-NEXT: vslidedown.vx v10, v11, a3
+; RV32-NEXT: vslidedown.vx v10, v10, a3
+; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma
+; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; RV32-NEXT: vmsne.vi v0, v10, 0
; RV32-NEXT: vmerge.vim v8, v8, 1, v0
@@ -404,12 +404,12 @@ define i32 @masked_load_store_factor2_v2_shared_mask_extract(<vscale x 2 x i1> %
; RV64-NEXT: vmv1r.v v12, v0
; RV64-NEXT: vwaddu.vv v11, v10, v10
; RV64-NEXT: vwmaccu.vx v11, a2, v10
-; RV64-NEXT: vmsne.vi v0, v11, 0
-; RV64-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: srli a2, a2, 2
+; RV64-NEXT: vmsne.vi v0, v11, 0
+; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vx v10, v11, a2
+; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV64-NEXT: vmsne.vi v0, v10, 0
; RV64-NEXT: vmerge.vim v8, v8, 1, v0
@@ -502,13 +502,13 @@ define {<vscale x 2 x i32>, <vscale x 2 x i32>} @not_same_mask(<vscale x 2 x i1>
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
; RV32-NEXT: vmv1r.v v10, v0
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vmv.v.i v8, 0
-; RV32-NEXT: vmerge.vim v9, v8, 1, v0
; RV32-NEXT: slli a1, a1, 1
+; RV32-NEXT: vmv.v.i v12, 0
; RV32-NEXT: li a2, -1
+; RV32-NEXT: vmv1r.v v0, v8
+; RV32-NEXT: vmerge.vim v9, v12, 1, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmerge.vim v10, v8, 1, v0
+; RV32-NEXT: vmerge.vim v10, v12, 1, v0
; RV32-NEXT: vwaddu.vv v11, v10, v9
; RV32-NEXT: vwmaccu.vx v11, a2, v9
; RV32-NEXT: csrr a2, vlenb
@@ -523,7 +523,7 @@ define {<vscale x 2 x i32>, <vscale x 2 x i32>} @not_same_mask(<vscale x 2 x i1>
; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV32-NEXT: vmsne.vi v0, v10, 0
-; RV32-NEXT: vmerge.vim v8, v8, 1, v0
+; RV32-NEXT: vmerge.vim v8, v12, 1, v0
; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; RV32-NEXT: vslideup.vx v9, v8, a2
; RV32-NEXT: vmsne.vi v0, v9, 0
@@ -538,31 +538,31 @@ define {<vscale x 2 x i32>, <vscale x 2 x i32>} @not_same_mask(<vscale x 2 x i1>
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
; RV64-NEXT: vmv1r.v v11, v0
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vmv.v.i v8, 0
-; RV64-NEXT: vmerge.vim v9, v8, 1, v0
+; RV64-NEXT: vmv.v.i v13, 0
; RV64-NEXT: li a2, -1
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv.v.i v10, 0
-; RV64-NEXT: vmv1r.v v0, v11
+; RV64-NEXT: vmv.v.i v9, 0
+; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmerge.vim v11, v8, 1, v0
-; RV64-NEXT: vwaddu.vv v12, v11, v9
-; RV64-NEXT: vwmaccu.vx v12, a2, v9
+; RV64-NEXT: vmerge.vim v10, v13, 1, v0
+; RV64-NEXT: vmv1r.v v0, v11
+; RV64-NEXT: vmerge.vim v11, v13, 1, v0
+; RV64-NEXT: vwaddu.vv v12, v11, v10
+; RV64-NEXT: vwmaccu.vx v12, a2, v10
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a1, a1, 33
; RV64-NEXT: srli a2, a2, 2
; RV64-NEXT: srli a1, a1, 32
; RV64-NEXT: vmsne.vi v0, v12, 0
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vslidedown.vx v9, v12, a2
-; RV64-NEXT: vmerge.vim v10, v10, 1, v0
+; RV64-NEXT: vslidedown.vx v10, v12, a2
+; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmsne.vi v0, v9, 0
-; RV64-NEXT: vmerge.vim v8, v8, 1, v0
-; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vslideup.vx v10, v8, a2
; RV64-NEXT: vmsne.vi v0, v10, 0
+; RV64-NEXT: vmerge.vim v8, v13, 1, v0
+; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; RV64-NEXT: vslideup.vx v9, v8, a2
+; RV64-NEXT: vmsne.vi v0, v9, 0
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma
; RV64-NEXT: vle32.v v10, (a0), v0.t
; RV64-NEXT: li a0, 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
index 258014a023105..210bf47e4dff5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
@@ -255,12 +255,12 @@ define <vscale x 32 x i8> @vpgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8
; RV32-NEXT: sltu a5, a1, a4
; RV32-NEXT: addi a5, a5, -1
; RV32-NEXT: and a4, a5, a4
-; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
-; RV32-NEXT: vsext.vf4 v16, v10
-; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; RV32-NEXT: vmv1r.v v12, v0
; RV32-NEXT: vslidedown.vx v0, v0, a3
-; RV32-NEXT: vsetvli zero, a4, e8, m2, ta, ma
+; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
+; RV32-NEXT: vsext.vf4 v16, v10
+; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; RV32-NEXT: vluxei32.v v10, (a0), v16, v0.t
; RV32-NEXT: bltu a1, a2, .LBB12_2
; RV32-NEXT: # %bb.1:
@@ -277,11 +277,14 @@ define <vscale x 32 x i8> @vpgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8
; RV64: # %bb.0:
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a3, a2, 1
-; RV64-NEXT: srli a7, a2, 2
-; RV64-NEXT: sub a4, a1, a3
-; RV64-NEXT: sltu a5, a1, a4
-; RV64-NEXT: addi a5, a5, -1
-; RV64-NEXT: and a5, a5, a4
+; RV64-NEXT: srli a4, a2, 2
+; RV64-NEXT: sub a5, a1, a3
+; RV64-NEXT: vsetvli a6, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v12, v0
+; RV64-NEXT: vslidedown.vx v14, v0, a4
+; RV64-NEXT: sltu a4, a1, a5
+; RV64-NEXT: addi a4, a4, -1
+; RV64-NEXT: and a5, a4, a5
; RV64-NEXT: sub a4, a5, a2
; RV64-NEXT: sltu a6, a5, a4
; RV64-NEXT: addi a6, a6, -1
@@ -289,12 +292,9 @@ define <vscale x 32 x i8> @vpgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8
; RV64-NEXT: srli a4, a2, 3
; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v11
-; RV64-NEXT: vmv1r.v v12, v0
-; RV64-NEXT: vsetvli t0, zero, e8, mf2, ta, ma
-; RV64-NEXT: vslidedown.vx v11, v0, a7
-; RV64-NEXT: vmv1r.v v13, v11
+; RV64-NEXT: vmv1r.v v13, v14
; RV64-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v0, v11, a4
+; RV64-NEXT: vslidedown.vx v0, v14, a4
; RV64-NEXT: bltu a5, a2, .LBB12_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a5, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
index 6ba9684228449..2497f43fe3480 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
@@ -540,30 +540,30 @@ define <vscale x 128 x i8> @vpmerge_vv_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv8r.v v24, v16
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a4, a0, a1
-; CHECK-NEXT: sub a5, a3, a1
-; CHECK-NEXT: vl8r.v v16, (a4)
-; CHECK-NEXT: sltu a4, a3, a5
; CHECK-NEXT: vlm.v v0, (a2)
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a2, a0, a1
+; CHECK-NEXT: sub a4, a3, a1
+; CHECK-NEXT: vl8r.v v24, (a2)
+; CHECK-NEXT: sltu a2, a3, a4
; CHECK-NEXT: vl8r.v v8, (a0)
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a4, a4, a5
-; CHECK-NEXT: vsetvli zero, a4, e8, m8, tu, ma
-; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a4
+; CHECK-NEXT: vsetvli zero, a2, e8, m8, tu, ma
+; CHECK-NEXT: vmerge.vvm v24, v24, v16, v0
; CHECK-NEXT: bltu a3, a1, .LBB35_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: .LBB35_2:
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
+; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
+; CHECK-NEXT: vmv8r.v v16, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -580,18 +580,18 @@ define <vscale x 128 x i8> @vpmerge_vx_nxv128i8(i8 %a, <vscale x 128 x i8> %vb,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: sltu a1, a2, a4
-; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a1, a1, a4
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: sub a3, a2, a1
+; CHECK-NEXT: sltu a4, a2, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: vsetvli zero, a3, e8, m8, tu, ma
; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0
-; CHECK-NEXT: bltu a2, a3, .LBB36_2
+; CHECK-NEXT: bltu a2, a1, .LBB36_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a3
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB36_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, tu, ma
@@ -608,18 +608,18 @@ define <vscale x 128 x i8> @vpmerge_vi_nxv128i8(<vscale x 128 x i8> %vb, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: sltu a0, a1, a3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a3
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, ma
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: sub a2, a1, a0
+; CHECK-NEXT: sltu a3, a1, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e8, m8, tu, ma
; CHECK-NEXT: vmerge.vim v16, v16, 2, v0
-; CHECK-NEXT: bltu a1, a2, .LBB37_2
+; CHECK-NEXT: bltu a1, a0, .LBB37_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: .LBB37_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
index 25e4f2cba1edf..15b3508d8e20d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
@@ -85,15 +85,15 @@ define half @vpreduce_ord_fadd_nxv4f16(half %s, <vscale x 4 x half> %v, <vscale
define half @vpreduce_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_fadd_nxv64f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a2, a3, 2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a1, a2, 1
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v25, v0, a1
; CHECK-NEXT: sub a1, a0, a2
-; CHECK-NEXT: sltu a4, a0, a1
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a1, a4, a1
-; CHECK-NEXT: srli a3, a3, 1
-; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v25, v0, a3
+; CHECK-NEXT: sltu a3, a0, a1
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a1, a3, a1
; CHECK-NEXT: bltu a0, a2, .LBB6_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
@@ -114,15 +114,15 @@ define half @vpreduce_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x
define half @vpreduce_ord_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_ord_fadd_nxv64f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a2, a3, 2
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: srli a1, a2, 1
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v25, v0, a1
; CHECK-NEXT: sub a1, a0, a2
-; CHECK-NEXT: sltu a4, a0, a1
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a1, a4, a1
-; CHECK-NEXT: srli a3, a3, 1
-; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v25, v0, a3
+; CHECK-NEXT: sltu a3, a0, a1
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a1, a3, a1
; CHECK-NEXT: bltu a0, a2, .LBB7_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
index dcd1af0c12879..295d146ea7a7a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
@@ -878,15 +878,15 @@ define signext i32 @vpreduce_umax_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v,
define signext i32 @vpreduce_umax_nxv32i32(i32 signext %s, <vscale x 32 x i32> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_umax_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a4, vlenb
-; CHECK-NEXT: slli a3, a4, 1
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: srli a2, a3, 2
+; CHECK-NEXT: slli a3, a3, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v25, v0, a2
; CHECK-NEXT: sub a2, a1, a3
-; CHECK-NEXT: sltu a5, a1, a2
-; CHECK-NEXT: addi a5, a5, -1
-; CHECK-NEXT: and a2, a5, a2
-; CHECK-NEXT: srli a4, a4, 2
-; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v25, v0, a4
+; CHECK-NEXT: sltu a4, a1, a2
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a2, a4, a2
; CHECK-NEXT: bltu a1, a3, .LBB67_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, a3
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
index 04dfcbe2945aa..e197ada5706ab 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
@@ -553,18 +553,18 @@ define <vscale x 128 x i8> @vsadd_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: sltu a0, a1, a3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a3
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: sub a2, a1, a0
+; CHECK-NEXT: sltu a3, a1, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
-; CHECK-NEXT: bltu a1, a2, .LBB50_2
+; CHECK-NEXT: bltu a1, a0, .LBB50_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
@@ -1305,17 +1305,17 @@ define <vscale x 16 x i32> @vsadd_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vsadd_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a1, a2, 1
-; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: srli a2, a2, 2
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB118_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
index cf6899fa4933b..c35b8af7ffc4f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
@@ -552,18 +552,18 @@ define <vscale x 128 x i8> @vsaddu_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: sltu a0, a1, a3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a0, a0, a3
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: sub a2, a1, a0
+; CHECK-NEXT: sltu a3, a1, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
-; CHECK-NEXT: bltu a1, a2, .LBB50_2
+; CHECK-NEXT: bltu a1, a0, .LBB50_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
@@ -1304,17 +1304,17 @@ define <vscale x 16 x i32> @vsaddu_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vsaddu_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a1, a2, 1
-; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: srli a2, a2, 2
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB118_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll b/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
index 373044da3e02a..dcf88bd34b00b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
@@ -436,8 +436,8 @@ define <vscale x 2 x i32> @vwop_vscale_zext_i1i32_multiple_users(ptr %x, ptr %y,
; NO_FOLDING: # %bb.0:
; NO_FOLDING-NEXT: vsetvli a3, zero, e32, m1, ta, mu
; NO_FOLDING-NEXT: vlm.v v0, (a0)
-; NO_FOLDING-NEXT: vmv.v.i v8, 0
; NO_FOLDING-NEXT: vlm.v v10, (a2)
+; NO_FOLDING-NEXT: vmv.v.i v8, 0
; NO_FOLDING-NEXT: vlm.v v11, (a1)
; NO_FOLDING-NEXT: vmerge.vim v8, v8, 1, v0
; NO_FOLDING-NEXT: vmv.v.v v9, v8
@@ -454,8 +454,8 @@ define <vscale x 2 x i32> @vwop_vscale_zext_i1i32_multiple_users(ptr %x, ptr %y,
; FOLDING: # %bb.0:
; FOLDING-NEXT: vsetvli a3, zero, e32, m1, ta, mu
; FOLDING-NEXT: vlm.v v0, (a0)
-; FOLDING-NEXT: vmv.v.i v8, 0
; FOLDING-NEXT: vlm.v v10, (a2)
+; FOLDING-NEXT: vmv.v.i v8, 0
; FOLDING-NEXT: vlm.v v11, (a1)
; FOLDING-NEXT: vmerge.vim v8, v8, 1, v0
; FOLDING-NEXT: vmv.v.v v9, v8
@@ -486,8 +486,8 @@ define <vscale x 2 x i8> @vwop_vscale_zext_i1i8_multiple_users(ptr %x, ptr %y, p
; NO_FOLDING: # %bb.0:
; NO_FOLDING-NEXT: vsetvli a3, zero, e8, mf4, ta, mu
; NO_FOLDING-NEXT: vlm.v v0, (a0)
-; NO_FOLDING-NEXT: vmv.v.i v8, 0
; NO_FOLDING-NEXT: vlm.v v10, (a2)
+; NO_FOLDING-NEXT: vmv.v.i v8, 0
; NO_FOLDING-NEXT: vlm.v v11, (a1)
; NO_FOLDING-NEXT: vmerge.vim v8, v8, 1, v0
; NO_FOLDING-NEXT: vmv1r.v v9, v8
@@ -504,8 +504,8 @@ define <vscale x 2 x i8> @vwop_vscale_zext_i1i8_multiple_users(ptr %x, ptr %y, p
; FOLDING: # %bb.0:
; FOLDING-NEXT: vsetvli a3, zero, e8, mf4, ta, mu
; FOLDING-NEXT: vlm.v v0, (a0)
-; FOLDING-NEXT: vmv.v.i v8, 0
; FOLDING-NEXT: vlm.v v10, (a2)
+; FOLDING-NEXT: vmv.v.i v8, 0
; FOLDING-NEXT: vlm.v v11, (a1)
; FOLDING-NEXT: vmerge.vim v8, v8, 1, v0
; FOLDING-NEXT: vmv1r.v v9, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
index 759880629ecff..1391f0a564708 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
@@ -494,17 +494,17 @@ define <vscale x 8 x double> @vfmerge_nzv_nxv8f64(<vscale x 8 x double> %va, <vs
define <vscale x 16 x double> @vselect_combine_regression(<vscale x 16 x i64> %va, <vscale x 16 x double> %vb) {
; CHECK-LABEL: vselect_combine_regression:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmv8r.v v24, v16
-; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu
+; CHECK-NEXT: vmseq.vi v24, v16, 0
; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: vle64.v v8, (a0), v0.t
-; CHECK-NEXT: vmseq.vi v0, v24, 0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: vle64.v v16, (a0), v0.t
+; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vle64.v v16, (a1), v0.t
; CHECK-NEXT: ret
%cond = icmp eq <vscale x 16 x i64> %va, zeroinitializer
%sel = select <vscale x 16 x i1> %cond, <vscale x 16 x double> %vb, <vscale x 16 x double> zeroinitializer
@@ -523,11 +523,11 @@ define void @vselect_legalize_regression(<vscale x 16 x double> %a, <vscale x 16
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
; CHECK-NEXT: vmand.mm v0, v0, v7
-; CHECK-NEXT: vsetvli a3, zero, e64, m8, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: vslidedown.vx v7, v0, a2
; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, ma
+; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: add a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
index 7f594f398288a..61de230f9c8d1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
@@ -137,17 +137,17 @@ define <vscale x 2 x i64> @vsext_nxv2i32_nxv2i64_unmasked(<vscale x 2 x i32> %a,
define <vscale x 32 x i32> @vsext_nxv32i8_nxv32i32(<vscale x 32 x i8> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vsext_nxv32i8_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a1, a2, 1
-; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: srli a2, a2, 2
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vsext.vf4 v16, v10, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB12_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
index 2f79cf0df6645..6a96645620d0c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
@@ -471,17 +471,17 @@ define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i64_unmasked(<vscale x 2 x i64
define <vscale x 32 x half> @vsitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: vsitofp_nxv32f16_nxv32i32:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: csrr a2, vlenb
-; ZVFH-NEXT: slli a1, a2, 1
-; ZVFH-NEXT: sub a3, a0, a1
-; ZVFH-NEXT: sltu a4, a0, a3
-; ZVFH-NEXT: addi a4, a4, -1
-; ZVFH-NEXT: and a3, a4, a3
-; ZVFH-NEXT: srli a2, a2, 2
-; ZVFH-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFH-NEXT: csrr a1, vlenb
+; ZVFH-NEXT: srli a2, a1, 2
+; ZVFH-NEXT: slli a1, a1, 1
+; ZVFH-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; ZVFH-NEXT: vmv1r.v v24, v0
; ZVFH-NEXT: vslidedown.vx v0, v0, a2
-; ZVFH-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFH-NEXT: sub a2, a0, a1
+; ZVFH-NEXT: sltu a3, a0, a2
+; ZVFH-NEXT: addi a3, a3, -1
+; ZVFH-NEXT: and a2, a3, a2
+; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFH-NEXT: vfncvt.f.x.w v28, v16, v0.t
; ZVFH-NEXT: bltu a0, a1, .LBB34_2
; ZVFH-NEXT: # %bb.1:
@@ -495,17 +495,17 @@ define <vscale x 32 x half> @vsitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va,
;
; ZVFHMIN-LABEL: vsitofp_nxv32f16_nxv32i32:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a1, a2, 1
-; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
-; ZVFHMIN-NEXT: srli a2, a2, 2
-; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: srli a2, a1, 2
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
-; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a3, a0, a2
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v24
@@ -527,17 +527,17 @@ define <vscale x 32 x half> @vsitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va,
define <vscale x 32 x float> @vsitofp_nxv32f32_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_nxv32f32_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a1, a2, 1
-; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: srli a2, a2, 2
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB35_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
index 2acc910226174..6c0160591f245 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
@@ -570,23 +570,23 @@ define <vscale x 128 x i8> @vssub_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: sub a3, a1, a2
-; CHECK-NEXT: sltu a4, a1, a3
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: sub a2, a1, a0
+; CHECK-NEXT: sltu a3, a1, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a3, a3, a2
+; CHECK-NEXT: li a2, -1
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t
-; CHECK-NEXT: bltu a1, a2, .LBB50_2
+; CHECK-NEXT: vssub.vx v16, v16, a2, v0.t
+; CHECK-NEXT: bltu a1, a0, .LBB50_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vssub.vx v8, v8, a2, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 128 x i8> @llvm.vp.ssub.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> %m, i32 %evl)
ret <vscale x 128 x i8> %v
@@ -1346,18 +1346,18 @@ define <vscale x 16 x i32> @vssub_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vssub_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a1, a3, 1
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a4, a0, a2
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a4, a4, a2
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a3, a3, a2
; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: srli a3, a3, 2
-; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vssub.vx v16, v16, a2, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB118_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
index 3d2fb62ef39a5..a041b8478b0bb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
@@ -568,23 +568,23 @@ define <vscale x 128 x i8> @vssubu_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: sub a3, a1, a2
-; CHECK-NEXT: sltu a4, a1, a3
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: li a0, -1
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: sub a2, a1, a0
+; CHECK-NEXT: sltu a3, a1, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a3, a3, a2
+; CHECK-NEXT: li a2, -1
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t
-; CHECK-NEXT: bltu a1, a2, .LBB50_2
+; CHECK-NEXT: vssubu.vx v16, v16, a2, v0.t
+; CHECK-NEXT: bltu a1, a0, .LBB50_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a2
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
+; CHECK-NEXT: vssubu.vx v8, v8, a2, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 128 x i8> @llvm.vp.usub.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> %m, i32 %evl)
ret <vscale x 128 x i8> %v
@@ -1344,18 +1344,18 @@ define <vscale x 16 x i32> @vssubu_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vssubu_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a1, a3, 1
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a4, a0, a2
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a4, a4, a2
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a3, a3, a2
; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: srli a3, a3, 2
-; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vssubu.vx v16, v16, a2, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB118_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
index 12d2f73f7baa9..63f6cadbc123c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
@@ -142,14 +142,14 @@ define <vscale x 15 x i16> @vtrunc_nxv15i16_nxv15i64(<vscale x 15 x i64> %a, <vs
; CHECK-LABEL: vtrunc_nxv15i16_nxv15i64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: srli a3, a1, 3
+; CHECK-NEXT: srli a2, a1, 3
+; CHECK-NEXT: sub a3, a0, a1
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v28, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: sltu a2, a0, a3
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
@@ -194,17 +194,17 @@ define <vscale x 2 x i32> @vtrunc_nxv2i32_nxv2i64_unmasked(<vscale x 2 x i64> %a
define <vscale x 32 x i7> @vtrunc_nxv32i7_nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv32i7_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a1, a2, 1
-; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: srli a2, a2, 2
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v28, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v18, v24, 0, v0.t
@@ -226,17 +226,17 @@ define <vscale x 32 x i7> @vtrunc_nxv32i7_nxv32i32(<vscale x 32 x i32> %a, <vsca
define <vscale x 32 x i8> @vtrunc_nxv32i8_nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv32i8_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a1, a2, 1
-; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: srli a2, a2, 2
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v28, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v18, v24, 0, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
index ef376162a8022..a23fb0c7db18b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
@@ -471,17 +471,17 @@ define <vscale x 2 x double> @vuitofp_nxv2f64_nxv2i64_unmasked(<vscale x 2 x i64
define <vscale x 32 x half> @vuitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: vuitofp_nxv32f16_nxv32i32:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: csrr a2, vlenb
-; ZVFH-NEXT: slli a1, a2, 1
-; ZVFH-NEXT: sub a3, a0, a1
-; ZVFH-NEXT: sltu a4, a0, a3
-; ZVFH-NEXT: addi a4, a4, -1
-; ZVFH-NEXT: and a3, a4, a3
-; ZVFH-NEXT: srli a2, a2, 2
-; ZVFH-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFH-NEXT: csrr a1, vlenb
+; ZVFH-NEXT: srli a2, a1, 2
+; ZVFH-NEXT: slli a1, a1, 1
+; ZVFH-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; ZVFH-NEXT: vmv1r.v v24, v0
; ZVFH-NEXT: vslidedown.vx v0, v0, a2
-; ZVFH-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFH-NEXT: sub a2, a0, a1
+; ZVFH-NEXT: sltu a3, a0, a2
+; ZVFH-NEXT: addi a3, a3, -1
+; ZVFH-NEXT: and a2, a3, a2
+; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFH-NEXT: vfncvt.f.xu.w v28, v16, v0.t
; ZVFH-NEXT: bltu a0, a1, .LBB34_2
; ZVFH-NEXT: # %bb.1:
@@ -495,17 +495,17 @@ define <vscale x 32 x half> @vuitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va,
;
; ZVFHMIN-LABEL: vuitofp_nxv32f16_nxv32i32:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a1, a2, 1
-; ZVFHMIN-NEXT: sub a3, a0, a1
-; ZVFHMIN-NEXT: sltu a4, a0, a3
-; ZVFHMIN-NEXT: addi a4, a4, -1
-; ZVFHMIN-NEXT: and a3, a4, a3
-; ZVFHMIN-NEXT: srli a2, a2, 2
-; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: srli a2, a1, 2
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
-; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a3, a0, a2
+; ZVFHMIN-NEXT: addi a3, a3, -1
+; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.f.xu.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v24
@@ -527,17 +527,17 @@ define <vscale x 32 x half> @vuitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va,
define <vscale x 32 x float> @vuitofp_nxv32f32_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_nxv32f32_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a1, a2, 1
-; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: srli a2, a2, 2
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB35_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
index 78ec7457e4064..d3ec428c825ee 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
@@ -137,17 +137,17 @@ define <vscale x 2 x i64> @vzext_nxv2i32_nxv2i64_unmasked(<vscale x 2 x i32> %a,
define <vscale x 32 x i32> @vzext_nxv32i8_nxv32i32(<vscale x 32 x i8> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vzext_nxv32i8_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a1, a2, 1
-; CHECK-NEXT: sub a3, a0, a1
-; CHECK-NEXT: sltu a4, a0, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: srli a2, a2, 2
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: srli a2, a1, 2
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vzext.vf4 v16, v10, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB12_2
; CHECK-NEXT: # %bb.1:
>From 4e46f4471617225f811ea32f2d15e7d3c0b790fb Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Wed, 21 Jan 2026 20:05:03 +0800
Subject: [PATCH 5/5] Revert "[RISCV] Change the limit of register pressure
VMV0 to 2"
This reverts commit 5f8019be5952efa8cc70f90991311df9e6afc97f.
---
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 2 +-
.../CodeGen/RISCV/combine-storetomstore.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/abs-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll | 60 +-
llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll | 8 +-
.../RISCV/rvv/combine-reduce-add-to-vcpop.ll | 374 +++--
.../RISCV/rvv/constant-folding-crash.ll | 10 +-
llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll | 72 +-
llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll | 187 ++-
llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll | 88 +-
llvm/test/CodeGen/RISCV/rvv/expandload.ll | 309 ++--
llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll | 42 +-
.../CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-bitreverse-vp.ll | 61 +-
.../RISCV/rvv/fixed-vectors-bswap-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-ceil-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-ctlz-vp.ll | 1084 +++++---------
.../RISCV/rvv/fixed-vectors-ctpop-vp.ll | 362 +++--
.../RISCV/rvv/fixed-vectors-cttz-vp.ll | 888 +++++-------
.../RISCV/rvv/fixed-vectors-extract-i1.ll | 108 +-
.../RISCV/rvv/fixed-vectors-floor-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-fmaximum-vp.ll | 27 +-
.../RISCV/rvv/fixed-vectors-fminimum-vp.ll | 27 +-
.../RISCV/rvv/fixed-vectors-fpext-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-fptosi-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-fptoui-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-fptrunc-vp.ll | 2 +-
.../rvv/fixed-vectors-interleaved-access.ll | 593 ++++----
.../rvv/fixed-vectors-reduction-fp-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-reduction-fp.ll | 150 +-
.../rvv/fixed-vectors-reduction-int-vp.ll | 4 +-
.../rvv/fixed-vectors-reduction-mask-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-round-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-roundeven-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-roundtozero-vp.ll | 4 +-
.../RISCV/rvv/fixed-vectors-setcc-int-vp.ll | 30 +-
.../RISCV/rvv/fixed-vectors-sext-vp.ll | 2 +-
.../rvv/fixed-vectors-shuffle-deinterleave.ll | 6 +-
.../fixed-vectors-shuffle-deinterleave2.ll | 13 +-
.../RISCV/rvv/fixed-vectors-sitofp-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-strided-vpload.ll | 29 +-
.../RISCV/rvv/fixed-vectors-trunc-vp.ll | 566 ++++----
.../RISCV/rvv/fixed-vectors-uitofp-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-vadd-vp.ll | 15 +-
.../RISCV/rvv/fixed-vectors-vfabs-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-vfneg-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-vfsqrt-vp.ll | 2 +-
.../RISCV/rvv/fixed-vectors-vmax-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-vmaxu-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-vmin-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-vminu-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-vsadd-vp.ll | 15 +-
.../RISCV/rvv/fixed-vectors-vsaddu-vp.ll | 15 +-
.../RISCV/rvv/fixed-vectors-vselect-vp.ll | 10 +-
.../RISCV/rvv/fixed-vectors-vssub-vp.ll | 13 +-
.../RISCV/rvv/fixed-vectors-vssubu-vp.ll | 13 +-
.../RISCV/rvv/fixed-vectors-zext-vp.ll | 2 +-
llvm/test/CodeGen/RISCV/rvv/floor-vp.ll | 8 +-
.../test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll | 66 +-
llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll | 121 +-
.../test/CodeGen/RISCV/rvv/fminimum-sdnode.ll | 66 +-
llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll | 121 +-
llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll | 141 +-
.../CodeGen/RISCV/rvv/insert-subvector.ll | 2 +-
llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll | 10 +-
.../test/CodeGen/RISCV/rvv/mscatter-sdnode.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll | 16 +-
llvm/test/CodeGen/RISCV/rvv/pr165232.ll | 309 ++--
.../CodeGen/RISCV/rvv/reproducer-pr146855.ll | 3 +-
llvm/test/CodeGen/RISCV/rvv/round-vp.ll | 8 +-
llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll | 8 +-
llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll | 8 +-
llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll | 72 +-
llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll | 64 +-
llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll | 4 +-
llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll | 44 +-
.../RISCV/rvv/vector-deinterleave-fixed.ll | 18 +-
.../CodeGen/RISCV/rvv/vector-deinterleave.ll | 170 +--
.../RISCV/rvv/vector-interleave-store.ll | 12 +-
.../CodeGen/RISCV/rvv/vector-interleave.ll | 268 ++--
llvm/test/CodeGen/RISCV/rvv/vector-splice.ll | 308 ++--
llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll | 174 +--
llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll | 72 +-
llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll | 1269 ++++++++++-------
llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll | 18 +-
llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll | 12 +-
llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll | 72 +-
llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll | 44 +-
llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll | 44 +-
llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll | 44 +-
llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll | 44 +-
llvm/test/CodeGen/RISCV/rvv/vmseq.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmsge.ll | 32 +-
llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll | 32 +-
llvm/test/CodeGen/RISCV/rvv/vmsgt.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmsle.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmsleu.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmslt.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmsltu.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vmsne.ll | 30 +-
llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll | 4 +-
.../rvv/vp-reverse-mask-fixed-vectors.ll | 16 +-
.../test/CodeGen/RISCV/rvv/vp-reverse-mask.ll | 28 +-
.../RISCV/rvv/vp-splice-mask-fixed-vectors.ll | 64 +-
.../RISCV/rvv/vp-splice-mask-vectors.ll | 112 +-
.../RISCV/rvv/vp-vector-interleaved-access.ll | 62 +-
.../test/CodeGen/RISCV/rvv/vpgather-sdnode.ll | 28 +-
llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll | 60 +-
.../CodeGen/RISCV/rvv/vreductions-fp-vp.ll | 32 +-
.../CodeGen/RISCV/rvv/vreductions-int-vp.ll | 16 +-
llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll | 36 +-
llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll | 36 +-
.../RISCV/rvv/vscale-vw-web-simplification.ll | 8 +-
llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll | 22 +-
llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll | 18 +-
llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll | 54 +-
llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll | 42 +-
llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll | 42 +-
llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll | 48 +-
llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll | 54 +-
llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll | 18 +-
133 files changed, 4874 insertions(+), 5455 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index eeba182d1ad30..7535da24d8524 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -862,7 +862,7 @@ float RISCVRegisterInfo::getSpillWeightScaleFactor(
unsigned RISCVRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF,
unsigned Idx) const {
if (Idx == RISCV::RegisterPressureSets::VMV0)
- return 2;
+ return 1;
return RISCVGenRegisterInfo::getRegPressureSetLimit(MF, Idx);
}
diff --git a/llvm/test/CodeGen/RISCV/combine-storetomstore.ll b/llvm/test/CodeGen/RISCV/combine-storetomstore.ll
index 19882d41b5445..ad0bcf57c78a9 100644
--- a/llvm/test/CodeGen/RISCV/combine-storetomstore.ll
+++ b/llvm/test/CodeGen/RISCV/combine-storetomstore.ll
@@ -212,10 +212,10 @@ define void @test_masked_store_success_v8f16(<8 x half> %x, ptr %ptr, <8 x i1> %
; RISCV-NEXT: vmv1r.v v13, v0
; RISCV-NEXT: vmerge.vim v8, v9, 1, v0
; RISCV-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RISCV-NEXT: vslidedown.vi v8, v8, 2
+; RISCV-NEXT: vslidedown.vi v10, v8, 2
; RISCV-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
-; RISCV-NEXT: vmsne.vi v0, v8, 0
; RISCV-NEXT: vmv.v.i v8, 0
+; RISCV-NEXT: vmsne.vi v0, v10, 0
; RISCV-NEXT: vmv1r.v v12, v0
; RISCV-NEXT: vmerge.vim v10, v8, 1, v0
; RISCV-NEXT: vslidedown.vi v10, v10, 1
@@ -567,10 +567,10 @@ define void @test_masked_store_multiple_v8i32(<8 x i32> %x, <8 x i32> %y, ptr %p
; RISCV-LABEL: test_masked_store_multiple_v8i32:
; RISCV: # %bb.0:
; RISCV-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; RISCV-NEXT: vle32.v v14, (a1)
+; RISCV-NEXT: vle32.v v16, (a1)
; RISCV-NEXT: vse32.v v8, (a0), v0.t
; RISCV-NEXT: vmv1r.v v0, v12
-; RISCV-NEXT: vmerge.vvm v8, v14, v10, v0
+; RISCV-NEXT: vmerge.vvm v8, v16, v10, v0
; RISCV-NEXT: vse32.v v8, (a1)
; RISCV-NEXT: ret
%load = load <8 x i32>, ptr %ptr1, align 32
@@ -586,10 +586,10 @@ define void @test_masked_store_multiple_v8i64(<8 x i64> %x, <8 x i64> %y, ptr %p
; RISCV-LABEL: test_masked_store_multiple_v8i64:
; RISCV: # %bb.0:
; RISCV-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RISCV-NEXT: vle64.v v20, (a1)
+; RISCV-NEXT: vle64.v v24, (a1)
; RISCV-NEXT: vse64.v v8, (a0), v0.t
; RISCV-NEXT: vmv1r.v v0, v16
-; RISCV-NEXT: vmerge.vvm v8, v20, v12, v0
+; RISCV-NEXT: vmerge.vvm v8, v24, v12, v0
; RISCV-NEXT: vse64.v v8, (a1)
; RISCV-NEXT: ret
%load = load <8 x i64>, ptr %ptr1, align 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
index dbe3609d61934..77fcd3f4a3506 100644
--- a/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll
@@ -514,14 +514,14 @@ define <vscale x 16 x i64> @vp_abs_nxv16i64(<vscale x 16 x i64> %va, <vscale x 1
; CHECK-LABEL: vp_abs_nxv16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v16, 0, v0.t
; CHECK-NEXT: vmax.vv v16, v16, v24, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
index 5c7667b902863..a13ab90bfb8f4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
@@ -3327,23 +3327,23 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64_unmasked(<vscale x 8 x i64> %va
define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bitreverse_nxv64i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: lui a1, 1
-; CHECK-NEXT: lui a3, 3
-; CHECK-NEXT: srli a4, a2, 1
-; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: lui a2, 1
+; CHECK-NEXT: lui a5, 3
+; CHECK-NEXT: slli a3, a1, 2
+; CHECK-NEXT: sub a4, a0, a3
+; CHECK-NEXT: sltu a6, a0, a4
+; CHECK-NEXT: addi a6, a6, -1
+; CHECK-NEXT: and a6, a6, a4
+; CHECK-NEXT: lui a7, 5
+; CHECK-NEXT: srli t0, a1, 1
+; CHECK-NEXT: addi a4, a2, -241
+; CHECK-NEXT: addi a2, a5, 819
+; CHECK-NEXT: addi a1, a7, 1365
; CHECK-NEXT: vsetvli a5, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a4
-; CHECK-NEXT: sub a4, a0, a2
-; CHECK-NEXT: sltu a5, a0, a4
-; CHECK-NEXT: addi a5, a5, -1
-; CHECK-NEXT: and a5, a5, a4
-; CHECK-NEXT: lui a6, 5
-; CHECK-NEXT: addi a4, a1, -241
-; CHECK-NEXT: addi a3, a3, 819
-; CHECK-NEXT: addi a1, a6, 1365
-; CHECK-NEXT: vsetvli zero, a5, e16, m8, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, t0
+; CHECK-NEXT: vsetvli zero, a6, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
@@ -3353,8 +3353,8 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: vsrl.vi v24, v16, 2, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a3, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a3, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a2, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: vsrl.vi v24, v16, 1, v0.t
@@ -3362,9 +3362,9 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 1, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
-; CHECK-NEXT: bltu a0, a2, .LBB46_2
+; CHECK-NEXT: bltu a0, a3, .LBB46_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a0, a2
+; CHECK-NEXT: mv a0, a3
; CHECK-NEXT: .LBB46_2:
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
@@ -3377,8 +3377,8 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
; CHECK-NEXT: vsrl.vi v24, v8, 2, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a3, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a2, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
; CHECK-NEXT: vsrl.vi v24, v8, 1, v0.t
@@ -3390,17 +3390,17 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
;
; CHECK-ZVBB-LABEL: vp_bitreverse_nxv64i16:
; CHECK-ZVBB: # %bb.0:
-; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: srli a2, a1, 1
-; CHECK-ZVBB-NEXT: slli a1, a1, 2
-; CHECK-ZVBB-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-ZVBB-NEXT: csrr a2, vlenb
+; CHECK-ZVBB-NEXT: slli a1, a2, 2
+; CHECK-ZVBB-NEXT: sub a3, a0, a1
+; CHECK-ZVBB-NEXT: sltu a4, a0, a3
+; CHECK-ZVBB-NEXT: addi a4, a4, -1
+; CHECK-ZVBB-NEXT: and a3, a4, a3
+; CHECK-ZVBB-NEXT: srli a2, a2, 1
+; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, m1, ta, ma
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-ZVBB-NEXT: sub a2, a0, a1
-; CHECK-ZVBB-NEXT: sltu a3, a0, a2
-; CHECK-ZVBB-NEXT: addi a3, a3, -1
-; CHECK-ZVBB-NEXT: and a2, a3, a2
-; CHECK-ZVBB-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; CHECK-ZVBB-NEXT: vsetvli zero, a3, e16, m8, ta, ma
; CHECK-ZVBB-NEXT: vbrev.v v16, v16, v0.t
; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB46_2
; CHECK-ZVBB-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
index fc2940e1649b2..8ef3c228b3f29 100644
--- a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
@@ -1819,17 +1819,17 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32
define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vp_bswap_nxv64i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 1
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 2
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
@@ -1846,17 +1846,17 @@ define <vscale x 64 x i16> @vp_bswap_nxv64i16(<vscale x 64 x i16> %va, <vscale x
;
; CHECK-ZVKB-LABEL: vp_bswap_nxv64i16:
; CHECK-ZVKB: # %bb.0:
-; CHECK-ZVKB-NEXT: csrr a1, vlenb
-; CHECK-ZVKB-NEXT: srli a2, a1, 1
-; CHECK-ZVKB-NEXT: slli a1, a1, 2
-; CHECK-ZVKB-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-ZVKB-NEXT: csrr a2, vlenb
+; CHECK-ZVKB-NEXT: slli a1, a2, 2
+; CHECK-ZVKB-NEXT: sub a3, a0, a1
+; CHECK-ZVKB-NEXT: sltu a4, a0, a3
+; CHECK-ZVKB-NEXT: addi a4, a4, -1
+; CHECK-ZVKB-NEXT: and a3, a4, a3
+; CHECK-ZVKB-NEXT: srli a2, a2, 1
+; CHECK-ZVKB-NEXT: vsetvli a4, zero, e8, m1, ta, ma
; CHECK-ZVKB-NEXT: vmv1r.v v24, v0
; CHECK-ZVKB-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-ZVKB-NEXT: sub a2, a0, a1
-; CHECK-ZVKB-NEXT: sltu a3, a0, a2
-; CHECK-ZVKB-NEXT: addi a3, a3, -1
-; CHECK-ZVKB-NEXT: and a2, a3, a2
-; CHECK-ZVKB-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; CHECK-ZVKB-NEXT: vsetvli zero, a3, e16, m8, ta, ma
; CHECK-ZVKB-NEXT: vrev8.v v16, v16, v0.t
; CHECK-ZVKB-NEXT: bltu a0, a1, .LBB32_2
; CHECK-ZVKB-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
index b84878f227a7a..2af49bd353f68 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
@@ -17,12 +17,12 @@ define <vscale x 1 x bfloat> @vp_ceil_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -67,12 +67,12 @@ define <vscale x 2 x bfloat> @vp_ceil_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
@@ -410,12 +410,12 @@ define <vscale x 1 x half> @vp_ceil_vv_nxv1f16(<vscale x 1 x half> %va, <vscale
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -494,12 +494,12 @@ define <vscale x 2 x half> @vp_ceil_vv_nxv2f16(<vscale x 2 x half> %va, <vscale
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll b/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
index d963665f50028..dfd057c9d7dea 100644
--- a/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
@@ -95,25 +95,40 @@ define i32 @test_v256i1(<256 x i1> %x) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x22, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 34 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x29, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 41 * vlenb
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vmv1r.v v7, v8
+; CHECK-NEXT: vmv1r.v v16, v8
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v26, v16, 8
+; CHECK-NEXT: vmv1r.v v25, v16
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v7, 4
+; CHECK-NEXT: vslidedown.vi v0, v26, 4
+; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
+; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a2, a1, 5
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v25, 4
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a2, a2, a1
; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
@@ -124,101 +139,85 @@ define i32 @test_v256i1(<256 x i1> %x) {
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a2, a1, 4
+; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmv1r.v v0, v26
+; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a2, a1, 3
+; CHECK-NEXT: add a1, a2, a1
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
; CHECK-NEXT: vadd.vv v16, v24, v16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vi v16, v7, 8
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a2, a1, 5
-; CHECK-NEXT: add a1, a2, a1
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs1r.v v16, (a1) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vslidedown.vi v16, v0, 8
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 5
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs1r.v v16, (a1) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a2, a1, 5
-; CHECK-NEXT: add a1, a2, a1
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vslidedown.vi v0, v0, 8
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 5
+; CHECK-NEXT: slli a2, a1, 3
+; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
-; CHECK-NEXT: vadd.vv v16, v16, v24
-; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v24, v24, v16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a2, a2, a1
; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vv v24, v24, v16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a2, a1, 5
+; CHECK-NEXT: slli a2, a1, 4
; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl1r.v v16, (a1) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v16, v0, v16
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vl1r.v v7, (a1) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vi v0, v16, 4
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 5
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl1r.v v16, (a1) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vslidedown.vi v7, v16, 4
+; CHECK-NEXT: vslidedown.vi v0, v7, 4
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a1, a0, 5
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vv v16, v16, v0
-; CHECK-NEXT: vadd.vv v8, v24, v8
+; CHECK-NEXT: vadd.vv v8, v8, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v24, v0, v24
; CHECK-NEXT: vadd.vv v8, v16, v8
+; CHECK-NEXT: vadd.vv v8, v24, v8
; CHECK-NEXT: vmv.s.x v16, zero
; CHECK-NEXT: vredsum.vs v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add sp, sp, a1
; CHECK-NEXT: .cfi_def_cfa sp, 16
@@ -337,9 +336,9 @@ define i32 @test_nxv128i1(<vscale x 128 x i1> %x) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vmv1r.v v7, v8
@@ -350,45 +349,63 @@ define i32 @test_nxv128i1(<vscale x 128 x i1> %x) {
; CHECK-NEXT: vslidedown.vx v0, v0, a1
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
-; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
+; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v9, a0
+; CHECK-NEXT: vslidedown.vx v0, v0, a0
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a1
-; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
+; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
+; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v7, a1
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
+; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v7, v7, a0
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv.v.v v0, v7
+; CHECK-NEXT: vslidedown.vx v0, v7, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
; CHECK-NEXT: vadd.vv v8, v24, v8
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v6, a1
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
-; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v7, a1
+; CHECK-NEXT: vslidedown.vx v0, v0, a1
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vadd.vv v16, v24, v16
; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vmv.s.x v16, zero
; CHECK-NEXT: vredsum.vs v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add sp, sp, a1
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
@@ -406,128 +423,110 @@ define i32 @test_nxv256i1(<vscale x 256 x i1> %x) {
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a1, a1, a0
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x32, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 50 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v6, v10
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a1, a0, 5
-; CHECK-NEXT: add a0, a1, a0
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs1r.v v10, (a0) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vmv1r.v v7, v9
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs1r.v v9, (a0) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmv.v.i v24, 0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a0, a1, 2
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a0
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
+; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a3, a3, a2
; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, a0
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
+; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 4
-; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: srli a1, a1, 1
; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
+; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v11, a1
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
+; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a3, a2, 4
+; CHECK-NEXT: slli a3, a2, 3
; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a0
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
+; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 3
-; CHECK-NEXT: add a3, a3, a2
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: slli a3, a2, 4
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
-; CHECK-NEXT: vmv8r.v v24, v16
+; CHECK-NEXT: vmerge.vim v8, v24, 1, v0
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a1
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
+; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a0
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v24, v24, 1, v0
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a3, a2, 3
-; CHECK-NEXT: add a2, a3, a2
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a3, a3, a2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v6, a0
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 4
-; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 4
-; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: slli a3, a2, 5
+; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v7, a0
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a3, a3, a2
; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: add a2, a2, a3
@@ -537,96 +536,99 @@ define i32 @test_nxv256i1(<vscale x 256 x i1> %x) {
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a3, a3, a2
; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a3, a2, 5
-; CHECK-NEXT: add a2, a3, a2
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v6, a1
+; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
+; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
+; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a0
; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a3, a3, a2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
-; CHECK-NEXT: vadd.vv v8, v24, v8
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: add a2, sp, a2
-; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a3, a3, a2
+; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vs1r.v v7, (a2) # vscale x 8-byte Folded Spill
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 2
-; CHECK-NEXT: add a3, a3, a2
-; CHECK-NEXT: slli a2, a2, 2
-; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
; CHECK-NEXT: vadd.vv v8, v24, v8
; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a3, a3, a2
; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v7, v0, a1
+; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a3, a2, 5
; CHECK-NEXT: add a2, a3, a2
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl1r.v v8, (a2) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vslidedown.vx v0, v8, a1
-; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a2, a1, 4
-; CHECK-NEXT: add a1, a2, a1
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vadd.vv v24, v8, v16
-; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v6, a0
+; CHECK-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v24, v24, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: mv a3, a2
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a3, a3, a2
+; CHECK-NEXT: slli a2, a2, 2
+; CHECK-NEXT: add a2, a2, a3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: addi a2, sp, 16
+; CHECK-NEXT: vl1r.v v24, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v24, a1
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a2, a1, 3
; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
+; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
+; CHECK-NEXT: vadd.vv v16, v24, v16
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v7, a0
+; CHECK-NEXT: vslidedown.vx v0, v0, a0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a1, a0, 4
+; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
+; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: slli a0, a0, 3
@@ -635,34 +637,26 @@ define i32 @test_nxv256i1(<vscale x 256 x i1> %x) {
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
-; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
-; CHECK-NEXT: vadd.vv v0, v8, v16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vv v16, v8, v24
+; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v24, v24, v0
+; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: slli a0, a0, 2
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a1, a1, a0
; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vadd.vv v8, v8, v0
-; CHECK-NEXT: vadd.vv v8, v16, v8
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vadd.vv v16, v16, v24
+; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: vmv.s.x v16, zero
; CHECK-NEXT: vredsum.vs v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a2, a2, a1
; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: add a1, a1, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll b/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
index f05f07eacaf4c..4572658c5985f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
@@ -23,16 +23,17 @@ define void @constant_folding_crash(ptr %v54, <4 x ptr> %lanes.a, <4 x ptr> %lan
; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vmerge.vim v10, v10, 1, v0
; RV32-NEXT: vrgather.vi v11, v10, 0
-; RV32-NEXT: vmsne.vi v11, v11, 0
; RV32-NEXT: andi a0, a0, 1
; RV32-NEXT: seqz a0, a0
; RV32-NEXT: vmv.v.x v10, a0
; RV32-NEXT: vmsne.vi v0, v10, 0
; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV32-NEXT: vmerge.vvm v8, v9, v8, v0
+; RV32-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV32-NEXT: vmsne.vi v0, v11, 0
+; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: vmv.v.i v8, 10
-; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: vse32.v v8, (a0), v0.t
; RV32-NEXT: ret
;
@@ -43,17 +44,18 @@ define void @constant_folding_crash(ptr %v54, <4 x ptr> %lanes.a, <4 x ptr> %lan
; RV64-NEXT: vmv.v.i v12, 0
; RV64-NEXT: vmerge.vim v12, v12, 1, v0
; RV64-NEXT: vrgather.vi v13, v12, 0
-; RV64-NEXT: vmsne.vi v13, v13, 0
; RV64-NEXT: andi a0, a0, 1
; RV64-NEXT: seqz a0, a0
; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vmsne.vi v0, v12, 0
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vmerge.vvm v8, v10, v8, v0
+; RV64-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; RV64-NEXT: vmsne.vi v0, v13, 0
+; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV64-NEXT: vmv.v.i v8, 10
-; RV64-NEXT: vmv1r.v v0, v13
; RV64-NEXT: vse32.v v8, (a0), v0.t
; RV64-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
index b2d5fb276ba66..5a465219b2124 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
@@ -1188,24 +1188,24 @@ define <vscale x 16 x i64> @vp_ctlz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; CHECK-LABEL: vp_ctlz_nxv16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: fsrmi a4, 1
+; CHECK-NEXT: fsrmi a5, 1
; CHECK-NEXT: li a2, 52
-; CHECK-NEXT: srli a3, a1, 3
-; CHECK-NEXT: sub a5, a0, a1
-; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: sltu a3, a0, a5
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a5, a3, a5
; CHECK-NEXT: li a3, 1086
-; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma
+; CHECK-NEXT: li a4, 64
+; CHECK-NEXT: sub a6, a0, a1
+; CHECK-NEXT: sltu a7, a0, a6
+; CHECK-NEXT: addi a7, a7, -1
+; CHECK-NEXT: and a6, a7, a6
+; CHECK-NEXT: srli a7, a1, 3
+; CHECK-NEXT: vsetvli t0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a7
+; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t
-; CHECK-NEXT: fsrm a4
; CHECK-NEXT: vsrl.vx v16, v16, a2, v0.t
; CHECK-NEXT: vrsub.vx v16, v16, a3, v0.t
-; CHECK-NEXT: li a4, 64
; CHECK-NEXT: vminu.vx v16, v16, a4, v0.t
+; CHECK-NEXT: fsrm a5
; CHECK-NEXT: bltu a0, a1, .LBB46_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -1223,14 +1223,14 @@ define <vscale x 16 x i64> @vp_ctlz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; CHECK-ZVBB-LABEL: vp_ctlz_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: srli a2, a1, 3
-; CHECK-ZVBB-NEXT: sub a3, a0, a1
+; CHECK-ZVBB-NEXT: sub a2, a0, a1
+; CHECK-ZVBB-NEXT: sltu a3, a0, a2
+; CHECK-ZVBB-NEXT: addi a3, a3, -1
+; CHECK-ZVBB-NEXT: and a2, a3, a2
+; CHECK-ZVBB-NEXT: srli a3, a1, 3
; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
-; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-ZVBB-NEXT: sltu a2, a0, a3
-; CHECK-ZVBB-NEXT: addi a2, a2, -1
-; CHECK-ZVBB-NEXT: and a2, a2, a3
+; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a3
; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v16, v16, v0.t
; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB46_2
@@ -2396,22 +2396,22 @@ define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: fsrmi a3, 1
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a4, a0, a1
-; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a4
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a4, a2, a4
+; CHECK-NEXT: fsrmi a4, 1
; CHECK-NEXT: li a2, 52
-; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; CHECK-NEXT: li a3, 1086
+; CHECK-NEXT: sub a5, a0, a1
+; CHECK-NEXT: sltu a6, a0, a5
+; CHECK-NEXT: addi a6, a6, -1
+; CHECK-NEXT: and a5, a6, a5
+; CHECK-NEXT: srli a6, a1, 3
+; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a6
+; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma
; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t
-; CHECK-NEXT: fsrm a3
; CHECK-NEXT: vsrl.vx v16, v16, a2, v0.t
-; CHECK-NEXT: li a3, 1086
; CHECK-NEXT: vrsub.vx v16, v16, a3, v0.t
+; CHECK-NEXT: fsrm a4
; CHECK-NEXT: bltu a0, a1, .LBB94_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -2428,14 +2428,14 @@ define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: srli a2, a1, 3
-; CHECK-ZVBB-NEXT: sub a3, a0, a1
+; CHECK-ZVBB-NEXT: sub a2, a0, a1
+; CHECK-ZVBB-NEXT: sltu a3, a0, a2
+; CHECK-ZVBB-NEXT: addi a3, a3, -1
+; CHECK-ZVBB-NEXT: and a2, a3, a2
+; CHECK-ZVBB-NEXT: srli a3, a1, 3
; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
-; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-ZVBB-NEXT: sltu a2, a0, a3
-; CHECK-ZVBB-NEXT: addi a2, a2, -1
-; CHECK-ZVBB-NEXT: and a2, a2, a3
+; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a3
; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vclz.v v16, v16, v0.t
; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB94_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
index 1b03694ee3b36..37adb42ad3e9a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
@@ -1985,63 +1985,63 @@ define <vscale x 16 x i64> @vp_ctpop_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV32-NEXT: srli a3, a1, 3
; RV32-NEXT: sub a4, a0, a1
; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 48
-; RV32-NEXT: mul a5, a5, a6
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs1r.v v0, (a5) # vscale x 8-byte Folded Spill
-; RV32-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vx v0, v0, a3
-; RV32-NEXT: sltu a3, a0, a4
; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a2
-; RV32-NEXT: addi a3, a3, -1
-; RV32-NEXT: and a3, a3, a4
-; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV32-NEXT: sltu a2, a0, a4
+; RV32-NEXT: addi a2, a2, -1
+; RV32-NEXT: and a2, a2, a4
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: li a5, 48
+; RV32-NEXT: mul a4, a4, a5
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vx v0, v0, a3
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 5
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 5
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vsub.vv v8, v16, v8, v0.t
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: addi a2, a2, 819
+; RV32-NEXT: lui a3, 209715
+; RV32-NEXT: addi a3, a3, 819
; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a2
-; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV32-NEXT: vmv.v.x v24, a3
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v8, v24, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: addi a3, sp, 16
+; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a2, 61681
+; RV32-NEXT: lui a3, 61681
; RV32-NEXT: lui a4, 4112
-; RV32-NEXT: addi a2, a2, -241
+; RV32-NEXT: addi a3, a3, -241
; RV32-NEXT: addi a4, a4, 257
; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: vmv.v.x v16, a3
+; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: li a5, 24
-; RV32-NEXT: mul a2, a2, a5
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV32-NEXT: mul a3, a3, a5
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v8, v16, v0.t
-; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a4
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmul.vv v16, v16, v8, v0.t
; RV32-NEXT: li a2, 56
; RV32-NEXT: vsrl.vx v8, v16, a2, v0.t
@@ -2124,97 +2124,76 @@ define <vscale x 16 x i64> @vp_ctpop_nxv16i64(<vscale x 16 x i64> %va, <vscale x
;
; RV64-LABEL: vp_ctpop_nxv16i64:
; RV64: # %bb.0:
-; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: srli a1, a5, 3
-; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v7, v0, a1
-; RV64-NEXT: mv a1, a0
-; RV64-NEXT: bltu a0, a5, .LBB46_2
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: srli a3, a1, 3
+; RV64-NEXT: mv a2, a0
+; RV64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vx v7, v0, a3
+; RV64-NEXT: bltu a0, a1, .LBB46_2
; RV64-NEXT: # %bb.1:
-; RV64-NEXT: mv a1, a5
+; RV64-NEXT: mv a2, a1
; RV64-NEXT: .LBB46_2:
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
-; RV64-NEXT: lui a6, 4112
+; RV64-NEXT: lui a5, 4112
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: addi a3, a3, 819
; RV64-NEXT: addi a4, a4, -241
-; RV64-NEXT: addi a6, a6, 257
-; RV64-NEXT: slli a7, a2, 32
-; RV64-NEXT: add a7, a2, a7
-; RV64-NEXT: slli a2, a3, 32
-; RV64-NEXT: add t0, a3, a2
-; RV64-NEXT: slli a2, a4, 32
-; RV64-NEXT: add a4, a4, a2
-; RV64-NEXT: slli a2, a6, 32
-; RV64-NEXT: add a2, a6, a2
-; RV64-NEXT: li a3, 56
-; RV64-NEXT: sub a5, a0, a5
-; RV64-NEXT: sltu a0, a0, a5
-; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a0, a0, a5
-; RV64-NEXT: vand.vx v24, v24, a7, v0.t
+; RV64-NEXT: addi a5, a5, 257
+; RV64-NEXT: slli a6, a2, 32
+; RV64-NEXT: add a2, a2, a6
+; RV64-NEXT: slli a6, a3, 32
+; RV64-NEXT: add a3, a3, a6
+; RV64-NEXT: slli a6, a4, 32
+; RV64-NEXT: add a4, a4, a6
+; RV64-NEXT: slli a6, a5, 32
+; RV64-NEXT: add a5, a5, a6
+; RV64-NEXT: li a6, 56
+; RV64-NEXT: vand.vx v24, v24, a2, v0.t
; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v6, v0
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a7, v0.t
-; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v8, t0, v0.t
+; RV64-NEXT: vand.vx v24, v8, a3, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, t0, v0.t
+; RV64-NEXT: vand.vx v8, v8, a3, v0.t
; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v16, t0, v0.t
-; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, t0, v0.t
-; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vand.vx v8, v8, a4, v0.t
+; RV64-NEXT: vmul.vx v8, v8, a5, v0.t
+; RV64-NEXT: vsrl.vx v8, v8, a6, v0.t
+; RV64-NEXT: sub a1, a0, a1
+; RV64-NEXT: sltu a0, a0, a1
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a2, v0.t
+; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
+; RV64-NEXT: vand.vx v24, v16, a3, v0.t
+; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
+; RV64-NEXT: vand.vx v16, v16, a3, v0.t
+; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vmul.vx v8, v8, a2, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v16, a4, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v8, v8, a3, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV64-NEXT: vmul.vx v16, v16, a2, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a3, v0.t
+; RV64-NEXT: vmul.vx v16, v16, a5, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a6, v0.t
; RV64-NEXT: ret
;
; CHECK-ZVBB-LABEL: vp_ctpop_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: srli a2, a1, 3
-; CHECK-ZVBB-NEXT: sub a3, a0, a1
+; CHECK-ZVBB-NEXT: sub a2, a0, a1
+; CHECK-ZVBB-NEXT: sltu a3, a0, a2
+; CHECK-ZVBB-NEXT: addi a3, a3, -1
+; CHECK-ZVBB-NEXT: and a2, a3, a2
+; CHECK-ZVBB-NEXT: srli a3, a1, 3
; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
-; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-ZVBB-NEXT: sltu a2, a0, a3
-; CHECK-ZVBB-NEXT: addi a2, a2, -1
-; CHECK-ZVBB-NEXT: and a2, a2, a3
+; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a3
; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vcpop.v v16, v16, v0.t
; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB46_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
index bf003ef675a36..ed2dc76750466 100644
--- a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll
@@ -2150,8 +2150,11 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: lui a2, 349525
-; RV32-NEXT: srli a3, a1, 3
-; RV32-NEXT: sub a4, a0, a1
+; RV32-NEXT: sub a3, a0, a1
+; RV32-NEXT: sltu a4, a0, a3
+; RV32-NEXT: addi a4, a4, -1
+; RV32-NEXT: and a3, a4, a3
+; RV32-NEXT: srli a4, a1, 3
; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: li a6, 48
@@ -2160,10 +2163,7 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs1r.v v0, (a5) # vscale x 8-byte Folded Spill
; RV32-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vx v0, v0, a3
-; RV32-NEXT: sltu a3, a0, a4
-; RV32-NEXT: addi a3, a3, -1
-; RV32-NEXT: and a3, a3, a4
+; RV32-NEXT: vslidedown.vx v0, v0, a4
; RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; RV32-NEXT: vadd.vi v8, v16, -1, v0.t
; RV32-NEXT: vnot.v v16, v16, v0.t
@@ -2304,26 +2304,26 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
; RV64-NEXT: lui a5, 4112
-; RV64-NEXT: srli a6, a1, 3
-; RV64-NEXT: sub a7, a0, a1
+; RV64-NEXT: sub a6, a0, a1
; RV64-NEXT: addi a2, a2, 1365
; RV64-NEXT: addi a3, a3, 819
-; RV64-NEXT: addi t0, a4, -241
-; RV64-NEXT: addi t1, a5, 257
-; RV64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmv1r.v v7, v0
-; RV64-NEXT: vslidedown.vx v0, v0, a6
+; RV64-NEXT: addi a7, a4, -241
+; RV64-NEXT: addi t0, a5, 257
; RV64-NEXT: slli a5, a2, 32
; RV64-NEXT: add a5, a2, a5
; RV64-NEXT: slli a4, a3, 32
; RV64-NEXT: add a4, a3, a4
-; RV64-NEXT: slli a2, t0, 32
-; RV64-NEXT: add a2, t0, a2
-; RV64-NEXT: slli a3, t1, 32
-; RV64-NEXT: add a3, t1, a3
-; RV64-NEXT: sltu a6, a0, a7
-; RV64-NEXT: addi a6, a6, -1
-; RV64-NEXT: and a6, a6, a7
+; RV64-NEXT: slli a2, a7, 32
+; RV64-NEXT: add a2, a7, a2
+; RV64-NEXT: slli a3, t0, 32
+; RV64-NEXT: add a3, t0, a3
+; RV64-NEXT: sltu a7, a0, a6
+; RV64-NEXT: addi a7, a7, -1
+; RV64-NEXT: and a6, a7, a6
+; RV64-NEXT: srli a7, a1, 3
+; RV64-NEXT: vsetvli t0, zero, e8, mf4, ta, ma
+; RV64-NEXT: vmv1r.v v7, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a7
; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; RV64-NEXT: vadd.vi v24, v16, -1, v0.t
; RV64-NEXT: vnot.v v16, v16, v0.t
@@ -2367,14 +2367,14 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
; CHECK-ZVBB-LABEL: vp_cttz_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: srli a2, a1, 3
-; CHECK-ZVBB-NEXT: sub a3, a0, a1
+; CHECK-ZVBB-NEXT: sub a2, a0, a1
+; CHECK-ZVBB-NEXT: sltu a3, a0, a2
+; CHECK-ZVBB-NEXT: addi a3, a3, -1
+; CHECK-ZVBB-NEXT: and a2, a3, a2
+; CHECK-ZVBB-NEXT: srli a3, a1, 3
; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
-; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-ZVBB-NEXT: sltu a2, a0, a3
-; CHECK-ZVBB-NEXT: addi a2, a2, -1
-; CHECK-ZVBB-NEXT: and a2, a2, a3
+; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a3
; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v16, v16, v0.t
; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB46_2
@@ -3747,24 +3747,24 @@ define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
; CHECK-LABEL: vp_cttz_zero_undef_nxv16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: fsrmi a3, 1
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a4, a0, a1
-; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a4
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a4, a2, a4
+; CHECK-NEXT: fsrmi a4, 1
; CHECK-NEXT: li a2, 52
-; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; CHECK-NEXT: li a3, 1023
+; CHECK-NEXT: sub a5, a0, a1
+; CHECK-NEXT: sltu a6, a0, a5
+; CHECK-NEXT: addi a6, a6, -1
+; CHECK-NEXT: and a5, a6, a5
+; CHECK-NEXT: srli a6, a1, 3
+; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a6
+; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma
; CHECK-NEXT: vrsub.vi v24, v16, 0, v0.t
; CHECK-NEXT: vand.vv v16, v16, v24, v0.t
; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t
-; CHECK-NEXT: fsrm a3
; CHECK-NEXT: vsrl.vx v16, v16, a2, v0.t
-; CHECK-NEXT: li a3, 1023
; CHECK-NEXT: vsub.vx v16, v16, a3, v0.t
+; CHECK-NEXT: fsrm a4
; CHECK-NEXT: bltu a0, a1, .LBB94_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -3783,14 +3783,14 @@ define <vscale x 16 x i64> @vp_cttz_zero_undef_nxv16i64(<vscale x 16 x i64> %va,
; CHECK-ZVBB-LABEL: vp_cttz_zero_undef_nxv16i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: csrr a1, vlenb
-; CHECK-ZVBB-NEXT: srli a2, a1, 3
-; CHECK-ZVBB-NEXT: sub a3, a0, a1
+; CHECK-ZVBB-NEXT: sub a2, a0, a1
+; CHECK-ZVBB-NEXT: sltu a3, a0, a2
+; CHECK-ZVBB-NEXT: addi a3, a3, -1
+; CHECK-ZVBB-NEXT: and a2, a3, a2
+; CHECK-ZVBB-NEXT: srli a3, a1, 3
; CHECK-ZVBB-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
-; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-ZVBB-NEXT: sltu a2, a0, a3
-; CHECK-ZVBB-NEXT: addi a2, a2, -1
-; CHECK-ZVBB-NEXT: and a2, a2, a3
+; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a3
; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vctz.v v16, v16, v0.t
; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB94_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/expandload.ll b/llvm/test/CodeGen/RISCV/rvv/expandload.ll
index f13a9d0764c8b..0a2c8c9693b47 100644
--- a/llvm/test/CodeGen/RISCV/rvv/expandload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/expandload.ll
@@ -218,24 +218,31 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: csrr a2, vlenb
-; CHECK-RV32-NEXT: slli a3, a2, 5
-; CHECK-RV32-NEXT: add a2, a3, a2
+; CHECK-RV32-NEXT: li a3, 34
+; CHECK-RV32-NEXT: mul a2, a2, a3
; CHECK-RV32-NEXT: sub sp, sp, a2
-; CHECK-RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; CHECK-RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x22, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 34 * vlenb
; CHECK-RV32-NEXT: csrr a2, vlenb
-; CHECK-RV32-NEXT: li a3, 24
+; CHECK-RV32-NEXT: li a3, 26
; CHECK-RV32-NEXT: mul a2, a2, a3
; CHECK-RV32-NEXT: add a2, sp, a2
; CHECK-RV32-NEXT: addi a2, a2, 16
; CHECK-RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: csrr a2, vlenb
-; CHECK-RV32-NEXT: slli a2, a2, 5
+; CHECK-RV32-NEXT: li a3, 25
+; CHECK-RV32-NEXT: mul a2, a2, a3
+; CHECK-RV32-NEXT: add a2, sp, a2
+; CHECK-RV32-NEXT: addi a2, a2, 16
+; CHECK-RV32-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
+; CHECK-RV32-NEXT: csrr a2, vlenb
+; CHECK-RV32-NEXT: li a3, 24
+; CHECK-RV32-NEXT: mul a2, a2, a3
; CHECK-RV32-NEXT: add a2, sp, a2
; CHECK-RV32-NEXT: addi a2, a2, 16
; CHECK-RV32-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: li a2, 128
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v8, v0, 1
+; CHECK-RV32-NEXT: vslidedown.vi v11, v0, 1
; CHECK-RV32-NEXT: li a3, 32
; CHECK-RV32-NEXT: vmv.x.s a4, v0
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -246,9 +253,9 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV32-NEXT: addi a1, a1, 16
; CHECK-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vsrl.vx v9, v8, a3
+; CHECK-RV32-NEXT: vsrl.vx v9, v11, a3
; CHECK-RV32-NEXT: vsrl.vx v10, v0, a3
-; CHECK-RV32-NEXT: vmv.x.s a1, v8
+; CHECK-RV32-NEXT: vmv.x.s a1, v11
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV32-NEXT: vcpop.m a3, v0
; CHECK-RV32-NEXT: cpop a4, a4
@@ -256,12 +263,12 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV32-NEXT: vmv.x.s a5, v9
; CHECK-RV32-NEXT: vmv.x.s a6, v10
; CHECK-RV32-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-RV32-NEXT: vle8.v v8, (a0)
+; CHECK-RV32-NEXT: vle8.v v24, (a0)
; CHECK-RV32-NEXT: csrr a3, vlenb
; CHECK-RV32-NEXT: slli a3, a3, 4
; CHECK-RV32-NEXT: add a3, sp, a3
; CHECK-RV32-NEXT: addi a3, a3, 16
-; CHECK-RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: cpop a1, a1
; CHECK-RV32-NEXT: cpop a3, a6
; CHECK-RV32-NEXT: cpop a5, a5
@@ -269,65 +276,75 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV32-NEXT: add a1, a1, a5
; CHECK-RV32-NEXT: add a1, a3, a1
; CHECK-RV32-NEXT: add a0, a0, a1
-; CHECK-RV32-NEXT: csrr a1, vlenb
-; CHECK-RV32-NEXT: slli a1, a1, 5
-; CHECK-RV32-NEXT: add a1, sp, a1
-; CHECK-RV32-NEXT: addi a1, a1, 16
-; CHECK-RV32-NEXT: vl1r.v v8, (a1) # vscale x 8-byte Folded Reload
; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV32-NEXT: vcpop.m a1, v8
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-RV32-NEXT: vle8.v v8, (a0)
; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, mu
-; CHECK-RV32-NEXT: viota.m v16, v0
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 4
+; CHECK-RV32-NEXT: li a1, 25
+; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a2, e8, m8, ta, mu
+; CHECK-RV32-NEXT: viota.m v8, v24
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: li a1, 24
+; CHECK-RV32-NEXT: li a1, 25
; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: vrgather.vv v8, v24, v16, v0.t
+; CHECK-RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: li a1, 24
+; CHECK-RV32-NEXT: li a1, 26
; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 5
+; CHECK-RV32-NEXT: slli a0, a0, 4
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
-; CHECK-RV32-NEXT: viota.m v8, v24
+; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vrgather.vv v16, v24, v8, v0.t
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 5
+; CHECK-RV32-NEXT: li a1, 26
+; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; CHECK-RV32-NEXT: csrr a0, vlenb
+; CHECK-RV32-NEXT: li a1, 24
+; CHECK-RV32-NEXT: mul a0, a0, a1
+; CHECK-RV32-NEXT: add a0, sp, a0
+; CHECK-RV32-NEXT: addi a0, a0, 16
+; CHECK-RV32-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV32-NEXT: viota.m v16, v8
; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: slli a0, a0, 3
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: vrgather.vv v16, v24, v8, v0.t
; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: li a1, 24
; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
+; CHECK-RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vrgather.vv v24, v8, v16, v0.t
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a1, a0, 5
-; CHECK-RV32-NEXT: add a0, a1, a0
+; CHECK-RV32-NEXT: li a1, 26
+; CHECK-RV32-NEXT: mul a0, a0, a1
+; CHECK-RV32-NEXT: add a0, sp, a0
+; CHECK-RV32-NEXT: addi a0, a0, 16
+; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vmv.v.v v16, v24
+; CHECK-RV32-NEXT: csrr a0, vlenb
+; CHECK-RV32-NEXT: li a1, 34
+; CHECK-RV32-NEXT: mul a0, a0, a1
; CHECK-RV32-NEXT: add sp, sp, a0
; CHECK-RV32-NEXT: .cfi_def_cfa sp, 16
; CHECK-RV32-NEXT: addi sp, sp, 16
@@ -339,24 +356,31 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV64-NEXT: addi sp, sp, -16
; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV64-NEXT: csrr a2, vlenb
-; CHECK-RV64-NEXT: slli a3, a2, 5
-; CHECK-RV64-NEXT: add a2, a3, a2
+; CHECK-RV64-NEXT: li a3, 34
+; CHECK-RV64-NEXT: mul a2, a2, a3
; CHECK-RV64-NEXT: sub sp, sp, a2
-; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x22, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 34 * vlenb
; CHECK-RV64-NEXT: csrr a2, vlenb
-; CHECK-RV64-NEXT: li a3, 24
+; CHECK-RV64-NEXT: li a3, 26
; CHECK-RV64-NEXT: mul a2, a2, a3
; CHECK-RV64-NEXT: add a2, sp, a2
; CHECK-RV64-NEXT: addi a2, a2, 16
; CHECK-RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: csrr a2, vlenb
-; CHECK-RV64-NEXT: slli a2, a2, 5
+; CHECK-RV64-NEXT: li a3, 25
+; CHECK-RV64-NEXT: mul a2, a2, a3
+; CHECK-RV64-NEXT: add a2, sp, a2
+; CHECK-RV64-NEXT: addi a2, a2, 16
+; CHECK-RV64-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
+; CHECK-RV64-NEXT: csrr a2, vlenb
+; CHECK-RV64-NEXT: li a3, 24
+; CHECK-RV64-NEXT: mul a2, a2, a3
; CHECK-RV64-NEXT: add a2, sp, a2
; CHECK-RV64-NEXT: addi a2, a2, 16
; CHECK-RV64-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: li a2, 128
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v8, v0, 1
+; CHECK-RV64-NEXT: vslidedown.vi v9, v0, 1
; CHECK-RV64-NEXT: vmv.x.s a3, v0
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV64-NEXT: vle8.v v16, (a1)
@@ -366,21 +390,16 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV64-NEXT: addi a1, a1, 16
; CHECK-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a2, e64, m1, ta, ma
-; CHECK-RV64-NEXT: vmv.x.s a1, v8
+; CHECK-RV64-NEXT: vmv.x.s a1, v9
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV64-NEXT: vcpop.m a4, v0
; CHECK-RV64-NEXT: vsetvli zero, a4, e8, m8, ta, ma
-; CHECK-RV64-NEXT: vle8.v v8, (a0)
+; CHECK-RV64-NEXT: vle8.v v24, (a0)
; CHECK-RV64-NEXT: csrr a4, vlenb
; CHECK-RV64-NEXT: slli a4, a4, 4
; CHECK-RV64-NEXT: add a4, sp, a4
; CHECK-RV64-NEXT: addi a4, a4, 16
-; CHECK-RV64-NEXT: vs8r.v v8, (a4) # vscale x 64-byte Folded Spill
-; CHECK-RV64-NEXT: csrr a4, vlenb
-; CHECK-RV64-NEXT: slli a4, a4, 5
-; CHECK-RV64-NEXT: add a4, sp, a4
-; CHECK-RV64-NEXT: addi a4, a4, 16
-; CHECK-RV64-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; CHECK-RV64-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-RV64-NEXT: vcpop.m a4, v8
; CHECK-RV64-NEXT: cpop a3, a3
@@ -391,54 +410,68 @@ define <256 x i8> @test_expandload_v256i8(ptr %base, <256 x i1> %mask, <256 x i8
; CHECK-RV64-NEXT: vle8.v v8, (a0)
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: csrr a0, vlenb
+; CHECK-RV64-NEXT: li a1, 25
+; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: add a0, sp, a0
+; CHECK-RV64-NEXT: addi a0, a0, 16
+; CHECK-RV64-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: vsetvli zero, a2, e8, m8, ta, mu
-; CHECK-RV64-NEXT: viota.m v16, v0
+; CHECK-RV64-NEXT: viota.m v24, v8
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 4
+; CHECK-RV64-NEXT: li a1, 25
+; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 24
+; CHECK-RV64-NEXT: li a1, 26
; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV64-NEXT: vrgather.vv v8, v24, v16, v0.t
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 24
-; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: slli a0, a0, 4
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 5
+; CHECK-RV64-NEXT: li a1, 26
+; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
-; CHECK-RV64-NEXT: viota.m v24, v8
+; CHECK-RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 5
+; CHECK-RV64-NEXT: li a1, 24
+; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV64-NEXT: vl1r.v v16, (a0) # vscale x 8-byte Folded Reload
+; CHECK-RV64-NEXT: viota.m v24, v16
; CHECK-RV64-NEXT: csrr a0, vlenb
; CHECK-RV64-NEXT: slli a0, a0, 3
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: csrr a0, vlenb
+; CHECK-RV64-NEXT: li a1, 24
+; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: add a0, sp, a0
+; CHECK-RV64-NEXT: addi a0, a0, 16
+; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vrgather.vv v16, v8, v24, v0.t
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 24
+; CHECK-RV64-NEXT: li a1, 26
; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a1, a0, 5
-; CHECK-RV64-NEXT: add a0, a1, a0
+; CHECK-RV64-NEXT: li a1, 34
+; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add sp, sp, a0
; CHECK-RV64-NEXT: .cfi_def_cfa sp, 16
; CHECK-RV64-NEXT: addi sp, sp, 16
@@ -694,22 +727,22 @@ define <128 x i16> @test_expandload_v128i16(ptr %base, <128 x i1> %mask, <128 x
; CHECK-RV32-NEXT: add a1, sp, a1
; CHECK-RV32-NEXT: addi a1, a1, 16
; CHECK-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-RV32-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m8, ta, ma
; CHECK-RV32-NEXT: vmv8r.v v16, v8
; CHECK-RV32-NEXT: li a1, 64
-; CHECK-RV32-NEXT: vslidedown.vi v8, v0, 8
-; CHECK-RV32-NEXT: csrr a2, vlenb
-; CHECK-RV32-NEXT: slli a2, a2, 5
-; CHECK-RV32-NEXT: add a2, sp, a2
-; CHECK-RV32-NEXT: addi a2, a2, 16
-; CHECK-RV32-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: li a2, 32
-; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-RV32-NEXT: vmv.x.s a3, v0
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-RV32-NEXT: vcpop.m a4, v0
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-RV32-NEXT: vsrl.vx v8, v0, a2
+; CHECK-RV32-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vi v9, v0, 8
+; CHECK-RV32-NEXT: csrr a2, vlenb
+; CHECK-RV32-NEXT: slli a2, a2, 5
+; CHECK-RV32-NEXT: add a2, sp, a2
+; CHECK-RV32-NEXT: addi a2, a2, 16
+; CHECK-RV32-NEXT: vs1r.v v9, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: csrr a2, vlenb
; CHECK-RV32-NEXT: slli a2, a2, 5
; CHECK-RV32-NEXT: add a2, sp, a2
@@ -798,20 +831,21 @@ define <128 x i16> @test_expandload_v128i16(ptr %base, <128 x i1> %mask, <128 x
; CHECK-RV64-NEXT: addi a1, a1, 16
; CHECK-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: li a1, 64
-; CHECK-RV64-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 8
-; CHECK-RV64-NEXT: csrr a2, vlenb
-; CHECK-RV64-NEXT: slli a2, a2, 5
-; CHECK-RV64-NEXT: add a2, sp, a2
-; CHECK-RV64-NEXT: addi a2, a2, 16
-; CHECK-RV64-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-RV64-NEXT: vcpop.m a2, v0
+; CHECK-RV64-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 8
+; CHECK-RV64-NEXT: csrr a3, vlenb
+; CHECK-RV64-NEXT: slli a3, a3, 5
+; CHECK-RV64-NEXT: add a3, sp, a3
+; CHECK-RV64-NEXT: addi a3, a3, 16
+; CHECK-RV64-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: csrr a3, vlenb
; CHECK-RV64-NEXT: slli a3, a3, 5
; CHECK-RV64-NEXT: add a3, sp, a3
; CHECK-RV64-NEXT: addi a3, a3, 16
; CHECK-RV64-NEXT: vl1r.v v24, (a3) # vscale x 8-byte Folded Reload
+; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-RV64-NEXT: vcpop.m a3, v24
; CHECK-RV64-NEXT: vsetvli zero, a2, e16, m8, ta, ma
; CHECK-RV64-NEXT: vle16.v v24, (a0)
@@ -1084,20 +1118,21 @@ define <64 x i32> @test_expandload_v64i32(ptr %base, <64 x i1> %mask, <64 x i32>
; CHECK-RV32-NEXT: addi a1, a1, 16
; CHECK-RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: li a1, 32
-; CHECK-RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v24, v0, 4
-; CHECK-RV32-NEXT: csrr a2, vlenb
-; CHECK-RV32-NEXT: slli a2, a2, 5
-; CHECK-RV32-NEXT: add a2, sp, a2
-; CHECK-RV32-NEXT: addi a2, a2, 16
-; CHECK-RV32-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vcpop.m a2, v0
+; CHECK-RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vi v24, v0, 4
+; CHECK-RV32-NEXT: csrr a3, vlenb
+; CHECK-RV32-NEXT: slli a3, a3, 5
+; CHECK-RV32-NEXT: add a3, sp, a3
+; CHECK-RV32-NEXT: addi a3, a3, 16
+; CHECK-RV32-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: csrr a3, vlenb
; CHECK-RV32-NEXT: slli a3, a3, 5
; CHECK-RV32-NEXT: add a3, sp, a3
; CHECK-RV32-NEXT: addi a3, a3, 16
; CHECK-RV32-NEXT: vl1r.v v24, (a3) # vscale x 8-byte Folded Reload
+; CHECK-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV32-NEXT: vcpop.m a3, v24
; CHECK-RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-RV32-NEXT: vle32.v v24, (a0)
@@ -1166,37 +1201,33 @@ define <64 x i32> @test_expandload_v64i32(ptr %base, <64 x i1> %mask, <64 x i32>
; CHECK-RV64-NEXT: addi sp, sp, -16
; CHECK-RV64-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV64-NEXT: csrr a1, vlenb
-; CHECK-RV64-NEXT: slli a2, a1, 5
-; CHECK-RV64-NEXT: add a1, a2, a1
+; CHECK-RV64-NEXT: li a2, 25
+; CHECK-RV64-NEXT: mul a1, a1, a2
; CHECK-RV64-NEXT: sub sp, sp, a1
-; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; CHECK-RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x19, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 25 * vlenb
; CHECK-RV64-NEXT: csrr a1, vlenb
-; CHECK-RV64-NEXT: li a2, 24
-; CHECK-RV64-NEXT: mul a1, a1, a2
+; CHECK-RV64-NEXT: slli a1, a1, 4
; CHECK-RV64-NEXT: add a1, sp, a1
; CHECK-RV64-NEXT: addi a1, a1, 16
; CHECK-RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: li a1, 32
-; CHECK-RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 4
-; CHECK-RV64-NEXT: csrr a2, vlenb
-; CHECK-RV64-NEXT: slli a2, a2, 5
-; CHECK-RV64-NEXT: add a2, sp, a2
-; CHECK-RV64-NEXT: addi a2, a2, 16
-; CHECK-RV64-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
-; CHECK-RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-RV64-NEXT: vmv.x.s a2, v0
; CHECK-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-RV64-NEXT: vcpop.m a3, v0
; CHECK-RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; CHECK-RV64-NEXT: vle32.v v24, (a0)
+; CHECK-RV64-NEXT: vle32.v v16, (a0)
+; CHECK-RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 4
; CHECK-RV64-NEXT: csrr a3, vlenb
-; CHECK-RV64-NEXT: slli a3, a3, 4
+; CHECK-RV64-NEXT: li a4, 24
+; CHECK-RV64-NEXT: mul a3, a3, a4
; CHECK-RV64-NEXT: add a3, sp, a3
; CHECK-RV64-NEXT: addi a3, a3, 16
-; CHECK-RV64-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; CHECK-RV64-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: csrr a3, vlenb
-; CHECK-RV64-NEXT: slli a3, a3, 5
+; CHECK-RV64-NEXT: li a4, 24
+; CHECK-RV64-NEXT: mul a3, a3, a4
; CHECK-RV64-NEXT: add a3, sp, a3
; CHECK-RV64-NEXT: addi a3, a3, 16
; CHECK-RV64-NEXT: vl1r.v v24, (a3) # vscale x 8-byte Folded Reload
@@ -1214,28 +1245,24 @@ define <64 x i32> @test_expandload_v64i32(ptr %base, <64 x i1> %mask, <64 x i32>
; CHECK-RV64-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; CHECK-RV64-NEXT: viota.m v24, v0
-; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 4
-; CHECK-RV64-NEXT: add a0, sp, a0
-; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: vrgather.vv v8, v16, v24, v0.t
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 5
+; CHECK-RV64-NEXT: li a1, 24
+; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: viota.m v16, v24
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 5
+; CHECK-RV64-NEXT: li a1, 24
+; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: li a1, 24
-; CHECK-RV64-NEXT: mul a0, a0, a1
+; CHECK-RV64-NEXT: slli a0, a0, 4
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -1249,8 +1276,8 @@ define <64 x i32> @test_expandload_v64i32(ptr %base, <64 x i1> %mask, <64 x i32>
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a1, a0, 5
-; CHECK-RV64-NEXT: add a0, a1, a0
+; CHECK-RV64-NEXT: li a1, 25
+; CHECK-RV64-NEXT: mul a0, a0, a1
; CHECK-RV64-NEXT: add sp, sp, a0
; CHECK-RV64-NEXT: .cfi_def_cfa sp, 16
; CHECK-RV64-NEXT: addi sp, sp, 16
@@ -1438,17 +1465,17 @@ define <32 x i64> @test_expandload_v32i64(ptr %base, <32 x i1> %mask, <32 x i64>
; CHECK-RV32-NEXT: addi a1, a1, 16
; CHECK-RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV32-NEXT: vmv.x.s a1, v0
-; CHECK-RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-RV32-NEXT: csrr a2, vlenb
-; CHECK-RV32-NEXT: slli a2, a2, 5
-; CHECK-RV32-NEXT: add a2, sp, a2
-; CHECK-RV32-NEXT: addi a2, a2, 16
-; CHECK-RV32-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: zext.h a1, a1
; CHECK-RV32-NEXT: cpop a1, a1
; CHECK-RV32-NEXT: slli a1, a1, 3
; CHECK-RV32-NEXT: add a0, a0, a1
+; CHECK-RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-RV32-NEXT: csrr a1, vlenb
+; CHECK-RV32-NEXT: slli a1, a1, 5
+; CHECK-RV32-NEXT: add a1, sp, a1
+; CHECK-RV32-NEXT: addi a1, a1, 16
+; CHECK-RV32-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
; CHECK-RV32-NEXT: csrr a1, vlenb
; CHECK-RV32-NEXT: slli a1, a1, 5
; CHECK-RV32-NEXT: add a1, sp, a1
@@ -1479,24 +1506,23 @@ define <32 x i64> @test_expandload_v32i64(ptr %base, <32 x i1> %mask, <32 x i64>
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
; CHECK-RV32-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
-; CHECK-RV32-NEXT: viota.m v16, v24
+; CHECK-RV32-NEXT: viota.m v8, v24
; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: slli a0, a0, 5
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
; CHECK-RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 4
+; CHECK-RV32-NEXT: slli a0, a0, 3
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
-; CHECK-RV32-NEXT: slli a0, a0, 3
+; CHECK-RV32-NEXT: slli a0, a0, 4
; CHECK-RV32-NEXT: add a0, sp, a0
; CHECK-RV32-NEXT: addi a0, a0, 16
-; CHECK-RV32-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV32-NEXT: vrgather.vv v8, v24, v16, v0.t
-; CHECK-RV32-NEXT: vmv.v.v v16, v8
+; CHECK-RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV32-NEXT: vrgather.vv v16, v24, v8, v0.t
; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV32-NEXT: csrr a0, vlenb
@@ -1533,17 +1559,17 @@ define <32 x i64> @test_expandload_v32i64(ptr %base, <32 x i1> %mask, <32 x i64>
; CHECK-RV64-NEXT: addi a1, a1, 16
; CHECK-RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; CHECK-RV64-NEXT: vmv.x.s a1, v0
-; CHECK-RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-RV64-NEXT: csrr a2, vlenb
-; CHECK-RV64-NEXT: slli a2, a2, 5
-; CHECK-RV64-NEXT: add a2, sp, a2
-; CHECK-RV64-NEXT: addi a2, a2, 16
-; CHECK-RV64-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: zext.h a1, a1
; CHECK-RV64-NEXT: cpopw a1, a1
; CHECK-RV64-NEXT: slli a1, a1, 3
; CHECK-RV64-NEXT: add a0, a0, a1
+; CHECK-RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vi v24, v0, 2
+; CHECK-RV64-NEXT: csrr a1, vlenb
+; CHECK-RV64-NEXT: slli a1, a1, 5
+; CHECK-RV64-NEXT: add a1, sp, a1
+; CHECK-RV64-NEXT: addi a1, a1, 16
+; CHECK-RV64-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
; CHECK-RV64-NEXT: csrr a1, vlenb
; CHECK-RV64-NEXT: slli a1, a1, 5
; CHECK-RV64-NEXT: add a1, sp, a1
@@ -1574,24 +1600,23 @@ define <32 x i64> @test_expandload_v32i64(ptr %base, <32 x i1> %mask, <32 x i64>
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl1r.v v24, (a0) # vscale x 8-byte Folded Reload
-; CHECK-RV64-NEXT: viota.m v16, v24
+; CHECK-RV64-NEXT: viota.m v8, v24
; CHECK-RV64-NEXT: csrr a0, vlenb
; CHECK-RV64-NEXT: slli a0, a0, 5
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
; CHECK-RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 4
+; CHECK-RV64-NEXT: slli a0, a0, 3
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
-; CHECK-RV64-NEXT: slli a0, a0, 3
+; CHECK-RV64-NEXT: slli a0, a0, 4
; CHECK-RV64-NEXT: add a0, sp, a0
; CHECK-RV64-NEXT: addi a0, a0, 16
-; CHECK-RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; CHECK-RV64-NEXT: vrgather.vv v8, v24, v16, v0.t
-; CHECK-RV64-NEXT: vmv.v.v v16, v8
+; CHECK-RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-RV64-NEXT: vrgather.vv v16, v24, v8, v0.t
; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-RV64-NEXT: csrr a0, vlenb
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
index 62dadfe936e44..e0edf68e949b6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
@@ -139,22 +139,21 @@ define i1 @extractelt_nxv128i1(ptr %x, i64 %idx) nounwind {
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: sub sp, sp, a3
; RV32-NEXT: andi sp, sp, -64
-; RV32-NEXT: addi a3, sp, 64
-; RV32-NEXT: vl8r.v v8, (a0)
; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: vl8r.v v8, (a0)
; RV32-NEXT: add a0, a0, a2
; RV32-NEXT: vl8r.v v16, (a0)
; RV32-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: vmseq.vi v0, v8, 0
-; RV32-NEXT: vmv.v.i v8, 0
-; RV32-NEXT: add a1, a3, a1
-; RV32-NEXT: vmseq.vi v25, v16, 0
-; RV32-NEXT: vmerge.vim v16, v8, 1, v0
-; RV32-NEXT: vs8r.v v16, (a3)
-; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: vmv1r.v v0, v25
-; RV32-NEXT: vmerge.vim v8, v8, 1, v0
-; RV32-NEXT: vs8r.v v8, (a2)
+; RV32-NEXT: vmerge.vim v8, v24, 1, v0
+; RV32-NEXT: vmseq.vi v0, v16, 0
+; RV32-NEXT: vmerge.vim v16, v24, 1, v0
+; RV32-NEXT: addi a0, sp, 64
+; RV32-NEXT: add a1, a0, a1
+; RV32-NEXT: vs8r.v v8, (a0)
+; RV32-NEXT: add a0, a0, a2
+; RV32-NEXT: vs8r.v v16, (a0)
; RV32-NEXT: lbu a0, 0(a1)
; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
@@ -179,22 +178,21 @@ define i1 @extractelt_nxv128i1(ptr %x, i64 %idx) nounwind {
; RV64-NEXT: slli a3, a3, 4
; RV64-NEXT: sub sp, sp, a3
; RV64-NEXT: andi sp, sp, -64
-; RV64-NEXT: addi a3, sp, 64
-; RV64-NEXT: vl8r.v v8, (a0)
; RV64-NEXT: slli a2, a2, 3
+; RV64-NEXT: vl8r.v v8, (a0)
; RV64-NEXT: add a0, a0, a2
; RV64-NEXT: vl8r.v v16, (a0)
; RV64-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; RV64-NEXT: vmv.v.i v24, 0
; RV64-NEXT: vmseq.vi v0, v8, 0
-; RV64-NEXT: vmv.v.i v8, 0
-; RV64-NEXT: add a1, a3, a1
-; RV64-NEXT: vmseq.vi v25, v16, 0
-; RV64-NEXT: vmerge.vim v16, v8, 1, v0
-; RV64-NEXT: vs8r.v v16, (a3)
-; RV64-NEXT: add a2, a3, a2
-; RV64-NEXT: vmv1r.v v0, v25
-; RV64-NEXT: vmerge.vim v8, v8, 1, v0
-; RV64-NEXT: vs8r.v v8, (a2)
+; RV64-NEXT: vmerge.vim v8, v24, 1, v0
+; RV64-NEXT: vmseq.vi v0, v16, 0
+; RV64-NEXT: vmerge.vim v16, v24, 1, v0
+; RV64-NEXT: addi a0, sp, 64
+; RV64-NEXT: add a1, a0, a1
+; RV64-NEXT: vs8r.v v8, (a0)
+; RV64-NEXT: add a0, a0, a2
+; RV64-NEXT: vs8r.v v16, (a0)
; RV64-NEXT: lbu a0, 0(a1)
; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
index fa81e1f6f3514..836883c002b8b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll
@@ -382,9 +382,9 @@ define <32 x i64> @vp_abs_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl)
; CHECK-LABEL: vp_abs_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v7, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB34_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
index faf9e630b0e10..ddc0cba841fec 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll
@@ -2696,9 +2696,9 @@ define <128 x i16> @vp_bitreverse_v128i16(<128 x i16> %va, <128 x i1> %m, i32 ze
; CHECK-LABEL: vp_bitreverse_v128i16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 64
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v7, v0, 8
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB34_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 64
@@ -2706,59 +2706,50 @@ define <128 x i16> @vp_bitreverse_v128i16(<128 x i16> %va, <128 x i1> %m, i32 ze
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v8, 8, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
-; CHECK-NEXT: lui a2, 1
-; CHECK-NEXT: lui a4, 3
-; CHECK-NEXT: addi a3, a0, -64
-; CHECK-NEXT: sltu a0, a0, a3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a3, a0, a3
-; CHECK-NEXT: lui a0, 5
+; CHECK-NEXT: lui a1, 1
+; CHECK-NEXT: lui a2, 3
+; CHECK-NEXT: lui a3, 5
; CHECK-NEXT: vor.vv v8, v8, v24, v0.t
-; CHECK-NEXT: addi a5, a2, -241
-; CHECK-NEXT: addi a2, a4, 819
-; CHECK-NEXT: addi a0, a0, 1365
+; CHECK-NEXT: addi a1, a1, -241
+; CHECK-NEXT: addi a2, a2, 819
+; CHECK-NEXT: addi a3, a3, 1365
; CHECK-NEXT: vsrl.vi v24, v8, 4, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a5, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a5, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
-; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v8, 2, v0.t
; CHECK-NEXT: vand.vx v8, v8, a2, v0.t
; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 2, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v24, v16, 4, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a5, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a5, v0.t
-; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
-; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vsrl.vi v24, v8, 1, v0.t
-; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a0, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a3, v0.t
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vor.vv v8, v24, v8, v0.t
+; CHECK-NEXT: addi a4, a0, -64
+; CHECK-NEXT: sltu a0, a0, a4
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a4
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
+; CHECK-NEXT: vsrl.vi v24, v16, 8, v0.t
+; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
+; CHECK-NEXT: vor.vv v16, v16, v24, v0.t
+; CHECK-NEXT: vsrl.vi v24, v16, 4, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
+; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
+; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: vsrl.vi v24, v16, 2, v0.t
; CHECK-NEXT: vand.vx v16, v16, a2, v0.t
; CHECK-NEXT: vand.vx v24, v24, a2, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 2, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: vsrl.vi v24, v16, 1, v0.t
-; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
-; CHECK-NEXT: vand.vx v24, v24, a0, v0.t
+; CHECK-NEXT: vand.vx v16, v16, a3, v0.t
+; CHECK-NEXT: vand.vx v24, v24, a3, v0.t
; CHECK-NEXT: vsll.vi v16, v16, 1, v0.t
; CHECK-NEXT: vor.vv v16, v24, v16, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
index d8b109fcbf77f..83f08ec191d91 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
@@ -1556,9 +1556,9 @@ define <128 x i16> @vp_bswap_v128i16(<128 x i16> %va, <128 x i1> %m, i32 zeroext
; CHECK-LABEL: vp_bswap_v128i16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 64
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v7, v0, 8
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB26_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 64
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
index 5d1a22368ddef..f4d1c2e291ee6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
@@ -31,12 +31,12 @@ define <2 x half> @vp_ceil_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl)
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -115,12 +115,12 @@ define <4 x half> @vp_ceil_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl)
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 3
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
index 0a1dcd4c6abb7..a70aefd2bacf0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll
@@ -1887,301 +1887,183 @@ define <16 x i64> @vp_ctlz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctlz_v32i64:
; RV32: # %bb.0:
-; RV32-NEXT: li a2, 16
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 49
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: sub sp, sp, a1
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a2, a1, 5
+; RV32-NEXT: add a1, a2, a1
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: li a1, 16
+; RV32-NEXT: mv a2, a0
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v24, v0
-; RV32-NEXT: vslidedown.vi v7, v0, 2
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: bltu a0, a2, .LBB34_2
+; RV32-NEXT: vslidedown.vi v16, v0, 2
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 5
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
+; RV32-NEXT: bltu a0, a1, .LBB34_2
; RV32-NEXT: # %bb.1:
-; RV32-NEXT: li a1, 16
+; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB34_2:
-; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 26
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: sub sp, sp, a2
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
-; RV32-NEXT: vmv1r.v v0, v24
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV32-NEXT: li a2, 32
-; RV32-NEXT: addi a3, a0, -16
-; RV32-NEXT: sltu a0, a0, a3
-; RV32-NEXT: addi a0, a0, -1
-; RV32-NEXT: and a0, a0, a3
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: li a1, 32
; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: addi a3, a3, 1365
-; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v6, v0
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v16, 2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 16, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a5, a4, 3
-; RV32-NEXT: add a4, a5, a4
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: li a5, 25
-; RV32-NEXT: mul a4, a4, a5
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vs1r.v v6, (a4) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a4, a3, 4
-; RV32-NEXT: add a3, a4, a3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.v.x v24, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
+; RV32-NEXT: li a4, 24
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v16, v16, v24, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a3, 209715
+; RV32-NEXT: addi a3, a3, 819
+; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
+; RV32-NEXT: li a4, 41
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
+; RV32-NEXT: li a4, 41
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a4, a3, 4
-; RV32-NEXT: add a3, a4, a3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
+; RV32-NEXT: li a4, 41
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a4, a3, 3
-; RV32-NEXT: add a3, a4, a3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v24, v16, a2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v8, v16, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 3
-; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs1r.v v7, (a2) # vscale x 8-byte Folded Spill
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 4
-; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a4, 61681
+; RV32-NEXT: lui a5, 4112
+; RV32-NEXT: li a3, 56
+; RV32-NEXT: addi a4, a4, -241
+; RV32-NEXT: addi a5, a5, 257
+; RV32-NEXT: vsetvli a6, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a4
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: slli a4, a4, 3
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a5
+; RV32-NEXT: addi a4, sp, 16
+; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v8, v8, a3, v0.t
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
-; RV32-NEXT: vmv1r.v v7, v0
; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: addi a2, a0, -16
+; RV32-NEXT: sltu a0, a0, a2
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 3
-; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: slli a4, a2, 5
+; RV32-NEXT: add a2, a4, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v24, 4, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 3
-; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vadd.vv v24, v8, v24, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 4
-; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v8, v24, 1, v0.t
+; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 24
+; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 41
+; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a2, 61681
-; RV32-NEXT: lui a3, 4112
-; RV32-NEXT: addi a2, a2, -241
-; RV32-NEXT: addi a3, a3, 257
; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a4, 25
-; RV32-NEXT: mul a2, a2, a4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a4, a2, 4
-; RV32-NEXT: add a2, a4, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a3, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 26
+; RV32-NEXT: li a1, 49
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -2192,133 +2074,88 @@ define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV64-LABEL: vp_ctlz_v32i64:
; RV64: # %bb.0:
; RV64-NEXT: li a2, 16
+; RV64-NEXT: mv a1, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v7, v0, 2
-; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB34_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB34_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: li a6, 32
+; RV64-NEXT: li a1, 32
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
; RV64-NEXT: lui a5, 4112
-; RV64-NEXT: addi a7, a2, 1365
-; RV64-NEXT: addi a2, a3, 819
-; RV64-NEXT: addi a3, a4, -241
-; RV64-NEXT: addi a4, a5, 257
-; RV64-NEXT: slli a5, a7, 32
-; RV64-NEXT: add a7, a7, a5
-; RV64-NEXT: slli a5, a2, 32
-; RV64-NEXT: add a5, a2, a5
+; RV64-NEXT: addi a2, a2, 1365
+; RV64-NEXT: addi a3, a3, 819
+; RV64-NEXT: addi a4, a4, -241
+; RV64-NEXT: addi a5, a5, 257
+; RV64-NEXT: slli a6, a2, 32
+; RV64-NEXT: add a6, a2, a6
; RV64-NEXT: slli a2, a3, 32
-; RV64-NEXT: add a2, a3, a2
-; RV64-NEXT: slli a3, a4, 32
-; RV64-NEXT: add a3, a4, a3
-; RV64-NEXT: addi a4, a0, -16
-; RV64-NEXT: sltu a0, a0, a4
-; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a4, a0, a4
-; RV64-NEXT: li a0, 56
+; RV64-NEXT: add a3, a3, a2
+; RV64-NEXT: slli a2, a4, 32
+; RV64-NEXT: add a2, a4, a2
+; RV64-NEXT: slli a4, a5, 32
+; RV64-NEXT: add a4, a5, a4
+; RV64-NEXT: li a5, 56
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 2, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v6, v0
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 8, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 2, v0.t
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 16, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vsrl.vx v24, v8, a1, v0.t
+; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV64-NEXT: vand.vx v24, v8, a3, v0.t
+; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV64-NEXT: vand.vx v8, v8, a3, v0.t
+; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: vsrl.vx v8, v8, a5, v0.t
+; RV64-NEXT: addi a7, a0, -16
+; RV64-NEXT: sltu a0, a0, a7
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a0, a0, a7
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
+; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vsrl.vi v24, v16, 2, v0.t
+; RV64-NEXT: vor.vv v16, v16, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v24, v8, a6, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 8, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vnot.v v8, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 16, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a7, v0.t
-; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v24, v16, a6, v0.t
+; RV64-NEXT: vsrl.vx v24, v16, a1, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v8, a5, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vnot.v v16, v16, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v8, v8, a5, v0.t
-; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a7, v0.t
+; RV64-NEXT: vand.vx v24, v24, a6, v0.t
; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v16, a5, v0.t
+; RV64-NEXT: vand.vx v24, v16, a3, v0.t
; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v16, a5, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v16, v16, a3, v0.t
; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vmul.vx v16, v16, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t
+; RV64-NEXT: vmul.vx v16, v16, a4, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a5, v0.t
; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
@@ -4426,323 +4263,205 @@ define <16 x i64> @vp_ctlz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroex
; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vsrl.vx v16, v8, a4
; RV64-NEXT: vor.vv v8, v8, v16
-; RV64-NEXT: vnot.v v8, v8
-; RV64-NEXT: vsrl.vi v16, v8, 1
-; RV64-NEXT: vand.vx v16, v16, a0
-; RV64-NEXT: vsub.vv v8, v8, v16
-; RV64-NEXT: vand.vx v16, v8, a1
-; RV64-NEXT: vsrl.vi v8, v8, 2
-; RV64-NEXT: vand.vx v8, v8, a1
-; RV64-NEXT: vadd.vv v8, v16, v8
-; RV64-NEXT: vsrl.vi v16, v8, 4
-; RV64-NEXT: vadd.vv v8, v8, v16
-; RV64-NEXT: vand.vx v8, v8, a2
-; RV64-NEXT: vmul.vx v8, v8, a3
-; RV64-NEXT: li a0, 56
-; RV64-NEXT: vsrl.vx v8, v8, a0
-; RV64-NEXT: ret
- %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl)
- ret <16 x i64> %v
-}
-
-define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
-; RV32-LABEL: vp_ctlz_zero_undef_v32i64:
-; RV32: # %bb.0:
-; RV32-NEXT: li a2, 16
-; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v24, v0
-; RV32-NEXT: vslidedown.vi v7, v0, 2
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: bltu a0, a2, .LBB70_2
-; RV32-NEXT: # %bb.1:
-; RV32-NEXT: li a1, 16
-; RV32-NEXT: .LBB70_2:
-; RV32-NEXT: addi sp, sp, -16
-; RV32-NEXT: .cfi_def_cfa_offset 16
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 26
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: sub sp, sp, a2
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
-; RV32-NEXT: vmv1r.v v0, v24
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV32-NEXT: li a2, 32
-; RV32-NEXT: addi a3, a0, -16
-; RV32-NEXT: sltu a0, a0, a3
-; RV32-NEXT: addi a0, a0, -1
-; RV32-NEXT: and a0, a0, a3
-; RV32-NEXT: lui a3, 349525
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: addi a3, a3, 1365
-; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v6, v0
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v16, 2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t
-; RV32-NEXT: vor.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v16, 8, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: vsrl.vi v24, v16, 16, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a5, a4, 3
-; RV32-NEXT: add a4, a5, a4
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: li a5, 25
-; RV32-NEXT: mul a4, a4, a5
-; RV32-NEXT: add a4, sp, a4
-; RV32-NEXT: addi a4, a4, 16
-; RV32-NEXT: vs1r.v v6, (a4) # vscale x 8-byte Folded Spill
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
+; RV64-NEXT: vnot.v v8, v8
+; RV64-NEXT: vsrl.vi v16, v8, 1
+; RV64-NEXT: vand.vx v16, v16, a0
+; RV64-NEXT: vsub.vv v8, v8, v16
+; RV64-NEXT: vand.vx v16, v8, a1
+; RV64-NEXT: vsrl.vi v8, v8, 2
+; RV64-NEXT: vand.vx v8, v8, a1
+; RV64-NEXT: vadd.vv v8, v16, v8
+; RV64-NEXT: vsrl.vi v16, v8, 4
+; RV64-NEXT: vadd.vv v8, v8, v16
+; RV64-NEXT: vand.vx v8, v8, a2
+; RV64-NEXT: vmul.vx v8, v8, a3
+; RV64-NEXT: li a0, 56
+; RV64-NEXT: vsrl.vx v8, v8, a0
+; RV64-NEXT: ret
+ %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl)
+ ret <16 x i64> %v
+}
+
+define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
+; RV32-LABEL: vp_ctlz_zero_undef_v32i64:
+; RV32: # %bb.0:
+; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: .cfi_def_cfa_offset 16
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a2, 49
+; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: sub sp, sp, a1
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: slli a2, a1, 5
+; RV32-NEXT: add a1, a2, a1
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: li a1, 16
+; RV32-NEXT: mv a2, a0
+; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vi v16, v0, 2
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a4, a3, 4
-; RV32-NEXT: add a3, a4, a3
+; RV32-NEXT: slli a3, a3, 5
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
+; RV32-NEXT: bltu a0, a1, .LBB70_2
+; RV32-NEXT: # %bb.1:
+; RV32-NEXT: li a2, 16
+; RV32-NEXT: .LBB70_2:
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: li a1, 32
+; RV32-NEXT: lui a3, 349525
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: addi a3, a3, 1365
+; RV32-NEXT: vsrl.vi v16, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: vor.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v24, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
+; RV32-NEXT: li a4, 24
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vand.vv v16, v16, v24, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a3, 209715
+; RV32-NEXT: addi a3, a3, 819
+; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
+; RV32-NEXT: li a4, 41
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
+; RV32-NEXT: li a4, 41
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a4, a3, 4
-; RV32-NEXT: add a3, a4, a3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
+; RV32-NEXT: li a4, 41
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a4, a3, 3
-; RV32-NEXT: add a3, a4, a3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v24, v16, a2, v0.t
-; RV32-NEXT: vor.vv v16, v16, v24, v0.t
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v8, v16, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 3
-; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs1r.v v7, (a2) # vscale x 8-byte Folded Spill
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 4
-; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a4, 61681
+; RV32-NEXT: lui a5, 4112
+; RV32-NEXT: li a3, 56
+; RV32-NEXT: addi a4, a4, -241
+; RV32-NEXT: addi a5, a5, 257
+; RV32-NEXT: vsetvli a6, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a4
+; RV32-NEXT: csrr a4, vlenb
+; RV32-NEXT: slli a4, a4, 3
+; RV32-NEXT: add a4, sp, a4
+; RV32-NEXT: addi a4, a4, 16
+; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a5
+; RV32-NEXT: addi a4, sp, 16
+; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v8, v8, a3, v0.t
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
-; RV32-NEXT: vmv1r.v v7, v0
; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: addi a2, a0, -16
+; RV32-NEXT: sltu a0, a0, a2
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 3
-; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: slli a4, a2, 5
+; RV32-NEXT: add a2, a4, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v24, 4, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 3
-; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vadd.vv v24, v8, v24, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 4
-; RV32-NEXT: add a2, a3, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v8, v24, 1, v0.t
+; RV32-NEXT: vor.vv v8, v24, v8, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 2, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 16, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t
+; RV32-NEXT: vor.vv v8, v8, v24, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 24
+; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 41
+; RV32-NEXT: mul a0, a0, a1
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a2, 61681
-; RV32-NEXT: lui a3, 4112
-; RV32-NEXT: addi a2, a2, -241
-; RV32-NEXT: addi a3, a3, 257
; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a4, 25
-; RV32-NEXT: mul a2, a2, a4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a4, a2, 4
-; RV32-NEXT: add a2, a4, a2
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a3
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a3, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 26
+; RV32-NEXT: li a1, 49
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -4753,133 +4472,88 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV64-LABEL: vp_ctlz_zero_undef_v32i64:
; RV64: # %bb.0:
; RV64-NEXT: li a2, 16
+; RV64-NEXT: mv a1, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v7, v0, 2
-; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB70_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB70_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: li a6, 32
+; RV64-NEXT: li a1, 32
; RV64-NEXT: lui a2, 349525
; RV64-NEXT: lui a3, 209715
; RV64-NEXT: lui a4, 61681
; RV64-NEXT: lui a5, 4112
-; RV64-NEXT: addi a7, a2, 1365
-; RV64-NEXT: addi a2, a3, 819
-; RV64-NEXT: addi a3, a4, -241
-; RV64-NEXT: addi a4, a5, 257
-; RV64-NEXT: slli a5, a7, 32
-; RV64-NEXT: add a7, a7, a5
-; RV64-NEXT: slli a5, a2, 32
-; RV64-NEXT: add a5, a2, a5
+; RV64-NEXT: addi a2, a2, 1365
+; RV64-NEXT: addi a3, a3, 819
+; RV64-NEXT: addi a4, a4, -241
+; RV64-NEXT: addi a5, a5, 257
+; RV64-NEXT: slli a6, a2, 32
+; RV64-NEXT: add a6, a2, a6
; RV64-NEXT: slli a2, a3, 32
-; RV64-NEXT: add a2, a3, a2
-; RV64-NEXT: slli a3, a4, 32
-; RV64-NEXT: add a3, a4, a3
-; RV64-NEXT: addi a4, a0, -16
-; RV64-NEXT: sltu a0, a0, a4
-; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a4, a0, a4
-; RV64-NEXT: li a0, 56
+; RV64-NEXT: add a3, a3, a2
+; RV64-NEXT: slli a2, a4, 32
+; RV64-NEXT: add a2, a4, a2
+; RV64-NEXT: slli a4, a5, 32
+; RV64-NEXT: add a4, a5, a4
+; RV64-NEXT: li a5, 56
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 2, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v6, v0
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 8, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 2, v0.t
-; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 16, v0.t
; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vsrl.vx v24, v8, a1, v0.t
+; RV64-NEXT: vor.vv v8, v8, v24, v0.t
+; RV64-NEXT: vnot.v v8, v8, v0.t
+; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV64-NEXT: vand.vx v24, v8, a3, v0.t
+; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV64-NEXT: vand.vx v8, v8, a3, v0.t
+; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: vsrl.vx v8, v8, a5, v0.t
+; RV64-NEXT: addi a7, a0, -16
+; RV64-NEXT: sltu a0, a0, a7
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a0, a0, a7
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
+; RV64-NEXT: vor.vv v16, v16, v24, v0.t
+; RV64-NEXT: vsrl.vi v24, v16, 2, v0.t
+; RV64-NEXT: vor.vv v16, v16, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v24, v8, a6, v0.t
-; RV64-NEXT: vor.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 8, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vnot.v v8, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 16, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a7, v0.t
-; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v24, v16, a6, v0.t
+; RV64-NEXT: vsrl.vx v24, v16, a1, v0.t
; RV64-NEXT: vor.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v8, a5, v0.t
-; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vnot.v v16, v16, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v8, v8, a5, v0.t
-; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a7, v0.t
+; RV64-NEXT: vand.vx v24, v24, a6, v0.t
; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
-; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v16, a5, v0.t
+; RV64-NEXT: vand.vx v24, v16, a3, v0.t
; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v8, v8, a2, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v16, a5, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vmul.vx v8, v8, a3, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vand.vx v16, v16, a3, v0.t
; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vmul.vx v16, v16, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t
+; RV64-NEXT: vmul.vx v16, v16, a4, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a5, v0.t
; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
index ec6b0290a18ce..289948dbbf87d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll
@@ -1394,122 +1394,219 @@ define <32 x i64> @vp_ctpop_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 24
+; RV32-NEXT: li a2, 49
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 4
+; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: li a2, 16
+; RV32-NEXT: li a1, 16
+; RV32-NEXT: mv a2, a0
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vmv1r.v v16, v0
-; RV32-NEXT: vslidedown.vi v7, v0, 2
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: bltu a0, a2, .LBB34_2
+; RV32-NEXT: vslidedown.vi v16, v0, 2
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: li a4, 48
+; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
+; RV32-NEXT: bltu a0, a1, .LBB34_2
; RV32-NEXT: # %bb.1:
-; RV32-NEXT: li a1, 16
+; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB34_2:
-; RV32-NEXT: vmv1r.v v0, v16
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV32-NEXT: lui a2, 349525
-; RV32-NEXT: addi a2, a2, 1365
+; RV32-NEXT: lui a1, 349525
+; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a2
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vmv.v.x v24, a1
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 24
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24, v0.t
; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a1
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 40
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 40
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 40
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vand.vv v8, v8, v24, v0.t
+; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a3, 61681
+; RV32-NEXT: lui a4, 4112
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: addi a3, a3, -241
+; RV32-NEXT: addi a4, a4, 257
+; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a3
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 4
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a4
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: addi a2, sp, 16
; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v6, v0
; RV32-NEXT: addi a2, a0, -16
; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a2
-; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
+; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
-; RV32-NEXT: vand.vv v16, v16, v24, v0.t
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
-; RV32-NEXT: addi a3, sp, 16
-; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: vmv1r.v v0, v6
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: li a3, 48
+; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
+; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v8, v24, 1, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 24
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 40
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v8, v16, v0.t
-; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a2, 61681
-; RV32-NEXT: addi a2, a2, -241
-; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: lui a2, 4112
-; RV32-NEXT: addi a2, a2, 257
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 24
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 48
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 49
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -1520,82 +1617,61 @@ define <32 x i64> @vp_ctpop_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; RV64-LABEL: vp_ctpop_v32i64:
; RV64: # %bb.0:
; RV64-NEXT: li a2, 16
+; RV64-NEXT: mv a1, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v7, v0, 2
-; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB34_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB34_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: lui a3, 209715
-; RV64-NEXT: lui a4, 61681
-; RV64-NEXT: lui a5, 4112
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: addi a3, a3, 819
-; RV64-NEXT: addi a4, a4, -241
-; RV64-NEXT: addi a5, a5, 257
-; RV64-NEXT: slli a6, a2, 32
-; RV64-NEXT: add a6, a2, a6
-; RV64-NEXT: slli a2, a3, 32
-; RV64-NEXT: add a7, a3, a2
-; RV64-NEXT: slli a3, a4, 32
-; RV64-NEXT: add a3, a4, a3
-; RV64-NEXT: slli a2, a5, 32
-; RV64-NEXT: add a2, a5, a2
-; RV64-NEXT: addi a4, a0, -16
-; RV64-NEXT: sltu a0, a0, a4
-; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a4, a0, a4
-; RV64-NEXT: li a0, 56
-; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: lui a2, 209715
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: lui a4, 4112
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: addi a2, a2, 819
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 257
+; RV64-NEXT: slli a5, a1, 32
+; RV64-NEXT: add a1, a1, a5
+; RV64-NEXT: slli a5, a2, 32
+; RV64-NEXT: add a2, a2, a5
+; RV64-NEXT: slli a5, a3, 32
+; RV64-NEXT: add a3, a3, a5
+; RV64-NEXT: slli a5, a4, 32
+; RV64-NEXT: add a4, a4, a5
+; RV64-NEXT: li a5, 56
+; RV64-NEXT: vand.vx v24, v24, a1, v0.t
; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v6, v0
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a6, v0.t
-; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v8, a7, v0.t
+; RV64-NEXT: vand.vx v24, v8, a2, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a7, v0.t
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v16, a7, v0.t
-; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
-; RV64-NEXT: vand.vx v16, v16, a7, v0.t
-; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vand.vx v8, v8, a3, v0.t
+; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: vsrl.vx v8, v8, a5, v0.t
+; RV64-NEXT: addi a6, a0, -16
+; RV64-NEXT: sltu a0, a0, a6
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a0, a0, a6
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a1, v0.t
+; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
+; RV64-NEXT: vand.vx v24, v16, a2, v0.t
+; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
+; RV64-NEXT: vand.vx v16, v16, a2, v0.t
+; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vmul.vx v8, v8, a2, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v16, a3, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vmul.vx v16, v16, a2, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t
+; RV64-NEXT: vmul.vx v16, v16, a4, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a5, v0.t
; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.ctpop.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
index 5ad84a7fe96c5..46d62f48e7ef8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll
@@ -1526,253 +1526,160 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 26
+; RV32-NEXT: li a2, 49
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: slli a2, a1, 5
+; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: li a2, 16
+; RV32-NEXT: li a1, 16
+; RV32-NEXT: mv a2, a0
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v24, v0, 2
+; RV32-NEXT: vslidedown.vi v16, v0, 2
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 5
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
+; RV32-NEXT: bltu a0, a1, .LBB34_2
+; RV32-NEXT: # %bb.1:
+; RV32-NEXT: li a2, 16
+; RV32-NEXT: .LBB34_2:
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vadd.vi v16, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: lui a1, 349525
+; RV32-NEXT: vand.vv v24, v8, v16, v0.t
+; RV32-NEXT: addi a1, a1, 1365
+; RV32-NEXT: vsrl.vi v16, v24, 1, v0.t
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v8, a1
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a3, 24
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: bltu a0, a2, .LBB34_2
-; RV32-NEXT: # %bb.1:
-; RV32-NEXT: li a1, 16
-; RV32-NEXT: .LBB34_2:
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vadd.vi v24, v8, -1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v16, v16, v8, v0.t
+; RV32-NEXT: vsub.vv v8, v24, v16, v0.t
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a1
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 41
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 41
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 41
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a3, 61681
+; RV32-NEXT: lui a4, 4112
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: addi a3, a3, -241
+; RV32-NEXT: addi a4, a4, 257
+; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
-; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a2
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v16, v24, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: vmv.v.x v16, a4
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: addi a2, a0, -16
; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vi v8, v16, -1, v0.t
-; RV32-NEXT: vnot.v v16, v16, v0.t
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v24, v16, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v24, 4, v0.t
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vadd.vv v24, v8, v24, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl1r.v v7, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: slli a3, a2, 5
+; RV32-NEXT: add a2, a3, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vadd.vi v8, v24, -1, v0.t
+; RV32-NEXT: vnot.v v24, v24, v0.t
+; RV32-NEXT: vand.vv v8, v24, v8, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 24
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 41
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a2, 61681
-; RV32-NEXT: addi a2, a2, -241
; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: vmv1r.v v6, v0
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: lui a2, 4112
-; RV32-NEXT: addi a2, a2, 257
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 26
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 49
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -1783,9 +1690,9 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV64-LABEL: vp_cttz_v32i64:
; RV64: # %bb.0:
; RV64-NEXT: li a2, 16
+; RV64-NEXT: mv a1, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v7, v0, 2
-; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB34_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
@@ -1793,78 +1700,57 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vadd.vi v24, v8, -1, v0.t
; RV64-NEXT: vnot.v v8, v8, v0.t
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: lui a3, 209715
-; RV64-NEXT: lui a4, 61681
-; RV64-NEXT: lui a5, 4112
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: addi a3, a3, 819
-; RV64-NEXT: addi a4, a4, -241
-; RV64-NEXT: addi a5, a5, 257
-; RV64-NEXT: slli a6, a2, 32
-; RV64-NEXT: add a6, a2, a6
-; RV64-NEXT: slli a2, a3, 32
-; RV64-NEXT: add a7, a3, a2
-; RV64-NEXT: slli a2, a4, 32
-; RV64-NEXT: add a2, a4, a2
-; RV64-NEXT: slli a3, a5, 32
-; RV64-NEXT: add a3, a5, a3
-; RV64-NEXT: addi a4, a0, -16
-; RV64-NEXT: sltu a0, a0, a4
-; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a4, a0, a4
-; RV64-NEXT: li a0, 56
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: lui a2, 209715
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: lui a4, 4112
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: addi a2, a2, 819
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 257
+; RV64-NEXT: slli a5, a1, 32
+; RV64-NEXT: add a1, a1, a5
+; RV64-NEXT: slli a5, a2, 32
+; RV64-NEXT: add a2, a2, a5
+; RV64-NEXT: slli a5, a3, 32
+; RV64-NEXT: add a3, a3, a5
+; RV64-NEXT: slli a5, a4, 32
+; RV64-NEXT: add a4, a4, a5
+; RV64-NEXT: li a5, 56
; RV64-NEXT: vand.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a6, v0.t
-; RV64-NEXT: vsub.vv v24, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v6, v0
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vadd.vi v8, v16, -1, v0.t
-; RV64-NEXT: vnot.v v16, v16, v0.t
-; RV64-NEXT: vand.vv v8, v16, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v24, a7, v0.t
-; RV64-NEXT: vsrl.vi v24, v24, 2, v0.t
-; RV64-NEXT: vand.vx v24, v24, a7, v0.t
-; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: vand.vx v24, v24, a1, v0.t
; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v8, a7, v0.t
+; RV64-NEXT: vand.vx v24, v8, a2, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a7, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vadd.vv v24, v24, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vmul.vx v8, v16, a3, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v16, v24, 4, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV64-NEXT: vand.vx v8, v8, a3, v0.t
+; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: vsrl.vx v8, v8, a5, v0.t
+; RV64-NEXT: addi a6, a0, -16
+; RV64-NEXT: sltu a0, a0, a6
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a0, a0, a6
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vadd.vi v24, v16, -1, v0.t
+; RV64-NEXT: vnot.v v16, v16, v0.t
+; RV64-NEXT: vand.vv v16, v16, v24, v0.t
+; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a1, v0.t
+; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
+; RV64-NEXT: vand.vx v24, v16, a2, v0.t
+; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vmul.vx v16, v16, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t
+; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
+; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV64-NEXT: vand.vx v16, v16, a3, v0.t
+; RV64-NEXT: vmul.vx v16, v16, a4, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a5, v0.t
; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
@@ -3569,253 +3455,160 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 26
+; RV32-NEXT: li a2, 49
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1
-; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 3
+; RV32-NEXT: slli a2, a1, 5
+; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: li a2, 16
+; RV32-NEXT: li a1, 16
+; RV32-NEXT: mv a2, a0
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v24, v0, 2
+; RV32-NEXT: vslidedown.vi v16, v0, 2
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 5
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
+; RV32-NEXT: bltu a0, a1, .LBB70_2
+; RV32-NEXT: # %bb.1:
+; RV32-NEXT: li a2, 16
+; RV32-NEXT: .LBB70_2:
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vadd.vi v16, v8, -1, v0.t
+; RV32-NEXT: vnot.v v8, v8, v0.t
+; RV32-NEXT: lui a1, 349525
+; RV32-NEXT: vand.vv v24, v8, v16, v0.t
+; RV32-NEXT: addi a1, a1, 1365
+; RV32-NEXT: vsrl.vi v16, v24, 1, v0.t
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v8, a1
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a3, 24
; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs1r.v v24, (a1) # vscale x 8-byte Folded Spill
-; RV32-NEXT: mv a1, a0
-; RV32-NEXT: bltu a0, a2, .LBB70_2
-; RV32-NEXT: # %bb.1:
-; RV32-NEXT: li a1, 16
-; RV32-NEXT: .LBB70_2:
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vadd.vi v24, v8, -1, v0.t
-; RV32-NEXT: vnot.v v8, v8, v0.t
-; RV32-NEXT: lui a2, 349525
+; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v16, v16, v8, v0.t
+; RV32-NEXT: vsub.vv v8, v24, v16, v0.t
+; RV32-NEXT: lui a1, 209715
+; RV32-NEXT: addi a1, a1, 819
+; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a1
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 41
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 41
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v16, v8, v16, v0.t
+; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
+; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: li a3, 41
+; RV32-NEXT: mul a1, a1, a3
+; RV32-NEXT: add a1, sp, a1
+; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: addi a2, a2, 1365
-; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
+; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
+; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
+; RV32-NEXT: lui a3, 61681
+; RV32-NEXT: lui a4, 4112
+; RV32-NEXT: li a1, 56
+; RV32-NEXT: addi a3, a3, -241
+; RV32-NEXT: addi a4, a4, 257
+; RV32-NEXT: vsetvli a5, zero, e32, m8, ta, ma
+; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 25
-; RV32-NEXT: mul a3, a3, a4
+; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v24, a2
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v16, v24, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsub.vv v24, v8, v24, v0.t
+; RV32-NEXT: vmv.v.x v16, a4
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
+; RV32-NEXT: addi a2, sp, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: addi a2, a0, -16
; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vadd.vi v8, v16, -1, v0.t
-; RV32-NEXT: vnot.v v16, v16, v0.t
-; RV32-NEXT: vand.vv v8, v16, v8, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: lui a2, 209715
-; RV32-NEXT: addi a2, a2, 819
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v8, v24, v16, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vand.vv v8, v8, v24, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsub.vv v8, v24, v8, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vi v24, v24, 4, v0.t
-; RV32-NEXT: addi a2, sp, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vadd.vv v24, v8, v24, v0.t
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 4
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 25
-; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl1r.v v7, (a2) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 24
-; RV32-NEXT: mul a2, a2, a3
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 3
+; RV32-NEXT: slli a3, a2, 5
+; RV32-NEXT: add a2, a3, a2
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vadd.vi v8, v24, -1, v0.t
+; RV32-NEXT: vnot.v v24, v24, v0.t
+; RV32-NEXT: vand.vv v8, v24, v8, v0.t
+; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 24
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vand.vv v24, v24, v16, v0.t
+; RV32-NEXT: vsub.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a2, 41
+; RV32-NEXT: mul a0, a0, a2
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: lui a2, 61681
-; RV32-NEXT: addi a2, a2, -241
; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
-; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
-; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
-; RV32-NEXT: vmv1r.v v6, v0
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: lui a2, 4112
-; RV32-NEXT: addi a2, a2, 257
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: slli a3, a3, 4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v24, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vand.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV32-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: slli a0, a0, 4
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
-; RV32-NEXT: vsetvli a3, zero, e32, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a2
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v24, v24, v16, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vmul.vv v16, v8, v16, v0.t
-; RV32-NEXT: li a2, 56
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v8, v24, a2, v0.t
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; RV32-NEXT: vsrl.vx v16, v16, a2, v0.t
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 26
+; RV32-NEXT: slli a0, a0, 3
+; RV32-NEXT: add a0, sp, a0
+; RV32-NEXT: addi a0, a0, 16
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
+; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
+; RV32-NEXT: addi a0, sp, 16
+; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: csrr a0, vlenb
+; RV32-NEXT: li a1, 49
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -3826,9 +3619,9 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV64-LABEL: vp_cttz_zero_undef_v32i64:
; RV64: # %bb.0:
; RV64-NEXT: li a2, 16
+; RV64-NEXT: mv a1, a0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v7, v0, 2
-; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB70_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
@@ -3836,78 +3629,57 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vadd.vi v24, v8, -1, v0.t
; RV64-NEXT: vnot.v v8, v8, v0.t
-; RV64-NEXT: lui a2, 349525
-; RV64-NEXT: lui a3, 209715
-; RV64-NEXT: lui a4, 61681
-; RV64-NEXT: lui a5, 4112
-; RV64-NEXT: addi a2, a2, 1365
-; RV64-NEXT: addi a3, a3, 819
-; RV64-NEXT: addi a4, a4, -241
-; RV64-NEXT: addi a5, a5, 257
-; RV64-NEXT: slli a6, a2, 32
-; RV64-NEXT: add a6, a2, a6
-; RV64-NEXT: slli a2, a3, 32
-; RV64-NEXT: add a7, a3, a2
-; RV64-NEXT: slli a2, a4, 32
-; RV64-NEXT: add a2, a4, a2
-; RV64-NEXT: slli a3, a5, 32
-; RV64-NEXT: add a3, a5, a3
-; RV64-NEXT: addi a4, a0, -16
-; RV64-NEXT: sltu a0, a0, a4
-; RV64-NEXT: addi a0, a0, -1
-; RV64-NEXT: and a4, a0, a4
-; RV64-NEXT: li a0, 56
+; RV64-NEXT: lui a1, 349525
+; RV64-NEXT: lui a2, 209715
+; RV64-NEXT: lui a3, 61681
+; RV64-NEXT: lui a4, 4112
+; RV64-NEXT: addi a1, a1, 1365
+; RV64-NEXT: addi a2, a2, 819
+; RV64-NEXT: addi a3, a3, -241
+; RV64-NEXT: addi a4, a4, 257
+; RV64-NEXT: slli a5, a1, 32
+; RV64-NEXT: add a1, a1, a5
+; RV64-NEXT: slli a5, a2, 32
+; RV64-NEXT: add a2, a2, a5
+; RV64-NEXT: slli a5, a3, 32
+; RV64-NEXT: add a3, a3, a5
+; RV64-NEXT: slli a5, a4, 32
+; RV64-NEXT: add a4, a4, a5
+; RV64-NEXT: li a5, 56
; RV64-NEXT: vand.vv v8, v8, v24, v0.t
; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a6, v0.t
-; RV64-NEXT: vsub.vv v24, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v6, v0
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vadd.vi v8, v16, -1, v0.t
-; RV64-NEXT: vnot.v v16, v16, v0.t
-; RV64-NEXT: vand.vv v8, v16, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v24, a7, v0.t
-; RV64-NEXT: vsrl.vi v24, v24, 2, v0.t
-; RV64-NEXT: vand.vx v24, v24, a7, v0.t
-; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v8, 1, v0.t
-; RV64-NEXT: vand.vx v24, v24, a6, v0.t
+; RV64-NEXT: vand.vx v24, v24, a1, v0.t
; RV64-NEXT: vsub.vv v8, v8, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
-; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v24, v8, a7, v0.t
+; RV64-NEXT: vand.vx v24, v8, a2, v0.t
; RV64-NEXT: vsrl.vi v8, v8, 2, v0.t
-; RV64-NEXT: vand.vx v8, v8, a7, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vadd.vv v24, v24, v8, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vmul.vx v8, v16, a3, v0.t
-; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vi v16, v24, 4, v0.t
-; RV64-NEXT: vmv1r.v v0, v6
-; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
-; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t
+; RV64-NEXT: vand.vx v8, v8, a2, v0.t
+; RV64-NEXT: vadd.vv v8, v24, v8, v0.t
+; RV64-NEXT: vsrl.vi v24, v8, 4, v0.t
+; RV64-NEXT: vadd.vv v8, v8, v24, v0.t
+; RV64-NEXT: vand.vx v8, v8, a3, v0.t
+; RV64-NEXT: vmul.vx v8, v8, a4, v0.t
+; RV64-NEXT: vsrl.vx v8, v8, a5, v0.t
+; RV64-NEXT: addi a6, a0, -16
+; RV64-NEXT: sltu a0, a0, a6
+; RV64-NEXT: addi a0, a0, -1
+; RV64-NEXT: and a0, a0, a6
; RV64-NEXT: vmv1r.v v0, v7
-; RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
+; RV64-NEXT: vadd.vi v24, v16, -1, v0.t
+; RV64-NEXT: vnot.v v16, v16, v0.t
+; RV64-NEXT: vand.vv v16, v16, v24, v0.t
+; RV64-NEXT: vsrl.vi v24, v16, 1, v0.t
+; RV64-NEXT: vand.vx v24, v24, a1, v0.t
+; RV64-NEXT: vsub.vv v16, v16, v24, v0.t
+; RV64-NEXT: vand.vx v24, v16, a2, v0.t
+; RV64-NEXT: vsrl.vi v16, v16, 2, v0.t
; RV64-NEXT: vand.vx v16, v16, a2, v0.t
-; RV64-NEXT: vmul.vx v16, v16, a3, v0.t
-; RV64-NEXT: vsrl.vx v16, v16, a0, v0.t
+; RV64-NEXT: vadd.vv v16, v24, v16, v0.t
+; RV64-NEXT: vsrl.vi v24, v16, 4, v0.t
+; RV64-NEXT: vadd.vv v16, v16, v24, v0.t
+; RV64-NEXT: vand.vx v16, v16, a3, v0.t
+; RV64-NEXT: vmul.vx v16, v16, a4, v0.t
+; RV64-NEXT: vsrl.vx v16, v16, a5, v0.t
; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
index f37a3cf5e6bb2..5060e01cf9ee6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
@@ -324,24 +324,23 @@ define i1 @extractelt_v256i1(ptr %x, i64 %idx) nounwind {
; RV32-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
; RV32-NEXT: addi s0, sp, 384
; RV32-NEXT: andi sp, sp, -128
-; RV32-NEXT: zext.b a1, a1
; RV32-NEXT: li a2, 128
-; RV32-NEXT: addi a3, a0, 128
; RV32-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; RV32-NEXT: vle8.v v16, (a3)
-; RV32-NEXT: mv a2, sp
; RV32-NEXT: vle8.v v8, (a0)
-; RV32-NEXT: addi a0, sp, 128
-; RV32-NEXT: add a1, a2, a1
-; RV32-NEXT: vmseq.vi v24, v16, 0
-; RV32-NEXT: vmv.v.i v16, 0
+; RV32-NEXT: addi a0, a0, 128
+; RV32-NEXT: vle8.v v16, (a0)
+; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: vmseq.vi v0, v8, 0
-; RV32-NEXT: vmerge.vim v8, v16, 1, v0
-; RV32-NEXT: vmv1r.v v0, v24
-; RV32-NEXT: vmerge.vim v16, v16, 1, v0
-; RV32-NEXT: vse8.v v8, (a2)
-; RV32-NEXT: vse8.v v16, (a0)
-; RV32-NEXT: lbu a0, 0(a1)
+; RV32-NEXT: vmerge.vim v8, v24, 1, v0
+; RV32-NEXT: vmseq.vi v0, v16, 0
+; RV32-NEXT: vmerge.vim v16, v24, 1, v0
+; RV32-NEXT: zext.b a0, a1
+; RV32-NEXT: mv a1, sp
+; RV32-NEXT: addi a2, sp, 128
+; RV32-NEXT: add a0, a1, a0
+; RV32-NEXT: vse8.v v8, (a1)
+; RV32-NEXT: vse8.v v16, (a2)
+; RV32-NEXT: lbu a0, 0(a0)
; RV32-NEXT: addi sp, s0, -384
; RV32-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
@@ -355,24 +354,23 @@ define i1 @extractelt_v256i1(ptr %x, i64 %idx) nounwind {
; RV64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
; RV64-NEXT: addi s0, sp, 384
; RV64-NEXT: andi sp, sp, -128
-; RV64-NEXT: zext.b a1, a1
; RV64-NEXT: li a2, 128
-; RV64-NEXT: addi a3, a0, 128
; RV64-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; RV64-NEXT: vle8.v v16, (a3)
-; RV64-NEXT: mv a2, sp
; RV64-NEXT: vle8.v v8, (a0)
-; RV64-NEXT: addi a0, sp, 128
-; RV64-NEXT: add a1, a2, a1
-; RV64-NEXT: vmseq.vi v24, v16, 0
-; RV64-NEXT: vmv.v.i v16, 0
+; RV64-NEXT: addi a0, a0, 128
+; RV64-NEXT: vle8.v v16, (a0)
+; RV64-NEXT: vmv.v.i v24, 0
; RV64-NEXT: vmseq.vi v0, v8, 0
-; RV64-NEXT: vmerge.vim v8, v16, 1, v0
-; RV64-NEXT: vmv1r.v v0, v24
-; RV64-NEXT: vmerge.vim v16, v16, 1, v0
-; RV64-NEXT: vse8.v v8, (a2)
-; RV64-NEXT: vse8.v v16, (a0)
-; RV64-NEXT: lbu a0, 0(a1)
+; RV64-NEXT: vmerge.vim v8, v24, 1, v0
+; RV64-NEXT: vmseq.vi v0, v16, 0
+; RV64-NEXT: vmerge.vim v16, v24, 1, v0
+; RV64-NEXT: zext.b a0, a1
+; RV64-NEXT: mv a1, sp
+; RV64-NEXT: addi a2, sp, 128
+; RV64-NEXT: add a0, a1, a0
+; RV64-NEXT: vse8.v v8, (a1)
+; RV64-NEXT: vse8.v v16, (a2)
+; RV64-NEXT: lbu a0, 0(a0)
; RV64-NEXT: addi sp, s0, -384
; RV64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
@@ -386,24 +384,23 @@ define i1 @extractelt_v256i1(ptr %x, i64 %idx) nounwind {
; RV32ZBS-NEXT: sw s0, 376(sp) # 4-byte Folded Spill
; RV32ZBS-NEXT: addi s0, sp, 384
; RV32ZBS-NEXT: andi sp, sp, -128
-; RV32ZBS-NEXT: zext.b a1, a1
; RV32ZBS-NEXT: li a2, 128
-; RV32ZBS-NEXT: addi a3, a0, 128
; RV32ZBS-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; RV32ZBS-NEXT: vle8.v v16, (a3)
-; RV32ZBS-NEXT: mv a2, sp
; RV32ZBS-NEXT: vle8.v v8, (a0)
-; RV32ZBS-NEXT: addi a0, sp, 128
-; RV32ZBS-NEXT: add a1, a2, a1
-; RV32ZBS-NEXT: vmseq.vi v24, v16, 0
-; RV32ZBS-NEXT: vmv.v.i v16, 0
+; RV32ZBS-NEXT: addi a0, a0, 128
+; RV32ZBS-NEXT: vle8.v v16, (a0)
+; RV32ZBS-NEXT: vmv.v.i v24, 0
; RV32ZBS-NEXT: vmseq.vi v0, v8, 0
-; RV32ZBS-NEXT: vmerge.vim v8, v16, 1, v0
-; RV32ZBS-NEXT: vmv1r.v v0, v24
-; RV32ZBS-NEXT: vmerge.vim v16, v16, 1, v0
-; RV32ZBS-NEXT: vse8.v v8, (a2)
-; RV32ZBS-NEXT: vse8.v v16, (a0)
-; RV32ZBS-NEXT: lbu a0, 0(a1)
+; RV32ZBS-NEXT: vmerge.vim v8, v24, 1, v0
+; RV32ZBS-NEXT: vmseq.vi v0, v16, 0
+; RV32ZBS-NEXT: vmerge.vim v16, v24, 1, v0
+; RV32ZBS-NEXT: zext.b a0, a1
+; RV32ZBS-NEXT: mv a1, sp
+; RV32ZBS-NEXT: addi a2, sp, 128
+; RV32ZBS-NEXT: add a0, a1, a0
+; RV32ZBS-NEXT: vse8.v v8, (a1)
+; RV32ZBS-NEXT: vse8.v v16, (a2)
+; RV32ZBS-NEXT: lbu a0, 0(a0)
; RV32ZBS-NEXT: addi sp, s0, -384
; RV32ZBS-NEXT: lw ra, 380(sp) # 4-byte Folded Reload
; RV32ZBS-NEXT: lw s0, 376(sp) # 4-byte Folded Reload
@@ -417,24 +414,23 @@ define i1 @extractelt_v256i1(ptr %x, i64 %idx) nounwind {
; RV64ZBS-NEXT: sd s0, 368(sp) # 8-byte Folded Spill
; RV64ZBS-NEXT: addi s0, sp, 384
; RV64ZBS-NEXT: andi sp, sp, -128
-; RV64ZBS-NEXT: zext.b a1, a1
; RV64ZBS-NEXT: li a2, 128
-; RV64ZBS-NEXT: addi a3, a0, 128
; RV64ZBS-NEXT: vsetvli zero, a2, e8, m8, ta, ma
-; RV64ZBS-NEXT: vle8.v v16, (a3)
-; RV64ZBS-NEXT: mv a2, sp
; RV64ZBS-NEXT: vle8.v v8, (a0)
-; RV64ZBS-NEXT: addi a0, sp, 128
-; RV64ZBS-NEXT: add a1, a2, a1
-; RV64ZBS-NEXT: vmseq.vi v24, v16, 0
-; RV64ZBS-NEXT: vmv.v.i v16, 0
+; RV64ZBS-NEXT: addi a0, a0, 128
+; RV64ZBS-NEXT: vle8.v v16, (a0)
+; RV64ZBS-NEXT: vmv.v.i v24, 0
; RV64ZBS-NEXT: vmseq.vi v0, v8, 0
-; RV64ZBS-NEXT: vmerge.vim v8, v16, 1, v0
-; RV64ZBS-NEXT: vmv1r.v v0, v24
-; RV64ZBS-NEXT: vmerge.vim v16, v16, 1, v0
-; RV64ZBS-NEXT: vse8.v v8, (a2)
-; RV64ZBS-NEXT: vse8.v v16, (a0)
-; RV64ZBS-NEXT: lbu a0, 0(a1)
+; RV64ZBS-NEXT: vmerge.vim v8, v24, 1, v0
+; RV64ZBS-NEXT: vmseq.vi v0, v16, 0
+; RV64ZBS-NEXT: vmerge.vim v16, v24, 1, v0
+; RV64ZBS-NEXT: zext.b a0, a1
+; RV64ZBS-NEXT: mv a1, sp
+; RV64ZBS-NEXT: addi a2, sp, 128
+; RV64ZBS-NEXT: add a0, a1, a0
+; RV64ZBS-NEXT: vse8.v v8, (a1)
+; RV64ZBS-NEXT: vse8.v v16, (a2)
+; RV64ZBS-NEXT: lbu a0, 0(a0)
; RV64ZBS-NEXT: addi sp, s0, -384
; RV64ZBS-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; RV64ZBS-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
index b5ec8d73c48de..de4cff9b4c3e0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
@@ -31,12 +31,12 @@ define <2 x half> @vp_floor_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl)
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -115,12 +115,12 @@ define <4 x half> @vp_floor_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl)
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
index 5f8272ef76ef9..21dab2385a796 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll
@@ -612,13 +612,16 @@ define <32 x double> @vfmax_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a1)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
@@ -631,26 +634,25 @@ define <32 x double> @vfmax_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: .LBB25_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v24, v24
; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
; CHECK-NEXT: vfmax.vv v8, v8, v16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -658,10 +660,7 @@ define <32 x double> @vfmax_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
; CHECK-NEXT: vfmax.vv v16, v16, v24
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
index c173443acb20a..45c047b12f704 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll
@@ -612,13 +612,16 @@ define <32 x double> @vfmin_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a1)
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
@@ -631,26 +634,25 @@ define <32 x double> @vfmin_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: .LBB25_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v24, v24
; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
; CHECK-NEXT: vfmin.vv v8, v8, v16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -658,10 +660,7 @@ define <32 x double> @vfmin_vv_v32f64_unmasked(<32 x double> %va, <32 x double>
; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
; CHECK-NEXT: vfmin.vv v16, v16, v24
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
index 135088631abac..19bedd47808fd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll
@@ -87,9 +87,9 @@ define <32 x double> @vfpext_v32f32_v32f64(<32 x float> %a, <32 x i1> %m, i32 ze
; CHECK-LABEL: vfpext_v32f32_v32f64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB7_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
index 96eda109e1c70..b298a37655a2f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
@@ -367,9 +367,9 @@ define <32 x i64> @vfptosi_v32i64_v32f64(<32 x double> %va, <32 x i1> %m, i32 ze
; CHECK-LABEL: vfptosi_v32i64_v32f64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB25_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
index 4020100bf364b..ac83f1e630ce3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
@@ -367,9 +367,9 @@ define <32 x i64> @vfptoui_v32i64_v32f64(<32 x double> %va, <32 x i1> %m, i32 ze
; CHECK-LABEL: vfptoui_v32i64_v32f64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB25_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
index e509722b623a2..472ed89cce10c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll
@@ -89,8 +89,8 @@ define <32 x float> @vfptrunc_v32f32_v32f64(<32 x double> %a, <32 x i1> %m, i32
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: vslidedown.vi v12, v0, 2
; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: vslidedown.vi v12, v0, 2
; CHECK-NEXT: bltu a0, a2, .LBB7_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
index 488a076c316be..e1fbf9c511d81 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
@@ -530,214 +530,187 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 74
+; RV32-NEXT: li a3, 76
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: sub sp, sp, a2
-; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xca, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 74 * vlenb
-; RV32-NEXT: addi a4, a1, 128
-; RV32-NEXT: li a2, 32
-; RV32-NEXT: lui a5, 12291
-; RV32-NEXT: lui a3, %hi(.LCPI27_0)
-; RV32-NEXT: addi a3, a3, %lo(.LCPI27_0)
-; RV32-NEXT: lui a6, 49164
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; RV32-NEXT: vle32.v v8, (a4)
-; RV32-NEXT: lui a4, 196656
-; RV32-NEXT: addi a5, a5, 3
-; RV32-NEXT: vmv.s.x v0, a5
+; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xcc, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 76 * vlenb
+; RV32-NEXT: addi a5, a1, 128
+; RV32-NEXT: li a6, 32
+; RV32-NEXT: lui a4, 12291
+; RV32-NEXT: lui a3, 49164
+; RV32-NEXT: lui a2, 196656
+; RV32-NEXT: vsetvli zero, a6, e32, m8, ta, ma
+; RV32-NEXT: vle32.v v8, (a5)
; RV32-NEXT: lui a5, 786624
-; RV32-NEXT: vle32.v v16, (a1)
-; RV32-NEXT: addi a6, a6, 12
-; RV32-NEXT: vmv.s.x v7, a6
-; RV32-NEXT: lui a6, 768
-; RV32-NEXT: addi a4, a4, 48
-; RV32-NEXT: vmerge.vvm v24, v8, v16, v0
-; RV32-NEXT: csrr a7, vlenb
-; RV32-NEXT: li t0, 66
-; RV32-NEXT: mul a7, a7, t0
-; RV32-NEXT: add a7, sp, a7
-; RV32-NEXT: addi a7, a7, 16
-; RV32-NEXT: vs8r.v v24, (a7) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv.s.x v6, a4
-; RV32-NEXT: lui a4, 3073
+; RV32-NEXT: vle32.v v24, (a1)
+; RV32-NEXT: addi a4, a4, 3
+; RV32-NEXT: vmv.s.x v0, a4
+; RV32-NEXT: lui a4, 768
+; RV32-NEXT: addi a3, a3, 12
+; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV32-NEXT: csrr a6, vlenb
+; RV32-NEXT: li a7, 48
+; RV32-NEXT: mul a6, a6, a7
+; RV32-NEXT: add a6, sp, a6
+; RV32-NEXT: addi a6, a6, 16
+; RV32-NEXT: vs8r.v v16, (a6) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.s.x v0, a3
+; RV32-NEXT: lui a3, 3073
+; RV32-NEXT: addi a2, a2, 48
; RV32-NEXT: addi a5, a5, 192
-; RV32-NEXT: addi a6, a6, 768
-; RV32-NEXT: addi a4, a4, -1024
-; RV32-NEXT: vmv1r.v v0, v7
-; RV32-NEXT: vmerge.vvm v24, v8, v16, v0
-; RV32-NEXT: csrr a7, vlenb
-; RV32-NEXT: li t0, 26
-; RV32-NEXT: mul a7, a7, t0
-; RV32-NEXT: add a7, sp, a7
-; RV32-NEXT: addi a7, a7, 16
-; RV32-NEXT: vs8r.v v24, (a7) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv.s.x v5, a5
-; RV32-NEXT: vmv1r.v v0, v6
-; RV32-NEXT: vmerge.vvm v24, v8, v16, v0
-; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a7, 34
-; RV32-NEXT: mul a5, a5, a7
-; RV32-NEXT: add a5, sp, a5
-; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv.s.x v4, a6
-; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; RV32-NEXT: vle16.v v6, (a3)
-; RV32-NEXT: vmv1r.v v0, v5
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
-; RV32-NEXT: vmerge.vvm v24, v8, v16, v0
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a5, 42
-; RV32-NEXT: mul a3, a3, a5
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv.s.x v5, a4
-; RV32-NEXT: vmv1r.v v0, v4
-; RV32-NEXT: vmerge.vvm v24, v8, v16, v0
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 50
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v5
-; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 58
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 66
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vl8r.v v8, (a3) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vrgatherei16.vv v16, v8, v6
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li a4, 10
-; RV32-NEXT: mul a3, a3, a4
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: addi a4, a4, 768
+; RV32-NEXT: addi a3, a3, -1024
+; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV32-NEXT: csrr a6, vlenb
+; RV32-NEXT: li a7, 20
+; RV32-NEXT: mul a6, a6, a7
+; RV32-NEXT: add a6, sp, a6
+; RV32-NEXT: addi a6, a6, 16
+; RV32-NEXT: vs8r.v v16, (a6) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.s.x v0, a2
+; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 5
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.s.x v0, a5
+; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a5, 40
+; RV32-NEXT: mul a2, a2, a5
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.s.x v0, a4
+; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a4, 56
+; RV32-NEXT: mul a2, a2, a4
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv.s.x v0, a3
+; RV32-NEXT: vmerge.vvm v8, v8, v24, v0
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: slli a2, a2, 6
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: addi a1, a1, 256
-; RV32-NEXT: lui a3, 12
-; RV32-NEXT: lui a4, 3
-; RV32-NEXT: li a5, 48
-; RV32-NEXT: li a6, 192
-; RV32-NEXT: addi a4, a4, 3
-; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; RV32-NEXT: lui a2, 12
+; RV32-NEXT: lui a3, 3
+; RV32-NEXT: li a4, 48
+; RV32-NEXT: li a5, 192
; RV32-NEXT: vle32.v v8, (a1)
-; RV32-NEXT: addi a1, a3, 12
-; RV32-NEXT: vmv.s.x v16, a5
-; RV32-NEXT: vmv.s.x v0, a4
+; RV32-NEXT: addi a3, a3, 3
+; RV32-NEXT: addi a1, a2, 12
+; RV32-NEXT: vmv.s.x v0, a3
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v8, 16
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; RV32-NEXT: vmerge.vvm v12, v24, v8, v0
-; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a2, a2, 1
-; RV32-NEXT: add a2, sp, a2
-; RV32-NEXT: addi a2, a2, 16
-; RV32-NEXT: vs4r.v v12, (a2) # vscale x 32-byte Folded Spill
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: slli a3, a3, 3
+; RV32-NEXT: add a3, sp, a3
+; RV32-NEXT: addi a3, a3, 16
+; RV32-NEXT: vs4r.v v12, (a3) # vscale x 32-byte Folded Spill
; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: vmerge.vvm v12, v24, v8, v0
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 6
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: li a3, 12
+; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
-; RV32-NEXT: vmv.s.x v17, a6
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmv.s.x v0, a4
; RV32-NEXT: vmerge.vvm v12, v24, v8, v0
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 22
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: li a3, 28
+; RV32-NEXT: mul a1, a1, a3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
-; RV32-NEXT: vslideup.vi v4, v8, 4
-; RV32-NEXT: vslideup.vi v12, v8, 2
-; RV32-NEXT: vmv1r.v v0, v17
+; RV32-NEXT: vmv.s.x v0, a5
+; RV32-NEXT: vslideup.vi v12, v8, 4
+; RV32-NEXT: vslideup.vi v4, v8, 2
; RV32-NEXT: vmerge.vvm v8, v24, v8, v0
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 18
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
+; RV32-NEXT: lui a1, %hi(.LCPI27_0)
+; RV32-NEXT: addi a1, a1, %lo(.LCPI27_0)
+; RV32-NEXT: vmv.s.x v0, a2
+; RV32-NEXT: vslideup.vi v12, v24, 10, v0.t
+; RV32-NEXT: csrr a2, vlenb
+; RV32-NEXT: li a3, 72
+; RV32-NEXT: mul a2, a2, a3
+; RV32-NEXT: add a2, sp, a2
+; RV32-NEXT: addi a2, a2, 16
+; RV32-NEXT: vs4r.v v12, (a2) # vscale x 32-byte Folded Spill
+; RV32-NEXT: vle16.v v8, (a1)
+; RV32-NEXT: vslideup.vi v4, v24, 8, v0.t
; RV32-NEXT: lui a1, %hi(.LCPI27_1)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_1)
-; RV32-NEXT: vmv.s.x v0, a3
-; RV32-NEXT: vslideup.vi v4, v24, 10, v0.t
-; RV32-NEXT: vle16.v v8, (a1)
-; RV32-NEXT: vslideup.vi v12, v24, 8, v0.t
+; RV32-NEXT: vle16.v v10, (a1)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 66
+; RV32-NEXT: li a2, 48
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
+; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32-NEXT: vrgatherei16.vv v24, v16, v8
+; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: lui a1, %hi(.LCPI27_3)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_3)
-; RV32-NEXT: vle16.v v10, (a1)
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vs2r.v v10, (a1) # vscale x 16-byte Folded Spill
+; RV32-NEXT: vle16.v v2, (a1)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 26
+; RV32-NEXT: li a2, 20
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32-NEXT: vrgatherei16.vv v16, v24, v8
+; RV32-NEXT: vrgatherei16.vv v16, v24, v10
; RV32-NEXT: lui a1, %hi(.LCPI27_2)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_2)
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vle16.v v20, (a1)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 34
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: addi a1, sp, 16
-; RV32-NEXT: vl2r.v v22, (a1) # vscale x 16-byte Folded Reload
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vrgatherei16.vv v8, v24, v22
+; RV32-NEXT: vrgatherei16.vv v8, v24, v2
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 10
+; RV32-NEXT: li a2, 72
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
+; RV32-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
+; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetivli zero, 12, e32, m4, tu, ma
-; RV32-NEXT: vmv.v.v v4, v24
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 34
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs4r.v v4, (a1) # vscale x 32-byte Folded Spill
+; RV32-NEXT: vmv.v.v v12, v24
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 66
+; RV32-NEXT: li a2, 72
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vmv.v.v v12, v16
+; RV32-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
+; RV32-NEXT: vmv.v.v v4, v16
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 66
+; RV32-NEXT: li a2, 48
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
+; RV32-NEXT: vs4r.v v4, (a1) # vscale x 32-byte Folded Spill
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: slli a1, a1, 1
+; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
@@ -752,48 +725,36 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; RV32-NEXT: vle16.v v20, (a2)
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT: vle16.v v8, (a1)
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 26
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vle16.v v26, (a1)
; RV32-NEXT: lui a1, %hi(.LCPI27_7)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_7)
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vle16.v v22, (a1)
+; RV32-NEXT: vle16.v v24, (a1)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 42
+; RV32-NEXT: li a2, 40
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vrgatherei16.vv v8, v0, v20
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 6
+; RV32-NEXT: li a2, 12
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 26
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl1r.v v20, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vrgatherei16.vv v24, v12, v20
+; RV32-NEXT: vrgatherei16.vv v20, v12, v26
; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
-; RV32-NEXT: vmv.v.v v24, v8
+; RV32-NEXT: vmv.v.v v20, v8
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 50
+; RV32-NEXT: li a2, 56
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vrgatherei16.vv v8, v0, v22
+; RV32-NEXT: vrgatherei16.vv v8, v0, v24
; RV32-NEXT: lui a1, %hi(.LCPI27_6)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_6)
; RV32-NEXT: lui a2, %hi(.LCPI27_8)
@@ -803,86 +764,60 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV32-NEXT: lui a1, %hi(.LCPI27_9)
; RV32-NEXT: addi a1, a1, %lo(.LCPI27_9)
; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; RV32-NEXT: vle16.v v14, (a1)
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a3, 42
-; RV32-NEXT: mul a1, a1, a3
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs2r.v v14, (a1) # vscale x 16-byte Folded Spill
+; RV32-NEXT: vle16.v v28, (a1)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vle16.v v13, (a2)
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 50
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs1r.v v13, (a1) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vle16.v v30, (a2)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 22
+; RV32-NEXT: li a2, 28
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v4, (a1) # vscale x 32-byte Folded Reload
-; RV32-NEXT: vrgatherei16.vv v20, v4, v12
+; RV32-NEXT: vrgatherei16.vv v24, v4, v12
; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
-; RV32-NEXT: vmv.v.v v20, v8
+; RV32-NEXT: vmv.v.v v24, v8
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 58
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a1, a1, 6
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 42
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl2r.v v28, (a1) # vscale x 16-byte Folded Reload
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vrgatherei16.vv v8, v0, v28
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 18
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v4, (a1) # vscale x 32-byte Folded Reload
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 50
-; RV32-NEXT: mul a1, a1, a2
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl1r.v v3, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT: vrgatherei16.vv v12, v4, v3
+; RV32-NEXT: vrgatherei16.vv v12, v4, v30
; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma
; RV32-NEXT: vmv.v.v v12, v8
; RV32-NEXT: addi a1, a0, 320
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vse32.v v12, (a1)
; RV32-NEXT: addi a1, a0, 256
-; RV32-NEXT: vse32.v v20, (a1)
-; RV32-NEXT: addi a1, a0, 192
; RV32-NEXT: vse32.v v24, (a1)
+; RV32-NEXT: addi a1, a0, 192
+; RV32-NEXT: vse32.v v20, (a1)
; RV32-NEXT: addi a1, a0, 128
; RV32-NEXT: vse32.v v16, (a1)
; RV32-NEXT: addi a1, a0, 64
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 66
+; RV32-NEXT: li a3, 48
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 34
+; RV32-NEXT: li a2, 72
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 74
+; RV32-NEXT: li a1, 76
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 16
@@ -895,90 +830,87 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 62
+; RV64-NEXT: li a3, 68
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: sub sp, sp, a2
-; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x3e, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 62 * vlenb
+; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc4, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 68 * vlenb
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vle64.v v8, (a1)
-; RV64-NEXT: addi a5, a1, 128
+; RV64-NEXT: addi a4, a1, 128
; RV64-NEXT: lui a3, 1
; RV64-NEXT: lui a2, %hi(.LCPI27_0)
; RV64-NEXT: addi a2, a2, %lo(.LCPI27_0)
-; RV64-NEXT: lui a4, 2
-; RV64-NEXT: vle64.v v16, (a5)
-; RV64-NEXT: li a5, 1040
-; RV64-NEXT: vmv.s.x v5, a5
-; RV64-NEXT: addi a5, a3, 65
-; RV64-NEXT: vmv.s.x v0, a5
-; RV64-NEXT: lui a5, 4
-; RV64-NEXT: addi a4, a4, 130
-; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
-; RV64-NEXT: csrr a6, vlenb
-; RV64-NEXT: li a7, 22
-; RV64-NEXT: mul a6, a6, a7
-; RV64-NEXT: add a6, sp, a6
-; RV64-NEXT: addi a6, a6, 16
-; RV64-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
+; RV64-NEXT: lui a5, 2
+; RV64-NEXT: lui a6, 4
+; RV64-NEXT: vle64.v v16, (a4)
+; RV64-NEXT: addi a4, a3, 65
; RV64-NEXT: vmv.s.x v0, a4
; RV64-NEXT: lui a4, 8
-; RV64-NEXT: addi a5, a5, 260
+; RV64-NEXT: addi a5, a5, 130
+; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV64-NEXT: csrr a7, vlenb
+; RV64-NEXT: li t0, 60
+; RV64-NEXT: mul a7, a7, t0
+; RV64-NEXT: add a7, sp, a7
+; RV64-NEXT: addi a7, a7, 16
+; RV64-NEXT: vs8r.v v24, (a7) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv.s.x v0, a5
+; RV64-NEXT: li a5, 1040
+; RV64-NEXT: addi a6, a6, 260
; RV64-NEXT: addi a4, a4, 520
; RV64-NEXT: addi a3, a3, -2016
; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV64-NEXT: csrr a7, vlenb
+; RV64-NEXT: li t0, 12
+; RV64-NEXT: mul a7, a7, t0
+; RV64-NEXT: add a7, sp, a7
+; RV64-NEXT: addi a7, a7, 16
+; RV64-NEXT: vs8r.v v24, (a7) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv.s.x v0, a6
+; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
; RV64-NEXT: csrr a6, vlenb
-; RV64-NEXT: li a7, 14
-; RV64-NEXT: mul a6, a6, a7
+; RV64-NEXT: slli a6, a6, 2
; RV64-NEXT: add a6, sp, a6
; RV64-NEXT: addi a6, a6, 16
; RV64-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv.s.x v0, a5
-; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
-; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 6
-; RV64-NEXT: mul a5, a5, a6
-; RV64-NEXT: add a5, sp, a5
-; RV64-NEXT: addi a5, a5, 16
-; RV64-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
; RV64-NEXT: vmv.s.x v0, a4
+; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
+; RV64-NEXT: csrr a4, vlenb
+; RV64-NEXT: li a6, 36
+; RV64-NEXT: mul a4, a4, a6
+; RV64-NEXT: add a4, sp, a4
+; RV64-NEXT: addi a4, a4, 16
+; RV64-NEXT: vs8r.v v24, (a4) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv.s.x v0, a5
; RV64-NEXT: vle16.v v6, (a2)
; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a4, 54
+; RV64-NEXT: li a4, 44
; RV64-NEXT: mul a2, a2, a4
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv.s.x v4, a3
-; RV64-NEXT: vmv1r.v v0, v5
-; RV64-NEXT: vmerge.vvm v24, v16, v8, v0
-; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 38
-; RV64-NEXT: mul a2, a2, a3
-; RV64-NEXT: add a2, sp, a2
-; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v4
+; RV64-NEXT: vmv.s.x v0, a3
; RV64-NEXT: vmerge.vvm v8, v16, v8, v0
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 46
+; RV64-NEXT: li a3, 52
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 22
+; RV64-NEXT: li a3, 60
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vrgatherei16.vv v8, v16, v6
+; RV64-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vrgatherei16.vv v16, v8, v6
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 30
+; RV64-NEXT: li a3, 28
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
-; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64-NEXT: lui a2, %hi(.LCPI27_1)
; RV64-NEXT: addi a2, a2, %lo(.LCPI27_1)
; RV64-NEXT: lui a3, %hi(.LCPI27_2)
@@ -988,27 +920,26 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: addi a1, a1, 256
; RV64-NEXT: vle64.v v16, (a1)
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 14
+; RV64-NEXT: li a2, 12
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vrgatherei16.vv v24, v0, v8
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 22
+; RV64-NEXT: li a2, 20
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 6
-; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: slli a1, a1, 2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vrgatherei16.vv v24, v0, v10
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 14
+; RV64-NEXT: li a2, 12
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
@@ -1018,194 +949,198 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_
; RV64-NEXT: vmv4r.v v8, v16
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vslideup.vi v8, v16, 5, v0.t
-; RV64-NEXT: vmv.v.v v24, v8
; RV64-NEXT: vslidedown.vi v4, v16, 1
; RV64-NEXT: vslideup.vi v4, v16, 4, v0.t
; RV64-NEXT: li a1, 128
; RV64-NEXT: vmv.s.x v0, a1
-; RV64-NEXT: vslideup.vi v28, v16, 2
+; RV64-NEXT: vslideup.vi v12, v16, 2
; RV64-NEXT: vsetivli zero, 8, e64, m8, ta, ma
-; RV64-NEXT: vslidedown.vi v8, v16, 8
+; RV64-NEXT: vslidedown.vi v24, v16, 8
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
-; RV64-NEXT: vslideup.vi v28, v8, 5, v0.t
-; RV64-NEXT: vslideup.vi v12, v16, 1
-; RV64-NEXT: vslideup.vi v12, v8, 4, v0.t
-; RV64-NEXT: vrgather.vi v24, v8, 4, v0.t
-; RV64-NEXT: vrgather.vi v4, v8, 5, v0.t
-; RV64-NEXT: vmv.v.v v20, v4
-; RV64-NEXT: vslideup.vi v4, v8, 6
-; RV64-NEXT: vslideup.vi v4, v8, 1, v0.t
+; RV64-NEXT: vslideup.vi v12, v24, 5, v0.t
+; RV64-NEXT: vslideup.vi v20, v16, 1
+; RV64-NEXT: vslideup.vi v20, v24, 4, v0.t
+; RV64-NEXT: vmv.v.v v28, v20
+; RV64-NEXT: vrgather.vi v8, v24, 4, v0.t
+; RV64-NEXT: vrgather.vi v4, v24, 5, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 6
+; RV64-NEXT: li a2, 60
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v4, (a1) # vscale x 32-byte Folded Spill
-; RV64-NEXT: li a1, 64
-; RV64-NEXT: vmv.s.x v0, a1
-; RV64-NEXT: vmv4r.v v4, v8
-; RV64-NEXT: vslideup.vi v4, v8, 5, v0.t
+; RV64-NEXT: vslideup.vi v20, v24, 6
+; RV64-NEXT: vslideup.vi v20, v24, 1, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 1
+; RV64-NEXT: slli a1, a1, 2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v4, (a1) # vscale x 32-byte Folded Spill
+; RV64-NEXT: vs4r.v v20, (a1) # vscale x 32-byte Folded Spill
+; RV64-NEXT: li a1, 64
+; RV64-NEXT: vmv.s.x v0, a1
+; RV64-NEXT: vmv4r.v v20, v24
+; RV64-NEXT: vslideup.vi v20, v24, 5, v0.t
; RV64-NEXT: lui a1, %hi(.LCPI27_3)
; RV64-NEXT: addi a1, a1, %lo(.LCPI27_3)
; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; RV64-NEXT: vle16.v v8, (a1)
-; RV64-NEXT: addi a1, sp, 16
-; RV64-NEXT: vs2r.v v8, (a1) # vscale x 16-byte Folded Spill
+; RV64-NEXT: vle16.v v24, (a1)
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 30
+; RV64-NEXT: li a2, 28
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
-; RV64-NEXT: vmv.v.v v28, v0
+; RV64-NEXT: vmv.v.v v12, v0
+; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: li a2, 28
+; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: add a1, sp, a1
+; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 30
+; RV64-NEXT: li a2, 20
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
+; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmv.v.v v28, v0
+; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vs4r.v v28, (a1) # vscale x 32-byte Folded Spill
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 22
+; RV64-NEXT: li a2, 12
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmv.v.v v12, v0
+; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
+; RV64-NEXT: vmv.v.v v8, v0
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 22
+; RV64-NEXT: li a2, 20
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
+; RV64-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 14
+; RV64-NEXT: li a2, 36
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
-; RV64-NEXT: vmv.v.v v24, v8
+; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; RV64-NEXT: vrgatherei16.vv v0, v8, v24
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 14
+; RV64-NEXT: li a2, 60
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs4r.v v24, (a1) # vscale x 32-byte Folded Spill
+; RV64-NEXT: vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
+; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
+; RV64-NEXT: vmv.v.v v8, v0
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 54
+; RV64-NEXT: li a2, 60
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: addi a1, sp, 16
-; RV64-NEXT: vl2r.v v6, (a1) # vscale x 16-byte Folded Reload
-; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vrgatherei16.vv v8, v24, v6
-; RV64-NEXT: vmv4r.v v4, v20
-; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
-; RV64-NEXT: vmv.v.v v4, v8
+; RV64-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; RV64-NEXT: li a1, 192
; RV64-NEXT: lui a2, %hi(.LCPI27_4)
; RV64-NEXT: addi a2, a2, %lo(.LCPI27_4)
; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; RV64-NEXT: vle16.v v2, (a2)
-; RV64-NEXT: vmv.s.x v8, a1
+; RV64-NEXT: vle16.v v8, (a2)
+; RV64-NEXT: csrr a2, vlenb
+; RV64-NEXT: li a3, 12
+; RV64-NEXT: mul a2, a2, a3
+; RV64-NEXT: add a2, sp, a2
+; RV64-NEXT: addi a2, a2, 16
+; RV64-NEXT: vs2r.v v8, (a2) # vscale x 16-byte Folded Spill
+; RV64-NEXT: vmv.s.x v0, a1
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 54
+; RV64-NEXT: li a2, 36
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
+; RV64-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vrgather.vi v8, v16, 2
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 6
-; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: slli a1, a1, 2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
+; RV64-NEXT: vmerge.vvm v24, v8, v12, v0
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 54
+; RV64-NEXT: li a2, 44
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v20, v8, v12, v0
+; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 38
+; RV64-NEXT: li a2, 12
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vl2r.v v28, (a1) # vscale x 16-byte Folded Reload
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vrgatherei16.vv v8, v24, v2
+; RV64-NEXT: vrgatherei16.vv v8, v0, v28
; RV64-NEXT: lui a1, %hi(.LCPI27_5)
; RV64-NEXT: addi a1, a1, %lo(.LCPI27_5)
-; RV64-NEXT: vle16.v v2, (a1)
+; RV64-NEXT: vle16.v v28, (a1)
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
-; RV64-NEXT: vmv.v.v v20, v8
+; RV64-NEXT: vmv.v.v v24, v8
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vrgather.vi v8, v16, 3
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: slli a1, a1, 1
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl4r.v v12, (a1) # vscale x 32-byte Folded Reload
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 54
+; RV64-NEXT: li a2, 36
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v16, v8, v12, v0
+; RV64-NEXT: vmerge.vvm v16, v8, v20, v0
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 46
+; RV64-NEXT: li a2, 52
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
-; RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vrgatherei16.vv v8, v24, v2
+; RV64-NEXT: vrgatherei16.vv v8, v0, v28
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
; RV64-NEXT: vmv.v.v v16, v8
; RV64-NEXT: addi a1, a0, 320
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vse64.v v16, (a1)
; RV64-NEXT: addi a1, a0, 256
-; RV64-NEXT: vse64.v v20, (a1)
+; RV64-NEXT: vse64.v v24, (a1)
; RV64-NEXT: addi a1, a0, 192
-; RV64-NEXT: vse64.v v4, (a1)
-; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 14
+; RV64-NEXT: li a3, 60
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
; RV64-NEXT: vse64.v v8, (a1)
-; RV64-NEXT: addi a1, a0, 64
+; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 22
+; RV64-NEXT: li a3, 20
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
; RV64-NEXT: vse64.v v8, (a1)
+; RV64-NEXT: addi a1, a0, 64
+; RV64-NEXT: addi a2, sp, 16
+; RV64-NEXT: vl4r.v v8, (a2) # vscale x 32-byte Folded Reload
+; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 30
+; RV64-NEXT: li a2, 28
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v8, (a1) # vscale x 32-byte Folded Reload
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 62
+; RV64-NEXT: li a1, 68
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
index 58826b4f67bf1..6887f11fe38c7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
@@ -112,9 +112,9 @@ define float @vpreduce_fadd_v64f32(float %s, <64 x float> %v, <64 x i1> %m, i32
; CHECK-LABEL: vpreduce_fadd_v64f32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 32
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v25, v0, 4
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB8_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 32
@@ -140,9 +140,9 @@ define float @vpreduce_ord_fadd_v64f32(float %s, <64 x float> %v, <64 x i1> %m,
; CHECK-LABEL: vpreduce_ord_fadd_v64f32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 32
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v25, v0, 4
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB9_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
index 52be38834661d..0401fe04556a9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
@@ -1891,58 +1891,53 @@ define float @vreduce_fminimum_v128f32(ptr %x) {
; CHECK-NEXT: addi a1, a0, 384
; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: addi a1, a0, 256
-; CHECK-NEXT: vle32.v v24, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v24, v16, v16
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v7, v8, v8
; CHECK-NEXT: vle32.v v24, (a1)
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v24, v24
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmerge.vvm v24, v24, v8, v0
+; CHECK-NEXT: vmerge.vvm v24, v8, v24, v0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
@@ -2307,26 +2302,22 @@ define double @vreduce_fminimum_v64f64(ptr %x) {
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmfeq.vv v24, v16, v16
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
-; RV32-NEXT: vmfeq.vv v7, v8, v8
+; RV32-NEXT: vmfeq.vv v0, v16, v16
; RV32-NEXT: vle64.v v24, (a1)
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vmerge.vvm v16, v16, v8, v0
+; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmfeq.vv v0, v8, v8
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
@@ -2337,21 +2328,20 @@ define double @vreduce_fminimum_v64f64(ptr %x) {
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmfeq.vv v0, v8, v8
-; RV32-NEXT: vmfeq.vv v7, v24, v24
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmfeq.vv v0, v16, v16
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmerge.vvm v16, v16, v24, v0
+; RV32-NEXT: vmfeq.vv v0, v24, v24
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vmerge.vvm v24, v24, v8, v0
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -2417,26 +2407,22 @@ define double @vreduce_fminimum_v64f64(ptr %x) {
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmfeq.vv v24, v16, v16
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
-; RV64-NEXT: vmfeq.vv v7, v8, v8
+; RV64-NEXT: vmfeq.vv v0, v16, v16
; RV64-NEXT: vle64.v v24, (a1)
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vmerge.vvm v16, v16, v8, v0
+; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmfeq.vv v0, v8, v8
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vmerge.vvm v8, v8, v16, v0
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
@@ -2447,21 +2433,20 @@ define double @vreduce_fminimum_v64f64(ptr %x) {
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmfeq.vv v0, v8, v8
-; RV64-NEXT: vmfeq.vv v7, v24, v24
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmfeq.vv v0, v16, v16
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmerge.vvm v16, v16, v24, v0
+; RV64-NEXT: vmfeq.vv v0, v24, v24
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vmerge.vvm v24, v24, v8, v0
; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -2806,58 +2791,53 @@ define float @vreduce_fmaximum_v128f32(ptr %x) {
; CHECK-NEXT: addi a1, a0, 384
; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: addi a1, a0, 256
-; CHECK-NEXT: vle32.v v24, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v24, v16, v16
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v7, v8, v8
; CHECK-NEXT: vle32.v v24, (a1)
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
+; CHECK-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmfeq.vv v0, v8, v8
-; CHECK-NEXT: vmfeq.vv v7, v24, v24
+; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: vmerge.vvm v24, v24, v8, v0
+; CHECK-NEXT: vmerge.vvm v24, v8, v24, v0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
@@ -3222,26 +3202,22 @@ define double @vreduce_fmaximum_v64f64(ptr %x) {
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmfeq.vv v24, v16, v16
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
-; RV32-NEXT: vmfeq.vv v7, v8, v8
+; RV32-NEXT: vmfeq.vv v0, v16, v16
; RV32-NEXT: vle64.v v24, (a1)
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: addi a0, sp, 16
-; RV32-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV32-NEXT: vmerge.vvm v16, v16, v8, v0
+; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmfeq.vv v0, v8, v8
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vmerge.vvm v8, v8, v16, v0
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
@@ -3252,21 +3228,20 @@ define double @vreduce_fmaximum_v64f64(ptr %x) {
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmfeq.vv v0, v8, v8
-; RV32-NEXT: vmfeq.vv v7, v24, v24
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmfeq.vv v0, v16, v16
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
-; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV32-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vmerge.vvm v16, v16, v24, v0
+; RV32-NEXT: vmfeq.vv v0, v24, v24
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: vmerge.vvm v24, v24, v8, v0
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -3332,26 +3307,22 @@ define double @vreduce_fmaximum_v64f64(ptr %x) {
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmfeq.vv v24, v16, v16
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vs1r.v v24, (a0) # vscale x 8-byte Folded Spill
-; RV64-NEXT: vmfeq.vv v7, v8, v8
+; RV64-NEXT: vmfeq.vv v0, v16, v16
; RV64-NEXT: vle64.v v24, (a1)
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: addi a0, sp, 16
-; RV64-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; RV64-NEXT: vmerge.vvm v16, v16, v8, v0
+; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmfeq.vv v0, v8, v8
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vmerge.vvm v8, v8, v16, v0
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
@@ -3362,21 +3333,20 @@ define double @vreduce_fmaximum_v64f64(ptr %x) {
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmfeq.vv v0, v8, v8
-; RV64-NEXT: vmfeq.vv v7, v24, v24
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmfeq.vv v0, v16, v16
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
-; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmerge.vvm v16, v8, v24, v0
+; RV64-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vmerge.vvm v16, v16, v24, v0
+; RV64-NEXT: vmfeq.vv v0, v24, v24
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: add a0, sp, a0
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: vmerge.vvm v24, v24, v8, v0
; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
index 4b5d581e7b668..564c4fb40a70b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
@@ -645,18 +645,18 @@ define signext i32 @vpreduce_xor_v64i32(i32 signext %s, <64 x i32> %v, <64 x i1>
; CHECK-LABEL: vpreduce_xor_v64i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v25, v0, 4
-; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bltu a1, a3, .LBB49_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: .LBB49_2:
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vmv.s.x v24, a0
-; CHECK-NEXT: addi a0, a1, -32
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; CHECK-NEXT: vredxor.vs v24, v8, v24, v0.t
+; CHECK-NEXT: addi a0, a1, -32
; CHECK-NEXT: sltu a1, a1, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
index e527169a07d96..3e88d19fb95e7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll
@@ -213,16 +213,16 @@ define zeroext i1 @vpreduce_and_v256i1(i1 zeroext %s, <256 x i1> %v, <256 x i1>
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vmnot.m v9, v11
; CHECK-NEXT: vcpop.m a2, v9, v0.t
-; CHECK-NEXT: seqz a2, a2
-; CHECK-NEXT: and a0, a2, a0
-; CHECK-NEXT: addi a2, a1, -128
-; CHECK-NEXT: sltu a1, a1, a2
+; CHECK-NEXT: addi a3, a1, -128
+; CHECK-NEXT: sltu a1, a1, a3
; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a1, a1, a2
+; CHECK-NEXT: and a1, a1, a3
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmnot.m v8, v8
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vcpop.m a1, v8, v0.t
+; CHECK-NEXT: seqz a2, a2
+; CHECK-NEXT: and a0, a2, a0
; CHECK-NEXT: seqz a1, a1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
index dcb2fde553d58..9af900ce005e5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
@@ -31,12 +31,12 @@ define <2 x half> @vp_round_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl)
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -115,12 +115,12 @@ define <4 x half> @vp_round_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl)
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
index f398cb306559b..656a62a693da8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
@@ -31,12 +31,12 @@ define <2 x half> @vp_roundeven_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -115,12 +115,12 @@ define <4 x half> @vp_roundeven_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
index bfbf6c8371a4e..0a06067a65782 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
@@ -31,12 +31,12 @@ define <2 x half> @vp_roundtozero_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -115,12 +115,12 @@ define <4 x half> @vp_roundtozero_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
index f9b97da6d02aa..f76c7fcb628b5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
@@ -596,15 +596,15 @@ define <256 x i1> @icmp_eq_vv_v256i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1>
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: li a1, 128
; CHECK-NEXT: addi a4, a0, 128
+; CHECK-NEXT: addi a5, a3, -128
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vlm.v v0, (a2)
-; CHECK-NEXT: addi a2, a3, -128
; CHECK-NEXT: vle8.v v24, (a4)
-; CHECK-NEXT: sltu a4, a3, a2
+; CHECK-NEXT: sltu a4, a3, a5
+; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a2, a4, a2
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-NEXT: and a4, a4, a5
+; CHECK-NEXT: vsetvli zero, a4, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vv v7, v16, v24, v0.t
; CHECK-NEXT: bltu a3, a1, .LBB51_2
; CHECK-NEXT: # %bb.1:
@@ -634,12 +634,12 @@ define <256 x i1> @icmp_eq_vx_v256i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 z
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
+; CHECK-NEXT: addi a4, a2, -128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: addi a1, a2, -128
-; CHECK-NEXT: sltu a4, a2, a1
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a1, a4, a1
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB52_2
@@ -664,12 +664,12 @@ define <256 x i1> @icmp_eq_vx_swap_v256i8(<256 x i8> %va, i8 %b, <256 x i1> %m,
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
+; CHECK-NEXT: addi a4, a2, -128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: addi a1, a2, -128
-; CHECK-NEXT: sltu a4, a2, a1
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a1, a4, a1
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB53_2
@@ -1289,9 +1289,9 @@ define <64 x i1> @icmp_eq_vx_v64i32(<64 x i32> %va, i32 %b, <64 x i1> %m, i32 ze
; CHECK-LABEL: icmp_eq_vx_v64i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v25, v0, 4
-; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bltu a1, a3, .LBB100_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 32
@@ -1319,9 +1319,9 @@ define <64 x i1> @icmp_eq_vx_swap_v64i32(<64 x i32> %va, i32 %b, <64 x i1> %m, i
; CHECK-LABEL: icmp_eq_vx_swap_v64i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 32
+; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v25, v0, 4
-; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bltu a1, a3, .LBB101_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
index b03415e1a8550..6dc54bce9aaa0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll
@@ -138,9 +138,9 @@ define <32 x i64> @vsext_v32i64_v32i32(<32 x i32> %va, <32 x i1> %m, i32 zeroext
; CHECK-LABEL: vsext_v32i64_v32i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB12_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
index 03bde17b1230a..33583a4b5beca 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
@@ -145,12 +145,11 @@ define void @deinterleave6_0_i8(ptr %in, ptr %out) {
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.v.i v0, 2
-; CHECK-NEXT: vmv.v.i v10, 4
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 8
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 5, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv.v.i v0, 4
; CHECK-NEXT: vrgather.vi v8, v9, 4, v0.t
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
@@ -190,12 +189,11 @@ define void @deinterleave7_0_i8(ptr %in, ptr %out) {
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.v.i v0, 2
-; CHECK-NEXT: vmv.v.i v10, 4
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 8
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v8, v8, 6, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmv.v.i v0, 4
; CHECK-NEXT: vrgather.vi v8, v9, 6, v0.t
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
index 1a018ecb190e1..cb0cc43389b6b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
@@ -1612,22 +1612,21 @@ define <16 x i64> @unzip2a_dual_v16i64_exact(<16 x i64> %a, <16 x i64> %b) vscal
; V-NEXT: vsetivli zero, 4, e64, m1, ta, mu
; V-NEXT: vslideup.vi v16, v15, 2
; V-NEXT: vmv.v.i v0, 8
-; V-NEXT: vmv.v.i v18, 2
; V-NEXT: vslideup.vi v17, v11, 2
; V-NEXT: vslideup.vi v16, v15, 1, v0.t
-; V-NEXT: vmv.v.v v19, v0
-; V-NEXT: vmv.v.v v0, v18
+; V-NEXT: vmv.v.v v15, v0
+; V-NEXT: vmv.v.i v0, 2
; V-NEXT: vslidedown.vi v14, v14, 1, v0.t
-; V-NEXT: vmv.v.v v15, v18
-; V-NEXT: vmv.v.v v0, v19
+; V-NEXT: vmv.v.v v18, v0
+; V-NEXT: vmv.v.v v0, v15
; V-NEXT: vslideup.vi v17, v11, 1, v0.t
-; V-NEXT: vmv.v.v v20, v19
+; V-NEXT: vmv.v.v v11, v15
; V-NEXT: vmv.v.v v0, v18
; V-NEXT: vslidedown.vi v10, v10, 1, v0.t
; V-NEXT: vmv.v.v v19, v18
; V-NEXT: vslideup.vi v15, v13, 2
; V-NEXT: vslideup.vi v18, v9, 2
-; V-NEXT: vmv.v.v v0, v20
+; V-NEXT: vmv.v.v v0, v11
; V-NEXT: vslideup.vi v15, v13, 1, v0.t
; V-NEXT: vslideup.vi v18, v9, 1, v0.t
; V-NEXT: vmv.v.i v0, 12
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
index afa8f2fda2ed4..feec2470461de 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll
@@ -363,9 +363,9 @@ define <32 x double> @vsitofp_v32f64_v32i64(<32 x i64> %va, <32 x i1> %m, i32 ze
; CHECK-LABEL: vsitofp_v32f64_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB25_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
index f44f90085eabd..95f110f0e1a2c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
@@ -493,17 +493,16 @@ define <32 x double> @strided_vpload_v32f64(ptr %ptr, i32 signext %stride, <32 x
; CHECK-NEXT: .LBB45_2:
; CHECK-NEXT: mul a4, a3, a1
; CHECK-NEXT: addi a5, a2, -16
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v8, v0, 2
-; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: add a4, a0, a4
; CHECK-NEXT: sltu a2, a2, a5
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a5
-; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v8, v0
+; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vlse64.v v16, (a4), a1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t
; CHECK-NEXT: ret
@@ -539,8 +538,6 @@ define <32 x double> @strided_vpload_v32f64_allones_mask(ptr %ptr, i32 signext %
define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask, i32 zeroext %evl) {
; CHECK-RV32-LABEL: strided_load_v33f64:
; CHECK-RV32: # %bb.0:
-; CHECK-RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-RV32-NEXT: vmv1r.v v16, v0
; CHECK-RV32-NEXT: li a5, 32
; CHECK-RV32-NEXT: mv a3, a4
; CHECK-RV32-NEXT: bltu a4, a5, .LBB47_2
@@ -559,7 +556,8 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
; CHECK-RV32-NEXT: li a7, 16
; CHECK-RV32-NEXT: .LBB47_4:
; CHECK-RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v0, v16, 4
+; CHECK-RV32-NEXT: vmv1r.v v16, v0
+; CHECK-RV32-NEXT: vslidedown.vi v0, v0, 4
; CHECK-RV32-NEXT: vsetvli zero, a7, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v8, (a6), a2, v0.t
; CHECK-RV32-NEXT: addi a6, a3, -16
@@ -572,12 +570,11 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
; CHECK-RV32-NEXT: .LBB47_6:
; CHECK-RV32-NEXT: mul a5, a4, a2
; CHECK-RV32-NEXT: vmv1r.v v0, v16
-; CHECK-RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-RV32-NEXT: vslidedown.vi v9, v16, 2
; CHECK-RV32-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v16, (a1), a2, v0.t
+; CHECK-RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-RV32-NEXT: vslidedown.vi v0, v0, 2
; CHECK-RV32-NEXT: add a1, a1, a5
-; CHECK-RV32-NEXT: vmv1r.v v0, v9
; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v24, (a1), a2, v0.t
; CHECK-RV32-NEXT: addi a1, a0, 128
@@ -591,8 +588,6 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
;
; CHECK-RV64-LABEL: strided_load_v33f64:
; CHECK-RV64: # %bb.0:
-; CHECK-RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-RV64-NEXT: vmv1r.v v16, v0
; CHECK-RV64-NEXT: li a5, 32
; CHECK-RV64-NEXT: mv a4, a3
; CHECK-RV64-NEXT: bltu a3, a5, .LBB47_2
@@ -611,7 +606,8 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
; CHECK-RV64-NEXT: li a7, 16
; CHECK-RV64-NEXT: .LBB47_4:
; CHECK-RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v0, v16, 4
+; CHECK-RV64-NEXT: vmv1r.v v16, v0
+; CHECK-RV64-NEXT: vslidedown.vi v0, v0, 4
; CHECK-RV64-NEXT: vsetvli zero, a7, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v8, (a6), a2, v0.t
; CHECK-RV64-NEXT: addi a6, a4, -16
@@ -624,12 +620,11 @@ define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask
; CHECK-RV64-NEXT: .LBB47_6:
; CHECK-RV64-NEXT: mul a5, a3, a2
; CHECK-RV64-NEXT: vmv1r.v v0, v16
-; CHECK-RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-RV64-NEXT: vslidedown.vi v9, v16, 2
; CHECK-RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v16, (a1), a2, v0.t
+; CHECK-RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-RV64-NEXT: vslidedown.vi v0, v0, 2
; CHECK-RV64-NEXT: add a1, a1, a5
-; CHECK-RV64-NEXT: vmv1r.v v0, v9
; CHECK-RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v24, (a1), a2, v0.t
; CHECK-RV64-NEXT: addi a1, a0, 128
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
index 20ff862320466..32ace86a0d1fc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll
@@ -48,8 +48,8 @@ define <128 x i7> @vtrunc_v128i7_v128i16(<128 x i16> %a, <128 x i1> %m, i32 zero
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: li a1, 64
-; CHECK-NEXT: vslidedown.vi v12, v0, 8
; CHECK-NEXT: mv a2, a0
+; CHECK-NEXT: vslidedown.vi v12, v0, 8
; CHECK-NEXT: bltu a0, a1, .LBB4_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 64
@@ -207,24 +207,21 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: sw s0, 28(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset s0, -4
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 74
+; RV32-NEXT: li a3, 73
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: sub sp, sp, a2
-; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0xca, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 74 * vlenb
+; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0xc9, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 73 * vlenb
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: slli a3, a2, 5
-; RV32-NEXT: add a2, a3, a2
+; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 41
+; RV32-NEXT: li a3, 40
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; RV32-NEXT: vslidedown.vi v8, v0, 8
; RV32-NEXT: addi a3, a7, -64
; RV32-NEXT: li a2, 16
; RV32-NEXT: sltu a4, a7, a3
@@ -234,186 +231,177 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: sltu a5, a4, a3
; RV32-NEXT: addi a5, a5, -1
; RV32-NEXT: and a3, a5, a3
-; RV32-NEXT: addi t0, a3, -16
+; RV32-NEXT: addi a6, a3, -16
; RV32-NEXT: mv a5, a3
-; RV32-NEXT: csrr a6, vlenb
-; RV32-NEXT: li t1, 49
-; RV32-NEXT: mul a6, a6, t1
-; RV32-NEXT: add a6, sp, a6
-; RV32-NEXT: addi a6, a6, 16
-; RV32-NEXT: vs1r.v v0, (a6) # vscale x 8-byte Folded Spill
+; RV32-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; RV32-NEXT: vslidedown.vi v8, v0, 8
+; RV32-NEXT: csrr t0, vlenb
+; RV32-NEXT: li t1, 48
+; RV32-NEXT: mul t0, t0, t1
+; RV32-NEXT: add t0, sp, t0
+; RV32-NEXT: addi t0, t0, 16
+; RV32-NEXT: vs1r.v v0, (t0) # vscale x 8-byte Folded Spill
; RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; RV32-NEXT: vslidedown.vi v9, v0, 4
-; RV32-NEXT: vmv1r.v v28, v8
-; RV32-NEXT: vslidedown.vi v8, v8, 4
+; RV32-NEXT: vmv1r.v v13, v8
+; RV32-NEXT: vslidedown.vi v10, v8, 4
; RV32-NEXT: bltu a3, a2, .LBB16_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a5, 16
; RV32-NEXT: .LBB16_2:
; RV32-NEXT: li t2, 64
-; RV32-NEXT: sltu t1, a3, t0
-; RV32-NEXT: mv a6, a7
+; RV32-NEXT: sltu t1, a3, a6
+; RV32-NEXT: mv t0, a7
; RV32-NEXT: bltu a7, t2, .LBB16_4
; RV32-NEXT: # %bb.3:
-; RV32-NEXT: li a6, 64
+; RV32-NEXT: li t0, 64
; RV32-NEXT: .LBB16_4:
-; RV32-NEXT: addi t2, a1, 128
-; RV32-NEXT: csrr a3, vlenb
-; RV32-NEXT: li t3, 24
-; RV32-NEXT: mul a3, a3, t3
-; RV32-NEXT: add a3, sp, a3
-; RV32-NEXT: addi a3, a3, 16
-; RV32-NEXT: vs1r.v v9, (a3) # vscale x 8-byte Folded Spill
+; RV32-NEXT: addi t3, a1, 128
+; RV32-NEXT: vmv1r.v v12, v9
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v31, v9, 2
+; RV32-NEXT: vslidedown.vi v14, v9, 2
; RV32-NEXT: addi s0, a1, 512
; RV32-NEXT: addi t6, a1, 640
-; RV32-NEXT: vmv1r.v v30, v8
-; RV32-NEXT: vslidedown.vi v0, v8, 2
; RV32-NEXT: addi t1, t1, -1
-; RV32-NEXT: addi t3, a1, 384
+; RV32-NEXT: addi t2, a1, 384
; RV32-NEXT: li a3, 32
-; RV32-NEXT: addi t4, a6, -32
-; RV32-NEXT: sltu a6, a6, t4
-; RV32-NEXT: addi a6, a6, -1
-; RV32-NEXT: and a6, a6, t4
-; RV32-NEXT: addi t4, a6, -16
-; RV32-NEXT: sltu t5, a6, t4
+; RV32-NEXT: addi t4, t0, -32
+; RV32-NEXT: sltu t0, t0, t4
+; RV32-NEXT: addi t0, t0, -1
+; RV32-NEXT: and t0, t0, t4
+; RV32-NEXT: addi t4, t0, -16
+; RV32-NEXT: sltu t5, t0, t4
; RV32-NEXT: addi t5, t5, -1
-; RV32-NEXT: vslidedown.vi v29, v28, 2
-; RV32-NEXT: bltu a6, a2, .LBB16_6
+; RV32-NEXT: vslidedown.vi v0, v10, 2
+; RV32-NEXT: vslidedown.vi v15, v13, 2
+; RV32-NEXT: bltu t0, a2, .LBB16_6
; RV32-NEXT: # %bb.5:
-; RV32-NEXT: li a6, 16
+; RV32-NEXT: li t0, 16
; RV32-NEXT: .LBB16_6:
+; RV32-NEXT: vmv1r.v v7, v10
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vle64.v v8, (s0)
+; RV32-NEXT: vle64.v v16, (s0)
; RV32-NEXT: csrr s0, vlenb
; RV32-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
-; RV32-NEXT: li a0, 58
+; RV32-NEXT: li a0, 57
; RV32-NEXT: mul s0, s0, a0
; RV32-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
; RV32-NEXT: add s0, sp, s0
; RV32-NEXT: addi s0, s0, 16
-; RV32-NEXT: vs8r.v v8, (s0) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vle64.v v16, (t6)
-; RV32-NEXT: vle64.v v8, (t2)
-; RV32-NEXT: csrr t2, vlenb
-; RV32-NEXT: slli t2, t2, 3
-; RV32-NEXT: add t2, sp, t2
-; RV32-NEXT: addi t2, t2, 16
-; RV32-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vle64.v v8, (a1)
+; RV32-NEXT: vs8r.v v16, (s0) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vle64.v v24, (t6)
+; RV32-NEXT: vle64.v v16, (t3)
+; RV32-NEXT: csrr t3, vlenb
+; RV32-NEXT: slli t3, t3, 4
+; RV32-NEXT: add t3, sp, t3
+; RV32-NEXT: addi t3, t3, 16
+; RV32-NEXT: vs8r.v v16, (t3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vle64.v v16, (a1)
+; RV32-NEXT: csrr t3, vlenb
+; RV32-NEXT: slli t3, t3, 3
+; RV32-NEXT: add t3, sp, t3
+; RV32-NEXT: addi t3, t3, 16
+; RV32-NEXT: vs8r.v v16, (t3) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vle64.v v16, (t2)
; RV32-NEXT: csrr t2, vlenb
-; RV32-NEXT: li t6, 50
-; RV32-NEXT: mul t2, t2, t6
-; RV32-NEXT: add t2, sp, t2
-; RV32-NEXT: addi t2, t2, 16
-; RV32-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vle64.v v8, (t3)
-; RV32-NEXT: csrr t2, vlenb
-; RV32-NEXT: slli t2, t2, 4
+; RV32-NEXT: li t3, 49
+; RV32-NEXT: mul t2, t2, t3
; RV32-NEXT: add t2, sp, t2
; RV32-NEXT: addi t2, t2, 16
-; RV32-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: and t2, t1, t0
+; RV32-NEXT: vs8r.v v16, (t2) # vscale x 64-byte Folded Spill
+; RV32-NEXT: and t2, t1, a6
; RV32-NEXT: and t1, t5, t4
; RV32-NEXT: addi a1, a1, 256
-; RV32-NEXT: mv t0, a4
+; RV32-NEXT: mv a6, a4
; RV32-NEXT: bltu a4, a3, .LBB16_8
; RV32-NEXT: # %bb.7:
-; RV32-NEXT: li t0, 32
+; RV32-NEXT: li a6, 32
; RV32-NEXT: .LBB16_8:
; RV32-NEXT: vsetvli zero, t2, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
-; RV32-NEXT: addi t2, sp, 16
-; RV32-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v30
+; RV32-NEXT: vnsrl.wi v8, v24, 0, v0.t
+; RV32-NEXT: vmv1r.v v0, v7
; RV32-NEXT: csrr t2, vlenb
-; RV32-NEXT: li t3, 58
+; RV32-NEXT: li t3, 57
; RV32-NEXT: mul t2, t2, t3
; RV32-NEXT: add t2, sp, t2
; RV32-NEXT: addi t2, t2, 16
; RV32-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a5, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; RV32-NEXT: vnsrl.wi v24, v16, 0, v0.t
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li t2, 66
-; RV32-NEXT: mul a5, a5, t2
+; RV32-NEXT: slli t2, a5, 6
+; RV32-NEXT: add a5, t2, a5
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v31
+; RV32-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v14
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: slli a5, a5, 3
+; RV32-NEXT: slli a5, a5, 4
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, t1, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; RV32-NEXT: vnsrl.wi v24, v16, 0, v0.t
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li t1, 25
+; RV32-NEXT: li t1, 24
; RV32-NEXT: mul a5, a5, t1
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; RV32-NEXT: addi a5, t0, -16
-; RV32-NEXT: sltu t0, t0, a5
-; RV32-NEXT: addi t0, t0, -1
-; RV32-NEXT: and a5, t0, a5
+; RV32-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: csrr a5, vlenb
+; RV32-NEXT: slli a5, a5, 3
+; RV32-NEXT: add a5, sp, a5
+; RV32-NEXT: addi a5, a5, 16
+; RV32-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, t0, e32, m4, ta, ma
+; RV32-NEXT: vnsrl.wi v16, v24, 0, v0.t
+; RV32-NEXT: csrr a5, vlenb
+; RV32-NEXT: li t0, 57
+; RV32-NEXT: mul a5, a5, t0
+; RV32-NEXT: add a5, sp, a5
+; RV32-NEXT: addi a5, a5, 16
+; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; RV32-NEXT: addi a5, a6, -16
+; RV32-NEXT: sltu a6, a6, a5
+; RV32-NEXT: addi a6, a6, -1
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV32-NEXT: vle64.v v8, (a1)
+; RV32-NEXT: vle64.v v16, (a1)
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li t0, 50
-; RV32-NEXT: mul a1, a1, t0
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li t0, 24
-; RV32-NEXT: mul a1, a1, t0
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a6, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
-; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a6, 58
-; RV32-NEXT: mul a1, a1, a6
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV32-NEXT: csrr a1, vlenb
+; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV32-NEXT: and a1, a6, a5
+; RV32-NEXT: vmv1r.v v0, v15
+; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: li a6, 49
-; RV32-NEXT: mul a1, a1, a6
-; RV32-NEXT: add a1, sp, a1
-; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl1r.v v8, (a1) # vscale x 8-byte Folded Reload
-; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT: vslidedown.vi v8, v8, 2
+; RV32-NEXT: mul a5, a5, a6
+; RV32-NEXT: add a5, sp, a5
+; RV32-NEXT: addi a5, a5, 16
+; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV32-NEXT: vnsrl.wi v24, v16, 0, v0.t
+; RV32-NEXT: addi a1, sp, 16
+; RV32-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a6, 24
-; RV32-NEXT: mul a1, a1, a6
+; RV32-NEXT: li a5, 48
+; RV32-NEXT: mul a1, a1, a5
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
-; RV32-NEXT: vmv1r.v v0, v29
+; RV32-NEXT: vl1r.v v12, (a1) # vscale x 8-byte Folded Reload
+; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV32-NEXT: vslidedown.vi v12, v12, 2
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
-; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vsetvli zero, a5, e32, m4, ta, ma
-; RV32-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; RV32-NEXT: vs1r.v v12, (a1) # vscale x 8-byte Folded Spill
; RV32-NEXT: bltu a4, a2, .LBB16_10
; RV32-NEXT: # %bb.9:
; RV32-NEXT: li a4, 16
; RV32-NEXT: .LBB16_10:
-; RV32-NEXT: vmv1r.v v0, v28
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
@@ -422,7 +410,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: vsetvli zero, a4, e32, m4, ta, ma
; RV32-NEXT: vnsrl.wi v16, v24, 0, v0.t
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a4, 50
+; RV32-NEXT: li a4, 49
; RV32-NEXT: mul a1, a1, a4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
@@ -432,68 +420,65 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: # %bb.11:
; RV32-NEXT: li a1, 32
; RV32-NEXT: .LBB16_12:
-; RV32-NEXT: addi a4, sp, 16
-; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vmv4r.v v24, v16
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: li a5, 25
+; RV32-NEXT: li a5, 24
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
+; RV32-NEXT: addi a4, sp, 16
+; RV32-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: li a5, 66
-; RV32-NEXT: mul a4, a4, a5
+; RV32-NEXT: slli a5, a4, 6
+; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; RV32-NEXT: vslideup.vi v16, v24, 16
+; RV32-NEXT: vslideup.vi v16, v8, 16
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: li a5, 66
-; RV32-NEXT: mul a4, a4, a5
+; RV32-NEXT: slli a5, a4, 6
+; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV32-NEXT: addi a4, a1, -16
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 58
+; RV32-NEXT: li a6, 57
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vslideup.vi v16, v0, 16
+; RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vslideup.vi v8, v0, 16
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 58
+; RV32-NEXT: li a6, 57
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 50
+; RV32-NEXT: li a6, 49
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV32-NEXT: vslideup.vi v16, v8, 16
+; RV32-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; RV32-NEXT: vslideup.vi v8, v24, 16
; RV32-NEXT: csrr a5, vlenb
-; RV32-NEXT: li a6, 50
+; RV32-NEXT: li a6, 49
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
-; RV32-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
; RV32-NEXT: sltu a1, a1, a4
; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a4
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: slli a5, a4, 5
-; RV32-NEXT: add a4, a5, a4
+; RV32-NEXT: slli a4, a4, 5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV32-NEXT: csrr a4, vlenb
-; RV32-NEXT: li a5, 24
-; RV32-NEXT: mul a4, a4, a5
+; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
@@ -504,13 +489,13 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: li a7, 16
; RV32-NEXT: .LBB16_14:
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 49
+; RV32-NEXT: li a2, 48
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 41
+; RV32-NEXT: li a2, 40
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
@@ -522,7 +507,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: vse32.v v24, (a0)
; RV32-NEXT: addi a1, a0, 256
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 50
+; RV32-NEXT: li a3, 49
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
@@ -530,7 +515,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: addi a1, a0, 128
; RV32-NEXT: csrr a2, vlenb
-; RV32-NEXT: li a3, 58
+; RV32-NEXT: li a3, 57
; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
@@ -538,14 +523,14 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV32-NEXT: vse32.v v8, (a1)
; RV32-NEXT: addi a0, a0, 384
; RV32-NEXT: csrr a1, vlenb
-; RV32-NEXT: li a2, 66
-; RV32-NEXT: mul a1, a1, a2
+; RV32-NEXT: slli a2, a1, 6
+; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: csrr a0, vlenb
-; RV32-NEXT: li a1, 74
+; RV32-NEXT: li a1, 73
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: .cfi_def_cfa sp, 32
@@ -562,24 +547,21 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: sd s0, 40(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset s0, -8
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 74
+; RV64-NEXT: li a3, 73
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: sub sp, sp, a2
-; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0xca, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 74 * vlenb
+; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0xc9, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 73 * vlenb
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: slli a3, a2, 5
-; RV64-NEXT: add a2, a3, a2
+; RV64-NEXT: slli a2, a2, 5
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 32
; RV64-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 41
+; RV64-NEXT: li a3, 40
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 32
; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vsetivli zero, 8, e8, m1, ta, ma
-; RV64-NEXT: vslidedown.vi v8, v0, 8
; RV64-NEXT: addi a3, a7, -64
; RV64-NEXT: li a2, 16
; RV64-NEXT: sltu a4, a7, a3
@@ -589,186 +571,177 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: sltu a5, a4, a3
; RV64-NEXT: addi a5, a5, -1
; RV64-NEXT: and a3, a5, a3
-; RV64-NEXT: addi t0, a3, -16
+; RV64-NEXT: addi a6, a3, -16
; RV64-NEXT: mv a5, a3
-; RV64-NEXT: csrr a6, vlenb
-; RV64-NEXT: li t1, 49
-; RV64-NEXT: mul a6, a6, t1
-; RV64-NEXT: add a6, sp, a6
-; RV64-NEXT: addi a6, a6, 32
-; RV64-NEXT: vs1r.v v0, (a6) # vscale x 8-byte Folded Spill
+; RV64-NEXT: vsetivli zero, 8, e8, m1, ta, ma
+; RV64-NEXT: vslidedown.vi v8, v0, 8
+; RV64-NEXT: csrr t0, vlenb
+; RV64-NEXT: li t1, 48
+; RV64-NEXT: mul t0, t0, t1
+; RV64-NEXT: add t0, sp, t0
+; RV64-NEXT: addi t0, t0, 32
+; RV64-NEXT: vs1r.v v0, (t0) # vscale x 8-byte Folded Spill
; RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vi v9, v0, 4
-; RV64-NEXT: vmv1r.v v28, v8
-; RV64-NEXT: vslidedown.vi v8, v8, 4
+; RV64-NEXT: vmv1r.v v13, v8
+; RV64-NEXT: vslidedown.vi v10, v8, 4
; RV64-NEXT: bltu a3, a2, .LBB16_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a5, 16
; RV64-NEXT: .LBB16_2:
; RV64-NEXT: li t2, 64
-; RV64-NEXT: sltu t1, a3, t0
-; RV64-NEXT: mv a6, a7
+; RV64-NEXT: sltu t1, a3, a6
+; RV64-NEXT: mv t0, a7
; RV64-NEXT: bltu a7, t2, .LBB16_4
; RV64-NEXT: # %bb.3:
-; RV64-NEXT: li a6, 64
+; RV64-NEXT: li t0, 64
; RV64-NEXT: .LBB16_4:
-; RV64-NEXT: addi t2, a1, 128
-; RV64-NEXT: csrr a3, vlenb
-; RV64-NEXT: li t3, 24
-; RV64-NEXT: mul a3, a3, t3
-; RV64-NEXT: add a3, sp, a3
-; RV64-NEXT: addi a3, a3, 32
-; RV64-NEXT: vs1r.v v9, (a3) # vscale x 8-byte Folded Spill
+; RV64-NEXT: addi t3, a1, 128
+; RV64-NEXT: vmv1r.v v12, v9
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vi v31, v9, 2
+; RV64-NEXT: vslidedown.vi v14, v9, 2
; RV64-NEXT: addi s0, a1, 512
; RV64-NEXT: addi t6, a1, 640
-; RV64-NEXT: vmv1r.v v30, v8
-; RV64-NEXT: vslidedown.vi v0, v8, 2
; RV64-NEXT: addi t1, t1, -1
-; RV64-NEXT: addi t3, a1, 384
+; RV64-NEXT: addi t2, a1, 384
; RV64-NEXT: li a3, 32
-; RV64-NEXT: addi t4, a6, -32
-; RV64-NEXT: sltu a6, a6, t4
-; RV64-NEXT: addi a6, a6, -1
-; RV64-NEXT: and a6, a6, t4
-; RV64-NEXT: addi t4, a6, -16
-; RV64-NEXT: sltu t5, a6, t4
+; RV64-NEXT: addi t4, t0, -32
+; RV64-NEXT: sltu t0, t0, t4
+; RV64-NEXT: addi t0, t0, -1
+; RV64-NEXT: and t0, t0, t4
+; RV64-NEXT: addi t4, t0, -16
+; RV64-NEXT: sltu t5, t0, t4
; RV64-NEXT: addi t5, t5, -1
-; RV64-NEXT: vslidedown.vi v29, v28, 2
-; RV64-NEXT: bltu a6, a2, .LBB16_6
+; RV64-NEXT: vslidedown.vi v0, v10, 2
+; RV64-NEXT: vslidedown.vi v15, v13, 2
+; RV64-NEXT: bltu t0, a2, .LBB16_6
; RV64-NEXT: # %bb.5:
-; RV64-NEXT: li a6, 16
+; RV64-NEXT: li t0, 16
; RV64-NEXT: .LBB16_6:
+; RV64-NEXT: vmv1r.v v7, v10
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vle64.v v8, (s0)
+; RV64-NEXT: vle64.v v16, (s0)
; RV64-NEXT: csrr s0, vlenb
; RV64-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT: li a0, 58
+; RV64-NEXT: li a0, 57
; RV64-NEXT: mul s0, s0, a0
; RV64-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: add s0, sp, s0
; RV64-NEXT: addi s0, s0, 32
-; RV64-NEXT: vs8r.v v8, (s0) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vle64.v v16, (t6)
-; RV64-NEXT: vle64.v v8, (t2)
+; RV64-NEXT: vs8r.v v16, (s0) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vle64.v v24, (t6)
+; RV64-NEXT: vle64.v v16, (t3)
+; RV64-NEXT: csrr t3, vlenb
+; RV64-NEXT: slli t3, t3, 4
+; RV64-NEXT: add t3, sp, t3
+; RV64-NEXT: addi t3, t3, 32
+; RV64-NEXT: vs8r.v v16, (t3) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vle64.v v16, (a1)
+; RV64-NEXT: csrr t3, vlenb
+; RV64-NEXT: slli t3, t3, 3
+; RV64-NEXT: add t3, sp, t3
+; RV64-NEXT: addi t3, t3, 32
+; RV64-NEXT: vs8r.v v16, (t3) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vle64.v v16, (t2)
; RV64-NEXT: csrr t2, vlenb
-; RV64-NEXT: slli t2, t2, 3
-; RV64-NEXT: add t2, sp, t2
-; RV64-NEXT: addi t2, t2, 32
-; RV64-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vle64.v v8, (a1)
-; RV64-NEXT: csrr t2, vlenb
-; RV64-NEXT: li t6, 50
-; RV64-NEXT: mul t2, t2, t6
-; RV64-NEXT: add t2, sp, t2
-; RV64-NEXT: addi t2, t2, 32
-; RV64-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vle64.v v8, (t3)
-; RV64-NEXT: csrr t2, vlenb
-; RV64-NEXT: slli t2, t2, 4
+; RV64-NEXT: li t3, 49
+; RV64-NEXT: mul t2, t2, t3
; RV64-NEXT: add t2, sp, t2
; RV64-NEXT: addi t2, t2, 32
-; RV64-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: and t2, t1, t0
+; RV64-NEXT: vs8r.v v16, (t2) # vscale x 64-byte Folded Spill
+; RV64-NEXT: and t2, t1, a6
; RV64-NEXT: and t1, t5, t4
; RV64-NEXT: addi a1, a1, 256
-; RV64-NEXT: mv t0, a4
+; RV64-NEXT: mv a6, a4
; RV64-NEXT: bltu a4, a3, .LBB16_8
; RV64-NEXT: # %bb.7:
-; RV64-NEXT: li t0, 32
+; RV64-NEXT: li a6, 32
; RV64-NEXT: .LBB16_8:
; RV64-NEXT: vsetvli zero, t2, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
-; RV64-NEXT: addi t2, sp, 32
-; RV64-NEXT: vs8r.v v8, (t2) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v30
+; RV64-NEXT: vnsrl.wi v8, v24, 0, v0.t
+; RV64-NEXT: vmv1r.v v0, v7
; RV64-NEXT: csrr t2, vlenb
-; RV64-NEXT: li t3, 58
+; RV64-NEXT: li t3, 57
; RV64-NEXT: mul t2, t2, t3
; RV64-NEXT: add t2, sp, t2
; RV64-NEXT: addi t2, t2, 32
; RV64-NEXT: vl8r.v v16, (t2) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, a5, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; RV64-NEXT: vnsrl.wi v24, v16, 0, v0.t
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li t2, 66
-; RV64-NEXT: mul a5, a5, t2
+; RV64-NEXT: slli t2, a5, 6
+; RV64-NEXT: add a5, t2, a5
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v31
+; RV64-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv1r.v v0, v14
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: slli a5, a5, 3
+; RV64-NEXT: slli a5, a5, 4
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, t1, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; RV64-NEXT: vnsrl.wi v24, v16, 0, v0.t
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li t1, 25
+; RV64-NEXT: li t1, 24
; RV64-NEXT: mul a5, a5, t1
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
-; RV64-NEXT: addi a5, t0, -16
-; RV64-NEXT: sltu t0, t0, a5
-; RV64-NEXT: addi t0, t0, -1
-; RV64-NEXT: and a5, t0, a5
+; RV64-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vmv1r.v v0, v12
+; RV64-NEXT: csrr a5, vlenb
+; RV64-NEXT: slli a5, a5, 3
+; RV64-NEXT: add a5, sp, a5
+; RV64-NEXT: addi a5, a5, 32
+; RV64-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vsetvli zero, t0, e32, m4, ta, ma
+; RV64-NEXT: vnsrl.wi v16, v24, 0, v0.t
+; RV64-NEXT: csrr a5, vlenb
+; RV64-NEXT: li t0, 57
+; RV64-NEXT: mul a5, a5, t0
+; RV64-NEXT: add a5, sp, a5
+; RV64-NEXT: addi a5, a5, 32
+; RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; RV64-NEXT: addi a5, a6, -16
+; RV64-NEXT: sltu a6, a6, a5
+; RV64-NEXT: addi a6, a6, -1
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
-; RV64-NEXT: vle64.v v8, (a1)
+; RV64-NEXT: vle64.v v16, (a1)
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li t0, 50
-; RV64-NEXT: mul a1, a1, t0
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li t0, 24
-; RV64-NEXT: mul a1, a1, t0
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; RV64-NEXT: vsetvli zero, a6, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
-; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a6, 58
-; RV64-NEXT: mul a1, a1, a6
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
-; RV64-NEXT: csrr a1, vlenb
+; RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; RV64-NEXT: and a1, a6, a5
+; RV64-NEXT: vmv1r.v v0, v15
+; RV64-NEXT: csrr a5, vlenb
; RV64-NEXT: li a6, 49
-; RV64-NEXT: mul a1, a1, a6
-; RV64-NEXT: add a1, sp, a1
-; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vl1r.v v8, (a1) # vscale x 8-byte Folded Reload
-; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vi v8, v8, 2
+; RV64-NEXT: mul a5, a5, a6
+; RV64-NEXT: add a5, sp, a5
+; RV64-NEXT: addi a5, a5, 32
+; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vsetvli zero, a1, e32, m4, ta, ma
+; RV64-NEXT: vnsrl.wi v24, v16, 0, v0.t
+; RV64-NEXT: addi a1, sp, 32
+; RV64-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a6, 24
-; RV64-NEXT: mul a1, a1, a6
+; RV64-NEXT: li a5, 48
+; RV64-NEXT: mul a1, a1, a5
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
-; RV64-NEXT: vmv1r.v v0, v29
+; RV64-NEXT: vl1r.v v12, (a1) # vscale x 8-byte Folded Reload
+; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vi v12, v12, 2
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 4
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
-; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vsetvli zero, a5, e32, m4, ta, ma
-; RV64-NEXT: vnsrl.wi v8, v16, 0, v0.t
+; RV64-NEXT: vs1r.v v12, (a1) # vscale x 8-byte Folded Spill
; RV64-NEXT: bltu a4, a2, .LBB16_10
; RV64-NEXT: # %bb.9:
; RV64-NEXT: li a4, 16
; RV64-NEXT: .LBB16_10:
-; RV64-NEXT: vmv1r.v v0, v28
+; RV64-NEXT: vmv1r.v v0, v13
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, sp, a1
@@ -777,7 +750,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: vsetvli zero, a4, e32, m4, ta, ma
; RV64-NEXT: vnsrl.wi v16, v24, 0, v0.t
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a4, 50
+; RV64-NEXT: li a4, 49
; RV64-NEXT: mul a1, a1, a4
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
@@ -787,68 +760,65 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: # %bb.11:
; RV64-NEXT: li a1, 32
; RV64-NEXT: .LBB16_12:
-; RV64-NEXT: addi a4, sp, 32
-; RV64-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vmv4r.v v24, v16
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: li a5, 25
+; RV64-NEXT: li a5, 24
; RV64-NEXT: mul a4, a4, a5
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
; RV64-NEXT: vl8r.v v0, (a4) # vscale x 64-byte Folded Reload
+; RV64-NEXT: addi a4, sp, 32
+; RV64-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: li a5, 66
-; RV64-NEXT: mul a4, a4, a5
+; RV64-NEXT: slli a5, a4, 6
+; RV64-NEXT: add a4, a5, a4
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
; RV64-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
-; RV64-NEXT: vslideup.vi v16, v24, 16
+; RV64-NEXT: vslideup.vi v16, v8, 16
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: li a5, 66
-; RV64-NEXT: mul a4, a4, a5
+; RV64-NEXT: slli a5, a4, 6
+; RV64-NEXT: add a4, a5, a4
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
; RV64-NEXT: vs8r.v v16, (a4) # vscale x 64-byte Folded Spill
; RV64-NEXT: addi a4, a1, -16
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 58
+; RV64-NEXT: li a6, 57
; RV64-NEXT: mul a5, a5, a6
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vslideup.vi v16, v0, 16
+; RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vslideup.vi v8, v0, 16
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 58
+; RV64-NEXT: li a6, 57
; RV64-NEXT: mul a5, a5, a6
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 50
+; RV64-NEXT: li a6, 49
; RV64-NEXT: mul a5, a5, a6
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
-; RV64-NEXT: vslideup.vi v16, v8, 16
+; RV64-NEXT: vl8r.v v8, (a5) # vscale x 64-byte Folded Reload
+; RV64-NEXT: vslideup.vi v8, v24, 16
; RV64-NEXT: csrr a5, vlenb
-; RV64-NEXT: li a6, 50
+; RV64-NEXT: li a6, 49
; RV64-NEXT: mul a5, a5, a6
; RV64-NEXT: add a5, sp, a5
; RV64-NEXT: addi a5, a5, 32
-; RV64-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
; RV64-NEXT: sltu a1, a1, a4
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: and a1, a1, a4
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: slli a5, a4, 5
-; RV64-NEXT: add a4, a5, a4
+; RV64-NEXT: slli a4, a4, 5
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
; RV64-NEXT: vl8r.v v16, (a4) # vscale x 64-byte Folded Reload
; RV64-NEXT: csrr a4, vlenb
-; RV64-NEXT: li a5, 24
-; RV64-NEXT: mul a4, a4, a5
+; RV64-NEXT: slli a4, a4, 4
; RV64-NEXT: add a4, sp, a4
; RV64-NEXT: addi a4, a4, 32
; RV64-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
@@ -859,13 +829,13 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: li a7, 16
; RV64-NEXT: .LBB16_14:
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 49
+; RV64-NEXT: li a2, 48
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
; RV64-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 41
+; RV64-NEXT: li a2, 40
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
@@ -877,7 +847,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: vse32.v v24, (a0)
; RV64-NEXT: addi a1, a0, 256
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 50
+; RV64-NEXT: li a3, 49
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 32
@@ -885,7 +855,7 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: vse32.v v8, (a1)
; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: csrr a2, vlenb
-; RV64-NEXT: li a3, 58
+; RV64-NEXT: li a3, 57
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 32
@@ -893,14 +863,14 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
; RV64-NEXT: vse32.v v8, (a1)
; RV64-NEXT: addi a0, a0, 384
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: li a2, 66
-; RV64-NEXT: mul a1, a1, a2
+; RV64-NEXT: slli a2, a1, 6
+; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 32
; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: li a1, 74
+; RV64-NEXT: li a1, 73
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: .cfi_def_cfa sp, 48
@@ -919,8 +889,8 @@ define <32 x i32> @vtrunc_v32i32_v32i64(<32 x i64> %a, <32 x i1> %m, i32 zeroext
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: vslidedown.vi v12, v0, 2
; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: vslidedown.vi v12, v0, 2
; CHECK-NEXT: bltu a0, a2, .LBB17_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
index 3d1febe95421f..2b35ad000e6d6 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll
@@ -363,9 +363,9 @@ define <32 x double> @vuitofp_v32f64_v32i64(<32 x i64> %va, <32 x i1> %m, i32 ze
; CHECK-LABEL: vuitofp_v32f64_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB25_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
index 1fc4283795075..06a958b4df7d2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
@@ -352,12 +352,12 @@ define <256 x i8> @vadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %ev
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
+; CHECK-NEXT: addi a3, a1, -128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: addi a0, a1, -128
-; CHECK-NEXT: sltu a3, a1, a0
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a0, a3, a0
+; CHECK-NEXT: sltu a0, a1, a3
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a3
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB32_2
@@ -1319,9 +1319,9 @@ define <32 x i64> @vadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; CHECK-LABEL: vadd_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB108_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
@@ -1375,11 +1375,10 @@ define <32 x i64> @vadd_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
define <32 x i64> @vadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vadd_vx_v32i64_evl27:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
index 671da89366041..d752848664009 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll
@@ -548,9 +548,9 @@ define <32 x double> @vfabs_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; CHECK-LABEL: vfabs_vv_v32f64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB34_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
index e94c8278f511a..58d889860abd2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
@@ -524,9 +524,9 @@ define <32 x double> @vfneg_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe
; CHECK-LABEL: vfneg_vv_v32f64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB34_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
index b431d4873fa1b..ef5497c766e30 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll
@@ -352,9 +352,9 @@ define <32 x double> @vfsqrt_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zero
; CHECK-LABEL: vfsqrt_vv_v32f64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB26_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
index eafb52c1c006a..179c303fb3414 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
@@ -256,12 +256,12 @@ define <256 x i8> @vmax_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zero
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
+; CHECK-NEXT: addi a4, a2, -128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: addi a1, a2, -128
-; CHECK-NEXT: sltu a4, a2, a1
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a1, a4, a1
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmax.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB22_2
@@ -991,9 +991,9 @@ define <32 x i64> @vmax_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; CHECK-LABEL: vmax_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB74_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
index dd234cb203873..729621d7c53eb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll
@@ -255,12 +255,12 @@ define <256 x i8> @vmaxu_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zer
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
+; CHECK-NEXT: addi a4, a2, -128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: addi a1, a2, -128
-; CHECK-NEXT: sltu a4, a2, a1
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a1, a4, a1
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmaxu.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB22_2
@@ -990,9 +990,9 @@ define <32 x i64> @vmaxu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; CHECK-LABEL: vmaxu_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB74_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
index 609d1df976dde..e3a3087241e2f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll
@@ -256,12 +256,12 @@ define <256 x i8> @vmin_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zero
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
+; CHECK-NEXT: addi a4, a2, -128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: addi a1, a2, -128
-; CHECK-NEXT: sltu a4, a2, a1
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a1, a4, a1
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmin.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB22_2
@@ -991,9 +991,9 @@ define <32 x i64> @vmin_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl
; CHECK-LABEL: vmin_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB74_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
index 7c4efb760393e..f7a4c11f576ca 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll
@@ -255,12 +255,12 @@ define <256 x i8> @vminu_vx_v258i8(<256 x i8> %va, i8 %b, <256 x i1> %m, i32 zer
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a3, 128
+; CHECK-NEXT: addi a4, a2, -128
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: addi a1, a2, -128
-; CHECK-NEXT: sltu a4, a2, a1
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a1, a4, a1
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vminu.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB22_2
@@ -990,9 +990,9 @@ define <32 x i64> @vminu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; CHECK-LABEL: vminu_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB74_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
index a72ae512b2019..bcd4c530334d0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll
@@ -361,12 +361,12 @@ define <256 x i8> @vsadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %e
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
+; CHECK-NEXT: addi a3, a1, -128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: addi a0, a1, -128
-; CHECK-NEXT: sltu a3, a1, a0
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a0, a3, a0
+; CHECK-NEXT: sltu a0, a1, a3
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a3
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB32_2
@@ -1326,9 +1326,9 @@ define <32 x i64> @vsadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; CHECK-LABEL: vsadd_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB108_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
@@ -1382,11 +1382,10 @@ define <32 x i64> @vsadd_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
define <32 x i64> @vsadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vsadd_vx_v32i64_evl27:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
index 51bab9bcf2997..1c3348f8f5f13 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll
@@ -357,12 +357,12 @@ define <256 x i8> @vsaddu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
+; CHECK-NEXT: addi a3, a1, -128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: addi a0, a1, -128
-; CHECK-NEXT: sltu a3, a1, a0
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a0, a3, a0
+; CHECK-NEXT: sltu a0, a1, a3
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a3
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB32_2
@@ -1322,9 +1322,9 @@ define <32 x i64> @vsaddu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %e
; CHECK-LABEL: vsaddu_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB108_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
@@ -1378,11 +1378,10 @@ define <32 x i64> @vsaddu_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
define <32 x i64> @vsaddu_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vsaddu_vx_v32i64_evl27:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
index 2db96dca3123d..cbf4c37b70ecb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
@@ -140,8 +140,8 @@ define <256 x i8> @select_v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c, i3
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v6, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: addi a4, a1, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -152,7 +152,6 @@ define <256 x i8> @select_v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c, i3
; CHECK-NEXT: vle8.v v16, (a1)
; CHECK-NEXT: addi a4, a4, -1
; CHECK-NEXT: and a0, a4, a0
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vmerge.vvm v24, v8, v24, v0
; CHECK-NEXT: bltu a3, a2, .LBB11_2
@@ -180,17 +179,16 @@ define <256 x i8> @select_evl_v256i8(<256 x i1> %a, <256 x i8> %b, <256 x i8> %c
; CHECK-LABEL: select_evl_v256i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
-; CHECK-NEXT: vmv1r.v v7, v8
-; CHECK-NEXT: vmv1r.v v6, v0
+; CHECK-NEXT: vmv1r.v v7, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: addi a3, a1, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v24, (a3)
; CHECK-NEXT: vle8.v v8, (a1)
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v24, (a0), v0.t
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: vmv8r.v v16, v24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
index f5aba6885efcc..1cb1a838a2596 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll
@@ -374,11 +374,11 @@ define <256 x i8> @vssub_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %e
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: addi a3, a1, -128
+; CHECK-NEXT: sltu a4, a1, a3
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: sltu a0, a1, a3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a3, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t
@@ -1366,9 +1366,9 @@ define <32 x i64> @vssub_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev
; CHECK-LABEL: vssub_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB108_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
@@ -1425,12 +1425,11 @@ define <32 x i64> @vssub_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
define <32 x i64> @vssub_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vssub_vx_v32i64_evl27:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
index 1d74d1f5a6ead..199a341e12acd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll
@@ -369,11 +369,11 @@ define <256 x i8> @vssubu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: addi a3, a1, -128
+; CHECK-NEXT: sltu a4, a1, a3
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: sltu a0, a1, a3
-; CHECK-NEXT: addi a0, a0, -1
-; CHECK-NEXT: and a3, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t
@@ -1361,9 +1361,9 @@ define <32 x i64> @vssubu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %e
; CHECK-LABEL: vssubu_vx_v32i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB108_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
@@ -1420,12 +1420,11 @@ define <32 x i64> @vssubu_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) {
define <32 x i64> @vssubu_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; CHECK-LABEL: vssubu_vx_v32i64_evl27:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
+; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetivli zero, 11, e64, m8, ta, ma
; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
index 714c027fbfa0b..890a537683ba2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll
@@ -138,9 +138,9 @@ define <32 x i64> @vzext_v32i64_v32i32(<32 x i32> %va, <32 x i1> %m, i32 zeroext
; CHECK-LABEL: vzext_v32i64_v32i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 16
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v0, 2
-; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB12_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
index fe41552c4c984..333216423ad63 100644
--- a/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
@@ -17,12 +17,12 @@ define <vscale x 1 x bfloat> @vp_floor_nxv1bf16(<vscale x 1 x bfloat> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -67,12 +67,12 @@ define <vscale x 2 x bfloat> @vp_floor_nxv2bf16(<vscale x 2 x bfloat> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
@@ -410,12 +410,12 @@ define <vscale x 1 x half> @vp_floor_nxv1f16(<vscale x 1 x half> %va, <vscale x
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -494,12 +494,12 @@ define <vscale x 2 x half> @vp_floor_nxv2f16(<vscale x 2 x half> %va, <vscale x
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
index c0ddb812f833e..cebc7287c0a7e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll
@@ -169,47 +169,46 @@ define <vscale x 32 x bfloat> @vfmax_nxv32bf16_vv(<vscale x 32 x bfloat> %a, <vs
; ZVFBFMIN-NEXT: slli a0, a0, 4
; ZVFBFMIN-NEXT: sub sp, sp, a0
; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vmv8r.v v0, v16
-; ZVFBFMIN-NEXT: vmv8r.v v24, v8
+; ZVFBFMIN-NEXT: vmv8r.v v24, v16
; ZVFBFMIN-NEXT: addi a0, sp, 16
-; ZVFBFMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v0
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v24
+; ZVFBFMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFBFMIN-NEXT: vmv8r.v v0, v8
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v24
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v0
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmfeq.vv v3, v16, v16
; ZVFBFMIN-NEXT: vmerge.vvm v24, v8, v16, v0
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
; ZVFBFMIN-NEXT: addi a0, a0, 16
; ZVFBFMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFBFMIN-NEXT: vmv1r.v v0, v3
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v8, v0
+; ZVFBFMIN-NEXT: addi a0, sp, 16
+; ZVFBFMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v24, v4
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v28
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
; ZVFBFMIN-NEXT: addi a0, a0, 16
-; ZVFBFMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFBFMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFBFMIN-NEXT: vfmax.vv v8, v8, v16
+; ZVFBFMIN-NEXT: vfmax.vv v8, v8, v24
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
; ZVFBFMIN-NEXT: addi a0, a0, 16
; ZVFBFMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVFBFMIN-NEXT: addi a0, sp, 16
-; ZVFBFMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v20
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v4
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmerge.vvm v16, v8, v24, v0
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v24, v24
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v24, v8, v0
-; ZVFBFMIN-NEXT: vfmax.vv v16, v8, v16
+; ZVFBFMIN-NEXT: vmerge.vvm v24, v8, v16, v0
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v8, v0
+; ZVFBFMIN-NEXT: vfmax.vv v16, v8, v24
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
@@ -400,47 +399,46 @@ define <vscale x 32 x half> @vfmax_nxv32f16_vv(<vscale x 32 x half> %a, <vscale
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: sub sp, sp, a0
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vmv8r.v v0, v16
-; ZVFHMIN-NEXT: vmv8r.v v24, v8
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24
+; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv8r.v v0, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmfeq.vv v3, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
+; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmax.vv v8, v8, v16
+; ZVFHMIN-NEXT: vfmax.vv v8, v8, v24
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v16, v8, v24, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24
-; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v8, v0
-; ZVFHMIN-NEXT: vfmax.vv v16, v8, v16
+; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
+; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
+; ZVFHMIN-NEXT: vfmax.vv v16, v8, v24
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
index 6d3d9fecfa0d8..c5da02c3af05c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll
@@ -237,6 +237,9 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
@@ -249,21 +252,18 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a4, 25
-; CHECK-NEXT: mul a3, a3, a4
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: mul a2, a2, a4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 25
@@ -392,8 +392,7 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v8, v24, v24, v0.t
-; CHECK-NEXT: vmv1r.v v5, v8
+; CHECK-NEXT: vmfeq.vv v6, v24, v24, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2
@@ -403,12 +402,12 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v7, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vmv1r.v v5, v0
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vmv1r.v v0, v5
; CHECK-NEXT: vfmax.vv v16, v8, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
@@ -817,6 +816,9 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -829,21 +831,18 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: li a4, 25
-; ZVFHMIN-NEXT: mul a3, a3, a4
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: mul a2, a2, a4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: li a3, 25
@@ -982,8 +981,7 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v5, v8
+; ZVFHMIN-NEXT: vmfeq.vv v6, v24, v24, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
@@ -993,12 +991,12 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v7, v8, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v6, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v5
+; ZVFHMIN-NEXT: vmv1r.v v5, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vmerge.vvm v16, v24, v8, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v24, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vmv1r.v v0, v5
; ZVFHMIN-NEXT: vfmax.vv v16, v8, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
@@ -1323,16 +1321,16 @@ define <vscale x 16 x double> @vfmax_vv_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a3, a1, 3
-; CHECK-NEXT: srli a4, a1, 3
-; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a4
; CHECK-NEXT: sub a4, a2, a1
; CHECK-NEXT: add a3, a0, a3
; CHECK-NEXT: vl8re64.v v24, (a3)
; CHECK-NEXT: sltu a3, a2, a4
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a3, a3, a4
+; CHECK-NEXT: srli a4, a1, 3
+; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v5, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a4
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v7, v16, v16, v0.t
; CHECK-NEXT: vmfeq.vv v6, v24, v24, v0.t
@@ -1399,7 +1397,10 @@ define <vscale x 16 x double> @vfmax_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a3, a1, 3
@@ -1410,43 +1411,32 @@ define <vscale x 16 x double> @vfmax_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a3, a3, a4
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v8, v16, v16
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v7, v24, v24
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: vfmax.vv v8, v16, v8
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: bltu a2, a1, .LBB41_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB41_2:
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -1454,10 +1444,7 @@ define <vscale x 16 x double> @vfmax_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: vfmax.vv v8, v8, v24
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
index 02ae0b8032776..13d41efc556bb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll
@@ -169,47 +169,46 @@ define <vscale x 32 x bfloat> @vfmin_nxv32bf16_vv(<vscale x 32 x bfloat> %a, <vs
; ZVFBFMIN-NEXT: slli a0, a0, 4
; ZVFBFMIN-NEXT: sub sp, sp, a0
; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vmv8r.v v0, v16
-; ZVFBFMIN-NEXT: vmv8r.v v24, v8
+; ZVFBFMIN-NEXT: vmv8r.v v24, v16
; ZVFBFMIN-NEXT: addi a0, sp, 16
-; ZVFBFMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v0
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v24
+; ZVFBFMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFBFMIN-NEXT: vmv8r.v v0, v8
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v24
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v0
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmfeq.vv v3, v16, v16
; ZVFBFMIN-NEXT: vmerge.vvm v24, v8, v16, v0
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
; ZVFBFMIN-NEXT: addi a0, a0, 16
; ZVFBFMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFBFMIN-NEXT: vmv1r.v v0, v3
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v8, v0
+; ZVFBFMIN-NEXT: addi a0, sp, 16
+; ZVFBFMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v24, v4
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v16, v28
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
; ZVFBFMIN-NEXT: addi a0, a0, 16
-; ZVFBFMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFBFMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFBFMIN-NEXT: vfmin.vv v8, v8, v16
+; ZVFBFMIN-NEXT: vfmin.vv v8, v8, v24
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
; ZVFBFMIN-NEXT: addi a0, a0, 16
; ZVFBFMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVFBFMIN-NEXT: addi a0, sp, 16
-; ZVFBFMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v20
+; ZVFBFMIN-NEXT: vfwcvtbf16.f.f.v v8, v4
; ZVFBFMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFBFMIN-NEXT: vmerge.vvm v16, v8, v24, v0
-; ZVFBFMIN-NEXT: vmfeq.vv v0, v24, v24
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v24, v8, v0
-; ZVFBFMIN-NEXT: vfmin.vv v16, v8, v16
+; ZVFBFMIN-NEXT: vmerge.vvm v24, v8, v16, v0
+; ZVFBFMIN-NEXT: vmfeq.vv v0, v16, v16
+; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v8, v0
+; ZVFBFMIN-NEXT: vfmin.vv v16, v8, v24
; ZVFBFMIN-NEXT: csrr a0, vlenb
; ZVFBFMIN-NEXT: slli a0, a0, 3
; ZVFBFMIN-NEXT: add a0, sp, a0
@@ -400,47 +399,46 @@ define <vscale x 32 x half> @vfmin_nxv32f16_vv(<vscale x 32 x half> %a, <vscale
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: sub sp, sp, a0
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vmv8r.v v0, v16
-; ZVFHMIN-NEXT: vmv8r.v v24, v8
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24
+; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv8r.v v0, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmfeq.vv v3, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vmv1r.v v0, v3
+; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v4
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmin.vv v8, v8, v16
+; ZVFHMIN-NEXT: vfmin.vv v8, v8, v24
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
-; ZVFHMIN-NEXT: vmerge.vvm v16, v8, v24, v0
-; ZVFHMIN-NEXT: vmfeq.vv v0, v24, v24
-; ZVFHMIN-NEXT: vmerge.vvm v8, v24, v8, v0
-; ZVFHMIN-NEXT: vfmin.vv v16, v8, v16
+; ZVFHMIN-NEXT: vmerge.vvm v24, v8, v16, v0
+; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v16
+; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
+; ZVFHMIN-NEXT: vfmin.vv v16, v8, v24
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
index ab0b4fefbb786..72cd2ef1d9702 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll
@@ -237,6 +237,9 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
@@ -249,21 +252,18 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a4, 25
-; CHECK-NEXT: mul a3, a3, a4
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: mul a2, a2, a4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 25
@@ -392,8 +392,7 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v8, v24, v24, v0.t
-; CHECK-NEXT: vmv1r.v v5, v8
+; CHECK-NEXT: vmfeq.vv v6, v24, v24, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2
@@ -403,12 +402,12 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v7, v8, v8, v0.t
-; CHECK-NEXT: vmv1r.v v6, v0
-; CHECK-NEXT: vmv1r.v v0, v5
+; CHECK-NEXT: vmv1r.v v5, v0
+; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: vmerge.vvm v16, v24, v8, v0
; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
-; CHECK-NEXT: vmv1r.v v0, v6
+; CHECK-NEXT: vmv1r.v v0, v5
; CHECK-NEXT: vfmin.vv v16, v8, v16, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
@@ -817,6 +816,9 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -829,21 +831,18 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v24, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: li a4, 25
-; ZVFHMIN-NEXT: mul a3, a3, a4
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: mul a2, a2, a4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: li a3, 25
@@ -982,8 +981,7 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v8, v24, v24, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v5, v8
+; ZVFHMIN-NEXT: vmfeq.vv v6, v24, v24, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
@@ -993,12 +991,12 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vmfeq.vv v7, v8, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v6, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v5
+; ZVFHMIN-NEXT: vmv1r.v v5, v0
+; ZVFHMIN-NEXT: vmv1r.v v0, v6
; ZVFHMIN-NEXT: vmerge.vvm v16, v24, v8, v0
; ZVFHMIN-NEXT: vmv1r.v v0, v7
; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v24, v0
-; ZVFHMIN-NEXT: vmv1r.v v0, v6
+; ZVFHMIN-NEXT: vmv1r.v v0, v5
; ZVFHMIN-NEXT: vfmin.vv v16, v8, v16, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
@@ -1323,16 +1321,16 @@ define <vscale x 16 x double> @vfmin_vv_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a3, a1, 3
-; CHECK-NEXT: srli a4, a1, 3
-; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv1r.v v5, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a4
; CHECK-NEXT: sub a4, a2, a1
; CHECK-NEXT: add a3, a0, a3
; CHECK-NEXT: vl8re64.v v24, (a3)
; CHECK-NEXT: sltu a3, a2, a4
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a3, a3, a4
+; CHECK-NEXT: srli a4, a1, 3
+; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vmv1r.v v5, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a4
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v7, v16, v16, v0.t
; CHECK-NEXT: vmfeq.vv v6, v24, v24, v0.t
@@ -1399,7 +1397,10 @@ define <vscale x 16 x double> @vfmin_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
-; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: add a1, sp, a1
+; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a3, a1, 3
@@ -1410,43 +1411,32 @@ define <vscale x 16 x double> @vfmin_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a3, a3, a4
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v8, v16, v16
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vmfeq.vv v7, v24, v24
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
-; CHECK-NEXT: vmv1r.v v0, v7
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: vfmin.vv v8, v16, v8
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: bltu a2, a1, .LBB41_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB41_2:
-; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v0, v16, v16
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -1454,10 +1444,7 @@ define <vscale x 16 x double> @vfmin_vv_nxv16f64_unmasked(<vscale x 16 x double>
; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
; CHECK-NEXT: vfmin.vv v8, v8, v24
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24
diff --git a/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
index 5d00204f903fe..1a0d1431de1d0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
@@ -1506,104 +1506,69 @@ define <vscale x 16 x i64> @fshl_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a3, a1, 5
-; CHECK-NEXT: add a1, a3, a1
+; CHECK-NEXT: li a3, 26
+; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
+; CHECK-NEXT: slli a3, a1, 4
+; CHECK-NEXT: add a1, a3, a1
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: li a1, 63
; CHECK-NEXT: slli a5, a3, 3
-; CHECK-NEXT: srli a1, a3, 3
; CHECK-NEXT: sub a6, a4, a3
-; CHECK-NEXT: csrr a7, vlenb
-; CHECK-NEXT: slli a7, a7, 5
-; CHECK-NEXT: add a7, sp, a7
-; CHECK-NEXT: addi a7, a7, 16
+; CHECK-NEXT: add a7, a2, a5
+; CHECK-NEXT: vl8re64.v v8, (a7)
+; CHECK-NEXT: sltu a7, a4, a6
+; CHECK-NEXT: addi a7, a7, -1
+; CHECK-NEXT: and a6, a7, a6
+; CHECK-NEXT: srli a7, a3, 3
+; CHECK-NEXT: csrr t0, vlenb
+; CHECK-NEXT: li t1, 25
+; CHECK-NEXT: mul t0, t0, t1
+; CHECK-NEXT: add t0, sp, t0
+; CHECK-NEXT: addi t0, t0, 16
+; CHECK-NEXT: vs1r.v v0, (t0) # vscale x 8-byte Folded Spill
+; CHECK-NEXT: vsetvli t0, zero, e8, mf4, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a7
+; CHECK-NEXT: addi a7, sp, 16
; CHECK-NEXT: vs1r.v v0, (a7) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vx v8, v0, a1
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: li a7, 24
-; CHECK-NEXT: mul a1, a1, a7
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs1r.v v8, (a1) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: add a1, a2, a5
-; CHECK-NEXT: vl8re64.v v8, (a1)
-; CHECK-NEXT: sltu a1, a4, a6
-; CHECK-NEXT: addi a1, a1, -1
-; CHECK-NEXT: and a6, a1, a6
-; CHECK-NEXT: li a1, 63
-; CHECK-NEXT: csrr a7, vlenb
-; CHECK-NEXT: li t0, 24
-; CHECK-NEXT: mul a7, a7, t0
-; CHECK-NEXT: add a7, sp, a7
-; CHECK-NEXT: addi a7, a7, 16
-; CHECK-NEXT: vl1r.v v0, (a7) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; CHECK-NEXT: vand.vx v24, v8, a1, v0.t
+; CHECK-NEXT: vsll.vv v16, v16, v24, v0.t
; CHECK-NEXT: csrr a6, vlenb
-; CHECK-NEXT: li a7, 24
-; CHECK-NEXT: mul a6, a6, a7
+; CHECK-NEXT: slli a7, a6, 3
+; CHECK-NEXT: add a6, a7, a6
; CHECK-NEXT: add a6, sp, a6
; CHECK-NEXT: addi a6, a6, 16
-; CHECK-NEXT: vl1r.v v0, (a6) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsll.vv v16, v16, v24, v0.t
-; CHECK-NEXT: addi a6, sp, 16
; CHECK-NEXT: vs8r.v v16, (a6) # vscale x 64-byte Folded Spill
; CHECK-NEXT: add a5, a0, a5
-; CHECK-NEXT: csrr a6, vlenb
-; CHECK-NEXT: li a7, 24
-; CHECK-NEXT: mul a6, a6, a7
-; CHECK-NEXT: add a6, sp, a6
-; CHECK-NEXT: addi a6, a6, 16
-; CHECK-NEXT: vl1r.v v0, (a6) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vnot.v v24, v8, v0.t
; CHECK-NEXT: vl8re64.v v16, (a5)
-; CHECK-NEXT: csrr a5, vlenb
-; CHECK-NEXT: li a6, 24
-; CHECK-NEXT: mul a5, a5, a6
-; CHECK-NEXT: add a5, sp, a5
-; CHECK-NEXT: addi a5, a5, 16
-; CHECK-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vand.vx v8, v24, a1, v0.t
; CHECK-NEXT: vl8re64.v v24, (a0)
+; CHECK-NEXT: vl8re64.v v0, (a2)
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vl8re64.v v24, (a2)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a2, 24
-; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v0, (a0) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsrl.vi v16, v16, 1, v0.t
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a2, 24
-; CHECK-NEXT: mul a0, a0, a2
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsrl.vv v8, v16, v8, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a2, 24
-; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: slli a2, a0, 3
+; CHECK-NEXT: add a0, a2, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a2, 24
-; CHECK-NEXT: mul a0, a0, a2
+; CHECK-NEXT: slli a2, a0, 3
+; CHECK-NEXT: add a0, a2, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
@@ -1612,68 +1577,74 @@ define <vscale x 16 x i64> @fshl_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
; CHECK-NEXT: mv a4, a3
; CHECK-NEXT: .LBB47_2:
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: li a2, 25
+; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
+; CHECK-NEXT: vsrl.vi v16, v24, 1, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: li a2, 25
+; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
-; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vnot.v v24, v24, v0.t
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vnot.v v24, v8, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: li a2, 25
+; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vand.vx v24, v24, a1, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: li a2, 25
+; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsrl.vv v16, v16, v24, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: li a2, 25
+; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vand.vx v24, v8, a1, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: slli a1, a0, 4
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: li a1, 25
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsll.vv v24, v8, v24, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 5
+; CHECK-NEXT: li a1, 25
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vor.vv v8, v24, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: li a1, 24
-; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: slli a1, a0, 3
+; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a1, a0, 5
-; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: li a1, 26
+; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa sp, 16
; CHECK-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
index 0d6d09e8dfa08..e81abda5f301c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
@@ -453,8 +453,8 @@ define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_2(<vscale x 4 x i1> %v, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
+; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: srli a1, a0, 3
diff --git a/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
index d3c3349919ec9..1ac2ee1234d78 100644
--- a/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/llrint-vp.ll
@@ -52,14 +52,14 @@ define <vscale x 16 x i64> @llrint_nxv16i64_nxv16f32(<vscale x 16 x float> %x, <
; CHECK-LABEL: llrint_nxv16i64_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma
; CHECK-NEXT: vfwcvt.x.f.v v16, v12, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB4_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
index e672a3a554962..a7bd1d379eb43 100644
--- a/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll
@@ -114,14 +114,14 @@ define <vscale x 16 x iXLen> @lrint_nxv16f32(<vscale x 16 x float> %x, <vscale x
; RV64-i64-LABEL: lrint_nxv16f32:
; RV64-i64: # %bb.0:
; RV64-i64-NEXT: csrr a1, vlenb
-; RV64-i64-NEXT: srli a2, a1, 3
-; RV64-i64-NEXT: sub a3, a0, a1
+; RV64-i64-NEXT: sub a2, a0, a1
+; RV64-i64-NEXT: sltu a3, a0, a2
+; RV64-i64-NEXT: addi a3, a3, -1
+; RV64-i64-NEXT: and a2, a3, a2
+; RV64-i64-NEXT: srli a3, a1, 3
; RV64-i64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; RV64-i64-NEXT: vmv1r.v v24, v0
-; RV64-i64-NEXT: vslidedown.vx v0, v0, a2
-; RV64-i64-NEXT: sltu a2, a0, a3
-; RV64-i64-NEXT: addi a2, a2, -1
-; RV64-i64-NEXT: and a2, a2, a3
+; RV64-i64-NEXT: vslidedown.vx v0, v0, a3
; RV64-i64-NEXT: vsetvli zero, a2, e32, m4, ta, ma
; RV64-i64-NEXT: vfwcvt.x.f.v v16, v12, v0.t
; RV64-i64-NEXT: bltu a0, a1, .LBB4_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
index 75b8aa515a717..792426e96dceb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
@@ -2284,16 +2284,16 @@ define <vscale x 32 x i8> @mgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8>
; RV64-NEXT: vluxei64.v v13, (a0), v16, v0.t
; RV64-NEXT: srli a1, a1, 2
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vslidedown.vx v9, v8, a1
-; RV64-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v0, v9, a2
+; RV64-NEXT: vslidedown.vx v8, v8, a1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v11
-; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
+; RV64-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
+; RV64-NEXT: vslidedown.vx v0, v8, a2
+; RV64-NEXT: vsetvli a1, zero, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v15, (a0), v16, v0.t
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v10
-; RV64-NEXT: vmv1r.v v0, v9
+; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v14, (a0), v16, v0.t
; RV64-NEXT: vmv4r.v v8, v12
diff --git a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
index 639a91535f191..a7afdcc817343 100644
--- a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
@@ -1951,8 +1951,8 @@ define void @mscatter_baseidx_zext_nxv1i1_nxv1i8(<vscale x 1 x i8> %val, ptr %ba
; CHECK-LABEL: mscatter_baseidx_zext_nxv1i1_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
+; CHECK-NEXT: vmv.v.i v11, 0
+; CHECK-NEXT: vmerge.vim v10, v11, 1, v0
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vsoxei8.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
index f7b68ce1f64b8..4e69a2623339d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
@@ -17,10 +17,10 @@ define <vscale x 1 x bfloat> @vp_nearbyint_nxv1bf16(<vscale x 1 x bfloat> %va, <
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
@@ -67,10 +67,10 @@ define <vscale x 2 x bfloat> @vp_nearbyint_nxv2bf16(<vscale x 2 x bfloat> %va, <
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
@@ -296,12 +296,12 @@ define <vscale x 32 x bfloat> @vp_nearbyint_nxv32bf16(<vscale x 32 x bfloat> %va
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; CHECK-NEXT: fsflags a2
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
+; CHECK-NEXT: fsflags a2
; CHECK-NEXT: bltu a0, a1, .LBB10_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -359,12 +359,12 @@ define <vscale x 32 x bfloat> @vp_nearbyint_nxv32bf16_unmasked(<vscale x 32 x bf
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; CHECK-NEXT: fsflags a2
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v12, v16, v0.t
+; CHECK-NEXT: fsflags a2
; CHECK-NEXT: bltu a0, a1, .LBB11_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a1
@@ -410,10 +410,10 @@ define <vscale x 1 x half> @vp_nearbyint_nxv1f16(<vscale x 1 x half> %va, <vscal
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
@@ -494,10 +494,10 @@ define <vscale x 2 x half> @vp_nearbyint_nxv2f16(<vscale x 2 x half> %va, <vscal
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
@@ -865,12 +865,12 @@ define <vscale x 32 x half> @vp_nearbyint_nxv32f16(<vscale x 32 x half> %va, <vs
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; ZVFHMIN-NEXT: fsflags a2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: fsflags a2
; ZVFHMIN-NEXT: bltu a0, a1, .LBB22_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
@@ -944,12 +944,12 @@ define <vscale x 32 x half> @vp_nearbyint_nxv32f16_unmasked(<vscale x 32 x half>
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
-; ZVFHMIN-NEXT: fsflags a2
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
; ZVFHMIN-NEXT: vmv1r.v v0, v12
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: fsflags a2
; ZVFHMIN-NEXT: bltu a0, a1, .LBB23_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a0, a1
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr165232.ll b/llvm/test/CodeGen/RISCV/rvv/pr165232.ll
index 39a1b3b6e4559..9c4c293d599b4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/pr165232.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/pr165232.ll
@@ -12,254 +12,183 @@ define i1 @main(ptr %var_117, ptr %arrayinit.element3045, ptr %arrayinit.element
; CHECK-NEXT: csrr t0, vlenb
; CHECK-NEXT: slli t0, t0, 1
; CHECK-NEXT: mv t1, t0
+; CHECK-NEXT: slli t0, t0, 3
+; CHECK-NEXT: add t0, t0, t1
+; CHECK-NEXT: sub sp, sp, t0
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x12, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 18 * vlenb
+; CHECK-NEXT: csrr t0, vlenb
+; CHECK-NEXT: slli t0, t0, 1
+; CHECK-NEXT: mv t1, t0
; CHECK-NEXT: slli t0, t0, 2
-; CHECK-NEXT: add t1, t1, t0
+; CHECK-NEXT: add t0, t0, t1
+; CHECK-NEXT: add t0, sp, t0
+; CHECK-NEXT: addi t0, t0, 16
+; CHECK-NEXT: vs4r.v v12, (t0) # vscale x 32-byte Folded Spill
+; CHECK-NEXT: csrr t1, vlenb
+; CHECK-NEXT: slli t1, t1, 2
+; CHECK-NEXT: add t0, t0, t1
+; CHECK-NEXT: vs4r.v v16, (t0) # vscale x 32-byte Folded Spill
+; CHECK-NEXT: csrr t0, vlenb
+; CHECK-NEXT: slli t0, t0, 1
+; CHECK-NEXT: mv t1, t0
; CHECK-NEXT: slli t0, t0, 1
; CHECK-NEXT: add t0, t0, t1
-; CHECK-NEXT: sub sp, sp, t0
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x1a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 26 * vlenb
-; CHECK-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
-; CHECK-NEXT: sd a2, 0(sp) # 8-byte Folded Spill
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs4r.v v12, (a1) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 2
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: vs4r.v v16, (a1) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: ld t0, 56(a1)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: ld t1, 48(a1)
+; CHECK-NEXT: add t0, sp, t0
+; CHECK-NEXT: addi t0, t0, 16
+; CHECK-NEXT: vs4r.v v8, (t0) # vscale x 32-byte Folded Spill
+; CHECK-NEXT: csrr t0, vlenb
+; CHECK-NEXT: slli t0, t0, 1
+; CHECK-NEXT: mv t1, t0
+; CHECK-NEXT: slli t0, t0, 3
+; CHECK-NEXT: add t0, t0, t1
+; CHECK-NEXT: add t0, sp, t0
+; CHECK-NEXT: ld t0, 56(t0)
+; CHECK-NEXT: csrr t1, vlenb
+; CHECK-NEXT: slli t1, t1, 1
+; CHECK-NEXT: mv t2, t1
+; CHECK-NEXT: slli t1, t1, 3
+; CHECK-NEXT: add t1, t1, t2
+; CHECK-NEXT: add t1, sp, t1
+; CHECK-NEXT: ld t1, 48(t1)
; CHECK-NEXT: vsetvli t2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: ld t2, 40(a1)
-; CHECK-NEXT: # kill: def $v13 killed $v12 killed $vtype
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: ld t3, 32(a1)
-; CHECK-NEXT: vmv.v.i v14, 0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: ld t4, 16(a1)
+; CHECK-NEXT: vmv.v.i v13, 0
+; CHECK-NEXT: csrr t2, vlenb
+; CHECK-NEXT: slli t2, t2, 1
+; CHECK-NEXT: mv t3, t2
+; CHECK-NEXT: slli t2, t2, 3
+; CHECK-NEXT: add t2, t2, t3
+; CHECK-NEXT: add t2, sp, t2
+; CHECK-NEXT: ld t2, 40(t2)
+; CHECK-NEXT: # kill: def $v14 killed $v13 killed $vtype
+; CHECK-NEXT: csrr t3, vlenb
+; CHECK-NEXT: slli t3, t3, 1
+; CHECK-NEXT: mv t4, t3
+; CHECK-NEXT: slli t3, t3, 3
+; CHECK-NEXT: add t3, t3, t4
+; CHECK-NEXT: add t3, sp, t3
+; CHECK-NEXT: ld t3, 32(t3)
; CHECK-NEXT: vmv.v.i v15, 0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: slli a1, a1, 2
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: ld t5, 24(a1)
+; CHECK-NEXT: csrr t4, vlenb
+; CHECK-NEXT: slli t4, t4, 1
+; CHECK-NEXT: mv t5, t4
+; CHECK-NEXT: slli t4, t4, 3
+; CHECK-NEXT: add t4, t4, t5
+; CHECK-NEXT: add t4, sp, t4
+; CHECK-NEXT: ld t4, 16(t4)
; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: csrr t5, vlenb
+; CHECK-NEXT: slli t5, t5, 1
+; CHECK-NEXT: mv t6, t5
+; CHECK-NEXT: slli t5, t5, 3
+; CHECK-NEXT: add t5, t5, t6
+; CHECK-NEXT: add t5, sp, t5
+; CHECK-NEXT: ld t5, 24(t5)
+; CHECK-NEXT: vmv.v.i v17, 0
; CHECK-NEXT: vsetvli t6, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v20, 0
-; CHECK-NEXT: vmv1r.v v17, v12
+; CHECK-NEXT: vmv1r.v v18, v13
; CHECK-NEXT: sd zero, 0(a0)
; CHECK-NEXT: vmv.v.i v22, 0
-; CHECK-NEXT: vmv1r.v v18, v12
-; CHECK-NEXT: vmv4r.v v8, v12
+; CHECK-NEXT: vmv1r.v v19, v13
+; CHECK-NEXT: vmv1r.v v8, v13
; CHECK-NEXT: li t6, 1023
; CHECK-NEXT: vmv.v.i v24, 0
-; CHECK-NEXT: vmv1r.v v9, v12
+; CHECK-NEXT: vmv1r.v v9, v13
; CHECK-NEXT: slli t6, t6, 52
; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vs4r.v v20, (a1) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: slli a2, a2, 2
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: ld a2, 0(sp) # 8-byte Folded Reload
-; CHECK-NEXT: vs4r.v v24, (a1) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
-; CHECK-NEXT: vmv1r.v v10, v12
+; CHECK-NEXT: vmv1r.v v10, v13
; CHECK-NEXT: sd t6, 0(t5)
-; CHECK-NEXT: vmv1r.v v19, v12
-; CHECK-NEXT: vmv1r.v v20, v13
-; CHECK-NEXT: vmv1r.v v21, v14
-; CHECK-NEXT: vmv1r.v v22, v15
-; CHECK-NEXT: vmv1r.v v23, v16
-; CHECK-NEXT: vmv1r.v v24, v17
-; CHECK-NEXT: vmv1r.v v25, v18
-; CHECK-NEXT: vmv1r.v v11, v12
+; CHECK-NEXT: vmv1r.v v11, v13
; CHECK-NEXT: csrr t5, vlenb
; CHECK-NEXT: slli t5, t5, 1
-; CHECK-NEXT: mv t6, t5
-; CHECK-NEXT: slli t5, t5, 2
-; CHECK-NEXT: add t5, t5, t6
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
; CHECK-NEXT: vs4r.v v8, (t5) # vscale x 32-byte Folded Spill
-; CHECK-NEXT: vsetivli zero, 0, e64, m2, ta, ma
+; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; CHECK-NEXT: vmclr.m v8
+; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: csrr t5, vlenb
-; CHECK-NEXT: slli t6, t5, 3
-; CHECK-NEXT: add t5, t6, t5
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
; CHECK-NEXT: vs1r.v v8, (t5) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: csrr t5, vlenb
-; CHECK-NEXT: slli t5, t5, 3
-; CHECK-NEXT: add t5, sp, t5
-; CHECK-NEXT: addi t5, t5, 16
+; CHECK-NEXT: addi t5, sp, 16
; CHECK-NEXT: vs1r.v v8, (t5) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: .LBB0_1: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmv.v.i v30, 0
-; CHECK-NEXT: vmv.v.i v31, 0
-; CHECK-NEXT: vmv.v.i v13, 0
-; CHECK-NEXT: vmv.v.i v26, 0
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmv.v.i v11, 0
-; CHECK-NEXT: vmv.v.i v18, 0
-; CHECK-NEXT: vmv2r.v v0, v18
-; CHECK-NEXT: vmv2r.v v2, v20
-; CHECK-NEXT: vmv2r.v v4, v22
-; CHECK-NEXT: vmv2r.v v6, v24
-; CHECK-NEXT: vmv2r.v v14, v16
-; CHECK-NEXT: vmv2r.v v28, v16
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: csrr t5, vlenb
-; CHECK-NEXT: slli t6, t5, 3
-; CHECK-NEXT: add t5, t6, t5
-; CHECK-NEXT: add t5, sp, t5
-; CHECK-NEXT: addi t5, t5, 16
-; CHECK-NEXT: vl1r.v v8, (t5) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma
-; CHECK-NEXT: vle32.v v30, (t4)
-; CHECK-NEXT: vle32.v v31, (t1)
-; CHECK-NEXT: vle32.v v11, (a7)
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-NEXT: vmv.v.i v6, 0
+; CHECK-NEXT: vmv.v.i v28, 0
+; CHECK-NEXT: vmv1r.v v30, v9
+; CHECK-NEXT: vmv1r.v v12, v9
+; CHECK-NEXT: vsetvli zero, zero, e64, m2, tu, ma
; CHECK-NEXT: vle64.v v28, (a4)
-; CHECK-NEXT: vle32.v v13, (t2)
-; CHECK-NEXT: vle32.v v26, (t3)
-; CHECK-NEXT: vle32.v v10, (a6)
-; CHECK-NEXT: vmv1r.v v2, v11
+; CHECK-NEXT: vle32.v v30, (a2)
+; CHECK-NEXT: vle32.v v12, (a3)
; CHECK-NEXT: csrr t5, vlenb
-; CHECK-NEXT: slli t5, t5, 3
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
-; CHECK-NEXT: vl1r.v v0, (t5) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vl1r.v v10, (t5) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
-; CHECK-NEXT: vmflt.vv v8, v28, v16, v0.t
-; CHECK-NEXT: vmv1r.v v11, v0
-; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vmflt.vv v10, v28, v6, v0.t
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu
-; CHECK-NEXT: vle32.v v12, (a2)
-; CHECK-NEXT: vle32.v v10, (a3)
-; CHECK-NEXT: vle32.v v18, (a5)
-; CHECK-NEXT: vmv1r.v v0, v30
+; CHECK-NEXT: vssub.vv v12, v9, v30, v0.t
+; CHECK-NEXT: vmv1r.v v10, v9
+; CHECK-NEXT: vmv1r.v v11, v9
+; CHECK-NEXT: vmv1r.v v28, v9
+; CHECK-NEXT: vmv1r.v v29, v9
+; CHECK-NEXT: vmv1r.v v30, v9
+; CHECK-NEXT: vmv1r.v v31, v9
+; CHECK-NEXT: vle32.v v10, (t4)
+; CHECK-NEXT: vle32.v v31, (a7)
+; CHECK-NEXT: vle32.v v11, (t1)
+; CHECK-NEXT: vle32.v v28, (t2)
+; CHECK-NEXT: vle32.v v29, (t3)
+; CHECK-NEXT: vmv1r.v v2, v13
+; CHECK-NEXT: vmv1r.v v4, v15
+; CHECK-NEXT: vmv1r.v v5, v16
+; CHECK-NEXT: vmv1r.v v6, v17
+; CHECK-NEXT: vmv1r.v v7, v18
+; CHECK-NEXT: vmv1r.v v8, v19
+; CHECK-NEXT: vle32.v v30, (a6)
+; CHECK-NEXT: vmv1r.v v3, v31
+; CHECK-NEXT: vmv1r.v v11, v9
+; CHECK-NEXT: vle32.v v11, (a5)
+; CHECK-NEXT: vmv1r.v v1, v10
; CHECK-NEXT: csrr t5, vlenb
; CHECK-NEXT: slli t5, t5, 1
-; CHECK-NEXT: mv t6, t5
-; CHECK-NEXT: slli t5, t5, 2
-; CHECK-NEXT: add t5, t5, t6
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
; CHECK-NEXT: vl4r.v v28, (t5) # vscale x 32-byte Folded Reload
; CHECK-NEXT: vsseg4e32.v v28, (zero)
-; CHECK-NEXT: vsseg8e32.v v0, (a1)
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vssub.vv v10, v9, v12, v0.t
+; CHECK-NEXT: vsseg8e32.v v1, (a1)
; CHECK-NEXT: csrr t5, vlenb
; CHECK-NEXT: slli t5, t5, 1
; CHECK-NEXT: mv t6, t5
; CHECK-NEXT: slli t5, t5, 1
-; CHECK-NEXT: add t6, t6, t5
-; CHECK-NEXT: slli t5, t5, 1
; CHECK-NEXT: add t5, t5, t6
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
-; CHECK-NEXT: vl2r.v v2, (t5) # vscale x 16-byte Folded Reload
-; CHECK-NEXT: csrr t6, vlenb
-; CHECK-NEXT: slli t6, t6, 1
-; CHECK-NEXT: add t5, t5, t6
-; CHECK-NEXT: vl2r.v v4, (t5) # vscale x 16-byte Folded Reload
+; CHECK-NEXT: vl4r.v v28, (t5) # vscale x 32-byte Folded Reload
; CHECK-NEXT: vsetvli zero, t0, e64, m2, ta, ma
-; CHECK-NEXT: vsseg2e64.v v2, (zero)
+; CHECK-NEXT: vsseg2e64.v v28, (zero)
; CHECK-NEXT: addi t5, sp, 16
-; CHECK-NEXT: vl2r.v v2, (t5) # vscale x 16-byte Folded Reload
-; CHECK-NEXT: csrr t6, vlenb
-; CHECK-NEXT: slli t6, t6, 1
-; CHECK-NEXT: add t5, t5, t6
-; CHECK-NEXT: vl4r.v v4, (t5) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: slli t6, t6, 1
-; CHECK-NEXT: add t5, t5, t6
-; CHECK-NEXT: vl2r.v v8, (t5) # vscale x 16-byte Folded Reload
-; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vl1r.v v0, (t5) # vscale x 8-byte Folded Reload
; CHECK-NEXT: vsetivli zero, 0, e64, m2, ta, ma
-; CHECK-NEXT: vsseg4e64.v v2, (zero), v0.t
+; CHECK-NEXT: vsseg4e64.v v20, (zero), v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vsseg8e32.v v10, (a0)
+; CHECK-NEXT: vsseg8e32.v v12, (a0)
; CHECK-NEXT: csrr t5, vlenb
; CHECK-NEXT: slli t5, t5, 1
; CHECK-NEXT: mv t6, t5
-; CHECK-NEXT: slli t5, t5, 3
+; CHECK-NEXT: slli t5, t5, 2
; CHECK-NEXT: add t5, t5, t6
; CHECK-NEXT: add t5, sp, t5
; CHECK-NEXT: addi t5, t5, 16
-; CHECK-NEXT: vl2r.v v2, (t5) # vscale x 16-byte Folded Reload
-; CHECK-NEXT: csrr t6, vlenb
-; CHECK-NEXT: slli t6, t6, 1
-; CHECK-NEXT: add t5, t5, t6
-; CHECK-NEXT: vl4r.v v4, (t5) # vscale x 32-byte Folded Reload
-; CHECK-NEXT: slli t6, t6, 1
-; CHECK-NEXT: add t5, t5, t6
-; CHECK-NEXT: vl2r.v v8, (t5) # vscale x 16-byte Folded Reload
+; CHECK-NEXT: vl8r.v v0, (t5) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; CHECK-NEXT: vsseg4e64.v v2, (zero)
+; CHECK-NEXT: vsseg4e64.v v0, (zero)
; CHECK-NEXT: j .LBB0_1
entry:
store double 0.000000e+00, ptr %var_117, align 8
diff --git a/llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll b/llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
index bfff09bc35c8e..b66ef6511a823 100644
--- a/llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/reproducer-pr146855.ll
@@ -19,11 +19,12 @@ define i32 @_ZN4Mesh12rezone_countESt6vectorIiSaIiEERiS3_(<vscale x 4 x i32> %wi
; CHECK-NEXT: vmv2r.v v14, v8
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vle32.v v14, (a0), v0.t
-; CHECK-NEXT: vor.vi v12, v12, 1, v0.t
; CHECK-NEXT: vand.vi v14, v14, 1
; CHECK-NEXT: vmsne.vi v16, v14, 0
; CHECK-NEXT: vmand.mm v0, v17, v16
; CHECK-NEXT: vmerge.vim v10, v10, -1, v0
+; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vor.vi v12, v12, 1, v0.t
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: j .LBB0_1
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll
index c5a3b2252de19..7c6074d2dcf5b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll
@@ -17,12 +17,12 @@ define <vscale x 1 x bfloat> @vp_round_nxv1bf16(<vscale x 1 x bfloat> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -67,12 +67,12 @@ define <vscale x 2 x bfloat> @vp_round_nxv2bf16(<vscale x 2 x bfloat> %va, <vsca
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 4
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
@@ -410,12 +410,12 @@ define <vscale x 1 x half> @vp_round_nxv1f16(<vscale x 1 x half> %va, <vscale x
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -494,12 +494,12 @@ define <vscale x 2 x half> @vp_round_nxv2f16(<vscale x 2 x half> %va, <vscale x
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 4
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll b/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
index 443909ba2cc25..40a4642d51979 100644
--- a/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
@@ -17,12 +17,12 @@ define <vscale x 1 x bfloat> @vp_roundeven_nxv1bf16(<vscale x 1 x bfloat> %va, <
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -67,12 +67,12 @@ define <vscale x 2 x bfloat> @vp_roundeven_nxv2bf16(<vscale x 2 x bfloat> %va, <
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
@@ -410,12 +410,12 @@ define <vscale x 1 x half> @vp_roundeven_nxv1f16(<vscale x 1 x half> %va, <vscal
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -494,12 +494,12 @@ define <vscale x 2 x half> @vp_roundeven_nxv2f16(<vscale x 2 x half> %va, <vscal
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
index b81e2d7568ceb..6238d57e7eea5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
@@ -17,12 +17,12 @@ define <vscale x 1 x bfloat> @vp_roundtozero_nxv1bf16(<vscale x 1 x bfloat> %va,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -67,12 +67,12 @@ define <vscale x 2 x bfloat> @vp_roundtozero_nxv2bf16(<vscale x 2 x bfloat> %va,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8, v0.t
-; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: lui a0, 307200
; CHECK-NEXT: fmv.w.x fa5, a0
; CHECK-NEXT: fsrmi a0, 1
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfabs.v v8, v9, v0.t
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vf v0, v8, fa5, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
@@ -410,12 +410,12 @@ define <vscale x 1 x half> @vp_roundtozero_nxv1f16(<vscale x 1 x half> %va, <vsc
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
@@ -494,12 +494,12 @@ define <vscale x 2 x half> @vp_roundtozero_nxv2f16(<vscale x 2 x half> %va, <vsc
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: lui a0, 307200
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fsrmi a0, 1
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; ZVFHMIN-NEXT: vfabs.v v8, v9, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v10, v0
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
index 7357260229c56..6ad291b37f313 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
@@ -1381,17 +1381,6 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64bf16(<vscale x 64 x bfloat> %va, <vs
; CHECK-NEXT: and a7, a7, a1
; CHECK-NEXT: srli a1, a3, 1
; CHECK-NEXT: srli a3, a3, 2
-; CHECK-NEXT: csrr t0, vlenb
-; CHECK-NEXT: mv t1, t0
-; CHECK-NEXT: slli t0, t0, 3
-; CHECK-NEXT: add t1, t1, t0
-; CHECK-NEXT: slli t0, t0, 2
-; CHECK-NEXT: add t0, t0, t1
-; CHECK-NEXT: add t0, sp, t0
-; CHECK-NEXT: addi t0, t0, 16
-; CHECK-NEXT: vl1r.v v8, (t0) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli t0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v6, v8, a1
; CHECK-NEXT: vl8re16.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: mv t0, a0
@@ -1418,9 +1407,21 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64bf16(<vscale x 64 x bfloat> %va, <vs
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20
-; CHECK-NEXT: vmv1r.v v7, v6
+; CHECK-NEXT: vmv8r.v v16, v8
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: mv t0, a0
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add t0, t0, a0
+; CHECK-NEXT: slli a0, a0, 2
+; CHECK-NEXT: add a0, a0, t0
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl1r.v v28, (a0) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v28, v28, a1
+; CHECK-NEXT: vmv.v.v v7, v28
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v6, a3
+; CHECK-NEXT: vslidedown.vx v0, v28, a3
; CHECK-NEXT: bltu a6, a4, .LBB85_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a6, a4
@@ -1429,9 +1430,10 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64bf16(<vscale x 64 x bfloat> %va, <vs
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vmv8r.v v24, v16
; CHECK-NEXT: vsetvli zero, a7, e32, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v16, v8, v24, v0.t
+; CHECK-NEXT: vmfeq.vv v16, v24, v8, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
@@ -3575,17 +3577,6 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFHMIN-NEXT: and a7, a7, a1
; ZVFHMIN-NEXT: srli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
-; ZVFHMIN-NEXT: csrr t0, vlenb
-; ZVFHMIN-NEXT: mv t1, t0
-; ZVFHMIN-NEXT: slli t0, t0, 3
-; ZVFHMIN-NEXT: add t1, t1, t0
-; ZVFHMIN-NEXT: slli t0, t0, 2
-; ZVFHMIN-NEXT: add t0, t0, t1
-; ZVFHMIN-NEXT: add t0, sp, t0
-; ZVFHMIN-NEXT: addi t0, t0, 16
-; ZVFHMIN-NEXT: vl1r.v v8, (t0) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli t0, zero, e8, m1, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v6, v8, a1
; ZVFHMIN-NEXT: vl8re16.v v8, (a0)
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: mv t0, a0
@@ -3612,9 +3603,21 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20
-; ZVFHMIN-NEXT: vmv1r.v v7, v6
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: mv t0, a0
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add t0, t0, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, t0
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl1r.v v28, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v28, v28, a1
+; ZVFHMIN-NEXT: vmv.v.v v7, v28
; ZVFHMIN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v0, v6, a3
+; ZVFHMIN-NEXT: vslidedown.vx v0, v28, a3
; ZVFHMIN-NEXT: bltu a6, a4, .LBB171_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a6, a4
@@ -3623,9 +3626,10 @@ define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscal
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
; ZVFHMIN-NEXT: vsetvli zero, a7, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vmfeq.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: vmfeq.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
@@ -4870,10 +4874,10 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK32-NEXT: vl8re64.v v8, (a2)
; CHECK32-NEXT: slli a5, s0, 4
; CHECK32-NEXT: slli a2, s0, 1
+; CHECK32-NEXT: mv a3, s1
; CHECK32-NEXT: vmv1r.v v7, v16
-; CHECK32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
+; CHECK32-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
; CHECK32-NEXT: vslidedown.vx v0, v16, a0
-; CHECK32-NEXT: mv a3, s1
; CHECK32-NEXT: bltu s1, a2, .LBB257_2
; CHECK32-NEXT: # %bb.1:
; CHECK32-NEXT: mv a3, a2
@@ -5081,10 +5085,10 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
; CHECK64-NEXT: vl8re64.v v8, (a2)
; CHECK64-NEXT: slli a5, s0, 4
; CHECK64-NEXT: slli a2, s0, 1
+; CHECK64-NEXT: mv a3, s1
; CHECK64-NEXT: vmv1r.v v7, v16
-; CHECK64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
+; CHECK64-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
; CHECK64-NEXT: vslidedown.vx v0, v16, a0
-; CHECK64-NEXT: mv a3, s1
; CHECK64-NEXT: bltu s1, a2, .LBB257_2
; CHECK64-NEXT: # %bb.1:
; CHECK64-NEXT: mv a3, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
index 5de9b5550035f..2dd99a820b8d3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
@@ -1078,16 +1078,16 @@ define <vscale x 128 x i1> @icmp_eq_vv_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: sub a4, a3, a1
-; CHECK-NEXT: vl8r.v v24, (a2)
-; CHECK-NEXT: sltu a2, a3, a4
+; CHECK-NEXT: add a4, a0, a1
+; CHECK-NEXT: sub a5, a3, a1
+; CHECK-NEXT: vl8r.v v24, (a4)
+; CHECK-NEXT: sltu a4, a3, a5
+; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vl8r.v v8, (a0)
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a4
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a4, a4, a5
+; CHECK-NEXT: vsetvli zero, a4, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vv v7, v16, v24, v0.t
; CHECK-NEXT: bltu a3, a1, .LBB96_2
; CHECK-NEXT: # %bb.1:
@@ -1116,18 +1116,18 @@ define <vscale x 128 x i1> @icmp_eq_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: sub a3, a2, a1
-; CHECK-NEXT: sltu a4, a2, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
-; CHECK-NEXT: bltu a2, a1, .LBB97_2
+; CHECK-NEXT: bltu a2, a3, .LBB97_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB97_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -1146,18 +1146,18 @@ define <vscale x 128 x i1> @icmp_eq_vx_swap_nxv128i8(<vscale x 128 x i8> %va, i8
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: sub a3, a2, a1
-; CHECK-NEXT: sltu a4, a2, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
-; CHECK-NEXT: bltu a2, a1, .LBB98_2
+; CHECK-NEXT: bltu a2, a3, .LBB98_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB98_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -2250,13 +2250,13 @@ define <vscale x 32 x i1> @icmp_eq_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b,
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: srli a2, a3, 2
; CHECK-NEXT: slli a3, a3, 1
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a4, a1, a3
; CHECK-NEXT: sltu a5, a1, a4
; CHECK-NEXT: addi a5, a5, -1
; CHECK-NEXT: and a4, a5, a4
+; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a3, .LBB190_2
@@ -2282,13 +2282,13 @@ define <vscale x 32 x i1> @icmp_eq_vx_swap_nxv32i32(<vscale x 32 x i32> %va, i32
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: srli a2, a3, 2
; CHECK-NEXT: slli a3, a3, 1
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v25, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: sub a4, a1, a3
; CHECK-NEXT: sltu a5, a1, a4
; CHECK-NEXT: addi a5, a5, -1
; CHECK-NEXT: and a4, a5, a4
+; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vmseq.vx v24, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a3, .LBB191_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll b/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
index 16f373e148bbf..8f519a1d5f7b1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
@@ -709,12 +709,12 @@ define <vscale x 16 x double> @strided_load_nxv17f64(ptr %ptr, i64 %stride, <vsc
; CHECK-RV32-NEXT: .LBB57_4:
; CHECK-RV32-NEXT: mul t1, a5, a1
; CHECK-RV32-NEXT: srli t2, a2, 3
-; CHECK-RV32-NEXT: sub a7, a3, a7
; CHECK-RV32-NEXT: add t1, a0, t1
; CHECK-RV32-NEXT: vsetvli t3, zero, e8, mf4, ta, ma
; CHECK-RV32-NEXT: vslidedown.vx v0, v9, t2
; CHECK-RV32-NEXT: vsetvli zero, t0, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v16, (t1), a1, v0.t
+; CHECK-RV32-NEXT: sub a7, a3, a7
; CHECK-RV32-NEXT: sltu a3, a3, a7
; CHECK-RV32-NEXT: addi a3, a3, -1
; CHECK-RV32-NEXT: and a3, a3, a7
@@ -757,12 +757,12 @@ define <vscale x 16 x double> @strided_load_nxv17f64(ptr %ptr, i64 %stride, <vsc
; CHECK-RV64-NEXT: .LBB57_4:
; CHECK-RV64-NEXT: mul t1, a5, a1
; CHECK-RV64-NEXT: srli t2, a4, 3
-; CHECK-RV64-NEXT: sub a7, a2, a7
; CHECK-RV64-NEXT: add t1, a0, t1
; CHECK-RV64-NEXT: vsetvli t3, zero, e8, mf4, ta, ma
; CHECK-RV64-NEXT: vslidedown.vx v0, v9, t2
; CHECK-RV64-NEXT: vsetvli zero, t0, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v16, (t1), a1, v0.t
+; CHECK-RV64-NEXT: sub a7, a2, a7
; CHECK-RV64-NEXT: sltu a2, a2, a7
; CHECK-RV64-NEXT: addi a2, a2, -1
; CHECK-RV64-NEXT: and a2, a2, a7
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
index f850fb822507c..eda4c53e32478 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
@@ -547,18 +547,18 @@ define <vscale x 128 x i8> @vadd_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub a2, a1, a0
-; CHECK-NEXT: sltu a3, a1, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-NEXT: sltu a0, a1, a3
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a3
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t
-; CHECK-NEXT: bltu a1, a0, .LBB50_2
+; CHECK-NEXT: bltu a1, a2, .LBB50_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
@@ -1299,17 +1299,17 @@ define <vscale x 16 x i32> @vadd_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va, i
define <vscale x 32 x i32> @vadd_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vadd_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB118_2
; CHECK-NEXT: # %bb.1:
@@ -1368,15 +1368,15 @@ define <vscale x 32 x i32> @vadd_vi_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, <v
; RV64-LABEL: vadd_vi_nxv32i32_evl_nx8:
; RV64: # %bb.0:
; RV64-NEXT: csrr a0, vlenb
-; RV64-NEXT: srli a2, a0, 2
; RV64-NEXT: slli a1, a0, 1
-; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
-; RV64-NEXT: vslidedown.vx v0, v0, a2
; RV64-NEXT: sub a2, a0, a1
; RV64-NEXT: sltu a3, a0, a2
; RV64-NEXT: addi a3, a3, -1
; RV64-NEXT: and a2, a3, a2
+; RV64-NEXT: srli a3, a0, 2
+; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV64-NEXT: vadd.vi v16, v16, -1, v0.t
; RV64-NEXT: bltu a0, a1, .LBB120_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
index 93a626e355a6b..69574cc56742b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
@@ -101,16 +101,13 @@ define {<4 x i64>, <4 x i64>} @vector_deinterleave_v4i64_v8i64(<8 x i64> %vec) {
; V-NEXT: vmv.v.i v0, 8
; V-NEXT: vsetivli zero, 4, e64, m4, ta, ma
; V-NEXT: vslidedown.vi v12, v8, 4
-; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; V-NEXT: vmv.v.i v17, 2
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; V-NEXT: vslideup.vi v10, v12, 2
; V-NEXT: vslideup.vi v10, v12, 1, v0.t
; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; V-NEXT: vmv.v.i v18, 12
+; V-NEXT: vmv.v.i v0, 2
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; V-NEXT: vslidedown.vi v14, v8, 1
-; V-NEXT: vmv1r.v v0, v17
; V-NEXT: vslidedown.vi v14, v8, 2, v0.t
; V-NEXT: vslidedown.vi v8, v8, 1, v0.t
; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
@@ -118,7 +115,9 @@ define {<4 x i64>, <4 x i64>} @vector_deinterleave_v4i64_v8i64(<8 x i64> %vec) {
; V-NEXT: vmv2r.v v16, v12
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; V-NEXT: vslideup.vi v16, v12, 1, v0.t
-; V-NEXT: vmv1r.v v0, v18
+; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; V-NEXT: vmv.v.i v0, 12
+; V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; V-NEXT: vmerge.vvm v8, v8, v10, v0
; V-NEXT: vmerge.vvm v10, v14, v16, v0
; V-NEXT: ret
@@ -483,16 +482,13 @@ define {<4 x double>, <4 x double>} @vector_deinterleave_v4f64_v8f64(<8 x double
; V-NEXT: vmv.v.i v0, 8
; V-NEXT: vsetivli zero, 4, e64, m4, ta, ma
; V-NEXT: vslidedown.vi v12, v8, 4
-; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; V-NEXT: vmv.v.i v17, 2
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; V-NEXT: vslideup.vi v10, v12, 2
; V-NEXT: vslideup.vi v10, v12, 1, v0.t
; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
-; V-NEXT: vmv.v.i v18, 12
+; V-NEXT: vmv.v.i v0, 2
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; V-NEXT: vslidedown.vi v14, v8, 1
-; V-NEXT: vmv1r.v v0, v17
; V-NEXT: vslidedown.vi v14, v8, 2, v0.t
; V-NEXT: vslidedown.vi v8, v8, 1, v0.t
; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
@@ -500,7 +496,9 @@ define {<4 x double>, <4 x double>} @vector_deinterleave_v4f64_v8f64(<8 x double
; V-NEXT: vmv2r.v v16, v12
; V-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; V-NEXT: vslideup.vi v16, v12, 1, v0.t
-; V-NEXT: vmv1r.v v0, v18
+; V-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
+; V-NEXT: vmv.v.i v0, 12
+; V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; V-NEXT: vmerge.vvm v8, v8, v10, v0
; V-NEXT: vmerge.vvm v10, v14, v16, v0
; V-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
index 6b23ac6998e5e..afe18a9581ea5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
@@ -188,8 +188,8 @@ define {<vscale x 64 x i1>, <vscale x 64 x i1>} @vector_deinterleave_nxv64i1_nxv
; ZIP: # %bb.0:
; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZIP-NEXT: vmv1r.v v24, v0
-; ZIP-NEXT: vmv.v.i v16, 0
; ZIP-NEXT: vmv1r.v v0, v8
+; ZIP-NEXT: vmv.v.i v16, 0
; ZIP-NEXT: vmerge.vim v8, v16, 1, v0
; ZIP-NEXT: vmv1r.v v0, v24
; ZIP-NEXT: vmerge.vim v24, v16, 1, v0
@@ -357,19 +357,18 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>} @vector_dein
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: vmerge.vim v8, v12, 1, v0
+; CHECK-NEXT: vmv1r.v v14, v0
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v10, v0, a1
+; CHECK-NEXT: vslidedown.vx v0, v0, a1
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v10, v12, 1, v0
; CHECK-NEXT: addi a1, sp, 16
-; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v8, v12, 1, v0
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v14, v0, a0
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vslidedown.vx v0, v14, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v10, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: vlseg3e8.v v8, (a1)
@@ -476,32 +475,30 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: sub sp, sp, a0
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: sub a2, a0, a1
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v9, v0, a2
-; CHECK-NEXT: vmv1r.v v8, v0
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: srli a0, a0, 1
-; CHECK-NEXT: vmv.v.v v0, v9
-; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v14, v10, 1, v0
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: srli a0, a0, 1
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v12, v10, 1, v0
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v16, v8, a1
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v16
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a1
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
-; CHECK-NEXT: vs8r.v v8, (a2)
-; CHECK-NEXT: vlseg4e8.v v8, (a2)
+; CHECK-NEXT: vs8r.v v8, (a0)
+; CHECK-NEXT: vlseg4e8.v v8, (a0)
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vmsne.vi v8, v10, 0
; CHECK-NEXT: vmsne.vi v9, v12, 0
@@ -603,36 +600,39 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmv1r.v v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vim v14, v12, 1, v0
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmerge.vim v24, v12, 1, v0
-; CHECK-NEXT: vmv1r.v v10, v0
+; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vmerge.vim v8, v12, 1, v0
+; CHECK-NEXT: vmv1r.v v16, v0
; CHECK-NEXT: srli a1, a0, 2
-; CHECK-NEXT: srli a2, a0, 1
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v14, v12, 1, v0
-; CHECK-NEXT: sub a0, a0, a1
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v10, a0
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v0, a1
+; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v10, v12, 1, v0
+; CHECK-NEXT: sub a1, a0, a1
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v16, a1
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v20, v12, 1, v0
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v10, a1
-; CHECK-NEXT: vslidedown.vx v8, v10, a2
-; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v26, v12, 1, v0
+; CHECK-NEXT: srli a0, a0, 1
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v16, a0
; CHECK-NEXT: vmv1r.v v18, v21
-; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v28, v12, 1, v0
+; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
; CHECK-NEXT: vmv1r.v v19, v14
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vmv1r.v v16, v29
+; CHECK-NEXT: vmv1r.v v16, v13
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vmv1r.v v17, v20
-; CHECK-NEXT: vs8r.v v24, (a0)
+; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: vmv1r.v v20, v15
; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
@@ -835,7 +835,7 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: vmv.v.i v14, 0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vmerge.vim v24, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v16, v0
+; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a1
@@ -843,29 +843,30 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: vmerge.vim v26, v14, 1, v0
; CHECK-NEXT: srli a2, a0, 1
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v16, a2
+; CHECK-NEXT: vslidedown.vx v0, v9, a2
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v28, v14, 1, v0
-; CHECK-NEXT: addi a2, sp, 16
-; CHECK-NEXT: vs8r.v v24, (a2)
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v10, v14, 1, v0
+; CHECK-NEXT: vmerge.vim v18, v14, 1, v0
; CHECK-NEXT: sub a0, a0, a1
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v12, v8, a1
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vslidedown.vx v0, v16, a0
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v9, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v8, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmerge.vim v12, v14, 1, v0
-; CHECK-NEXT: vs8r.v v8, (a1)
-; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vlseg6e8.v v16, (a2)
-; CHECK-NEXT: vlseg6e8.v v10, (a1)
+; CHECK-NEXT: vmerge.vim v16, v14, 1, v0
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs8r.v v24, (a0)
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v8, a1
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
+; CHECK-NEXT: vs8r.v v16, (a2)
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; CHECK-NEXT: vlseg6e8.v v16, (a0)
+; CHECK-NEXT: vlseg6e8.v v10, (a2)
; CHECK-NEXT: vmv2r.v v8, v16
; CHECK-NEXT: vmv2r.v v22, v18
; CHECK-NEXT: vmv2r.v v24, v20
@@ -1336,48 +1337,47 @@ define {<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmv.v.i v18, 0
; CHECK-NEXT: srli a0, a1, 2
; CHECK-NEXT: sub a2, a1, a0
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v30, v16, 1, v0
-; CHECK-NEXT: srli a1, a1, 1
+; CHECK-NEXT: vmerge.vim v30, v18, 1, v0
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v8, a2
+; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v22, v18, 1, v0
+; CHECK-NEXT: srli a1, a1, 1
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v9, a1
-; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v28, v16, 1, v0
-; CHECK-NEXT: addi a3, sp, 16
+; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v28, v18, 1, v0
+; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v8, a1
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v20, v18, 1, v0
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
-; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; CHECK-NEXT: vmerge.vim v24, v18, 1, v0
+; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v9, a0
-; CHECK-NEXT: vsetvli a4, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v26, v16, 1, v0
-; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a2
+; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v26, v18, 1, v0
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v24, (a3)
-; CHECK-NEXT: vsetvli a4, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v14, v16, 1, v0
-; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v0, v8, a1
-; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v12, v16, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v10, v8, a0
+; CHECK-NEXT: vmerge.vim v16, v18, 1, v0
+; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v0, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmerge.vim v10, v16, 1, v0
-; CHECK-NEXT: vs8r.v v8, (a2)
+; CHECK-NEXT: vmerge.vim v18, v18, 1, v0
+; CHECK-NEXT: vs8r.v v16, (a2)
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; CHECK-NEXT: vlseg8e8.v v18, (a3)
+; CHECK-NEXT: vlseg8e8.v v18, (a1)
; CHECK-NEXT: vlseg8e8.v v10, (a2)
; CHECK-NEXT: vmv2r.v v8, v18
; CHECK-NEXT: vmv2r.v v26, v20
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
index fdf5a42f93502..c2d053b736305 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll
@@ -10,13 +10,13 @@ define void @vector_interleave_store_nxv32i1_nxv16i1(<vscale x 16 x i1> %a, <vsc
; CHECK-LABEL: vector_interleave_store_nxv32i1_nxv16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmv1r.v v9, v0
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: li a1, -1
+; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v8
-; CHECK-NEXT: vmerge.vim v12, v10, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v14, v10, 1, v0
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v12, v8, 1, v0
+; CHECK-NEXT: li a1, -1
+; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vim v14, v8, 1, v0
; CHECK-NEXT: vwaddu.vv v8, v14, v12
; CHECK-NEXT: vwmaccu.vx v8, a1, v12
; CHECK-NEXT: csrr a1, vlenb
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
index dabdde5e64615..84558183dbf64 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
@@ -13,13 +13,13 @@ define <vscale x 32 x i1> @vector_interleave_nxv32i1_nxv16i1(<vscale x 16 x i1>
; V-LABEL: vector_interleave_nxv32i1_nxv16i1:
; V: # %bb.0:
; V-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; V-NEXT: vmv1r.v v9, v0
-; V-NEXT: vmv.v.i v10, 0
-; V-NEXT: li a0, -1
+; V-NEXT: vmv1r.v v10, v0
; V-NEXT: vmv1r.v v0, v8
-; V-NEXT: vmerge.vim v12, v10, 1, v0
-; V-NEXT: vmv1r.v v0, v9
-; V-NEXT: vmerge.vim v14, v10, 1, v0
+; V-NEXT: vmv.v.i v8, 0
+; V-NEXT: vmerge.vim v12, v8, 1, v0
+; V-NEXT: li a0, -1
+; V-NEXT: vmv1r.v v0, v10
+; V-NEXT: vmerge.vim v14, v8, 1, v0
; V-NEXT: vwaddu.vv v8, v14, v12
; V-NEXT: vwmaccu.vx v8, a0, v12
; V-NEXT: csrr a0, vlenb
@@ -34,10 +34,10 @@ define <vscale x 32 x i1> @vector_interleave_nxv32i1_nxv16i1(<vscale x 16 x i1>
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, mu
; ZVBB-NEXT: vmv1r.v v14, v0
-; ZVBB-NEXT: vmv.v.i v10, 0
-; ZVBB-NEXT: li a0, 1
; ZVBB-NEXT: vmv1r.v v0, v8
-; ZVBB-NEXT: vmerge.vim v12, v10, 1, v0
+; ZVBB-NEXT: vmv.v.i v8, 0
+; ZVBB-NEXT: vmerge.vim v12, v8, 1, v0
+; ZVBB-NEXT: li a0, 1
; ZVBB-NEXT: vwsll.vi v8, v12, 8
; ZVBB-NEXT: vmv1r.v v0, v14
; ZVBB-NEXT: vwaddu.wx v8, v8, a0, v0.t
@@ -52,13 +52,13 @@ define <vscale x 32 x i1> @vector_interleave_nxv32i1_nxv16i1(<vscale x 16 x i1>
; ZIP-LABEL: vector_interleave_nxv32i1_nxv16i1:
; ZIP: # %bb.0:
; ZIP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; ZIP-NEXT: vmv1r.v v9, v0
-; ZIP-NEXT: vmv.v.i v12, 0
-; ZIP-NEXT: csrr a0, vlenb
+; ZIP-NEXT: vmv1r.v v12, v0
; ZIP-NEXT: vmv1r.v v0, v8
-; ZIP-NEXT: vmerge.vim v10, v12, 1, v0
-; ZIP-NEXT: vmv1r.v v0, v9
-; ZIP-NEXT: vmerge.vim v8, v12, 1, v0
+; ZIP-NEXT: vmv.v.i v8, 0
+; ZIP-NEXT: vmerge.vim v10, v8, 1, v0
+; ZIP-NEXT: csrr a0, vlenb
+; ZIP-NEXT: vmv1r.v v0, v12
+; ZIP-NEXT: vmerge.vim v8, v8, 1, v0
; ZIP-NEXT: ri.vzip2b.vv v12, v8, v10
; ZIP-NEXT: ri.vzip2a.vv v14, v8, v10
; ZIP-NEXT: vmsne.vi v8, v12, 0
@@ -217,21 +217,21 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv64i1(<vscale x 64 x i1
; V: # %bb.0:
; V-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; V-NEXT: vmv1r.v v24, v0
-; V-NEXT: vmv.v.i v16, 0
-; V-NEXT: li a0, -1
; V-NEXT: vmv1r.v v0, v8
+; V-NEXT: vmv.v.i v16, 0
; V-NEXT: vmerge.vim v8, v16, 1, v0
+; V-NEXT: li a0, -1
; V-NEXT: vmv1r.v v0, v24
-; V-NEXT: vmerge.vim v16, v16, 1, v0
+; V-NEXT: vmerge.vim v24, v16, 1, v0
; V-NEXT: vsetvli a1, zero, e8, m4, ta, ma
-; V-NEXT: vwaddu.vv v24, v16, v8
-; V-NEXT: vmv4r.v v4, v20
-; V-NEXT: vwaddu.vv v16, v4, v12
-; V-NEXT: vwmaccu.vx v24, a0, v8
-; V-NEXT: vwmaccu.vx v16, a0, v12
+; V-NEXT: vwaddu.vv v16, v24, v8
+; V-NEXT: vwaddu.vv v0, v28, v12
+; V-NEXT: vwmaccu.vx v16, a0, v8
+; V-NEXT: vwmaccu.vx v0, a0, v12
; V-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; V-NEXT: vmsne.vi v0, v24, 0
-; V-NEXT: vmsne.vi v8, v16, 0
+; V-NEXT: vmsne.vi v9, v16, 0
+; V-NEXT: vmsne.vi v8, v0, 0
+; V-NEXT: vmv1r.v v0, v9
; V-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv128i1_nxv64i1:
@@ -257,8 +257,8 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv64i1(<vscale x 64 x i1
; ZIP: # %bb.0:
; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZIP-NEXT: vmv1r.v v24, v0
-; ZIP-NEXT: vmv.v.i v16, 0
; ZIP-NEXT: vmv1r.v v0, v8
+; ZIP-NEXT: vmv.v.i v16, 0
; ZIP-NEXT: vmerge.vim v8, v16, 1, v0
; ZIP-NEXT: vmv1r.v v0, v24
; ZIP-NEXT: vmerge.vim v16, v16, 1, v0
@@ -495,11 +495,11 @@ define <vscale x 48 x i1> @vector_interleave_nxv48i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmv.v.i v14, 0
; CHECK-NEXT: vmerge.vim v12, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vim v10, v14, 1, v0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a2, a1, 1
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmerge.vim v10, v14, 1, v0
; CHECK-NEXT: add a3, a0, a2
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmerge.vim v14, v14, 1, v0
@@ -536,11 +536,11 @@ define <vscale x 48 x i1> @vector_interleave_nxv48i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: vmv1r.v v0, v8
; ZVBB-NEXT: vmv.v.i v14, 0
; ZVBB-NEXT: vmerge.vim v12, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v10
+; ZVBB-NEXT: vmerge.vim v10, v14, 1, v0
; ZVBB-NEXT: addi a0, sp, 16
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: slli a2, a1, 1
-; ZVBB-NEXT: vmv1r.v v0, v10
-; ZVBB-NEXT: vmerge.vim v10, v14, 1, v0
; ZVBB-NEXT: add a3, a0, a2
; ZVBB-NEXT: vmv1r.v v0, v9
; ZVBB-NEXT: vmerge.vim v14, v14, 1, v0
@@ -794,12 +794,12 @@ define <vscale x 64 x i1> @vector_interleave_nxv64i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: vmerge.vim v14, v18, 1, v0
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmerge.vim v12, v18, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: vmerge.vim v16, v18, 1, v0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a2, a1, 1
; CHECK-NEXT: add a3, a0, a2
-; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v16, v18, 1, v0
; CHECK-NEXT: add a4, a3, a2
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vim v18, v18, 1, v0
@@ -839,12 +839,12 @@ define <vscale x 64 x i1> @vector_interleave_nxv64i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: vmerge.vim v14, v18, 1, v0
; ZVBB-NEXT: vmv1r.v v0, v11
; ZVBB-NEXT: vmerge.vim v12, v18, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v9
+; ZVBB-NEXT: vmerge.vim v16, v18, 1, v0
; ZVBB-NEXT: addi a0, sp, 16
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: slli a2, a1, 1
; ZVBB-NEXT: add a3, a0, a2
-; ZVBB-NEXT: vmv1r.v v0, v9
-; ZVBB-NEXT: vmerge.vim v16, v18, 1, v0
; ZVBB-NEXT: add a4, a3, a2
; ZVBB-NEXT: vmv1r.v v0, v10
; ZVBB-NEXT: vmerge.vim v18, v18, 1, v0
@@ -1093,12 +1093,14 @@ define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v14, 0
-; CHECK-NEXT: vmerge.vim v22, v14, 1, v0
+; CHECK-NEXT: vmerge.vim v24, v14, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vim v22, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vim v12, v14, 1, v0
-; CHECK-NEXT: vmv2r.v v16, v22
+; CHECK-NEXT: vmv4r.v v16, v24
; CHECK-NEXT: vmv1r.v v0, v9
-; CHECK-NEXT: vmerge.vim v24, v14, 1, v0
+; CHECK-NEXT: vmerge.vim v26, v14, 1, v0
; CHECK-NEXT: addi a4, sp, 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a0, 2
@@ -1106,22 +1108,20 @@ define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
; CHECK-NEXT: add a2, a4, a1
-; CHECK-NEXT: vmv1r.v v17, v12
+; CHECK-NEXT: vmv1r.v v17, v22
; CHECK-NEXT: srli a3, a1, 1
-; CHECK-NEXT: vmv1r.v v18, v24
-; CHECK-NEXT: vmv1r.v v24, v13
+; CHECK-NEXT: vmv1r.v v18, v26
+; CHECK-NEXT: vmv1r.v v26, v23
; CHECK-NEXT: add a5, a2, a1
-; CHECK-NEXT: vmv1r.v v19, v20
-; CHECK-NEXT: vmv1r.v v26, v21
+; CHECK-NEXT: vmv1r.v v19, v12
+; CHECK-NEXT: vmv1r.v v28, v13
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
; CHECK-NEXT: vsetvli a6, zero, e8, m1, ta, ma
; CHECK-NEXT: vsseg5e8.v v16, (a4)
-; CHECK-NEXT: vmv1r.v v27, v21
-; CHECK-NEXT: vsseg5e8.v v23, (a0)
+; CHECK-NEXT: vmv1r.v v29, v21
+; CHECK-NEXT: vsseg5e8.v v25, (a0)
; CHECK-NEXT: vl1r.v v8, (a5)
; CHECK-NEXT: add a5, a5, a1
; CHECK-NEXT: vl1r.v v10, (a4)
@@ -1167,12 +1167,14 @@ define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmv.v.i v14, 0
-; ZVBB-NEXT: vmerge.vim v22, v14, 1, v0
+; ZVBB-NEXT: vmerge.vim v24, v14, 1, v0
; ZVBB-NEXT: vmv1r.v v0, v8
+; ZVBB-NEXT: vmerge.vim v22, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v10
; ZVBB-NEXT: vmerge.vim v12, v14, 1, v0
-; ZVBB-NEXT: vmv2r.v v16, v22
+; ZVBB-NEXT: vmv4r.v v16, v24
; ZVBB-NEXT: vmv1r.v v0, v9
-; ZVBB-NEXT: vmerge.vim v24, v14, 1, v0
+; ZVBB-NEXT: vmerge.vim v26, v14, 1, v0
; ZVBB-NEXT: addi a4, sp, 16
; ZVBB-NEXT: csrr a0, vlenb
; ZVBB-NEXT: slli a1, a0, 2
@@ -1180,22 +1182,20 @@ define <vscale x 80 x i1> @vector_interleave_nxv80i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: add a0, sp, a0
; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: vmv1r.v v0, v10
-; ZVBB-NEXT: vmerge.vim v20, v14, 1, v0
; ZVBB-NEXT: add a2, a4, a1
-; ZVBB-NEXT: vmv1r.v v17, v12
+; ZVBB-NEXT: vmv1r.v v17, v22
; ZVBB-NEXT: srli a3, a1, 1
-; ZVBB-NEXT: vmv1r.v v18, v24
-; ZVBB-NEXT: vmv1r.v v24, v13
+; ZVBB-NEXT: vmv1r.v v18, v26
+; ZVBB-NEXT: vmv1r.v v26, v23
; ZVBB-NEXT: add a5, a2, a1
-; ZVBB-NEXT: vmv1r.v v19, v20
-; ZVBB-NEXT: vmv1r.v v26, v21
+; ZVBB-NEXT: vmv1r.v v19, v12
+; ZVBB-NEXT: vmv1r.v v28, v13
; ZVBB-NEXT: vmv1r.v v0, v11
; ZVBB-NEXT: vmerge.vim v20, v14, 1, v0
; ZVBB-NEXT: vsetvli a6, zero, e8, m1, ta, ma
; ZVBB-NEXT: vsseg5e8.v v16, (a4)
-; ZVBB-NEXT: vmv1r.v v27, v21
-; ZVBB-NEXT: vsseg5e8.v v23, (a0)
+; ZVBB-NEXT: vmv1r.v v29, v21
+; ZVBB-NEXT: vsseg5e8.v v25, (a0)
; ZVBB-NEXT: vl1r.v v8, (a5)
; ZVBB-NEXT: add a5, a5, a1
; ZVBB-NEXT: vl1r.v v10, (a4)
@@ -2312,63 +2312,62 @@ define <vscale x 96 x i1> @vector_interleave_nxv96i1_nxv16i1(<vscale x 16 x i1>
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv1r.v v13, v12
-; CHECK-NEXT: vmv1r.v v12, v11
-; CHECK-NEXT: vmv1r.v v11, v9
+; CHECK-NEXT: vmv1r.v v12, v9
; CHECK-NEXT: vmv1r.v v17, v8
; CHECK-NEXT: vmv.v.i v14, 0
; CHECK-NEXT: vmerge.vim v8, v14, 1, v0
; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmerge.vim v24, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmerge.vim v22, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v11
-; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vim v16, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v11
+; CHECK-NEXT: vmerge.vim v18, v14, 1, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a0, 6
; CHECK-NEXT: mul a1, a1, a0
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: addi a4, sp, 16
-; CHECK-NEXT: vmv1r.v v10, v23
+; CHECK-NEXT: vmv1r.v v10, v25
+; CHECK-NEXT: addi a5, sp, 16
+; CHECK-NEXT: vmv1r.v v11, v23
; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: vmv1r.v v11, v21
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: vmerge.vim v24, v14, 1, v0
; CHECK-NEXT: vmv1r.v v12, v17
; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: vmerge.vim v18, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v13, v25
+; CHECK-NEXT: vmerge.vim v20, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v13, v19
; CHECK-NEXT: add a2, a1, a0
-; CHECK-NEXT: vmv1r.v v14, v19
+; CHECK-NEXT: vmv1r.v v14, v21
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vsseg6e8.v v9, (a1)
-; CHECK-NEXT: vmv1r.v v9, v22
-; CHECK-NEXT: add a5, a4, a0
-; CHECK-NEXT: vmv1r.v v10, v20
+; CHECK-NEXT: vmv1r.v v9, v24
+; CHECK-NEXT: add a4, a5, a0
+; CHECK-NEXT: vmv1r.v v10, v22
; CHECK-NEXT: srli a3, a0, 1
; CHECK-NEXT: vmv1r.v v11, v16
-; CHECK-NEXT: add a6, a5, a0
-; CHECK-NEXT: vmv1r.v v12, v24
+; CHECK-NEXT: add a6, a4, a0
+; CHECK-NEXT: vmv1r.v v12, v18
; CHECK-NEXT: add a7, a2, a0
-; CHECK-NEXT: vmv1r.v v13, v18
-; CHECK-NEXT: vsseg6e8.v v8, (a4)
+; CHECK-NEXT: vmv1r.v v13, v20
+; CHECK-NEXT: vsseg6e8.v v8, (a5)
; CHECK-NEXT: vl1r.v v8, (a1)
; CHECK-NEXT: add a1, a6, a0
; CHECK-NEXT: vl1r.v v10, (a6)
; CHECK-NEXT: add a6, a7, a0
-; CHECK-NEXT: vl1r.v v12, (a4)
-; CHECK-NEXT: add a4, a1, a0
+; CHECK-NEXT: vl1r.v v12, (a5)
+; CHECK-NEXT: add a5, a1, a0
; CHECK-NEXT: vl1r.v v14, (a7)
; CHECK-NEXT: add a7, a6, a0
-; CHECK-NEXT: vl1r.v v16, (a4)
-; CHECK-NEXT: add a4, a4, a0
+; CHECK-NEXT: vl1r.v v16, (a5)
+; CHECK-NEXT: add a5, a5, a0
; CHECK-NEXT: vl1r.v v18, (a7)
; CHECK-NEXT: add a7, a7, a0
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vl1r.v v9, (a2)
-; CHECK-NEXT: vl1r.v v17, (a4)
+; CHECK-NEXT: vl1r.v v17, (a5)
; CHECK-NEXT: vl1r.v v11, (a1)
-; CHECK-NEXT: vl1r.v v13, (a5)
+; CHECK-NEXT: vl1r.v v13, (a4)
; CHECK-NEXT: vl1r.v v19, (a7)
; CHECK-NEXT: vl1r.v v15, (a6)
; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
@@ -2401,63 +2400,62 @@ define <vscale x 96 x i1> @vector_interleave_nxv96i1_nxv16i1(<vscale x 16 x i1>
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmv1r.v v13, v12
-; ZVBB-NEXT: vmv1r.v v12, v11
-; ZVBB-NEXT: vmv1r.v v11, v9
+; ZVBB-NEXT: vmv1r.v v12, v9
; ZVBB-NEXT: vmv1r.v v17, v8
; ZVBB-NEXT: vmv.v.i v14, 0
; ZVBB-NEXT: vmerge.vim v8, v14, 1, v0
; ZVBB-NEXT: vmv1r.v v0, v17
+; ZVBB-NEXT: vmerge.vim v24, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v12
; ZVBB-NEXT: vmerge.vim v22, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v11
-; ZVBB-NEXT: vmerge.vim v20, v14, 1, v0
; ZVBB-NEXT: vmv1r.v v0, v10
; ZVBB-NEXT: vmerge.vim v16, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v11
+; ZVBB-NEXT: vmerge.vim v18, v14, 1, v0
; ZVBB-NEXT: csrr a1, vlenb
; ZVBB-NEXT: li a0, 6
; ZVBB-NEXT: mul a1, a1, a0
; ZVBB-NEXT: add a1, sp, a1
; ZVBB-NEXT: addi a1, a1, 16
-; ZVBB-NEXT: addi a4, sp, 16
-; ZVBB-NEXT: vmv1r.v v10, v23
+; ZVBB-NEXT: vmv1r.v v10, v25
+; ZVBB-NEXT: addi a5, sp, 16
+; ZVBB-NEXT: vmv1r.v v11, v23
; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: vmv1r.v v11, v21
-; ZVBB-NEXT: vmv1r.v v0, v12
-; ZVBB-NEXT: vmerge.vim v24, v14, 1, v0
; ZVBB-NEXT: vmv1r.v v12, v17
; ZVBB-NEXT: vmv1r.v v0, v13
-; ZVBB-NEXT: vmerge.vim v18, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v13, v25
+; ZVBB-NEXT: vmerge.vim v20, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v13, v19
; ZVBB-NEXT: add a2, a1, a0
-; ZVBB-NEXT: vmv1r.v v14, v19
+; ZVBB-NEXT: vmv1r.v v14, v21
; ZVBB-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; ZVBB-NEXT: vsseg6e8.v v9, (a1)
-; ZVBB-NEXT: vmv1r.v v9, v22
-; ZVBB-NEXT: add a5, a4, a0
-; ZVBB-NEXT: vmv1r.v v10, v20
+; ZVBB-NEXT: vmv1r.v v9, v24
+; ZVBB-NEXT: add a4, a5, a0
+; ZVBB-NEXT: vmv1r.v v10, v22
; ZVBB-NEXT: srli a3, a0, 1
; ZVBB-NEXT: vmv1r.v v11, v16
-; ZVBB-NEXT: add a6, a5, a0
-; ZVBB-NEXT: vmv1r.v v12, v24
+; ZVBB-NEXT: add a6, a4, a0
+; ZVBB-NEXT: vmv1r.v v12, v18
; ZVBB-NEXT: add a7, a2, a0
-; ZVBB-NEXT: vmv1r.v v13, v18
-; ZVBB-NEXT: vsseg6e8.v v8, (a4)
+; ZVBB-NEXT: vmv1r.v v13, v20
+; ZVBB-NEXT: vsseg6e8.v v8, (a5)
; ZVBB-NEXT: vl1r.v v8, (a1)
; ZVBB-NEXT: add a1, a6, a0
; ZVBB-NEXT: vl1r.v v10, (a6)
; ZVBB-NEXT: add a6, a7, a0
-; ZVBB-NEXT: vl1r.v v12, (a4)
-; ZVBB-NEXT: add a4, a1, a0
+; ZVBB-NEXT: vl1r.v v12, (a5)
+; ZVBB-NEXT: add a5, a1, a0
; ZVBB-NEXT: vl1r.v v14, (a7)
; ZVBB-NEXT: add a7, a6, a0
-; ZVBB-NEXT: vl1r.v v16, (a4)
-; ZVBB-NEXT: add a4, a4, a0
+; ZVBB-NEXT: vl1r.v v16, (a5)
+; ZVBB-NEXT: add a5, a5, a0
; ZVBB-NEXT: vl1r.v v18, (a7)
; ZVBB-NEXT: add a7, a7, a0
; ZVBB-NEXT: srli a0, a0, 2
; ZVBB-NEXT: vl1r.v v9, (a2)
-; ZVBB-NEXT: vl1r.v v17, (a4)
+; ZVBB-NEXT: vl1r.v v17, (a5)
; ZVBB-NEXT: vl1r.v v11, (a1)
-; ZVBB-NEXT: vl1r.v v13, (a5)
+; ZVBB-NEXT: vl1r.v v13, (a4)
; ZVBB-NEXT: vl1r.v v19, (a7)
; ZVBB-NEXT: vl1r.v v15, (a6)
; ZVBB-NEXT: vsetvli a1, zero, e8, m2, ta, ma
@@ -3666,22 +3664,23 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv1r.v v23, v13
-; CHECK-NEXT: vmv1r.v v28, v12
-; CHECK-NEXT: vmv1r.v v12, v11
+; CHECK-NEXT: vmv1r.v v13, v11
; CHECK-NEXT: vmv1r.v v11, v9
-; CHECK-NEXT: vmv1r.v v13, v8
+; CHECK-NEXT: vmv1r.v v17, v8
; CHECK-NEXT: vmv.v.i v14, 0
; CHECK-NEXT: vmerge.vim v8, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v0, v13
-; CHECK-NEXT: vmerge.vim v26, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v17
+; CHECK-NEXT: vmerge.vim v28, v14, 1, v0
; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vmerge.vim v26, v14, 1, v0
+; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmerge.vim v24, v14, 1, v0
; CHECK-NEXT: vmv4r.v v16, v8
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vmerge.vim v10, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v17, v26
+; CHECK-NEXT: vmv1r.v v17, v28
; CHECK-NEXT: vmv1r.v v18, v10
-; CHECK-NEXT: vmv1r.v v0, v12
+; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: vmerge.vim v12, v14, 1, v0
; CHECK-NEXT: addi a3, sp, 16
; CHECK-NEXT: csrr a0, vlenb
@@ -3690,19 +3689,17 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vmv1r.v v0, v28
-; CHECK-NEXT: vmerge.vim v28, v14, 1, v0
; CHECK-NEXT: add a2, a3, a1
-; CHECK-NEXT: vmv1r.v v19, v24
+; CHECK-NEXT: vmv1r.v v19, v26
; CHECK-NEXT: add a4, a2, a1
; CHECK-NEXT: vmv1r.v v20, v12
-; CHECK-NEXT: vmv1r.v v10, v27
+; CHECK-NEXT: vmv1r.v v10, v29
; CHECK-NEXT: add a5, a4, a1
-; CHECK-NEXT: vmv1r.v v21, v28
-; CHECK-NEXT: vmv1r.v v12, v25
+; CHECK-NEXT: vmv1r.v v21, v24
+; CHECK-NEXT: vmv1r.v v12, v27
; CHECK-NEXT: vmv1r.v v0, v23
; CHECK-NEXT: vmerge.vim v22, v14, 1, v0
-; CHECK-NEXT: vmv1r.v v14, v29
+; CHECK-NEXT: vmv1r.v v14, v25
; CHECK-NEXT: vsetvli a6, zero, e8, m1, ta, ma
; CHECK-NEXT: vsseg7e8.v v16, (a3)
; CHECK-NEXT: vmv1r.v v15, v23
@@ -3763,22 +3760,23 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; ZVBB-NEXT: sub sp, sp, a0
; ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; ZVBB-NEXT: vmv1r.v v23, v13
-; ZVBB-NEXT: vmv1r.v v28, v12
-; ZVBB-NEXT: vmv1r.v v12, v11
+; ZVBB-NEXT: vmv1r.v v13, v11
; ZVBB-NEXT: vmv1r.v v11, v9
-; ZVBB-NEXT: vmv1r.v v13, v8
+; ZVBB-NEXT: vmv1r.v v17, v8
; ZVBB-NEXT: vmv.v.i v14, 0
; ZVBB-NEXT: vmerge.vim v8, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v0, v13
-; ZVBB-NEXT: vmerge.vim v26, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v17
+; ZVBB-NEXT: vmerge.vim v28, v14, 1, v0
; ZVBB-NEXT: vmv1r.v v0, v10
+; ZVBB-NEXT: vmerge.vim v26, v14, 1, v0
+; ZVBB-NEXT: vmv1r.v v0, v12
; ZVBB-NEXT: vmerge.vim v24, v14, 1, v0
; ZVBB-NEXT: vmv4r.v v16, v8
; ZVBB-NEXT: vmv1r.v v0, v11
; ZVBB-NEXT: vmerge.vim v10, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v17, v26
+; ZVBB-NEXT: vmv1r.v v17, v28
; ZVBB-NEXT: vmv1r.v v18, v10
-; ZVBB-NEXT: vmv1r.v v0, v12
+; ZVBB-NEXT: vmv1r.v v0, v13
; ZVBB-NEXT: vmerge.vim v12, v14, 1, v0
; ZVBB-NEXT: addi a3, sp, 16
; ZVBB-NEXT: csrr a0, vlenb
@@ -3787,19 +3785,17 @@ define <vscale x 112 x i1> @vector_interleave_nxv112i1_nxv16i1(<vscale x 16 x i1
; ZVBB-NEXT: add a0, sp, a0
; ZVBB-NEXT: addi a0, a0, 16
; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: vmv1r.v v0, v28
-; ZVBB-NEXT: vmerge.vim v28, v14, 1, v0
; ZVBB-NEXT: add a2, a3, a1
-; ZVBB-NEXT: vmv1r.v v19, v24
+; ZVBB-NEXT: vmv1r.v v19, v26
; ZVBB-NEXT: add a4, a2, a1
; ZVBB-NEXT: vmv1r.v v20, v12
-; ZVBB-NEXT: vmv1r.v v10, v27
+; ZVBB-NEXT: vmv1r.v v10, v29
; ZVBB-NEXT: add a5, a4, a1
-; ZVBB-NEXT: vmv1r.v v21, v28
-; ZVBB-NEXT: vmv1r.v v12, v25
+; ZVBB-NEXT: vmv1r.v v21, v24
+; ZVBB-NEXT: vmv1r.v v12, v27
; ZVBB-NEXT: vmv1r.v v0, v23
; ZVBB-NEXT: vmerge.vim v22, v14, 1, v0
-; ZVBB-NEXT: vmv1r.v v14, v29
+; ZVBB-NEXT: vmv1r.v v14, v25
; ZVBB-NEXT: vsetvli a6, zero, e8, m1, ta, ma
; ZVBB-NEXT: vsseg7e8.v v16, (a3)
; ZVBB-NEXT: vmv1r.v v15, v23
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
index b619a4d5a2eba..168b9470f3e83 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
@@ -14,13 +14,13 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_negone(<vscale x 1 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv1i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 3
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
@@ -32,13 +32,13 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_negone(<vscale x 1 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv1i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: srli a0, a0, 3
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
@@ -56,13 +56,13 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_max(<vscale x 1 x i1> %a, <vscale
; NOVLDEP-LABEL: splice_nxv1i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 3
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 1
; NOVLDEP-NEXT: addi a0, a0, -1
@@ -74,13 +74,13 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_max(<vscale x 1 x i1> %a, <vscale
; VLDEP-LABEL: splice_nxv1i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: srli a0, a0, 3
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
@@ -98,13 +98,13 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_negone(<vscale x 2 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv2i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 2
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
@@ -116,13 +116,13 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_negone(<vscale x 2 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv2i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: srli a0, a0, 2
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
@@ -140,13 +140,13 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_max(<vscale x 2 x i1> %a, <vscale
; NOVLDEP-LABEL: splice_nxv2i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 2
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 3
; NOVLDEP-NEXT: addi a0, a0, -3
@@ -158,13 +158,13 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_max(<vscale x 2 x i1> %a, <vscale
; VLDEP-LABEL: splice_nxv2i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: srli a0, a0, 2
; VLDEP-NEXT: addi a0, a0, -3
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
@@ -182,13 +182,13 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_negone(<vscale x 4 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv4i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 1
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
@@ -200,13 +200,13 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_negone(<vscale x 4 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv4i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: srli a0, a0, 1
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
@@ -224,13 +224,13 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_max(<vscale x 4 x i1> %a, <vscale
; NOVLDEP-LABEL: splice_nxv4i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: srli a0, a0, 1
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 7
; NOVLDEP-NEXT: addi a0, a0, -7
@@ -242,13 +242,13 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_max(<vscale x 4 x i1> %a, <vscale
; VLDEP-LABEL: splice_nxv4i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: srli a0, a0, 1
; VLDEP-NEXT: addi a0, a0, -7
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
@@ -266,13 +266,13 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_negone(<vscale x 8 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv8i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
; NOVLDEP-NEXT: vslideup.vi v8, v9, 1
@@ -283,13 +283,13 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_negone(<vscale x 8 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv8i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; VLDEP-NEXT: vslidedown.vx v8, v8, a0
@@ -306,13 +306,13 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_max(<vscale x 8 x i1> %a, <vscale
; NOVLDEP-LABEL: splice_nxv8i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v11, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v10, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v11
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v10
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 15
; NOVLDEP-NEXT: addi a0, a0, -15
; NOVLDEP-NEXT: vslideup.vx v8, v9, a0
@@ -323,13 +323,13 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_max(<vscale x 8 x i1> %a, <vscale
; VLDEP-LABEL: splice_nxv8i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m1, ta, ma
-; VLDEP-NEXT: vmv1r.v v11, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v10, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v9, v10, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v11
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v9, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v10
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: addi a0, a0, -15
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; VLDEP-NEXT: vslidedown.vi v8, v8, 15
@@ -346,13 +346,13 @@ define <vscale x 16 x i1> @splice_nxv16i1_offset_negone(<vscale x 16 x i1> %a, <
; NOVLDEP-LABEL: splice_nxv16i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv.v.i v12, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v12, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v10, v12, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v12
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: slli a0, a0, 1
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
@@ -364,13 +364,13 @@ define <vscale x 16 x i1> @splice_nxv16i1_offset_negone(<vscale x 16 x i1> %a, <
; VLDEP-LABEL: splice_nxv16i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv.v.i v12, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v12, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v10, v12, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v12
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: slli a0, a0, 1
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, m2, ta, ma
@@ -388,13 +388,13 @@ define <vscale x 16 x i1> @splice_nxv16i1_offset_max(<vscale x 16 x i1> %a, <vsc
; NOVLDEP-LABEL: splice_nxv16i1_offset_max:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv.v.i v12, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v12, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v10, v12, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v12
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: slli a0, a0, 1
; NOVLDEP-NEXT: vslidedown.vi v8, v8, 31
; NOVLDEP-NEXT: addi a0, a0, -31
@@ -406,13 +406,13 @@ define <vscale x 16 x i1> @splice_nxv16i1_offset_max(<vscale x 16 x i1> %a, <vsc
; VLDEP-LABEL: splice_nxv16i1_offset_max:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m2, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv.v.i v12, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v12, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v10, v12, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v10, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v12
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: slli a0, a0, 1
; VLDEP-NEXT: addi a0, a0, -31
; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
@@ -430,13 +430,13 @@ define <vscale x 32 x i1> @splice_nxv32i1_offset_negone(<vscale x 32 x i1> %a, <
; NOVLDEP-LABEL: splice_nxv32i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv.v.i v16, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v16, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v12, v16, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v12, v8, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v16
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: slli a0, a0, 2
; NOVLDEP-NEXT: addi a0, a0, -1
; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
@@ -448,13 +448,13 @@ define <vscale x 32 x i1> @splice_nxv32i1_offset_negone(<vscale x 32 x i1> %a, <
; VLDEP-LABEL: splice_nxv32i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv.v.i v16, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v16, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v12, v16, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v12, v8, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v16
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: slli a0, a0, 2
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, m4, ta, ma
@@ -473,8 +473,8 @@ define <vscale x 32 x i1> @splice_nxv32i1_offset_max(<vscale x 32 x i1> %a, <vsc
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v16, 0
-; NOVLDEP-NEXT: li a0, 63
; NOVLDEP-NEXT: vmerge.vim v12, v16, 1, v0
+; NOVLDEP-NEXT: li a0, 63
; NOVLDEP-NEXT: vslidedown.vx v12, v12, a0
; NOVLDEP-NEXT: csrr a0, vlenb
; NOVLDEP-NEXT: vmv1r.v v0, v8
@@ -490,9 +490,9 @@ define <vscale x 32 x i1> @splice_nxv32i1_offset_max(<vscale x 32 x i1> %a, <vsc
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; VLDEP-NEXT: vmv.v.i v16, 0
+; VLDEP-NEXT: vmerge.vim v12, v16, 1, v0
; VLDEP-NEXT: csrr a0, vlenb
; VLDEP-NEXT: li a1, 63
-; VLDEP-NEXT: vmerge.vim v12, v16, 1, v0
; VLDEP-NEXT: slli a0, a0, 2
; VLDEP-NEXT: addi a0, a0, -63
; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
@@ -512,38 +512,38 @@ define <vscale x 64 x i1> @splice_nxv64i1_offset_negone(<vscale x 64 x i1> %a, <
; NOVLDEP-LABEL: splice_nxv64i1_offset_negone:
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; NOVLDEP-NEXT: vmv1r.v v9, v0
-; NOVLDEP-NEXT: vmv.v.i v24, 0
-; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v24, v0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v16, v24, 1, v0
-; NOVLDEP-NEXT: vmv1r.v v0, v9
-; NOVLDEP-NEXT: vmerge.vim v8, v24, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v16, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; NOVLDEP-NEXT: csrr a0, vlenb
+; NOVLDEP-NEXT: vmv1r.v v0, v24
+; NOVLDEP-NEXT: vmerge.vim v16, v16, 1, v0
; NOVLDEP-NEXT: slli a0, a0, 3
; NOVLDEP-NEXT: addi a0, a0, -1
-; NOVLDEP-NEXT: vslidedown.vx v8, v8, a0
-; NOVLDEP-NEXT: vslideup.vi v8, v16, 1
-; NOVLDEP-NEXT: vand.vi v8, v8, 1
+; NOVLDEP-NEXT: vslidedown.vx v16, v16, a0
+; NOVLDEP-NEXT: vslideup.vi v16, v8, 1
+; NOVLDEP-NEXT: vand.vi v8, v16, 1
; NOVLDEP-NEXT: vmsne.vi v0, v8, 0
; NOVLDEP-NEXT: ret
;
; VLDEP-LABEL: splice_nxv64i1_offset_negone:
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; VLDEP-NEXT: vmv1r.v v9, v0
-; VLDEP-NEXT: vmv.v.i v24, 0
-; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v24, v0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v16, v24, 1, v0
-; VLDEP-NEXT: vmv1r.v v0, v9
-; VLDEP-NEXT: vmerge.vim v8, v24, 1, v0
+; VLDEP-NEXT: vmv.v.i v16, 0
+; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; VLDEP-NEXT: csrr a0, vlenb
+; VLDEP-NEXT: vmv1r.v v0, v24
+; VLDEP-NEXT: vmerge.vim v16, v16, 1, v0
; VLDEP-NEXT: slli a0, a0, 3
; VLDEP-NEXT: addi a0, a0, -1
; VLDEP-NEXT: vsetivli zero, 1, e8, m8, ta, ma
-; VLDEP-NEXT: vslidedown.vx v8, v8, a0
+; VLDEP-NEXT: vslidedown.vx v16, v16, a0
; VLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
-; VLDEP-NEXT: vslideup.vi v8, v16, 1
-; VLDEP-NEXT: vand.vi v8, v8, 1
+; VLDEP-NEXT: vslideup.vi v16, v8, 1
+; VLDEP-NEXT: vand.vi v8, v16, 1
; VLDEP-NEXT: vmsne.vi v0, v8, 0
; VLDEP-NEXT: ret
%res = call <vscale x 64 x i1> @llvm.vector.splice.nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b, i32 -1)
@@ -555,8 +555,8 @@ define <vscale x 64 x i1> @splice_nxv64i1_offset_max(<vscale x 64 x i1> %a, <vsc
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v24, 0
-; NOVLDEP-NEXT: li a0, 127
; NOVLDEP-NEXT: vmerge.vim v16, v24, 1, v0
+; NOVLDEP-NEXT: li a0, 127
; NOVLDEP-NEXT: vslidedown.vx v16, v16, a0
; NOVLDEP-NEXT: csrr a0, vlenb
; NOVLDEP-NEXT: vmv1r.v v0, v8
@@ -572,9 +572,9 @@ define <vscale x 64 x i1> @splice_nxv64i1_offset_max(<vscale x 64 x i1> %a, <vsc
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; VLDEP-NEXT: vmv.v.i v24, 0
+; VLDEP-NEXT: vmerge.vim v16, v24, 1, v0
; VLDEP-NEXT: csrr a0, vlenb
; VLDEP-NEXT: li a1, 127
-; VLDEP-NEXT: vmerge.vim v16, v24, 1, v0
; VLDEP-NEXT: slli a0, a0, 3
; VLDEP-NEXT: addi a0, a0, -127
; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
index 00cfcde16969f..1155e95c09ee1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll
@@ -746,14 +746,14 @@ define <vscale x 16 x double> @vfabs_vv_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-LABEL: vfabs_vv_nxv16f64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vfabs.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB44_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
index 16de0a036d65e..b83bebb87182a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
@@ -933,22 +933,22 @@ define <vscale x 32 x bfloat> @vfadd_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; ZVFH-NEXT: slli a1, a2, 1
; ZVFH-NEXT: srli a2, a2, 2
; ZVFH-NEXT: sub a3, a0, a1
+; ZVFH-NEXT: sltu a4, a0, a3
+; ZVFH-NEXT: addi a4, a4, -1
+; ZVFH-NEXT: and a3, a4, a3
; ZVFH-NEXT: csrr a4, vlenb
; ZVFH-NEXT: slli a4, a4, 4
; ZVFH-NEXT: add a4, sp, a4
; ZVFH-NEXT: addi a4, a4, 16
; ZVFH-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFH-NEXT: vslidedown.vx v7, v0, a2
-; ZVFH-NEXT: sltu a2, a0, a3
-; ZVFH-NEXT: addi a2, a2, -1
-; ZVFH-NEXT: and a2, a2, a3
; ZVFH-NEXT: vmv1r.v v0, v7
-; ZVFH-NEXT: csrr a3, vlenb
-; ZVFH-NEXT: slli a3, a3, 3
-; ZVFH-NEXT: add a3, sp, a3
-; ZVFH-NEXT: addi a3, a3, 16
-; ZVFH-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a2, a2, 3
+; ZVFH-NEXT: add a2, sp, a2
+; ZVFH-NEXT: addi a2, a2, 16
+; ZVFH-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFH-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFH-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
; ZVFH-NEXT: csrr a2, vlenb
; ZVFH-NEXT: slli a3, a2, 4
@@ -1024,22 +1024,22 @@ define <vscale x 32 x bfloat> @vfadd_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
@@ -1115,22 +1115,22 @@ define <vscale x 32 x bfloat> @vfadd_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
+; ZVFBFA-NEXT: sltu a4, a0, a3
+; ZVFBFA-NEXT: addi a4, a4, -1
+; ZVFBFA-NEXT: and a3, a4, a3
; ZVFBFA-NEXT: csrr a4, vlenb
; ZVFBFA-NEXT: slli a4, a4, 4
; ZVFBFA-NEXT: add a4, sp, a4
; ZVFBFA-NEXT: addi a4, a4, 16
; ZVFBFA-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFBFA-NEXT: vslidedown.vx v7, v0, a2
-; ZVFBFA-NEXT: sltu a2, a0, a3
-; ZVFBFA-NEXT: addi a2, a2, -1
-; ZVFBFA-NEXT: and a2, a2, a3
; ZVFBFA-NEXT: vmv1r.v v0, v7
-; ZVFBFA-NEXT: csrr a3, vlenb
-; ZVFBFA-NEXT: slli a3, a3, 3
-; ZVFBFA-NEXT: add a3, sp, a3
-; ZVFBFA-NEXT: addi a3, a3, 16
-; ZVFBFA-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFBFA-NEXT: vsetvli zero, a2, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 3
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vsetvli zero, a3, e16alt, m4, ta, ma
; ZVFBFA-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFBFA-NEXT: csrr a2, vlenb
; ZVFBFA-NEXT: slli a3, a2, 4
@@ -1474,19 +1474,19 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; ZVFH-NEXT: slli a1, a2, 1
; ZVFH-NEXT: srli a2, a2, 2
; ZVFH-NEXT: sub a3, a0, a1
+; ZVFH-NEXT: sltu a4, a0, a3
+; ZVFH-NEXT: addi a4, a4, -1
+; ZVFH-NEXT: and a3, a4, a3
; ZVFH-NEXT: vmv1r.v v7, v0
; ZVFH-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFH-NEXT: vslidedown.vx v6, v0, a2
-; ZVFH-NEXT: sltu a2, a0, a3
-; ZVFH-NEXT: addi a2, a2, -1
-; ZVFH-NEXT: and a2, a2, a3
-; ZVFH-NEXT: csrr a3, vlenb
-; ZVFH-NEXT: slli a3, a3, 3
-; ZVFH-NEXT: add a3, sp, a3
-; ZVFH-NEXT: addi a3, a3, 16
-; ZVFH-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a2, a2, 3
+; ZVFH-NEXT: add a2, sp, a2
+; ZVFH-NEXT: addi a2, a2, 16
+; ZVFH-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFH-NEXT: vmv1r.v v0, v6
-; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFH-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFH-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
; ZVFH-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; ZVFH-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -1538,19 +1538,19 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -1601,16 +1601,16 @@ define <vscale x 32 x bfloat> @vfadd_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
+; ZVFBFA-NEXT: sltu a4, a0, a3
+; ZVFBFA-NEXT: addi a4, a4, -1
+; ZVFBFA-NEXT: and a3, a4, a3
; ZVFBFA-NEXT: vmv1r.v v7, v0
; ZVFBFA-NEXT: vsetvli a4, zero, e8alt, mf2, ta, ma
; ZVFBFA-NEXT: vslidedown.vx v6, v0, a2
-; ZVFBFA-NEXT: sltu a2, a0, a3
-; ZVFBFA-NEXT: addi a2, a2, -1
-; ZVFBFA-NEXT: and a2, a2, a3
-; ZVFBFA-NEXT: addi a3, sp, 16
-; ZVFBFA-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: addi a2, sp, 16
+; ZVFBFA-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFBFA-NEXT: vmv1r.v v0, v6
-; ZVFBFA-NEXT: vsetvli zero, a2, e16alt, m4, ta, ma
+; ZVFBFA-NEXT: vsetvli zero, a3, e16alt, m4, ta, ma
; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -2730,22 +2730,22 @@ define <vscale x 32 x half> @vfadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
@@ -2821,22 +2821,22 @@ define <vscale x 32 x half> @vfadd_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
+; ZVFBFA-NEXT: sltu a4, a0, a3
+; ZVFBFA-NEXT: addi a4, a4, -1
+; ZVFBFA-NEXT: and a3, a4, a3
; ZVFBFA-NEXT: csrr a4, vlenb
; ZVFBFA-NEXT: slli a4, a4, 4
; ZVFBFA-NEXT: add a4, sp, a4
; ZVFBFA-NEXT: addi a4, a4, 16
; ZVFBFA-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFBFA-NEXT: vslidedown.vx v7, v0, a2
-; ZVFBFA-NEXT: sltu a2, a0, a3
-; ZVFBFA-NEXT: addi a2, a2, -1
-; ZVFBFA-NEXT: and a2, a2, a3
; ZVFBFA-NEXT: vmv1r.v v0, v7
-; ZVFBFA-NEXT: csrr a3, vlenb
-; ZVFBFA-NEXT: slli a3, a3, 3
-; ZVFBFA-NEXT: add a3, sp, a3
-; ZVFBFA-NEXT: addi a3, a3, 16
-; ZVFBFA-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFBFA-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 3
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFBFA-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFBFA-NEXT: csrr a2, vlenb
; ZVFBFA-NEXT: slli a3, a2, 4
@@ -3104,19 +3104,19 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -3168,19 +3168,19 @@ define <vscale x 32 x half> @vfadd_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFBFA-NEXT: slli a1, a2, 1
; ZVFBFA-NEXT: srli a2, a2, 2
; ZVFBFA-NEXT: sub a3, a0, a1
+; ZVFBFA-NEXT: sltu a4, a0, a3
+; ZVFBFA-NEXT: addi a4, a4, -1
+; ZVFBFA-NEXT: and a3, a4, a3
; ZVFBFA-NEXT: vmv1r.v v7, v0
; ZVFBFA-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFBFA-NEXT: vslidedown.vx v6, v0, a2
-; ZVFBFA-NEXT: sltu a2, a0, a3
-; ZVFBFA-NEXT: addi a2, a2, -1
-; ZVFBFA-NEXT: and a2, a2, a3
-; ZVFBFA-NEXT: csrr a3, vlenb
-; ZVFBFA-NEXT: slli a3, a3, 3
-; ZVFBFA-NEXT: add a3, sp, a3
-; ZVFBFA-NEXT: addi a3, a3, 16
-; ZVFBFA-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFBFA-NEXT: csrr a2, vlenb
+; ZVFBFA-NEXT: slli a2, a2, 3
+; ZVFBFA-NEXT: add a2, sp, a2
+; ZVFBFA-NEXT: addi a2, a2, 16
+; ZVFBFA-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFBFA-NEXT: vmv1r.v v0, v6
-; ZVFBFA-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFBFA-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFBFA-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFBFA-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFBFA-NEXT: vsetvli zero, zero, e32, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
index fb4eca7837738..f80be5de3bbfd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
@@ -372,22 +372,22 @@ define <vscale x 32 x bfloat> @vfdiv_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
; CHECK-NEXT: addi a4, a4, 16
; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vslidedown.vx v7, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a3, a2, 4
@@ -555,19 +555,19 @@ define <vscale x 32 x bfloat> @vfdiv_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v6, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -1194,22 +1194,22 @@ define <vscale x 32 x half> @vfdiv_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
@@ -1389,19 +1389,19 @@ define <vscale x 32 x half> @vfdiv_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
index 48b0bfd21bdba..c44ae411f6982 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
@@ -613,6 +613,9 @@ define <vscale x 32 x bfloat> @vfma_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vs
; CHECK-NEXT: slli a0, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a1, a0
+; CHECK-NEXT: sltu a4, a1, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 3
; CHECK-NEXT: mv a5, a4
@@ -628,21 +631,18 @@ define <vscale x 32 x bfloat> @vfma_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vs
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: sltu a2, a1, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a4, a3, 5
-; CHECK-NEXT: add a3, a4, a3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a4, a2, 5
+; CHECK-NEXT: add a2, a4, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
@@ -914,6 +914,9 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bfl
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: mv a5, a4
@@ -932,18 +935,15 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bfl
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: mv a4, a3
-; CHECK-NEXT: slli a3, a3, 1
-; CHECK-NEXT: add a3, a3, a4
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: mv a4, a2
+; CHECK-NEXT: slli a2, a2, 1
+; CHECK-NEXT: add a2, a2, a4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
@@ -954,7 +954,7 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bfl
; CHECK-NEXT: slli a2, a2, 5
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: mv a3, a2
@@ -963,12 +963,12 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bfl
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
+; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v28, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
-; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a2, vlenb
@@ -1136,6 +1136,9 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_commute(<vscale x 32 x bfloat>
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 5
; CHECK-NEXT: add a4, sp, a4
@@ -1149,21 +1152,18 @@ define <vscale x 32 x bfloat> @vfma_vf_nxv32bf16_commute(<vscale x 32 x bfloat>
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 4
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a4, a3, 5
-; CHECK-NEXT: add a3, a4, a3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 4
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a4, a2, 5
+; CHECK-NEXT: add a2, a4, a2
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v20, v0.t
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
@@ -2363,6 +2363,9 @@ define <vscale x 32 x half> @vfma_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a0, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a1, a0
+; ZVFHMIN-NEXT: sltu a4, a1, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 3
; ZVFHMIN-NEXT: mv a5, a4
@@ -2378,21 +2381,18 @@ define <vscale x 32 x half> @vfma_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a2, a1, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a4, a3, 5
-; ZVFHMIN-NEXT: add a3, a4, a3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a4, a2, 5
+; ZVFHMIN-NEXT: add a2, a4, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
@@ -2677,6 +2677,9 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16(<vscale x 32 x half> %va, half %b,
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: mv a5, a4
@@ -2695,18 +2698,15 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16(<vscale x 32 x half> %va, half %b,
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: mv a4, a3
-; ZVFHMIN-NEXT: slli a3, a3, 1
-; ZVFHMIN-NEXT: add a3, a3, a4
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a4, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
@@ -2717,7 +2717,7 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16(<vscale x 32 x half> %va, half %b,
; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -2726,12 +2726,12 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16(<vscale x 32 x half> %va, half %b,
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
@@ -2905,6 +2905,9 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_commute(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -2918,21 +2921,18 @@ define <vscale x 32 x half> @vfma_vf_nxv32f16_commute(<vscale x 32 x half> %va,
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v8, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 4
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a4, a3, 5
-; ZVFHMIN-NEXT: add a3, a4, a3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a4, a2, 5
+; ZVFHMIN-NEXT: add a2, a4, a2
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
@@ -8564,30 +8564,24 @@ define <vscale x 32 x half> @vfmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscal
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 4
-; ZVFHMIN-NEXT: add a3, a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a3, a2, 5
+; ZVFHMIN-NEXT: add a2, a3, a2
; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: slli a2, a2, 1
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: vmv8r.v v16, v8
; ZVFHMIN-NEXT: vl8re16.v v24, (a0)
; ZVFHMIN-NEXT: lui a2, 8
@@ -8596,129 +8590,79 @@ define <vscale x 32 x half> @vfmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscal
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a4, a1, a0
; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 4
-; ZVFHMIN-NEXT: mv a6, a5
-; ZVFHMIN-NEXT: slli a5, a5, 1
-; ZVFHMIN-NEXT: add a5, a5, a6
-; ZVFHMIN-NEXT: add a5, sp, a5
-; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl1r.v v8, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
-; ZVFHMIN-NEXT: sltu a3, a1, a4
-; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 4
-; ZVFHMIN-NEXT: mv a6, a5
-; ZVFHMIN-NEXT: slli a5, a5, 1
-; ZVFHMIN-NEXT: add a5, a5, a6
+; ZVFHMIN-NEXT: slli a5, a5, 5
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: sltu a2, a1, a4
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a4
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
; ZVFHMIN-NEXT: vmv4r.v v8, v24
-; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: vmv1r.v v16, v0
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: slli a2, a2, 1
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vmv1r.v v0, v16
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
-; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: add a2, sp, a2
-; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a1, a0, .LBB280_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB280_2:
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: mv a2, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a2
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 2
-; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
@@ -8726,27 +8670,22 @@ define <vscale x 32 x half> @vfmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscal
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: add a1, a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: slli a1, a0, 5
+; ZVFHMIN-NEXT: add a0, a1, a0
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -8995,6 +8934,9 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16(<vscale x 32 x half> %va, half %
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -9008,9 +8950,6 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16(<vscale x 32 x half> %va, half %
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
@@ -9175,6 +9114,9 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16_commute(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -9182,9 +9124,6 @@ define <vscale x 32 x half> @vfmsub_vf_nxv32f16_commute(<vscale x 32 x half> %va
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a3
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
@@ -9561,145 +9500,247 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a3, a2, 5
-; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a3, a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vl8re16.v v8, (a0)
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8re16.v v24, (a0)
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a4, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vxor.vx v8, v16, a2, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a0, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a4, a1, a0
; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 5
-; ZVFHMIN-NEXT: add a5, sp, a5
-; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl1r.v v24, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v7, v24, a3
-; ZVFHMIN-NEXT: sltu a3, a1, a4
-; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 5
-; ZVFHMIN-NEXT: add a5, sp, a5
-; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: csrr a5, vlenb
; ZVFHMIN-NEXT: slli a5, a5, 4
+; ZVFHMIN-NEXT: mv a6, a5
+; ZVFHMIN-NEXT: slli a5, a5, 1
+; ZVFHMIN-NEXT: add a5, a5, a6
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
+; ZVFHMIN-NEXT: sltu a2, a1, a4
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a4
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 4
+; ZVFHMIN-NEXT: mv a5, a4
+; ZVFHMIN-NEXT: slli a4, a4, 1
+; ZVFHMIN-NEXT: add a4, a4, a5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: mv a4, a3
+; ZVFHMIN-NEXT: slli a3, a3, 2
+; ZVFHMIN-NEXT: add a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vmv4r.v v8, v24
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: mv a4, a3
+; ZVFHMIN-NEXT: slli a3, a3, 2
+; ZVFHMIN-NEXT: add a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v8, v7
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: slli a2, a2, 2
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a1, a0, .LBB286_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB286_2:
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a2
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a2
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: slli a0, a0, 2
; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv.v.v v16, v8
-; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a1, a0, 5
-; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -9740,7 +9781,10 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
@@ -9767,36 +9811,57 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a5, a5, a6
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl1r.v v8, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
-; ZVFHMIN-NEXT: sltu a3, a1, a4
-; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 3
-; ZVFHMIN-NEXT: mv a6, a5
-; ZVFHMIN-NEXT: slli a5, a5, 2
-; ZVFHMIN-NEXT: add a5, a5, a6
-; ZVFHMIN-NEXT: add a5, sp, a5
-; ZVFHMIN-NEXT: addi a5, a5, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: sltu a2, a1, a4
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a4
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 3
+; ZVFHMIN-NEXT: mv a5, a4
+; ZVFHMIN-NEXT: slli a4, a4, 2
+; ZVFHMIN-NEXT: add a4, a4, a5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vmv4r.v v8, v24
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -9804,23 +9869,22 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v16, v0
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vmv1r.v v0, v16
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
@@ -9838,17 +9902,14 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a2, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a2
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
@@ -9856,16 +9917,19 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -9878,7 +9942,7 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
@@ -9890,7 +9954,7 @@ define <vscale x 32 x half> @vfnmadd_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: slli a0, a0, 3
@@ -10238,11 +10302,12 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv8r.v v16, v8
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v16, a1
+; ZVFHMIN-NEXT: vmv.v.x v8, a1
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: mv a4, a1
@@ -10250,14 +10315,14 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: add a1, a1, a4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v24, v8, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v24, v16, a2, v0.t
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
@@ -10268,32 +10333,32 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: add a1, a4, a1
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a2, v0.t
+; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vl1r.v v16, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a3
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a4, a3, 5
; ZVFHMIN-NEXT: add a3, a4, a3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a4, a3, 5
; ZVFHMIN-NEXT: add a3, a4, a3
@@ -10301,11 +10366,11 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
@@ -10316,7 +10381,6 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
-; ZVFHMIN-NEXT: vmv8r.v v24, v8
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -10330,8 +10394,8 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -10339,9 +10403,9 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -10362,7 +10426,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 4
+; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
@@ -10375,13 +10439,13 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
@@ -10401,7 +10465,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -10454,17 +10518,12 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a2, a1, 5
-; ZVFHMIN-NEXT: add a1, a2, a1
-; ZVFHMIN-NEXT: add a1, sp, a1
-; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv8r.v v24, v8
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v16, a1
+; ZVFHMIN-NEXT: vmv.v.x v8, a1
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
; ZVFHMIN-NEXT: mv a4, a1
@@ -10472,50 +10531,44 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a1, a1, a4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v24, v8, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a4, a1, 5
-; ZVFHMIN-NEXT: add a1, a4, a1
-; ZVFHMIN-NEXT: add a1, sp, a1
-; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vl1r.v v16, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a3
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a4, a3, 5
; ZVFHMIN-NEXT: add a3, a4, a3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs1r.v v16, (a3) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a4, a3, 5
; ZVFHMIN-NEXT: add a3, a4, a3
@@ -10523,11 +10576,12 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vmv8r.v v8, v24
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
@@ -10537,7 +10591,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -10551,8 +10605,8 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -10560,9 +10614,9 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -10570,7 +10624,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a0, a1, .LBB291_2
@@ -10583,7 +10637,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
@@ -10596,7 +10650,7 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
@@ -10997,6 +11051,9 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -11010,9 +11067,6 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
@@ -11197,6 +11251,9 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -11210,9 +11267,6 @@ define <vscale x 32 x half> @vfnmadd_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
@@ -11669,145 +11723,247 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vsca
; ZVFHMIN-NEXT: addi sp, sp, -16
; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a3, a2, 5
-; ZVFHMIN-NEXT: add a2, a3, a2
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: add a3, a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: sub sp, sp, a2
-; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x21, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 33 * vlenb
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x31, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 49 * vlenb
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vl8re16.v v8, (a0)
-; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
-; ZVFHMIN-NEXT: add a0, sp, a0
-; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8re16.v v24, (a0)
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a4, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vxor.vx v8, v16, a2, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vxor.vx v16, v16, a2, v0.t
; ZVFHMIN-NEXT: slli a0, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a4, a1, a0
; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 5
-; ZVFHMIN-NEXT: add a5, sp, a5
-; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl1r.v v24, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v7, v24, a3
-; ZVFHMIN-NEXT: sltu a3, a1, a4
-; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 5
-; ZVFHMIN-NEXT: add a5, sp, a5
-; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: csrr a5, vlenb
; ZVFHMIN-NEXT: slli a5, a5, 4
+; ZVFHMIN-NEXT: mv a6, a5
+; ZVFHMIN-NEXT: slli a5, a5, 1
+; ZVFHMIN-NEXT: add a5, a5, a6
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
+; ZVFHMIN-NEXT: sltu a2, a1, a4
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a4
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 4
+; ZVFHMIN-NEXT: mv a5, a4
+; ZVFHMIN-NEXT: slli a4, a4, 1
+; ZVFHMIN-NEXT: add a4, a4, a5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: mv a4, a3
+; ZVFHMIN-NEXT: slli a3, a3, 2
+; ZVFHMIN-NEXT: add a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: vmv4r.v v8, v24
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: mv a4, a3
+; ZVFHMIN-NEXT: slli a3, a3, 2
+; ZVFHMIN-NEXT: add a3, a3, a4
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v8, v7
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: slli a2, a2, 2
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v4, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v24, v16, v8, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 2
+; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24, v0.t
-; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: bltu a1, a0, .LBB298_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: .LBB298_2:
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a2
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a2, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a2
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v24, v0.t
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 2
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v8, v16, v24, v0.t
-; ZVFHMIN-NEXT: vmv.v.v v16, v8
-; ZVFHMIN-NEXT: addi a0, sp, 16
-; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a1, a0, 5
-; ZVFHMIN-NEXT: add a0, a1, a0
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: add a1, a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add sp, sp, a0
; ZVFHMIN-NEXT: .cfi_def_cfa sp, 16
; ZVFHMIN-NEXT: addi sp, sp, 16
@@ -11848,7 +12004,10 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a2) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
@@ -11875,36 +12034,57 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a5, a5, a6
; ZVFHMIN-NEXT: add a5, sp, a5
; ZVFHMIN-NEXT: addi a5, a5, 16
-; ZVFHMIN-NEXT: vl1r.v v8, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
-; ZVFHMIN-NEXT: sltu a3, a1, a4
-; ZVFHMIN-NEXT: csrr a5, vlenb
-; ZVFHMIN-NEXT: slli a5, a5, 3
-; ZVFHMIN-NEXT: mv a6, a5
-; ZVFHMIN-NEXT: slli a5, a5, 2
-; ZVFHMIN-NEXT: add a5, a5, a6
-; ZVFHMIN-NEXT: add a5, sp, a5
-; ZVFHMIN-NEXT: addi a5, a5, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a5) # vscale x 8-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a3, a3, a4
-; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: sltu a2, a1, a4
+; ZVFHMIN-NEXT: addi a2, a2, -1
+; ZVFHMIN-NEXT: and a2, a2, a4
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: slli a4, a4, 3
+; ZVFHMIN-NEXT: mv a5, a4
+; ZVFHMIN-NEXT: slli a4, a4, 2
+; ZVFHMIN-NEXT: add a4, a4, a5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vmv4r.v v8, v24
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: slli a3, a3, 5
+; ZVFHMIN-NEXT: add a3, sp, a3
+; ZVFHMIN-NEXT: addi a3, a3, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: slli a2, a2, 4
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -11912,23 +12092,22 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
-; ZVFHMIN-NEXT: vmv1r.v v16, v0
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v0, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vmv1r.v v0, v16
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v4, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: addi a2, sp, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmadd.vv v16, v24, v8, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
+; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
@@ -11946,17 +12125,14 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a2, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a2
+; ZVFHMIN-NEXT: slli a0, a0, 4
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a1, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
@@ -11964,16 +12140,19 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: slli a0, a0, 3
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24, v0.t
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -11986,7 +12165,7 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
-; ZVFHMIN-NEXT: vfmadd.vv v24, v8, v16, v0.t
+; ZVFHMIN-NEXT: vfmadd.vv v16, v8, v24, v0.t
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a0, vlenb
@@ -11998,7 +12177,7 @@ define <vscale x 32 x half> @vfnmsub_vv_nxv32f16_commuted(<vscale x 32 x half> %
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a0) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24, v0.t
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: mv a1, a0
; ZVFHMIN-NEXT: slli a0, a0, 3
@@ -12340,50 +12519,50 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: fmv.x.h a1, fa0
-; ZVFHMIN-NEXT: lui a2, 8
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v24, a1
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 3
-; ZVFHMIN-NEXT: mv a4, a1
+; ZVFHMIN-NEXT: mv a2, a1
; ZVFHMIN-NEXT: slli a1, a1, 1
-; ZVFHMIN-NEXT: add a1, a1, a4
+; ZVFHMIN-NEXT: add a1, a1, a2
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: fmv.x.h a1, fa0
+; ZVFHMIN-NEXT: lui a2, 8
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.x v24, a1
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 5
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v16, v8, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vl1r.v v24, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v24, v24, a3
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a4, a3, 5
; ZVFHMIN-NEXT: add a3, a4, a3
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
+; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a4, a3, 5
; ZVFHMIN-NEXT: add a3, a4, a3
@@ -12391,14 +12570,17 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20, v0.t
; ZVFHMIN-NEXT: addi a2, sp, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 4
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
; ZVFHMIN-NEXT: add a2, a3, a2
@@ -12414,12 +12596,9 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 5
@@ -12451,14 +12630,17 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16, v0.t
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 4
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
@@ -12471,9 +12653,6 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16(<vscale x 32 x half> %va, half
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
@@ -12535,16 +12714,24 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a1) # vscale x 8-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
; ZVFHMIN-NEXT: lui a2, 8
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v24, a1
+; ZVFHMIN-NEXT: vmv.v.x v16, a1
; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: slli a1, a1, 5
+; ZVFHMIN-NEXT: slli a1, a1, 3
+; ZVFHMIN-NEXT: mv a4, a1
+; ZVFHMIN-NEXT: slli a1, a1, 1
+; ZVFHMIN-NEXT: add a1, a1, a4
; ZVFHMIN-NEXT: add a1, sp, a1
; ZVFHMIN-NEXT: addi a1, a1, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a1, vlenb
; ZVFHMIN-NEXT: slli a1, a1, 4
; ZVFHMIN-NEXT: mv a4, a1
@@ -12554,10 +12741,13 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a1, a1, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a1) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vxor.vx v8, v8, a2, v0.t
+; ZVFHMIN-NEXT: vxor.vx v16, v8, a2, v0.t
; ZVFHMIN-NEXT: slli a1, a3, 1
; ZVFHMIN-NEXT: srli a3, a3, 2
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: mv a5, a4
@@ -12565,9 +12755,9 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a4, a4, a5
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
-; ZVFHMIN-NEXT: vl1r.v v24, (a4) # vscale x 8-byte Folded Reload
+; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; ZVFHMIN-NEXT: vslidedown.vx v24, v24, a3
+; ZVFHMIN-NEXT: vslidedown.vx v8, v8, a3
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: mv a4, a3
@@ -12575,15 +12765,12 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: add a3, a3, a4
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs1r.v v24, (a3) # vscale x 8-byte Folded Spill
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
+; ZVFHMIN-NEXT: vs1r.v v8, (a3) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v8, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
; ZVFHMIN-NEXT: mv a4, a3
@@ -12593,15 +12780,12 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a3, a3, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a3) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12, v0.t
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 3
-; ZVFHMIN-NEXT: mv a3, a2
-; ZVFHMIN-NEXT: slli a2, a2, 1
-; ZVFHMIN-NEXT: add a2, a2, a3
+; ZVFHMIN-NEXT: slli a2, a2, 5
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vl8r.v v16, (a2) # vscale x 64-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a2, a2, 3
; ZVFHMIN-NEXT: mv a3, a2
@@ -12625,7 +12809,10 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl1r.v v0, (a2) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: csrr a2, vlenb
-; ZVFHMIN-NEXT: slli a2, a2, 5
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: mv a3, a2
+; ZVFHMIN-NEXT: slli a2, a2, 1
+; ZVFHMIN-NEXT: add a2, a2, a3
; ZVFHMIN-NEXT: add a2, sp, a2
; ZVFHMIN-NEXT: addi a2, a2, 16
; ZVFHMIN-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
@@ -12682,10 +12869,7 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a0, sp, 16
; ZVFHMIN-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 3
-; ZVFHMIN-NEXT: mv a1, a0
-; ZVFHMIN-NEXT: slli a0, a0, 1
-; ZVFHMIN-NEXT: add a0, a0, a1
+; ZVFHMIN-NEXT: slli a0, a0, 5
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
@@ -12699,7 +12883,10 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_commute(<vscale x 32 x half> %v
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: csrr a0, vlenb
-; ZVFHMIN-NEXT: slli a0, a0, 5
+; ZVFHMIN-NEXT: slli a0, a0, 3
+; ZVFHMIN-NEXT: mv a1, a0
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, a0, a1
; ZVFHMIN-NEXT: add a0, sp, a0
; ZVFHMIN-NEXT: addi a0, a0, 16
; ZVFHMIN-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
@@ -13114,6 +13301,9 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v16, v24, a2, v0.t
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 3
; ZVFHMIN-NEXT: mv a5, a4
@@ -13124,9 +13314,6 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat(<vscale x 32 x half>
; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 4
; ZVFHMIN-NEXT: add a3, sp, a3
@@ -13302,6 +13489,9 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: vl1r.v v0, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vxor.vx v24, v24, a2, v0.t
; ZVFHMIN-NEXT: sub a2, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a2
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a2, a4, a2
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 5
; ZVFHMIN-NEXT: add a4, sp, a4
@@ -13309,9 +13499,6 @@ define <vscale x 32 x half> @vfnmsub_vf_nxv32f16_neg_splat_commute(<vscale x 32
; ZVFHMIN-NEXT: vl1r.v v8, (a4) # vscale x 8-byte Folded Reload
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
; ZVFHMIN-NEXT: vmv4r.v v8, v24
; ZVFHMIN-NEXT: csrr a3, vlenb
; ZVFHMIN-NEXT: slli a3, a3, 3
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
index 42dd2dd28f614..1d32049f930cc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll
@@ -182,22 +182,22 @@ define <vscale x 32 x bfloat> @vfmax_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
; CHECK-NEXT: addi a4, a4, 16
; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vslidedown.vx v7, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a3, a2, 4
@@ -585,22 +585,22 @@ define <vscale x 32 x half> @vfmax_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
index 91b9d2d4e3258..0d10760e53e2b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll
@@ -182,22 +182,22 @@ define <vscale x 32 x bfloat> @vfmin_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
; CHECK-NEXT: addi a4, a4, 16
; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vslidedown.vx v7, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a3, a2, 4
@@ -585,22 +585,22 @@ define <vscale x 32 x half> @vfmin_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
index 92127a8e2f664..b32346ffc2df3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
@@ -494,22 +494,22 @@ define <vscale x 32 x half> @vfmul_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
@@ -689,19 +689,19 @@ define <vscale x 32 x half> @vfmul_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
index 6213a190e5c12..d8e8d12e3d86c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
@@ -710,14 +710,14 @@ define <vscale x 16 x double> @vfneg_vv_nxv16f64(<vscale x 16 x double> %va, <vs
; CHECK-LABEL: vfneg_vv_nxv16f64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vfneg.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB44_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
index 622fbaade9e95..533cb96560a49 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll
@@ -86,17 +86,17 @@ define <vscale x 7 x double> @vfpext_nxv7f32_nxv7f64(<vscale x 7 x float> %a, <v
define <vscale x 32 x float> @vfpext_nxv32f16_nxv32f32(<vscale x 32 x half> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vfpext_nxv32f16_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB7_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
index 14753384b6460..2dc3ced5e3081 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
@@ -462,17 +462,17 @@ define <vscale x 2 x i64> @vfptosi_nxv2i64_nxv2f64_unmasked(<vscale x 2 x double
define <vscale x 32 x i16> @vfptosi_nxv32i16_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptosi_nxv32i16_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB34_2
; CHECK-NEXT: # %bb.1:
@@ -490,17 +490,17 @@ define <vscale x 32 x i16> @vfptosi_nxv32i16_nxv32f32(<vscale x 32 x float> %va,
define <vscale x 32 x i32> @vfptosi_nxv32i32_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptosi_nxv32i32_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB35_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
index 5073a806cc2a5..ddd67b356540b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
@@ -462,17 +462,17 @@ define <vscale x 2 x i64> @vfptoui_nxv2i64_nxv2f64_unmasked(<vscale x 2 x double
define <vscale x 32 x i16> @vfptoui_nxv32i16_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptoui_nxv32i16_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB34_2
; CHECK-NEXT: # %bb.1:
@@ -490,17 +490,17 @@ define <vscale x 32 x i16> @vfptoui_nxv32i16_nxv32f32(<vscale x 32 x float> %va,
define <vscale x 32 x i32> @vfptoui_nxv32i32_nxv32f32(<vscale x 32 x float> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptoui_nxv32i32_nxv32f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.rtz.xu.f.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB35_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
index 475707f27d7e9..359a534508522 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
@@ -87,14 +87,14 @@ define <vscale x 16 x float> @vfptrunc_nxv16f32_nxv16f64(<vscale x 16 x double>
; CHECK-LABEL: vfptrunc_nxv16f32_nxv16f64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v28, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB7_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
index 63651bd3955bb..365396a684fd7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll
@@ -710,14 +710,14 @@ define <vscale x 16 x double> @vfsqrt_vv_nxv16f64(<vscale x 16 x double> %va, <v
; CHECK-LABEL: vfsqrt_vv_nxv16f64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vfsqrt.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB44_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
index 54d42930ed724..9b7017f323bfd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
@@ -372,22 +372,22 @@ define <vscale x 32 x bfloat> @vfsub_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <v
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: slli a4, a4, 4
; CHECK-NEXT: add a4, sp, a4
; CHECK-NEXT: addi a4, a4, 16
; CHECK-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; CHECK-NEXT: vslidedown.vx v7, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
; CHECK-NEXT: vmv1r.v v0, v7
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v28, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a3, a2, 4
@@ -555,19 +555,19 @@ define <vscale x 32 x bfloat> @vfsub_vf_nxv32bf16(<vscale x 32 x bfloat> %va, bf
; CHECK-NEXT: slli a1, a2, 1
; CHECK-NEXT: srli a2, a2, 2
; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: vmv1r.v v7, v0
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v6, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: slli a3, a3, 3
-; CHECK-NEXT: add a3, sp, a3
-; CHECK-NEXT: addi a3, a3, 16
-; CHECK-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: add a2, sp, a2
+; CHECK-NEXT: addi a2, a2, 16
+; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv1r.v v0, v6
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v24, v20, v0.t
; CHECK-NEXT: vfwcvtbf16.f.f.v v16, v12, v0.t
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
@@ -1194,22 +1194,22 @@ define <vscale x 32 x half> @vfsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: csrr a4, vlenb
; ZVFHMIN-NEXT: slli a4, a4, 4
; ZVFHMIN-NEXT: add a4, sp, a4
; ZVFHMIN-NEXT: addi a4, a4, 16
; ZVFHMIN-NEXT: vs1r.v v0, (a4) # vscale x 8-byte Folded Spill
; ZVFHMIN-NEXT: vslidedown.vx v7, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
; ZVFHMIN-NEXT: vmv1r.v v0, v7
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v24, (a3) # vscale x 64-byte Folded Spill
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v24, (a2) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28, v0.t
; ZVFHMIN-NEXT: csrr a2, vlenb
; ZVFHMIN-NEXT: slli a3, a2, 4
@@ -1389,19 +1389,19 @@ define <vscale x 32 x half> @vfsub_vf_nxv32f16(<vscale x 32 x half> %va, half %b
; ZVFHMIN-NEXT: slli a1, a2, 1
; ZVFHMIN-NEXT: srli a2, a2, 2
; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vslidedown.vx v6, v0, a2
-; ZVFHMIN-NEXT: sltu a2, a0, a3
-; ZVFHMIN-NEXT: addi a2, a2, -1
-; ZVFHMIN-NEXT: and a2, a2, a3
-; ZVFHMIN-NEXT: csrr a3, vlenb
-; ZVFHMIN-NEXT: slli a3, a3, 3
-; ZVFHMIN-NEXT: add a3, sp, a3
-; ZVFHMIN-NEXT: addi a3, a3, 16
-; ZVFHMIN-NEXT: vs8r.v v16, (a3) # vscale x 64-byte Folded Spill
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a2, a2, 3
+; ZVFHMIN-NEXT: add a2, sp, a2
+; ZVFHMIN-NEXT: addi a2, a2, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; ZVFHMIN-NEXT: vmv1r.v v0, v6
-; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v20, v0.t
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12, v0.t
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
index 7944afbbbb892..719226503e7b2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll
@@ -392,18 +392,18 @@ define <vscale x 128 x i8> @vmax_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: sub a3, a2, a1
-; CHECK-NEXT: sltu a4, a2, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmax.vx v16, v16, a0, v0.t
-; CHECK-NEXT: bltu a2, a1, .LBB34_2
+; CHECK-NEXT: bltu a2, a3, .LBB34_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -928,17 +928,17 @@ define <vscale x 16 x i32> @vmax_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i
define <vscale x 32 x i32> @vmax_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vmax_vx_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: srli a3, a2, 2
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a2, a3, 1
+; CHECK-NEXT: sub a4, a1, a2
+; CHECK-NEXT: sltu a5, a1, a4
+; CHECK-NEXT: addi a5, a5, -1
+; CHECK-NEXT: and a4, a5, a4
+; CHECK-NEXT: srli a3, a3, 2
+; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: sub a3, a1, a2
-; CHECK-NEXT: sltu a4, a1, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vmax.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB80_2
; CHECK-NEXT: # %bb.1:
@@ -1001,15 +1001,15 @@ define <vscale x 32 x i32> @vmax_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i3
; RV64-LABEL: vmax_vx_nxv32i32_evl_nx8:
; RV64: # %bb.0:
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: srli a3, a1, 2
; RV64-NEXT: slli a2, a1, 1
-; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
-; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: sub a3, a1, a2
; RV64-NEXT: sltu a4, a1, a3
; RV64-NEXT: addi a4, a4, -1
; RV64-NEXT: and a3, a4, a3
+; RV64-NEXT: srli a4, a1, 2
+; RV64-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a4
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vmax.vx v16, v16, a0, v0.t
; RV64-NEXT: bltu a1, a2, .LBB82_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
index 0a3190f84c748..0acaa40ec8a16 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll
@@ -391,18 +391,18 @@ define <vscale x 128 x i8> @vmaxu_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: sub a3, a2, a1
-; CHECK-NEXT: sltu a4, a2, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmaxu.vx v16, v16, a0, v0.t
-; CHECK-NEXT: bltu a2, a1, .LBB34_2
+; CHECK-NEXT: bltu a2, a3, .LBB34_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -927,17 +927,17 @@ define <vscale x 16 x i32> @vmaxu_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vmaxu_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vmaxu_vx_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: srli a3, a2, 2
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a2, a3, 1
+; CHECK-NEXT: sub a4, a1, a2
+; CHECK-NEXT: sltu a5, a1, a4
+; CHECK-NEXT: addi a5, a5, -1
+; CHECK-NEXT: and a4, a5, a4
+; CHECK-NEXT: srli a3, a3, 2
+; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: sub a3, a1, a2
-; CHECK-NEXT: sltu a4, a1, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vmaxu.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB80_2
; CHECK-NEXT: # %bb.1:
@@ -1000,15 +1000,15 @@ define <vscale x 32 x i32> @vmaxu_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i
; RV64-LABEL: vmaxu_vx_nxv32i32_evl_nx8:
; RV64: # %bb.0:
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: srli a3, a1, 2
; RV64-NEXT: slli a2, a1, 1
-; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
-; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: sub a3, a1, a2
; RV64-NEXT: sltu a4, a1, a3
; RV64-NEXT: addi a4, a4, -1
; RV64-NEXT: and a3, a4, a3
+; RV64-NEXT: srli a4, a1, 2
+; RV64-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a4
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vmaxu.vx v16, v16, a0, v0.t
; RV64-NEXT: bltu a1, a2, .LBB82_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
index ef94044613c6a..0cb5dc152e635 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll
@@ -392,18 +392,18 @@ define <vscale x 128 x i8> @vmin_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <vs
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: sub a3, a2, a1
-; CHECK-NEXT: sltu a4, a2, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vmin.vx v16, v16, a0, v0.t
-; CHECK-NEXT: bltu a2, a1, .LBB34_2
+; CHECK-NEXT: bltu a2, a3, .LBB34_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -928,17 +928,17 @@ define <vscale x 16 x i32> @vmin_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i
define <vscale x 32 x i32> @vmin_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vmin_vx_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: srli a3, a2, 2
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a2, a3, 1
+; CHECK-NEXT: sub a4, a1, a2
+; CHECK-NEXT: sltu a5, a1, a4
+; CHECK-NEXT: addi a5, a5, -1
+; CHECK-NEXT: and a4, a5, a4
+; CHECK-NEXT: srli a3, a3, 2
+; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: sub a3, a1, a2
-; CHECK-NEXT: sltu a4, a1, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vmin.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB80_2
; CHECK-NEXT: # %bb.1:
@@ -1001,15 +1001,15 @@ define <vscale x 32 x i32> @vmin_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i3
; RV64-LABEL: vmin_vx_nxv32i32_evl_nx8:
; RV64: # %bb.0:
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: srli a3, a1, 2
; RV64-NEXT: slli a2, a1, 1
-; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
-; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: sub a3, a1, a2
; RV64-NEXT: sltu a4, a1, a3
; RV64-NEXT: addi a4, a4, -1
; RV64-NEXT: and a3, a4, a3
+; RV64-NEXT: srli a4, a1, 2
+; RV64-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a4
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vmin.vx v16, v16, a0, v0.t
; RV64-NEXT: bltu a1, a2, .LBB82_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
index 40c2375849548..56dcba4d4b347 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll
@@ -391,18 +391,18 @@ define <vscale x 128 x i8> @vminu_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <v
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: sub a3, a2, a1
-; CHECK-NEXT: sltu a4, a2, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vminu.vx v16, v16, a0, v0.t
-; CHECK-NEXT: bltu a2, a1, .LBB34_2
+; CHECK-NEXT: bltu a2, a3, .LBB34_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB34_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
@@ -927,17 +927,17 @@ define <vscale x 16 x i32> @vminu_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vminu_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vminu_vx_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: srli a3, a2, 2
-; CHECK-NEXT: slli a2, a2, 1
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a2, a3, 1
+; CHECK-NEXT: sub a4, a1, a2
+; CHECK-NEXT: sltu a5, a1, a4
+; CHECK-NEXT: addi a5, a5, -1
+; CHECK-NEXT: and a4, a5, a4
+; CHECK-NEXT: srli a3, a3, 2
+; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a3
-; CHECK-NEXT: sub a3, a1, a2
-; CHECK-NEXT: sltu a4, a1, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vminu.vx v16, v16, a0, v0.t
; CHECK-NEXT: bltu a1, a2, .LBB80_2
; CHECK-NEXT: # %bb.1:
@@ -1000,15 +1000,15 @@ define <vscale x 32 x i32> @vminu_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i
; RV64-LABEL: vminu_vx_nxv32i32_evl_nx8:
; RV64: # %bb.0:
; RV64-NEXT: csrr a1, vlenb
-; RV64-NEXT: srli a3, a1, 2
; RV64-NEXT: slli a2, a1, 1
-; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v24, v0
-; RV64-NEXT: vslidedown.vx v0, v0, a3
; RV64-NEXT: sub a3, a1, a2
; RV64-NEXT: sltu a4, a1, a3
; RV64-NEXT: addi a4, a4, -1
; RV64-NEXT: and a3, a4, a3
+; RV64-NEXT: srli a4, a1, 2
+; RV64-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmv1r.v v24, v0
+; RV64-NEXT: vslidedown.vx v0, v0, a4
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: vminu.vx v16, v16, a0, v0.t
; RV64-NEXT: bltu a1, a2, .LBB82_2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmseq.ll b/llvm/test/CodeGen/RISCV/rvv/vmseq.ll
index 4dadaaec903f4..003b7193e7873 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmseq.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmseq.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmseq.vv v10, v8, v11, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmseq.vv v11, v8, v10, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmseq_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmseq.vv v12, v8, v14, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmseq.vv v11, v8, v12, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmseq_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmseq.vv v16, v8, v20, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmseq.vv v13, v8, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsge.ll b/llvm/test/CodeGen/RISCV/rvv/vmsge.ll
index 987271cf9e3a6..e892388079303 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsge.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsge.ll
@@ -819,8 +819,8 @@ define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i8_i8_1(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: li a0, 99
; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: li a0, 99
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
@@ -1316,15 +1316,15 @@ define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsle.vv v10, v11, v8, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmsle.vv v11, v10, v8, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1379,15 +1379,15 @@ define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsle.vv v12, v14, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmsle.vv v11, v12, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1442,15 +1442,15 @@ define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsle.vv v16, v20, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmsle.vv v13, v16, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
index f4f4e884e0cdb..db06aac7cec4f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll
@@ -1278,15 +1278,15 @@ define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsleu.vv v10, v11, v8, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmsleu.vv v11, v10, v8, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1341,15 +1341,15 @@ define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsleu.vv v12, v14, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmsleu.vv v11, v12, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1404,15 +1404,15 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsleu.vv v16, v20, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmsleu.vv v13, v16, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1545,8 +1545,8 @@ define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i8_i8_1(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v10, v0
-; CHECK-NEXT: li a0, 99
; CHECK-NEXT: vmv1r.v v0, v9
+; CHECK-NEXT: li a0, 99
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
index 23d117a02505b..68f9ad8325bf4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsgt_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmslt.vv v10, v11, v8, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmslt.vv v11, v10, v8, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsgt_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmslt.vv v12, v14, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmslt.vv v11, v12, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsgt_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmslt.vv v16, v20, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmslt.vv v13, v16, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
index f546196038252..82748be39bf1d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsltu.vv v10, v11, v8, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmsltu.vv v11, v10, v8, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsltu.vv v12, v14, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmsltu.vv v11, v12, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsltu.vv v16, v20, v8, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmsltu.vv v13, v16, v8, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsle.ll b/llvm/test/CodeGen/RISCV/rvv/vmsle.ll
index 02c6e644df646..7598e87d34357 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsle.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsle.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsle_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsle.vv v10, v8, v11, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmsle.vv v11, v8, v10, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsle_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsle.vv v12, v8, v14, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmsle.vv v11, v8, v12, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsle_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsle.vv v16, v8, v20, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmsle.vv v13, v8, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
index 76989d2994749..df4db27660499 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsleu_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsleu.vv v10, v8, v11, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmsleu.vv v11, v8, v10, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsleu_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsleu.vv v12, v8, v14, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmsleu.vv v11, v8, v12, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsleu_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsleu.vv v16, v8, v20, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmsleu.vv v13, v8, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmslt.ll b/llvm/test/CodeGen/RISCV/rvv/vmslt.ll
index 6f6a07e6c02bc..3f6b8c709f700 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmslt.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmslt.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmslt_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmslt.vv v10, v8, v11, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmslt.vv v11, v8, v10, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmslt_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmslt.vv v12, v8, v14, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmslt.vv v11, v8, v12, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmslt_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmslt.vv v16, v8, v20, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmslt.vv v13, v8, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
index 82ad07fc5b9ab..f1e055cf478ee 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsltu_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsltu.vv v10, v8, v11, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmsltu.vv v11, v8, v10, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsltu_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsltu.vv v12, v8, v14, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmsltu.vv v11, v8, v12, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsltu_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsltu.vv v16, v8, v20, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmsltu.vv v13, v8, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsne.ll b/llvm/test/CodeGen/RISCV/rvv/vmsne.ll
index a485fdf4e505f..fff1815df2c8e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsne.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsne.ll
@@ -1262,15 +1262,15 @@ define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i64_i64(<vscale x 1 x i1>
; RV32-LABEL: intrinsic_vmsne_mask_vx_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
-; RV32-NEXT: vlse64.v v11, (a0), zero
-; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vmv1r.v v0, v9
-; RV32-NEXT: vmsne.vv v10, v8, v11, v0.t
-; RV32-NEXT: vmv.v.v v0, v10
+; RV32-NEXT: vmsne.vv v11, v8, v10, v0.t
+; RV32-NEXT: vmv.v.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1324,15 +1324,15 @@ define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i64_i64(<vscale x 2 x i1>
; RV32-LABEL: intrinsic_vmsne_mask_vx_nxv2i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
+; RV32-NEXT: vmv1r.v v11, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu
-; RV32-NEXT: vlse64.v v14, (a0), zero
-; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmsne.vv v12, v8, v14, v0.t
-; RV32-NEXT: vmv1r.v v0, v12
+; RV32-NEXT: vmsne.vv v11, v8, v12, v0.t
+; RV32-NEXT: vmv1r.v v0, v11
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
@@ -1386,15 +1386,15 @@ define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i64_i64(<vscale x 4 x i1>
; RV32-LABEL: intrinsic_vmsne_mask_vx_nxv4i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
+; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
+; RV32-NEXT: vmv1r.v v13, v0
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: addi a0, sp, 8
-; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu
-; RV32-NEXT: vlse64.v v20, (a0), zero
-; RV32-NEXT: vmv1r.v v16, v0
+; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vmv1r.v v0, v12
-; RV32-NEXT: vmsne.vv v16, v8, v20, v0.t
-; RV32-NEXT: vmv1r.v v0, v16
+; RV32-NEXT: vmsne.vv v13, v8, v16, v0.t
+; RV32-NEXT: vmv1r.v v0, v13
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll b/llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
index 8e8622b3d71d4..0bb0339e1ded4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-cttz-elts.ll
@@ -19,9 +19,9 @@ define iXLen @bool_vec(<vscale x 2 x i1> %src, <vscale x 2 x i1> %m, i32 %evl) {
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64-NEXT: vmv1r.v v9, v0
+; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32
-; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; RV64-NEXT: vfirst.m a1, v9, v0.t
; RV64-NEXT: bltz a1, .LBB0_2
@@ -46,9 +46,9 @@ define iXLen @bool_vec_zero_poison(<vscale x 2 x i1> %src, <vscale x 2 x i1> %m,
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; RV64-NEXT: vmv1r.v v9, v0
+; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: srli a0, a0, 32
-; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; RV64-NEXT: vfirst.m a0, v9, v0.t
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
index 3e81dcb29e559..b140166415d0e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll
@@ -6,8 +6,8 @@ define <2 x i1> @test_vp_reverse_v2i1_masked(<2 x i1> %src, <2 x i1> %mask, i32
; CHECK-LABEL: test_vp_reverse_v2i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v11, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v9, v0.t
@@ -45,8 +45,8 @@ define <4 x i1> @test_vp_reverse_v4i1_masked(<4 x i1> %src, <4 x i1> %mask, i32
; CHECK-LABEL: test_vp_reverse_v4i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v11, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vid.v v9, v0.t
@@ -84,8 +84,8 @@ define <8 x i1> @test_vp_reverse_v8i1_masked(<8 x i1> %src, <8 x i1> %mask, i32
; CHECK-LABEL: test_vp_reverse_v8i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v11, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vid.v v9, v0.t
@@ -123,8 +123,8 @@ define <16 x i1> @test_vp_reverse_v16i1_masked(<16 x i1> %src, <16 x i1> %mask,
; CHECK-LABEL: test_vp_reverse_v16i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vid.v v8, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
index 510a18d8b756f..9ab5e98ea7f3f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll
@@ -5,8 +5,8 @@ define <vscale x 1 x i1> @test_vp_reverse_nxv1i1_masked(<vscale x 1 x i1> %src,
; CHECK-LABEL: test_vp_reverse_nxv1i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v11, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v9, v0.t
@@ -44,8 +44,8 @@ define <vscale x 2 x i1> @test_vp_reverse_nxv2i1_masked(<vscale x 2 x i1> %src,
; CHECK-LABEL: test_vp_reverse_nxv2i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v11, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vid.v v9, v0.t
@@ -83,8 +83,8 @@ define <vscale x 4 x i1> @test_vp_reverse_nxv4i1_masked(<vscale x 4 x i1> %src,
; CHECK-LABEL: test_vp_reverse_nxv4i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v11, v9, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v11, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vid.v v9, v0.t
@@ -122,8 +122,8 @@ define <vscale x 8 x i1> @test_vp_reverse_nxv8i1_masked(<vscale x 8 x i1> %src,
; CHECK-LABEL: test_vp_reverse_nxv8i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vid.v v8, v0.t
@@ -161,8 +161,8 @@ define <vscale x 16 x i1> @test_vp_reverse_nxv16i1_masked(<vscale x 16 x i1> %sr
; CHECK-LABEL: test_vp_reverse_nxv16i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmerge.vim v12, v10, 1, v0
+; CHECK-NEXT: vmv.v.i v12, 0
+; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; CHECK-NEXT: vid.v v8, v0.t
@@ -201,8 +201,8 @@ define <vscale x 32 x i1> @test_vp_reverse_nxv32i1_masked(<vscale x 32 x i1> %sr
; CHECK-LABEL: test_vp_reverse_nxv32i1_masked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
-; CHECK-NEXT: vmv.v.i v12, 0
-; CHECK-NEXT: vmerge.vim v16, v12, 1, v0
+; CHECK-NEXT: vmv.v.i v16, 0
+; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
; CHECK-NEXT: vid.v v8, v0.t
@@ -243,14 +243,12 @@ define <vscale x 64 x i1> @test_vp_reverse_nxv64i1_masked(<vscale x 64 x i1> %sr
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v26, v8
; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, ma
; CHECK-NEXT: vid.v v16
-; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: addi a2, a1, -1
; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: vsetvli a3, zero, e16, m2, ta, ma
; CHECK-NEXT: vrsub.vx v24, v16, a2
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; CHECK-NEXT: vrgatherei16.vv v23, v8, v24
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
index e560b1a62197f..fc6a96d00cdc2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll
@@ -9,9 +9,9 @@ define <2 x i1> @test_vp_splice_v2i1(<2 x i1> %va, <2 x i1> %vb, i32 zeroext %ev
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -27,9 +27,9 @@ define <2 x i1> @test_vp_splice_v2i1(<2 x i1> %va, <2 x i1> %vb, i32 zeroext %ev
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -51,9 +51,9 @@ define <2 x i1> @test_vp_splice_v2i1_negative_offset(<2 x i1> %va, <2 x i1> %vb,
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -69,9 +69,9 @@ define <2 x i1> @test_vp_splice_v2i1_negative_offset(<2 x i1> %va, <2 x i1> %vb,
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -139,9 +139,9 @@ define <4 x i1> @test_vp_splice_v4i1(<4 x i1> %va, <4 x i1> %vb, i32 zeroext %ev
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -157,9 +157,9 @@ define <4 x i1> @test_vp_splice_v4i1(<4 x i1> %va, <4 x i1> %vb, i32 zeroext %ev
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -181,9 +181,9 @@ define <4 x i1> @test_vp_splice_v4i1_negative_offset(<4 x i1> %va, <4 x i1> %vb,
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -199,9 +199,9 @@ define <4 x i1> @test_vp_splice_v4i1_negative_offset(<4 x i1> %va, <4 x i1> %vb,
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -269,9 +269,9 @@ define <8 x i1> @test_vp_splice_v8i1(<8 x i1> %va, <8 x i1> %vb, i32 zeroext %ev
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -287,9 +287,9 @@ define <8 x i1> @test_vp_splice_v8i1(<8 x i1> %va, <8 x i1> %vb, i32 zeroext %ev
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -311,9 +311,9 @@ define <8 x i1> @test_vp_splice_v8i1_negative_offset(<8 x i1> %va, <8 x i1> %vb,
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -329,9 +329,9 @@ define <8 x i1> @test_vp_splice_v8i1_negative_offset(<8 x i1> %va, <8 x i1> %vb,
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -399,9 +399,9 @@ define <16 x i1> @test_vp_splice_v16i1(<16 x i1> %va, <16 x i1> %vb, i32 zeroext
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -417,9 +417,9 @@ define <16 x i1> @test_vp_splice_v16i1(<16 x i1> %va, <16 x i1> %vb, i32 zeroext
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -441,9 +441,9 @@ define <16 x i1> @test_vp_splice_v16i1_negative_offset(<16 x i1> %va, <16 x i1>
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -459,9 +459,9 @@ define <16 x i1> @test_vp_splice_v16i1_negative_offset(<16 x i1> %va, <16 x i1>
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
index 9e7379f52baf5..bd54f34554d4d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll
@@ -7,9 +7,9 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1(<vscale x 1 x i1> %va, <vscale x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -25,9 +25,9 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1(<vscale x 1 x i1> %va, <vscale x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -49,9 +49,9 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1_negative_offset(<vscale x 1 x i1
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -67,9 +67,9 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1_negative_offset(<vscale x 1 x i1
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -137,9 +137,9 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1(<vscale x 2 x i1> %va, <vscale x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -155,9 +155,9 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1(<vscale x 2 x i1> %va, <vscale x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -179,9 +179,9 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1_negative_offset(<vscale x 2 x i1
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -197,9 +197,9 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1_negative_offset(<vscale x 2 x i1
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -267,9 +267,9 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1(<vscale x 4 x i1> %va, <vscale x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -285,9 +285,9 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1(<vscale x 4 x i1> %va, <vscale x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -309,9 +309,9 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1_negative_offset(<vscale x 4 x i1
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -327,9 +327,9 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1_negative_offset(<vscale x 4 x i1
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -397,9 +397,9 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1(<vscale x 8 x i1> %va, <vscale x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -415,9 +415,9 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1(<vscale x 8 x i1> %va, <vscale x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -439,9 +439,9 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1_negative_offset(<vscale x 8 x i1
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv1r.v v10, v0
-; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; NOVLDEP-NEXT: vmv.v.i v9, 0
; NOVLDEP-NEXT: vmv1r.v v0, v10
@@ -457,9 +457,9 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1_negative_offset(<vscale x 8 x i1
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; VLDEP-NEXT: vmv1r.v v10, v0
-; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v9, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; VLDEP-NEXT: vmv.v.i v9, 0
; VLDEP-NEXT: vmv1r.v v0, v10
@@ -527,9 +527,9 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1(<vscale x 16 x i1> %va, <vscal
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v12, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v12
@@ -545,9 +545,9 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1(<vscale x 16 x i1> %va, <vscal
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; VLDEP-NEXT: vmv1r.v v12, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v12
@@ -569,9 +569,9 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1_negative_offset(<vscale x 16 x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; NOVLDEP-NEXT: vmv1r.v v12, v0
-; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; NOVLDEP-NEXT: vmv.v.i v10, 0
; NOVLDEP-NEXT: vmv1r.v v0, v12
@@ -587,9 +587,9 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1_negative_offset(<vscale x 16 x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; VLDEP-NEXT: vmv1r.v v12, v0
-; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v10, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; VLDEP-NEXT: vmv.v.i v10, 0
; VLDEP-NEXT: vmv1r.v v0, v12
@@ -659,9 +659,9 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1(<vscale x 32 x i1> %va, <vscal
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v16, v0
-; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: vmv1r.v v0, v16
@@ -677,9 +677,9 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1(<vscale x 32 x i1> %va, <vscal
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; VLDEP-NEXT: vmv1r.v v16, v0
-; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: vmv1r.v v0, v16
@@ -701,9 +701,9 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1_negative_offset(<vscale x 32 x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv1r.v v16, v0
-; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; NOVLDEP-NEXT: vmv.v.i v12, 0
; NOVLDEP-NEXT: vmv1r.v v0, v16
@@ -719,9 +719,9 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1_negative_offset(<vscale x 32 x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; VLDEP-NEXT: vmv1r.v v16, v0
-; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v12, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; VLDEP-NEXT: vmv.v.i v12, 0
; VLDEP-NEXT: vmv1r.v v0, v16
@@ -791,9 +791,9 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1(<vscale x 64 x i1> %va, <vscal
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v24, v0
-; NOVLDEP-NEXT: vmv.v.i v16, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v16, 0
; NOVLDEP-NEXT: vmv1r.v v0, v24
@@ -809,9 +809,9 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1(<vscale x 64 x i1> %va, <vscal
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; VLDEP-NEXT: vmv1r.v v24, v0
-; VLDEP-NEXT: vmv.v.i v16, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; VLDEP-NEXT: vmv.v.i v16, 0
; VLDEP-NEXT: vmv1r.v v0, v24
@@ -833,9 +833,9 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1_negative_offset(<vscale x 64 x
; NOVLDEP: # %bb.0:
; NOVLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv1r.v v24, v0
-; NOVLDEP-NEXT: vmv.v.i v16, 0
; NOVLDEP-NEXT: vmv1r.v v0, v8
-; NOVLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; NOVLDEP-NEXT: vmv.v.i v8, 0
+; NOVLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; NOVLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; NOVLDEP-NEXT: vmv.v.i v16, 0
; NOVLDEP-NEXT: vmv1r.v v0, v24
@@ -851,9 +851,9 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1_negative_offset(<vscale x 64 x
; VLDEP: # %bb.0:
; VLDEP-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; VLDEP-NEXT: vmv1r.v v24, v0
-; VLDEP-NEXT: vmv.v.i v16, 0
; VLDEP-NEXT: vmv1r.v v0, v8
-; VLDEP-NEXT: vmerge.vim v8, v16, 1, v0
+; VLDEP-NEXT: vmv.v.i v8, 0
+; VLDEP-NEXT: vmerge.vim v8, v8, 1, v0
; VLDEP-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; VLDEP-NEXT: vmv.v.i v16, 0
; VLDEP-NEXT: vmv1r.v v0, v24
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll b/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
index 77808ad541088..d569dc84ac174 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll
@@ -363,18 +363,18 @@ define i32 @masked_load_store_factor2_v2_shared_mask_extract(<vscale x 2 x i1> %
; RV32-NEXT: li a3, -1
; RV32-NEXT: vmerge.vim v9, v8, 1, v0
; RV32-NEXT: vmv1r.v v12, v0
-; RV32-NEXT: vwaddu.vv v10, v9, v9
-; RV32-NEXT: vwmaccu.vx v10, a3, v9
-; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma
-; RV32-NEXT: vmv.v.i v9, 0
-; RV32-NEXT: srli a3, a3, 2
+; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
-; RV32-NEXT: vmsne.vi v0, v10, 0
-; RV32-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; RV32-NEXT: vslidedown.vx v10, v10, a3
+; RV32-NEXT: vwaddu.vv v11, v9, v9
+; RV32-NEXT: vwmaccu.vx v11, a3, v9
+; RV32-NEXT: vmsne.vi v0, v11, 0
; RV32-NEXT: vsetvli zero, a2, e8, mf2, ta, ma
-; RV32-NEXT: vmerge.vim v9, v9, 1, v0
+; RV32-NEXT: vmerge.vim v9, v10, 1, v0
+; RV32-NEXT: csrr a3, vlenb
+; RV32-NEXT: srli a3, a3, 2
+; RV32-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
+; RV32-NEXT: vslidedown.vx v10, v11, a3
; RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; RV32-NEXT: vmsne.vi v0, v10, 0
; RV32-NEXT: vmerge.vim v8, v8, 1, v0
@@ -404,12 +404,12 @@ define i32 @masked_load_store_factor2_v2_shared_mask_extract(<vscale x 2 x i1> %
; RV64-NEXT: vmv1r.v v12, v0
; RV64-NEXT: vwaddu.vv v11, v10, v10
; RV64-NEXT: vwmaccu.vx v11, a2, v10
+; RV64-NEXT: vmsne.vi v0, v11, 0
+; RV64-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
+; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: srli a2, a2, 2
-; RV64-NEXT: vmsne.vi v0, v11, 0
-; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vx v10, v11, a2
-; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV64-NEXT: vmsne.vi v0, v10, 0
; RV64-NEXT: vmerge.vim v8, v8, 1, v0
@@ -502,13 +502,13 @@ define {<vscale x 2 x i32>, <vscale x 2 x i32>} @not_same_mask(<vscale x 2 x i1>
; RV32: # %bb.0:
; RV32-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
; RV32-NEXT: vmv1r.v v10, v0
+; RV32-NEXT: vmv1r.v v0, v8
+; RV32-NEXT: vmv.v.i v8, 0
+; RV32-NEXT: vmerge.vim v9, v8, 1, v0
; RV32-NEXT: slli a1, a1, 1
-; RV32-NEXT: vmv.v.i v12, 0
; RV32-NEXT: li a2, -1
-; RV32-NEXT: vmv1r.v v0, v8
-; RV32-NEXT: vmerge.vim v9, v12, 1, v0
; RV32-NEXT: vmv1r.v v0, v10
-; RV32-NEXT: vmerge.vim v10, v12, 1, v0
+; RV32-NEXT: vmerge.vim v10, v8, 1, v0
; RV32-NEXT: vwaddu.vv v11, v10, v9
; RV32-NEXT: vwmaccu.vx v11, a2, v9
; RV32-NEXT: csrr a2, vlenb
@@ -523,7 +523,7 @@ define {<vscale x 2 x i32>, <vscale x 2 x i32>} @not_same_mask(<vscale x 2 x i1>
; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV32-NEXT: vmsne.vi v0, v10, 0
-; RV32-NEXT: vmerge.vim v8, v12, 1, v0
+; RV32-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; RV32-NEXT: vslideup.vx v9, v8, a2
; RV32-NEXT: vmsne.vi v0, v9, 0
@@ -538,31 +538,31 @@ define {<vscale x 2 x i32>, <vscale x 2 x i32>} @not_same_mask(<vscale x 2 x i1>
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
; RV64-NEXT: vmv1r.v v11, v0
-; RV64-NEXT: vmv.v.i v13, 0
+; RV64-NEXT: vmv1r.v v0, v8
+; RV64-NEXT: vmv.v.i v8, 0
+; RV64-NEXT: vmerge.vim v9, v8, 1, v0
; RV64-NEXT: li a2, -1
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv.v.i v9, 0
-; RV64-NEXT: vmv1r.v v0, v8
-; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmerge.vim v10, v13, 1, v0
+; RV64-NEXT: vmv.v.i v10, 0
; RV64-NEXT: vmv1r.v v0, v11
-; RV64-NEXT: vmerge.vim v11, v13, 1, v0
-; RV64-NEXT: vwaddu.vv v12, v11, v10
-; RV64-NEXT: vwmaccu.vx v12, a2, v10
+; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
+; RV64-NEXT: vmerge.vim v11, v8, 1, v0
+; RV64-NEXT: vwaddu.vv v12, v11, v9
+; RV64-NEXT: vwmaccu.vx v12, a2, v9
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a1, a1, 33
; RV64-NEXT: srli a2, a2, 2
; RV64-NEXT: srli a1, a1, 32
; RV64-NEXT: vmsne.vi v0, v12, 0
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vslidedown.vx v10, v12, a2
-; RV64-NEXT: vmerge.vim v9, v9, 1, v0
+; RV64-NEXT: vslidedown.vx v9, v12, a2
+; RV64-NEXT: vmerge.vim v10, v10, 1, v0
; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; RV64-NEXT: vmsne.vi v0, v10, 0
-; RV64-NEXT: vmerge.vim v8, v13, 1, v0
-; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; RV64-NEXT: vslideup.vx v9, v8, a2
; RV64-NEXT: vmsne.vi v0, v9, 0
+; RV64-NEXT: vmerge.vim v8, v8, 1, v0
+; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; RV64-NEXT: vslideup.vx v10, v8, a2
+; RV64-NEXT: vmsne.vi v0, v10, 0
; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma
; RV64-NEXT: vle32.v v10, (a0), v0.t
; RV64-NEXT: li a0, 32
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
index 210bf47e4dff5..258014a023105 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
@@ -255,12 +255,12 @@ define <vscale x 32 x i8> @vpgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8
; RV32-NEXT: sltu a5, a1, a4
; RV32-NEXT: addi a5, a5, -1
; RV32-NEXT: and a4, a5, a4
-; RV32-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
-; RV32-NEXT: vmv1r.v v12, v0
-; RV32-NEXT: vslidedown.vx v0, v0, a3
; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vsext.vf4 v16, v10
-; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, ma
+; RV32-NEXT: vmv1r.v v12, v0
+; RV32-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; RV32-NEXT: vslidedown.vx v0, v0, a3
+; RV32-NEXT: vsetvli zero, a4, e8, m2, ta, ma
; RV32-NEXT: vluxei32.v v10, (a0), v16, v0.t
; RV32-NEXT: bltu a1, a2, .LBB12_2
; RV32-NEXT: # %bb.1:
@@ -277,14 +277,11 @@ define <vscale x 32 x i8> @vpgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8
; RV64: # %bb.0:
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a3, a2, 1
-; RV64-NEXT: srli a4, a2, 2
-; RV64-NEXT: sub a5, a1, a3
-; RV64-NEXT: vsetvli a6, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmv1r.v v12, v0
-; RV64-NEXT: vslidedown.vx v14, v0, a4
-; RV64-NEXT: sltu a4, a1, a5
-; RV64-NEXT: addi a4, a4, -1
-; RV64-NEXT: and a5, a4, a5
+; RV64-NEXT: srli a7, a2, 2
+; RV64-NEXT: sub a4, a1, a3
+; RV64-NEXT: sltu a5, a1, a4
+; RV64-NEXT: addi a5, a5, -1
+; RV64-NEXT: and a5, a5, a4
; RV64-NEXT: sub a4, a5, a2
; RV64-NEXT: sltu a6, a5, a4
; RV64-NEXT: addi a6, a6, -1
@@ -292,9 +289,12 @@ define <vscale x 32 x i8> @vpgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8
; RV64-NEXT: srli a4, a2, 3
; RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v11
-; RV64-NEXT: vmv1r.v v13, v14
+; RV64-NEXT: vmv1r.v v12, v0
+; RV64-NEXT: vsetvli t0, zero, e8, mf2, ta, ma
+; RV64-NEXT: vslidedown.vx v11, v0, a7
+; RV64-NEXT: vmv1r.v v13, v11
; RV64-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
-; RV64-NEXT: vslidedown.vx v0, v14, a4
+; RV64-NEXT: vslidedown.vx v0, v11, a4
; RV64-NEXT: bltu a5, a2, .LBB12_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a5, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
index 2497f43fe3480..6ba9684228449 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
@@ -540,30 +540,30 @@ define <vscale x 128 x i8> @vpmerge_vv_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v6, v0
+; CHECK-NEXT: vmv8r.v v24, v16
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: sub a4, a3, a1
-; CHECK-NEXT: vl8r.v v24, (a2)
-; CHECK-NEXT: sltu a2, a3, a4
+; CHECK-NEXT: add a4, a0, a1
+; CHECK-NEXT: sub a5, a3, a1
+; CHECK-NEXT: vl8r.v v16, (a4)
+; CHECK-NEXT: sltu a4, a3, a5
+; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vl8r.v v8, (a0)
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a4
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, tu, ma
-; CHECK-NEXT: vmerge.vvm v24, v24, v16, v0
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a4, a4, a5
+; CHECK-NEXT: vsetvli zero, a4, e8, m8, tu, ma
+; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: bltu a3, a1, .LBB35_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: .LBB35_2:
; CHECK-NEXT: vmv1r.v v0, v6
; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
+; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vsetvli zero, a3, e8, m8, tu, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
-; CHECK-NEXT: vmv8r.v v16, v24
+; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
@@ -580,18 +580,18 @@ define <vscale x 128 x i8> @vpmerge_vx_nxv128i8(i8 %a, <vscale x 128 x i8> %vb,
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a3, a3, 3
+; CHECK-NEXT: sub a4, a2, a3
; CHECK-NEXT: vlm.v v0, (a1)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: sub a3, a2, a1
-; CHECK-NEXT: sltu a4, a2, a3
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a3, a4, a3
-; CHECK-NEXT: vsetvli zero, a3, e8, m8, tu, ma
+; CHECK-NEXT: sltu a1, a2, a4
+; CHECK-NEXT: addi a1, a1, -1
+; CHECK-NEXT: and a1, a1, a4
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0
-; CHECK-NEXT: bltu a2, a1, .LBB36_2
+; CHECK-NEXT: bltu a2, a3, .LBB36_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a1
+; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB36_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a2, e8, m8, tu, ma
@@ -608,18 +608,18 @@ define <vscale x 128 x i8> @vpmerge_vi_nxv128i8(<vscale x 128 x i8> %vb, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub a2, a1, a0
-; CHECK-NEXT: sltu a3, a1, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, tu, ma
+; CHECK-NEXT: sltu a0, a1, a3
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a3
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, ma
; CHECK-NEXT: vmerge.vim v16, v16, 2, v0
-; CHECK-NEXT: bltu a1, a0, .LBB37_2
+; CHECK-NEXT: bltu a1, a2, .LBB37_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: .LBB37_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
index 15b3508d8e20d..25e4f2cba1edf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
@@ -85,15 +85,15 @@ define half @vpreduce_ord_fadd_nxv4f16(half %s, <vscale x 4 x half> %v, <vscale
define half @vpreduce_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_fadd_nxv64f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: srli a1, a2, 1
-; CHECK-NEXT: slli a2, a2, 2
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v25, v0, a1
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a2, a3, 2
; CHECK-NEXT: sub a1, a0, a2
-; CHECK-NEXT: sltu a3, a0, a1
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a1, a3, a1
+; CHECK-NEXT: sltu a4, a0, a1
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a1, a4, a1
+; CHECK-NEXT: srli a3, a3, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v25, v0, a3
; CHECK-NEXT: bltu a0, a2, .LBB6_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
@@ -114,15 +114,15 @@ define half @vpreduce_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x
define half @vpreduce_ord_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_ord_fadd_nxv64f16:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a2, vlenb
-; CHECK-NEXT: srli a1, a2, 1
-; CHECK-NEXT: slli a2, a2, 2
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: vslidedown.vx v25, v0, a1
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a2, a3, 2
; CHECK-NEXT: sub a1, a0, a2
-; CHECK-NEXT: sltu a3, a0, a1
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a1, a3, a1
+; CHECK-NEXT: sltu a4, a0, a1
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a1, a4, a1
+; CHECK-NEXT: srli a3, a3, 1
+; CHECK-NEXT: vsetvli a4, zero, e8, m1, ta, ma
+; CHECK-NEXT: vslidedown.vx v25, v0, a3
; CHECK-NEXT: bltu a0, a2, .LBB7_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, a2
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
index 295d146ea7a7a..dcd1af0c12879 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
@@ -878,15 +878,15 @@ define signext i32 @vpreduce_umax_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v,
define signext i32 @vpreduce_umax_nxv32i32(i32 signext %s, <vscale x 32 x i32> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_umax_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a3, vlenb
-; CHECK-NEXT: srli a2, a3, 2
-; CHECK-NEXT: slli a3, a3, 1
-; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vslidedown.vx v25, v0, a2
+; CHECK-NEXT: csrr a4, vlenb
+; CHECK-NEXT: slli a3, a4, 1
; CHECK-NEXT: sub a2, a1, a3
-; CHECK-NEXT: sltu a4, a1, a2
-; CHECK-NEXT: addi a4, a4, -1
-; CHECK-NEXT: and a2, a4, a2
+; CHECK-NEXT: sltu a5, a1, a2
+; CHECK-NEXT: addi a5, a5, -1
+; CHECK-NEXT: and a2, a5, a2
+; CHECK-NEXT: srli a4, a4, 2
+; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vslidedown.vx v25, v0, a4
; CHECK-NEXT: bltu a1, a3, .LBB67_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, a3
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
index e197ada5706ab..04dfcbe2945aa 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll
@@ -553,18 +553,18 @@ define <vscale x 128 x i8> @vsadd_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub a2, a1, a0
-; CHECK-NEXT: sltu a3, a1, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-NEXT: sltu a0, a1, a3
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a3
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
-; CHECK-NEXT: bltu a1, a0, .LBB50_2
+; CHECK-NEXT: bltu a1, a2, .LBB50_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
@@ -1305,17 +1305,17 @@ define <vscale x 16 x i32> @vsadd_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vsadd_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsadd_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB118_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
index c35b8af7ffc4f..cf6899fa4933b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll
@@ -552,18 +552,18 @@ define <vscale x 128 x i8> @vsaddu_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub a2, a1, a0
-; CHECK-NEXT: sltu a3, a1, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
+; CHECK-NEXT: sltu a0, a1, a3
+; CHECK-NEXT: addi a0, a0, -1
+; CHECK-NEXT: and a0, a0, a3
+; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
-; CHECK-NEXT: bltu a1, a0, .LBB50_2
+; CHECK-NEXT: bltu a1, a2, .LBB50_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
@@ -1304,17 +1304,17 @@ define <vscale x 16 x i32> @vsaddu_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vsaddu_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsaddu_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB118_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll b/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
index dcf88bd34b00b..373044da3e02a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
@@ -436,8 +436,8 @@ define <vscale x 2 x i32> @vwop_vscale_zext_i1i32_multiple_users(ptr %x, ptr %y,
; NO_FOLDING: # %bb.0:
; NO_FOLDING-NEXT: vsetvli a3, zero, e32, m1, ta, mu
; NO_FOLDING-NEXT: vlm.v v0, (a0)
-; NO_FOLDING-NEXT: vlm.v v10, (a2)
; NO_FOLDING-NEXT: vmv.v.i v8, 0
+; NO_FOLDING-NEXT: vlm.v v10, (a2)
; NO_FOLDING-NEXT: vlm.v v11, (a1)
; NO_FOLDING-NEXT: vmerge.vim v8, v8, 1, v0
; NO_FOLDING-NEXT: vmv.v.v v9, v8
@@ -454,8 +454,8 @@ define <vscale x 2 x i32> @vwop_vscale_zext_i1i32_multiple_users(ptr %x, ptr %y,
; FOLDING: # %bb.0:
; FOLDING-NEXT: vsetvli a3, zero, e32, m1, ta, mu
; FOLDING-NEXT: vlm.v v0, (a0)
-; FOLDING-NEXT: vlm.v v10, (a2)
; FOLDING-NEXT: vmv.v.i v8, 0
+; FOLDING-NEXT: vlm.v v10, (a2)
; FOLDING-NEXT: vlm.v v11, (a1)
; FOLDING-NEXT: vmerge.vim v8, v8, 1, v0
; FOLDING-NEXT: vmv.v.v v9, v8
@@ -486,8 +486,8 @@ define <vscale x 2 x i8> @vwop_vscale_zext_i1i8_multiple_users(ptr %x, ptr %y, p
; NO_FOLDING: # %bb.0:
; NO_FOLDING-NEXT: vsetvli a3, zero, e8, mf4, ta, mu
; NO_FOLDING-NEXT: vlm.v v0, (a0)
-; NO_FOLDING-NEXT: vlm.v v10, (a2)
; NO_FOLDING-NEXT: vmv.v.i v8, 0
+; NO_FOLDING-NEXT: vlm.v v10, (a2)
; NO_FOLDING-NEXT: vlm.v v11, (a1)
; NO_FOLDING-NEXT: vmerge.vim v8, v8, 1, v0
; NO_FOLDING-NEXT: vmv1r.v v9, v8
@@ -504,8 +504,8 @@ define <vscale x 2 x i8> @vwop_vscale_zext_i1i8_multiple_users(ptr %x, ptr %y, p
; FOLDING: # %bb.0:
; FOLDING-NEXT: vsetvli a3, zero, e8, mf4, ta, mu
; FOLDING-NEXT: vlm.v v0, (a0)
-; FOLDING-NEXT: vlm.v v10, (a2)
; FOLDING-NEXT: vmv.v.i v8, 0
+; FOLDING-NEXT: vlm.v v10, (a2)
; FOLDING-NEXT: vlm.v v11, (a1)
; FOLDING-NEXT: vmerge.vim v8, v8, 1, v0
; FOLDING-NEXT: vmv1r.v v9, v8
diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
index 1391f0a564708..759880629ecff 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
@@ -494,17 +494,17 @@ define <vscale x 8 x double> @vfmerge_nzv_nxv8f64(<vscale x 8 x double> %va, <vs
define <vscale x 16 x double> @vselect_combine_regression(<vscale x 16 x i64> %va, <vscale x 16 x double> %vb) {
; CHECK-LABEL: vselect_combine_regression:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, mu
-; CHECK-NEXT: vmseq.vi v24, v16, 0
-; CHECK-NEXT: vmseq.vi v0, v8, 0
+; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; CHECK-NEXT: vmv8r.v v24, v16
; CHECK-NEXT: vmv.v.i v16, 0
-; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: vle64.v v8, (a0), v0.t
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: vle64.v v16, (a1), v0.t
+; CHECK-NEXT: vmseq.vi v0, v24, 0
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: vle64.v v16, (a0), v0.t
; CHECK-NEXT: ret
%cond = icmp eq <vscale x 16 x i64> %va, zeroinitializer
%sel = select <vscale x 16 x i1> %cond, <vscale x 16 x double> %vb, <vscale x 16 x double> zeroinitializer
@@ -523,11 +523,11 @@ define void @vselect_legalize_regression(<vscale x 16 x double> %a, <vscale x 16
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma
; CHECK-NEXT: vmand.mm v0, v0, v7
+; CHECK-NEXT: vsetvli a3, zero, e64, m8, ta, ma
+; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vslidedown.vx v7, v0, a2
+; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, ma
-; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
-; CHECK-NEXT: vmv1r.v v0, v7
; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: add a0, a1, a0
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
index 61de230f9c8d1..7f594f398288a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsext-vp.ll
@@ -137,17 +137,17 @@ define <vscale x 2 x i64> @vsext_nxv2i32_nxv2i64_unmasked(<vscale x 2 x i32> %a,
define <vscale x 32 x i32> @vsext_nxv32i8_nxv32i32(<vscale x 32 x i8> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vsext_nxv32i8_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vsext.vf4 v16, v10, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB12_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
index 6a96645620d0c..2f79cf0df6645 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll
@@ -471,17 +471,17 @@ define <vscale x 2 x double> @vsitofp_nxv2f64_nxv2i64_unmasked(<vscale x 2 x i64
define <vscale x 32 x half> @vsitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: vsitofp_nxv32f16_nxv32i32:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: csrr a1, vlenb
-; ZVFH-NEXT: srli a2, a1, 2
-; ZVFH-NEXT: slli a1, a1, 1
-; ZVFH-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a1, a2, 1
+; ZVFH-NEXT: sub a3, a0, a1
+; ZVFH-NEXT: sltu a4, a0, a3
+; ZVFH-NEXT: addi a4, a4, -1
+; ZVFH-NEXT: and a3, a4, a3
+; ZVFH-NEXT: srli a2, a2, 2
+; ZVFH-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFH-NEXT: vmv1r.v v24, v0
; ZVFH-NEXT: vslidedown.vx v0, v0, a2
-; ZVFH-NEXT: sub a2, a0, a1
-; ZVFH-NEXT: sltu a3, a0, a2
-; ZVFH-NEXT: addi a3, a3, -1
-; ZVFH-NEXT: and a2, a3, a2
-; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFH-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFH-NEXT: vfncvt.f.x.w v28, v16, v0.t
; ZVFH-NEXT: bltu a0, a1, .LBB34_2
; ZVFH-NEXT: # %bb.1:
@@ -495,17 +495,17 @@ define <vscale x 32 x half> @vsitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va,
;
; ZVFHMIN-LABEL: vsitofp_nxv32f16_nxv32i32:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: srli a2, a1, 2
-; ZVFHMIN-NEXT: slli a1, a1, 1
-; ZVFHMIN-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a1, a2, 1
+; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
+; ZVFHMIN-NEXT: srli a2, a2, 2
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
-; ZVFHMIN-NEXT: sub a2, a0, a1
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
-; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v24
@@ -527,17 +527,17 @@ define <vscale x 32 x half> @vsitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va,
define <vscale x 32 x float> @vsitofp_nxv32f32_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_nxv32f32_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB35_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
index 6c0160591f245..2acc910226174 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll
@@ -570,23 +570,23 @@ define <vscale x 128 x i8> @vssub_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: sub a3, a1, a2
+; CHECK-NEXT: sltu a4, a1, a3
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub a2, a1, a0
-; CHECK-NEXT: sltu a3, a1, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a3, a3, a2
-; CHECK-NEXT: li a2, -1
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v16, v16, a2, v0.t
-; CHECK-NEXT: bltu a1, a0, .LBB50_2
+; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t
+; CHECK-NEXT: bltu a1, a2, .LBB50_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vssub.vx v8, v8, a2, v0.t
+; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 128 x i8> @llvm.vp.ssub.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> %m, i32 %evl)
ret <vscale x 128 x i8> %v
@@ -1346,18 +1346,18 @@ define <vscale x 16 x i32> @vssub_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vssub_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssub_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a1, a3, 1
; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a3, a3, a2
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a4, a4, a2
; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: srli a3, a3, 2
+; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vssub.vx v16, v16, a2, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB118_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
index a041b8478b0bb..3d2fb62ef39a5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll
@@ -568,23 +568,23 @@ define <vscale x 128 x i8> @vssubu_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v25, v0
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a2, a2, 3
+; CHECK-NEXT: sub a3, a1, a2
+; CHECK-NEXT: sltu a4, a1, a3
; CHECK-NEXT: vlm.v v0, (a0)
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: sub a2, a1, a0
-; CHECK-NEXT: sltu a3, a1, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a3, a3, a2
-; CHECK-NEXT: li a2, -1
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: li a0, -1
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v16, v16, a2, v0.t
-; CHECK-NEXT: bltu a1, a0, .LBB50_2
+; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t
+; CHECK-NEXT: bltu a1, a2, .LBB50_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a1, a0
+; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
-; CHECK-NEXT: vssubu.vx v8, v8, a2, v0.t
+; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%v = call <vscale x 128 x i8> @llvm.vp.usub.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> %m, i32 %evl)
ret <vscale x 128 x i8> %v
@@ -1344,18 +1344,18 @@ define <vscale x 16 x i32> @vssubu_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va,
define <vscale x 32 x i32> @vssubu_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vssubu_vi_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
+; CHECK-NEXT: csrr a3, vlenb
+; CHECK-NEXT: slli a1, a3, 1
; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a3, a3, a2
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a4, a4, a2
; CHECK-NEXT: li a2, -1
-; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
+; CHECK-NEXT: srli a3, a3, 2
+; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vmv1r.v v24, v0
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
+; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; CHECK-NEXT: vssubu.vx v16, v16, a2, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB118_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
index 63f6cadbc123c..12d2f73f7baa9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
@@ -142,14 +142,14 @@ define <vscale x 15 x i16> @vtrunc_nxv15i16_nxv15i64(<vscale x 15 x i64> %a, <vs
; CHECK-LABEL: vtrunc_nxv15i16_nxv15i64:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 3
-; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sub a2, a0, a1
+; CHECK-NEXT: sltu a3, a0, a2
+; CHECK-NEXT: addi a3, a3, -1
+; CHECK-NEXT: and a2, a3, a2
+; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v28, v0
-; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sltu a2, a0, a3
-; CHECK-NEXT: addi a2, a2, -1
-; CHECK-NEXT: and a2, a2, a3
+; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
@@ -194,17 +194,17 @@ define <vscale x 2 x i32> @vtrunc_nxv2i32_nxv2i64_unmasked(<vscale x 2 x i64> %a
define <vscale x 32 x i7> @vtrunc_nxv32i7_nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv32i7_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v28, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v18, v24, 0, v0.t
@@ -226,17 +226,17 @@ define <vscale x 32 x i7> @vtrunc_nxv32i7_nxv32i32(<vscale x 32 x i32> %a, <vsca
define <vscale x 32 x i8> @vtrunc_nxv32i8_nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_nxv32i8_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v28, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v18, v24, 0, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
index a23fb0c7db18b..ef376162a8022 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll
@@ -471,17 +471,17 @@ define <vscale x 2 x double> @vuitofp_nxv2f64_nxv2i64_unmasked(<vscale x 2 x i64
define <vscale x 32 x half> @vuitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: vuitofp_nxv32f16_nxv32i32:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: csrr a1, vlenb
-; ZVFH-NEXT: srli a2, a1, 2
-; ZVFH-NEXT: slli a1, a1, 1
-; ZVFH-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; ZVFH-NEXT: csrr a2, vlenb
+; ZVFH-NEXT: slli a1, a2, 1
+; ZVFH-NEXT: sub a3, a0, a1
+; ZVFH-NEXT: sltu a4, a0, a3
+; ZVFH-NEXT: addi a4, a4, -1
+; ZVFH-NEXT: and a3, a4, a3
+; ZVFH-NEXT: srli a2, a2, 2
+; ZVFH-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFH-NEXT: vmv1r.v v24, v0
; ZVFH-NEXT: vslidedown.vx v0, v0, a2
-; ZVFH-NEXT: sub a2, a0, a1
-; ZVFH-NEXT: sltu a3, a0, a2
-; ZVFH-NEXT: addi a3, a3, -1
-; ZVFH-NEXT: and a2, a3, a2
-; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFH-NEXT: vsetvli zero, a3, e16, m4, ta, ma
; ZVFH-NEXT: vfncvt.f.xu.w v28, v16, v0.t
; ZVFH-NEXT: bltu a0, a1, .LBB34_2
; ZVFH-NEXT: # %bb.1:
@@ -495,17 +495,17 @@ define <vscale x 32 x half> @vuitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va,
;
; ZVFHMIN-LABEL: vuitofp_nxv32f16_nxv32i32:
; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: csrr a1, vlenb
-; ZVFHMIN-NEXT: srli a2, a1, 2
-; ZVFHMIN-NEXT: slli a1, a1, 1
-; ZVFHMIN-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: csrr a2, vlenb
+; ZVFHMIN-NEXT: slli a1, a2, 1
+; ZVFHMIN-NEXT: sub a3, a0, a1
+; ZVFHMIN-NEXT: sltu a4, a0, a3
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a3, a4, a3
+; ZVFHMIN-NEXT: srli a2, a2, 2
+; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; ZVFHMIN-NEXT: vmv1r.v v7, v0
; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a2
-; ZVFHMIN-NEXT: sub a2, a0, a1
-; ZVFHMIN-NEXT: sltu a3, a0, a2
-; ZVFHMIN-NEXT: addi a3, a3, -1
-; ZVFHMIN-NEXT: and a2, a3, a2
-; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; ZVFHMIN-NEXT: vfcvt.f.xu.v v24, v16, v0.t
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v24
@@ -527,17 +527,17 @@ define <vscale x 32 x half> @vuitofp_nxv32f16_nxv32i32(<vscale x 32 x i32> %va,
define <vscale x 32 x float> @vuitofp_nxv32f32_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_nxv32f32_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB35_2
; CHECK-NEXT: # %bb.1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
index d3ec428c825ee..78ec7457e4064 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vzext-vp.ll
@@ -137,17 +137,17 @@ define <vscale x 2 x i64> @vzext_nxv2i32_nxv2i64_unmasked(<vscale x 2 x i32> %a,
define <vscale x 32 x i32> @vzext_nxv32i8_nxv32i32(<vscale x 32 x i8> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vzext_nxv32i8_nxv32i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a2, a1, 2
-; CHECK-NEXT: slli a1, a1, 1
-; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
+; CHECK-NEXT: csrr a2, vlenb
+; CHECK-NEXT: slli a1, a2, 1
+; CHECK-NEXT: sub a3, a0, a1
+; CHECK-NEXT: sltu a4, a0, a3
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: srli a2, a2, 2
+; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vslidedown.vx v0, v0, a2
-; CHECK-NEXT: sub a2, a0, a1
-; CHECK-NEXT: sltu a3, a0, a2
-; CHECK-NEXT: addi a3, a3, -1
-; CHECK-NEXT: and a2, a3, a2
-; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vzext.vf4 v16, v10, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB12_2
; CHECK-NEXT: # %bb.1:
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