[llvm] [AMDGPU] Allow allocation of lo128 registers from all banks (PR #172614)

[Stanislav Mekhanoshin via llvm-commits]

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@@ -632,13 +632,20 @@ def VGPR_32 : SIRegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types
   let BaseClassOrder = 32;
 }
 
-// Identical to VGPR_32 except it only contains the low 128 (Lo128) registers.
+// Identical to VGPR_32 except only the low 128 (Lo128) registers in each
+// register bank are allocatable.
 def VGPR_32_Lo128 : SIRegisterClass<"AMDGPU", !listconcat(Reg32Types.types, Reg16Types.types), 32,
-                            (add (sequence "VGPR%u", 0, 127))> {
+                            (add (sequence "VGPR%u", 0, 895))> {
+  let AltOrders = [(add (sequence "VGPR%u", 0, 127),
+                        (sequence "VGPR%u", 256, 383),
+                        (sequence "VGPR%u", 512, 639),
+                        (sequence "VGPR%u", 768, 895))];
+  let AltOrderSelect = [{ return 1; }];
   let AllocationPriority = !add(0, !mul(BaseClassPriority, BaseClassScaleFactor));
   let GeneratePressureSet = 0;
   let Size = 32;
   let Weight = 1;
+  let BaseClassOrder = 33;
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rampitec wrote:

This fixes it: https://github.com/llvm/llvm-project/pull/177257. I now have problem with VINTERP selection, but at least it makes base class deterministically base.

https://github.com/llvm/llvm-project/pull/172614