[llvm] [CodeGen] [EarlyIfConversion] Prioritize conversion of hard to predict branches (PR #174457)
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 12 02:55:26 PST 2026
================
@@ -896,6 +909,133 @@ void EarlyIfConverter::invalidateTraces() {
Traces->verifyAnalysis();
}
+/// Check if a register's value comes from a memory load by walking the
+/// def-use chain. We want to prioritize converting branches which
+/// depend on values loaded from memory (unless they are loop invariant,
+/// or come from a constant pool).
+/// Results are cached for virtual registers only.
+bool EarlyIfConverter::doOperandsComeFromMemory(Register Reg) {
+ if (!Reg.isVirtual())
+ return false;
+
+ // Check cache first.
+ auto It = OperandMemoryCache.find(Reg);
+ if (It != OperandMemoryCache.end())
+ return It->second;
+
+ // Walk the def-use chain.
+ SmallPtrSet<const MachineInstr *, 8> Visited;
+ SmallVector<const MachineInstr *> Worklist;
+ SmallVector<Register, 16> VisitedRegs;
+
+ MachineInstr *DefMI = MRI->getVRegDef(Reg);
+ // The operand is defined outside of the function - it does not
+ // come from memory access.
+ if (!DefMI) {
+ OperandMemoryCache[Reg] = false;
+ return false;
+ }
+
+ Worklist.push_back(DefMI);
+ VisitedRegs.push_back(Reg);
+
+ while (!Worklist.empty()) {
+ const MachineInstr *MI = Worklist.pop_back_val();
+ if (!Visited.insert(MI).second)
+ continue;
+
+ // Check if this instruction is a load.
+ if (MI->mayLoad()) {
+ LLVM_DEBUG(dbgs() << "Operand comes from load: " << *MI);
+ // Check if the load is from a constant pool
+ bool IsConstantPoolLoad = false;
+ for (const auto &MOp : MI->memoperands()) {
+ if (const PseudoSourceValue *PSV = MOp->getPseudoValue())
+ if (PSV->isConstantPool()) {
+ LLVM_DEBUG(dbgs() << "Found constant pool load!\n");
+ IsConstantPoolLoad = true;
+ }
+ // Cache all visited virtual registers as coming from memory.
+ for (Register Reg : VisitedRegs)
+ OperandMemoryCache[Reg] = !IsConstantPoolLoad;
----------------
fhahn wrote:
hmm, doesn't VisitedRegs also potentially contain registers from instructions completely unconnected to the current load?
https://github.com/llvm/llvm-project/pull/174457
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