[llvm] [SDAG] fix miss opt: shl nuw + zext adds unnecessary masking (PR #172046)

[via llvm-commits]

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@@ -1572,6 +1572,9 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) {
   assert(VT.bitsLE(OpVT) && "Not extending!");
   if (OpVT == VT)
     return Op;
+  if (Op.getOpcode() == ISD::AssertZext &&
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actinks wrote:

No, existing test cases are not affected by updating getZeroExtendInReg—only the newly added test file pr172046.ll is impacted.

https://github.com/llvm/llvm-project/pull/172046