[llvm] [SelectionDAG] Provide context for vector count / type mismatch (PR #175433)
Trevor Gross via llvm-commits
llvm-commits at lists.llvm.org
Sun Jan 11 05:35:04 PST 2026
https://github.com/tgross35 updated https://github.com/llvm/llvm-project/pull/175433
>From 2c5c86230244169ba71d35f074e6a0e6b5a04bc4 Mon Sep 17 00:00:00 2001
From: Trevor Gross <tg at trevorgross.com>
Date: Sun, 11 Jan 2026 01:26:43 -0500
Subject: [PATCH] [SelectionDAG] Provide context for vector count / type
mismatch
This now gives better details about what the mismatch is, e.g.:
---
.../llvm/CodeGenTypes/MachineValueType.h | 3 +
.../SelectionDAG/SelectionDAGBuilder.cpp | 39 +-
llvm/lib/CodeGen/ValueTypes.cpp | 14 +-
llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll | 14 +-
llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll | 1084 ++++++++++++++---
llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll | 85 +-
llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll | 120 +-
llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll | 14 +-
llvm/test/CodeGen/AMDGPU/omod.ll | 21 +-
.../AMDGPU/select-fabs-fneg-extract.f16.ll | 616 ++++++----
llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll | 20 +-
llvm/test/CodeGen/AMDGPU/v_cndmask.ll | 5 +-
llvm/test/CodeGen/AMDGPU/v_madak_f16.ll | 34 +-
13 files changed, 1453 insertions(+), 616 deletions(-)
diff --git a/llvm/include/llvm/CodeGenTypes/MachineValueType.h b/llvm/include/llvm/CodeGenTypes/MachineValueType.h
index 08a9c85a213e0..64687d515d21a 100644
--- a/llvm/include/llvm/CodeGenTypes/MachineValueType.h
+++ b/llvm/include/llvm/CodeGenTypes/MachineValueType.h
@@ -64,6 +64,9 @@ namespace llvm {
bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
+ /// Return the value type as a string, e.g. `i32`.
+ std::string getString() const;
+
/// Support for debugging, callable in GDB: VT.dump()
LLVM_ABI void dump() const;
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index bff4799963fc2..4c82185f478fe 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -95,6 +95,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/InstructionCost.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
@@ -330,6 +331,32 @@ static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
return Ctx.emitError(I, ErrMsg);
}
+/// Emit a fatal error if the broken dow registers don't match part size, type,
+// or count.
+static void ensureMatchedVecRegParts(unsigned NumRegs, unsigned NumParts,
+ MVT RegisterVT, MVT PartVT,
+ const SDValue *Parts) {
+ if (NumRegs != NumParts || RegisterVT != PartVT)
+ report_fatal_error(Twine("Part count doesn't match vector breakdown! ")
+ .concat(Twine(NumRegs))
+ .concat(" registers, ")
+ .concat(Twine(NumParts))
+ .concat(" parts, ")
+ .concat(Twine(RegisterVT.getString()))
+ .concat(" RegisterVT, ")
+ .concat(Twine(PartVT.getString()))
+ .concat(" PartVT"));
+
+ unsigned RegSize = RegisterVT.getSizeInBits();
+ unsigned PartSize = Parts[0].getSimpleValueType().getSizeInBits();
+
+ if (NumParts > 0 && RegSize != PartSize) {
+ report_fatal_error(Twine("Part type sizes don't match! register size ")
+ .concat(Twine(RegSize))
+ .concat(", part size ")
+ .concat(Twine(PartSize)));
+ }
+}
/// getCopyFromPartsVector - Create a value that contains the specified legal
/// parts combined into the value they represent. If the parts combine to a
/// type larger than ValueVT then AssertOp can be used to specify whether the
@@ -364,12 +391,7 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
NumIntermediates, RegisterVT);
}
- assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
- NumParts = NumRegs; // Silence a compiler warning.
- assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
- assert(RegisterVT.getSizeInBits() ==
- Parts[0].getSimpleValueType().getSizeInBits() &&
- "Part type sizes don't match!");
+ ensureMatchedVecRegParts(NumRegs, NumParts, RegisterVT, PartVT, Parts);
// Assemble the parts into intermediate operands.
SmallVector<SDValue, 8> Ops(NumIntermediates);
@@ -769,10 +791,7 @@ static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL,
NumIntermediates, RegisterVT);
}
- assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
- NumParts = NumRegs; // Silence a compiler warning.
- assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
-
+ ensureMatchedVecRegParts(NumRegs, NumParts, RegisterVT, PartVT, Parts);
assert(IntermediateVT.isScalableVector() == ValueVT.isScalableVector() &&
"Mixing scalable and fixed vectors when copying in parts");
diff --git a/llvm/lib/CodeGen/ValueTypes.cpp b/llvm/lib/CodeGen/ValueTypes.cpp
index 0743c92c5b95b..f3e4eaa2ef00f 100644
--- a/llvm/lib/CodeGen/ValueTypes.cpp
+++ b/llvm/lib/CodeGen/ValueTypes.cpp
@@ -333,6 +333,13 @@ const fltSemantics &EVT::getFltSemantics() const {
return getScalarType().getSimpleVT().getFltSemantics();
}
+std::string MVT::getString() const {
+ if (SimpleTy == INVALID_SIMPLE_VALUE_TYPE)
+ return "invalid";
+
+ return EVT(*this).getEVTString();
+}
+
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
void MVT::dump() const {
print(dbgs());
@@ -340,9 +347,4 @@ void MVT::dump() const {
}
#endif
-void MVT::print(raw_ostream &OS) const {
- if (SimpleTy == INVALID_SIMPLE_VALUE_TYPE)
- OS << "invalid";
- else
- OS << EVT(*this).getEVTString();
-}
+void MVT::print(raw_ostream &OS) const { OS << getString(); }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
index b7768998160d5..0b72374fd44a3 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
@@ -143,19 +143,19 @@ define amdgpu_kernel void @cos_v2f16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
; GFX6-NEXT: s_mov_b32 s4, s0
; GFX6-NEXT: s_mov_b32 s5, s1
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX6-NEXT: v_mul_f32_e32 v1, 0x3e22f983, v1
-; GFX6-NEXT: v_fract_f32_e32 v1, v1
; GFX6-NEXT: v_mul_f32_e32 v0, 0x3e22f983, v0
+; GFX6-NEXT: v_fract_f32_e32 v1, v1
+; GFX6-NEXT: v_cos_f32_e32 v1, v1
; GFX6-NEXT: v_fract_f32_e32 v0, v0
; GFX6-NEXT: v_cos_f32_e32 v0, v0
-; GFX6-NEXT: v_cos_f32_e32 v1, v1
-; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
index 97ea988581ce3..e8bf198f89855 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
@@ -16,29 +16,74 @@ define amdgpu_kernel void @fma_f16(
; SI-NEXT: s_mov_b32 s14, s10
; SI-NEXT: s_mov_b32 s15, s11
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s12, s2
-; SI-NEXT: s_mov_b32 s13, s3
; SI-NEXT: s_mov_b32 s16, s4
; SI-NEXT: s_mov_b32 s17, s5
-; SI-NEXT: s_mov_b32 s18, s10
-; SI-NEXT: s_mov_b32 s19, s11
; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s6, s10
; SI-NEXT: s_mov_b32 s7, s11
-; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0
+; SI-NEXT: s_mov_b32 s12, s2
+; SI-NEXT: s_mov_b32 s13, s3
+; SI-NEXT: s_mov_b32 s18, s10
+; SI-NEXT: s_mov_b32 s19, s11
+; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
; SI-NEXT: buffer_load_ushort v1, off, s[16:19], 0
-; SI-NEXT: buffer_load_ushort v2, off, s[4:7], 0
+; SI-NEXT: buffer_load_ushort v2, off, s[12:15], 0
; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1
+; SI-NEXT: s_movk_i32 s2, 0x7e00
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NEXT: v_fma_f32 v0, v0, v1, v2
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v2
+; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v3
+; SI-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
+; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
+; SI-NEXT: v_readfirstlane_b32 s0, v1
+; SI-NEXT: s_and_b32 s1, s0, 0x1ff
+; SI-NEXT: v_or_b32_e32 v0, s1, v0
+; SI-NEXT: s_lshr_b32 s3, s0, 8
+; SI-NEXT: s_bfe_u32 s4, s0, 0xb0014
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: s_and_b32 s1, s3, 0xffe
+; SI-NEXT: s_sub_i32 s3, 0x3f1, s4
+; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; SI-NEXT: v_med3_i32 v1, s3, 0, 13
+; SI-NEXT: v_readfirstlane_b32 s3, v0
+; SI-NEXT: s_or_b32 s1, s1, s3
+; SI-NEXT: v_readfirstlane_b32 s5, v1
+; SI-NEXT: s_or_b32 s3, s1, 0x1000
+; SI-NEXT: s_lshr_b32 s6, s3, s5
+; SI-NEXT: s_lshl_b32 s5, s6, s5
+; SI-NEXT: s_cmp_lg_u32 s5, s3
+; SI-NEXT: s_cselect_b32 s3, 1, 0
+; SI-NEXT: s_addk_i32 s4, 0xfc10
+; SI-NEXT: s_lshl_b32 s5, s4, 12
+; SI-NEXT: s_or_b32 s3, s6, s3
+; SI-NEXT: s_or_b32 s5, s1, s5
+; SI-NEXT: s_cmp_lt_i32 s4, 1
+; SI-NEXT: s_cselect_b32 s3, s3, s5
+; SI-NEXT: s_and_b32 s5, s3, 7
+; SI-NEXT: s_cmp_gt_i32 s5, 5
+; SI-NEXT: s_cselect_b32 s6, 1, 0
+; SI-NEXT: s_cmp_eq_u32 s5, 3
+; SI-NEXT: s_cselect_b32 s5, 1, 0
+; SI-NEXT: s_lshr_b32 s3, s3, 2
+; SI-NEXT: s_or_b32 s5, s5, s6
+; SI-NEXT: s_add_i32 s3, s3, s5
+; SI-NEXT: s_cmp_lt_i32 s4, 31
+; SI-NEXT: s_cselect_b32 s3, s3, 0x7c00
+; SI-NEXT: s_cmp_lg_u32 s1, 0
+; SI-NEXT: s_cselect_b32 s1, s2, 0x7c00
+; SI-NEXT: s_cmpk_eq_i32 s4, 0x40f
+; SI-NEXT: s_cselect_b32 s1, s1, s3
+; SI-NEXT: s_lshr_b32 s0, s0, 16
+; SI-NEXT: s_and_b32 s0, s0, 0x8000
+; SI-NEXT: s_or_b32 s0, s0, s1
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
; SI-NEXT: s_endpgm
;
@@ -112,29 +157,74 @@ define amdgpu_kernel void @fma_f16(
define amdgpu_kernel void @fma_f16_imm_a(
; SI-LABEL: fma_f16_imm_a:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s14, s6
+; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s6, s2
+; SI-NEXT: s_mov_b32 s7, s3
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s12, s2
-; SI-NEXT: s_mov_b32 s13, s3
-; SI-NEXT: s_mov_b32 s15, s7
-; SI-NEXT: s_mov_b32 s10, s6
-; SI-NEXT: s_mov_b32 s11, s7
-; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0
-; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
-; SI-NEXT: s_mov_b32 s2, 0x40400000
-; SI-NEXT: s_mov_b32 s4, s0
-; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: s_mov_b32 s12, s10
+; SI-NEXT: s_mov_b32 s13, s11
+; SI-NEXT: s_mov_b32 s14, s2
+; SI-NEXT: s_mov_b32 s15, s3
+; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
+; SI-NEXT: buffer_load_ushort v1, off, s[12:15], 0
+; SI-NEXT: s_mov_b32 s4, 0
+; SI-NEXT: s_mov_b32 s5, 0x40080000
+; SI-NEXT: s_mov_b32 s0, s8
+; SI-NEXT: s_mov_b32 s1, s9
+; SI-NEXT: s_movk_i32 s6, 0x7e00
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NEXT: v_fma_f32 v0, v0, s2, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v1
+; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
+; SI-NEXT: v_fma_f64 v[0:1], v[2:3], s[4:5], v[0:1]
+; SI-NEXT: v_readfirstlane_b32 s4, v1
+; SI-NEXT: s_and_b32 s5, s4, 0x1ff
+; SI-NEXT: v_or_b32_e32 v0, s5, v0
+; SI-NEXT: s_lshr_b32 s7, s4, 8
+; SI-NEXT: s_bfe_u32 s8, s4, 0xb0014
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: s_and_b32 s5, s7, 0xffe
+; SI-NEXT: s_sub_i32 s7, 0x3f1, s8
+; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; SI-NEXT: v_med3_i32 v1, s7, 0, 13
+; SI-NEXT: v_readfirstlane_b32 s7, v0
+; SI-NEXT: s_or_b32 s5, s5, s7
+; SI-NEXT: v_readfirstlane_b32 s9, v1
+; SI-NEXT: s_or_b32 s7, s5, 0x1000
+; SI-NEXT: s_lshr_b32 s10, s7, s9
+; SI-NEXT: s_lshl_b32 s9, s10, s9
+; SI-NEXT: s_cmp_lg_u32 s9, s7
+; SI-NEXT: s_cselect_b32 s7, 1, 0
+; SI-NEXT: s_addk_i32 s8, 0xfc10
+; SI-NEXT: s_lshl_b32 s9, s8, 12
+; SI-NEXT: s_or_b32 s7, s10, s7
+; SI-NEXT: s_or_b32 s9, s5, s9
+; SI-NEXT: s_cmp_lt_i32 s8, 1
+; SI-NEXT: s_cselect_b32 s7, s7, s9
+; SI-NEXT: s_and_b32 s9, s7, 7
+; SI-NEXT: s_cmp_gt_i32 s9, 5
+; SI-NEXT: s_cselect_b32 s10, 1, 0
+; SI-NEXT: s_cmp_eq_u32 s9, 3
+; SI-NEXT: s_cselect_b32 s9, 1, 0
+; SI-NEXT: s_lshr_b32 s7, s7, 2
+; SI-NEXT: s_or_b32 s9, s9, s10
+; SI-NEXT: s_add_i32 s7, s7, s9
+; SI-NEXT: s_cmp_lt_i32 s8, 31
+; SI-NEXT: s_cselect_b32 s7, s7, 0x7c00
+; SI-NEXT: s_cmp_lg_u32 s5, 0
+; SI-NEXT: s_cselect_b32 s5, s6, 0x7c00
+; SI-NEXT: s_cmpk_eq_i32 s8, 0x40f
+; SI-NEXT: s_cselect_b32 s5, s5, s7
+; SI-NEXT: s_lshr_b32 s4, s4, 16
+; SI-NEXT: s_and_b32 s4, s4, 0x8000
+; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fma_f16_imm_a:
@@ -195,29 +285,74 @@ define amdgpu_kernel void @fma_f16_imm_a(
define amdgpu_kernel void @fma_f16_imm_b(
; SI-LABEL: fma_f16_imm_b:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s14, s6
+; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s6, s2
+; SI-NEXT: s_mov_b32 s7, s3
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s12, s2
-; SI-NEXT: s_mov_b32 s13, s3
-; SI-NEXT: s_mov_b32 s15, s7
-; SI-NEXT: s_mov_b32 s10, s6
-; SI-NEXT: s_mov_b32 s11, s7
-; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0
-; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
-; SI-NEXT: s_mov_b32 s2, 0x40400000
-; SI-NEXT: s_mov_b32 s4, s0
-; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: s_mov_b32 s12, s10
+; SI-NEXT: s_mov_b32 s13, s11
+; SI-NEXT: s_mov_b32 s14, s2
+; SI-NEXT: s_mov_b32 s15, s3
+; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
+; SI-NEXT: buffer_load_ushort v1, off, s[12:15], 0
+; SI-NEXT: s_mov_b32 s4, 0
+; SI-NEXT: s_mov_b32 s5, 0x40080000
+; SI-NEXT: s_mov_b32 s0, s8
+; SI-NEXT: s_mov_b32 s1, s9
+; SI-NEXT: s_movk_i32 s6, 0x7e00
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NEXT: v_fma_f32 v0, v0, s2, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v1
+; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
+; SI-NEXT: v_fma_f64 v[0:1], v[2:3], s[4:5], v[0:1]
+; SI-NEXT: v_readfirstlane_b32 s4, v1
+; SI-NEXT: s_and_b32 s5, s4, 0x1ff
+; SI-NEXT: v_or_b32_e32 v0, s5, v0
+; SI-NEXT: s_lshr_b32 s7, s4, 8
+; SI-NEXT: s_bfe_u32 s8, s4, 0xb0014
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: s_and_b32 s5, s7, 0xffe
+; SI-NEXT: s_sub_i32 s7, 0x3f1, s8
+; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; SI-NEXT: v_med3_i32 v1, s7, 0, 13
+; SI-NEXT: v_readfirstlane_b32 s7, v0
+; SI-NEXT: s_or_b32 s5, s5, s7
+; SI-NEXT: v_readfirstlane_b32 s9, v1
+; SI-NEXT: s_or_b32 s7, s5, 0x1000
+; SI-NEXT: s_lshr_b32 s10, s7, s9
+; SI-NEXT: s_lshl_b32 s9, s10, s9
+; SI-NEXT: s_cmp_lg_u32 s9, s7
+; SI-NEXT: s_cselect_b32 s7, 1, 0
+; SI-NEXT: s_addk_i32 s8, 0xfc10
+; SI-NEXT: s_lshl_b32 s9, s8, 12
+; SI-NEXT: s_or_b32 s7, s10, s7
+; SI-NEXT: s_or_b32 s9, s5, s9
+; SI-NEXT: s_cmp_lt_i32 s8, 1
+; SI-NEXT: s_cselect_b32 s7, s7, s9
+; SI-NEXT: s_and_b32 s9, s7, 7
+; SI-NEXT: s_cmp_gt_i32 s9, 5
+; SI-NEXT: s_cselect_b32 s10, 1, 0
+; SI-NEXT: s_cmp_eq_u32 s9, 3
+; SI-NEXT: s_cselect_b32 s9, 1, 0
+; SI-NEXT: s_lshr_b32 s7, s7, 2
+; SI-NEXT: s_or_b32 s9, s9, s10
+; SI-NEXT: s_add_i32 s7, s7, s9
+; SI-NEXT: s_cmp_lt_i32 s8, 31
+; SI-NEXT: s_cselect_b32 s7, s7, 0x7c00
+; SI-NEXT: s_cmp_lg_u32 s5, 0
+; SI-NEXT: s_cselect_b32 s5, s6, 0x7c00
+; SI-NEXT: s_cmpk_eq_i32 s8, 0x40f
+; SI-NEXT: s_cselect_b32 s5, s5, s7
+; SI-NEXT: s_lshr_b32 s4, s4, 16
+; SI-NEXT: s_and_b32 s4, s4, 0x8000
+; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fma_f16_imm_b:
@@ -278,29 +413,74 @@ define amdgpu_kernel void @fma_f16_imm_b(
define amdgpu_kernel void @fma_f16_imm_c(
; SI-LABEL: fma_f16_imm_c:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s14, s6
+; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s6, s2
+; SI-NEXT: s_mov_b32 s7, s3
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s12, s2
-; SI-NEXT: s_mov_b32 s13, s3
-; SI-NEXT: s_mov_b32 s15, s7
-; SI-NEXT: s_mov_b32 s10, s6
-; SI-NEXT: s_mov_b32 s11, s7
-; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0
-; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
-; SI-NEXT: s_mov_b32 s2, 0x40400000
-; SI-NEXT: s_mov_b32 s4, s0
-; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: s_mov_b32 s12, s10
+; SI-NEXT: s_mov_b32 s13, s11
+; SI-NEXT: s_mov_b32 s14, s2
+; SI-NEXT: s_mov_b32 s15, s3
+; SI-NEXT: buffer_load_ushort v0, off, s[4:7], 0
+; SI-NEXT: buffer_load_ushort v1, off, s[12:15], 0
+; SI-NEXT: s_mov_b32 s4, 0
+; SI-NEXT: s_mov_b32 s5, 0x40080000
+; SI-NEXT: s_mov_b32 s0, s8
+; SI-NEXT: s_mov_b32 s1, s9
+; SI-NEXT: s_movk_i32 s6, 0x7e00
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NEXT: v_fma_f32 v0, v0, v1, s2
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v1
+; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
+; SI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], s[4:5]
+; SI-NEXT: v_readfirstlane_b32 s4, v1
+; SI-NEXT: s_and_b32 s5, s4, 0x1ff
+; SI-NEXT: v_or_b32_e32 v0, s5, v0
+; SI-NEXT: s_lshr_b32 s7, s4, 8
+; SI-NEXT: s_bfe_u32 s8, s4, 0xb0014
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: s_and_b32 s5, s7, 0xffe
+; SI-NEXT: s_sub_i32 s7, 0x3f1, s8
+; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; SI-NEXT: v_med3_i32 v1, s7, 0, 13
+; SI-NEXT: v_readfirstlane_b32 s7, v0
+; SI-NEXT: s_or_b32 s5, s5, s7
+; SI-NEXT: v_readfirstlane_b32 s9, v1
+; SI-NEXT: s_or_b32 s7, s5, 0x1000
+; SI-NEXT: s_lshr_b32 s10, s7, s9
+; SI-NEXT: s_lshl_b32 s9, s10, s9
+; SI-NEXT: s_cmp_lg_u32 s9, s7
+; SI-NEXT: s_cselect_b32 s7, 1, 0
+; SI-NEXT: s_addk_i32 s8, 0xfc10
+; SI-NEXT: s_lshl_b32 s9, s8, 12
+; SI-NEXT: s_or_b32 s7, s10, s7
+; SI-NEXT: s_or_b32 s9, s5, s9
+; SI-NEXT: s_cmp_lt_i32 s8, 1
+; SI-NEXT: s_cselect_b32 s7, s7, s9
+; SI-NEXT: s_and_b32 s9, s7, 7
+; SI-NEXT: s_cmp_gt_i32 s9, 5
+; SI-NEXT: s_cselect_b32 s10, 1, 0
+; SI-NEXT: s_cmp_eq_u32 s9, 3
+; SI-NEXT: s_cselect_b32 s9, 1, 0
+; SI-NEXT: s_lshr_b32 s7, s7, 2
+; SI-NEXT: s_or_b32 s9, s9, s10
+; SI-NEXT: s_add_i32 s7, s7, s9
+; SI-NEXT: s_cmp_lt_i32 s8, 31
+; SI-NEXT: s_cselect_b32 s7, s7, 0x7c00
+; SI-NEXT: s_cmp_lg_u32 s5, 0
+; SI-NEXT: s_cselect_b32 s5, s6, 0x7c00
+; SI-NEXT: s_cmpk_eq_i32 s8, 0x40f
+; SI-NEXT: s_cselect_b32 s5, s5, s7
+; SI-NEXT: s_lshr_b32 s4, s4, 16
+; SI-NEXT: s_and_b32 s4, s4, 0x8000
+; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fma_f16_imm_c:
@@ -376,30 +556,119 @@ define amdgpu_kernel void @fma_v2f16(
; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s6, s10
-; SI-NEXT: buffer_load_dword v0, off, s[12:15], 0
; SI-NEXT: s_mov_b32 s7, s11
+; SI-NEXT: buffer_load_dword v0, off, s[12:15], 0
; SI-NEXT: buffer_load_dword v1, off, s[16:19], 0
; SI-NEXT: buffer_load_dword v2, off, s[4:7], 0
; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1
+; SI-NEXT: s_movk_i32 s2, 0x7e00
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_cvt_f32_f16_e32 v3, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v7, v0
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
-; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NEXT: v_fma_f32 v0, v0, v4, v5
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: v_fma_f32 v1, v3, v1, v2
-; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v8, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v9, v4
+; SI-NEXT: v_cvt_f32_f16_e32 v10, v3
+; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v2
+; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v6
+; SI-NEXT: v_cvt_f64_f32_e32 v[4:5], v7
+; SI-NEXT: v_cvt_f64_f32_e32 v[6:7], v8
+; SI-NEXT: v_cvt_f64_f32_e32 v[8:9], v9
+; SI-NEXT: v_cvt_f64_f32_e32 v[10:11], v10
+; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
+; SI-NEXT: v_readfirstlane_b32 s0, v1
+; SI-NEXT: s_and_b32 s1, s0, 0x1ff
+; SI-NEXT: v_or_b32_e32 v0, s1, v0
+; SI-NEXT: s_lshr_b32 s3, s0, 8
+; SI-NEXT: s_bfe_u32 s4, s0, 0xb0014
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: s_and_b32 s1, s3, 0xffe
+; SI-NEXT: s_sub_i32 s3, 0x3f1, s4
+; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; SI-NEXT: v_med3_i32 v1, s3, 0, 13
+; SI-NEXT: v_readfirstlane_b32 s3, v0
+; SI-NEXT: s_or_b32 s1, s1, s3
+; SI-NEXT: v_readfirstlane_b32 s6, v1
+; SI-NEXT: s_or_b32 s3, s1, 0x1000
+; SI-NEXT: s_lshr_b32 s7, s3, s6
+; SI-NEXT: s_lshl_b32 s6, s7, s6
+; SI-NEXT: s_cmp_lg_u32 s6, s3
+; SI-NEXT: s_cselect_b32 s3, 1, 0
+; SI-NEXT: s_addk_i32 s4, 0xfc10
+; SI-NEXT: s_lshl_b32 s6, s4, 12
+; SI-NEXT: s_or_b32 s3, s7, s3
+; SI-NEXT: s_or_b32 s6, s1, s6
+; SI-NEXT: s_cmp_lt_i32 s4, 1
+; SI-NEXT: s_cselect_b32 s3, s3, s6
+; SI-NEXT: s_and_b32 s6, s3, 7
+; SI-NEXT: s_cmp_gt_i32 s6, 5
+; SI-NEXT: s_cselect_b32 s7, 1, 0
+; SI-NEXT: s_cmp_eq_u32 s6, 3
+; SI-NEXT: s_cselect_b32 s6, 1, 0
+; SI-NEXT: s_lshr_b32 s3, s3, 2
+; SI-NEXT: s_or_b32 s6, s6, s7
+; SI-NEXT: s_add_i32 s3, s3, s6
+; SI-NEXT: v_fma_f64 v[2:3], v[10:11], v[8:9], v[6:7]
+; SI-NEXT: s_cmp_lt_i32 s4, 31
+; SI-NEXT: s_cselect_b32 s3, s3, 0x7c00
+; SI-NEXT: s_cmp_lg_u32 s1, 0
+; SI-NEXT: v_readfirstlane_b32 s5, v3
+; SI-NEXT: s_cselect_b32 s1, s2, 0x7c00
+; SI-NEXT: s_cmpk_eq_i32 s4, 0x40f
+; SI-NEXT: s_cselect_b32 s1, s1, s3
+; SI-NEXT: s_and_b32 s3, s5, 0x1ff
+; SI-NEXT: v_or_b32_e32 v0, s3, v2
+; SI-NEXT: s_lshr_b32 s0, s0, 16
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: s_lshr_b32 s4, s5, 8
+; SI-NEXT: s_bfe_u32 s6, s5, 0xb0014
+; SI-NEXT: s_and_b32 s0, s0, 0x8000
+; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; SI-NEXT: s_and_b32 s3, s4, 0xffe
+; SI-NEXT: s_sub_i32 s4, 0x3f1, s6
+; SI-NEXT: s_or_b32 s0, s0, s1
+; SI-NEXT: v_readfirstlane_b32 s1, v0
+; SI-NEXT: v_med3_i32 v1, s4, 0, 13
+; SI-NEXT: s_or_b32 s1, s3, s1
+; SI-NEXT: v_readfirstlane_b32 s4, v1
+; SI-NEXT: s_or_b32 s3, s1, 0x1000
+; SI-NEXT: s_lshr_b32 s7, s3, s4
+; SI-NEXT: s_and_b32 s0, s0, 0xffff
+; SI-NEXT: s_lshl_b32 s4, s7, s4
+; SI-NEXT: s_cmp_lg_u32 s4, s3
+; SI-NEXT: s_cselect_b32 s3, 1, 0
+; SI-NEXT: s_addk_i32 s6, 0xfc10
+; SI-NEXT: s_lshl_b32 s4, s6, 12
+; SI-NEXT: s_or_b32 s3, s7, s3
+; SI-NEXT: s_or_b32 s4, s1, s4
+; SI-NEXT: s_cmp_lt_i32 s6, 1
+; SI-NEXT: s_cselect_b32 s3, s3, s4
+; SI-NEXT: s_and_b32 s4, s3, 7
+; SI-NEXT: s_cmp_gt_i32 s4, 5
+; SI-NEXT: s_cselect_b32 s7, 1, 0
+; SI-NEXT: s_cmp_eq_u32 s4, 3
+; SI-NEXT: s_cselect_b32 s4, 1, 0
+; SI-NEXT: s_lshr_b32 s3, s3, 2
+; SI-NEXT: s_or_b32 s4, s4, s7
+; SI-NEXT: s_add_i32 s3, s3, s4
+; SI-NEXT: s_cmp_lt_i32 s6, 31
+; SI-NEXT: s_cselect_b32 s3, s3, 0x7c00
+; SI-NEXT: s_cmp_lg_u32 s1, 0
+; SI-NEXT: s_cselect_b32 s1, s2, 0x7c00
+; SI-NEXT: s_cmpk_eq_i32 s6, 0x40f
+; SI-NEXT: s_cselect_b32 s1, s1, s3
+; SI-NEXT: s_lshr_b32 s2, s5, 16
+; SI-NEXT: s_and_b32 s2, s2, 0x8000
+; SI-NEXT: s_or_b32 s1, s2, s1
+; SI-NEXT: s_lshl_b32 s1, s1, 16
+; SI-NEXT: s_or_b32 s0, s0, s1
+; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; SI-NEXT: s_endpgm
;
@@ -481,37 +750,125 @@ define amdgpu_kernel void @fma_v2f16(
define amdgpu_kernel void @fma_v2f16_imm_a(
; SI-LABEL: fma_v2f16_imm_a:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s10, s6
-; SI-NEXT: s_mov_b32 s11, s7
+; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s14, s2
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s12, s2
-; SI-NEXT: s_mov_b32 s13, s3
-; SI-NEXT: s_mov_b32 s14, s6
-; SI-NEXT: s_mov_b32 s15, s7
-; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
+; SI-NEXT: s_mov_b32 s12, s10
+; SI-NEXT: s_mov_b32 s13, s11
+; SI-NEXT: s_mov_b32 s6, s2
+; SI-NEXT: s_mov_b32 s7, s3
+; SI-NEXT: s_mov_b32 s15, s3
+; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0
; SI-NEXT: buffer_load_dword v1, off, s[12:15], 0
-; SI-NEXT: s_mov_b32 s2, 0x40400000
-; SI-NEXT: s_mov_b32 s4, s0
-; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: s_mov_b32 s4, 0
+; SI-NEXT: s_mov_b32 s5, 0x40080000
+; SI-NEXT: s_mov_b32 s0, s8
+; SI-NEXT: s_movk_i32 s6, 0x7e00
+; SI-NEXT: s_mov_b32 s1, s9
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v1
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NEXT: v_fma_f32 v2, v3, s2, v2
-; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-NEXT: v_fma_f32 v0, v1, s2, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v3
+; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v4
+; SI-NEXT: v_cvt_f64_f32_e32 v[4:5], v5
+; SI-NEXT: v_cvt_f64_f32_e32 v[6:7], v6
+; SI-NEXT: v_fma_f64 v[0:1], v[2:3], s[4:5], v[0:1]
+; SI-NEXT: v_fma_f64 v[2:3], v[6:7], s[4:5], v[4:5]
+; SI-NEXT: v_readfirstlane_b32 s4, v1
+; SI-NEXT: s_and_b32 s5, s4, 0x1ff
+; SI-NEXT: v_or_b32_e32 v0, s5, v0
+; SI-NEXT: s_lshr_b32 s7, s4, 8
+; SI-NEXT: s_bfe_u32 s8, s4, 0xb0014
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: s_and_b32 s5, s7, 0xffe
+; SI-NEXT: s_sub_i32 s7, 0x3f1, s8
+; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; SI-NEXT: v_med3_i32 v1, s7, 0, 13
+; SI-NEXT: v_readfirstlane_b32 s7, v0
+; SI-NEXT: s_or_b32 s5, s5, s7
+; SI-NEXT: v_readfirstlane_b32 s10, v1
+; SI-NEXT: s_or_b32 s7, s5, 0x1000
+; SI-NEXT: s_lshr_b32 s11, s7, s10
+; SI-NEXT: s_lshl_b32 s10, s11, s10
+; SI-NEXT: s_cmp_lg_u32 s10, s7
+; SI-NEXT: s_cselect_b32 s7, 1, 0
+; SI-NEXT: s_addk_i32 s8, 0xfc10
+; SI-NEXT: s_lshl_b32 s10, s8, 12
+; SI-NEXT: s_or_b32 s7, s11, s7
+; SI-NEXT: s_or_b32 s10, s5, s10
+; SI-NEXT: s_cmp_lt_i32 s8, 1
+; SI-NEXT: s_cselect_b32 s7, s7, s10
+; SI-NEXT: s_and_b32 s10, s7, 7
+; SI-NEXT: s_cmp_gt_i32 s10, 5
+; SI-NEXT: s_cselect_b32 s11, 1, 0
+; SI-NEXT: s_cmp_eq_u32 s10, 3
+; SI-NEXT: s_cselect_b32 s10, 1, 0
+; SI-NEXT: s_lshr_b32 s7, s7, 2
+; SI-NEXT: s_or_b32 s10, s10, s11
+; SI-NEXT: s_add_i32 s7, s7, s10
+; SI-NEXT: s_cmp_lt_i32 s8, 31
+; SI-NEXT: s_cselect_b32 s7, s7, 0x7c00
+; SI-NEXT: s_cmp_lg_u32 s5, 0
+; SI-NEXT: v_readfirstlane_b32 s9, v3
+; SI-NEXT: s_cselect_b32 s5, s6, 0x7c00
+; SI-NEXT: s_cmpk_eq_i32 s8, 0x40f
+; SI-NEXT: s_cselect_b32 s5, s5, s7
+; SI-NEXT: s_and_b32 s7, s9, 0x1ff
+; SI-NEXT: v_or_b32_e32 v0, s7, v2
+; SI-NEXT: s_lshr_b32 s4, s4, 16
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: s_lshr_b32 s8, s9, 8
+; SI-NEXT: s_bfe_u32 s10, s9, 0xb0014
+; SI-NEXT: s_and_b32 s4, s4, 0x8000
+; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; SI-NEXT: s_and_b32 s7, s8, 0xffe
+; SI-NEXT: s_sub_i32 s8, 0x3f1, s10
+; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: v_readfirstlane_b32 s5, v0
+; SI-NEXT: v_med3_i32 v1, s8, 0, 13
+; SI-NEXT: s_or_b32 s5, s7, s5
+; SI-NEXT: v_readfirstlane_b32 s8, v1
+; SI-NEXT: s_or_b32 s7, s5, 0x1000
+; SI-NEXT: s_lshr_b32 s11, s7, s8
+; SI-NEXT: s_and_b32 s4, s4, 0xffff
+; SI-NEXT: s_lshl_b32 s8, s11, s8
+; SI-NEXT: s_cmp_lg_u32 s8, s7
+; SI-NEXT: s_cselect_b32 s7, 1, 0
+; SI-NEXT: s_addk_i32 s10, 0xfc10
+; SI-NEXT: s_lshl_b32 s8, s10, 12
+; SI-NEXT: s_or_b32 s7, s11, s7
+; SI-NEXT: s_or_b32 s8, s5, s8
+; SI-NEXT: s_cmp_lt_i32 s10, 1
+; SI-NEXT: s_cselect_b32 s7, s7, s8
+; SI-NEXT: s_and_b32 s8, s7, 7
+; SI-NEXT: s_cmp_gt_i32 s8, 5
+; SI-NEXT: s_cselect_b32 s11, 1, 0
+; SI-NEXT: s_cmp_eq_u32 s8, 3
+; SI-NEXT: s_cselect_b32 s8, 1, 0
+; SI-NEXT: s_lshr_b32 s7, s7, 2
+; SI-NEXT: s_or_b32 s8, s8, s11
+; SI-NEXT: s_add_i32 s7, s7, s8
+; SI-NEXT: s_cmp_lt_i32 s10, 31
+; SI-NEXT: s_cselect_b32 s7, s7, 0x7c00
+; SI-NEXT: s_cmp_lg_u32 s5, 0
+; SI-NEXT: s_cselect_b32 s5, s6, 0x7c00
+; SI-NEXT: s_cmpk_eq_i32 s10, 0x40f
+; SI-NEXT: s_cselect_b32 s5, s5, s7
+; SI-NEXT: s_lshr_b32 s6, s9, 16
+; SI-NEXT: s_and_b32 s6, s6, 0x8000
+; SI-NEXT: s_or_b32 s5, s6, s5
+; SI-NEXT: s_lshl_b32 s5, s5, 16
+; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fma_v2f16_imm_a:
@@ -578,37 +935,125 @@ define amdgpu_kernel void @fma_v2f16_imm_a(
define amdgpu_kernel void @fma_v2f16_imm_b(
; SI-LABEL: fma_v2f16_imm_b:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s10, s6
-; SI-NEXT: s_mov_b32 s11, s7
+; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s14, s2
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s12, s2
-; SI-NEXT: s_mov_b32 s13, s3
-; SI-NEXT: s_mov_b32 s14, s6
-; SI-NEXT: s_mov_b32 s15, s7
-; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
+; SI-NEXT: s_mov_b32 s12, s10
+; SI-NEXT: s_mov_b32 s13, s11
+; SI-NEXT: s_mov_b32 s6, s2
+; SI-NEXT: s_mov_b32 s7, s3
+; SI-NEXT: s_mov_b32 s15, s3
+; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0
; SI-NEXT: buffer_load_dword v1, off, s[12:15], 0
-; SI-NEXT: s_mov_b32 s2, 0x40400000
-; SI-NEXT: s_mov_b32 s4, s0
-; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: s_mov_b32 s4, 0
+; SI-NEXT: s_mov_b32 s5, 0x40080000
+; SI-NEXT: s_mov_b32 s0, s8
+; SI-NEXT: s_movk_i32 s6, 0x7e00
+; SI-NEXT: s_mov_b32 s1, s9
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v1
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NEXT: v_fma_f32 v2, v3, s2, v2
-; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-NEXT: v_fma_f32 v0, v1, s2, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v3
+; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v4
+; SI-NEXT: v_cvt_f64_f32_e32 v[4:5], v5
+; SI-NEXT: v_cvt_f64_f32_e32 v[6:7], v6
+; SI-NEXT: v_fma_f64 v[0:1], v[2:3], s[4:5], v[0:1]
+; SI-NEXT: v_fma_f64 v[2:3], v[6:7], s[4:5], v[4:5]
+; SI-NEXT: v_readfirstlane_b32 s4, v1
+; SI-NEXT: s_and_b32 s5, s4, 0x1ff
+; SI-NEXT: v_or_b32_e32 v0, s5, v0
+; SI-NEXT: s_lshr_b32 s7, s4, 8
+; SI-NEXT: s_bfe_u32 s8, s4, 0xb0014
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: s_and_b32 s5, s7, 0xffe
+; SI-NEXT: s_sub_i32 s7, 0x3f1, s8
+; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; SI-NEXT: v_med3_i32 v1, s7, 0, 13
+; SI-NEXT: v_readfirstlane_b32 s7, v0
+; SI-NEXT: s_or_b32 s5, s5, s7
+; SI-NEXT: v_readfirstlane_b32 s10, v1
+; SI-NEXT: s_or_b32 s7, s5, 0x1000
+; SI-NEXT: s_lshr_b32 s11, s7, s10
+; SI-NEXT: s_lshl_b32 s10, s11, s10
+; SI-NEXT: s_cmp_lg_u32 s10, s7
+; SI-NEXT: s_cselect_b32 s7, 1, 0
+; SI-NEXT: s_addk_i32 s8, 0xfc10
+; SI-NEXT: s_lshl_b32 s10, s8, 12
+; SI-NEXT: s_or_b32 s7, s11, s7
+; SI-NEXT: s_or_b32 s10, s5, s10
+; SI-NEXT: s_cmp_lt_i32 s8, 1
+; SI-NEXT: s_cselect_b32 s7, s7, s10
+; SI-NEXT: s_and_b32 s10, s7, 7
+; SI-NEXT: s_cmp_gt_i32 s10, 5
+; SI-NEXT: s_cselect_b32 s11, 1, 0
+; SI-NEXT: s_cmp_eq_u32 s10, 3
+; SI-NEXT: s_cselect_b32 s10, 1, 0
+; SI-NEXT: s_lshr_b32 s7, s7, 2
+; SI-NEXT: s_or_b32 s10, s10, s11
+; SI-NEXT: s_add_i32 s7, s7, s10
+; SI-NEXT: s_cmp_lt_i32 s8, 31
+; SI-NEXT: s_cselect_b32 s7, s7, 0x7c00
+; SI-NEXT: s_cmp_lg_u32 s5, 0
+; SI-NEXT: v_readfirstlane_b32 s9, v3
+; SI-NEXT: s_cselect_b32 s5, s6, 0x7c00
+; SI-NEXT: s_cmpk_eq_i32 s8, 0x40f
+; SI-NEXT: s_cselect_b32 s5, s5, s7
+; SI-NEXT: s_and_b32 s7, s9, 0x1ff
+; SI-NEXT: v_or_b32_e32 v0, s7, v2
+; SI-NEXT: s_lshr_b32 s4, s4, 16
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: s_lshr_b32 s8, s9, 8
+; SI-NEXT: s_bfe_u32 s10, s9, 0xb0014
+; SI-NEXT: s_and_b32 s4, s4, 0x8000
+; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; SI-NEXT: s_and_b32 s7, s8, 0xffe
+; SI-NEXT: s_sub_i32 s8, 0x3f1, s10
+; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: v_readfirstlane_b32 s5, v0
+; SI-NEXT: v_med3_i32 v1, s8, 0, 13
+; SI-NEXT: s_or_b32 s5, s7, s5
+; SI-NEXT: v_readfirstlane_b32 s8, v1
+; SI-NEXT: s_or_b32 s7, s5, 0x1000
+; SI-NEXT: s_lshr_b32 s11, s7, s8
+; SI-NEXT: s_and_b32 s4, s4, 0xffff
+; SI-NEXT: s_lshl_b32 s8, s11, s8
+; SI-NEXT: s_cmp_lg_u32 s8, s7
+; SI-NEXT: s_cselect_b32 s7, 1, 0
+; SI-NEXT: s_addk_i32 s10, 0xfc10
+; SI-NEXT: s_lshl_b32 s8, s10, 12
+; SI-NEXT: s_or_b32 s7, s11, s7
+; SI-NEXT: s_or_b32 s8, s5, s8
+; SI-NEXT: s_cmp_lt_i32 s10, 1
+; SI-NEXT: s_cselect_b32 s7, s7, s8
+; SI-NEXT: s_and_b32 s8, s7, 7
+; SI-NEXT: s_cmp_gt_i32 s8, 5
+; SI-NEXT: s_cselect_b32 s11, 1, 0
+; SI-NEXT: s_cmp_eq_u32 s8, 3
+; SI-NEXT: s_cselect_b32 s8, 1, 0
+; SI-NEXT: s_lshr_b32 s7, s7, 2
+; SI-NEXT: s_or_b32 s8, s8, s11
+; SI-NEXT: s_add_i32 s7, s7, s8
+; SI-NEXT: s_cmp_lt_i32 s10, 31
+; SI-NEXT: s_cselect_b32 s7, s7, 0x7c00
+; SI-NEXT: s_cmp_lg_u32 s5, 0
+; SI-NEXT: s_cselect_b32 s5, s6, 0x7c00
+; SI-NEXT: s_cmpk_eq_i32 s10, 0x40f
+; SI-NEXT: s_cselect_b32 s5, s5, s7
+; SI-NEXT: s_lshr_b32 s6, s9, 16
+; SI-NEXT: s_and_b32 s6, s6, 0x8000
+; SI-NEXT: s_or_b32 s5, s6, s5
+; SI-NEXT: s_lshl_b32 s5, s5, 16
+; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fma_v2f16_imm_b:
@@ -675,37 +1120,125 @@ define amdgpu_kernel void @fma_v2f16_imm_b(
define amdgpu_kernel void @fma_v2f16_imm_c(
; SI-LABEL: fma_v2f16_imm_c:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s10, s6
-; SI-NEXT: s_mov_b32 s11, s7
+; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s14, s2
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s12, s2
-; SI-NEXT: s_mov_b32 s13, s3
-; SI-NEXT: s_mov_b32 s14, s6
-; SI-NEXT: s_mov_b32 s15, s7
-; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
+; SI-NEXT: s_mov_b32 s12, s10
+; SI-NEXT: s_mov_b32 s13, s11
+; SI-NEXT: s_mov_b32 s6, s2
+; SI-NEXT: s_mov_b32 s7, s3
+; SI-NEXT: s_mov_b32 s15, s3
+; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0
; SI-NEXT: buffer_load_dword v1, off, s[12:15], 0
-; SI-NEXT: s_mov_b32 s2, 0x40400000
-; SI-NEXT: s_mov_b32 s4, s0
-; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: s_mov_b32 s4, 0
+; SI-NEXT: s_mov_b32 s5, 0x40080000
+; SI-NEXT: s_mov_b32 s0, s8
+; SI-NEXT: s_movk_i32 s6, 0x7e00
+; SI-NEXT: s_mov_b32 s1, s9
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f32_f16_e32 v4, v1
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NEXT: v_fma_f32 v2, v3, v2, s2
-; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-NEXT: v_fma_f32 v0, v1, v0, s2
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; SI-NEXT: v_or_b32_e32 v0, v0, v1
-; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-NEXT: v_cvt_f32_f16_e32 v5, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v6, v3
+; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v4
+; SI-NEXT: v_cvt_f64_f32_e32 v[4:5], v5
+; SI-NEXT: v_cvt_f64_f32_e32 v[6:7], v6
+; SI-NEXT: v_fma_f64 v[0:1], v[2:3], v[0:1], s[4:5]
+; SI-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], s[4:5]
+; SI-NEXT: v_readfirstlane_b32 s4, v1
+; SI-NEXT: s_and_b32 s5, s4, 0x1ff
+; SI-NEXT: v_or_b32_e32 v0, s5, v0
+; SI-NEXT: s_lshr_b32 s7, s4, 8
+; SI-NEXT: s_bfe_u32 s8, s4, 0xb0014
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: s_and_b32 s5, s7, 0xffe
+; SI-NEXT: s_sub_i32 s7, 0x3f1, s8
+; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; SI-NEXT: v_med3_i32 v1, s7, 0, 13
+; SI-NEXT: v_readfirstlane_b32 s7, v0
+; SI-NEXT: s_or_b32 s5, s5, s7
+; SI-NEXT: v_readfirstlane_b32 s10, v1
+; SI-NEXT: s_or_b32 s7, s5, 0x1000
+; SI-NEXT: s_lshr_b32 s11, s7, s10
+; SI-NEXT: s_lshl_b32 s10, s11, s10
+; SI-NEXT: s_cmp_lg_u32 s10, s7
+; SI-NEXT: s_cselect_b32 s7, 1, 0
+; SI-NEXT: s_addk_i32 s8, 0xfc10
+; SI-NEXT: s_lshl_b32 s10, s8, 12
+; SI-NEXT: s_or_b32 s7, s11, s7
+; SI-NEXT: s_or_b32 s10, s5, s10
+; SI-NEXT: s_cmp_lt_i32 s8, 1
+; SI-NEXT: s_cselect_b32 s7, s7, s10
+; SI-NEXT: s_and_b32 s10, s7, 7
+; SI-NEXT: s_cmp_gt_i32 s10, 5
+; SI-NEXT: s_cselect_b32 s11, 1, 0
+; SI-NEXT: s_cmp_eq_u32 s10, 3
+; SI-NEXT: s_cselect_b32 s10, 1, 0
+; SI-NEXT: s_lshr_b32 s7, s7, 2
+; SI-NEXT: s_or_b32 s10, s10, s11
+; SI-NEXT: s_add_i32 s7, s7, s10
+; SI-NEXT: s_cmp_lt_i32 s8, 31
+; SI-NEXT: s_cselect_b32 s7, s7, 0x7c00
+; SI-NEXT: s_cmp_lg_u32 s5, 0
+; SI-NEXT: v_readfirstlane_b32 s9, v3
+; SI-NEXT: s_cselect_b32 s5, s6, 0x7c00
+; SI-NEXT: s_cmpk_eq_i32 s8, 0x40f
+; SI-NEXT: s_cselect_b32 s5, s5, s7
+; SI-NEXT: s_and_b32 s7, s9, 0x1ff
+; SI-NEXT: v_or_b32_e32 v0, s7, v2
+; SI-NEXT: s_lshr_b32 s4, s4, 16
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: s_lshr_b32 s8, s9, 8
+; SI-NEXT: s_bfe_u32 s10, s9, 0xb0014
+; SI-NEXT: s_and_b32 s4, s4, 0x8000
+; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; SI-NEXT: s_and_b32 s7, s8, 0xffe
+; SI-NEXT: s_sub_i32 s8, 0x3f1, s10
+; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: v_readfirstlane_b32 s5, v0
+; SI-NEXT: v_med3_i32 v1, s8, 0, 13
+; SI-NEXT: s_or_b32 s5, s7, s5
+; SI-NEXT: v_readfirstlane_b32 s8, v1
+; SI-NEXT: s_or_b32 s7, s5, 0x1000
+; SI-NEXT: s_lshr_b32 s11, s7, s8
+; SI-NEXT: s_and_b32 s4, s4, 0xffff
+; SI-NEXT: s_lshl_b32 s8, s11, s8
+; SI-NEXT: s_cmp_lg_u32 s8, s7
+; SI-NEXT: s_cselect_b32 s7, 1, 0
+; SI-NEXT: s_addk_i32 s10, 0xfc10
+; SI-NEXT: s_lshl_b32 s8, s10, 12
+; SI-NEXT: s_or_b32 s7, s11, s7
+; SI-NEXT: s_or_b32 s8, s5, s8
+; SI-NEXT: s_cmp_lt_i32 s10, 1
+; SI-NEXT: s_cselect_b32 s7, s7, s8
+; SI-NEXT: s_and_b32 s8, s7, 7
+; SI-NEXT: s_cmp_gt_i32 s8, 5
+; SI-NEXT: s_cselect_b32 s11, 1, 0
+; SI-NEXT: s_cmp_eq_u32 s8, 3
+; SI-NEXT: s_cselect_b32 s8, 1, 0
+; SI-NEXT: s_lshr_b32 s7, s7, 2
+; SI-NEXT: s_or_b32 s8, s8, s11
+; SI-NEXT: s_add_i32 s7, s7, s8
+; SI-NEXT: s_cmp_lt_i32 s10, 31
+; SI-NEXT: s_cselect_b32 s7, s7, 0x7c00
+; SI-NEXT: s_cmp_lg_u32 s5, 0
+; SI-NEXT: s_cselect_b32 s5, s6, 0x7c00
+; SI-NEXT: s_cmpk_eq_i32 s10, 0x40f
+; SI-NEXT: s_cselect_b32 s5, s5, s7
+; SI-NEXT: s_lshr_b32 s6, s9, 16
+; SI-NEXT: s_and_b32 s6, s6, 0x8000
+; SI-NEXT: s_or_b32 s5, s6, s5
+; SI-NEXT: s_lshl_b32 s5, s5, 16
+; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fma_v2f16_imm_c:
@@ -787,45 +1320,222 @@ define amdgpu_kernel void @fma_v4f16(
; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s6, s10
+; SI-NEXT: buffer_load_dwordx2 v[5:6], off, s[12:15], 0
; SI-NEXT: s_mov_b32 s7, s11
-; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[12:15], 0
-; SI-NEXT: buffer_load_dwordx2 v[2:3], off, s[16:19], 0
-; SI-NEXT: buffer_load_dwordx2 v[4:5], off, s[4:7], 0
+; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[16:19], 0
+; SI-NEXT: buffer_load_dwordx2 v[2:3], off, s[4:7], 0
; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1
+; SI-NEXT: s_movk_i32 s2, 0x7e00
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_cvt_f32_f16_e32 v6, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_cvt_f32_f16_e32 v7, v1
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v10, v6
; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_cvt_f32_f16_e32 v8, v2
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_cvt_f32_f16_e32 v9, v3
-; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v10, v4
-; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; SI-NEXT: v_cvt_f32_f16_e32 v11, v5
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v3
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v11, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v13, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v15, v5
+; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6
+; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v17, v9
+; SI-NEXT: v_cvt_f32_f16_e32 v18, v8
+; SI-NEXT: v_cvt_f32_f16_e32 v19, v7
+; SI-NEXT: v_cvt_f64_f32_e32 v[5:6], v3
+; SI-NEXT: v_cvt_f64_f32_e32 v[7:8], v1
+; SI-NEXT: v_cvt_f64_f32_e32 v[9:10], v10
+; SI-NEXT: v_cvt_f64_f32_e32 v[11:12], v11
+; SI-NEXT: v_cvt_f64_f32_e32 v[13:14], v13
+; SI-NEXT: v_cvt_f64_f32_e32 v[15:16], v15
+; SI-NEXT: v_fma_f64 v[5:6], v[9:10], v[7:8], v[5:6]
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; SI-NEXT: v_readfirstlane_b32 s0, v6
+; SI-NEXT: v_fma_f64 v[2:3], v[15:16], v[13:14], v[11:12]
+; SI-NEXT: s_and_b32 s3, s0, 0x1ff
+; SI-NEXT: v_readfirstlane_b32 s1, v3
+; SI-NEXT: v_or_b32_e32 v3, s3, v5
+; SI-NEXT: s_lshr_b32 s4, s0, 8
+; SI-NEXT: s_bfe_u32 s5, s0, 0xb0014
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; SI-NEXT: s_and_b32 s3, s4, 0xffe
+; SI-NEXT: s_sub_i32 s4, 0x3f1, s5
+; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; SI-NEXT: v_med3_i32 v5, s4, 0, 13
+; SI-NEXT: v_readfirstlane_b32 s4, v3
+; SI-NEXT: s_or_b32 s3, s3, s4
+; SI-NEXT: v_readfirstlane_b32 s7, v5
+; SI-NEXT: s_or_b32 s4, s3, 0x1000
+; SI-NEXT: s_lshr_b32 s12, s4, s7
+; SI-NEXT: s_lshl_b32 s7, s12, s7
+; SI-NEXT: s_cmp_lg_u32 s7, s4
+; SI-NEXT: s_cselect_b32 s4, 1, 0
+; SI-NEXT: s_addk_i32 s5, 0xfc10
+; SI-NEXT: s_lshl_b32 s7, s5, 12
+; SI-NEXT: s_or_b32 s4, s12, s4
+; SI-NEXT: s_or_b32 s7, s3, s7
+; SI-NEXT: s_cmp_lt_i32 s5, 1
+; SI-NEXT: s_cselect_b32 s4, s4, s7
+; SI-NEXT: s_and_b32 s7, s4, 7
+; SI-NEXT: s_cmp_gt_i32 s7, 5
+; SI-NEXT: v_cvt_f64_f32_e32 v[7:8], v17
+; SI-NEXT: v_cvt_f64_f32_e32 v[9:10], v18
+; SI-NEXT: v_cvt_f64_f32_e32 v[17:18], v19
+; SI-NEXT: s_cselect_b32 s12, 1, 0
+; SI-NEXT: s_cmp_eq_u32 s7, 3
+; SI-NEXT: s_cselect_b32 s7, 1, 0
+; SI-NEXT: s_lshr_b32 s4, s4, 2
+; SI-NEXT: s_or_b32 s7, s7, s12
+; SI-NEXT: s_add_i32 s4, s4, s7
+; SI-NEXT: v_fma_f64 v[7:8], v[17:18], v[9:10], v[7:8]
+; SI-NEXT: s_cmp_lt_i32 s5, 31
+; SI-NEXT: s_cselect_b32 s4, s4, 0x7c00
+; SI-NEXT: s_cmp_lg_u32 s3, 0
+; SI-NEXT: v_readfirstlane_b32 s6, v8
+; SI-NEXT: s_cselect_b32 s3, s2, 0x7c00
+; SI-NEXT: s_cmpk_eq_i32 s5, 0x40f
+; SI-NEXT: s_cselect_b32 s3, s3, s4
+; SI-NEXT: s_and_b32 s4, s6, 0x1ff
+; SI-NEXT: v_or_b32_e32 v3, s4, v7
+; SI-NEXT: s_lshr_b32 s0, s0, 16
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
+; SI-NEXT: s_lshr_b32 s5, s6, 8
+; SI-NEXT: s_bfe_u32 s7, s6, 0xb0014
+; SI-NEXT: s_and_b32 s0, s0, 0x8000
+; SI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; SI-NEXT: s_and_b32 s4, s5, 0xffe
+; SI-NEXT: s_sub_i32 s5, 0x3f1, s7
+; SI-NEXT: s_or_b32 s0, s0, s3
+; SI-NEXT: v_readfirstlane_b32 s3, v3
+; SI-NEXT: v_med3_i32 v5, s5, 0, 13
+; SI-NEXT: s_or_b32 s3, s4, s3
+; SI-NEXT: v_readfirstlane_b32 s5, v5
+; SI-NEXT: s_or_b32 s4, s3, 0x1000
+; SI-NEXT: s_lshr_b32 s12, s4, s5
+; SI-NEXT: s_and_b32 s0, s0, 0xffff
+; SI-NEXT: s_lshl_b32 s5, s12, s5
+; SI-NEXT: s_cmp_lg_u32 s5, s4
+; SI-NEXT: s_cselect_b32 s4, 1, 0
+; SI-NEXT: s_addk_i32 s7, 0xfc10
+; SI-NEXT: s_lshl_b32 s5, s7, 12
+; SI-NEXT: s_or_b32 s4, s12, s4
+; SI-NEXT: s_or_b32 s5, s3, s5
+; SI-NEXT: s_cmp_lt_i32 s7, 1
+; SI-NEXT: s_cselect_b32 s4, s4, s5
+; SI-NEXT: s_and_b32 s5, s4, 7
+; SI-NEXT: s_cmp_gt_i32 s5, 5
+; SI-NEXT: s_cselect_b32 s12, 1, 0
+; SI-NEXT: s_cmp_eq_u32 s5, 3
+; SI-NEXT: s_cselect_b32 s5, 1, 0
+; SI-NEXT: s_lshr_b32 s4, s4, 2
+; SI-NEXT: s_or_b32 s5, s5, s12
+; SI-NEXT: s_add_i32 s4, s4, s5
+; SI-NEXT: s_cmp_lt_i32 s7, 31
+; SI-NEXT: s_cselect_b32 s4, s4, 0x7c00
+; SI-NEXT: s_cmp_lg_u32 s3, 0
+; SI-NEXT: s_cselect_b32 s3, s2, 0x7c00
+; SI-NEXT: s_cmpk_eq_i32 s7, 0x40f
+; SI-NEXT: s_cselect_b32 s3, s3, s4
+; SI-NEXT: s_and_b32 s5, s1, 0x1ff
+; SI-NEXT: s_lshr_b32 s4, s6, 16
+; SI-NEXT: v_or_b32_e32 v2, s5, v2
+; SI-NEXT: s_and_b32 s4, s4, 0x8000
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
+; SI-NEXT: s_lshr_b32 s6, s1, 8
+; SI-NEXT: s_bfe_u32 s7, s1, 0xb0014
+; SI-NEXT: s_or_b32 s3, s4, s3
+; SI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; SI-NEXT: s_and_b32 s5, s6, 0xffe
+; SI-NEXT: s_sub_i32 s6, 0x3f1, s7
+; SI-NEXT: s_lshl_b32 s3, s3, 16
+; SI-NEXT: v_readfirstlane_b32 s4, v2
+; SI-NEXT: v_med3_i32 v3, s6, 0, 13
+; SI-NEXT: s_or_b32 s0, s0, s3
+; SI-NEXT: s_or_b32 s3, s5, s4
+; SI-NEXT: v_readfirstlane_b32 s6, v3
+; SI-NEXT: s_or_b32 s4, s3, 0x1000
+; SI-NEXT: s_lshr_b32 s5, s4, s6
+; SI-NEXT: s_lshl_b32 s6, s5, s6
+; SI-NEXT: s_cmp_lg_u32 s6, s4
+; SI-NEXT: s_cselect_b32 s4, 1, 0
+; SI-NEXT: s_addk_i32 s7, 0xfc10
+; SI-NEXT: s_or_b32 s4, s5, s4
+; SI-NEXT: s_lshl_b32 s5, s7, 12
+; SI-NEXT: s_or_b32 s5, s3, s5
+; SI-NEXT: s_cmp_lt_i32 s7, 1
+; SI-NEXT: s_cselect_b32 s4, s4, s5
+; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: s_and_b32 s5, s4, 7
+; SI-NEXT: s_cmp_gt_i32 s5, 5
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v2, v0
; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-NEXT: v_fma_f32 v7, v7, v9, v11
-; SI-NEXT: v_fma_f32 v6, v6, v8, v10
-; SI-NEXT: v_fma_f32 v1, v1, v3, v5
-; SI-NEXT: v_fma_f32 v0, v0, v2, v4
-; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: v_cvt_f16_f32_e32 v2, v7
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v6
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: v_or_b32_e32 v0, v3, v0
+; SI-NEXT: s_cselect_b32 s6, 1, 0
+; SI-NEXT: s_cmp_eq_u32 s5, 3
+; SI-NEXT: s_cselect_b32 s5, 1, 0
+; SI-NEXT: s_or_b32 s5, s5, s6
+; SI-NEXT: s_lshr_b32 s4, s4, 2
+; SI-NEXT: s_add_i32 s4, s4, s5
+; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v1
+; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
+; SI-NEXT: v_cvt_f64_f32_e32 v[4:5], v4
+; SI-NEXT: s_cmp_lt_i32 s7, 31
+; SI-NEXT: s_cselect_b32 s4, s4, 0x7c00
+; SI-NEXT: s_cmp_lg_u32 s3, 0
+; SI-NEXT: s_cselect_b32 s3, s2, 0x7c00
+; SI-NEXT: s_cmpk_eq_i32 s7, 0x40f
+; SI-NEXT: s_cselect_b32 s3, s3, s4
+; SI-NEXT: s_lshr_b32 s1, s1, 16
+; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[2:3], v[0:1]
+; SI-NEXT: s_and_b32 s1, s1, 0x8000
+; SI-NEXT: s_or_b32 s1, s1, s3
+; SI-NEXT: v_readfirstlane_b32 s3, v1
+; SI-NEXT: s_and_b32 s4, s3, 0x1ff
+; SI-NEXT: v_or_b32_e32 v0, s4, v0
+; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; SI-NEXT: s_lshr_b32 s4, s3, 8
+; SI-NEXT: s_bfe_u32 s6, s3, 0xb0014
+; SI-NEXT: s_and_b32 s4, s4, 0xffe
+; SI-NEXT: v_readfirstlane_b32 s5, v0
+; SI-NEXT: s_sub_i32 s7, 0x3f1, s6
+; SI-NEXT: s_or_b32 s4, s4, s5
+; SI-NEXT: v_med3_i32 v0, s7, 0, 13
+; SI-NEXT: s_or_b32 s5, s4, 0x1000
+; SI-NEXT: v_readfirstlane_b32 s7, v0
+; SI-NEXT: s_lshr_b32 s12, s5, s7
+; SI-NEXT: s_and_b32 s1, s1, 0xffff
+; SI-NEXT: s_lshl_b32 s7, s12, s7
+; SI-NEXT: s_cmp_lg_u32 s7, s5
+; SI-NEXT: s_cselect_b32 s5, 1, 0
+; SI-NEXT: s_addk_i32 s6, 0xfc10
+; SI-NEXT: s_lshl_b32 s7, s6, 12
+; SI-NEXT: s_or_b32 s5, s12, s5
+; SI-NEXT: s_or_b32 s7, s4, s7
+; SI-NEXT: s_cmp_lt_i32 s6, 1
+; SI-NEXT: s_cselect_b32 s5, s5, s7
+; SI-NEXT: s_and_b32 s7, s5, 7
+; SI-NEXT: s_cmp_gt_i32 s7, 5
+; SI-NEXT: s_cselect_b32 s12, 1, 0
+; SI-NEXT: s_cmp_eq_u32 s7, 3
+; SI-NEXT: s_cselect_b32 s7, 1, 0
+; SI-NEXT: s_or_b32 s7, s7, s12
+; SI-NEXT: s_lshr_b32 s5, s5, 2
+; SI-NEXT: s_add_i32 s5, s5, s7
+; SI-NEXT: s_cmp_lt_i32 s6, 31
+; SI-NEXT: s_cselect_b32 s5, s5, 0x7c00
+; SI-NEXT: s_cmp_lg_u32 s4, 0
+; SI-NEXT: s_cselect_b32 s2, s2, 0x7c00
+; SI-NEXT: s_cmpk_eq_i32 s6, 0x40f
+; SI-NEXT: s_cselect_b32 s2, s2, s5
+; SI-NEXT: s_lshr_b32 s3, s3, 16
+; SI-NEXT: s_and_b32 s3, s3, 0x8000
+; SI-NEXT: s_or_b32 s2, s3, s2
+; SI-NEXT: s_lshl_b32 s2, s2, 16
+; SI-NEXT: s_or_b32 s1, s1, s2
+; SI-NEXT: v_mov_b32_e32 v0, s1
+; SI-NEXT: v_mov_b32_e32 v1, s0
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; SI-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
index efb55db486489..e11a8caafc97d 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
@@ -19,32 +19,33 @@ define amdgpu_kernel void @fmuladd_f16(
; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s10, -1
-; SI-NEXT: s_mov_b32 s14, s10
-; SI-NEXT: s_mov_b32 s15, s11
+; SI-NEXT: s_mov_b32 s18, s10
+; SI-NEXT: s_mov_b32 s19, s11
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s12, s2
-; SI-NEXT: s_mov_b32 s13, s3
; SI-NEXT: s_mov_b32 s16, s4
; SI-NEXT: s_mov_b32 s17, s5
-; SI-NEXT: s_mov_b32 s18, s10
-; SI-NEXT: s_mov_b32 s19, s11
-; SI-NEXT: s_mov_b32 s4, s6
-; SI-NEXT: s_mov_b32 s5, s7
-; SI-NEXT: s_mov_b32 s6, s10
-; SI-NEXT: s_mov_b32 s7, s11
-; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0
-; SI-NEXT: buffer_load_ushort v1, off, s[16:19], 0
-; SI-NEXT: buffer_load_ushort v2, off, s[4:7], 0
+; SI-NEXT: s_mov_b32 s14, s10
+; SI-NEXT: s_mov_b32 s12, s2
+; SI-NEXT: s_mov_b32 s13, s3
+; SI-NEXT: s_mov_b32 s15, s11
+; SI-NEXT: buffer_load_ushort v0, off, s[16:19], 0
+; SI-NEXT: buffer_load_ushort v1, off, s[12:15], 0
+; SI-NEXT: s_mov_b32 s12, s6
+; SI-NEXT: s_mov_b32 s13, s7
+; SI-NEXT: buffer_load_ushort v2, off, s[12:15], 0
; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_mul_f32_e32 v0, v1, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NEXT: v_mac_f32_e32 v2, v0, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_add_f32_e32 v0, v0, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
; SI-NEXT: s_endpgm
;
@@ -302,17 +303,20 @@ define amdgpu_kernel void @fmuladd_f16_imm_a(
; SI-NEXT: s_mov_b32 s12, s2
; SI-NEXT: s_mov_b32 s13, s3
; SI-NEXT: s_mov_b32 s15, s7
-; SI-NEXT: s_mov_b32 s10, s6
-; SI-NEXT: s_mov_b32 s11, s7
; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_mov_b32 s10, s6
+; SI-NEXT: s_mov_b32 s11, s7
; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NEXT: v_madmk_f32 v0, v0, 0x40400000, v1
+; SI-NEXT: v_mul_f32_e32 v0, 0x40400000, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_add_f32_e32 v0, v0, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
@@ -534,17 +538,20 @@ define amdgpu_kernel void @fmuladd_f16_imm_b(
; SI-NEXT: s_mov_b32 s12, s2
; SI-NEXT: s_mov_b32 s13, s3
; SI-NEXT: s_mov_b32 s15, s7
-; SI-NEXT: s_mov_b32 s10, s6
-; SI-NEXT: s_mov_b32 s11, s7
; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: s_mov_b32 s10, s6
+; SI-NEXT: s_mov_b32 s11, s7
; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NEXT: v_madmk_f32 v0, v0, 0x40400000, v1
+; SI-NEXT: v_mul_f32_e32 v0, 0x40400000, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_add_f32_e32 v0, v0, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
@@ -769,33 +776,39 @@ define amdgpu_kernel void @fmuladd_v2f16(
; SI-NEXT: s_mov_b32 s17, s5
; SI-NEXT: s_mov_b32 s18, s10
; SI-NEXT: s_mov_b32 s19, s11
+; SI-NEXT: buffer_load_dword v0, off, s[12:15], 0
+; SI-NEXT: buffer_load_dword v1, off, s[16:19], 0
; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s6, s10
-; SI-NEXT: buffer_load_dword v0, off, s[12:15], 0
; SI-NEXT: s_mov_b32 s7, s11
-; SI-NEXT: buffer_load_dword v1, off, s[16:19], 0
; SI-NEXT: buffer_load_dword v2, off, s[4:7], 0
; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1
; SI-NEXT: s_waitcnt vmcnt(2)
-; SI-NEXT: v_cvt_f32_f16_e32 v3, v0
-; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
-; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; SI-NEXT: v_mul_f32_e32 v3, v3, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_mul_f32_e32 v0, v0, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v5
+; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NEXT: v_mac_f32_e32 v5, v0, v4
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v5
-; SI-NEXT: v_mac_f32_e32 v2, v3, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v1, v2
-; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_add_f32_e32 v1, v3, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_add_f32_e32 v0, v0, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; SI-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
index de24617e058dd..69f17ed072425 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
@@ -442,14 +442,14 @@ define amdgpu_kernel void @maxnum_v2f16(
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_lshr_b32 s5, s2, 16
; SI-NEXT: s_lshr_b32 s6, s4, 16
-; SI-NEXT: v_cvt_f32_f16_e32 v0, s5
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s6
-; SI-NEXT: v_cvt_f32_f16_e32 v2, s2
-; SI-NEXT: v_cvt_f32_f16_e32 v3, s4
+; SI-NEXT: v_cvt_f32_f16_e32 v0, s6
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s5
+; SI-NEXT: v_cvt_f32_f16_e32 v2, s4
+; SI-NEXT: v_cvt_f32_f16_e32 v3, s2
; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_max_f32_e32 v0, v0, v1
+; SI-NEXT: v_max_f32_e32 v0, v1, v0
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: v_max_f32_e32 v1, v2, v3
+; SI-NEXT: v_max_f32_e32 v1, v3, v2
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
@@ -731,24 +731,24 @@ define amdgpu_kernel void @maxnum_v3f16(
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v0, s7
-; SI-NEXT: s_lshr_b32 s7, s6, 16
-; SI-NEXT: s_lshr_b32 s8, s4, 16
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s7
+; SI-NEXT: s_lshr_b32 s8, s6, 16
+; SI-NEXT: s_lshr_b32 s9, s4, 16
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s9
; SI-NEXT: v_cvt_f32_f16_e32 v2, s8
+; SI-NEXT: v_cvt_f32_f16_e32 v0, s4
; SI-NEXT: v_cvt_f32_f16_e32 v3, s6
-; SI-NEXT: v_cvt_f32_f16_e32 v4, s4
-; SI-NEXT: v_cvt_f32_f16_e32 v5, s5
-; SI-NEXT: v_max_f32_e32 v1, v1, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v4, s5
+; SI-NEXT: v_cvt_f32_f16_e32 v5, s7
+; SI-NEXT: v_max_f32_e32 v1, v2, v1
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NEXT: v_max_f32_e32 v2, v3, v4
-; SI-NEXT: v_max_f32_e32 v0, v0, v5
-; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_max_f32_e32 v0, v3, v0
+; SI-NEXT: v_max_f32_e32 v2, v5, v4
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v1, v2, v1
-; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:4
-; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; SI-NEXT: v_or_b32_e32 v0, v0, v1
+; SI-NEXT: buffer_store_short v2, off, s[0:3], 0 offset:4
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: maxnum_v3f16:
@@ -859,39 +859,39 @@ define amdgpu_kernel void @maxnum_v4f16(
; SI-LABEL: maxnum_v4f16:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
+; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_load_dwordx2 s[6:7], s[10:11], 0x0
-; SI-NEXT: s_mov_b32 s0, s8
+; SI-NEXT: s_load_dwordx2 s[4:5], s[10:11], 0x0
+; SI-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x0
; SI-NEXT: s_mov_b32 s1, s9
-; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
+; SI-NEXT: s_mov_b32 s0, s8
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v0, s6
-; SI-NEXT: s_lshr_b32 s6, s6, 16
-; SI-NEXT: v_cvt_f32_f16_e32 v2, s6
-; SI-NEXT: s_lshr_b32 s6, s7, 16
-; SI-NEXT: v_cvt_f32_f16_e32 v3, s6
-; SI-NEXT: v_cvt_f32_f16_e32 v4, s4
-; SI-NEXT: s_lshr_b32 s6, s5, 16
-; SI-NEXT: s_lshr_b32 s4, s4, 16
-; SI-NEXT: v_cvt_f32_f16_e32 v5, s6
-; SI-NEXT: v_cvt_f32_f16_e32 v7, s4
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s7
-; SI-NEXT: v_cvt_f32_f16_e32 v6, s5
-; SI-NEXT: v_max_f32_e32 v3, v3, v5
-; SI-NEXT: v_max_f32_e32 v2, v2, v7
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
-; SI-NEXT: v_max_f32_e32 v1, v1, v6
-; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; SI-NEXT: v_max_f32_e32 v0, v0, v4
-; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: s_lshr_b32 s9, s5, 16
+; SI-NEXT: s_lshr_b32 s10, s7, 16
+; SI-NEXT: v_cvt_f32_f16_e32 v0, s10
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s9
+; SI-NEXT: v_cvt_f32_f16_e32 v2, s7
+; SI-NEXT: v_cvt_f32_f16_e32 v3, s5
+; SI-NEXT: s_lshr_b32 s8, s4, 16
+; SI-NEXT: s_lshr_b32 s5, s6, 16
+; SI-NEXT: v_max_f32_e32 v0, v1, v0
+; SI-NEXT: v_max_f32_e32 v1, v3, v2
+; SI-NEXT: v_cvt_f32_f16_e32 v2, s5
+; SI-NEXT: v_cvt_f32_f16_e32 v3, s8
+; SI-NEXT: v_cvt_f32_f16_e32 v4, s6
+; SI-NEXT: v_cvt_f32_f16_e32 v5, s4
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v1, v1, v3
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
+; SI-NEXT: v_max_f32_e32 v2, v3, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; SI-NEXT: v_max_f32_e32 v3, v5, v4
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SI-NEXT: v_or_b32_e32 v1, v1, v0
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
+; SI-NEXT: v_or_b32_e32 v0, v3, v0
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
@@ -1009,24 +1009,24 @@ define amdgpu_kernel void @fmax_v4f16_imm_a(
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v1, s5
-; SI-NEXT: s_lshr_b32 s5, s5, 16
-; SI-NEXT: v_cvt_f32_f16_e32 v0, s4
-; SI-NEXT: s_lshr_b32 s4, s4, 16
-; SI-NEXT: v_cvt_f32_f16_e32 v2, s5
-; SI-NEXT: v_cvt_f32_f16_e32 v3, s4
-; SI-NEXT: v_max_f32_e32 v1, 0x40400000, v1
-; SI-NEXT: v_max_f32_e32 v0, 0x41000000, v0
+; SI-NEXT: s_lshr_b32 s7, s5, 16
+; SI-NEXT: s_lshr_b32 s6, s4, 16
+; SI-NEXT: v_cvt_f32_f16_e32 v2, s7
+; SI-NEXT: v_cvt_f32_f16_e32 v0, s5
+; SI-NEXT: v_cvt_f32_f16_e32 v3, s6
+; SI-NEXT: v_cvt_f32_f16_e32 v1, s4
; SI-NEXT: v_max_f32_e32 v2, 4.0, v2
+; SI-NEXT: v_max_f32_e32 v0, 0x40400000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
; SI-NEXT: v_max_f32_e32 v3, 2.0, v3
-; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_max_f32_e32 v1, 0x41000000, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; SI-NEXT: v_or_b32_e32 v0, v0, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; SI-NEXT: v_cvt_f16_f32_e32 v4, v1
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; SI-NEXT: v_or_b32_e32 v1, v0, v1
+; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v3
+; SI-NEXT: v_or_b32_e32 v0, v4, v0
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
index 56cfec29e4ed2..bc568a357d3bb 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
@@ -143,19 +143,19 @@ define amdgpu_kernel void @sin_v2f16(ptr addrspace(1) %r, ptr addrspace(1) %a) {
; GFX6-NEXT: s_mov_b32 s4, s0
; GFX6-NEXT: s_mov_b32 s5, s1
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v1
; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX6-NEXT: v_mul_f32_e32 v1, 0x3e22f983, v1
-; GFX6-NEXT: v_fract_f32_e32 v1, v1
; GFX6-NEXT: v_mul_f32_e32 v0, 0x3e22f983, v0
+; GFX6-NEXT: v_fract_f32_e32 v1, v1
+; GFX6-NEXT: v_sin_f32_e32 v1, v1
; GFX6-NEXT: v_fract_f32_e32 v0, v0
; GFX6-NEXT: v_sin_f32_e32 v0, v0
-; GFX6-NEXT: v_sin_f32_e32 v1, v1
-; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/omod.ll b/llvm/test/CodeGen/AMDGPU/omod.ll
index 9371ce57dc0fe..7ed68dd6a00fe 100644
--- a/llvm/test/CodeGen/AMDGPU/omod.ll
+++ b/llvm/test/CodeGen/AMDGPU/omod.ll
@@ -1083,11 +1083,12 @@ define amdgpu_ps void @v_omod_mul2_f64_denormals(double %a) #2 {
define amdgpu_ps void @v_omod_div2_f16_denormals(half %a) #0 {
; SI-LABEL: v_omod_div2_f16_denormals:
; SI: ; %bb.0:
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 div:2
+; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e64 v0, v0 div:2
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
@@ -1140,11 +1141,12 @@ define amdgpu_ps void @v_omod_div2_f16_denormals(half %a) #0 {
define amdgpu_ps void @v_omod_mul2_f16_denormals(half %a) #0 {
; SI-LABEL: v_omod_mul2_f16_denormals:
; SI: ; %bb.0:
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:2
+; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e64 v0, v0 mul:2
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
@@ -1196,11 +1198,12 @@ define amdgpu_ps void @v_omod_mul2_f16_denormals(half %a) #0 {
define amdgpu_ps void @v_omod_div2_f16_no_denormals(half %a) #3 {
; SI-LABEL: v_omod_div2_f16_no_denormals:
; SI: ; %bb.0:
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 div:2
+; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e64 v0, v0 div:2
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
index 1222d0efd62bb..4a113f70f1a7d 100644
--- a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.f16.ll
@@ -13,15 +13,12 @@ define half @add_select_fabs_fabs_f16(i32 %c, half %x, half %y, half %z) {
; CI-LABEL: add_select_fabs_fabs_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
; CI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-NEXT: v_add_f32_e64 v0, |v0|, v3
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v3
+; CI-NEXT: v_add_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_fabs_fabs_f16:
@@ -79,18 +76,16 @@ define { half, half } @add_select_multi_use_lhs_fabs_fabs_f16(i32 %c, half %x, h
; CI-LABEL: add_select_multi_use_lhs_fabs_fabs_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v4, v4
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e32 v4, v4
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-NEXT: v_add_f32_e64 v0, |v0|, v4
-; CI-NEXT: v_add_f32_e64 v1, |v1|, v3
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; CI-NEXT: v_cvt_f32_f16_e32 v2, v4
+; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
+; CI-NEXT: v_cvt_f32_f16_e64 v1, |v1|
+; CI-NEXT: v_add_f32_e32 v0, v0, v2
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: v_add_f32_e32 v1, v1, v3
+; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_multi_use_lhs_fabs_fabs_f16:
@@ -156,16 +151,13 @@ define { half, half } @add_select_multi_store_use_lhs_fabs_fabs_f16(i32 %c, half
; CI-LABEL: add_select_multi_store_use_lhs_fabs_fabs_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v4, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; CI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v4
-; CI-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
-; CI-NEXT: v_add_f32_e64 v0, |v0|, v3
+; CI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; CI-NEXT: v_cvt_f32_f16_e32 v2, v3
+; CI-NEXT: v_and_b32_e32 v1, 0x7fff, v1
+; CI-NEXT: v_add_f32_e32 v0, v0, v2
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_multi_store_use_lhs_fabs_fabs_f16:
@@ -231,18 +223,16 @@ define { half, half } @add_select_multi_use_rhs_fabs_fabs_f16(i32 %c, half %x, h
; CI-LABEL: add_select_multi_use_rhs_fabs_fabs_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
-; CI-NEXT: v_cvt_f16_f32_e32 v4, v4
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; CI-NEXT: v_cvt_f32_f16_e32 v4, v4
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-NEXT: v_add_f32_e64 v0, |v0|, v3
-; CI-NEXT: v_add_f32_e64 v1, |v2|, v4
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v3
+; CI-NEXT: v_cvt_f32_f16_e32 v3, v4
+; CI-NEXT: v_cvt_f32_f16_e64 v2, |v2|
+; CI-NEXT: v_add_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: v_add_f32_e32 v1, v2, v3
+; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_multi_use_rhs_fabs_fabs_f16:
@@ -308,15 +298,13 @@ define half @add_select_fabs_var_f16(i32 %c, half %x, half %y, half %z) {
; CI-LABEL: add_select_fabs_var_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; CI-NEXT: v_and_b32_e32 v1, 0x7fff, v1
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e64 v1, |v1|
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
; CI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-NEXT: v_add_f32_e32 v0, v0, v3
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v3
+; CI-NEXT: v_add_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_fabs_var_f16:
@@ -378,13 +366,14 @@ define half @add_select_fabs_negk_f16(i32 %c, half %x, half %y) {
; CI-LABEL: add_select_fabs_negk_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; CI-NEXT: v_and_b32_e32 v1, 0x7fff, v1
+; CI-NEXT: v_mov_b32_e32 v3, 0xffffbc00
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e64 v1, |v1|
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cndmask_b32_e32 v0, -1.0, v1, vcc
-; CI-NEXT: v_add_f32_e32 v0, v0, v2
+; CI-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v2
+; CI-NEXT: v_add_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_fabs_negk_f16:
@@ -448,11 +437,14 @@ define half @add_select_fabs_negk_negk_f16(i32 %c, half %x) {
; CI-LABEL: add_select_fabs_negk_negk_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; CI-NEXT: v_mov_b32_e32 v2, 0xbc00
+; CI-NEXT: v_mov_b32_e32 v3, 0xc000
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cndmask_b32_e64 v0, -1.0, -2.0, vcc
+; CI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_sub_f32_e32 v0, v1, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_fabs_negk_negk_f16:
@@ -515,11 +507,14 @@ define half @add_select_posk_posk_f16(i32 %c, half %x) {
; CI-LABEL: add_select_posk_posk_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; CI-NEXT: v_mov_b32_e32 v2, 0x3c00
+; CI-NEXT: v_mov_b32_e32 v3, 0x4000
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cndmask_b32_e64 v0, 1.0, 2.0, vcc
+; CI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_add_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_posk_posk_f16:
@@ -581,13 +576,14 @@ define half @add_select_negk_fabs_f16(i32 %c, half %x, half %y) {
; CI-LABEL: add_select_negk_fabs_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; CI-NEXT: v_and_b32_e32 v1, 0x7fff, v1
+; CI-NEXT: v_mov_b32_e32 v3, 0xffffbc00
; CI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e64 v1, |v1|
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cndmask_b32_e32 v0, -1.0, v1, vcc
-; CI-NEXT: v_add_f32_e32 v0, v0, v2
+; CI-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v2
+; CI-NEXT: v_add_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_negk_fabs_f16:
@@ -650,14 +646,14 @@ define half @add_select_negliteralk_fabs_f16(i32 %c, half %x, half %y) {
; CI-LABEL: add_select_negliteralk_fabs_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_mov_b32_e32 v3, 0xc4800000
+; CI-NEXT: v_and_b32_e32 v1, 0x7fff, v1
+; CI-NEXT: v_mov_b32_e32 v3, 0xffffe400
; CI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e64 v1, |v1|
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
; CI-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
-; CI-NEXT: v_add_f32_e32 v0, v0, v2
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v2
+; CI-NEXT: v_add_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_negliteralk_fabs_f16:
@@ -720,13 +716,13 @@ define half @add_select_fabs_posk_f16(i32 %c, half %x, half %y) {
; CI-LABEL: add_select_fabs_posk_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; CI-NEXT: v_mov_b32_e32 v3, 0x3c00
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
-; CI-NEXT: v_add_f32_e64 v0, |v0|, v2
+; CI-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v2
+; CI-NEXT: v_add_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_fabs_posk_f16:
@@ -784,13 +780,13 @@ define half @add_select_posk_fabs_f16(i32 %c, half %x, half %y) {
; CI-LABEL: add_select_posk_fabs_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; CI-NEXT: v_mov_b32_e32 v3, 0x3c00
; CI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
-; CI-NEXT: v_add_f32_e64 v0, |v0|, v2
+; CI-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
+; CI-NEXT: v_cvt_f32_f16_e64 v0, |v0|
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v2
+; CI-NEXT: v_add_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_posk_fabs_f16:
@@ -848,15 +844,12 @@ define half @add_select_fneg_fneg_f16(i32 %c, half %x, half %y, half %z) {
; CI-LABEL: add_select_fneg_fneg_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
; CI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-NEXT: v_sub_f32_e32 v0, v3, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v3
+; CI-NEXT: v_sub_f32_e32 v0, v1, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_fneg_fneg_f16:
@@ -914,18 +907,16 @@ define { half, half } @add_select_multi_use_lhs_fneg_fneg_f16(i32 %c, half %x, h
; CI-LABEL: add_select_multi_use_lhs_fneg_fneg_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
-; CI-NEXT: v_cvt_f16_f32_e32 v4, v4
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; CI-NEXT: v_cvt_f32_f16_e32 v4, v4
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-NEXT: v_sub_f32_e32 v0, v3, v0
-; CI-NEXT: v_sub_f32_e32 v1, v4, v1
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v2, v3
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT: v_cvt_f32_f16_e32 v3, v4
+; CI-NEXT: v_sub_f32_e32 v0, v2, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: v_sub_f32_e32 v1, v3, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_multi_use_lhs_fneg_fneg_f16:
@@ -991,16 +982,13 @@ define { half, half } @add_select_multi_store_use_lhs_fneg_fneg_f16(i32 %c, half
; CI-LABEL: add_select_multi_store_use_lhs_fneg_fneg_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v4, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; CI-NEXT: v_cvt_f32_f16_e64 v1, -v1
-; CI-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
-; CI-NEXT: v_sub_f32_e32 v0, v3, v0
+; CI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v2, v3
+; CI-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
+; CI-NEXT: v_sub_f32_e32 v0, v2, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_multi_store_use_lhs_fneg_fneg_f16:
@@ -1066,18 +1054,16 @@ define { half, half } @add_select_multi_use_rhs_fneg_fneg_f16(i32 %c, half %x, h
; CI-LABEL: add_select_multi_use_rhs_fneg_fneg_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
-; CI-NEXT: v_cvt_f16_f32_e32 v4, v4
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; CI-NEXT: v_cvt_f32_f16_e32 v4, v4
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-NEXT: v_sub_f32_e32 v0, v3, v0
-; CI-NEXT: v_sub_f32_e32 v1, v4, v2
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v3
+; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
+; CI-NEXT: v_cvt_f32_f16_e32 v3, v4
+; CI-NEXT: v_sub_f32_e32 v0, v1, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; CI-NEXT: v_sub_f32_e32 v1, v3, v2
+; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_multi_use_rhs_fneg_fneg_f16:
@@ -1143,15 +1129,13 @@ define half @add_select_fneg_var_f16(i32 %c, half %x, half %y, half %z) {
; CI-LABEL: add_select_fneg_var_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e64 v1, -v1
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; CI-NEXT: v_xor_b32_e32 v1, 0x8000, v1
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
; CI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-NEXT: v_add_f32_e32 v0, v0, v3
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v3
+; CI-NEXT: v_add_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_fneg_var_f16:
@@ -1213,13 +1197,13 @@ define half @add_select_fneg_negk_f16(i32 %c, half %x, half %y) {
; CI-LABEL: add_select_fneg_negk_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; CI-NEXT: v_mov_b32_e32 v3, 0x3c00
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
-; CI-NEXT: v_sub_f32_e32 v0, v2, v0
+; CI-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v2
+; CI-NEXT: v_sub_f32_e32 v0, v1, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_fneg_negk_f16:
@@ -1277,14 +1261,13 @@ define half @add_select_fneg_inv2pi_f16(i32 %c, half %x, half %y) {
; CI-LABEL: add_select_fneg_inv2pi_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_mov_b32_e32 v3, 0xbe230000
+; CI-NEXT: v_mov_b32_e32 v3, 0xffffb118
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
; CI-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
-; CI-NEXT: v_sub_f32_e32 v0, v2, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v2
+; CI-NEXT: v_sub_f32_e32 v0, v1, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_fneg_inv2pi_f16:
@@ -1342,14 +1325,13 @@ define half @add_select_fneg_neginv2pi_f16(i32 %c, half %x, half %y) {
; CI-LABEL: add_select_fneg_neginv2pi_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_mov_b32_e32 v3, 0x3e230000
+; CI-NEXT: v_mov_b32_e32 v3, 0x3118
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
; CI-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
-; CI-NEXT: v_sub_f32_e32 v0, v2, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v2
+; CI-NEXT: v_sub_f32_e32 v0, v1, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_fneg_neginv2pi_f16:
@@ -1407,11 +1389,14 @@ define half @add_select_negk_negk_f16(i32 %c, half %x) {
; CI-LABEL: add_select_negk_negk_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; CI-NEXT: v_mov_b32_e32 v2, 0xbc00
+; CI-NEXT: v_mov_b32_e32 v3, 0xc000
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cndmask_b32_e64 v0, -1.0, -2.0, vcc
+; CI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_add_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_negk_negk_f16:
@@ -1473,13 +1458,14 @@ define half @add_select_negliteralk_negliteralk_f16(i32 %c, half %x) {
; CI-LABEL: add_select_negliteralk_negliteralk_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_mov_b32_e32 v2, 0xc5800000
-; CI-NEXT: v_mov_b32_e32 v3, 0xc5000000
+; CI-NEXT: v_mov_b32_e32 v2, 0xec00
+; CI-NEXT: v_mov_b32_e32 v3, 0xe800
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_add_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_negliteralk_negliteralk_f16:
@@ -1541,11 +1527,14 @@ define half @add_select_fneg_negk_negk_f16(i32 %c, half %x) {
; CI-LABEL: add_select_fneg_negk_negk_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; CI-NEXT: v_mov_b32_e32 v2, 0xbc00
+; CI-NEXT: v_mov_b32_e32 v3, 0xc000
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cndmask_b32_e64 v0, -1.0, -2.0, vcc
+; CI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: v_sub_f32_e32 v0, v1, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_fneg_negk_negk_f16:
@@ -1608,13 +1597,13 @@ define half @add_select_negk_fneg_f16(i32 %c, half %x, half %y) {
; CI-LABEL: add_select_negk_fneg_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; CI-NEXT: v_mov_b32_e32 v3, 0x3c00
; CI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
-; CI-NEXT: v_sub_f32_e32 v0, v2, v0
+; CI-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v2
+; CI-NEXT: v_sub_f32_e32 v0, v1, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_negk_fneg_f16:
@@ -1672,13 +1661,13 @@ define half @add_select_fneg_posk_f16(i32 %c, half %x, half %y) {
; CI-LABEL: add_select_fneg_posk_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; CI-NEXT: v_mov_b32_e32 v3, 0xffffbc00
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cndmask_b32_e32 v0, -1.0, v1, vcc
-; CI-NEXT: v_sub_f32_e32 v0, v2, v0
+; CI-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v2
+; CI-NEXT: v_sub_f32_e32 v0, v1, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_fneg_posk_f16:
@@ -1736,13 +1725,13 @@ define half @add_select_posk_fneg_f16(i32 %c, half %x, half %y) {
; CI-LABEL: add_select_posk_fneg_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; CI-NEXT: v_mov_b32_e32 v3, 0xffffbc00
; CI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cndmask_b32_e32 v0, -1.0, v1, vcc
-; CI-NEXT: v_sub_f32_e32 v0, v2, v0
+; CI-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v2
+; CI-NEXT: v_sub_f32_e32 v0, v1, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_posk_fneg_f16:
@@ -1800,15 +1789,14 @@ define half @add_select_negfabs_fabs_f16(i32 %c, half %x, half %y, half %z) {
; CI-LABEL: add_select_negfabs_fabs_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; CI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
+; CI-NEXT: v_or_b32_e32 v1, 0x8000, v1
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e64 v1, -|v1|
-; CI-NEXT: v_cvt_f32_f16_e64 v2, |v2|
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
; CI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-NEXT: v_add_f32_e32 v0, v0, v3
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v3
+; CI-NEXT: v_add_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_negfabs_fabs_f16:
@@ -1877,15 +1865,14 @@ define half @add_select_fabs_negfabs_f16(i32 %c, half %x, half %y, half %z) {
; CI-LABEL: add_select_fabs_negfabs_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; CI-NEXT: v_and_b32_e32 v1, 0x7fff, v1
+; CI-NEXT: v_or_b32_e32 v2, 0x8000, v2
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e64 v1, |v1|
-; CI-NEXT: v_cvt_f32_f16_e64 v2, -|v2|
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
; CI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-NEXT: v_add_f32_e32 v0, v0, v3
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v3
+; CI-NEXT: v_add_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_fabs_negfabs_f16:
@@ -1954,15 +1941,14 @@ define half @add_select_neg_fabs_f16(i32 %c, half %x, half %y, half %z) {
; CI-LABEL: add_select_neg_fabs_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e64 v1, -v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; CI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
+; CI-NEXT: v_xor_b32_e32 v1, 0x8000, v1
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e64 v2, |v2|
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
; CI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-NEXT: v_add_f32_e32 v0, v0, v3
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v3
+; CI-NEXT: v_add_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_neg_fabs_f16:
@@ -2030,15 +2016,14 @@ define half @add_select_fabs_neg_f16(i32 %c, half %x, half %y, half %z) {
; CI-LABEL: add_select_fabs_neg_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e64 v2, -v2
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; CI-NEXT: v_and_b32_e32 v1, 0x7fff, v1
+; CI-NEXT: v_xor_b32_e32 v2, 0x8000, v2
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e64 v1, |v1|
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
; CI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-NEXT: v_add_f32_e32 v0, v0, v3
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v3
+; CI-NEXT: v_add_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_fabs_neg_f16:
@@ -2106,15 +2091,13 @@ define half @add_select_neg_negfabs_f16(i32 %c, half %x, half %y, half %z) {
; CI-LABEL: add_select_neg_negfabs_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; CI-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e64 v2, |v2|
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
; CI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
-; CI-NEXT: v_sub_f32_e32 v0, v3, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v3
+; CI-NEXT: v_sub_f32_e32 v0, v1, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_neg_negfabs_f16:
@@ -2178,15 +2161,13 @@ define half @add_select_negfabs_neg_f16(i32 %c, half %x, half %y, half %z) {
; CI-LABEL: add_select_negfabs_neg_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
+; CI-NEXT: v_and_b32_e32 v1, 0x7fff, v1
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e64 v1, |v1|
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
; CI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
-; CI-NEXT: v_sub_f32_e32 v0, v3, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v3
+; CI-NEXT: v_sub_f32_e32 v0, v1, v0
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: add_select_negfabs_neg_f16:
@@ -2250,13 +2231,14 @@ define half @mul_select_negfabs_posk_f16(i32 %c, half %x, half %y) {
; CI-LABEL: mul_select_negfabs_posk_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; CI-NEXT: v_or_b32_e32 v1, 0x8000, v1
+; CI-NEXT: v_mov_b32_e32 v3, 0x4400
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e64 v1, -|v1|
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cndmask_b32_e32 v0, 4.0, v1, vcc
-; CI-NEXT: v_mul_f32_e32 v0, v0, v2
+; CI-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v2
+; CI-NEXT: v_mul_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: mul_select_negfabs_posk_f16:
@@ -2320,13 +2302,14 @@ define half @mul_select_posk_negfabs_f16(i32 %c, half %x, half %y) {
; CI-LABEL: mul_select_posk_negfabs_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; CI-NEXT: v_or_b32_e32 v1, 0x8000, v1
+; CI-NEXT: v_mov_b32_e32 v3, 0x4400
; CI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e64 v1, -|v1|
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cndmask_b32_e32 v0, 4.0, v1, vcc
-; CI-NEXT: v_mul_f32_e32 v0, v0, v2
+; CI-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v2
+; CI-NEXT: v_mul_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: mul_select_posk_negfabs_f16:
@@ -2390,13 +2373,14 @@ define half @mul_select_negfabs_negk_f16(i32 %c, half %x, half %y) {
; CI-LABEL: mul_select_negfabs_negk_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; CI-NEXT: v_or_b32_e32 v1, 0x8000, v1
+; CI-NEXT: v_mov_b32_e32 v3, 0xffffc400
; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e64 v1, -|v1|
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cndmask_b32_e32 v0, -4.0, v1, vcc
-; CI-NEXT: v_mul_f32_e32 v0, v0, v2
+; CI-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v2
+; CI-NEXT: v_mul_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: mul_select_negfabs_negk_f16:
@@ -2460,13 +2444,14 @@ define half @mul_select_negk_negfabs_f16(i32 %c, half %x, half %y) {
; CI-LABEL: mul_select_negk_negfabs_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
+; CI-NEXT: v_or_b32_e32 v1, 0x8000, v1
+; CI-NEXT: v_mov_b32_e32 v3, 0xffffc400
; CI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
-; CI-NEXT: v_cvt_f32_f16_e64 v1, -|v1|
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cndmask_b32_e32 v0, -4.0, v1, vcc
-; CI-NEXT: v_mul_f32_e32 v0, v0, v2
+; CI-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
+; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; CI-NEXT: v_cvt_f32_f16_e32 v1, v2
+; CI-NEXT: v_mul_f32_e32 v0, v0, v1
+; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: mul_select_negk_negfabs_f16:
@@ -2534,11 +2519,13 @@ define half @select_fneg_posk_src_add_f16(i32 %c, half %x, half %y) {
; CI-SAFE-LABEL: select_fneg_posk_src_add_f16:
; CI-SAFE: ; %bb.0:
; CI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000
+; CI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-SAFE-NEXT: v_add_f32_e32 v1, 4.0, v1
-; CI-SAFE-NEXT: v_cndmask_b32_e64 v0, 2.0, -v1, vcc
+; CI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
+; CI-SAFE-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
+; CI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; CI-SAFE-NEXT: s_setpc_b64 s[30:31]
;
; VI-SAFE-LABEL: select_fneg_posk_src_add_f16:
@@ -2574,11 +2561,12 @@ define half @select_fneg_posk_src_add_f16(i32 %c, half %x, half %y) {
; CI-NSZ-LABEL: select_fneg_posk_src_add_f16:
; CI-NSZ: ; %bb.0:
; CI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-NSZ-NEXT: v_mov_b32_e32 v2, 0x4000
+; CI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-NSZ-NEXT: v_sub_f32_e32 v1, -4.0, v1
-; CI-NSZ-NEXT: v_cndmask_b32_e32 v0, 2.0, v1, vcc
+; CI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
+; CI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; CI-NSZ-NEXT: s_setpc_b64 s[30:31]
;
; VI-NSZ-LABEL: select_fneg_posk_src_add_f16:
@@ -2618,11 +2606,13 @@ define half @select_fneg_posk_src_sub_f16(i32 %c, half %x) {
; CI-SAFE-LABEL: select_fneg_posk_src_sub_f16:
; CI-SAFE: ; %bb.0:
; CI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000
+; CI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-SAFE-NEXT: v_add_f32_e32 v1, -4.0, v1
-; CI-SAFE-NEXT: v_cndmask_b32_e64 v0, 2.0, -v1, vcc
+; CI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
+; CI-SAFE-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
+; CI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; CI-SAFE-NEXT: s_setpc_b64 s[30:31]
;
; VI-SAFE-LABEL: select_fneg_posk_src_sub_f16:
@@ -2658,11 +2648,12 @@ define half @select_fneg_posk_src_sub_f16(i32 %c, half %x) {
; CI-NSZ-LABEL: select_fneg_posk_src_sub_f16:
; CI-NSZ: ; %bb.0:
; CI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-NSZ-NEXT: v_mov_b32_e32 v2, 0x4000
+; CI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-NSZ-NEXT: v_sub_f32_e32 v1, 4.0, v1
-; CI-NSZ-NEXT: v_cndmask_b32_e32 v0, 2.0, v1, vcc
+; CI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
+; CI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; CI-NSZ-NEXT: s_setpc_b64 s[30:31]
;
; VI-NSZ-LABEL: select_fneg_posk_src_sub_f16:
@@ -2702,11 +2693,12 @@ define half @select_fneg_posk_src_mul_f16(i32 %c, half %x) {
; CI-LABEL: select_fneg_posk_src_mul_f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; CI-NEXT: v_mov_b32_e32 v2, 0x4000
+; CI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-NEXT: v_mul_f32_e32 v1, -4.0, v1
-; CI-NEXT: v_cndmask_b32_e32 v0, 2.0, v1, vcc
+; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; CI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; CI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: select_fneg_posk_src_mul_f16:
@@ -2764,13 +2756,58 @@ define half @select_fneg_posk_src_fma_f16(i32 %c, half %x, half %z) {
; CI-SAFE-LABEL: select_fneg_posk_src_fma_f16:
; CI-SAFE: ; %bb.0:
; CI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-SAFE-NEXT: v_fma_f32 v1, v1, 4.0, v2
-; CI-SAFE-NEXT: v_cndmask_b32_e64 v0, 2.0, -v1, vcc
+; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v3, v1
+; CI-SAFE-NEXT: s_movk_i32 s4, 0x3f1
+; CI-SAFE-NEXT: v_cvt_f64_f32_e32 v[1:2], v2
+; CI-SAFE-NEXT: v_cvt_f64_f32_e32 v[3:4], v3
+; CI-SAFE-NEXT: v_fma_f64 v[1:2], v[3:4], 4.0, v[1:2]
+; CI-SAFE-NEXT: v_and_b32_e32 v3, 0x1ff, v2
+; CI-SAFE-NEXT: v_or_b32_e32 v1, v3, v1
+; CI-SAFE-NEXT: v_lshrrev_b32_e32 v4, 8, v2
+; CI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; CI-SAFE-NEXT: v_and_b32_e32 v3, 0xffe, v4
+; CI-SAFE-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; CI-SAFE-NEXT: v_bfe_u32 v4, v2, 20, 11
+; CI-SAFE-NEXT: v_or_b32_e32 v1, v3, v1
+; CI-SAFE-NEXT: v_sub_i32_e32 v5, vcc, s4, v4
+; CI-SAFE-NEXT: v_or_b32_e32 v3, 0x1000, v1
+; CI-SAFE-NEXT: v_med3_i32 v5, v5, 0, 13
+; CI-SAFE-NEXT: v_lshrrev_b32_e32 v6, v5, v3
+; CI-SAFE-NEXT: v_lshlrev_b32_e32 v5, v5, v6
+; CI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, v5, v3
+; CI-SAFE-NEXT: s_movk_i32 s4, 0xfc10
+; CI-SAFE-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; CI-SAFE-NEXT: v_add_i32_e32 v4, vcc, s4, v4
+; CI-SAFE-NEXT: v_lshlrev_b32_e32 v5, 12, v4
+; CI-SAFE-NEXT: v_or_b32_e32 v3, v6, v3
+; CI-SAFE-NEXT: v_or_b32_e32 v5, v1, v5
+; CI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
+; CI-SAFE-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; CI-SAFE-NEXT: v_and_b32_e32 v5, 7, v3
+; CI-SAFE-NEXT: v_cmp_lt_i32_e32 vcc, 5, v5
+; CI-SAFE-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; CI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 3, v5
+; CI-SAFE-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; CI-SAFE-NEXT: v_or_b32_e32 v5, v5, v6
+; CI-SAFE-NEXT: v_lshrrev_b32_e32 v3, 2, v3
+; CI-SAFE-NEXT: v_add_i32_e32 v3, vcc, v3, v5
+; CI-SAFE-NEXT: v_mov_b32_e32 v5, 0x7c00
+; CI-SAFE-NEXT: v_cmp_gt_i32_e32 vcc, 31, v4
+; CI-SAFE-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; CI-SAFE-NEXT: v_mov_b32_e32 v6, 0x7e00
+; CI-SAFE-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; CI-SAFE-NEXT: s_movk_i32 s4, 0x40f
+; CI-SAFE-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
+; CI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, s4, v4
+; CI-SAFE-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; CI-SAFE-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; CI-SAFE-NEXT: v_and_b32_e32 v2, 0x8000, v2
+; CI-SAFE-NEXT: v_or_b32_e32 v1, v2, v1
+; CI-SAFE-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
+; CI-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000
+; CI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; CI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; CI-SAFE-NEXT: s_setpc_b64 s[30:31]
;
; VI-SAFE-LABEL: select_fneg_posk_src_fma_f16:
@@ -2806,13 +2843,57 @@ define half @select_fneg_posk_src_fma_f16(i32 %c, half %x, half %z) {
; CI-NSZ-LABEL: select_fneg_posk_src_fma_f16:
; CI-NSZ: ; %bb.0:
; CI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NSZ-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
+; CI-NSZ-NEXT: v_cvt_f32_f16_e64 v2, -v2
+; CI-NSZ-NEXT: v_cvt_f32_f16_e32 v3, v1
+; CI-NSZ-NEXT: s_movk_i32 s4, 0x3f1
+; CI-NSZ-NEXT: v_cvt_f64_f32_e32 v[1:2], v2
+; CI-NSZ-NEXT: v_cvt_f64_f32_e32 v[3:4], v3
+; CI-NSZ-NEXT: v_fma_f64 v[1:2], v[3:4], -4.0, v[1:2]
+; CI-NSZ-NEXT: v_and_b32_e32 v3, 0x1ff, v2
+; CI-NSZ-NEXT: v_or_b32_e32 v1, v3, v1
+; CI-NSZ-NEXT: v_lshrrev_b32_e32 v4, 8, v2
+; CI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; CI-NSZ-NEXT: v_and_b32_e32 v3, 0xffe, v4
+; CI-NSZ-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; CI-NSZ-NEXT: v_bfe_u32 v4, v2, 20, 11
+; CI-NSZ-NEXT: v_or_b32_e32 v1, v3, v1
+; CI-NSZ-NEXT: v_sub_i32_e32 v5, vcc, s4, v4
+; CI-NSZ-NEXT: v_or_b32_e32 v3, 0x1000, v1
+; CI-NSZ-NEXT: v_med3_i32 v5, v5, 0, 13
+; CI-NSZ-NEXT: v_lshrrev_b32_e32 v6, v5, v3
+; CI-NSZ-NEXT: v_lshlrev_b32_e32 v5, v5, v6
+; CI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, v5, v3
+; CI-NSZ-NEXT: s_movk_i32 s4, 0xfc10
+; CI-NSZ-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; CI-NSZ-NEXT: v_add_i32_e32 v4, vcc, s4, v4
+; CI-NSZ-NEXT: v_lshlrev_b32_e32 v5, 12, v4
+; CI-NSZ-NEXT: v_or_b32_e32 v3, v6, v3
+; CI-NSZ-NEXT: v_or_b32_e32 v5, v1, v5
+; CI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
+; CI-NSZ-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; CI-NSZ-NEXT: v_and_b32_e32 v5, 7, v3
+; CI-NSZ-NEXT: v_cmp_lt_i32_e32 vcc, 5, v5
+; CI-NSZ-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; CI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 3, v5
+; CI-NSZ-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; CI-NSZ-NEXT: v_or_b32_e32 v5, v5, v6
+; CI-NSZ-NEXT: v_lshrrev_b32_e32 v3, 2, v3
+; CI-NSZ-NEXT: v_add_i32_e32 v3, vcc, v3, v5
+; CI-NSZ-NEXT: v_mov_b32_e32 v5, 0x7c00
+; CI-NSZ-NEXT: v_cmp_gt_i32_e32 vcc, 31, v4
+; CI-NSZ-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; CI-NSZ-NEXT: v_mov_b32_e32 v6, 0x7e00
+; CI-NSZ-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; CI-NSZ-NEXT: s_movk_i32 s4, 0x40f
+; CI-NSZ-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
+; CI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, s4, v4
+; CI-NSZ-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; CI-NSZ-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; CI-NSZ-NEXT: v_and_b32_e32 v2, 0x8000, v2
+; CI-NSZ-NEXT: v_or_b32_e32 v1, v2, v1
+; CI-NSZ-NEXT: v_mov_b32_e32 v2, 0x4000
; CI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; CI-NSZ-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NSZ-NEXT: v_fma_f32 v1, v1, -4.0, -v2
-; CI-NSZ-NEXT: v_cndmask_b32_e32 v0, 2.0, v1, vcc
+; CI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; CI-NSZ-NEXT: s_setpc_b64 s[30:31]
;
; VI-NSZ-LABEL: select_fneg_posk_src_fma_f16:
@@ -2852,14 +2933,17 @@ define half @select_fneg_posk_src_fmad_f16(i32 %c, half %x, half %z) {
; CI-SAFE-LABEL: select_fneg_posk_src_fmad_f16:
; CI-SAFE: ; %bb.0:
; CI-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-SAFE-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v2, v2
+; CI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-SAFE-NEXT: v_mul_f32_e32 v1, 4.0, v1
+; CI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
+; CI-SAFE-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-SAFE-NEXT: v_add_f32_e32 v1, v1, v2
-; CI-SAFE-NEXT: v_cndmask_b32_e64 v0, 2.0, -v1, vcc
+; CI-SAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
+; CI-SAFE-NEXT: v_mov_b32_e32 v2, 0x4000
+; CI-SAFE-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
+; CI-SAFE-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; CI-SAFE-NEXT: s_setpc_b64 s[30:31]
;
; VI-SAFE-LABEL: select_fneg_posk_src_fmad_f16:
@@ -2895,14 +2979,16 @@ define half @select_fneg_posk_src_fmad_f16(i32 %c, half %x, half %z) {
; CI-NSZ-LABEL: select_fneg_posk_src_fmad_f16:
; CI-NSZ: ; %bb.0:
; CI-NSZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NSZ-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NSZ-NEXT: v_cvt_f32_f16_e32 v2, v2
+; CI-NSZ-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; CI-NSZ-NEXT: v_mul_f32_e32 v1, -4.0, v1
+; CI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
+; CI-NSZ-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NSZ-NEXT: v_sub_f32_e32 v1, v1, v2
-; CI-NSZ-NEXT: v_cndmask_b32_e32 v0, 2.0, v1, vcc
+; CI-NSZ-NEXT: v_cvt_f16_f32_e32 v1, v1
+; CI-NSZ-NEXT: v_mov_b32_e32 v2, 0x4000
+; CI-NSZ-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; CI-NSZ-NEXT: s_setpc_b64 s[30:31]
;
; VI-NSZ-LABEL: select_fneg_posk_src_fmad_f16:
diff --git a/llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll b/llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll
index ba04cdb795ce3..563e95f7f55b5 100644
--- a/llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-phi-s16-fp.ll
@@ -15,14 +15,12 @@ define void @phi_vec1half_to_f32_with_const_folding(ptr addrspace(1) %dst) #0 {
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_mov_b32 s4, 0
; CHECK-NEXT: ; %bb.1: ; %bb
-; CHECK-NEXT: v_cvt_f16_f32_e64 v2, s4
-; CHECK-NEXT: s_mov_b32 s7, 0xf000
-; CHECK-NEXT: s_mov_b32 s6, 0
-; CHECK-NEXT: s_mov_b32 s4, s6
-; CHECK-NEXT: s_mov_b32 s5, s6
-; CHECK-NEXT: buffer_store_short v2, v[0:1], s[4:7], 0 addr64 offset:2
-; CHECK-NEXT: v_cvt_f16_f32_e64 v2, s4
-; CHECK-NEXT: buffer_store_short v2, v[0:1], s[4:7], 0 addr64
+; CHECK-NEXT: s_mov_b32 s11, 0xf000
+; CHECK-NEXT: s_mov_b32 s10, 0
+; CHECK-NEXT: s_mov_b32 s8, s10
+; CHECK-NEXT: s_mov_b32 s9, s10
+; CHECK-NEXT: v_mov_b32_e32 v2, s4
+; CHECK-NEXT: buffer_store_short v2, v[0:1], s[8:11], 0 addr64 offset:2
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31]
entry:
@@ -48,17 +46,13 @@ define void @phi_vec1half_to_f32(ptr addrspace(1) %src, ptr addrspace(1) %dst) #
; CHECK-NEXT: s_mov_b32 s4, s6
; CHECK-NEXT: s_mov_b32 s5, s6
; CHECK-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64
-; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: v_cvt_f32_f16_e64 v0, v0
; CHECK-NEXT: ; %bb.1: ; %bb
-; CHECK-NEXT: v_cvt_f16_f32_e64 v0, v0
; CHECK-NEXT: s_mov_b32 s7, 0xf000
; CHECK-NEXT: s_mov_b32 s6, 0
; CHECK-NEXT: s_mov_b32 s4, s6
; CHECK-NEXT: s_mov_b32 s5, s6
+; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: buffer_store_short v0, v[2:3], s[4:7], 0 addr64 offset:2
-; CHECK-NEXT: v_cvt_f16_f32_e64 v0, s4
-; CHECK-NEXT: buffer_store_short v0, v[2:3], s[4:7], 0 addr64
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31]
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/v_cndmask.ll b/llvm/test/CodeGen/AMDGPU/v_cndmask.ll
index ca93fcf3f55a2..c3a7e2ae4f344 100644
--- a/llvm/test/CodeGen/AMDGPU/v_cndmask.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_cndmask.ll
@@ -2175,11 +2175,10 @@ define amdgpu_kernel void @v_cndmask_abs_neg_f16(ptr addrspace(1) %out, i32 %c,
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_cmp_lg_u32 s8, 0
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e64 v1, |v0|
-; SI-NEXT: v_cvt_f32_f16_e64 v0, -v0
+; SI-NEXT: v_and_b32_e32 v1, 0x7fff, v0
+; SI-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; SI-NEXT: s_cselect_b64 vcc, -1, 0
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/v_madak_f16.ll b/llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
index 3afe55fc93423..b675e0ffe9eed 100644
--- a/llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
@@ -11,22 +11,25 @@ define amdgpu_kernel void @madak_f16(
; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s14, s6
+; SI-NEXT: s_mov_b32 s10, s6
+; SI-NEXT: s_mov_b32 s11, s7
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s12, s2
; SI-NEXT: s_mov_b32 s13, s3
+; SI-NEXT: s_mov_b32 s14, s6
; SI-NEXT: s_mov_b32 s15, s7
-; SI-NEXT: s_mov_b32 s10, s6
-; SI-NEXT: s_mov_b32 s11, s7
-; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0
-; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
+; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
+; SI-NEXT: buffer_load_ushort v1, off, s[12:15], 0
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NEXT: v_madak_f32 v0, v0, v1, 0x41200000
+; SI-NEXT: v_mul_f32_e32 v0, v1, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_add_f32_e32 v0, 0x41200000, v0
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
@@ -140,7 +143,6 @@ define amdgpu_kernel void @madak_f16_use_2(
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_mov_b32_e32 v3, 0x41200000
; SI-NEXT: s_mov_b32 s0, s8
; SI-NEXT: s_mov_b32 s1, s9
; SI-NEXT: s_mov_b32 s4, s10
@@ -148,12 +150,18 @@ define amdgpu_kernel void @madak_f16_use_2(
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; SI-NEXT: v_madak_f32 v1, v0, v1, 0x41200000
-; SI-NEXT: v_mac_f32_e32 v3, v0, v2
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v1, v3
-; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
-; SI-NEXT: buffer_store_short v1, off, s[4:7], 0
+; SI-NEXT: v_mul_f32_e32 v1, v0, v1
+; SI-NEXT: v_mul_f32_e32 v0, v0, v2
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-NEXT: v_add_f32_e32 v1, 0x41200000, v1
+; SI-NEXT: v_add_f32_e32 v0, 0x41200000, v0
+; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
+; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-NEXT: buffer_store_short v1, off, s[0:3], 0
+; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: madak_f16_use_2:
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