[llvm] [SDAG] fix miss opt: shl nuw + zext adds unnecessary masking (PR #172046)

[via llvm-commits]

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@@ -1572,6 +1572,9 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) {
   assert(VT.bitsLE(OpVT) && "Not extending!");
   if (OpVT == VT)
     return Op;
+  if (Op.getOpcode() == ISD::AssertZext &&
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actinks wrote:

All the changes are required to achieve the original goal, which is to optimize the test case I added in the pre-commit: llvm/test/CodeGen/X86/pr172046.ll. They are not limited to just the changes introduced by getZeroExtendInReg.

https://github.com/llvm/llvm-project/pull/172046