[llvm] [VectorCombine] Fold vector sign-bit checks (PR #175194)

[Yingwei Zheng via llvm-commits]

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@@ -3806,6 +3807,216 @@ bool VectorCombine::foldCastFromReductions(Instruction &I) {
   return true;
 }
 
+/// Fold:
+///   icmp pred (reduce.{add,or,and,umax,umin}(signbit_extract(x))), C
+/// into:
+///   icmp sgt/slt (reduce.{or,umax,and,umin}(x)), -1/0
+///
+/// Sign-bit reductions produce values with known semantics:
+///   - reduce.{or,umax}: 0 if no element is negative, 1 if any is
+///   - reduce.{and,umin}: 1 if all elements are negative, 0 if any isn't
+///   - reduce.add: count of negative elements (0 to NumElts)
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dtcxzyw wrote:

It is a bit weird to use `reduce.add` for sign bit checking. Can you share some real-world cases? Is it generated by auto-vectorization?

https://github.com/llvm/llvm-project/pull/175194