[llvm] [RISCV] Add Zbb to P extension SIMD tests. NFC (PR #175378)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Jan 10 11:16:11 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
It's likely the P extension will depend on Zbb and this improves the code.
---
Patch is 27.69 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/175378.diff
2 Files Affected:
- (modified) llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll (+122-148)
- (modified) llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll (+95-97)
``````````diff
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
index 6497203c70c73..ed89084537051 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv32.ll
@@ -1,6 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-p,+m -riscv-enable-p-ext-simd-codegen -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECK-RV32 %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+m -riscv-enable-p-ext-simd-codegen -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECK-RV64 %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-p,+m,+zbb \
+; RUN: -riscv-enable-p-ext-simd-codegen -verify-machineinstrs < %s | \
+; RUN: FileCheck --check-prefixes=CHECK,CHECK-RV32 %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb \
+; RUN: -riscv-enable-p-ext-simd-codegen -verify-machineinstrs < %s | \
+; RUN: FileCheck --check-prefixes=CHECK,CHECK-RV64 %s
; Test basic add/sub operations for v2i16
define void @test_padd_h(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
@@ -989,9 +993,8 @@ define void @test_psrl_hs_vec_shamt(ptr %ret_ptr, ptr %a_ptr, ptr %shamt_ptr) {
; CHECK-RV32-NEXT: lw a1, 0(a1)
; CHECK-RV32-NEXT: srli a3, a2, 16
; CHECK-RV32-NEXT: srli a4, a1, 16
-; CHECK-RV32-NEXT: slli a1, a1, 16
+; CHECK-RV32-NEXT: zext.h a1, a1
; CHECK-RV32-NEXT: srl a3, a4, a3
-; CHECK-RV32-NEXT: srli a1, a1, 16
; CHECK-RV32-NEXT: srl a1, a1, a2
; CHECK-RV32-NEXT: pack a1, a1, a3
; CHECK-RV32-NEXT: sw a1, 0(a0)
@@ -1003,9 +1006,8 @@ define void @test_psrl_hs_vec_shamt(ptr %ret_ptr, ptr %a_ptr, ptr %shamt_ptr) {
; CHECK-RV64-NEXT: lw a1, 0(a1)
; CHECK-RV64-NEXT: srli a3, a2, 16
; CHECK-RV64-NEXT: srliw a4, a1, 16
-; CHECK-RV64-NEXT: slli a1, a1, 48
+; CHECK-RV64-NEXT: zext.h a1, a1
; CHECK-RV64-NEXT: srl a3, a4, a3
-; CHECK-RV64-NEXT: srli a1, a1, 48
; CHECK-RV64-NEXT: srl a1, a1, a2
; CHECK-RV64-NEXT: ppaire.h a1, a1, a3
; CHECK-RV64-NEXT: sw a1, 0(a0)
@@ -1077,9 +1079,8 @@ define void @test_psra_hs_vec_shamt(ptr %ret_ptr, ptr %a_ptr, ptr %shamt_ptr) {
; CHECK-RV32-NEXT: lw a1, 0(a1)
; CHECK-RV32-NEXT: srli a3, a2, 16
; CHECK-RV32-NEXT: srai a4, a1, 16
-; CHECK-RV32-NEXT: slli a1, a1, 16
+; CHECK-RV32-NEXT: sext.h a1, a1
; CHECK-RV32-NEXT: sra a3, a4, a3
-; CHECK-RV32-NEXT: srai a1, a1, 16
; CHECK-RV32-NEXT: sra a1, a1, a2
; CHECK-RV32-NEXT: pack a1, a1, a3
; CHECK-RV32-NEXT: sw a1, 0(a0)
@@ -1090,10 +1091,9 @@ define void @test_psra_hs_vec_shamt(ptr %ret_ptr, ptr %a_ptr, ptr %shamt_ptr) {
; CHECK-RV64-NEXT: lw a2, 0(a2)
; CHECK-RV64-NEXT: lw a1, 0(a1)
; CHECK-RV64-NEXT: srli a3, a2, 16
-; CHECK-RV64-NEXT: sraiw a4, a1, 16
-; CHECK-RV64-NEXT: slli a1, a1, 48
+; CHECK-RV64-NEXT: srai a4, a1, 16
+; CHECK-RV64-NEXT: sext.h a1, a1
; CHECK-RV64-NEXT: sra a3, a4, a3
-; CHECK-RV64-NEXT: srai a1, a1, 48
; CHECK-RV64-NEXT: sra a1, a1, a2
; CHECK-RV64-NEXT: ppaire.h a1, a1, a3
; CHECK-RV64-NEXT: sw a1, 0(a0)
@@ -1113,17 +1113,16 @@ define void @test_psra_bs_vec_shamt(ptr %ret_ptr, ptr %a_ptr, ptr %shamt_ptr) {
; CHECK-RV32-NEXT: srli a3, a2, 24
; CHECK-RV32-NEXT: srai a4, a1, 24
; CHECK-RV32-NEXT: srli a5, a2, 8
-; CHECK-RV32-NEXT: slli a6, a1, 16
+; CHECK-RV32-NEXT: srli a6, a1, 8
; CHECK-RV32-NEXT: sra a7, a4, a3
-; CHECK-RV32-NEXT: srai a3, a6, 24
+; CHECK-RV32-NEXT: sext.b a3, a6
; CHECK-RV32-NEXT: sra a6, a3, a5
-; CHECK-RV32-NEXT: srli a3, a2, 16
-; CHECK-RV32-NEXT: slli a4, a1, 8
-; CHECK-RV32-NEXT: slli a1, a1, 24
-; CHECK-RV32-NEXT: srai a4, a4, 24
-; CHECK-RV32-NEXT: sra a3, a4, a3
-; CHECK-RV32-NEXT: srai a1, a1, 24
-; CHECK-RV32-NEXT: sra a2, a1, a2
+; CHECK-RV32-NEXT: sext.b a3, a1
+; CHECK-RV32-NEXT: srli a4, a2, 16
+; CHECK-RV32-NEXT: srli a1, a1, 16
+; CHECK-RV32-NEXT: sra a2, a3, a2
+; CHECK-RV32-NEXT: sext.b a1, a1
+; CHECK-RV32-NEXT: sra a3, a1, a4
; CHECK-RV32-NEXT: ppaire.db a2, a2, a6
; CHECK-RV32-NEXT: pack a1, a2, a3
; CHECK-RV32-NEXT: sw a1, 0(a0)
@@ -1134,21 +1133,20 @@ define void @test_psra_bs_vec_shamt(ptr %ret_ptr, ptr %a_ptr, ptr %shamt_ptr) {
; CHECK-RV64-NEXT: lw a2, 0(a2)
; CHECK-RV64-NEXT: lw a1, 0(a1)
; CHECK-RV64-NEXT: srli a3, a2, 24
-; CHECK-RV64-NEXT: sraiw a4, a1, 24
+; CHECK-RV64-NEXT: srai a4, a1, 24
; CHECK-RV64-NEXT: srli a5, a2, 16
-; CHECK-RV64-NEXT: slli a6, a1, 40
; CHECK-RV64-NEXT: sra a3, a4, a3
-; CHECK-RV64-NEXT: srli a4, a2, 8
-; CHECK-RV64-NEXT: srai a6, a6, 56
-; CHECK-RV64-NEXT: sra a5, a6, a5
-; CHECK-RV64-NEXT: slli a6, a1, 48
-; CHECK-RV64-NEXT: srai a6, a6, 56
-; CHECK-RV64-NEXT: sra a4, a6, a4
-; CHECK-RV64-NEXT: slli a1, a1, 56
-; CHECK-RV64-NEXT: srai a1, a1, 56
+; CHECK-RV64-NEXT: srli a4, a1, 16
+; CHECK-RV64-NEXT: sext.b a4, a4
+; CHECK-RV64-NEXT: sra a4, a4, a5
+; CHECK-RV64-NEXT: sext.b a5, a1
+; CHECK-RV64-NEXT: sra a5, a5, a2
+; CHECK-RV64-NEXT: srli a2, a2, 8
+; CHECK-RV64-NEXT: srli a1, a1, 8
+; CHECK-RV64-NEXT: sext.b a1, a1
; CHECK-RV64-NEXT: sra a1, a1, a2
-; CHECK-RV64-NEXT: ppaire.b a2, a5, a3
-; CHECK-RV64-NEXT: ppaire.b a1, a1, a4
+; CHECK-RV64-NEXT: ppaire.b a2, a4, a3
+; CHECK-RV64-NEXT: ppaire.b a1, a5, a1
; CHECK-RV64-NEXT: ppaire.h a1, a1, a2
; CHECK-RV64-NEXT: sw a1, 0(a0)
; CHECK-RV64-NEXT: ret
@@ -1299,11 +1297,9 @@ define void @test_psdiv_h(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-RV32-NEXT: lw a1, 0(a1)
; CHECK-RV32-NEXT: srai a3, a2, 16
; CHECK-RV32-NEXT: srai a4, a1, 16
-; CHECK-RV32-NEXT: slli a2, a2, 16
-; CHECK-RV32-NEXT: slli a1, a1, 16
+; CHECK-RV32-NEXT: sext.h a2, a2
+; CHECK-RV32-NEXT: sext.h a1, a1
; CHECK-RV32-NEXT: div a3, a4, a3
-; CHECK-RV32-NEXT: srai a2, a2, 16
-; CHECK-RV32-NEXT: srai a1, a1, 16
; CHECK-RV32-NEXT: div a1, a1, a2
; CHECK-RV32-NEXT: pack a1, a1, a3
; CHECK-RV32-NEXT: sw a1, 0(a0)
@@ -1313,13 +1309,11 @@ define void @test_psdiv_h(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: lw a2, 0(a2)
; CHECK-RV64-NEXT: lw a1, 0(a1)
-; CHECK-RV64-NEXT: sraiw a3, a2, 16
-; CHECK-RV64-NEXT: sraiw a4, a1, 16
-; CHECK-RV64-NEXT: slli a2, a2, 48
-; CHECK-RV64-NEXT: slli a1, a1, 48
+; CHECK-RV64-NEXT: srai a3, a2, 16
+; CHECK-RV64-NEXT: srai a4, a1, 16
+; CHECK-RV64-NEXT: sext.h a2, a2
+; CHECK-RV64-NEXT: sext.h a1, a1
; CHECK-RV64-NEXT: divw a3, a4, a3
-; CHECK-RV64-NEXT: srai a2, a2, 48
-; CHECK-RV64-NEXT: srai a1, a1, 48
; CHECK-RV64-NEXT: divw a1, a1, a2
; CHECK-RV64-NEXT: ppaire.h a1, a1, a3
; CHECK-RV64-NEXT: sw a1, 0(a0)
@@ -1338,23 +1332,21 @@ define void @test_psdiv_b(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-RV32-NEXT: lw a1, 0(a1)
; CHECK-RV32-NEXT: srai a3, a2, 24
; CHECK-RV32-NEXT: srai a4, a1, 24
-; CHECK-RV32-NEXT: slli a5, a2, 16
-; CHECK-RV32-NEXT: slli a6, a1, 16
+; CHECK-RV32-NEXT: srli a5, a2, 8
+; CHECK-RV32-NEXT: srli a6, a1, 8
; CHECK-RV32-NEXT: div a7, a4, a3
-; CHECK-RV32-NEXT: srai a5, a5, 24
-; CHECK-RV32-NEXT: srai a3, a6, 24
-; CHECK-RV32-NEXT: div a6, a3, a5
-; CHECK-RV32-NEXT: slli a3, a2, 8
-; CHECK-RV32-NEXT: slli a4, a1, 8
-; CHECK-RV32-NEXT: slli a2, a2, 24
-; CHECK-RV32-NEXT: slli a1, a1, 24
-; CHECK-RV32-NEXT: srai a3, a3, 24
-; CHECK-RV32-NEXT: srai a4, a4, 24
-; CHECK-RV32-NEXT: srai a2, a2, 24
-; CHECK-RV32-NEXT: div a3, a4, a3
-; CHECK-RV32-NEXT: srai a1, a1, 24
-; CHECK-RV32-NEXT: div a2, a1, a2
-; CHECK-RV32-NEXT: ppaire.db a2, a2, a6
+; CHECK-RV32-NEXT: sext.b a3, a5
+; CHECK-RV32-NEXT: sext.b a4, a6
+; CHECK-RV32-NEXT: div a6, a4, a3
+; CHECK-RV32-NEXT: sext.b a3, a2
+; CHECK-RV32-NEXT: sext.b a4, a1
+; CHECK-RV32-NEXT: srli a2, a2, 16
+; CHECK-RV32-NEXT: srli a1, a1, 16
+; CHECK-RV32-NEXT: div a4, a4, a3
+; CHECK-RV32-NEXT: sext.b a2, a2
+; CHECK-RV32-NEXT: sext.b a1, a1
+; CHECK-RV32-NEXT: div a5, a1, a2
+; CHECK-RV32-NEXT: ppaire.db a2, a4, a6
; CHECK-RV32-NEXT: pack a1, a2, a3
; CHECK-RV32-NEXT: sw a1, 0(a0)
; CHECK-RV32-NEXT: ret
@@ -1363,26 +1355,24 @@ define void @test_psdiv_b(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: lw a2, 0(a2)
; CHECK-RV64-NEXT: lw a1, 0(a1)
-; CHECK-RV64-NEXT: sraiw a3, a2, 24
-; CHECK-RV64-NEXT: sraiw a4, a1, 24
-; CHECK-RV64-NEXT: slli a5, a2, 40
-; CHECK-RV64-NEXT: slli a6, a1, 40
+; CHECK-RV64-NEXT: srai a3, a2, 24
+; CHECK-RV64-NEXT: srai a4, a1, 24
+; CHECK-RV64-NEXT: srli a5, a2, 16
+; CHECK-RV64-NEXT: sext.b a6, a2
; CHECK-RV64-NEXT: divw a3, a4, a3
-; CHECK-RV64-NEXT: slli a4, a2, 48
-; CHECK-RV64-NEXT: srai a5, a5, 56
-; CHECK-RV64-NEXT: srai a6, a6, 56
+; CHECK-RV64-NEXT: sext.b a4, a1
+; CHECK-RV64-NEXT: divw a4, a4, a6
+; CHECK-RV64-NEXT: srli a6, a1, 16
+; CHECK-RV64-NEXT: sext.b a5, a5
+; CHECK-RV64-NEXT: sext.b a6, a6
; CHECK-RV64-NEXT: divw a5, a6, a5
-; CHECK-RV64-NEXT: slli a6, a1, 48
-; CHECK-RV64-NEXT: srai a4, a4, 56
-; CHECK-RV64-NEXT: srai a6, a6, 56
-; CHECK-RV64-NEXT: divw a4, a6, a4
-; CHECK-RV64-NEXT: slli a2, a2, 56
-; CHECK-RV64-NEXT: slli a1, a1, 56
-; CHECK-RV64-NEXT: srai a2, a2, 56
-; CHECK-RV64-NEXT: srai a1, a1, 56
+; CHECK-RV64-NEXT: srli a2, a2, 8
+; CHECK-RV64-NEXT: srli a1, a1, 8
+; CHECK-RV64-NEXT: sext.b a2, a2
+; CHECK-RV64-NEXT: sext.b a1, a1
; CHECK-RV64-NEXT: divw a1, a1, a2
; CHECK-RV64-NEXT: ppaire.b a2, a5, a3
-; CHECK-RV64-NEXT: ppaire.b a1, a1, a4
+; CHECK-RV64-NEXT: ppaire.b a1, a4, a1
; CHECK-RV64-NEXT: ppaire.h a1, a1, a2
; CHECK-RV64-NEXT: sw a1, 0(a0)
; CHECK-RV64-NEXT: ret
@@ -1398,15 +1388,13 @@ define void @test_pudiv_h(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: lw a2, 0(a2)
; CHECK-RV32-NEXT: lw a1, 0(a1)
-; CHECK-RV32-NEXT: lui a3, 16
-; CHECK-RV32-NEXT: addi a3, a3, -1
-; CHECK-RV32-NEXT: and a4, a2, a3
-; CHECK-RV32-NEXT: and a3, a1, a3
-; CHECK-RV32-NEXT: srli a2, a2, 16
-; CHECK-RV32-NEXT: srli a1, a1, 16
-; CHECK-RV32-NEXT: divu a3, a3, a4
+; CHECK-RV32-NEXT: srli a3, a2, 16
+; CHECK-RV32-NEXT: srli a4, a1, 16
+; CHECK-RV32-NEXT: zext.h a2, a2
+; CHECK-RV32-NEXT: zext.h a1, a1
+; CHECK-RV32-NEXT: divu a3, a4, a3
; CHECK-RV32-NEXT: divu a1, a1, a2
-; CHECK-RV32-NEXT: pack a1, a3, a1
+; CHECK-RV32-NEXT: pack a1, a1, a3
; CHECK-RV32-NEXT: sw a1, 0(a0)
; CHECK-RV32-NEXT: ret
;
@@ -1414,15 +1402,13 @@ define void @test_pudiv_h(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: lw a2, 0(a2)
; CHECK-RV64-NEXT: lw a1, 0(a1)
-; CHECK-RV64-NEXT: lui a3, 16
-; CHECK-RV64-NEXT: addi a3, a3, -1
-; CHECK-RV64-NEXT: and a4, a2, a3
-; CHECK-RV64-NEXT: and a3, a1, a3
-; CHECK-RV64-NEXT: srliw a2, a2, 16
-; CHECK-RV64-NEXT: srliw a1, a1, 16
-; CHECK-RV64-NEXT: divuw a3, a3, a4
+; CHECK-RV64-NEXT: srliw a3, a2, 16
+; CHECK-RV64-NEXT: srliw a4, a1, 16
+; CHECK-RV64-NEXT: zext.h a2, a2
+; CHECK-RV64-NEXT: zext.h a1, a1
+; CHECK-RV64-NEXT: divuw a3, a4, a3
; CHECK-RV64-NEXT: divuw a1, a1, a2
-; CHECK-RV64-NEXT: ppaire.h a1, a3, a1
+; CHECK-RV64-NEXT: ppaire.h a1, a1, a3
; CHECK-RV64-NEXT: sw a1, 0(a0)
; CHECK-RV64-NEXT: ret
%a = load <2 x i16>, ptr %a_ptr
@@ -1497,11 +1483,9 @@ define void @test_psrem_h(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-RV32-NEXT: lw a1, 0(a1)
; CHECK-RV32-NEXT: srai a3, a2, 16
; CHECK-RV32-NEXT: srai a4, a1, 16
-; CHECK-RV32-NEXT: slli a2, a2, 16
-; CHECK-RV32-NEXT: slli a1, a1, 16
+; CHECK-RV32-NEXT: sext.h a2, a2
+; CHECK-RV32-NEXT: sext.h a1, a1
; CHECK-RV32-NEXT: rem a3, a4, a3
-; CHECK-RV32-NEXT: srai a2, a2, 16
-; CHECK-RV32-NEXT: srai a1, a1, 16
; CHECK-RV32-NEXT: rem a1, a1, a2
; CHECK-RV32-NEXT: pack a1, a1, a3
; CHECK-RV32-NEXT: sw a1, 0(a0)
@@ -1511,13 +1495,11 @@ define void @test_psrem_h(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: lw a2, 0(a2)
; CHECK-RV64-NEXT: lw a1, 0(a1)
-; CHECK-RV64-NEXT: sraiw a3, a2, 16
-; CHECK-RV64-NEXT: sraiw a4, a1, 16
-; CHECK-RV64-NEXT: slli a2, a2, 48
-; CHECK-RV64-NEXT: slli a1, a1, 48
+; CHECK-RV64-NEXT: srai a3, a2, 16
+; CHECK-RV64-NEXT: srai a4, a1, 16
+; CHECK-RV64-NEXT: sext.h a2, a2
+; CHECK-RV64-NEXT: sext.h a1, a1
; CHECK-RV64-NEXT: remw a3, a4, a3
-; CHECK-RV64-NEXT: srai a2, a2, 48
-; CHECK-RV64-NEXT: srai a1, a1, 48
; CHECK-RV64-NEXT: remw a1, a1, a2
; CHECK-RV64-NEXT: ppaire.h a1, a1, a3
; CHECK-RV64-NEXT: sw a1, 0(a0)
@@ -1536,23 +1518,21 @@ define void @test_psrem_b(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-RV32-NEXT: lw a1, 0(a1)
; CHECK-RV32-NEXT: srai a3, a2, 24
; CHECK-RV32-NEXT: srai a4, a1, 24
-; CHECK-RV32-NEXT: slli a5, a2, 16
-; CHECK-RV32-NEXT: slli a6, a1, 16
+; CHECK-RV32-NEXT: srli a5, a2, 8
+; CHECK-RV32-NEXT: srli a6, a1, 8
; CHECK-RV32-NEXT: rem a7, a4, a3
-; CHECK-RV32-NEXT: srai a5, a5, 24
-; CHECK-RV32-NEXT: srai a3, a6, 24
-; CHECK-RV32-NEXT: rem a6, a3, a5
-; CHECK-RV32-NEXT: slli a3, a2, 8
-; CHECK-RV32-NEXT: slli a4, a1, 8
-; CHECK-RV32-NEXT: slli a2, a2, 24
-; CHECK-RV32-NEXT: slli a1, a1, 24
-; CHECK-RV32-NEXT: srai a3, a3, 24
-; CHECK-RV32-NEXT: srai a4, a4, 24
-; CHECK-RV32-NEXT: srai a2, a2, 24
-; CHECK-RV32-NEXT: rem a3, a4, a3
-; CHECK-RV32-NEXT: srai a1, a1, 24
-; CHECK-RV32-NEXT: rem a2, a1, a2
-; CHECK-RV32-NEXT: ppaire.db a2, a2, a6
+; CHECK-RV32-NEXT: sext.b a3, a5
+; CHECK-RV32-NEXT: sext.b a4, a6
+; CHECK-RV32-NEXT: rem a6, a4, a3
+; CHECK-RV32-NEXT: sext.b a3, a2
+; CHECK-RV32-NEXT: sext.b a4, a1
+; CHECK-RV32-NEXT: srli a2, a2, 16
+; CHECK-RV32-NEXT: srli a1, a1, 16
+; CHECK-RV32-NEXT: rem a4, a4, a3
+; CHECK-RV32-NEXT: sext.b a2, a2
+; CHECK-RV32-NEXT: sext.b a1, a1
+; CHECK-RV32-NEXT: rem a5, a1, a2
+; CHECK-RV32-NEXT: ppaire.db a2, a4, a6
; CHECK-RV32-NEXT: pack a1, a2, a3
; CHECK-RV32-NEXT: sw a1, 0(a0)
; CHECK-RV32-NEXT: ret
@@ -1561,26 +1541,24 @@ define void @test_psrem_b(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: lw a2, 0(a2)
; CHECK-RV64-NEXT: lw a1, 0(a1)
-; CHECK-RV64-NEXT: sraiw a3, a2, 24
-; CHECK-RV64-NEXT: sraiw a4, a1, 24
-; CHECK-RV64-NEXT: slli a5, a2, 40
-; CHECK-RV64-NEXT: slli a6, a1, 40
+; CHECK-RV64-NEXT: srai a3, a2, 24
+; CHECK-RV64-NEXT: srai a4, a1, 24
+; CHECK-RV64-NEXT: srli a5, a2, 16
+; CHECK-RV64-NEXT: sext.b a6, a2
; CHECK-RV64-NEXT: remw a3, a4, a3
-; CHECK-RV64-NEXT: slli a4, a2, 48
-; CHECK-RV64-NEXT: srai a5, a5, 56
-; CHECK-RV64-NEXT: srai a6, a6, 56
+; CHECK-RV64-NEXT: sext.b a4, a1
+; CHECK-RV64-NEXT: remw a4, a4, a6
+; CHECK-RV64-NEXT: srli a6, a1, 16
+; CHECK-RV64-NEXT: sext.b a5, a5
+; CHECK-RV64-NEXT: sext.b a6, a6
; CHECK-RV64-NEXT: remw a5, a6, a5
-; CHECK-RV64-NEXT: slli a6, a1, 48
-; CHECK-RV64-NEXT: srai a4, a4, 56
-; CHECK-RV64-NEXT: srai a6, a6, 56
-; CHECK-RV64-NEXT: remw a4, a6, a4
-; CHECK-RV64-NEXT: slli a2, a2, 56
-; CHECK-RV64-NEXT: slli a1, a1, 56
-; CHECK-RV64-NEXT: srai a2, a2, 56
-; CHECK-RV64-NEXT: srai a1, a1, 56
+; CHECK-RV64-NEXT: srli a2, a2, 8
+; CHECK-RV64-NEXT: srli a1, a1, 8
+; CHECK-RV64-NEXT: sext.b a2, a2
+; CHECK-RV64-NEXT: sext.b a1, a1
; CHECK-RV64-NEXT: remw a1, a1, a2
; CHECK-RV64-NEXT: ppaire.b a2, a5, a3
-; CHECK-RV64-NEXT: ppaire.b a1, a1, a4
+; CHECK-RV64-NEXT: ppaire.b a1, a4, a1
; CHECK-RV64-NEXT: ppaire.h a1, a1, a2
; CHECK-RV64-NEXT: sw a1, 0(a0)
; CHECK-RV64-NEXT: ret
@@ -1596,15 +1574,13 @@ define void @test_purem_h(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: lw a2, 0(a2)
; CHECK-RV32-NEXT: lw a1, 0(a1)
-; CHECK-RV32-NEXT: lui a3, 16
-; CHECK-RV32-NEXT: addi a3, a3, -1
-; CHECK-RV32-NEXT: and a4, a2, a3
-; CHECK-RV32-NEXT: and a3, a1, a3
-; CHECK-RV32-NEXT: srli a2, a2, 16
-; CHECK-RV32-NEXT: srli a1, a1, 16
-; CHECK-RV32-NEXT: remu a3, a3, a4
+; CHECK-RV32-NEXT: srli a3, a2, 16
+; CHECK-RV32-NEXT: srli a4, a1, 16
+; CHECK-RV32-NEXT: zext.h a2, a2
+; CHECK-RV32-NEXT: zext.h a1, a1
+; CHECK-RV32-NEXT: remu a3, a4, a3
; CHECK-RV32-NEXT: remu a1, a1, a2
-; CHECK-RV32-NEXT: pack a1, a3, a1
+; CHECK-RV32-NEXT: pack a1, a1, a3
; CHECK-RV32-NEXT: sw a1, 0(a0)
; CHECK-RV32-NEXT: ret
;
@@ -1612,15 +1588,13 @@ define void @test_purem_h(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: lw a2, 0(a2)
; CHECK-RV64-NEXT: lw a1, 0(a1)
-; CHECK-RV64-NEXT: lui a3, 16
-; CHECK-RV64-NEXT: addi a3, a3, -1
-; CHECK-RV64-NEXT: and a4, a2, a3
-; CHECK-RV64-NEXT: and a3, a1, a3
-; CHECK-RV64-NEXT: srliw a2, a2, 16
-; CHECK-RV64-NEXT: srliw a1, a1, 16
-; CHECK-RV64-NEXT: remuw a3, a3, a4
+; CHECK-RV64-NEXT: srliw a3, a2, 16
+; CHECK-RV64-NEXT: srliw a4, a1, 16
+; CHECK-RV64-NEXT: zext.h a2, a2
+; CHECK-RV64-NEXT: zext.h a1, a1
+; CHECK-RV64-NEXT: remuw a3, a4, a3
; CHECK-RV64-NEXT: remuw a1, a1, a2
-; CHECK-RV64-NEXT: ppaire.h a1, a3, a1
+; CHECK-RV64-NEXT: ppaire.h a1, a1, a3
; CHECK-RV64-NEXT: sw a1, 0(a0)
; CHECK-RV64-NEXT: ret
%a = load <2 x i16>, ptr %a_ptr
diff --git a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
index db5a510ae422b..c459e607c55b1 100644
--- a/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-ext-rv64.ll
@@ -1,5 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+m -riscv-enable-p-ext-simd-codegen -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p,+m,+zbb \
+; RUN: -riscv-enable-p-ext-simd-codegen -verify-machineinstrs < %s | \
+; RUN: FileCheck %s
; Test basic add/sub operations for v4i16
define void @test_padd_h(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
@@ -1388,22 +1390,22 @@ define void @test_psdiv_h(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-NEXT: ld a1, 0(a1)
; CHECK-NEXT: srai a3, a2, 48
; CHECK-NEXT: srai a4, a1, 48
-; CHECK-NEXT: slli a5, a2, 16
-; CHECK-NEXT: sraiw a6, a2, 16
+; CHECK-NEXT: srli a5, a2, 32
+; CHECK-NEXT: sext.h a6, a2
; CHECK-NEXT: divw a3, a4, a3
-; CHECK-NEXT: sraiw a4, a1, 16
+; CHECK-NEXT: sext.h a4, a1
; CHECK-NEXT: divw a4, a4, a6
-; CHECK-NEXT: slli a6, a1, 16
-; CHECK-NEXT: srai a5, a5, 48
-; CHECK-NEXT: srai a6, a6, 48
+; CHECK-NEXT: srli a6, a1, 32
+; CHECK-NEXT: sext.h a5, a5
+; CHECK-NEXT: sext.h a6, a6
; CHECK-NEXT: divw a5, a6, a5
-; CHECK-NEXT: slli a2, a2, 48
-; CHECK-NEXT: slli a1, a1, 48
-; CHECK-NEXT: srai a2, a2, 48
-; CHECK-NEXT: srai a1, a1, 48
+; CHECK-NEXT: srli a2, a2, 16
+; CHECK-NEXT: srli a1, a1, 16
+; CHECK-NEXT: sext.h a2, a2
+; CHECK-NEXT: sext.h a1, a1
; CHECK-NEXT: divw a1, a1, a2
; CHECK-NEXT: ppaire.h a2, a5, a3
-; CHECK-NEXT: ppaire.h a1, a1, a4
+; CHECK-NEXT: ppaire.h a1, a4, a1
; CHECK-NEXT: pack a1, a1, a2
; CHECK-NEXT: sd a1, 0(a0)
; CHECK-NEXT: ret
@@ -1421,46 +1423,46 @@ define void @test_psdiv_b(ptr %ret_ptr, ptr %a_ptr, ptr %b_ptr) {
; CHECK-NEXT: ld a1, 0(a1)
; CHECK-NEXT: srai a3, a2, 56
; CHECK-NEXT: srai a4, a1, 56
-; CHECK-NEXT: slli a5, a2, 8
-; CHECK-NEXT: slli a6, a1, 8
-; CHECK-NEXT: slli a7, a2, 16
-; CHECK-NEXT: slli t0, a1, 16
-; CHECK-NEXT: slli t1, a2, 24
-; CHECK-NEXT: sraiw t2, a2, 24
+; CHECK-NEXT: srli a5, a2, 48
+; CHECK-NEXT: srli a6, a1, 48
+; CHECK-NEXT: srli a7, a2, 40
+; CHECK-NEXT: srli t0, a1, 40
+; CHECK-NEXT: srli t1, a2, 32
+; CHECK-NEXT: sext.b t2, a2
; CHECK-NEXT: divw a3, a4, a3
-; CHECK-NEXT: sraiw a4, a1, 24
+; CHECK-NEXT: ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/175378
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