[llvm] [RISCV] AI Foundry ET extensions for RISC-V (PR #174571)

[Craig Topper via llvm-commits]

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+//===-- RISCVInstrInfoXAIF.td ------------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Instruction definitions for the AI Foundry ET extensions, formerly known as
+// the ET-SoC-1 Minion extensions by Esperanto Technologies.
+//
+// Full documentation for these extensions is publicly available at the
+// following URL:
+//
+//   https://github.com/aifoundry-org/et-man/blob/main/ET%20Programmer's%20Reference%20Manual.pdf
+//
+// The following conventions are used in this file:
+//
+// 1. Specific instruction formats are named
+//
+//        RVInstET<#>
+//
+//    where <#> is a number from 1 to 14. Each number corresponds to a template
+//    fitting a given instruction and other similar ones, as defined in
+//    RISCVInstrFormatsXAIF.td
+//
+// 2. Each masked vector instruction <INST> is handled with an ETOps<Operands>
+//    multiclass defining one instruction and two pseudo instructions:
+//
+//     - <INST>: regular masked vector instructions as described in the manual,
+//       implicitly using M0 register for masking out destination register
+//       elements.
+//
+//     - <INST>_EX: masked vector pseudo-instruction explictly accepting M0 as
+//       its last operand, as opposed to <INST> where the register dependency
+//       is just implicit. In addition to the explicit operands accepted by
+//       <INST>, we must add m0 as the last operand.
+//
+//       The purpose of this instruction variant is to explicitly mark the
+//       dependency on the m0 register contents in MIR (Machine Instruction
+//       Representation).
+//
+//     - <INST>_PASSTHRU_EX: Similar to <INST_EX>, but also making explicit the
+//       dependency on the previous destination register contents. In addition
+//       to the explicit operands accepted by <INST_EX>, we must add the
+//       destination register as the first operand.
+//
+//       Destination and first source operands are constrained to be assigned
+//       the same physical register during register allocation.
+//
+//       This variant should be the choice during instruction selection for
+//       cases when m0 is not guaranteed to be all ones.
+//
+//===----------------------------------------------------------------------===//
+
+let DecoderNamespace = "XAIF" in {
+let Predicates = [HasXAIFET] in {
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topperc wrote:

Combine these 2 `let` statements into one

https://github.com/llvm/llvm-project/pull/174571