[llvm] [AMDGPU] Handle `s_setreg_imm32_b32` targeting `MODE` register (PR #174681)

[Shilei Tian via llvm-commits]

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@@ -160,12 +176,19 @@ bool AMDGPULowerVGPREncoding::setMode(ModeTy NewMode, ModeTy Mask,
     CurrentMode |= NewMode;
     CurrentMask |= Mask;
 
-    MachineOperand &Op = MostRecentModeSet->getOperand(0);
-
-    // Carry old mode bits from the existing instruction.
-    int64_t OldModeBits = Op.getImm() & (ModeMask << ModeWidth);
+    // Update MostRecentModeSet with the new mode. It can be either
+    // S_SET_VGPR_MSB or S_SETREG_IMM32_B32 (with Size <= 12).
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shiltian wrote:

Yes, that's the core idea.

https://github.com/llvm/llvm-project/pull/174681