[llvm] [AMDGPU] Have VCC as a first-class member of the SGPR pool. (PR #173870)

[Ivan Kosarev via llvm-commits]

kosarev wrote:

> Southern Islands ISA manual: "Shader Hazard with VCC The user/compiler must prevent a scalar-ALU write to the SGPR holding VCC, immediately followed by a conditional branch using VCCZ. The hardware cannot detect this, and inserts the one required wait state (hardware does detect it when the SALU writes to VCC, it only fails to do this when the SALU instruction references the SGPRs that happen to hold VCC)."

We seem to handle that by adding extra waits on `hasReadVCCZBug()` and `!partialVCCWritesUpdateVCCZ()` for all such branches.

I don't see how not using VCC tuples in some instructions can help this.

> > It is my reading of the email thread that VCC was never an exception. I also see no signs of us treating VCC any differently in the backend
> 
> We avoided this by reserving the high N registers that alias VCC

I'm not aware of any VCC aliases that we have. Do you mean reserving SGPR_32 registers beyond `getMaxNumSGPRs()`?

Where those high numbered SGPRs are not available, the new VCC tuples should not be available either -- automatically.

https://github.com/llvm/llvm-project/pull/173870