[llvm] [RFC][SPIR-V] Add intrinsics to convert to/from ap.float (PR #164252)

[Dmitry Sidorov via llvm-commits]

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MrSidims wrote:

What I had in mind is that for FP4 conversions legalization is quite trivial in case if add a loop up table, then FP4 value becomes just an index. After double checking - FP6 case seem to be also trivial as it's indeed just bit shuffling + rounding.

There are FP8 + FN/FNUZ/E8M0FNU case, where generic lowering stops being “just shuffle + one rounding bit” and becomes “shuffle + full special-case semantics + careful NaN/zero rules.”. I lean towards agreeing, that generic legalization is feasible, yet not 100% sure if there will be interest for the intrinsics outside of the use cases, when a hardware supports the conversions in a performant way.

https://github.com/llvm/llvm-project/pull/164252