[llvm] [AArch64] Add lowering for NEON saturating shift intrinsics (PR #171485)

[via llvm-commits]

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@@ -4592,18 +4592,21 @@ static SDValue lowerADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG,
 static SDValue lowerIntNeonIntrinsic(SDValue Op, unsigned Opcode,
                                      SelectionDAG &DAG) {
   SDLoc DL(Op);
+  SmallVector<SDValue, 2> NewOps;
   auto getFloatVT = [](EVT VT) {
     assert((VT == MVT::i32 || VT == MVT::i64) && "Unexpected VT");
     return VT == MVT::i32 ? MVT::f32 : MVT::f64;
   };
   auto bitcastToFloat = [&](SDValue Val) {
     return DAG.getBitcast(getFloatVT(Val.getValueType()), Val);
   };
-  SmallVector<SDValue, 2> NewOps;
-  NewOps.reserve(Op.getNumOperands() - 1);
 
-  for (unsigned I = 1, E = Op.getNumOperands(); I < E; ++I)
-    NewOps.push_back(bitcastToFloat(Op.getOperand(I)));
+  // Skip first operand as it is intrinsic ID.
+  for (unsigned I = 1, E = Op.getNumOperands(); I < E; ++I) {
+    SDValue Val = Op.getOperand(I);
+    NewOps.push_back(isa<ConstantSDNode>(Val.getNode()) ? Val
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Lukacma wrote:

Ah I see the issue now. I didn't think about constant folding. Thanks for catching this! I guess we have to return to my original solution of using flags to exclude last parameter explicitly.

https://github.com/llvm/llvm-project/pull/171485