[llvm] [RISCV] AI Foundry ET extensions for RISC-V (PR #174571)

[Abel Bernabeu via llvm-commits]

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@@ -901,3 +901,57 @@ let RegInfos = XLenRI in {
   def TRM2 : RISCVRegisterClass<[untyped], 32, (add (decimate TR, 2))>;
   def TRM4 : RISCVRegisterClass<[untyped], 32, (add (decimate TR, 4))>;
 }
+
+//===----------------------------------------------------------------------===//
+// XAIFET registers
+//===----------------------------------------------------------------------===//
+
+// Each scalar floating point register is extended to a 256 bits wide vector.
+// The original scalar floating point register occupies the 32 LSB of the
+// vector.
+
+class RISCVReg256<RISCVReg32 subreg> :
+  RISCVRegWithSubRegs<subreg.HWEncoding{4-0}, subreg.AsmName, [subreg],
+                      subreg.AltNames> {
+  let SubRegIndices = [sub_32];
+}
+
+let RegAltNameIndices = [ABIRegAltName] in {
+  foreach Index = 0-31 in {
+    def F#Index#_PS : RISCVReg256<!cast<RISCVReg32>("F"#Index#"_F")>,
+                                  DwarfRegNum<[!add(Index, 3088)]>;
+  }
+}
+
+// The order of registers represents the preferred allocation sequence,
+// meaning caller-save regs are listed before callee-save.
+
+def FPR256 : RISCVRegisterClass<[v8i32, v8f32], 256,
+                                (add
+                                  (sequence "F%u_PS", 0, 7),
+                                  (sequence "F%u_PS", 10, 17),
+                                  (sequence "F%u_PS", 28, 31),
+                                  (sequence "F%u_PS", 8, 9),
+                                  (sequence "F%u_PS", 18, 27)
+                                )> {
+  let RegInfos = RegInfoByHwMode<[RV32,                RV64],
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abel-bernabeu wrote:

No, we do not. Removed.

https://github.com/llvm/llvm-project/pull/174571