[llvm] 4684e50 - [Instcombine] Ensure simplifyValueKnownNonZero adds instrs in dominance order (#173703)

[via llvm-commits]

Author: Justin Lebar
Date: 2026-01-09T10:30:28+01:00
New Revision: 4684e504a8bd84c8c12c0f4ba47f13f3f7c422c5

URL: https://github.com/llvm/llvm-project/commit/4684e504a8bd84c8c12c0f4ba47f13f3f7c422c5
DIFF: https://github.com/llvm/llvm-project/commit/4684e504a8bd84c8c12c0f4ba47f13f3f7c422c5.diff

LOG: [Instcombine] Ensure simplifyValueKnownNonZero adds instrs in dominance order (#173703)

This was found by a fuzzer I'm working on.  The high-level design is to
randomly generate LLVM IR, run a pass on it, and then run the original
and new IR through the interpreter.  They should produce the same
results.  Right now I'm only fuzzing instcombine.

Added: 
    llvm/test/Transforms/InstCombine/instcombine-dominance-fixup.ll

Modified: 
    llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
index 313268ae51185..9022a029a9f7a 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
@@ -69,9 +69,13 @@ static Value *simplifyValueKnownNonZero(Value *V, InstCombinerImpl &IC,
       IC.isKnownToBeAPowerOfTwo(I->getOperand(0), false, &CxtI)) {
     // We know that this is an exact/nuw shift and that the input is a
     // non-zero context as well.
-    if (Value *V2 = simplifyValueKnownNonZero(I->getOperand(0), IC, CxtI)) {
-      IC.replaceOperand(*I, 0, V2);
-      MadeChange = true;
+    {
+      IRBuilderBase::InsertPointGuard Guard(IC.Builder);
+      IC.Builder.SetInsertPoint(I);
+      if (Value *V2 = simplifyValueKnownNonZero(I->getOperand(0), IC, CxtI)) {
+        IC.replaceOperand(*I, 0, V2);
+        MadeChange = true;
+      }
     }
 
     if (I->getOpcode() == Instruction::LShr && !I->isExact()) {

diff  --git a/llvm/test/Transforms/InstCombine/instcombine-dominance-fixup.ll b/llvm/test/Transforms/InstCombine/instcombine-dominance-fixup.ll
new file mode 100644
index 0000000000000..c374ef2fc9a53
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/instcombine-dominance-fixup.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; NOTE: This test ensures InstCombine preserves dominance even when it
+; reorders shifts through SimplifyDemandedBits/log2 folding.
+;
+; RUN: opt -passes=instcombine -S < %s | FileCheck %s
+
+define i64 @f(i64 %arg0, i64 %arg1) {
+; CHECK-LABEL: define i64 @f(
+; CHECK-SAME: i64 [[ARG0:%.*]], i64 [[ARG1:%.*]]) {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    [[I:%.*]] = add i64 [[ARG1]], -1
+; CHECK-NEXT:    [[I1:%.*]] = shl nuw i64 1, [[I]]
+; CHECK-NEXT:    [[SHL2:%.*]] = shl nuw i64 [[I1]], [[ARG1]]
+; CHECK-NEXT:    [[SREM:%.*]] = srem i64 [[ARG0]], [[SHL2]]
+; CHECK-NEXT:    ret i64 [[SREM]]
+;
+entry:
+  %shl = shl nuw i64 1, %arg1
+  %lshr = lshr exact i64 %shl, 1
+  %shl2 = shl nuw i64 %lshr, %arg1
+  %srem = srem i64 %arg0, %shl2
+  ret i64 %srem
+}