[llvm] [AMDGPU] Add wave reduce intrinsics for double types - 1 (PR #170811)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 9 00:14:10 PST 2026
https://github.com/easyonaadit updated https://github.com/llvm/llvm-project/pull/170811
>From e163cb49aa234e06f605ea9991d255ddd3d1ec17 Mon Sep 17 00:00:00 2001
From: Aaditya <Aaditya.AlokDeshpande at amd.com>
Date: Mon, 24 Nov 2025 10:10:10 +0530
Subject: [PATCH 1/4] [AMDGPU] Add wave reduce intrinsics for double types - 1
Supported Ops: `min`, `max`
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 66 +-
llvm/lib/Target/AMDGPU/SIInstructions.td | 2 +
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll | 1280 +++++++++++++++++
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll | 1280 +++++++++++++++++
4 files changed, 2627 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 301f2fc8dab45..80978c6a00a9c 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5522,6 +5522,9 @@ static uint64_t getIdentityValueFor64BitWaveReduction(unsigned Opc) {
return std::numeric_limits<uint64_t>::min();
case AMDGPU::V_CMP_GT_I64_e64: // max.i64
return std::numeric_limits<int64_t>::min();
+ case AMDGPU::V_MIN_F64_e64:
+ case AMDGPU::V_MAX_F64_e64:
+ return 0x7FF8000000000000; // qNAN
case AMDGPU::S_ADD_U64_PSEUDO:
case AMDGPU::S_SUB_U64_PSEUDO:
case AMDGPU::S_OR_B64:
@@ -5547,7 +5550,8 @@ static bool is32bitWaveReduceOperation(unsigned Opc) {
static bool isFloatingPointWaveReduceOperation(unsigned Opc) {
return Opc == AMDGPU::V_MIN_F32_e64 || Opc == AMDGPU::V_MAX_F32_e64 ||
- Opc == AMDGPU::V_ADD_F32_e64 || Opc == AMDGPU::V_SUB_F32_e64;
+ Opc == AMDGPU::V_ADD_F32_e64 || Opc == AMDGPU::V_SUB_F32_e64 ||
+ Opc == AMDGPU::V_MIN_F64_e64 || Opc == AMDGPU::V_MAX_F64_e64;
}
static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
@@ -5583,6 +5587,8 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
case AMDGPU::V_CMP_LT_I64_e64: // min
case AMDGPU::V_CMP_GT_U64_e64: // umax
case AMDGPU::V_CMP_GT_I64_e64: // max
+ case AMDGPU::V_MIN_F64_e64:
+ case AMDGPU::V_MAX_F64_e64:
case AMDGPU::S_AND_B64:
case AMDGPU::S_OR_B64: {
// Idempotent operations.
@@ -5952,6 +5958,60 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
.addReg(Accumulator->getOperand(0).getReg());
break;
}
+ case AMDGPU::V_MIN_F64_e64:
+ case AMDGPU::V_MAX_F64_e64: {
+ const TargetRegisterClass *VregRC = TRI->getVGPR64Class();
+ const TargetRegisterClass *VregSubRC =
+ TRI->getSubRegisterClass(VregRC, AMDGPU::sub0);
+ Register AccumulatorVReg = MRI.createVirtualRegister(VregRC);
+ Register DstVreg = MRI.createVirtualRegister(VregRC);
+ Register LaneValLo =
+ MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
+ Register LaneValHi =
+ MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
+ BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::V_MOV_B64_PSEUDO),
+ AccumulatorVReg)
+ .addReg(Accumulator->getOperand(0).getReg());
+ if (ST.getGeneration() == AMDGPUSubtarget::Generation::GFX12) {
+ switch (Opc) {
+ case AMDGPU::V_MIN_F64_e64:
+ Opc = AMDGPU::V_MIN_NUM_F64_e64;
+ break;
+ case AMDGPU::V_MAX_F64_e64:
+ Opc = AMDGPU::V_MAX_NUM_F64_e64;
+ break;
+ }
+ }
+ auto DstVregInst = BuildMI(*ComputeLoop, I, DL, TII->get(Opc), DstVreg)
+ .addImm(0) // src0 modifiers
+ .addReg(LaneValue->getOperand(0).getReg())
+ .addImm(0) // src1 modifiers
+ .addReg(AccumulatorVReg)
+ .addImm(0) // clamp
+ .addImm(0); // omod
+ auto ReadLaneLo =
+ BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
+ LaneValLo);
+ auto ReadLaneHi =
+ BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
+ LaneValHi);
+ MachineBasicBlock::iterator Iters = *ReadLaneLo;
+ MachineOperand Op1L =
+ TII->buildExtractSubRegOrImm(Iters, MRI, DstVregInst->getOperand(0),
+ VregRC, AMDGPU::sub0, VregSubRC);
+ MachineOperand Op1H =
+ TII->buildExtractSubRegOrImm(Iters, MRI, DstVregInst->getOperand(0),
+ VregRC, AMDGPU::sub1, VregSubRC);
+ ReadLaneLo.add(Op1L);
+ ReadLaneHi.add(Op1H);
+ NewAccumulator = BuildMI(*ComputeLoop, I, DL,
+ TII->get(TargetOpcode::REG_SEQUENCE), DstReg)
+ .addReg(LaneValLo)
+ .addImm(AMDGPU::sub0)
+ .addReg(LaneValHi)
+ .addImm(AMDGPU::sub1);
+ break;
+ }
case AMDGPU::S_ADD_U64_PSEUDO:
case AMDGPU::S_SUB_U64_PSEUDO: {
NewAccumulator = BuildMI(*ComputeLoop, I, DL, TII->get(Opc), DstReg)
@@ -6009,6 +6069,8 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_CMP_LT_I64_e64);
case AMDGPU::WAVE_REDUCE_FMIN_PSEUDO_F32:
return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_MIN_F32_e64);
+ case AMDGPU::WAVE_REDUCE_FMIN_PSEUDO_F64:
+ return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_MIN_F64_e64);
case AMDGPU::WAVE_REDUCE_UMAX_PSEUDO_U32:
return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_MAX_U32);
case AMDGPU::WAVE_REDUCE_UMAX_PSEUDO_U64:
@@ -6019,6 +6081,8 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_CMP_GT_I64_e64);
case AMDGPU::WAVE_REDUCE_FMAX_PSEUDO_F32:
return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_MAX_F32_e64);
+ case AMDGPU::WAVE_REDUCE_FMAX_PSEUDO_F64:
+ return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::V_MAX_F64_e64);
case AMDGPU::WAVE_REDUCE_ADD_PSEUDO_I32:
return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_ADD_I32);
case AMDGPU::WAVE_REDUCE_ADD_PSEUDO_U64:
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index ca5a4d7301bda..82a83e12649fb 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -373,7 +373,9 @@ defvar Operations = [
WaveReduceOp<"xor", "B64", i64, SGPR_64, VSrc_b64>,
WaveReduceOp<"fmin", "F32", f32, SGPR_32, VSrc_b32>,
+ WaveReduceOp<"fmin", "F64", f64, SGPR_64, VSrc_b64>,
WaveReduceOp<"fmax", "F32", f32, SGPR_32, VSrc_b32>,
+ WaveReduceOp<"fmax", "F64", f64, SGPR_64, VSrc_b64>,
WaveReduceOp<"fadd", "F32", f32, SGPR_32, VSrc_b32>,
WaveReduceOp<"fsub", "F32", f32, SGPR_32, VSrc_b32>,
];
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
index f02fd876f1aac..ca4091bcd3366 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
@@ -11,6 +11,7 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL %s
define amdgpu_kernel void @uniform_value_float(ptr addrspace(1) %out, float %in) {
@@ -119,6 +120,14 @@ define amdgpu_kernel void @uniform_value_float(ptr addrspace(1) %out, float %in)
; GFX1132GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1132GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
+;
+; GFX12DAGISEL-LABEL: uniform_value_float:
+; GFX12DAGISEL: ; %bb.0: ; %entry
+; GFX12DAGISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
+; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX12DAGISEL-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12DAGISEL-NEXT: s_endpgm
entry:
%result = call float @llvm.amdgcn.wave.reduce.fmax(float %in, i32 1)
store float %result, ptr addrspace(1) %out
@@ -357,6 +366,33 @@ define void @divergent_value_float(ptr addrspace(1) %out, float %in) {
; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s1
; GFX1132GISEL-NEXT: global_store_b32 v[0:1], v2, off
; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12DAGISEL-LABEL: divergent_value_float:
+; GFX12DAGISEL: ; %bb.0: ; %entry
+; GFX12DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_expcnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12DAGISEL-NEXT: s_mov_b32 s0, exec_lo
+; GFX12DAGISEL-NEXT: s_mov_b32 s1, 0x7fc00000
+; GFX12DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s2, s0
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: v_readlane_b32 s3, v2, s2
+; GFX12DAGISEL-NEXT: s_bitset0_b32 s0, s2
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX12DAGISEL-NEXT: v_max_num_f32_e64 v3, s1, s3
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX12DAGISEL-NEXT: ; %bb.2:
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12DAGISEL-NEXT: v_mov_b32_e32 v2, s1
+; GFX12DAGISEL-NEXT: global_store_b32 v[0:1], v2, off
+; GFX12DAGISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%result = call float @llvm.amdgcn.wave.reduce.fmax(float %in, i32 1)
store float %result, ptr addrspace(1) %out
@@ -905,6 +941,68 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX1132GISEL-NEXT: global_store_b32 v[0:1], v2, off
; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12DAGISEL-LABEL: divergent_cfg_float:
+; GFX12DAGISEL: ; %bb.0: ; %entry
+; GFX12DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_expcnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12DAGISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc_lo, 15, v4
+; GFX12DAGISEL-NEXT: ; implicit-def: $vgpr4
+; GFX12DAGISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX12DAGISEL-NEXT: s_cbranch_execz .LBB2_4
+; GFX12DAGISEL-NEXT: ; %bb.1: ; %else
+; GFX12DAGISEL-NEXT: s_mov_b32 s1, exec_lo
+; GFX12DAGISEL-NEXT: s_mov_b32 s2, 0x7fc00000
+; GFX12DAGISEL-NEXT: .LBB2_2: ; =>This Inner Loop Header: Depth=1
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s3, s1
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
+; GFX12DAGISEL-NEXT: s_bitset0_b32 s1, s3
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX12DAGISEL-NEXT: v_max_num_f32_e64 v3, s2, s4
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s2, v3
+; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB2_2
+; GFX12DAGISEL-NEXT: ; %bb.3:
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12DAGISEL-NEXT: v_mov_b32_e32 v4, s2
+; GFX12DAGISEL-NEXT: ; implicit-def: $vgpr3
+; GFX12DAGISEL-NEXT: .LBB2_4: ; %Flow
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX12DAGISEL-NEXT: s_cbranch_execz .LBB2_8
+; GFX12DAGISEL-NEXT: ; %bb.5: ; %if
+; GFX12DAGISEL-NEXT: s_mov_b32 s1, exec_lo
+; GFX12DAGISEL-NEXT: s_mov_b32 s2, 0x7fc00000
+; GFX12DAGISEL-NEXT: .LBB2_6: ; =>This Inner Loop Header: Depth=1
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s3, s1
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: v_readlane_b32 s4, v3, s3
+; GFX12DAGISEL-NEXT: s_bitset0_b32 s1, s3
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX12DAGISEL-NEXT: v_max_num_f32_e64 v2, s2, s4
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB2_6
+; GFX12DAGISEL-NEXT: ; %bb.7:
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12DAGISEL-NEXT: v_mov_b32_e32 v4, s2
+; GFX12DAGISEL-NEXT: .LBB2_8: ; %endif
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX12DAGISEL-NEXT: global_store_b32 v[0:1], v4, off
+; GFX12DAGISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%d_cmp = icmp ult i32 %tid, 16
@@ -923,6 +1021,1188 @@ endif:
store float %combine, ptr addrspace(1) %out
ret void
}
+
+define amdgpu_kernel void @uniform_value_double(ptr addrspace(1) %out, double %in) {
+; GFX8DAGISEL-LABEL: uniform_value_double:
+; GFX8DAGISEL: ; %bb.0: ; %entry
+; GFX8DAGISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s3
+; GFX8DAGISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8DAGISEL-NEXT: s_endpgm
+;
+; GFX8GISEL-LABEL: uniform_value_double:
+; GFX8GISEL: ; %bb.0: ; %entry
+; GFX8GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX8GISEL-NEXT: s_endpgm
+;
+; GFX9DAGISEL-LABEL: uniform_value_double:
+; GFX9DAGISEL: ; %bb.0: ; %entry
+; GFX9DAGISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX9DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX9DAGISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX9DAGISEL-NEXT: s_endpgm
+;
+; GFX9GISEL-LABEL: uniform_value_double:
+; GFX9GISEL: ; %bb.0: ; %entry
+; GFX9GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX9GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX9GISEL-NEXT: s_endpgm
+;
+; GFX10DAGISEL-LABEL: uniform_value_double:
+; GFX10DAGISEL: ; %bb.0: ; %entry
+; GFX10DAGISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX10DAGISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX10DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10DAGISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX10DAGISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX10DAGISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX10DAGISEL-NEXT: s_endpgm
+;
+; GFX10GISEL-LABEL: uniform_value_double:
+; GFX10GISEL: ; %bb.0: ; %entry
+; GFX10GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX10GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX10GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX10GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX10GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX10GISEL-NEXT: s_endpgm
+;
+; GFX1164DAGISEL-LABEL: uniform_value_double:
+; GFX1164DAGISEL: ; %bb.0: ; %entry
+; GFX1164DAGISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX1164DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX1164DAGISEL-NEXT: s_endpgm
+;
+; GFX1164GISEL-LABEL: uniform_value_double:
+; GFX1164GISEL: ; %bb.0: ; %entry
+; GFX1164GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX1164GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX1164GISEL-NEXT: s_endpgm
+;
+; GFX1132DAGISEL-LABEL: uniform_value_double:
+; GFX1132DAGISEL: ; %bb.0: ; %entry
+; GFX1132DAGISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX1132DAGISEL-NEXT: s_endpgm
+;
+; GFX1132GISEL-LABEL: uniform_value_double:
+; GFX1132GISEL: ; %bb.0: ; %entry
+; GFX1132GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX1132GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX1132GISEL-NEXT: s_endpgm
+;
+; GFX12DAGISEL-LABEL: uniform_value_double:
+; GFX12DAGISEL: ; %bb.0: ; %entry
+; GFX12DAGISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12DAGISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12DAGISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX12DAGISEL-NEXT: s_endpgm
+entry:
+ %result = call double @llvm.amdgcn.wave.reduce.fmax(double %in, i32 1)
+ store double %result, ptr addrspace(1) %out
+ ret void
+}
+
+define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
+; GFX8DAGISEL-LABEL: divergent_value_double:
+; GFX8DAGISEL: ; %bb.0: ; %entry
+; GFX8DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8DAGISEL-NEXT: s_mov_b32 s6, 0
+; GFX8DAGISEL-NEXT: s_mov_b32 s7, 0x7ff80000
+; GFX8DAGISEL-NEXT: s_mov_b64 s[4:5], exec
+; GFX8DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX8DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v5, s7
+; GFX8DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX8DAGISEL-NEXT: v_max_f64 v[4:5], s[8:9], v[4:5]
+; GFX8DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX8DAGISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s6, v4
+; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s7, v5
+; GFX8DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX8DAGISEL-NEXT: ; %bb.2:
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s7
+; GFX8DAGISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8DAGISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX8DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8GISEL-LABEL: divergent_value_double:
+; GFX8GISEL: ; %bb.0: ; %entry
+; GFX8GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8GISEL-NEXT: s_mov_b32 s6, 0
+; GFX8GISEL-NEXT: s_mov_b32 s7, 0x7ff80000
+; GFX8GISEL-NEXT: s_mov_b64 s[4:5], exec
+; GFX8GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX8GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX8GISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX8GISEL-NEXT: v_mov_b32_e32 v5, s7
+; GFX8GISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX8GISEL-NEXT: v_max_f64 v[4:5], s[8:9], v[4:5]
+; GFX8GISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX8GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s6, v4
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s7, v5
+; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX8GISEL-NEXT: ; %bb.2:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s7
+; GFX8GISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX8GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9DAGISEL-LABEL: divergent_value_double:
+; GFX9DAGISEL: ; %bb.0: ; %entry
+; GFX9DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9DAGISEL-NEXT: s_mov_b32 s6, 0
+; GFX9DAGISEL-NEXT: s_mov_b32 s7, 0x7ff80000
+; GFX9DAGISEL-NEXT: s_mov_b64 s[4:5], exec
+; GFX9DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX9DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v5, s7
+; GFX9DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX9DAGISEL-NEXT: v_max_f64 v[4:5], s[8:9], v[4:5]
+; GFX9DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX9DAGISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s6, v4
+; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s7, v5
+; GFX9DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX9DAGISEL-NEXT: ; %bb.2:
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v3, s7
+; GFX9DAGISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX9DAGISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9GISEL-LABEL: divergent_value_double:
+; GFX9GISEL: ; %bb.0: ; %entry
+; GFX9GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9GISEL-NEXT: s_mov_b32 s6, 0
+; GFX9GISEL-NEXT: s_mov_b32 s7, 0x7ff80000
+; GFX9GISEL-NEXT: s_mov_b64 s[4:5], exec
+; GFX9GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX9GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX9GISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX9GISEL-NEXT: v_mov_b32_e32 v5, s7
+; GFX9GISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX9GISEL-NEXT: v_max_f64 v[4:5], s[8:9], v[4:5]
+; GFX9GISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX9GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s6, v4
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s7, v5
+; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX9GISEL-NEXT: ; %bb.2:
+; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX9GISEL-NEXT: v_mov_b32_e32 v3, s7
+; GFX9GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX9GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1064DAGISEL-LABEL: divergent_value_double:
+; GFX1064DAGISEL: ; %bb.0: ; %entry
+; GFX1064DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1064DAGISEL-NEXT: s_mov_b32 s6, 0
+; GFX1064DAGISEL-NEXT: s_mov_b32 s7, 0x7ff80000
+; GFX1064DAGISEL-NEXT: s_mov_b64 s[4:5], exec
+; GFX1064DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
+; GFX1064DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX1064DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX1064DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX1064DAGISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX1064DAGISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[6:7]
+; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s6, v4
+; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s7, v5
+; GFX1064DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX1064DAGISEL-NEXT: ; %bb.2:
+; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v3, s7
+; GFX1064DAGISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX1064DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1064GISEL-LABEL: divergent_value_double:
+; GFX1064GISEL: ; %bb.0: ; %entry
+; GFX1064GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1064GISEL-NEXT: s_mov_b32 s6, 0
+; GFX1064GISEL-NEXT: s_mov_b32 s7, 0x7ff80000
+; GFX1064GISEL-NEXT: s_mov_b64 s[4:5], exec
+; GFX1064GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX1064GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
+; GFX1064GISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX1064GISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX1064GISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX1064GISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[6:7]
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s6, v4
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s7, v5
+; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX1064GISEL-NEXT: ; %bb.2:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v3, s7
+; GFX1064GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX1064GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1032DAGISEL-LABEL: divergent_value_double:
+; GFX1032DAGISEL: ; %bb.0: ; %entry
+; GFX1032DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1032DAGISEL-NEXT: s_mov_b32 s4, 0
+; GFX1032DAGISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1032DAGISEL-NEXT: s_mov_b32 s6, exec_lo
+; GFX1032DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s7, s6
+; GFX1032DAGISEL-NEXT: v_readlane_b32 s8, v2, s7
+; GFX1032DAGISEL-NEXT: v_readlane_b32 s9, v3, s7
+; GFX1032DAGISEL-NEXT: s_bitset0_b32 s6, s7
+; GFX1032DAGISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1032DAGISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[4:5]
+; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1032DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX1032DAGISEL-NEXT: ; %bb.2:
+; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX1032DAGISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX1032DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1032GISEL-LABEL: divergent_value_double:
+; GFX1032GISEL: ; %bb.0: ; %entry
+; GFX1032GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1032GISEL-NEXT: s_mov_b32 s4, 0
+; GFX1032GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1032GISEL-NEXT: s_mov_b32 s6, exec_lo
+; GFX1032GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX1032GISEL-NEXT: s_ff1_i32_b32 s7, s6
+; GFX1032GISEL-NEXT: v_readlane_b32 s8, v2, s7
+; GFX1032GISEL-NEXT: v_readlane_b32 s9, v3, s7
+; GFX1032GISEL-NEXT: s_bitset0_b32 s6, s7
+; GFX1032GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1032GISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[4:5]
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX1032GISEL-NEXT: ; %bb.2:
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX1032GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1164DAGISEL-LABEL: divergent_value_double:
+; GFX1164DAGISEL: ; %bb.0: ; %entry
+; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1164DAGISEL-NEXT: s_mov_b32 s2, 0
+; GFX1164DAGISEL-NEXT: s_mov_b32 s3, 0x7ff80000
+; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec
+; GFX1164DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s6, s[0:1]
+; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s6
+; GFX1164DAGISEL-NEXT: v_readlane_b32 s5, v3, s6
+; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s6
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX1164DAGISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[2:3]
+; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX1164DAGISEL-NEXT: ; %bb.2:
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v3, s3
+; GFX1164DAGISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1164GISEL-LABEL: divergent_value_double:
+; GFX1164GISEL: ; %bb.0: ; %entry
+; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1164GISEL-NEXT: s_mov_b32 s2, 0
+; GFX1164GISEL-NEXT: s_mov_b32 s3, 0x7ff80000
+; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec
+; GFX1164GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: s_ctz_i32_b64 s6, s[0:1]
+; GFX1164GISEL-NEXT: v_readlane_b32 s4, v2, s6
+; GFX1164GISEL-NEXT: v_readlane_b32 s5, v3, s6
+; GFX1164GISEL-NEXT: s_bitset0_b64 s[0:1], s6
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX1164GISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[2:3]
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX1164GISEL-NEXT: ; %bb.2:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v3, s3
+; GFX1164GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1132DAGISEL-LABEL: divergent_value_double:
+; GFX1132DAGISEL: ; %bb.0: ; %entry
+; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0
+; GFX1132DAGISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX1132DAGISEL-NEXT: s_mov_b32 s2, exec_lo
+; GFX1132DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s3, s2
+; GFX1132DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
+; GFX1132DAGISEL-NEXT: v_readlane_b32 s5, v3, s3
+; GFX1132DAGISEL-NEXT: s_bitset0_b32 s2, s3
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1132DAGISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[0:1]
+; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX1132DAGISEL-NEXT: ; %bb.2:
+; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX1132DAGISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1132GISEL-LABEL: divergent_value_double:
+; GFX1132GISEL: ; %bb.0: ; %entry
+; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1132GISEL-NEXT: s_mov_b32 s0, 0
+; GFX1132GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
+; GFX1132GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2
+; GFX1132GISEL-NEXT: v_readlane_b32 s4, v2, s3
+; GFX1132GISEL-NEXT: v_readlane_b32 s5, v3, s3
+; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1132GISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[0:1]
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX1132GISEL-NEXT: ; %bb.2:
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX1132GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12DAGISEL-LABEL: divergent_value_double:
+; GFX12DAGISEL: ; %bb.0: ; %entry
+; GFX12DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_expcnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12DAGISEL-NEXT: s_mov_b32 s0, 0
+; GFX12DAGISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX12DAGISEL-NEXT: s_mov_b32 s2, exec_lo
+; GFX12DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s3, s2
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
+; GFX12DAGISEL-NEXT: v_readlane_b32 s5, v3, s3
+; GFX12DAGISEL-NEXT: s_bitset0_b32 s2, s3
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX12DAGISEL-NEXT: v_max_num_f64_e64 v[4:5], s[4:5], s[0:1]
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX12DAGISEL-NEXT: ; %bb.2:
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12DAGISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX12DAGISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX12DAGISEL-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %result = call double @llvm.amdgcn.wave.reduce.fmax(double %in, i32 1)
+ store double %result, ptr addrspace(1) %out
+ ret void
+}
+
+define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2) {
+; GFX8DAGISEL-LABEL: divergent_cfg_double:
+; GFX8DAGISEL: ; %bb.0: ; %entry
+; GFX8DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8DAGISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX8DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc, 15, v6
+; GFX8DAGISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX8DAGISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX8DAGISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX8DAGISEL-NEXT: s_cbranch_execz .LBB5_4
+; GFX8DAGISEL-NEXT: ; %bb.1: ; %else
+; GFX8DAGISEL-NEXT: s_mov_b32 s8, 0
+; GFX8DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX8DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX8DAGISEL-NEXT: v_readlane_b32 s10, v2, s12
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v5, s9
+; GFX8DAGISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX8DAGISEL-NEXT: v_max_f64 v[4:5], s[10:11], v[4:5]
+; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX8DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s9, v5
+; GFX8DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX8DAGISEL-NEXT: ; %bb.3:
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX8DAGISEL-NEXT: ; implicit-def: $vgpr4
+; GFX8DAGISEL-NEXT: ; implicit-def: $vgpr5
+; GFX8DAGISEL-NEXT: .LBB5_4: ; %Flow
+; GFX8DAGISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX8DAGISEL-NEXT: s_cbranch_execz .LBB5_8
+; GFX8DAGISEL-NEXT: ; %bb.5: ; %if
+; GFX8DAGISEL-NEXT: s_mov_b32 s8, 0
+; GFX8DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX8DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
+; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s8
+; GFX8DAGISEL-NEXT: v_readlane_b32 s10, v4, s12
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s9
+; GFX8DAGISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX8DAGISEL-NEXT: v_max_f64 v[2:3], s[10:11], v[2:3]
+; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX8DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s8, v2
+; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s9, v3
+; GFX8DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
+; GFX8DAGISEL-NEXT: ; %bb.7:
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX8DAGISEL-NEXT: .LBB5_8: ; %endif
+; GFX8DAGISEL-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX8DAGISEL-NEXT: flat_store_dwordx2 v[0:1], v[6:7]
+; GFX8DAGISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX8DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8GISEL-LABEL: divergent_cfg_double:
+; GFX8GISEL: ; %bb.0: ; %entry
+; GFX8GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX8GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v6
+; GFX8GISEL-NEXT: ; implicit-def: $sgpr4_sgpr5
+; GFX8GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX8GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB5_3
+; GFX8GISEL-NEXT: ; %bb.1: ; %else
+; GFX8GISEL-NEXT: s_mov_b32 s4, 0
+; GFX8GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX8GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX8GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX8GISEL-NEXT: v_readlane_b32 s10, v2, s12
+; GFX8GISEL-NEXT: v_mov_b32_e32 v5, s5
+; GFX8GISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX8GISEL-NEXT: v_max_f64 v[4:5], s[10:11], v[4:5]
+; GFX8GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX8GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX8GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX8GISEL-NEXT: ; implicit-def: $vgpr5
+; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX8GISEL-NEXT: .LBB5_3: ; %Flow
+; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB5_6
+; GFX8GISEL-NEXT: ; %bb.4: ; %if
+; GFX8GISEL-NEXT: s_mov_b32 s4, 0
+; GFX8GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX8GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX8GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
+; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX8GISEL-NEXT: v_readlane_b32 s10, v4, s12
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX8GISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX8GISEL-NEXT: v_max_f64 v[2:3], s[10:11], v[2:3]
+; GFX8GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX8GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB5_5
+; GFX8GISEL-NEXT: .LBB5_6: ; %endif
+; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX8GISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX8GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9DAGISEL-LABEL: divergent_cfg_double:
+; GFX9DAGISEL: ; %bb.0: ; %entry
+; GFX9DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9DAGISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX9DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc, 15, v6
+; GFX9DAGISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX9DAGISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX9DAGISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9DAGISEL-NEXT: s_cbranch_execz .LBB5_4
+; GFX9DAGISEL-NEXT: ; %bb.1: ; %else
+; GFX9DAGISEL-NEXT: s_mov_b32 s8, 0
+; GFX9DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX9DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX9DAGISEL-NEXT: v_readlane_b32 s10, v2, s12
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v5, s9
+; GFX9DAGISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX9DAGISEL-NEXT: v_max_f64 v[4:5], s[10:11], v[4:5]
+; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX9DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s9, v5
+; GFX9DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX9DAGISEL-NEXT: ; %bb.3:
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX9DAGISEL-NEXT: ; implicit-def: $vgpr4
+; GFX9DAGISEL-NEXT: ; implicit-def: $vgpr5
+; GFX9DAGISEL-NEXT: .LBB5_4: ; %Flow
+; GFX9DAGISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9DAGISEL-NEXT: s_cbranch_execz .LBB5_8
+; GFX9DAGISEL-NEXT: ; %bb.5: ; %if
+; GFX9DAGISEL-NEXT: s_mov_b32 s8, 0
+; GFX9DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX9DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
+; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v2, s8
+; GFX9DAGISEL-NEXT: v_readlane_b32 s10, v4, s12
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v3, s9
+; GFX9DAGISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX9DAGISEL-NEXT: v_max_f64 v[2:3], s[10:11], v[2:3]
+; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX9DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s8, v2
+; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s9, v3
+; GFX9DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
+; GFX9DAGISEL-NEXT: ; %bb.7:
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX9DAGISEL-NEXT: .LBB5_8: ; %endif
+; GFX9DAGISEL-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9DAGISEL-NEXT: global_store_dwordx2 v[0:1], v[6:7], off
+; GFX9DAGISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9GISEL-LABEL: divergent_cfg_double:
+; GFX9GISEL: ; %bb.0: ; %entry
+; GFX9GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX9GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v6
+; GFX9GISEL-NEXT: ; implicit-def: $sgpr4_sgpr5
+; GFX9GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX9GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB5_3
+; GFX9GISEL-NEXT: ; %bb.1: ; %else
+; GFX9GISEL-NEXT: s_mov_b32 s4, 0
+; GFX9GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX9GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX9GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX9GISEL-NEXT: v_readlane_b32 s10, v2, s12
+; GFX9GISEL-NEXT: v_mov_b32_e32 v5, s5
+; GFX9GISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX9GISEL-NEXT: v_max_f64 v[4:5], s[10:11], v[4:5]
+; GFX9GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX9GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX9GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX9GISEL-NEXT: ; implicit-def: $vgpr5
+; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX9GISEL-NEXT: .LBB5_3: ; %Flow
+; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB5_6
+; GFX9GISEL-NEXT: ; %bb.4: ; %if
+; GFX9GISEL-NEXT: s_mov_b32 s4, 0
+; GFX9GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX9GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX9GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
+; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX9GISEL-NEXT: v_readlane_b32 s10, v4, s12
+; GFX9GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX9GISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX9GISEL-NEXT: v_max_f64 v[2:3], s[10:11], v[2:3]
+; GFX9GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX9GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB5_5
+; GFX9GISEL-NEXT: .LBB5_6: ; %endif
+; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX9GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX9GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX9GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1064DAGISEL-LABEL: divergent_cfg_double:
+; GFX1064DAGISEL: ; %bb.0: ; %entry
+; GFX1064DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1064DAGISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX1064DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc, 15, v6
+; GFX1064DAGISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1064DAGISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX1064DAGISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX1064DAGISEL-NEXT: s_cbranch_execz .LBB5_4
+; GFX1064DAGISEL-NEXT: ; %bb.1: ; %else
+; GFX1064DAGISEL-NEXT: s_mov_b32 s8, 0
+; GFX1064DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX1064DAGISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX1064DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX1064DAGISEL-NEXT: v_readlane_b32 s10, v2, s12
+; GFX1064DAGISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX1064DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX1064DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX1064DAGISEL-NEXT: v_max_f64 v[4:5], s[10:11], s[8:9]
+; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s9, v5
+; GFX1064DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX1064DAGISEL-NEXT: ; %bb.3:
+; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX1064DAGISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1064DAGISEL-NEXT: ; implicit-def: $vgpr5
+; GFX1064DAGISEL-NEXT: .LBB5_4: ; %Flow
+; GFX1064DAGISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX1064DAGISEL-NEXT: s_cbranch_execz .LBB5_8
+; GFX1064DAGISEL-NEXT: ; %bb.5: ; %if
+; GFX1064DAGISEL-NEXT: s_mov_b32 s8, 0
+; GFX1064DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX1064DAGISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX1064DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
+; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX1064DAGISEL-NEXT: v_readlane_b32 s10, v4, s12
+; GFX1064DAGISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX1064DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX1064DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX1064DAGISEL-NEXT: v_max_f64 v[2:3], s[10:11], s[8:9]
+; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s8, v2
+; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s9, v3
+; GFX1064DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
+; GFX1064DAGISEL-NEXT: ; %bb.7:
+; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX1064DAGISEL-NEXT: .LBB5_8: ; %endif
+; GFX1064DAGISEL-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX1064DAGISEL-NEXT: global_store_dwordx2 v[0:1], v[6:7], off
+; GFX1064DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1064GISEL-LABEL: divergent_cfg_double:
+; GFX1064GISEL: ; %bb.0: ; %entry
+; GFX1064GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1064GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX1064GISEL-NEXT: ; implicit-def: $sgpr4_sgpr5
+; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v6
+; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1064GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB5_3
+; GFX1064GISEL-NEXT: ; %bb.1: ; %else
+; GFX1064GISEL-NEXT: s_mov_b32 s4, 0
+; GFX1064GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1064GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX1064GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX1064GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX1064GISEL-NEXT: v_readlane_b32 s10, v2, s12
+; GFX1064GISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX1064GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
+; GFX1064GISEL-NEXT: v_max_f64 v[4:5], s[10:11], s[4:5]
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1064GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1064GISEL-NEXT: ; implicit-def: $vgpr5
+; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX1064GISEL-NEXT: .LBB5_3: ; %Flow
+; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB5_6
+; GFX1064GISEL-NEXT: ; %bb.4: ; %if
+; GFX1064GISEL-NEXT: s_mov_b32 s4, 0
+; GFX1064GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1064GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX1064GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
+; GFX1064GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX1064GISEL-NEXT: v_readlane_b32 s10, v4, s12
+; GFX1064GISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX1064GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
+; GFX1064GISEL-NEXT: v_max_f64 v[2:3], s[10:11], s[4:5]
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB5_5
+; GFX1064GISEL-NEXT: .LBB5_6: ; %endif
+; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX1064GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX1064GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1032DAGISEL-LABEL: divergent_cfg_double:
+; GFX1032DAGISEL: ; %bb.0: ; %entry
+; GFX1032DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1032DAGISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX1032DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc_lo, 15, v6
+; GFX1032DAGISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1032DAGISEL-NEXT: s_and_saveexec_b32 s4, vcc_lo
+; GFX1032DAGISEL-NEXT: s_xor_b32 s6, exec_lo, s4
+; GFX1032DAGISEL-NEXT: s_cbranch_execz .LBB5_4
+; GFX1032DAGISEL-NEXT: ; %bb.1: ; %else
+; GFX1032DAGISEL-NEXT: s_mov_b32 s4, 0
+; GFX1032DAGISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1032DAGISEL-NEXT: s_mov_b32 s7, exec_lo
+; GFX1032DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s10, s7
+; GFX1032DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX1032DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX1032DAGISEL-NEXT: s_bitset0_b32 s7, s10
+; GFX1032DAGISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1032DAGISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[4:5]
+; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1032DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX1032DAGISEL-NEXT: ; %bb.3:
+; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v7, s5
+; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v6, s4
+; GFX1032DAGISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1032DAGISEL-NEXT: ; implicit-def: $vgpr5
+; GFX1032DAGISEL-NEXT: .LBB5_4: ; %Flow
+; GFX1032DAGISEL-NEXT: s_andn2_saveexec_b32 s6, s6
+; GFX1032DAGISEL-NEXT: s_cbranch_execz .LBB5_8
+; GFX1032DAGISEL-NEXT: ; %bb.5: ; %if
+; GFX1032DAGISEL-NEXT: s_mov_b32 s4, 0
+; GFX1032DAGISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1032DAGISEL-NEXT: s_mov_b32 s7, exec_lo
+; GFX1032DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
+; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s10, s7
+; GFX1032DAGISEL-NEXT: v_readlane_b32 s8, v4, s10
+; GFX1032DAGISEL-NEXT: v_readlane_b32 s9, v5, s10
+; GFX1032DAGISEL-NEXT: s_bitset0_b32 s7, s10
+; GFX1032DAGISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1032DAGISEL-NEXT: v_max_f64 v[2:3], s[8:9], s[4:5]
+; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX1032DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
+; GFX1032DAGISEL-NEXT: ; %bb.7:
+; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v7, s5
+; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v6, s4
+; GFX1032DAGISEL-NEXT: .LBB5_8: ; %endif
+; GFX1032DAGISEL-NEXT: s_or_b32 exec_lo, exec_lo, s6
+; GFX1032DAGISEL-NEXT: global_store_dwordx2 v[0:1], v[6:7], off
+; GFX1032DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1032GISEL-LABEL: divergent_cfg_double:
+; GFX1032GISEL: ; %bb.0: ; %entry
+; GFX1032GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1032GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX1032GISEL-NEXT: ; implicit-def: $sgpr4_sgpr5
+; GFX1032GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v6
+; GFX1032GISEL-NEXT: s_and_saveexec_b32 s6, vcc_lo
+; GFX1032GISEL-NEXT: s_xor_b32 s6, exec_lo, s6
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB5_3
+; GFX1032GISEL-NEXT: ; %bb.1: ; %else
+; GFX1032GISEL-NEXT: s_mov_b32 s4, 0
+; GFX1032GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1032GISEL-NEXT: s_mov_b32 s7, exec_lo
+; GFX1032GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX1032GISEL-NEXT: s_ff1_i32_b32 s10, s7
+; GFX1032GISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX1032GISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX1032GISEL-NEXT: s_bitset0_b32 s7, s10
+; GFX1032GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1032GISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[4:5]
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1032GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1032GISEL-NEXT: ; implicit-def: $vgpr5
+; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX1032GISEL-NEXT: .LBB5_3: ; %Flow
+; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s6, s6
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB5_6
+; GFX1032GISEL-NEXT: ; %bb.4: ; %if
+; GFX1032GISEL-NEXT: s_mov_b32 s4, 0
+; GFX1032GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1032GISEL-NEXT: s_mov_b32 s7, exec_lo
+; GFX1032GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
+; GFX1032GISEL-NEXT: s_ff1_i32_b32 s10, s7
+; GFX1032GISEL-NEXT: v_readlane_b32 s8, v4, s10
+; GFX1032GISEL-NEXT: v_readlane_b32 s9, v5, s10
+; GFX1032GISEL-NEXT: s_bitset0_b32 s7, s10
+; GFX1032GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1032GISEL-NEXT: v_max_f64 v[2:3], s[8:9], s[4:5]
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB5_5
+; GFX1032GISEL-NEXT: .LBB5_6: ; %endif
+; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s6
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX1032GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1164DAGISEL-LABEL: divergent_cfg_double:
+; GFX1164DAGISEL: ; %bb.0: ; %entry
+; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1164DAGISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc, 15, v6
+; GFX1164DAGISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1164DAGISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX1164DAGISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
+; GFX1164DAGISEL-NEXT: s_cbranch_execz .LBB5_4
+; GFX1164DAGISEL-NEXT: ; %bb.1: ; %else
+; GFX1164DAGISEL-NEXT: s_mov_b32 s4, 0
+; GFX1164DAGISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec
+; GFX1164DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s8, s[2:3]
+; GFX1164DAGISEL-NEXT: v_readlane_b32 s6, v2, s8
+; GFX1164DAGISEL-NEXT: v_readlane_b32 s7, v3, s8
+; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[2:3], s8
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX1164DAGISEL-NEXT: v_max_f64 v[4:5], s[6:7], s[4:5]
+; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX1164DAGISEL-NEXT: ; %bb.3:
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v7, s5
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v6, s4
+; GFX1164DAGISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1164DAGISEL-NEXT: ; implicit-def: $vgpr5
+; GFX1164DAGISEL-NEXT: .LBB5_4: ; %Flow
+; GFX1164DAGISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1]
+; GFX1164DAGISEL-NEXT: s_cbranch_execz .LBB5_8
+; GFX1164DAGISEL-NEXT: ; %bb.5: ; %if
+; GFX1164DAGISEL-NEXT: s_mov_b32 s4, 0
+; GFX1164DAGISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec
+; GFX1164DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s8, s[2:3]
+; GFX1164DAGISEL-NEXT: v_readlane_b32 s6, v4, s8
+; GFX1164DAGISEL-NEXT: v_readlane_b32 s7, v5, s8
+; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[2:3], s8
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX1164DAGISEL-NEXT: v_max_f64 v[2:3], s[6:7], s[4:5]
+; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
+; GFX1164DAGISEL-NEXT: ; %bb.7:
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v7, s5
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v6, s4
+; GFX1164DAGISEL-NEXT: .LBB5_8: ; %endif
+; GFX1164DAGISEL-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1164DAGISEL-NEXT: global_store_b64 v[0:1], v[6:7], off
+; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1164GISEL-LABEL: divergent_cfg_double:
+; GFX1164GISEL: ; %bb.0: ; %entry
+; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1164GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
+; GFX1164GISEL-NEXT: ; implicit-def: $sgpr0_sgpr1
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v6
+; GFX1164GISEL-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB5_3
+; GFX1164GISEL-NEXT: ; %bb.1: ; %else
+; GFX1164GISEL-NEXT: s_mov_b32 s0, 0
+; GFX1164GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX1164GISEL-NEXT: s_mov_b64 s[4:5], exec
+; GFX1164GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: s_ctz_i32_b64 s8, s[4:5]
+; GFX1164GISEL-NEXT: v_readlane_b32 s6, v2, s8
+; GFX1164GISEL-NEXT: v_readlane_b32 s7, v3, s8
+; GFX1164GISEL-NEXT: s_bitset0_b64 s[4:5], s8
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX1164GISEL-NEXT: v_max_f64 v[4:5], s[6:7], s[0:1]
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1164GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1164GISEL-NEXT: ; implicit-def: $vgpr5
+; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX1164GISEL-NEXT: .LBB5_3: ; %Flow
+; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[2:3], s[2:3]
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB5_6
+; GFX1164GISEL-NEXT: ; %bb.4: ; %if
+; GFX1164GISEL-NEXT: s_mov_b32 s0, 0
+; GFX1164GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX1164GISEL-NEXT: s_mov_b64 s[4:5], exec
+; GFX1164GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: s_ctz_i32_b64 s8, s[4:5]
+; GFX1164GISEL-NEXT: v_readlane_b32 s6, v4, s8
+; GFX1164GISEL-NEXT: v_readlane_b32 s7, v5, s8
+; GFX1164GISEL-NEXT: s_bitset0_b64 s[4:5], s8
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX1164GISEL-NEXT: v_max_f64 v[2:3], s[6:7], s[0:1]
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB5_5
+; GFX1164GISEL-NEXT: .LBB5_6: ; %endif
+; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v3, s1
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX1164GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1132DAGISEL-LABEL: divergent_cfg_double:
+; GFX1132DAGISEL: ; %bb.0: ; %entry
+; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1132DAGISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc_lo, 15, v6
+; GFX1132DAGISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1132DAGISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX1132DAGISEL-NEXT: s_xor_b32 s2, exec_lo, s0
+; GFX1132DAGISEL-NEXT: s_cbranch_execz .LBB5_4
+; GFX1132DAGISEL-NEXT: ; %bb.1: ; %else
+; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0
+; GFX1132DAGISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX1132DAGISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX1132DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX1132DAGISEL-NEXT: v_readlane_b32 s4, v2, s6
+; GFX1132DAGISEL-NEXT: v_readlane_b32 s5, v3, s6
+; GFX1132DAGISEL-NEXT: s_bitset0_b32 s3, s6
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1132DAGISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[0:1]
+; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX1132DAGISEL-NEXT: ; %bb.3:
+; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
+; GFX1132DAGISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1132DAGISEL-NEXT: ; implicit-def: $vgpr5
+; GFX1132DAGISEL-NEXT: .LBB5_4: ; %Flow
+; GFX1132DAGISEL-NEXT: s_and_not1_saveexec_b32 s2, s2
+; GFX1132DAGISEL-NEXT: s_cbranch_execz .LBB5_8
+; GFX1132DAGISEL-NEXT: ; %bb.5: ; %if
+; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0
+; GFX1132DAGISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX1132DAGISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX1132DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX1132DAGISEL-NEXT: v_readlane_b32 s4, v4, s6
+; GFX1132DAGISEL-NEXT: v_readlane_b32 s5, v5, s6
+; GFX1132DAGISEL-NEXT: s_bitset0_b32 s3, s6
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1132DAGISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[0:1]
+; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
+; GFX1132DAGISEL-NEXT: ; %bb.7:
+; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
+; GFX1132DAGISEL-NEXT: .LBB5_8: ; %endif
+; GFX1132DAGISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX1132DAGISEL-NEXT: global_store_b64 v[0:1], v[6:7], off
+; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1132GISEL-LABEL: divergent_cfg_double:
+; GFX1132GISEL: ; %bb.0: ; %entry
+; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1132GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
+; GFX1132GISEL-NEXT: ; implicit-def: $sgpr0_sgpr1
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1132GISEL-NEXT: v_cmpx_le_u32_e32 16, v6
+; GFX1132GISEL-NEXT: s_xor_b32 s2, exec_lo, s2
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB5_3
+; GFX1132GISEL-NEXT: ; %bb.1: ; %else
+; GFX1132GISEL-NEXT: s_mov_b32 s0, 0
+; GFX1132GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX1132GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX1132GISEL-NEXT: v_readlane_b32 s4, v2, s6
+; GFX1132GISEL-NEXT: v_readlane_b32 s5, v3, s6
+; GFX1132GISEL-NEXT: s_bitset0_b32 s3, s6
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1132GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1132GISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[0:1]
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1132GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1132GISEL-NEXT: ; implicit-def: $vgpr5
+; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX1132GISEL-NEXT: .LBB5_3: ; %Flow
+; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s2, s2
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB5_6
+; GFX1132GISEL-NEXT: ; %bb.4: ; %if
+; GFX1132GISEL-NEXT: s_mov_b32 s0, 0
+; GFX1132GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX1132GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX1132GISEL-NEXT: v_readlane_b32 s4, v4, s6
+; GFX1132GISEL-NEXT: v_readlane_b32 s5, v5, s6
+; GFX1132GISEL-NEXT: s_bitset0_b32 s3, s6
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1132GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1132GISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[0:1]
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB5_5
+; GFX1132GISEL-NEXT: .LBB5_6: ; %endif
+; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX1132GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12DAGISEL-LABEL: divergent_cfg_double:
+; GFX12DAGISEL: ; %bb.0: ; %entry
+; GFX12DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_expcnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12DAGISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc_lo, 15, v6
+; GFX12DAGISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX12DAGISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_xor_b32 s2, exec_lo, s0
+; GFX12DAGISEL-NEXT: s_cbranch_execz .LBB5_4
+; GFX12DAGISEL-NEXT: ; %bb.1: ; %else
+; GFX12DAGISEL-NEXT: s_mov_b32 s0, 0
+; GFX12DAGISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX12DAGISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX12DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: v_readlane_b32 s4, v2, s6
+; GFX12DAGISEL-NEXT: v_readlane_b32 s5, v3, s6
+; GFX12DAGISEL-NEXT: s_bitset0_b32 s3, s6
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX12DAGISEL-NEXT: v_max_num_f64_e64 v[4:5], s[4:5], s[0:1]
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX12DAGISEL-NEXT: ; %bb.3:
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12DAGISEL-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
+; GFX12DAGISEL-NEXT: ; implicit-def: $vgpr4
+; GFX12DAGISEL-NEXT: ; implicit-def: $vgpr5
+; GFX12DAGISEL-NEXT: .LBB5_4: ; %Flow
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_and_not1_saveexec_b32 s2, s2
+; GFX12DAGISEL-NEXT: s_cbranch_execz .LBB5_8
+; GFX12DAGISEL-NEXT: ; %bb.5: ; %if
+; GFX12DAGISEL-NEXT: s_mov_b32 s0, 0
+; GFX12DAGISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX12DAGISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX12DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: v_readlane_b32 s4, v4, s6
+; GFX12DAGISEL-NEXT: v_readlane_b32 s5, v5, s6
+; GFX12DAGISEL-NEXT: s_bitset0_b32 s3, s6
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX12DAGISEL-NEXT: v_max_num_f64_e64 v[2:3], s[4:5], s[0:1]
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
+; GFX12DAGISEL-NEXT: ; %bb.7:
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12DAGISEL-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
+; GFX12DAGISEL-NEXT: .LBB5_8: ; %endif
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX12DAGISEL-NEXT: global_store_b64 v[0:1], v[6:7], off
+; GFX12DAGISEL-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %d_cmp = icmp ult i32 %tid, 16
+ br i1 %d_cmp, label %if, label %else
+
+if:
+ %reducedValTid = call double @llvm.amdgcn.wave.reduce.fmax(double %in2, i32 1)
+ br label %endif
+
+else:
+ %reducedValIn = call double @llvm.amdgcn.wave.reduce.fmax(double %in, i32 1)
+ br label %endif
+
+endif:
+ %combine = phi double [%reducedValTid, %if], [%reducedValIn, %else]
+ store double %combine, ptr addrspace(1) %out
+ ret void
+}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX11DAGISEL: {{.*}}
; GFX11GISEL: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
index cb093cb14c4b5..075b5ad6539cf 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
@@ -11,6 +11,7 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1164GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11DAGISEL,GFX1132DAGISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11GISEL,GFX1132GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX12DAGISEL %s
define amdgpu_kernel void @uniform_value_float(ptr addrspace(1) %out, float %in) {
@@ -119,6 +120,14 @@ define amdgpu_kernel void @uniform_value_float(ptr addrspace(1) %out, float %in)
; GFX1132GISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX1132GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX1132GISEL-NEXT: s_endpgm
+;
+; GFX12DAGISEL-LABEL: uniform_value_float:
+; GFX12DAGISEL: ; %bb.0: ; %entry
+; GFX12DAGISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
+; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX12DAGISEL-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12DAGISEL-NEXT: s_endpgm
entry:
%result = call float @llvm.amdgcn.wave.reduce.fmin(float %in, i32 1)
store float %result, ptr addrspace(1) %out
@@ -357,6 +366,33 @@ define void @divergent_value_float(ptr addrspace(1) %out, float %in) {
; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s1
; GFX1132GISEL-NEXT: global_store_b32 v[0:1], v2, off
; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12DAGISEL-LABEL: divergent_value_float:
+; GFX12DAGISEL: ; %bb.0: ; %entry
+; GFX12DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_expcnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12DAGISEL-NEXT: s_mov_b32 s0, exec_lo
+; GFX12DAGISEL-NEXT: s_mov_b32 s1, 0x7fc00000
+; GFX12DAGISEL-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=1
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s2, s0
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: v_readlane_b32 s3, v2, s2
+; GFX12DAGISEL-NEXT: s_bitset0_b32 s0, s2
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX12DAGISEL-NEXT: v_min_num_f32_e64 v3, s1, s3
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX12DAGISEL-NEXT: ; %bb.2:
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12DAGISEL-NEXT: v_mov_b32_e32 v2, s1
+; GFX12DAGISEL-NEXT: global_store_b32 v[0:1], v2, off
+; GFX12DAGISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%result = call float @llvm.amdgcn.wave.reduce.fmin(float %in, i32 1)
store float %result, ptr addrspace(1) %out
@@ -905,6 +941,68 @@ define void @divergent_cfg_float(ptr addrspace(1) %out, float %in, float %in2) {
; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, s0
; GFX1132GISEL-NEXT: global_store_b32 v[0:1], v2, off
; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12DAGISEL-LABEL: divergent_cfg_float:
+; GFX12DAGISEL: ; %bb.0: ; %entry
+; GFX12DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_expcnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12DAGISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v31
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc_lo, 15, v4
+; GFX12DAGISEL-NEXT: ; implicit-def: $vgpr4
+; GFX12DAGISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_xor_b32 s0, exec_lo, s0
+; GFX12DAGISEL-NEXT: s_cbranch_execz .LBB2_4
+; GFX12DAGISEL-NEXT: ; %bb.1: ; %else
+; GFX12DAGISEL-NEXT: s_mov_b32 s1, exec_lo
+; GFX12DAGISEL-NEXT: s_mov_b32 s2, 0x7fc00000
+; GFX12DAGISEL-NEXT: .LBB2_2: ; =>This Inner Loop Header: Depth=1
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s3, s1
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
+; GFX12DAGISEL-NEXT: s_bitset0_b32 s1, s3
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX12DAGISEL-NEXT: v_min_num_f32_e64 v3, s2, s4
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s2, v3
+; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB2_2
+; GFX12DAGISEL-NEXT: ; %bb.3:
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12DAGISEL-NEXT: v_mov_b32_e32 v4, s2
+; GFX12DAGISEL-NEXT: ; implicit-def: $vgpr3
+; GFX12DAGISEL-NEXT: .LBB2_4: ; %Flow
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_and_not1_saveexec_b32 s0, s0
+; GFX12DAGISEL-NEXT: s_cbranch_execz .LBB2_8
+; GFX12DAGISEL-NEXT: ; %bb.5: ; %if
+; GFX12DAGISEL-NEXT: s_mov_b32 s1, exec_lo
+; GFX12DAGISEL-NEXT: s_mov_b32 s2, 0x7fc00000
+; GFX12DAGISEL-NEXT: .LBB2_6: ; =>This Inner Loop Header: Depth=1
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s3, s1
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: v_readlane_b32 s4, v3, s3
+; GFX12DAGISEL-NEXT: s_bitset0_b32 s1, s3
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX12DAGISEL-NEXT: v_min_num_f32_e64 v2, s2, s4
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB2_6
+; GFX12DAGISEL-NEXT: ; %bb.7:
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12DAGISEL-NEXT: v_mov_b32_e32 v4, s2
+; GFX12DAGISEL-NEXT: .LBB2_8: ; %endif
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX12DAGISEL-NEXT: global_store_b32 v[0:1], v4, off
+; GFX12DAGISEL-NEXT: s_setpc_b64 s[30:31]
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%d_cmp = icmp ult i32 %tid, 16
@@ -923,6 +1021,1188 @@ endif:
store float %combine, ptr addrspace(1) %out
ret void
}
+
+define amdgpu_kernel void @uniform_value_double(ptr addrspace(1) %out, double %in) {
+; GFX8DAGISEL-LABEL: uniform_value_double:
+; GFX8DAGISEL: ; %bb.0: ; %entry
+; GFX8DAGISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v1, s1
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s3
+; GFX8DAGISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8DAGISEL-NEXT: s_endpgm
+;
+; GFX8GISEL-LABEL: uniform_value_double:
+; GFX8GISEL: ; %bb.0: ; %entry
+; GFX8GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX8GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s1
+; GFX8GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX8GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX8GISEL-NEXT: s_endpgm
+;
+; GFX9DAGISEL-LABEL: uniform_value_double:
+; GFX9DAGISEL: ; %bb.0: ; %entry
+; GFX9DAGISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX9DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX9DAGISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX9DAGISEL-NEXT: s_endpgm
+;
+; GFX9GISEL-LABEL: uniform_value_double:
+; GFX9GISEL: ; %bb.0: ; %entry
+; GFX9GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX9GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX9GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX9GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX9GISEL-NEXT: s_endpgm
+;
+; GFX10DAGISEL-LABEL: uniform_value_double:
+; GFX10DAGISEL: ; %bb.0: ; %entry
+; GFX10DAGISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX10DAGISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX10DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10DAGISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX10DAGISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX10DAGISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX10DAGISEL-NEXT: s_endpgm
+;
+; GFX10GISEL-LABEL: uniform_value_double:
+; GFX10GISEL: ; %bb.0: ; %entry
+; GFX10GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX10GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX10GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX10GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX10GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX10GISEL-NEXT: s_endpgm
+;
+; GFX1164DAGISEL-LABEL: uniform_value_double:
+; GFX1164DAGISEL: ; %bb.0: ; %entry
+; GFX1164DAGISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1164DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX1164DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX1164DAGISEL-NEXT: s_endpgm
+;
+; GFX1164GISEL-LABEL: uniform_value_double:
+; GFX1164GISEL: ; %bb.0: ; %entry
+; GFX1164GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX1164GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX1164GISEL-NEXT: s_endpgm
+;
+; GFX1132DAGISEL-LABEL: uniform_value_double:
+; GFX1132DAGISEL: ; %bb.0: ; %entry
+; GFX1132DAGISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1132DAGISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1132DAGISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX1132DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX1132DAGISEL-NEXT: s_endpgm
+;
+; GFX1132GISEL-LABEL: uniform_value_double:
+; GFX1132GISEL: ; %bb.0: ; %entry
+; GFX1132GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX1132GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX1132GISEL-NEXT: s_endpgm
+;
+; GFX12DAGISEL-LABEL: uniform_value_double:
+; GFX12DAGISEL: ; %bb.0: ; %entry
+; GFX12DAGISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12DAGISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12DAGISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
+; GFX12DAGISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX12DAGISEL-NEXT: s_endpgm
+entry:
+ %result = call double @llvm.amdgcn.wave.reduce.fmin(double %in, i32 1)
+ store double %result, ptr addrspace(1) %out
+ ret void
+}
+
+define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
+; GFX8DAGISEL-LABEL: divergent_value_double:
+; GFX8DAGISEL: ; %bb.0: ; %entry
+; GFX8DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8DAGISEL-NEXT: s_mov_b32 s6, 0
+; GFX8DAGISEL-NEXT: s_mov_b32 s7, 0x7ff80000
+; GFX8DAGISEL-NEXT: s_mov_b64 s[4:5], exec
+; GFX8DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX8DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v5, s7
+; GFX8DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX8DAGISEL-NEXT: v_min_f64 v[4:5], s[8:9], v[4:5]
+; GFX8DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX8DAGISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s6, v4
+; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s7, v5
+; GFX8DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX8DAGISEL-NEXT: ; %bb.2:
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s7
+; GFX8DAGISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8DAGISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX8DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8GISEL-LABEL: divergent_value_double:
+; GFX8GISEL: ; %bb.0: ; %entry
+; GFX8GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8GISEL-NEXT: s_mov_b32 s6, 0
+; GFX8GISEL-NEXT: s_mov_b32 s7, 0x7ff80000
+; GFX8GISEL-NEXT: s_mov_b64 s[4:5], exec
+; GFX8GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX8GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX8GISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX8GISEL-NEXT: v_mov_b32_e32 v5, s7
+; GFX8GISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX8GISEL-NEXT: v_min_f64 v[4:5], s[8:9], v[4:5]
+; GFX8GISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX8GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s6, v4
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s7, v5
+; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX8GISEL-NEXT: ; %bb.2:
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s7
+; GFX8GISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX8GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9DAGISEL-LABEL: divergent_value_double:
+; GFX9DAGISEL: ; %bb.0: ; %entry
+; GFX9DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9DAGISEL-NEXT: s_mov_b32 s6, 0
+; GFX9DAGISEL-NEXT: s_mov_b32 s7, 0x7ff80000
+; GFX9DAGISEL-NEXT: s_mov_b64 s[4:5], exec
+; GFX9DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX9DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v5, s7
+; GFX9DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX9DAGISEL-NEXT: v_min_f64 v[4:5], s[8:9], v[4:5]
+; GFX9DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX9DAGISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s6, v4
+; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s7, v5
+; GFX9DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX9DAGISEL-NEXT: ; %bb.2:
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v3, s7
+; GFX9DAGISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX9DAGISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9GISEL-LABEL: divergent_value_double:
+; GFX9GISEL: ; %bb.0: ; %entry
+; GFX9GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9GISEL-NEXT: s_mov_b32 s6, 0
+; GFX9GISEL-NEXT: s_mov_b32 s7, 0x7ff80000
+; GFX9GISEL-NEXT: s_mov_b64 s[4:5], exec
+; GFX9GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX9GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s6
+; GFX9GISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX9GISEL-NEXT: v_mov_b32_e32 v5, s7
+; GFX9GISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX9GISEL-NEXT: v_min_f64 v[4:5], s[8:9], v[4:5]
+; GFX9GISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX9GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s6, v4
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s7, v5
+; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX9GISEL-NEXT: ; %bb.2:
+; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX9GISEL-NEXT: v_mov_b32_e32 v3, s7
+; GFX9GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX9GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1064DAGISEL-LABEL: divergent_value_double:
+; GFX1064DAGISEL: ; %bb.0: ; %entry
+; GFX1064DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1064DAGISEL-NEXT: s_mov_b32 s6, 0
+; GFX1064DAGISEL-NEXT: s_mov_b32 s7, 0x7ff80000
+; GFX1064DAGISEL-NEXT: s_mov_b64 s[4:5], exec
+; GFX1064DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
+; GFX1064DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX1064DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX1064DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX1064DAGISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX1064DAGISEL-NEXT: v_min_f64 v[4:5], s[8:9], s[6:7]
+; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s6, v4
+; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s7, v5
+; GFX1064DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX1064DAGISEL-NEXT: ; %bb.2:
+; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v3, s7
+; GFX1064DAGISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX1064DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1064GISEL-LABEL: divergent_value_double:
+; GFX1064GISEL: ; %bb.0: ; %entry
+; GFX1064GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1064GISEL-NEXT: s_mov_b32 s6, 0
+; GFX1064GISEL-NEXT: s_mov_b32 s7, 0x7ff80000
+; GFX1064GISEL-NEXT: s_mov_b64 s[4:5], exec
+; GFX1064GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX1064GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
+; GFX1064GISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX1064GISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX1064GISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX1064GISEL-NEXT: v_min_f64 v[4:5], s[8:9], s[6:7]
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s6, v4
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s7, v5
+; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX1064GISEL-NEXT: ; %bb.2:
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, s6
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v3, s7
+; GFX1064GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX1064GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1032DAGISEL-LABEL: divergent_value_double:
+; GFX1032DAGISEL: ; %bb.0: ; %entry
+; GFX1032DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1032DAGISEL-NEXT: s_mov_b32 s4, 0
+; GFX1032DAGISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1032DAGISEL-NEXT: s_mov_b32 s6, exec_lo
+; GFX1032DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s7, s6
+; GFX1032DAGISEL-NEXT: v_readlane_b32 s8, v2, s7
+; GFX1032DAGISEL-NEXT: v_readlane_b32 s9, v3, s7
+; GFX1032DAGISEL-NEXT: s_bitset0_b32 s6, s7
+; GFX1032DAGISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1032DAGISEL-NEXT: v_min_f64 v[4:5], s[8:9], s[4:5]
+; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1032DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX1032DAGISEL-NEXT: ; %bb.2:
+; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX1032DAGISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX1032DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1032GISEL-LABEL: divergent_value_double:
+; GFX1032GISEL: ; %bb.0: ; %entry
+; GFX1032GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1032GISEL-NEXT: s_mov_b32 s4, 0
+; GFX1032GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1032GISEL-NEXT: s_mov_b32 s6, exec_lo
+; GFX1032GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX1032GISEL-NEXT: s_ff1_i32_b32 s7, s6
+; GFX1032GISEL-NEXT: v_readlane_b32 s8, v2, s7
+; GFX1032GISEL-NEXT: v_readlane_b32 s9, v3, s7
+; GFX1032GISEL-NEXT: s_bitset0_b32 s6, s7
+; GFX1032GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1032GISEL-NEXT: v_min_f64 v[4:5], s[8:9], s[4:5]
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX1032GISEL-NEXT: ; %bb.2:
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX1032GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1164DAGISEL-LABEL: divergent_value_double:
+; GFX1164DAGISEL: ; %bb.0: ; %entry
+; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1164DAGISEL-NEXT: s_mov_b32 s2, 0
+; GFX1164DAGISEL-NEXT: s_mov_b32 s3, 0x7ff80000
+; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec
+; GFX1164DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s6, s[0:1]
+; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s6
+; GFX1164DAGISEL-NEXT: v_readlane_b32 s5, v3, s6
+; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s6
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX1164DAGISEL-NEXT: v_min_f64 v[4:5], s[4:5], s[2:3]
+; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX1164DAGISEL-NEXT: ; %bb.2:
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v3, s3
+; GFX1164DAGISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1164GISEL-LABEL: divergent_value_double:
+; GFX1164GISEL: ; %bb.0: ; %entry
+; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1164GISEL-NEXT: s_mov_b32 s2, 0
+; GFX1164GISEL-NEXT: s_mov_b32 s3, 0x7ff80000
+; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec
+; GFX1164GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: s_ctz_i32_b64 s6, s[0:1]
+; GFX1164GISEL-NEXT: v_readlane_b32 s4, v2, s6
+; GFX1164GISEL-NEXT: v_readlane_b32 s5, v3, s6
+; GFX1164GISEL-NEXT: s_bitset0_b64 s[0:1], s6
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX1164GISEL-NEXT: v_min_f64 v[4:5], s[4:5], s[2:3]
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX1164GISEL-NEXT: ; %bb.2:
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v3, s3
+; GFX1164GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1132DAGISEL-LABEL: divergent_value_double:
+; GFX1132DAGISEL: ; %bb.0: ; %entry
+; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0
+; GFX1132DAGISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX1132DAGISEL-NEXT: s_mov_b32 s2, exec_lo
+; GFX1132DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s3, s2
+; GFX1132DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
+; GFX1132DAGISEL-NEXT: v_readlane_b32 s5, v3, s3
+; GFX1132DAGISEL-NEXT: s_bitset0_b32 s2, s3
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1132DAGISEL-NEXT: v_min_f64 v[4:5], s[4:5], s[0:1]
+; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX1132DAGISEL-NEXT: ; %bb.2:
+; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX1132DAGISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1132GISEL-LABEL: divergent_value_double:
+; GFX1132GISEL: ; %bb.0: ; %entry
+; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1132GISEL-NEXT: s_mov_b32 s0, 0
+; GFX1132GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
+; GFX1132GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2
+; GFX1132GISEL-NEXT: v_readlane_b32 s4, v2, s3
+; GFX1132GISEL-NEXT: v_readlane_b32 s5, v3, s3
+; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1132GISEL-NEXT: v_min_f64 v[4:5], s[4:5], s[0:1]
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX1132GISEL-NEXT: ; %bb.2:
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX1132GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12DAGISEL-LABEL: divergent_value_double:
+; GFX12DAGISEL: ; %bb.0: ; %entry
+; GFX12DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_expcnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12DAGISEL-NEXT: s_mov_b32 s0, 0
+; GFX12DAGISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX12DAGISEL-NEXT: s_mov_b32 s2, exec_lo
+; GFX12DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s3, s2
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
+; GFX12DAGISEL-NEXT: v_readlane_b32 s5, v3, s3
+; GFX12DAGISEL-NEXT: s_bitset0_b32 s2, s3
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX12DAGISEL-NEXT: v_min_num_f64_e64 v[4:5], s[4:5], s[0:1]
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX12DAGISEL-NEXT: ; %bb.2:
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12DAGISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX12DAGISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX12DAGISEL-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %result = call double @llvm.amdgcn.wave.reduce.fmin(double %in, i32 1)
+ store double %result, ptr addrspace(1) %out
+ ret void
+}
+
+define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2) {
+; GFX8DAGISEL-LABEL: divergent_cfg_double:
+; GFX8DAGISEL: ; %bb.0: ; %entry
+; GFX8DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8DAGISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX8DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc, 15, v6
+; GFX8DAGISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX8DAGISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX8DAGISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX8DAGISEL-NEXT: s_cbranch_execz .LBB5_4
+; GFX8DAGISEL-NEXT: ; %bb.1: ; %else
+; GFX8DAGISEL-NEXT: s_mov_b32 s8, 0
+; GFX8DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX8DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX8DAGISEL-NEXT: v_readlane_b32 s10, v2, s12
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v5, s9
+; GFX8DAGISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX8DAGISEL-NEXT: v_min_f64 v[4:5], s[10:11], v[4:5]
+; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX8DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s9, v5
+; GFX8DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX8DAGISEL-NEXT: ; %bb.3:
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX8DAGISEL-NEXT: ; implicit-def: $vgpr4
+; GFX8DAGISEL-NEXT: ; implicit-def: $vgpr5
+; GFX8DAGISEL-NEXT: .LBB5_4: ; %Flow
+; GFX8DAGISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX8DAGISEL-NEXT: s_cbranch_execz .LBB5_8
+; GFX8DAGISEL-NEXT: ; %bb.5: ; %if
+; GFX8DAGISEL-NEXT: s_mov_b32 s8, 0
+; GFX8DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX8DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
+; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s8
+; GFX8DAGISEL-NEXT: v_readlane_b32 s10, v4, s12
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s9
+; GFX8DAGISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX8DAGISEL-NEXT: v_min_f64 v[2:3], s[10:11], v[2:3]
+; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX8DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s8, v2
+; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s9, v3
+; GFX8DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
+; GFX8DAGISEL-NEXT: ; %bb.7:
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX8DAGISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX8DAGISEL-NEXT: .LBB5_8: ; %endif
+; GFX8DAGISEL-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX8DAGISEL-NEXT: flat_store_dwordx2 v[0:1], v[6:7]
+; GFX8DAGISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX8DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8GISEL-LABEL: divergent_cfg_double:
+; GFX8GISEL: ; %bb.0: ; %entry
+; GFX8GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX8GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v6
+; GFX8GISEL-NEXT: ; implicit-def: $sgpr4_sgpr5
+; GFX8GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX8GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB5_3
+; GFX8GISEL-NEXT: ; %bb.1: ; %else
+; GFX8GISEL-NEXT: s_mov_b32 s4, 0
+; GFX8GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX8GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX8GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX8GISEL-NEXT: v_readlane_b32 s10, v2, s12
+; GFX8GISEL-NEXT: v_mov_b32_e32 v5, s5
+; GFX8GISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX8GISEL-NEXT: v_min_f64 v[4:5], s[10:11], v[4:5]
+; GFX8GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX8GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX8GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX8GISEL-NEXT: ; implicit-def: $vgpr5
+; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX8GISEL-NEXT: .LBB5_3: ; %Flow
+; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
+; GFX8GISEL-NEXT: s_cbranch_execz .LBB5_6
+; GFX8GISEL-NEXT: ; %bb.4: ; %if
+; GFX8GISEL-NEXT: s_mov_b32 s4, 0
+; GFX8GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX8GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX8GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
+; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX8GISEL-NEXT: v_readlane_b32 s10, v4, s12
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX8GISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX8GISEL-NEXT: v_min_f64 v[2:3], s[10:11], v[2:3]
+; GFX8GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX8GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB5_5
+; GFX8GISEL-NEXT: .LBB5_6: ; %endif
+; GFX8GISEL-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX8GISEL-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX8GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9DAGISEL-LABEL: divergent_cfg_double:
+; GFX9DAGISEL: ; %bb.0: ; %entry
+; GFX9DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9DAGISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX9DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc, 15, v6
+; GFX9DAGISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX9DAGISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX9DAGISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX9DAGISEL-NEXT: s_cbranch_execz .LBB5_4
+; GFX9DAGISEL-NEXT: ; %bb.1: ; %else
+; GFX9DAGISEL-NEXT: s_mov_b32 s8, 0
+; GFX9DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX9DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s8
+; GFX9DAGISEL-NEXT: v_readlane_b32 s10, v2, s12
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v5, s9
+; GFX9DAGISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX9DAGISEL-NEXT: v_min_f64 v[4:5], s[10:11], v[4:5]
+; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX9DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s9, v5
+; GFX9DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX9DAGISEL-NEXT: ; %bb.3:
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX9DAGISEL-NEXT: ; implicit-def: $vgpr4
+; GFX9DAGISEL-NEXT: ; implicit-def: $vgpr5
+; GFX9DAGISEL-NEXT: .LBB5_4: ; %Flow
+; GFX9DAGISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX9DAGISEL-NEXT: s_cbranch_execz .LBB5_8
+; GFX9DAGISEL-NEXT: ; %bb.5: ; %if
+; GFX9DAGISEL-NEXT: s_mov_b32 s8, 0
+; GFX9DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX9DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
+; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v2, s8
+; GFX9DAGISEL-NEXT: v_readlane_b32 s10, v4, s12
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v3, s9
+; GFX9DAGISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX9DAGISEL-NEXT: v_min_f64 v[2:3], s[10:11], v[2:3]
+; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX9DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s8, v2
+; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s9, v3
+; GFX9DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
+; GFX9DAGISEL-NEXT: ; %bb.7:
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX9DAGISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX9DAGISEL-NEXT: .LBB5_8: ; %endif
+; GFX9DAGISEL-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX9DAGISEL-NEXT: global_store_dwordx2 v[0:1], v[6:7], off
+; GFX9DAGISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9GISEL-LABEL: divergent_cfg_double:
+; GFX9GISEL: ; %bb.0: ; %entry
+; GFX9GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX9GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v6
+; GFX9GISEL-NEXT: ; implicit-def: $sgpr4_sgpr5
+; GFX9GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX9GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB5_3
+; GFX9GISEL-NEXT: ; %bb.1: ; %else
+; GFX9GISEL-NEXT: s_mov_b32 s4, 0
+; GFX9GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX9GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX9GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s4
+; GFX9GISEL-NEXT: v_readlane_b32 s10, v2, s12
+; GFX9GISEL-NEXT: v_mov_b32_e32 v5, s5
+; GFX9GISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX9GISEL-NEXT: v_min_f64 v[4:5], s[10:11], v[4:5]
+; GFX9GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX9GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX9GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX9GISEL-NEXT: ; implicit-def: $vgpr5
+; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX9GISEL-NEXT: .LBB5_3: ; %Flow
+; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
+; GFX9GISEL-NEXT: s_cbranch_execz .LBB5_6
+; GFX9GISEL-NEXT: ; %bb.4: ; %if
+; GFX9GISEL-NEXT: s_mov_b32 s4, 0
+; GFX9GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX9GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX9GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
+; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX9GISEL-NEXT: v_readlane_b32 s10, v4, s12
+; GFX9GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX9GISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX9GISEL-NEXT: v_min_f64 v[2:3], s[10:11], v[2:3]
+; GFX9GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX9GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB5_5
+; GFX9GISEL-NEXT: .LBB5_6: ; %endif
+; GFX9GISEL-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX9GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX9GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX9GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX9GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1064DAGISEL-LABEL: divergent_cfg_double:
+; GFX1064DAGISEL: ; %bb.0: ; %entry
+; GFX1064DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1064DAGISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX1064DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc, 15, v6
+; GFX1064DAGISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1064DAGISEL-NEXT: s_and_saveexec_b64 s[4:5], vcc
+; GFX1064DAGISEL-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX1064DAGISEL-NEXT: s_cbranch_execz .LBB5_4
+; GFX1064DAGISEL-NEXT: ; %bb.1: ; %else
+; GFX1064DAGISEL-NEXT: s_mov_b32 s8, 0
+; GFX1064DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX1064DAGISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX1064DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX1064DAGISEL-NEXT: v_readlane_b32 s10, v2, s12
+; GFX1064DAGISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX1064DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX1064DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX1064DAGISEL-NEXT: v_min_f64 v[4:5], s[10:11], s[8:9]
+; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s8, v4
+; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s9, v5
+; GFX1064DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX1064DAGISEL-NEXT: ; %bb.3:
+; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX1064DAGISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1064DAGISEL-NEXT: ; implicit-def: $vgpr5
+; GFX1064DAGISEL-NEXT: .LBB5_4: ; %Flow
+; GFX1064DAGISEL-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
+; GFX1064DAGISEL-NEXT: s_cbranch_execz .LBB5_8
+; GFX1064DAGISEL-NEXT: ; %bb.5: ; %if
+; GFX1064DAGISEL-NEXT: s_mov_b32 s8, 0
+; GFX1064DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
+; GFX1064DAGISEL-NEXT: s_mov_b64 s[6:7], exec
+; GFX1064DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
+; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX1064DAGISEL-NEXT: v_readlane_b32 s10, v4, s12
+; GFX1064DAGISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX1064DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX1064DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX1064DAGISEL-NEXT: v_min_f64 v[2:3], s[10:11], s[8:9]
+; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s8, v2
+; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s9, v3
+; GFX1064DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
+; GFX1064DAGISEL-NEXT: ; %bb.7:
+; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v6, s8
+; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v7, s9
+; GFX1064DAGISEL-NEXT: .LBB5_8: ; %endif
+; GFX1064DAGISEL-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX1064DAGISEL-NEXT: global_store_dwordx2 v[0:1], v[6:7], off
+; GFX1064DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1064GISEL-LABEL: divergent_cfg_double:
+; GFX1064GISEL: ; %bb.0: ; %entry
+; GFX1064GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1064GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX1064GISEL-NEXT: ; implicit-def: $sgpr4_sgpr5
+; GFX1064GISEL-NEXT: v_cmp_le_u32_e32 vcc, 16, v6
+; GFX1064GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1064GISEL-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB5_3
+; GFX1064GISEL-NEXT: ; %bb.1: ; %else
+; GFX1064GISEL-NEXT: s_mov_b32 s4, 0
+; GFX1064GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1064GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX1064GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX1064GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX1064GISEL-NEXT: v_readlane_b32 s10, v2, s12
+; GFX1064GISEL-NEXT: v_readlane_b32 s11, v3, s12
+; GFX1064GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
+; GFX1064GISEL-NEXT: v_min_f64 v[4:5], s[10:11], s[4:5]
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1064GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1064GISEL-NEXT: ; implicit-def: $vgpr5
+; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX1064GISEL-NEXT: .LBB5_3: ; %Flow
+; GFX1064GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
+; GFX1064GISEL-NEXT: s_cbranch_execz .LBB5_6
+; GFX1064GISEL-NEXT: ; %bb.4: ; %if
+; GFX1064GISEL-NEXT: s_mov_b32 s4, 0
+; GFX1064GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1064GISEL-NEXT: s_mov_b64 s[8:9], exec
+; GFX1064GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
+; GFX1064GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX1064GISEL-NEXT: v_readlane_b32 s10, v4, s12
+; GFX1064GISEL-NEXT: v_readlane_b32 s11, v5, s12
+; GFX1064GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
+; GFX1064GISEL-NEXT: v_min_f64 v[2:3], s[10:11], s[4:5]
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX1064GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB5_5
+; GFX1064GISEL-NEXT: .LBB5_6: ; %endif
+; GFX1064GISEL-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX1064GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX1064GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX1064GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1032DAGISEL-LABEL: divergent_cfg_double:
+; GFX1032DAGISEL: ; %bb.0: ; %entry
+; GFX1032DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1032DAGISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX1032DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc_lo, 15, v6
+; GFX1032DAGISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1032DAGISEL-NEXT: s_and_saveexec_b32 s4, vcc_lo
+; GFX1032DAGISEL-NEXT: s_xor_b32 s6, exec_lo, s4
+; GFX1032DAGISEL-NEXT: s_cbranch_execz .LBB5_4
+; GFX1032DAGISEL-NEXT: ; %bb.1: ; %else
+; GFX1032DAGISEL-NEXT: s_mov_b32 s4, 0
+; GFX1032DAGISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1032DAGISEL-NEXT: s_mov_b32 s7, exec_lo
+; GFX1032DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s10, s7
+; GFX1032DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX1032DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX1032DAGISEL-NEXT: s_bitset0_b32 s7, s10
+; GFX1032DAGISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1032DAGISEL-NEXT: v_min_f64 v[4:5], s[8:9], s[4:5]
+; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1032DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX1032DAGISEL-NEXT: ; %bb.3:
+; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v7, s5
+; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v6, s4
+; GFX1032DAGISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1032DAGISEL-NEXT: ; implicit-def: $vgpr5
+; GFX1032DAGISEL-NEXT: .LBB5_4: ; %Flow
+; GFX1032DAGISEL-NEXT: s_andn2_saveexec_b32 s6, s6
+; GFX1032DAGISEL-NEXT: s_cbranch_execz .LBB5_8
+; GFX1032DAGISEL-NEXT: ; %bb.5: ; %if
+; GFX1032DAGISEL-NEXT: s_mov_b32 s4, 0
+; GFX1032DAGISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1032DAGISEL-NEXT: s_mov_b32 s7, exec_lo
+; GFX1032DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
+; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s10, s7
+; GFX1032DAGISEL-NEXT: v_readlane_b32 s8, v4, s10
+; GFX1032DAGISEL-NEXT: v_readlane_b32 s9, v5, s10
+; GFX1032DAGISEL-NEXT: s_bitset0_b32 s7, s10
+; GFX1032DAGISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1032DAGISEL-NEXT: v_min_f64 v[2:3], s[8:9], s[4:5]
+; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX1032DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
+; GFX1032DAGISEL-NEXT: ; %bb.7:
+; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v7, s5
+; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v6, s4
+; GFX1032DAGISEL-NEXT: .LBB5_8: ; %endif
+; GFX1032DAGISEL-NEXT: s_or_b32 exec_lo, exec_lo, s6
+; GFX1032DAGISEL-NEXT: global_store_dwordx2 v[0:1], v[6:7], off
+; GFX1032DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1032GISEL-LABEL: divergent_cfg_double:
+; GFX1032GISEL: ; %bb.0: ; %entry
+; GFX1032GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1032GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX1032GISEL-NEXT: ; implicit-def: $sgpr4_sgpr5
+; GFX1032GISEL-NEXT: v_cmp_le_u32_e32 vcc_lo, 16, v6
+; GFX1032GISEL-NEXT: s_and_saveexec_b32 s6, vcc_lo
+; GFX1032GISEL-NEXT: s_xor_b32 s6, exec_lo, s6
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB5_3
+; GFX1032GISEL-NEXT: ; %bb.1: ; %else
+; GFX1032GISEL-NEXT: s_mov_b32 s4, 0
+; GFX1032GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1032GISEL-NEXT: s_mov_b32 s7, exec_lo
+; GFX1032GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX1032GISEL-NEXT: s_ff1_i32_b32 s10, s7
+; GFX1032GISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX1032GISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX1032GISEL-NEXT: s_bitset0_b32 s7, s10
+; GFX1032GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1032GISEL-NEXT: v_min_f64 v[4:5], s[8:9], s[4:5]
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1032GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1032GISEL-NEXT: ; implicit-def: $vgpr5
+; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX1032GISEL-NEXT: .LBB5_3: ; %Flow
+; GFX1032GISEL-NEXT: s_andn2_saveexec_b32 s6, s6
+; GFX1032GISEL-NEXT: s_cbranch_execz .LBB5_6
+; GFX1032GISEL-NEXT: ; %bb.4: ; %if
+; GFX1032GISEL-NEXT: s_mov_b32 s4, 0
+; GFX1032GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1032GISEL-NEXT: s_mov_b32 s7, exec_lo
+; GFX1032GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
+; GFX1032GISEL-NEXT: s_ff1_i32_b32 s10, s7
+; GFX1032GISEL-NEXT: v_readlane_b32 s8, v4, s10
+; GFX1032GISEL-NEXT: v_readlane_b32 s9, v5, s10
+; GFX1032GISEL-NEXT: s_bitset0_b32 s7, s10
+; GFX1032GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1032GISEL-NEXT: v_min_f64 v[2:3], s[8:9], s[4:5]
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX1032GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB5_5
+; GFX1032GISEL-NEXT: .LBB5_6: ; %endif
+; GFX1032GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s6
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX1032GISEL-NEXT: v_mov_b32_e32 v3, s5
+; GFX1032GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GFX1032GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1164DAGISEL-LABEL: divergent_cfg_double:
+; GFX1164DAGISEL: ; %bb.0: ; %entry
+; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1164DAGISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc, 15, v6
+; GFX1164DAGISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1164DAGISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX1164DAGISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
+; GFX1164DAGISEL-NEXT: s_cbranch_execz .LBB5_4
+; GFX1164DAGISEL-NEXT: ; %bb.1: ; %else
+; GFX1164DAGISEL-NEXT: s_mov_b32 s4, 0
+; GFX1164DAGISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec
+; GFX1164DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s8, s[2:3]
+; GFX1164DAGISEL-NEXT: v_readlane_b32 s6, v2, s8
+; GFX1164DAGISEL-NEXT: v_readlane_b32 s7, v3, s8
+; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[2:3], s8
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX1164DAGISEL-NEXT: v_min_f64 v[4:5], s[6:7], s[4:5]
+; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX1164DAGISEL-NEXT: ; %bb.3:
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v7, s5
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v6, s4
+; GFX1164DAGISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1164DAGISEL-NEXT: ; implicit-def: $vgpr5
+; GFX1164DAGISEL-NEXT: .LBB5_4: ; %Flow
+; GFX1164DAGISEL-NEXT: s_and_not1_saveexec_b64 s[0:1], s[0:1]
+; GFX1164DAGISEL-NEXT: s_cbranch_execz .LBB5_8
+; GFX1164DAGISEL-NEXT: ; %bb.5: ; %if
+; GFX1164DAGISEL-NEXT: s_mov_b32 s4, 0
+; GFX1164DAGISEL-NEXT: s_mov_b32 s5, 0x7ff80000
+; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec
+; GFX1164DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s8, s[2:3]
+; GFX1164DAGISEL-NEXT: v_readlane_b32 s6, v4, s8
+; GFX1164DAGISEL-NEXT: v_readlane_b32 s7, v5, s8
+; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[2:3], s8
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX1164DAGISEL-NEXT: v_min_f64 v[2:3], s[6:7], s[4:5]
+; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX1164DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
+; GFX1164DAGISEL-NEXT: ; %bb.7:
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v7, s5
+; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v6, s4
+; GFX1164DAGISEL-NEXT: .LBB5_8: ; %endif
+; GFX1164DAGISEL-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1164DAGISEL-NEXT: global_store_b64 v[0:1], v[6:7], off
+; GFX1164DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1164GISEL-LABEL: divergent_cfg_double:
+; GFX1164GISEL: ; %bb.0: ; %entry
+; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1164GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
+; GFX1164GISEL-NEXT: ; implicit-def: $sgpr0_sgpr1
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1164GISEL-NEXT: v_cmpx_le_u32_e32 16, v6
+; GFX1164GISEL-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB5_3
+; GFX1164GISEL-NEXT: ; %bb.1: ; %else
+; GFX1164GISEL-NEXT: s_mov_b32 s0, 0
+; GFX1164GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX1164GISEL-NEXT: s_mov_b64 s[4:5], exec
+; GFX1164GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: s_ctz_i32_b64 s8, s[4:5]
+; GFX1164GISEL-NEXT: v_readlane_b32 s6, v2, s8
+; GFX1164GISEL-NEXT: v_readlane_b32 s7, v3, s8
+; GFX1164GISEL-NEXT: s_bitset0_b64 s[4:5], s8
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX1164GISEL-NEXT: v_min_f64 v[4:5], s[6:7], s[0:1]
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1164GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1164GISEL-NEXT: ; implicit-def: $vgpr5
+; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX1164GISEL-NEXT: .LBB5_3: ; %Flow
+; GFX1164GISEL-NEXT: s_and_not1_saveexec_b64 s[2:3], s[2:3]
+; GFX1164GISEL-NEXT: s_cbranch_execz .LBB5_6
+; GFX1164GISEL-NEXT: ; %bb.4: ; %if
+; GFX1164GISEL-NEXT: s_mov_b32 s0, 0
+; GFX1164GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX1164GISEL-NEXT: s_mov_b64 s[4:5], exec
+; GFX1164GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: s_ctz_i32_b64 s8, s[4:5]
+; GFX1164GISEL-NEXT: v_readlane_b32 s6, v4, s8
+; GFX1164GISEL-NEXT: v_readlane_b32 s7, v5, s8
+; GFX1164GISEL-NEXT: s_bitset0_b64 s[4:5], s8
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX1164GISEL-NEXT: v_min_f64 v[2:3], s[6:7], s[0:1]
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1164GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1164GISEL-NEXT: s_cbranch_scc1 .LBB5_5
+; GFX1164GISEL-NEXT: .LBB5_6: ; %endif
+; GFX1164GISEL-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v3, s1
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX1164GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1164GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1132DAGISEL-LABEL: divergent_cfg_double:
+; GFX1132DAGISEL: ; %bb.0: ; %entry
+; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1132DAGISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc_lo, 15, v6
+; GFX1132DAGISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1132DAGISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX1132DAGISEL-NEXT: s_xor_b32 s2, exec_lo, s0
+; GFX1132DAGISEL-NEXT: s_cbranch_execz .LBB5_4
+; GFX1132DAGISEL-NEXT: ; %bb.1: ; %else
+; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0
+; GFX1132DAGISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX1132DAGISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX1132DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX1132DAGISEL-NEXT: v_readlane_b32 s4, v2, s6
+; GFX1132DAGISEL-NEXT: v_readlane_b32 s5, v3, s6
+; GFX1132DAGISEL-NEXT: s_bitset0_b32 s3, s6
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1132DAGISEL-NEXT: v_min_f64 v[4:5], s[4:5], s[0:1]
+; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX1132DAGISEL-NEXT: ; %bb.3:
+; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
+; GFX1132DAGISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1132DAGISEL-NEXT: ; implicit-def: $vgpr5
+; GFX1132DAGISEL-NEXT: .LBB5_4: ; %Flow
+; GFX1132DAGISEL-NEXT: s_and_not1_saveexec_b32 s2, s2
+; GFX1132DAGISEL-NEXT: s_cbranch_execz .LBB5_8
+; GFX1132DAGISEL-NEXT: ; %bb.5: ; %if
+; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0
+; GFX1132DAGISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX1132DAGISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX1132DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX1132DAGISEL-NEXT: v_readlane_b32 s4, v4, s6
+; GFX1132DAGISEL-NEXT: v_readlane_b32 s5, v5, s6
+; GFX1132DAGISEL-NEXT: s_bitset0_b32 s3, s6
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1132DAGISEL-NEXT: v_min_f64 v[2:3], s[4:5], s[0:1]
+; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1132DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
+; GFX1132DAGISEL-NEXT: ; %bb.7:
+; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
+; GFX1132DAGISEL-NEXT: .LBB5_8: ; %endif
+; GFX1132DAGISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX1132DAGISEL-NEXT: global_store_b64 v[0:1], v[6:7], off
+; GFX1132DAGISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1132GISEL-LABEL: divergent_cfg_double:
+; GFX1132GISEL: ; %bb.0: ; %entry
+; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1132GISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
+; GFX1132GISEL-NEXT: ; implicit-def: $sgpr0_sgpr1
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1132GISEL-NEXT: v_cmpx_le_u32_e32 16, v6
+; GFX1132GISEL-NEXT: s_xor_b32 s2, exec_lo, s2
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB5_3
+; GFX1132GISEL-NEXT: ; %bb.1: ; %else
+; GFX1132GISEL-NEXT: s_mov_b32 s0, 0
+; GFX1132GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX1132GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX1132GISEL-NEXT: v_readlane_b32 s4, v2, s6
+; GFX1132GISEL-NEXT: v_readlane_b32 s5, v3, s6
+; GFX1132GISEL-NEXT: s_bitset0_b32 s3, s6
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1132GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1132GISEL-NEXT: v_min_f64 v[4:5], s[4:5], s[0:1]
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1132GISEL-NEXT: ; implicit-def: $vgpr4
+; GFX1132GISEL-NEXT: ; implicit-def: $vgpr5
+; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX1132GISEL-NEXT: .LBB5_3: ; %Flow
+; GFX1132GISEL-NEXT: s_and_not1_saveexec_b32 s2, s2
+; GFX1132GISEL-NEXT: s_cbranch_execz .LBB5_6
+; GFX1132GISEL-NEXT: ; %bb.4: ; %if
+; GFX1132GISEL-NEXT: s_mov_b32 s0, 0
+; GFX1132GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX1132GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX1132GISEL-NEXT: v_readlane_b32 s4, v4, s6
+; GFX1132GISEL-NEXT: v_readlane_b32 s5, v5, s6
+; GFX1132GISEL-NEXT: s_bitset0_b32 s3, s6
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1132GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1132GISEL-NEXT: v_min_f64 v[2:3], s[4:5], s[0:1]
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1132GISEL-NEXT: s_cbranch_scc1 .LBB5_5
+; GFX1132GISEL-NEXT: .LBB5_6: ; %endif
+; GFX1132GISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX1132GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX1132GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1132GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12DAGISEL-LABEL: divergent_cfg_double:
+; GFX12DAGISEL: ; %bb.0: ; %entry
+; GFX12DAGISEL-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_expcnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_samplecnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_bvhcnt 0x0
+; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0
+; GFX12DAGISEL-NEXT: v_and_b32_e32 v6, 0x3ff, v31
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12DAGISEL-NEXT: v_cmp_lt_u32_e32 vcc_lo, 15, v6
+; GFX12DAGISEL-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX12DAGISEL-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_xor_b32 s2, exec_lo, s0
+; GFX12DAGISEL-NEXT: s_cbranch_execz .LBB5_4
+; GFX12DAGISEL-NEXT: ; %bb.1: ; %else
+; GFX12DAGISEL-NEXT: s_mov_b32 s0, 0
+; GFX12DAGISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX12DAGISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX12DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: v_readlane_b32 s4, v2, s6
+; GFX12DAGISEL-NEXT: v_readlane_b32 s5, v3, s6
+; GFX12DAGISEL-NEXT: s_bitset0_b32 s3, s6
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX12DAGISEL-NEXT: v_min_num_f64_e64 v[4:5], s[4:5], s[0:1]
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s1, v5
+; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
+; GFX12DAGISEL-NEXT: ; %bb.3:
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12DAGISEL-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
+; GFX12DAGISEL-NEXT: ; implicit-def: $vgpr4
+; GFX12DAGISEL-NEXT: ; implicit-def: $vgpr5
+; GFX12DAGISEL-NEXT: .LBB5_4: ; %Flow
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_and_not1_saveexec_b32 s2, s2
+; GFX12DAGISEL-NEXT: s_cbranch_execz .LBB5_8
+; GFX12DAGISEL-NEXT: ; %bb.5: ; %if
+; GFX12DAGISEL-NEXT: s_mov_b32 s0, 0
+; GFX12DAGISEL-NEXT: s_mov_b32 s1, 0x7ff80000
+; GFX12DAGISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX12DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: v_readlane_b32 s4, v4, s6
+; GFX12DAGISEL-NEXT: v_readlane_b32 s5, v5, s6
+; GFX12DAGISEL-NEXT: s_bitset0_b32 s3, s6
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX12DAGISEL-NEXT: v_min_num_f64_e64 v[2:3], s[4:5], s[0:1]
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
+; GFX12DAGISEL-NEXT: ; %bb.7:
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12DAGISEL-NEXT: v_dual_mov_b32 v7, s1 :: v_dual_mov_b32 v6, s0
+; GFX12DAGISEL-NEXT: .LBB5_8: ; %endif
+; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12DAGISEL-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX12DAGISEL-NEXT: global_store_b64 v[0:1], v[6:7], off
+; GFX12DAGISEL-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %d_cmp = icmp ult i32 %tid, 16
+ br i1 %d_cmp, label %if, label %else
+
+if:
+ %reducedValTid = call double @llvm.amdgcn.wave.reduce.fmin(double %in2, i32 1)
+ br label %endif
+
+else:
+ %reducedValIn = call double @llvm.amdgcn.wave.reduce.fmin(double %in, i32 1)
+ br label %endif
+
+endif:
+ %combine = phi double [%reducedValTid, %if], [%reducedValIn, %else]
+ store double %combine, ptr addrspace(1) %out
+ ret void
+}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX11DAGISEL: {{.*}}
; GFX11GISEL: {{.*}}
>From d8c48bd0a1039384297b56755b17e8cb0466943a Mon Sep 17 00:00:00 2001
From: Aaditya <Aaditya.AlokDeshpande at amd.com>
Date: Wed, 7 Jan 2026 11:50:16 +0530
Subject: [PATCH 2/4] Canonicalize NAN values.
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 30 +-
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll | 341 ++++++++++--------
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll | 341 ++++++++++--------
3 files changed, 425 insertions(+), 287 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 80978c6a00a9c..2db170424f18b 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5960,6 +5960,11 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
}
case AMDGPU::V_MIN_F64_e64:
case AMDGPU::V_MAX_F64_e64: {
+ const SIMachineFunctionInfo *Info =
+ MI.getMF()->getInfo<SIMachineFunctionInfo>();
+ bool IsIEEEMode = Info->getMode().IEEE;
+ bool IsGFX12Plus = AMDGPU::isGFX12Plus(ST);
+ bool NeedsNANCanonicalization = IsIEEEMode || IsGFX12Plus;
const TargetRegisterClass *VregRC = TRI->getVGPR64Class();
const TargetRegisterClass *VregSubRC =
TRI->getSubRegisterClass(VregRC, AMDGPU::sub0);
@@ -5972,7 +5977,9 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::V_MOV_B64_PSEUDO),
AccumulatorVReg)
.addReg(Accumulator->getOperand(0).getReg());
- if (ST.getGeneration() == AMDGPUSubtarget::Generation::GFX12) {
+ Register LaneValueReg = LaneValue->getOperand(0).getReg();
+ Register AccumulatorReg = AccumulatorVReg;
+ if (IsGFX12Plus) {
switch (Opc) {
case AMDGPU::V_MIN_F64_e64:
Opc = AMDGPU::V_MIN_NUM_F64_e64;
@@ -5982,11 +5989,28 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
break;
}
}
+ if (NeedsNANCanonicalization) {
+ unsigned MaxOpc =
+ IsGFX12Plus ? AMDGPU::V_MAX_NUM_F64_e64 : AMDGPU::V_MAX_F64_e64;
+ auto CanonicalizeForNaN = [&](Register Src) -> Register {
+ Register Dst = MRI.createVirtualRegister(VregRC);
+ BuildMI(*ComputeLoop, I, DL, TII->get(MaxOpc), Dst)
+ .addImm(0) // src0 modifiers
+ .addReg(Src)
+ .addImm(0) // src1 modifiers
+ .addReg(Src)
+ .addImm(0) // clamp
+ .addImm(0); // omod
+ return Dst;
+ };
+ LaneValueReg = CanonicalizeForNaN(LaneValueReg);
+ AccumulatorReg = CanonicalizeForNaN(AccumulatorReg);
+ }
auto DstVregInst = BuildMI(*ComputeLoop, I, DL, TII->get(Opc), DstVreg)
.addImm(0) // src0 modifiers
- .addReg(LaneValue->getOperand(0).getReg())
+ .addReg(LaneValueReg)
.addImm(0) // src1 modifiers
- .addReg(AccumulatorVReg)
+ .addReg(AccumulatorReg)
.addImm(0) // clamp
.addImm(0); // omod
auto ReadLaneLo =
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
index ca4091bcd3366..7da294179011c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
@@ -1145,14 +1145,14 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX8DAGISEL-NEXT: s_mov_b32 s7, 0x7ff80000
; GFX8DAGISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX8DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s6
-; GFX8DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v5, s7
-; GFX8DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
-; GFX8DAGISEL-NEXT: v_max_f64 v[4:5], s[8:9], v[4:5]
-; GFX8DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s8, s[4:5]
+; GFX8DAGISEL-NEXT: v_max_f64 v[4:5], s[6:7], s[6:7]
+; GFX8DAGISEL-NEXT: v_readlane_b32 s6, v2, s8
+; GFX8DAGISEL-NEXT: v_readlane_b32 s7, v3, s8
+; GFX8DAGISEL-NEXT: v_max_f64 v[6:7], s[6:7], s[6:7]
+; GFX8DAGISEL-NEXT: s_bitset0_b64 s[4:5], s8
; GFX8DAGISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX8DAGISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s6, v4
; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s7, v5
; GFX8DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
@@ -1170,14 +1170,14 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX8GISEL-NEXT: s_mov_b32 s7, 0x7ff80000
; GFX8GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX8GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GFX8GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s6
-; GFX8GISEL-NEXT: v_readlane_b32 s8, v2, s10
-; GFX8GISEL-NEXT: v_mov_b32_e32 v5, s7
-; GFX8GISEL-NEXT: v_readlane_b32 s9, v3, s10
-; GFX8GISEL-NEXT: v_max_f64 v[4:5], s[8:9], v[4:5]
-; GFX8GISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX8GISEL-NEXT: s_ff1_i32_b64 s8, s[4:5]
+; GFX8GISEL-NEXT: v_max_f64 v[4:5], s[6:7], s[6:7]
+; GFX8GISEL-NEXT: v_readlane_b32 s6, v2, s8
+; GFX8GISEL-NEXT: v_readlane_b32 s7, v3, s8
+; GFX8GISEL-NEXT: v_max_f64 v[6:7], s[6:7], s[6:7]
+; GFX8GISEL-NEXT: s_bitset0_b64 s[4:5], s8
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX8GISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX8GISEL-NEXT: v_readfirstlane_b32 s6, v4
; GFX8GISEL-NEXT: v_readfirstlane_b32 s7, v5
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB4_1
@@ -1195,14 +1195,14 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX9DAGISEL-NEXT: s_mov_b32 s7, 0x7ff80000
; GFX9DAGISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX9DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s6
-; GFX9DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v5, s7
-; GFX9DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
-; GFX9DAGISEL-NEXT: v_max_f64 v[4:5], s[8:9], v[4:5]
-; GFX9DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s8, s[4:5]
+; GFX9DAGISEL-NEXT: v_max_f64 v[4:5], s[6:7], s[6:7]
+; GFX9DAGISEL-NEXT: v_readlane_b32 s6, v2, s8
+; GFX9DAGISEL-NEXT: v_readlane_b32 s7, v3, s8
+; GFX9DAGISEL-NEXT: v_max_f64 v[6:7], s[6:7], s[6:7]
+; GFX9DAGISEL-NEXT: s_bitset0_b64 s[4:5], s8
; GFX9DAGISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX9DAGISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s6, v4
; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s7, v5
; GFX9DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
@@ -1220,14 +1220,14 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX9GISEL-NEXT: s_mov_b32 s7, 0x7ff80000
; GFX9GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX9GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GFX9GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s6
-; GFX9GISEL-NEXT: v_readlane_b32 s8, v2, s10
-; GFX9GISEL-NEXT: v_mov_b32_e32 v5, s7
-; GFX9GISEL-NEXT: v_readlane_b32 s9, v3, s10
-; GFX9GISEL-NEXT: v_max_f64 v[4:5], s[8:9], v[4:5]
-; GFX9GISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX9GISEL-NEXT: s_ff1_i32_b64 s8, s[4:5]
+; GFX9GISEL-NEXT: v_max_f64 v[4:5], s[6:7], s[6:7]
+; GFX9GISEL-NEXT: v_readlane_b32 s6, v2, s8
+; GFX9GISEL-NEXT: v_readlane_b32 s7, v3, s8
+; GFX9GISEL-NEXT: v_max_f64 v[6:7], s[6:7], s[6:7]
+; GFX9GISEL-NEXT: s_bitset0_b64 s[4:5], s8
; GFX9GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX9GISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX9GISEL-NEXT: v_readfirstlane_b32 s6, v4
; GFX9GISEL-NEXT: v_readfirstlane_b32 s7, v5
; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB4_1
@@ -1246,11 +1246,13 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX1064DAGISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX1064DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
+; GFX1064DAGISEL-NEXT: v_max_f64 v[4:5], s[6:7], s[6:7]
; GFX1064DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX1064DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
; GFX1064DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
; GFX1064DAGISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
-; GFX1064DAGISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[6:7]
+; GFX1064DAGISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX1064DAGISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s6, v4
; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s7, v5
; GFX1064DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
@@ -1268,11 +1270,13 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX1064GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX1064GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
; GFX1064GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
+; GFX1064GISEL-NEXT: v_max_f64 v[4:5], s[6:7], s[6:7]
; GFX1064GISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX1064GISEL-NEXT: v_readlane_b32 s9, v3, s10
; GFX1064GISEL-NEXT: s_bitset0_b64 s[4:5], s10
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
-; GFX1064GISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[6:7]
+; GFX1064GISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX1064GISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX1064GISEL-NEXT: v_readfirstlane_b32 s6, v4
; GFX1064GISEL-NEXT: v_readfirstlane_b32 s7, v5
; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB4_1
@@ -1290,11 +1294,13 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX1032DAGISEL-NEXT: s_mov_b32 s6, exec_lo
; GFX1032DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s7, s6
+; GFX1032DAGISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[4:5]
; GFX1032DAGISEL-NEXT: v_readlane_b32 s8, v2, s7
; GFX1032DAGISEL-NEXT: v_readlane_b32 s9, v3, s7
; GFX1032DAGISEL-NEXT: s_bitset0_b32 s6, s7
; GFX1032DAGISEL-NEXT: s_cmp_lg_u32 s6, 0
-; GFX1032DAGISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[4:5]
+; GFX1032DAGISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX1032DAGISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s5, v5
; GFX1032DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
@@ -1312,11 +1318,13 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX1032GISEL-NEXT: s_mov_b32 s6, exec_lo
; GFX1032GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
; GFX1032GISEL-NEXT: s_ff1_i32_b32 s7, s6
+; GFX1032GISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[4:5]
; GFX1032GISEL-NEXT: v_readlane_b32 s8, v2, s7
; GFX1032GISEL-NEXT: v_readlane_b32 s9, v3, s7
; GFX1032GISEL-NEXT: s_bitset0_b32 s6, s7
; GFX1032GISEL-NEXT: s_cmp_lg_u32 s6, 0
-; GFX1032GISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[4:5]
+; GFX1032GISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX1032GISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s5, v5
; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB4_1
@@ -1333,14 +1341,16 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX1164DAGISEL-NEXT: s_mov_b32 s3, 0x7ff80000
; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec
; GFX1164DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s6, s[0:1]
+; GFX1164DAGISEL-NEXT: v_max_f64 v[4:5], s[2:3], s[2:3]
; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s6
; GFX1164DAGISEL-NEXT: v_readlane_b32 s5, v3, s6
; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s6
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1164DAGISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[2:3]
+; GFX1164DAGISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164DAGISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s2, v4
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s3, v5
@@ -1358,14 +1368,16 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX1164GISEL-NEXT: s_mov_b32 s3, 0x7ff80000
; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec
; GFX1164GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1164GISEL-NEXT: s_ctz_i32_b64 s6, s[0:1]
+; GFX1164GISEL-NEXT: v_max_f64 v[4:5], s[2:3], s[2:3]
; GFX1164GISEL-NEXT: v_readlane_b32 s4, v2, s6
; GFX1164GISEL-NEXT: v_readlane_b32 s5, v3, s6
; GFX1164GISEL-NEXT: s_bitset0_b64 s[0:1], s6
-; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1164GISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[2:3]
+; GFX1164GISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164GISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX1164GISEL-NEXT: v_readfirstlane_b32 s2, v4
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_readfirstlane_b32 s3, v5
@@ -1383,14 +1395,16 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX1132DAGISEL-NEXT: s_mov_b32 s1, 0x7ff80000
; GFX1132DAGISEL-NEXT: s_mov_b32 s2, exec_lo
; GFX1132DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s3, s2
+; GFX1132DAGISEL-NEXT: v_max_f64 v[4:5], s[0:1], s[0:1]
; GFX1132DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
; GFX1132DAGISEL-NEXT: v_readlane_b32 s5, v3, s3
; GFX1132DAGISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s2, 0
-; GFX1132DAGISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[0:1]
+; GFX1132DAGISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132DAGISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s0, v4
; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s1, v5
@@ -1407,14 +1421,16 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX1132GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
; GFX1132GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2
+; GFX1132GISEL-NEXT: v_max_f64 v[4:5], s[0:1], s[0:1]
; GFX1132GISEL-NEXT: v_readlane_b32 s4, v2, s3
; GFX1132GISEL-NEXT: v_readlane_b32 s5, v3, s3
; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0
-; GFX1132GISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[0:1]
+; GFX1132GISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132GISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v4
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v5
@@ -1437,15 +1453,18 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX12DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s3, s2
+; GFX12DAGISEL-NEXT: v_max_num_f64_e64 v[4:5], s[0:1], s[0:1]
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
; GFX12DAGISEL-NEXT: v_readlane_b32 s5, v3, s3
; GFX12DAGISEL-NEXT: s_bitset0_b32 s2, s3
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s2, 0
-; GFX12DAGISEL-NEXT: v_max_num_f64_e64 v[4:5], s[4:5], s[0:1]
-; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12DAGISEL-NEXT: v_max_num_f64_e64 v[6:7], s[4:5], s[4:5]
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12DAGISEL-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[4:5]
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s1, v5
; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
; GFX12DAGISEL-NEXT: ; %bb.2:
@@ -1474,14 +1493,14 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX8DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
-; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s8
-; GFX8DAGISEL-NEXT: v_readlane_b32 s10, v2, s12
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v5, s9
-; GFX8DAGISEL-NEXT: v_readlane_b32 s11, v3, s12
-; GFX8DAGISEL-NEXT: v_max_f64 v[4:5], s[10:11], v[4:5]
-; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s10, s[6:7]
+; GFX8DAGISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[8:9]
+; GFX8DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX8DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX8DAGISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s10
; GFX8DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX8DAGISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s8, v4
; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s9, v5
; GFX8DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
@@ -1498,14 +1517,14 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX8DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
-; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s8
-; GFX8DAGISEL-NEXT: v_readlane_b32 s10, v4, s12
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s9
-; GFX8DAGISEL-NEXT: v_readlane_b32 s11, v5, s12
-; GFX8DAGISEL-NEXT: v_max_f64 v[2:3], s[10:11], v[2:3]
-; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s10, s[6:7]
+; GFX8DAGISEL-NEXT: v_max_f64 v[2:3], s[8:9], s[8:9]
+; GFX8DAGISEL-NEXT: v_readlane_b32 s8, v4, s10
+; GFX8DAGISEL-NEXT: v_readlane_b32 s9, v5, s10
+; GFX8DAGISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s10
; GFX8DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX8DAGISEL-NEXT: v_max_f64 v[2:3], v[6:7], v[2:3]
; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s8, v2
; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s9, v3
; GFX8DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
@@ -1532,18 +1551,18 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX8GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
; GFX8GISEL-NEXT: s_mov_b64 s[8:9], exec
; GFX8GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
-; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s4
-; GFX8GISEL-NEXT: v_readlane_b32 s10, v2, s12
-; GFX8GISEL-NEXT: v_mov_b32_e32 v5, s5
-; GFX8GISEL-NEXT: v_readlane_b32 s11, v3, s12
-; GFX8GISEL-NEXT: v_max_f64 v[4:5], s[10:11], v[4:5]
-; GFX8GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX8GISEL-NEXT: s_ff1_i32_b64 s10, s[8:9]
+; GFX8GISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[4:5]
+; GFX8GISEL-NEXT: v_readlane_b32 s4, v2, s10
+; GFX8GISEL-NEXT: v_readlane_b32 s5, v3, s10
+; GFX8GISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX8GISEL-NEXT: s_bitset0_b64 s[8:9], s10
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s4, v4
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX8GISEL-NEXT: v_max_f64 v[6:7], v[6:7], v[4:5]
; GFX8GISEL-NEXT: ; implicit-def: $vgpr4
; GFX8GISEL-NEXT: ; implicit-def: $vgpr5
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s5, v7
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB5_2
; GFX8GISEL-NEXT: .LBB5_3: ; %Flow
; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
@@ -1553,14 +1572,14 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX8GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
; GFX8GISEL-NEXT: s_mov_b64 s[8:9], exec
; GFX8GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
-; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
-; GFX8GISEL-NEXT: v_readlane_b32 s10, v4, s12
-; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s5
-; GFX8GISEL-NEXT: v_readlane_b32 s11, v5, s12
-; GFX8GISEL-NEXT: v_max_f64 v[2:3], s[10:11], v[2:3]
-; GFX8GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX8GISEL-NEXT: s_ff1_i32_b64 s10, s[8:9]
+; GFX8GISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[4:5]
+; GFX8GISEL-NEXT: v_readlane_b32 s4, v4, s10
+; GFX8GISEL-NEXT: v_readlane_b32 s5, v5, s10
+; GFX8GISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX8GISEL-NEXT: s_bitset0_b64 s[8:9], s10
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
+; GFX8GISEL-NEXT: v_max_f64 v[2:3], v[6:7], v[2:3]
; GFX8GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX8GISEL-NEXT: v_readfirstlane_b32 s5, v3
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB5_5
@@ -1586,14 +1605,14 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX9DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX9DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
-; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s8
-; GFX9DAGISEL-NEXT: v_readlane_b32 s10, v2, s12
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v5, s9
-; GFX9DAGISEL-NEXT: v_readlane_b32 s11, v3, s12
-; GFX9DAGISEL-NEXT: v_max_f64 v[4:5], s[10:11], v[4:5]
-; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s10, s[6:7]
+; GFX9DAGISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[8:9]
+; GFX9DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX9DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX9DAGISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s10
; GFX9DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX9DAGISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s8, v4
; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s9, v5
; GFX9DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
@@ -1610,14 +1629,14 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX9DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX9DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
-; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v2, s8
-; GFX9DAGISEL-NEXT: v_readlane_b32 s10, v4, s12
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v3, s9
-; GFX9DAGISEL-NEXT: v_readlane_b32 s11, v5, s12
-; GFX9DAGISEL-NEXT: v_max_f64 v[2:3], s[10:11], v[2:3]
-; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s10, s[6:7]
+; GFX9DAGISEL-NEXT: v_max_f64 v[2:3], s[8:9], s[8:9]
+; GFX9DAGISEL-NEXT: v_readlane_b32 s8, v4, s10
+; GFX9DAGISEL-NEXT: v_readlane_b32 s9, v5, s10
+; GFX9DAGISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s10
; GFX9DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX9DAGISEL-NEXT: v_max_f64 v[2:3], v[6:7], v[2:3]
; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s8, v2
; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s9, v3
; GFX9DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
@@ -1644,18 +1663,18 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX9GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
; GFX9GISEL-NEXT: s_mov_b64 s[8:9], exec
; GFX9GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
-; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s4
-; GFX9GISEL-NEXT: v_readlane_b32 s10, v2, s12
-; GFX9GISEL-NEXT: v_mov_b32_e32 v5, s5
-; GFX9GISEL-NEXT: v_readlane_b32 s11, v3, s12
-; GFX9GISEL-NEXT: v_max_f64 v[4:5], s[10:11], v[4:5]
-; GFX9GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX9GISEL-NEXT: s_ff1_i32_b64 s10, s[8:9]
+; GFX9GISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[4:5]
+; GFX9GISEL-NEXT: v_readlane_b32 s4, v2, s10
+; GFX9GISEL-NEXT: v_readlane_b32 s5, v3, s10
+; GFX9GISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX9GISEL-NEXT: s_bitset0_b64 s[8:9], s10
; GFX9GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s4, v4
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX9GISEL-NEXT: v_max_f64 v[6:7], v[6:7], v[4:5]
; GFX9GISEL-NEXT: ; implicit-def: $vgpr4
; GFX9GISEL-NEXT: ; implicit-def: $vgpr5
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s5, v7
; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB5_2
; GFX9GISEL-NEXT: .LBB5_3: ; %Flow
; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
@@ -1665,14 +1684,14 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX9GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
; GFX9GISEL-NEXT: s_mov_b64 s[8:9], exec
; GFX9GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
-; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s4
-; GFX9GISEL-NEXT: v_readlane_b32 s10, v4, s12
-; GFX9GISEL-NEXT: v_mov_b32_e32 v3, s5
-; GFX9GISEL-NEXT: v_readlane_b32 s11, v5, s12
-; GFX9GISEL-NEXT: v_max_f64 v[2:3], s[10:11], v[2:3]
-; GFX9GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX9GISEL-NEXT: s_ff1_i32_b64 s10, s[8:9]
+; GFX9GISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[4:5]
+; GFX9GISEL-NEXT: v_readlane_b32 s4, v4, s10
+; GFX9GISEL-NEXT: v_readlane_b32 s5, v5, s10
+; GFX9GISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX9GISEL-NEXT: s_bitset0_b64 s[8:9], s10
; GFX9GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
+; GFX9GISEL-NEXT: v_max_f64 v[2:3], v[6:7], v[2:3]
; GFX9GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX9GISEL-NEXT: v_readfirstlane_b32 s5, v3
; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB5_5
@@ -1699,11 +1718,13 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1064DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX1064DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX1064DAGISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[8:9]
; GFX1064DAGISEL-NEXT: v_readlane_b32 s10, v2, s12
; GFX1064DAGISEL-NEXT: v_readlane_b32 s11, v3, s12
; GFX1064DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
; GFX1064DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
-; GFX1064DAGISEL-NEXT: v_max_f64 v[4:5], s[10:11], s[8:9]
+; GFX1064DAGISEL-NEXT: v_max_f64 v[6:7], s[10:11], s[10:11]
+; GFX1064DAGISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s8, v4
; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s9, v5
; GFX1064DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
@@ -1721,11 +1742,13 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1064DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX1064DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX1064DAGISEL-NEXT: v_max_f64 v[2:3], s[8:9], s[8:9]
; GFX1064DAGISEL-NEXT: v_readlane_b32 s10, v4, s12
; GFX1064DAGISEL-NEXT: v_readlane_b32 s11, v5, s12
; GFX1064DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
; GFX1064DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
-; GFX1064DAGISEL-NEXT: v_max_f64 v[2:3], s[10:11], s[8:9]
+; GFX1064DAGISEL-NEXT: v_max_f64 v[6:7], s[10:11], s[10:11]
+; GFX1064DAGISEL-NEXT: v_max_f64 v[2:3], v[6:7], v[2:3]
; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s8, v2
; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s9, v3
; GFX1064DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
@@ -1752,11 +1775,13 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1064GISEL-NEXT: s_mov_b64 s[8:9], exec
; GFX1064GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
; GFX1064GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX1064GISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[4:5]
; GFX1064GISEL-NEXT: v_readlane_b32 s10, v2, s12
; GFX1064GISEL-NEXT: v_readlane_b32 s11, v3, s12
; GFX1064GISEL-NEXT: s_bitset0_b64 s[8:9], s12
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX1064GISEL-NEXT: v_max_f64 v[4:5], s[10:11], s[4:5]
+; GFX1064GISEL-NEXT: v_max_f64 v[6:7], s[10:11], s[10:11]
+; GFX1064GISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX1064GISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX1064GISEL-NEXT: v_readfirstlane_b32 s5, v5
; GFX1064GISEL-NEXT: ; implicit-def: $vgpr4
@@ -1771,11 +1796,13 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1064GISEL-NEXT: s_mov_b64 s[8:9], exec
; GFX1064GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
; GFX1064GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX1064GISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[4:5]
; GFX1064GISEL-NEXT: v_readlane_b32 s10, v4, s12
; GFX1064GISEL-NEXT: v_readlane_b32 s11, v5, s12
; GFX1064GISEL-NEXT: s_bitset0_b64 s[8:9], s12
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX1064GISEL-NEXT: v_max_f64 v[2:3], s[10:11], s[4:5]
+; GFX1064GISEL-NEXT: v_max_f64 v[6:7], s[10:11], s[10:11]
+; GFX1064GISEL-NEXT: v_max_f64 v[2:3], v[6:7], v[2:3]
; GFX1064GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX1064GISEL-NEXT: v_readfirstlane_b32 s5, v3
; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB5_5
@@ -1801,11 +1828,13 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1032DAGISEL-NEXT: s_mov_b32 s7, exec_lo
; GFX1032DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s10, s7
+; GFX1032DAGISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[4:5]
; GFX1032DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX1032DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
; GFX1032DAGISEL-NEXT: s_bitset0_b32 s7, s10
; GFX1032DAGISEL-NEXT: s_cmp_lg_u32 s7, 0
-; GFX1032DAGISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[4:5]
+; GFX1032DAGISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX1032DAGISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s5, v5
; GFX1032DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
@@ -1823,11 +1852,13 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1032DAGISEL-NEXT: s_mov_b32 s7, exec_lo
; GFX1032DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s10, s7
+; GFX1032DAGISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[4:5]
; GFX1032DAGISEL-NEXT: v_readlane_b32 s8, v4, s10
; GFX1032DAGISEL-NEXT: v_readlane_b32 s9, v5, s10
; GFX1032DAGISEL-NEXT: s_bitset0_b32 s7, s10
; GFX1032DAGISEL-NEXT: s_cmp_lg_u32 s7, 0
-; GFX1032DAGISEL-NEXT: v_max_f64 v[2:3], s[8:9], s[4:5]
+; GFX1032DAGISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX1032DAGISEL-NEXT: v_max_f64 v[2:3], v[6:7], v[2:3]
; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s5, v3
; GFX1032DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
@@ -1854,11 +1885,13 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1032GISEL-NEXT: s_mov_b32 s7, exec_lo
; GFX1032GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
; GFX1032GISEL-NEXT: s_ff1_i32_b32 s10, s7
+; GFX1032GISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[4:5]
; GFX1032GISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX1032GISEL-NEXT: v_readlane_b32 s9, v3, s10
; GFX1032GISEL-NEXT: s_bitset0_b32 s7, s10
; GFX1032GISEL-NEXT: s_cmp_lg_u32 s7, 0
-; GFX1032GISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[4:5]
+; GFX1032GISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX1032GISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s5, v5
; GFX1032GISEL-NEXT: ; implicit-def: $vgpr4
@@ -1873,11 +1906,13 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1032GISEL-NEXT: s_mov_b32 s7, exec_lo
; GFX1032GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
; GFX1032GISEL-NEXT: s_ff1_i32_b32 s10, s7
+; GFX1032GISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[4:5]
; GFX1032GISEL-NEXT: v_readlane_b32 s8, v4, s10
; GFX1032GISEL-NEXT: v_readlane_b32 s9, v5, s10
; GFX1032GISEL-NEXT: s_bitset0_b32 s7, s10
; GFX1032GISEL-NEXT: s_cmp_lg_u32 s7, 0
-; GFX1032GISEL-NEXT: v_max_f64 v[2:3], s[8:9], s[4:5]
+; GFX1032GISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX1032GISEL-NEXT: v_max_f64 v[2:3], v[6:7], v[2:3]
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s5, v3
; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB5_5
@@ -1903,14 +1938,16 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1164DAGISEL-NEXT: s_mov_b32 s5, 0x7ff80000
; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s8, s[2:3]
+; GFX1164DAGISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[4:5]
; GFX1164DAGISEL-NEXT: v_readlane_b32 s6, v2, s8
; GFX1164DAGISEL-NEXT: v_readlane_b32 s7, v3, s8
; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[2:3], s8
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
-; GFX1164DAGISEL-NEXT: v_max_f64 v[4:5], s[6:7], s[4:5]
+; GFX1164DAGISEL-NEXT: v_max_f64 v[6:7], s[6:7], s[6:7]
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164DAGISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s5, v5
@@ -1928,14 +1965,16 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1164DAGISEL-NEXT: s_mov_b32 s5, 0x7ff80000
; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s8, s[2:3]
+; GFX1164DAGISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[4:5]
; GFX1164DAGISEL-NEXT: v_readlane_b32 s6, v4, s8
; GFX1164DAGISEL-NEXT: v_readlane_b32 s7, v5, s8
; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[2:3], s8
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
-; GFX1164DAGISEL-NEXT: v_max_f64 v[2:3], s[6:7], s[4:5]
+; GFX1164DAGISEL-NEXT: v_max_f64 v[6:7], s[6:7], s[6:7]
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164DAGISEL-NEXT: v_max_f64 v[2:3], v[6:7], v[2:3]
; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s5, v3
@@ -1963,14 +2002,16 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1164GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
; GFX1164GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX1164GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
-; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1164GISEL-NEXT: s_ctz_i32_b64 s8, s[4:5]
+; GFX1164GISEL-NEXT: v_max_f64 v[4:5], s[0:1], s[0:1]
; GFX1164GISEL-NEXT: v_readlane_b32 s6, v2, s8
; GFX1164GISEL-NEXT: v_readlane_b32 s7, v3, s8
; GFX1164GISEL-NEXT: s_bitset0_b64 s[4:5], s8
-; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
-; GFX1164GISEL-NEXT: v_max_f64 v[4:5], s[6:7], s[0:1]
+; GFX1164GISEL-NEXT: v_max_f64 v[6:7], s[6:7], s[6:7]
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164GISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX1164GISEL-NEXT: v_readfirstlane_b32 s0, v4
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_readfirstlane_b32 s1, v5
@@ -1985,14 +2026,16 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1164GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
; GFX1164GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX1164GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
-; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1164GISEL-NEXT: s_ctz_i32_b64 s8, s[4:5]
+; GFX1164GISEL-NEXT: v_max_f64 v[2:3], s[0:1], s[0:1]
; GFX1164GISEL-NEXT: v_readlane_b32 s6, v4, s8
; GFX1164GISEL-NEXT: v_readlane_b32 s7, v5, s8
; GFX1164GISEL-NEXT: s_bitset0_b64 s[4:5], s8
-; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
-; GFX1164GISEL-NEXT: v_max_f64 v[2:3], s[6:7], s[0:1]
+; GFX1164GISEL-NEXT: v_max_f64 v[6:7], s[6:7], s[6:7]
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164GISEL-NEXT: v_max_f64 v[2:3], v[6:7], v[2:3]
; GFX1164GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_readfirstlane_b32 s1, v3
@@ -2019,14 +2062,16 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1132DAGISEL-NEXT: s_mov_b32 s1, 0x7ff80000
; GFX1132DAGISEL-NEXT: s_mov_b32 s3, exec_lo
; GFX1132DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
-; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX1132DAGISEL-NEXT: v_max_f64 v[4:5], s[0:1], s[0:1]
; GFX1132DAGISEL-NEXT: v_readlane_b32 s4, v2, s6
; GFX1132DAGISEL-NEXT: v_readlane_b32 s5, v3, s6
; GFX1132DAGISEL-NEXT: s_bitset0_b32 s3, s6
-; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s3, 0
-; GFX1132DAGISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[0:1]
+; GFX1132DAGISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132DAGISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s0, v4
; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s1, v5
@@ -2043,14 +2088,16 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1132DAGISEL-NEXT: s_mov_b32 s1, 0x7ff80000
; GFX1132DAGISEL-NEXT: s_mov_b32 s3, exec_lo
; GFX1132DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
-; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX1132DAGISEL-NEXT: v_max_f64 v[2:3], s[0:1], s[0:1]
; GFX1132DAGISEL-NEXT: v_readlane_b32 s4, v4, s6
; GFX1132DAGISEL-NEXT: v_readlane_b32 s5, v5, s6
; GFX1132DAGISEL-NEXT: s_bitset0_b32 s3, s6
-; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s3, 0
-; GFX1132DAGISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[0:1]
+; GFX1132DAGISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132DAGISEL-NEXT: v_max_f64 v[2:3], v[6:7], v[2:3]
; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s1, v3
@@ -2077,14 +2124,16 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1132GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
; GFX1132GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
-; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX1132GISEL-NEXT: v_max_f64 v[4:5], s[0:1], s[0:1]
; GFX1132GISEL-NEXT: v_readlane_b32 s4, v2, s6
; GFX1132GISEL-NEXT: v_readlane_b32 s5, v3, s6
; GFX1132GISEL-NEXT: s_bitset0_b32 s3, s6
-; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1132GISEL-NEXT: s_cmp_lg_u32 s3, 0
-; GFX1132GISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[0:1]
+; GFX1132GISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132GISEL-NEXT: v_max_f64 v[4:5], v[6:7], v[4:5]
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v4
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v5
@@ -2099,14 +2148,16 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1132GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
; GFX1132GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
-; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX1132GISEL-NEXT: v_max_f64 v[2:3], s[0:1], s[0:1]
; GFX1132GISEL-NEXT: v_readlane_b32 s4, v4, s6
; GFX1132GISEL-NEXT: v_readlane_b32 s5, v5, s6
; GFX1132GISEL-NEXT: s_bitset0_b32 s3, s6
-; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1132GISEL-NEXT: s_cmp_lg_u32 s3, 0
-; GFX1132GISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[0:1]
+; GFX1132GISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132GISEL-NEXT: v_max_f64 v[2:3], v[6:7], v[2:3]
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v3
@@ -2139,15 +2190,18 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX12DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX12DAGISEL-NEXT: v_max_num_f64_e64 v[4:5], s[0:1], s[0:1]
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: v_readlane_b32 s4, v2, s6
; GFX12DAGISEL-NEXT: v_readlane_b32 s5, v3, s6
; GFX12DAGISEL-NEXT: s_bitset0_b32 s3, s6
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s3, 0
-; GFX12DAGISEL-NEXT: v_max_num_f64_e64 v[4:5], s[4:5], s[0:1]
-; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12DAGISEL-NEXT: v_max_num_f64_e64 v[6:7], s[4:5], s[4:5]
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12DAGISEL-NEXT: v_max_num_f64_e32 v[4:5], v[6:7], v[4:5]
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s1, v5
; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
; GFX12DAGISEL-NEXT: ; %bb.3:
@@ -2166,15 +2220,18 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX12DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX12DAGISEL-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: v_readlane_b32 s4, v4, s6
; GFX12DAGISEL-NEXT: v_readlane_b32 s5, v5, s6
; GFX12DAGISEL-NEXT: s_bitset0_b32 s3, s6
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s3, 0
-; GFX12DAGISEL-NEXT: v_max_num_f64_e64 v[2:3], s[4:5], s[0:1]
-; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12DAGISEL-NEXT: v_max_num_f64_e64 v[6:7], s[4:5], s[4:5]
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12DAGISEL-NEXT: v_max_num_f64_e32 v[2:3], v[6:7], v[2:3]
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s1, v3
; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
; GFX12DAGISEL-NEXT: ; %bb.7:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
index 075b5ad6539cf..7d9f0c2e69ff0 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
@@ -1145,14 +1145,14 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX8DAGISEL-NEXT: s_mov_b32 s7, 0x7ff80000
; GFX8DAGISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX8DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s6
-; GFX8DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v5, s7
-; GFX8DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
-; GFX8DAGISEL-NEXT: v_min_f64 v[4:5], s[8:9], v[4:5]
-; GFX8DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s8, s[4:5]
+; GFX8DAGISEL-NEXT: v_max_f64 v[4:5], s[6:7], s[6:7]
+; GFX8DAGISEL-NEXT: v_readlane_b32 s6, v2, s8
+; GFX8DAGISEL-NEXT: v_readlane_b32 s7, v3, s8
+; GFX8DAGISEL-NEXT: v_max_f64 v[6:7], s[6:7], s[6:7]
+; GFX8DAGISEL-NEXT: s_bitset0_b64 s[4:5], s8
; GFX8DAGISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX8DAGISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s6, v4
; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s7, v5
; GFX8DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
@@ -1170,14 +1170,14 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX8GISEL-NEXT: s_mov_b32 s7, 0x7ff80000
; GFX8GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX8GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GFX8GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s6
-; GFX8GISEL-NEXT: v_readlane_b32 s8, v2, s10
-; GFX8GISEL-NEXT: v_mov_b32_e32 v5, s7
-; GFX8GISEL-NEXT: v_readlane_b32 s9, v3, s10
-; GFX8GISEL-NEXT: v_min_f64 v[4:5], s[8:9], v[4:5]
-; GFX8GISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX8GISEL-NEXT: s_ff1_i32_b64 s8, s[4:5]
+; GFX8GISEL-NEXT: v_max_f64 v[4:5], s[6:7], s[6:7]
+; GFX8GISEL-NEXT: v_readlane_b32 s6, v2, s8
+; GFX8GISEL-NEXT: v_readlane_b32 s7, v3, s8
+; GFX8GISEL-NEXT: v_max_f64 v[6:7], s[6:7], s[6:7]
+; GFX8GISEL-NEXT: s_bitset0_b64 s[4:5], s8
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX8GISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX8GISEL-NEXT: v_readfirstlane_b32 s6, v4
; GFX8GISEL-NEXT: v_readfirstlane_b32 s7, v5
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB4_1
@@ -1195,14 +1195,14 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX9DAGISEL-NEXT: s_mov_b32 s7, 0x7ff80000
; GFX9DAGISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX9DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s6
-; GFX9DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v5, s7
-; GFX9DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
-; GFX9DAGISEL-NEXT: v_min_f64 v[4:5], s[8:9], v[4:5]
-; GFX9DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s8, s[4:5]
+; GFX9DAGISEL-NEXT: v_max_f64 v[4:5], s[6:7], s[6:7]
+; GFX9DAGISEL-NEXT: v_readlane_b32 s6, v2, s8
+; GFX9DAGISEL-NEXT: v_readlane_b32 s7, v3, s8
+; GFX9DAGISEL-NEXT: v_max_f64 v[6:7], s[6:7], s[6:7]
+; GFX9DAGISEL-NEXT: s_bitset0_b64 s[4:5], s8
; GFX9DAGISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX9DAGISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s6, v4
; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s7, v5
; GFX9DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
@@ -1220,14 +1220,14 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX9GISEL-NEXT: s_mov_b32 s7, 0x7ff80000
; GFX9GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX9GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GFX9GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s6
-; GFX9GISEL-NEXT: v_readlane_b32 s8, v2, s10
-; GFX9GISEL-NEXT: v_mov_b32_e32 v5, s7
-; GFX9GISEL-NEXT: v_readlane_b32 s9, v3, s10
-; GFX9GISEL-NEXT: v_min_f64 v[4:5], s[8:9], v[4:5]
-; GFX9GISEL-NEXT: s_bitset0_b64 s[4:5], s10
+; GFX9GISEL-NEXT: s_ff1_i32_b64 s8, s[4:5]
+; GFX9GISEL-NEXT: v_max_f64 v[4:5], s[6:7], s[6:7]
+; GFX9GISEL-NEXT: v_readlane_b32 s6, v2, s8
+; GFX9GISEL-NEXT: v_readlane_b32 s7, v3, s8
+; GFX9GISEL-NEXT: v_max_f64 v[6:7], s[6:7], s[6:7]
+; GFX9GISEL-NEXT: s_bitset0_b64 s[4:5], s8
; GFX9GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX9GISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX9GISEL-NEXT: v_readfirstlane_b32 s6, v4
; GFX9GISEL-NEXT: v_readfirstlane_b32 s7, v5
; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB4_1
@@ -1246,11 +1246,13 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX1064DAGISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX1064DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
+; GFX1064DAGISEL-NEXT: v_max_f64 v[4:5], s[6:7], s[6:7]
; GFX1064DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX1064DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
; GFX1064DAGISEL-NEXT: s_bitset0_b64 s[4:5], s10
; GFX1064DAGISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
-; GFX1064DAGISEL-NEXT: v_min_f64 v[4:5], s[8:9], s[6:7]
+; GFX1064DAGISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX1064DAGISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s6, v4
; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s7, v5
; GFX1064DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
@@ -1268,11 +1270,13 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX1064GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX1064GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
; GFX1064GISEL-NEXT: s_ff1_i32_b64 s10, s[4:5]
+; GFX1064GISEL-NEXT: v_max_f64 v[4:5], s[6:7], s[6:7]
; GFX1064GISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX1064GISEL-NEXT: v_readlane_b32 s9, v3, s10
; GFX1064GISEL-NEXT: s_bitset0_b64 s[4:5], s10
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
-; GFX1064GISEL-NEXT: v_min_f64 v[4:5], s[8:9], s[6:7]
+; GFX1064GISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX1064GISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX1064GISEL-NEXT: v_readfirstlane_b32 s6, v4
; GFX1064GISEL-NEXT: v_readfirstlane_b32 s7, v5
; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB4_1
@@ -1290,11 +1294,13 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX1032DAGISEL-NEXT: s_mov_b32 s6, exec_lo
; GFX1032DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s7, s6
+; GFX1032DAGISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[4:5]
; GFX1032DAGISEL-NEXT: v_readlane_b32 s8, v2, s7
; GFX1032DAGISEL-NEXT: v_readlane_b32 s9, v3, s7
; GFX1032DAGISEL-NEXT: s_bitset0_b32 s6, s7
; GFX1032DAGISEL-NEXT: s_cmp_lg_u32 s6, 0
-; GFX1032DAGISEL-NEXT: v_min_f64 v[4:5], s[8:9], s[4:5]
+; GFX1032DAGISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX1032DAGISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s5, v5
; GFX1032DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
@@ -1312,11 +1318,13 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX1032GISEL-NEXT: s_mov_b32 s6, exec_lo
; GFX1032GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
; GFX1032GISEL-NEXT: s_ff1_i32_b32 s7, s6
+; GFX1032GISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[4:5]
; GFX1032GISEL-NEXT: v_readlane_b32 s8, v2, s7
; GFX1032GISEL-NEXT: v_readlane_b32 s9, v3, s7
; GFX1032GISEL-NEXT: s_bitset0_b32 s6, s7
; GFX1032GISEL-NEXT: s_cmp_lg_u32 s6, 0
-; GFX1032GISEL-NEXT: v_min_f64 v[4:5], s[8:9], s[4:5]
+; GFX1032GISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX1032GISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s5, v5
; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB4_1
@@ -1333,14 +1341,16 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX1164DAGISEL-NEXT: s_mov_b32 s3, 0x7ff80000
; GFX1164DAGISEL-NEXT: s_mov_b64 s[0:1], exec
; GFX1164DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s6, s[0:1]
+; GFX1164DAGISEL-NEXT: v_max_f64 v[4:5], s[2:3], s[2:3]
; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s6
; GFX1164DAGISEL-NEXT: v_readlane_b32 s5, v3, s6
; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[0:1], s6
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1164DAGISEL-NEXT: v_min_f64 v[4:5], s[4:5], s[2:3]
+; GFX1164DAGISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164DAGISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s2, v4
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s3, v5
@@ -1358,14 +1368,16 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX1164GISEL-NEXT: s_mov_b32 s3, 0x7ff80000
; GFX1164GISEL-NEXT: s_mov_b64 s[0:1], exec
; GFX1164GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1164GISEL-NEXT: s_ctz_i32_b64 s6, s[0:1]
+; GFX1164GISEL-NEXT: v_max_f64 v[4:5], s[2:3], s[2:3]
; GFX1164GISEL-NEXT: v_readlane_b32 s4, v2, s6
; GFX1164GISEL-NEXT: v_readlane_b32 s5, v3, s6
; GFX1164GISEL-NEXT: s_bitset0_b64 s[0:1], s6
-; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
-; GFX1164GISEL-NEXT: v_min_f64 v[4:5], s[4:5], s[2:3]
+; GFX1164GISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164GISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX1164GISEL-NEXT: v_readfirstlane_b32 s2, v4
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_readfirstlane_b32 s3, v5
@@ -1383,14 +1395,16 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX1132DAGISEL-NEXT: s_mov_b32 s1, 0x7ff80000
; GFX1132DAGISEL-NEXT: s_mov_b32 s2, exec_lo
; GFX1132DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s3, s2
+; GFX1132DAGISEL-NEXT: v_max_f64 v[4:5], s[0:1], s[0:1]
; GFX1132DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
; GFX1132DAGISEL-NEXT: v_readlane_b32 s5, v3, s3
; GFX1132DAGISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s2, 0
-; GFX1132DAGISEL-NEXT: v_min_f64 v[4:5], s[4:5], s[0:1]
+; GFX1132DAGISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132DAGISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s0, v4
; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s1, v5
@@ -1407,14 +1421,16 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX1132GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
; GFX1132GISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
-; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2
+; GFX1132GISEL-NEXT: v_max_f64 v[4:5], s[0:1], s[0:1]
; GFX1132GISEL-NEXT: v_readlane_b32 s4, v2, s3
; GFX1132GISEL-NEXT: v_readlane_b32 s5, v3, s3
; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3
-; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1132GISEL-NEXT: s_cmp_lg_u32 s2, 0
-; GFX1132GISEL-NEXT: v_min_f64 v[4:5], s[4:5], s[0:1]
+; GFX1132GISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132GISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v4
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v5
@@ -1437,15 +1453,18 @@ define void @divergent_value_double(ptr addrspace(1) %out, double %in) {
; GFX12DAGISEL-NEXT: .LBB4_1: ; =>This Inner Loop Header: Depth=1
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s3, s2
+; GFX12DAGISEL-NEXT: v_max_num_f64_e64 v[4:5], s[0:1], s[0:1]
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
; GFX12DAGISEL-NEXT: v_readlane_b32 s5, v3, s3
; GFX12DAGISEL-NEXT: s_bitset0_b32 s2, s3
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s2, 0
-; GFX12DAGISEL-NEXT: v_min_num_f64_e64 v[4:5], s[4:5], s[0:1]
-; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12DAGISEL-NEXT: v_max_num_f64_e64 v[6:7], s[4:5], s[4:5]
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12DAGISEL-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[4:5]
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s1, v5
; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB4_1
; GFX12DAGISEL-NEXT: ; %bb.2:
@@ -1474,14 +1493,14 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX8DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
-; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s8
-; GFX8DAGISEL-NEXT: v_readlane_b32 s10, v2, s12
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v5, s9
-; GFX8DAGISEL-NEXT: v_readlane_b32 s11, v3, s12
-; GFX8DAGISEL-NEXT: v_min_f64 v[4:5], s[10:11], v[4:5]
-; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s10, s[6:7]
+; GFX8DAGISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[8:9]
+; GFX8DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX8DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX8DAGISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s10
; GFX8DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX8DAGISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s8, v4
; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s9, v5
; GFX8DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
@@ -1498,14 +1517,14 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX8DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX8DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
-; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v2, s8
-; GFX8DAGISEL-NEXT: v_readlane_b32 s10, v4, s12
-; GFX8DAGISEL-NEXT: v_mov_b32_e32 v3, s9
-; GFX8DAGISEL-NEXT: v_readlane_b32 s11, v5, s12
-; GFX8DAGISEL-NEXT: v_min_f64 v[2:3], s[10:11], v[2:3]
-; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s10, s[6:7]
+; GFX8DAGISEL-NEXT: v_max_f64 v[2:3], s[8:9], s[8:9]
+; GFX8DAGISEL-NEXT: v_readlane_b32 s8, v4, s10
+; GFX8DAGISEL-NEXT: v_readlane_b32 s9, v5, s10
+; GFX8DAGISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX8DAGISEL-NEXT: s_bitset0_b64 s[6:7], s10
; GFX8DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX8DAGISEL-NEXT: v_min_f64 v[2:3], v[6:7], v[2:3]
; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s8, v2
; GFX8DAGISEL-NEXT: v_readfirstlane_b32 s9, v3
; GFX8DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
@@ -1532,18 +1551,18 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX8GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
; GFX8GISEL-NEXT: s_mov_b64 s[8:9], exec
; GFX8GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
-; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s4
-; GFX8GISEL-NEXT: v_readlane_b32 s10, v2, s12
-; GFX8GISEL-NEXT: v_mov_b32_e32 v5, s5
-; GFX8GISEL-NEXT: v_readlane_b32 s11, v3, s12
-; GFX8GISEL-NEXT: v_min_f64 v[4:5], s[10:11], v[4:5]
-; GFX8GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX8GISEL-NEXT: s_ff1_i32_b64 s10, s[8:9]
+; GFX8GISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[4:5]
+; GFX8GISEL-NEXT: v_readlane_b32 s4, v2, s10
+; GFX8GISEL-NEXT: v_readlane_b32 s5, v3, s10
+; GFX8GISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX8GISEL-NEXT: s_bitset0_b64 s[8:9], s10
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s4, v4
-; GFX8GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX8GISEL-NEXT: v_min_f64 v[6:7], v[6:7], v[4:5]
; GFX8GISEL-NEXT: ; implicit-def: $vgpr4
; GFX8GISEL-NEXT: ; implicit-def: $vgpr5
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX8GISEL-NEXT: v_readfirstlane_b32 s5, v7
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB5_2
; GFX8GISEL-NEXT: .LBB5_3: ; %Flow
; GFX8GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
@@ -1553,14 +1572,14 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX8GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
; GFX8GISEL-NEXT: s_mov_b64 s[8:9], exec
; GFX8GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
-; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
-; GFX8GISEL-NEXT: v_mov_b32_e32 v2, s4
-; GFX8GISEL-NEXT: v_readlane_b32 s10, v4, s12
-; GFX8GISEL-NEXT: v_mov_b32_e32 v3, s5
-; GFX8GISEL-NEXT: v_readlane_b32 s11, v5, s12
-; GFX8GISEL-NEXT: v_min_f64 v[2:3], s[10:11], v[2:3]
-; GFX8GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX8GISEL-NEXT: s_ff1_i32_b64 s10, s[8:9]
+; GFX8GISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[4:5]
+; GFX8GISEL-NEXT: v_readlane_b32 s4, v4, s10
+; GFX8GISEL-NEXT: v_readlane_b32 s5, v5, s10
+; GFX8GISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX8GISEL-NEXT: s_bitset0_b64 s[8:9], s10
; GFX8GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
+; GFX8GISEL-NEXT: v_min_f64 v[2:3], v[6:7], v[2:3]
; GFX8GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX8GISEL-NEXT: v_readfirstlane_b32 s5, v3
; GFX8GISEL-NEXT: s_cbranch_scc1 .LBB5_5
@@ -1586,14 +1605,14 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX9DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX9DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
-; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s8
-; GFX9DAGISEL-NEXT: v_readlane_b32 s10, v2, s12
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v5, s9
-; GFX9DAGISEL-NEXT: v_readlane_b32 s11, v3, s12
-; GFX9DAGISEL-NEXT: v_min_f64 v[4:5], s[10:11], v[4:5]
-; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s10, s[6:7]
+; GFX9DAGISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[8:9]
+; GFX9DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
+; GFX9DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
+; GFX9DAGISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s10
; GFX9DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX9DAGISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s8, v4
; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s9, v5
; GFX9DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
@@ -1610,14 +1629,14 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX9DAGISEL-NEXT: s_mov_b32 s9, 0x7ff80000
; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX9DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
-; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v2, s8
-; GFX9DAGISEL-NEXT: v_readlane_b32 s10, v4, s12
-; GFX9DAGISEL-NEXT: v_mov_b32_e32 v3, s9
-; GFX9DAGISEL-NEXT: v_readlane_b32 s11, v5, s12
-; GFX9DAGISEL-NEXT: v_min_f64 v[2:3], s[10:11], v[2:3]
-; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
+; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s10, s[6:7]
+; GFX9DAGISEL-NEXT: v_max_f64 v[2:3], s[8:9], s[8:9]
+; GFX9DAGISEL-NEXT: v_readlane_b32 s8, v4, s10
+; GFX9DAGISEL-NEXT: v_readlane_b32 s9, v5, s10
+; GFX9DAGISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX9DAGISEL-NEXT: s_bitset0_b64 s[6:7], s10
; GFX9DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX9DAGISEL-NEXT: v_min_f64 v[2:3], v[6:7], v[2:3]
; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s8, v2
; GFX9DAGISEL-NEXT: v_readfirstlane_b32 s9, v3
; GFX9DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
@@ -1644,18 +1663,18 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX9GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
; GFX9GISEL-NEXT: s_mov_b64 s[8:9], exec
; GFX9GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
-; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s4
-; GFX9GISEL-NEXT: v_readlane_b32 s10, v2, s12
-; GFX9GISEL-NEXT: v_mov_b32_e32 v5, s5
-; GFX9GISEL-NEXT: v_readlane_b32 s11, v3, s12
-; GFX9GISEL-NEXT: v_min_f64 v[4:5], s[10:11], v[4:5]
-; GFX9GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX9GISEL-NEXT: s_ff1_i32_b64 s10, s[8:9]
+; GFX9GISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[4:5]
+; GFX9GISEL-NEXT: v_readlane_b32 s4, v2, s10
+; GFX9GISEL-NEXT: v_readlane_b32 s5, v3, s10
+; GFX9GISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX9GISEL-NEXT: s_bitset0_b64 s[8:9], s10
; GFX9GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s4, v4
-; GFX9GISEL-NEXT: v_readfirstlane_b32 s5, v5
+; GFX9GISEL-NEXT: v_min_f64 v[6:7], v[6:7], v[4:5]
; GFX9GISEL-NEXT: ; implicit-def: $vgpr4
; GFX9GISEL-NEXT: ; implicit-def: $vgpr5
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX9GISEL-NEXT: v_readfirstlane_b32 s5, v7
; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB5_2
; GFX9GISEL-NEXT: .LBB5_3: ; %Flow
; GFX9GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[6:7]
@@ -1665,14 +1684,14 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX9GISEL-NEXT: s_mov_b32 s5, 0x7ff80000
; GFX9GISEL-NEXT: s_mov_b64 s[8:9], exec
; GFX9GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
-; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
-; GFX9GISEL-NEXT: v_mov_b32_e32 v2, s4
-; GFX9GISEL-NEXT: v_readlane_b32 s10, v4, s12
-; GFX9GISEL-NEXT: v_mov_b32_e32 v3, s5
-; GFX9GISEL-NEXT: v_readlane_b32 s11, v5, s12
-; GFX9GISEL-NEXT: v_min_f64 v[2:3], s[10:11], v[2:3]
-; GFX9GISEL-NEXT: s_bitset0_b64 s[8:9], s12
+; GFX9GISEL-NEXT: s_ff1_i32_b64 s10, s[8:9]
+; GFX9GISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[4:5]
+; GFX9GISEL-NEXT: v_readlane_b32 s4, v4, s10
+; GFX9GISEL-NEXT: v_readlane_b32 s5, v5, s10
+; GFX9GISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX9GISEL-NEXT: s_bitset0_b64 s[8:9], s10
; GFX9GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
+; GFX9GISEL-NEXT: v_min_f64 v[2:3], v[6:7], v[2:3]
; GFX9GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX9GISEL-NEXT: v_readfirstlane_b32 s5, v3
; GFX9GISEL-NEXT: s_cbranch_scc1 .LBB5_5
@@ -1699,11 +1718,13 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1064DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX1064DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX1064DAGISEL-NEXT: v_max_f64 v[4:5], s[8:9], s[8:9]
; GFX1064DAGISEL-NEXT: v_readlane_b32 s10, v2, s12
; GFX1064DAGISEL-NEXT: v_readlane_b32 s11, v3, s12
; GFX1064DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
; GFX1064DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
-; GFX1064DAGISEL-NEXT: v_min_f64 v[4:5], s[10:11], s[8:9]
+; GFX1064DAGISEL-NEXT: v_max_f64 v[6:7], s[10:11], s[10:11]
+; GFX1064DAGISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s8, v4
; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s9, v5
; GFX1064DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
@@ -1721,11 +1742,13 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1064DAGISEL-NEXT: s_mov_b64 s[6:7], exec
; GFX1064DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
+; GFX1064DAGISEL-NEXT: v_max_f64 v[2:3], s[8:9], s[8:9]
; GFX1064DAGISEL-NEXT: v_readlane_b32 s10, v4, s12
; GFX1064DAGISEL-NEXT: v_readlane_b32 s11, v5, s12
; GFX1064DAGISEL-NEXT: s_bitset0_b64 s[6:7], s12
; GFX1064DAGISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
-; GFX1064DAGISEL-NEXT: v_min_f64 v[2:3], s[10:11], s[8:9]
+; GFX1064DAGISEL-NEXT: v_max_f64 v[6:7], s[10:11], s[10:11]
+; GFX1064DAGISEL-NEXT: v_min_f64 v[2:3], v[6:7], v[2:3]
; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s8, v2
; GFX1064DAGISEL-NEXT: v_readfirstlane_b32 s9, v3
; GFX1064DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
@@ -1752,11 +1775,13 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1064GISEL-NEXT: s_mov_b64 s[8:9], exec
; GFX1064GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
; GFX1064GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX1064GISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[4:5]
; GFX1064GISEL-NEXT: v_readlane_b32 s10, v2, s12
; GFX1064GISEL-NEXT: v_readlane_b32 s11, v3, s12
; GFX1064GISEL-NEXT: s_bitset0_b64 s[8:9], s12
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX1064GISEL-NEXT: v_min_f64 v[4:5], s[10:11], s[4:5]
+; GFX1064GISEL-NEXT: v_max_f64 v[6:7], s[10:11], s[10:11]
+; GFX1064GISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX1064GISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX1064GISEL-NEXT: v_readfirstlane_b32 s5, v5
; GFX1064GISEL-NEXT: ; implicit-def: $vgpr4
@@ -1771,11 +1796,13 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1064GISEL-NEXT: s_mov_b64 s[8:9], exec
; GFX1064GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
; GFX1064GISEL-NEXT: s_ff1_i32_b64 s12, s[8:9]
+; GFX1064GISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[4:5]
; GFX1064GISEL-NEXT: v_readlane_b32 s10, v4, s12
; GFX1064GISEL-NEXT: v_readlane_b32 s11, v5, s12
; GFX1064GISEL-NEXT: s_bitset0_b64 s[8:9], s12
; GFX1064GISEL-NEXT: s_cmp_lg_u64 s[8:9], 0
-; GFX1064GISEL-NEXT: v_min_f64 v[2:3], s[10:11], s[4:5]
+; GFX1064GISEL-NEXT: v_max_f64 v[6:7], s[10:11], s[10:11]
+; GFX1064GISEL-NEXT: v_min_f64 v[2:3], v[6:7], v[2:3]
; GFX1064GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX1064GISEL-NEXT: v_readfirstlane_b32 s5, v3
; GFX1064GISEL-NEXT: s_cbranch_scc1 .LBB5_5
@@ -1801,11 +1828,13 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1032DAGISEL-NEXT: s_mov_b32 s7, exec_lo
; GFX1032DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s10, s7
+; GFX1032DAGISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[4:5]
; GFX1032DAGISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX1032DAGISEL-NEXT: v_readlane_b32 s9, v3, s10
; GFX1032DAGISEL-NEXT: s_bitset0_b32 s7, s10
; GFX1032DAGISEL-NEXT: s_cmp_lg_u32 s7, 0
-; GFX1032DAGISEL-NEXT: v_min_f64 v[4:5], s[8:9], s[4:5]
+; GFX1032DAGISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX1032DAGISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s5, v5
; GFX1032DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
@@ -1823,11 +1852,13 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1032DAGISEL-NEXT: s_mov_b32 s7, exec_lo
; GFX1032DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s10, s7
+; GFX1032DAGISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[4:5]
; GFX1032DAGISEL-NEXT: v_readlane_b32 s8, v4, s10
; GFX1032DAGISEL-NEXT: v_readlane_b32 s9, v5, s10
; GFX1032DAGISEL-NEXT: s_bitset0_b32 s7, s10
; GFX1032DAGISEL-NEXT: s_cmp_lg_u32 s7, 0
-; GFX1032DAGISEL-NEXT: v_min_f64 v[2:3], s[8:9], s[4:5]
+; GFX1032DAGISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX1032DAGISEL-NEXT: v_min_f64 v[2:3], v[6:7], v[2:3]
; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX1032DAGISEL-NEXT: v_readfirstlane_b32 s5, v3
; GFX1032DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
@@ -1854,11 +1885,13 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1032GISEL-NEXT: s_mov_b32 s7, exec_lo
; GFX1032GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
; GFX1032GISEL-NEXT: s_ff1_i32_b32 s10, s7
+; GFX1032GISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[4:5]
; GFX1032GISEL-NEXT: v_readlane_b32 s8, v2, s10
; GFX1032GISEL-NEXT: v_readlane_b32 s9, v3, s10
; GFX1032GISEL-NEXT: s_bitset0_b32 s7, s10
; GFX1032GISEL-NEXT: s_cmp_lg_u32 s7, 0
-; GFX1032GISEL-NEXT: v_min_f64 v[4:5], s[8:9], s[4:5]
+; GFX1032GISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX1032GISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s5, v5
; GFX1032GISEL-NEXT: ; implicit-def: $vgpr4
@@ -1873,11 +1906,13 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1032GISEL-NEXT: s_mov_b32 s7, exec_lo
; GFX1032GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
; GFX1032GISEL-NEXT: s_ff1_i32_b32 s10, s7
+; GFX1032GISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[4:5]
; GFX1032GISEL-NEXT: v_readlane_b32 s8, v4, s10
; GFX1032GISEL-NEXT: v_readlane_b32 s9, v5, s10
; GFX1032GISEL-NEXT: s_bitset0_b32 s7, s10
; GFX1032GISEL-NEXT: s_cmp_lg_u32 s7, 0
-; GFX1032GISEL-NEXT: v_min_f64 v[2:3], s[8:9], s[4:5]
+; GFX1032GISEL-NEXT: v_max_f64 v[6:7], s[8:9], s[8:9]
+; GFX1032GISEL-NEXT: v_min_f64 v[2:3], v[6:7], v[2:3]
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX1032GISEL-NEXT: v_readfirstlane_b32 s5, v3
; GFX1032GISEL-NEXT: s_cbranch_scc1 .LBB5_5
@@ -1903,14 +1938,16 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1164DAGISEL-NEXT: s_mov_b32 s5, 0x7ff80000
; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s8, s[2:3]
+; GFX1164DAGISEL-NEXT: v_max_f64 v[4:5], s[4:5], s[4:5]
; GFX1164DAGISEL-NEXT: v_readlane_b32 s6, v2, s8
; GFX1164DAGISEL-NEXT: v_readlane_b32 s7, v3, s8
; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[2:3], s8
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
-; GFX1164DAGISEL-NEXT: v_min_f64 v[4:5], s[6:7], s[4:5]
+; GFX1164DAGISEL-NEXT: v_max_f64 v[6:7], s[6:7], s[6:7]
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164DAGISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s4, v4
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s5, v5
@@ -1928,14 +1965,16 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1164DAGISEL-NEXT: s_mov_b32 s5, 0x7ff80000
; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec
; GFX1164DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s8, s[2:3]
+; GFX1164DAGISEL-NEXT: v_max_f64 v[2:3], s[4:5], s[4:5]
; GFX1164DAGISEL-NEXT: v_readlane_b32 s6, v4, s8
; GFX1164DAGISEL-NEXT: v_readlane_b32 s7, v5, s8
; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[2:3], s8
-; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1164DAGISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
-; GFX1164DAGISEL-NEXT: v_min_f64 v[2:3], s[6:7], s[4:5]
+; GFX1164DAGISEL-NEXT: v_max_f64 v[6:7], s[6:7], s[6:7]
+; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164DAGISEL-NEXT: v_min_f64 v[2:3], v[6:7], v[2:3]
; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s4, v2
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164DAGISEL-NEXT: v_readfirstlane_b32 s5, v3
@@ -1963,14 +2002,16 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1164GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
; GFX1164GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX1164GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
-; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1164GISEL-NEXT: s_ctz_i32_b64 s8, s[4:5]
+; GFX1164GISEL-NEXT: v_max_f64 v[4:5], s[0:1], s[0:1]
; GFX1164GISEL-NEXT: v_readlane_b32 s6, v2, s8
; GFX1164GISEL-NEXT: v_readlane_b32 s7, v3, s8
; GFX1164GISEL-NEXT: s_bitset0_b64 s[4:5], s8
-; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
-; GFX1164GISEL-NEXT: v_min_f64 v[4:5], s[6:7], s[0:1]
+; GFX1164GISEL-NEXT: v_max_f64 v[6:7], s[6:7], s[6:7]
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164GISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX1164GISEL-NEXT: v_readfirstlane_b32 s0, v4
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_readfirstlane_b32 s1, v5
@@ -1985,14 +2026,16 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1164GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
; GFX1164GISEL-NEXT: s_mov_b64 s[4:5], exec
; GFX1164GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
-; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1164GISEL-NEXT: s_ctz_i32_b64 s8, s[4:5]
+; GFX1164GISEL-NEXT: v_max_f64 v[2:3], s[0:1], s[0:1]
; GFX1164GISEL-NEXT: v_readlane_b32 s6, v4, s8
; GFX1164GISEL-NEXT: v_readlane_b32 s7, v5, s8
; GFX1164GISEL-NEXT: s_bitset0_b64 s[4:5], s8
-; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1164GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
-; GFX1164GISEL-NEXT: v_min_f64 v[2:3], s[6:7], s[0:1]
+; GFX1164GISEL-NEXT: v_max_f64 v[6:7], s[6:7], s[6:7]
+; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1164GISEL-NEXT: v_min_f64 v[2:3], v[6:7], v[2:3]
; GFX1164GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1164GISEL-NEXT: v_readfirstlane_b32 s1, v3
@@ -2019,14 +2062,16 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1132DAGISEL-NEXT: s_mov_b32 s1, 0x7ff80000
; GFX1132DAGISEL-NEXT: s_mov_b32 s3, exec_lo
; GFX1132DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
-; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX1132DAGISEL-NEXT: v_max_f64 v[4:5], s[0:1], s[0:1]
; GFX1132DAGISEL-NEXT: v_readlane_b32 s4, v2, s6
; GFX1132DAGISEL-NEXT: v_readlane_b32 s5, v3, s6
; GFX1132DAGISEL-NEXT: s_bitset0_b32 s3, s6
-; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s3, 0
-; GFX1132DAGISEL-NEXT: v_min_f64 v[4:5], s[4:5], s[0:1]
+; GFX1132DAGISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132DAGISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s0, v4
; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s1, v5
@@ -2043,14 +2088,16 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1132DAGISEL-NEXT: s_mov_b32 s1, 0x7ff80000
; GFX1132DAGISEL-NEXT: s_mov_b32 s3, exec_lo
; GFX1132DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
-; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX1132DAGISEL-NEXT: v_max_f64 v[2:3], s[0:1], s[0:1]
; GFX1132DAGISEL-NEXT: v_readlane_b32 s4, v4, s6
; GFX1132DAGISEL-NEXT: v_readlane_b32 s5, v5, s6
; GFX1132DAGISEL-NEXT: s_bitset0_b32 s3, s6
-; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1132DAGISEL-NEXT: s_cmp_lg_u32 s3, 0
-; GFX1132DAGISEL-NEXT: v_min_f64 v[2:3], s[4:5], s[0:1]
+; GFX1132DAGISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132DAGISEL-NEXT: v_min_f64 v[2:3], v[6:7], v[2:3]
; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132DAGISEL-NEXT: v_readfirstlane_b32 s1, v3
@@ -2077,14 +2124,16 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1132GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
; GFX1132GISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
-; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX1132GISEL-NEXT: v_max_f64 v[4:5], s[0:1], s[0:1]
; GFX1132GISEL-NEXT: v_readlane_b32 s4, v2, s6
; GFX1132GISEL-NEXT: v_readlane_b32 s5, v3, s6
; GFX1132GISEL-NEXT: s_bitset0_b32 s3, s6
-; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1132GISEL-NEXT: s_cmp_lg_u32 s3, 0
-; GFX1132GISEL-NEXT: v_min_f64 v[4:5], s[4:5], s[0:1]
+; GFX1132GISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132GISEL-NEXT: v_min_f64 v[4:5], v[6:7], v[4:5]
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v4
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v5
@@ -2099,14 +2148,16 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX1132GISEL-NEXT: s_mov_b32 s1, 0x7ff80000
; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
; GFX1132GISEL-NEXT: .LBB5_5: ; =>This Inner Loop Header: Depth=1
-; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX1132GISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX1132GISEL-NEXT: v_max_f64 v[2:3], s[0:1], s[0:1]
; GFX1132GISEL-NEXT: v_readlane_b32 s4, v4, s6
; GFX1132GISEL-NEXT: v_readlane_b32 s5, v5, s6
; GFX1132GISEL-NEXT: s_bitset0_b32 s3, s6
-; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1132GISEL-NEXT: s_cmp_lg_u32 s3, 0
-; GFX1132GISEL-NEXT: v_min_f64 v[2:3], s[4:5], s[0:1]
+; GFX1132GISEL-NEXT: v_max_f64 v[6:7], s[4:5], s[4:5]
+; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1132GISEL-NEXT: v_min_f64 v[2:3], v[6:7], v[2:3]
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s0, v2
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1132GISEL-NEXT: v_readfirstlane_b32 s1, v3
@@ -2139,15 +2190,18 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX12DAGISEL-NEXT: .LBB5_2: ; =>This Inner Loop Header: Depth=1
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX12DAGISEL-NEXT: v_max_num_f64_e64 v[4:5], s[0:1], s[0:1]
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: v_readlane_b32 s4, v2, s6
; GFX12DAGISEL-NEXT: v_readlane_b32 s5, v3, s6
; GFX12DAGISEL-NEXT: s_bitset0_b32 s3, s6
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s3, 0
-; GFX12DAGISEL-NEXT: v_min_num_f64_e64 v[4:5], s[4:5], s[0:1]
-; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12DAGISEL-NEXT: v_max_num_f64_e64 v[6:7], s[4:5], s[4:5]
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12DAGISEL-NEXT: v_min_num_f64_e32 v[4:5], v[6:7], v[4:5]
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s1, v5
; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB5_2
; GFX12DAGISEL-NEXT: ; %bb.3:
@@ -2166,15 +2220,18 @@ define void @divergent_cfg_double(ptr addrspace(1) %out, double %in, double %in2
; GFX12DAGISEL-NEXT: .LBB5_6: ; =>This Inner Loop Header: Depth=1
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_ctz_i32_b32 s6, s3
+; GFX12DAGISEL-NEXT: v_max_num_f64_e64 v[2:3], s[0:1], s[0:1]
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: v_readlane_b32 s4, v4, s6
; GFX12DAGISEL-NEXT: v_readlane_b32 s5, v5, s6
; GFX12DAGISEL-NEXT: s_bitset0_b32 s3, s6
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_cmp_lg_u32 s3, 0
-; GFX12DAGISEL-NEXT: v_min_num_f64_e64 v[2:3], s[4:5], s[0:1]
-; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12DAGISEL-NEXT: v_max_num_f64_e64 v[6:7], s[4:5], s[4:5]
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12DAGISEL-NEXT: v_min_num_f64_e32 v[2:3], v[6:7], v[2:3]
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s1, v3
; GFX12DAGISEL-NEXT: s_cbranch_scc1 .LBB5_6
; GFX12DAGISEL-NEXT: ; %bb.7:
>From 08cd8f3a228ca80cff056239bcc6e93caa377a7d Mon Sep 17 00:00:00 2001
From: Aaditya <Aaditya.AlokDeshpande at amd.com>
Date: Thu, 8 Jan 2026 16:15:36 +0530
Subject: [PATCH 3/4] Use `getRegClass`
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 5 ++++-
llvm/lib/Target/AMDGPU/SIInstructions.td | 2 +-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 2db170424f18b..26c7026c27119 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5965,7 +5965,10 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
bool IsIEEEMode = Info->getMode().IEEE;
bool IsGFX12Plus = AMDGPU::isGFX12Plus(ST);
bool NeedsNANCanonicalization = IsIEEEMode || IsGFX12Plus;
- const TargetRegisterClass *VregRC = TRI->getVGPR64Class();
+ int SrcIdx =
+ AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src);
+ const TargetRegisterClass *VregRC =
+ TRI->getAllocatableClass(TII->getRegClass(MI.getDesc(), SrcIdx));
const TargetRegisterClass *VregSubRC =
TRI->getSubRegisterClass(VregRC, AMDGPU::sub0);
Register AccumulatorVReg = MRI.createVirtualRegister(VregRC);
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 82a83e12649fb..b0a723272f42e 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -328,7 +328,7 @@ def : GCNPat<(i32 (int_amdgcn_set_inactive_chain_arg i32:$src, i32:$inactive)),
multiclass
AMDGPUWaveReducePseudoGenerator<string Op, string DataType, ValueType ty, RegisterClass RetReg, SrcRegOrImm9 Reg> {
- let usesCustomInserter = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in {
+ let usesCustomInserter = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0, UseNamedOperandTable = 1, Uses = [EXEC] in {
def !toupper(Op) #"_PSEUDO_" #DataType
: VPseudoInstSI<(outs RetReg : $sdst),
(ins Reg : $src, VSrc_b32 : $strategy),
>From 0c85470713a90649f2dae5b25122591815396247 Mon Sep 17 00:00:00 2001
From: Aaditya <Aaditya.AlokDeshpande at amd.com>
Date: Fri, 9 Jan 2026 12:13:58 +0530
Subject: [PATCH 4/4] Refactor
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 26c7026c27119..26438f655111d 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5562,6 +5562,10 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
const SIRegisterInfo *TRI = ST.getRegisterInfo();
const DebugLoc &DL = MI.getDebugLoc();
const SIInstrInfo *TII = ST.getInstrInfo();
+ const SIMachineFunctionInfo *Info =
+ MI.getMF()->getInfo<SIMachineFunctionInfo>();
+ bool IsIEEEMode = Info->getMode().IEEE;
+ bool IsGFX12Plus = AMDGPU::isGFX12Plus(ST);
// Reduction operations depend on whether the input operand is SGPR or VGPR.
Register SrcReg = MI.getOperand(1).getReg();
@@ -5960,10 +5964,6 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
}
case AMDGPU::V_MIN_F64_e64:
case AMDGPU::V_MAX_F64_e64: {
- const SIMachineFunctionInfo *Info =
- MI.getMF()->getInfo<SIMachineFunctionInfo>();
- bool IsIEEEMode = Info->getMode().IEEE;
- bool IsGFX12Plus = AMDGPU::isGFX12Plus(ST);
bool NeedsNANCanonicalization = IsIEEEMode || IsGFX12Plus;
int SrcIdx =
AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src);
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