[llvm] [TableGen][SIInsertWaitcnts] use RegIntervals for AMDGPU (PR #174888)

[Nicolai Hähnle via llvm-commits]

================
@@ -1929,6 +1929,115 @@ void CodeGenRegBank::computeRegUnitWeights() {
   }
 }
 
+// Enforce that all registers are intervals of regunits if the target
+// requests this property. This will renumber regunits to ensure the
+// interval property holds, or error out if it cannot be satisfied.
+void CodeGenRegBank::enforceRegUnitIntervals() {
+  std::vector<const Record *> Targets =
+      Records.getAllDerivedDefinitions("Target");
+
+  if (Targets.empty())
+    return;
+
+  const Record *Target = Targets[0];
+  if (!Target->getValueAsBit("RegistersAreIntervals"))
+    return;
+
+  LLVM_DEBUG(dbgs() << "Enforcing regunit intervals for target\n");
+  std::vector<unsigned> RegUnitRenumbering(RegUnits.size(), ~0u);
+
+  // RegUnits that have been renumbered from X -> Y. Y is what is marked so that
+  // it doesn't create a chain of swaps.
+  SparseBitVector DontRenumberUnits;
+
+  std::function<unsigned(unsigned)> GetRenumberedUnit =
+      [&](unsigned NewUnit) -> unsigned {
+    if (RegUnitRenumbering[NewUnit] == ~0u)
+      return NewUnit;
+    else
+      return RegUnitRenumbering[NewUnit];
+  };
+
+  std::function<void(unsigned, unsigned)> UpdateRenumbering =
+      [&](unsigned PrevUnit, unsigned NewUnit) {
+        RegUnitRenumbering[NewUnit] = PrevUnit;
+        RegUnitRenumbering[PrevUnit] = NewUnit;
+        DontRenumberUnits.set(NewUnit);
+      };
----------------
nhaehnle wrote:

Just inline this.

Also -- should it be a swap instead?

https://github.com/llvm/llvm-project/pull/174888