[llvm] [RISCV] AI Foundry ET extensions for RISC-V (PR #174571)
Abel Bernabeu via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 8 13:41:23 PST 2026
https://github.com/abel-bernabeu updated https://github.com/llvm/llvm-project/pull/174571
>From 50eea877d3fff57d3434b11b3034afeceabfa856 Mon Sep 17 00:00:00 2001
From: Abel Bernabeu <abel.bernabeu at gmail.com>
Date: Wed, 31 Dec 2025 23:20:26 +0000
Subject: [PATCH] [RISCV] AI Foundry ET extensions for RISC-V
This patch is part of an ongoing effort for upstreaming the AI Foundry ET
extensions for RISC-V, formerly known as the ET-SoC-1 Minion extensions by
Esperanto Technologies.
Changes
=======
The changes in this patch are:
- Defining the XAIFET feature as an "umbrella" extension under which
all the vendor extensions from ET-SoC-1 are included.
- Defining Esperanto Technologies's ET-SoC-1 Minion processor (et-soc1).
- Defining Ainekko's Erbium Minion processor (an-erbium), using the same
ISA.
- Adding the XAIFET vector register and mask register classes.
- Adding all the custsom machine instructions
Reference manual
================
Full documentation for these extensions is publicly available at the
following URL:
https://github.com/aifoundry-org/et-man/blob/main/ET%20Programmer's%20Reference%20Manual.pdf
Note on gather/scatter syntax
=============================
The assembly syntax for gather/scatter instructions used by Esperanto
Technologies used a complex source operand consisting on two registers.
For example, consider the syntax that the manual proposed for `fg32w.ps`:
fg32w.ps fd, fs1(rs1)
Note that the second operand (the source) is composed of two register
names.
While Esperanto Technologies fork of LLVM 11 supported this syntax,
it is easier to fit on the existing RISCV infrastructure if a comma is
inserted between the two source register names:
fg32w.ps fd, fs1, (rs1)
That way is as clear as the proposal from the manual and does not
require defining a complex operand consisting on two registers.
This subject was discussed on the #et-platform Discord channel, with
enough agreement on streamlining the syntax as proposed here for
llvm/clang.
Note on instruction prefixes
============================
The `aif.` prefix has been added to all the instructions under these
extensions, in line with the RISC-V toolchain practices, so an
instruction from the manual like `fadd.pi` becomes `aif.fadd.pi`
with the upstream toolchain.
The same goes for CSRs, so `fcc` becomes `aif.fcc`.
Authors
=======
This patch contains code rebased from the LLVM 11 fork by Esperanto
Technologies as published at the following URL:
https://github.com/aifoundry-org/llvm/tree/et
The list of authors that contributed to that fork follow:
- Abel Bernabeu <abel.bernabeu at esperantotech.com>, maintainer.
- David Callahan <callahan at reservoir.com>, project founder.
- Josep M. Perez <josep.m.perez at esperantotech.com>, contributor.
- Muhammad Kamran <muhammad.kamran at esperantotech.com>, contributor.
- Pere Munt <pere.munt at esperantotech.com>, contributor.
- Rafael Jimenez <rafael.jimenez at esperantotech.com>, contributor.
- Stefan Freudenberger <stefan at reservoir.com>, contributor.
---
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 9 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 25 +
.../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 3 +-
llvm/lib/Target/RISCV/RISCVFeatures.td | 6 +
.../lib/Target/RISCV/RISCVInstrFormatsXAIF.td | 263 ++++++
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 2 +
llvm/lib/Target/RISCV/RISCVInstrInfoXAIF.td | 789 ++++++++++++++++++
llvm/lib/Target/RISCV/RISCVProcessors.td | 16 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 54 ++
llvm/lib/Target/RISCV/RISCVSystemOperands.td | 58 ++
llvm/test/MC/RISCV/xaifet-amo-valid.s | 751 +++++++++++++++++
llvm/test/MC/RISCV/xaifet-simd-valid.s | 535 ++++++++++++
12 files changed, 2510 insertions(+), 1 deletion(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrFormatsXAIF.td
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXAIF.td
create mode 100644 llvm/test/MC/RISCV/xaifet-amo-valid.s
create mode 100644 llvm/test/MC/RISCV/xaifet-simd-valid.s
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 9bb3724c96c11..443c031cafd90 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1316,6 +1316,11 @@ static MCRegister convertVRToVRMx(const MCRegisterInfo &RI, MCRegister Reg,
&RISCVMCRegisterClasses[RegClassID]);
}
+static MCRegister convertFPR64ToFPR256(MCRegister Reg) {
+ assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register");
+ return Reg - RISCV::F0_D + RISCV::F0_PS;
+}
+
unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
unsigned Kind) {
RISCVOperand &Op = static_cast<RISCVOperand &>(AsmOp);
@@ -1329,6 +1334,10 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(Reg);
bool IsRegVR = RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg);
+ if (IsRegFPR64 && Kind == MCK_FPR256) {
+ Op.Reg.Reg = convertFPR64ToFPR256(Reg);
+ return Match_Success;
+ }
if (IsRegFPR64 && Kind == MCK_FPR128) {
Op.Reg.Reg = convertFPR64ToFPR128(Reg);
return Match_Success;
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 4bea4c48dddd1..478a1e5352cd3 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -194,6 +194,28 @@ static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, uint32_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeFPR256RegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo >= 32)
+ return MCDisassembler::Fail;
+
+ MCRegister Reg = RISCV::F0_PS + RegNo;
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeMRRegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo >= 8)
+ return MCDisassembler::Fail;
+
+ MCRegister Reg = RISCV::M0 + RegNo;
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeGPRX1RegisterClass(MCInst &Inst,
const MCDisassembler *Decoder) {
Inst.addOperand(MCOperand::createReg(RISCV::X1));
@@ -686,6 +708,8 @@ static constexpr FeatureBitset XAndesGroup = {
static constexpr FeatureBitset XSMTGroup = {RISCV::FeatureVendorXSMTVDot};
+static constexpr FeatureBitset XAIFGroup = {RISCV::FeatureVendorXAIFET};
+
static constexpr DecoderListEntry DecoderList32[]{
// Vendor Extensions
{DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
@@ -701,6 +725,7 @@ static constexpr DecoderListEntry DecoderList32[]{
{DecoderTableXMIPS32, XMIPSGroup, "Mips extensions"},
{DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
{DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},
+ {DecoderTableXAIF32, XAIFGroup, "AI Foundry extensions"},
// Standard Extensions
{DecoderTable32, {}, "standard 32-bit instructions"},
{DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"},
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index a047324ef36fa..8ae69e2d08d3f 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -414,6 +414,7 @@ enum OperandType : unsigned {
OPERAND_SIMM12_LSB00000,
OPERAND_SIMM16,
OPERAND_SIMM16_NONZERO,
+ OPERAND_SIMM20,
OPERAND_SIMM20_LI,
OPERAND_SIMM26,
OPERAND_CLUI_IMM,
@@ -639,7 +640,7 @@ struct SysReg {
namespace RISCVInsnOpcode {
struct RISCVOpcode {
- char Name[10];
+ char Name[15];
uint8_t Value;
};
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 66e1b18f37392..d8da44247b25f 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1730,6 +1730,12 @@ def HasVendorXSMTVDot
AssemblerPredicate<(all_of FeatureVendorXSMTVDot),
"'XSMTVDot' (SpacemiT Vector Dot Product Extension)">;
+def FeatureVendorXAIFET
+ : RISCVExtension<1, 0, "AI Foundry ET Extension", [FeatureStdExtF]>;
+def HasXAIFET : Predicate<"Subtarget->hasXAIFET()">,
+ AssemblerPredicate<(all_of FeatureVendorXAIFET),
+ "'XAIFET' (AI Foundry ET Extension)">;
+
//===----------------------------------------------------------------------===//
// LLVM specific features and extensions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsXAIF.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsXAIF.td
new file mode 100644
index 0000000000000..b21b28fd80046
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsXAIF.td
@@ -0,0 +1,263 @@
+//===-- RISCVInstrFormatXAIF.td ----------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Instruction formats for the AI Foundry ET extensions, formerly known as the
+// ET-SoC-1 Minion extensions by Esperanto Technologies.
+//
+// Full documentation for these extensions is publicly available at the
+// following URL:
+//
+// https://github.com/aifoundry-org/et-man/blob/main/ET%20Programmer's%20Reference%20Manual.pdf
+//
+//===----------------------------------------------------------------------===//
+
+def OPC_ET_MEM_PS : RISCVOpcode<"ET_MEM_PS", 0b0001011>;
+def OPC_ET_IMM_PS : RISCVOpcode<"ET_IMM_PS", 0b0011111>;
+def OPC_ET_IMM10_PI : RISCVOpcode<"ET_IMM1_PI", 0b0111111>;
+def OPC_ET_OP3_PS : RISCVOpcode<"ET_OP3_PS", 0b1011011>;
+def OPC_ET_IMM_PI : RISCVOpcode<"ET_IMM_PI", 0b1011111>;
+def OPC_ET_CVT_PS : RISCVOpcode<"ET_CVT_PS", 0b1110111>;
+def OPC_ET_OP_PS : RISCVOpcode<"ET_OP_PS", 0b1111011>; // OPC_CUSTOM_3
+
+// Example: AIF.FSWIZZ.PS
+class RVInstET1<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> rd;
+ bits<5> rs1;
+ bits<8> imm;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-20} = imm{7-3};
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = imm{2-0};
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FADDI.PS
+class RVInstET2<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<10> imm;
+ bits<5> rs1;
+ bits<5> rd;
+
+ let Inst{31-27} = imm{9-5};
+ let Inst{26-25} = 0b10;
+ let Inst{24-20} = imm{4-0};
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FADD.PS
+class RVInstET3<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> rd;
+ bits<5> rs1;
+ bits<5> rs2;
+ bits<3> rm;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = rm;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FMADD.PS
+class RVInstET4<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> rd;
+ bits<5> rs1;
+ bits<5> rs2;
+ bits<5> rs3;
+ bits<3> rm;
+
+ let Inst{31-27} = rs3;
+ let Inst{26-25} = funct2;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = rm;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FMVZ.X.PS
+class RVInstET5<bits<7> funct7,bits<3> funct3,
+ RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> rd;
+ bits<5> rs1;
+ bits<3> idx;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-23} = 0;
+ let Inst{22-20} = idx;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FSLLI.PS
+class RVInstET6<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> imm;
+ bits<5> rs1;
+ bits<5> rd;
+
+ let Inst{31-25} = 0b0100111;
+ let Inst{24-20} = imm;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FROUND.P
+class RVInstET7<RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> rs1;
+ bits<3> rm;
+ bits<5> rd;
+
+ let Inst{31-20} = 0b010110000001;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = rm;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.MOV.M.X
+class RVInstET8<RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<8> imm;
+ bits<5> rs1;
+ bits<3> rd;
+
+ let Inst{31-25} = 0b0101011;
+ let Inst{24-20} = imm{7-3};
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = imm{2-0};
+ let Inst{11-10} = 0b00;
+ let Inst{9-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.MASKAND
+class RVInstET9<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<3> rs2;
+ bits<3> rs1;
+ bits<3> rd;
+
+ let Inst{31-25} = 0b0110011;
+ let Inst{24-23} = 0b00;
+ let Inst{22-20} = rs2;
+ let Inst{19-18} = 0b00;
+ let Inst{17-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-10} = 0b00;
+ let Inst{9-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.MASKPOPC
+class RVInstET10<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<3> rs1;
+ bits<5> rd;
+
+ let Inst{31-27} = 0b01010;
+ let Inst{26-25} = funct2;
+ let Inst{24-18} = 0b0000000;
+ let Inst{17-15} = rs1;
+ let Inst{14-12} = 0b000;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.MASKPOPC.RAST
+class RVInstET11<RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<4> imm;
+ bits<3> rs2;
+ bits<3> rs1;
+ bits<5> rd;
+
+ let Inst{31-25} = 0b0101111;
+ let Inst{24-23} = imm{3-2};
+ let Inst{22-20} = rs2;
+ let Inst{19-18} = imm{1-0};
+ let Inst{17-15} = rs1;
+ let Inst{14-12} = 0b000;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FSCW.PS
+class RVInstET12<bits<7> funct7,bits<3> funct3,
+ RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> rs1;
+ bits<5> rs2;
+ bits<5> rs3;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = rs3;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.SBG
+class RVInstET13<bits<7> funct7,bits<3> funct3,
+ RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> rs1;
+ bits<5> rs2;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = 0b00000;
+ let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FSWL.PS
+class RVInstET14<bits<7> funct7,bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+ bits<5> fs3;
+ bits<5> rs1;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-20} = 0b00000;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = fs3;
+ let Inst{6-0} = opcode.Value;
+}
+
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 708414496f4b6..264e3da6afd33 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -625,6 +625,7 @@ def LeadingOnesWMask : ImmLeaf<XLenVT, [{
include "RISCVInstrFormats.td"
include "RISCVInstrFormatsC.td"
include "RISCVInstrFormatsV.td"
+include "RISCVInstrFormatsXAIF.td"
//===----------------------------------------------------------------------===//
// Instruction Class Templates
@@ -2382,6 +2383,7 @@ include "RISCVInstrInfoXMips.td"
include "RISCVInstrInfoXRivos.td"
include "RISCVInstrInfoXAndes.td"
include "RISCVInstrInfoXSpacemiT.td"
+include "RISCVInstrInfoXAIF.td"
//===----------------------------------------------------------------------===//
// Global ISel
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXAIF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXAIF.td
new file mode 100644
index 0000000000000..66a867646cb1c
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXAIF.td
@@ -0,0 +1,789 @@
+//===-- RISCVInstrInfoXAIF.td ------------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Instruction definitions for the AI Foundry ET extensions, formerly known as
+// the ET-SoC-1 Minion extensions by Esperanto Technologies.
+//
+// Full documentation for these extensions is publicly available at the
+// following URL:
+//
+// https://github.com/aifoundry-org/et-man/blob/main/ET%20Programmer's%20Reference%20Manual.pdf
+//
+// The following conventions are used in this file:
+//
+// 1. Specific instruction formats are named
+//
+// RVInstET<#>
+//
+// where <#> is a number from 1 to 14. Each number corresponds to a template
+// fitting a given instruction and other similar ones, as defined in
+// RISCVInstrFormatsXAIF.td
+//
+// 2. Each masked vector instruction <INST> is handled with an ETOps<Operands>
+// multiclass defining one instruction and two pseudo instructions:
+//
+// - <INST>: regular masked vector instructions as described in the manual,
+// implicitly using M0 register for masking out destination register
+// elements.
+//
+// - <INST>_EX: masked vector pseudo-instruction explictly accepting M0 as
+// its last operand, as opposed to <INST> where the register dependency
+// is just implicit. In addition to the explicit operands accepted by
+// <INST>, we must add m0 as the last operand.
+//
+// The purpose of this instruction variant is to explicitly mark the
+// dependency on the m0 register contents in MIR (Machine Instruction
+// Representation).
+//
+// - <INST>_PASSTHRU_EX: Similar to <INST_EX>, but also making explicit the
+// dependency on the previous destination register contents. In addition
+// to the explicit operands accepted by <INST_EX>, we must add the
+// destination register as the first operand.
+//
+// Destination and first source operands are constrained to be assigned
+// the same physical register during register allocation.
+//
+// This variant should be the choice during instruction selection for
+// cases when m0 is not guaranteed to be all ones.
+//
+//===----------------------------------------------------------------------===//
+
+let DecoderNamespace = "XAIF" in {
+let Predicates = [HasXAIFET] in {
+
+ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+ def FLQ2 : RVInstI<0b101, OPC_LOAD_FP,
+ (outs FPR256:$rd),
+ (ins simm12_lo:$imm12, GPR:$rs1),
+ "aif.flq2", "$rd, ${imm12}(${rs1})">;
+
+ let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+ def FSQ2 : RVInstS<0b101, OPC_STORE_FP,
+ (outs),
+ (ins FPR256:$rs2, simm12_lo:$imm12, GPR:$rs1),
+ "aif.fsq2", "$rs2, ${imm12}(${rs1})">;
+
+ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+ def FLW_PS : RVInstI<0b010, OPC_ET_MEM_PS,
+ (outs FPR256:$rd),
+ (ins simm12_lo:$imm12, GPR:$rs1),
+ "aif.flw.ps", "$rd, ${imm12}(${rs1})">;
+ def FLW_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins simm12_lo:$imm12, GPR:$rs1, MR0:$m0), [],
+ "aif.flw.ps", "$rd, ${imm12}(${rs1}), $m0">;
+ def FLW_PS_PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, simm12_lo:$imm12, GPR:$rs1, MR0:$m0), [],
+ "aif.flw.ps", "$rd, ${imm12}(${rs1}), $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+ def FSW_PS : RVInstS<0b110, OPC_ET_MEM_PS,
+ (outs),
+ (ins FPR256:$rs2, simm12_lo:$imm12, GPR:$rs1),
+ "aif.fsw.ps", "$rs2, ${imm12}(${rs1})">;
+ def FSW_PS_EX : Pseudo<(outs),
+ (ins FPR256:$rs2, simm12_lo:$imm12, GPR:$rs1, MR0:$m0),
+ [], "aif.fsw.ps", "$rs2, ${imm12}(${rs1}), $m0">;
+ }
+
+ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+ def FBC_PS : RVInstI<0b000, OPC_ET_MEM_PS,
+ (outs FPR256:$rd),
+ (ins simm12_lo:$imm12, GPR:$rs1),
+ "aif.fbc.ps", "$rd, ${imm12}(${rs1})">;
+ def FBC_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins simm12_lo:$imm12, GPR:$rs1, MR0:$m0), [],
+ "aif.fbc.ps", "$rd, ${imm12}(${rs1}), $m0">;
+ }
+
+ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+ def FBCX_PS : RVInstI<0b011, OPC_ET_MEM_PS,
+ (outs FPR256:$rd),
+ (ins GPR:$rs1),
+ "aif.fbcx.ps", "$rd, ${rs1}"> {
+ let imm12 = 0;
+ }
+ def FBCX_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins GPR:$rs1, MR0:$m0),[],
+ "aif.fbcx.ps", "$rd, ${rs1}, $m0">;
+ def FBCX_PS_PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, GPR:$rs1, MR0:$m0),[],
+ "aif.fbcx.ps", "$rd, ${rs1}, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+
+ def FBCI_PS : RVInstU<OPC_ET_IMM_PS,
+ (outs FPR256:$rd),
+ (ins uimm20_lui:$imm20),
+ "aif.fbci.ps", "$rd, $imm20"> ;
+
+ def FBCI_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins uimm20_lui:$imm20, MR0:$m0), [],
+ "aif.fbci.ps", "$rd, $imm20, $m0">;
+ def FBCI_PS_PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, uimm20_lui:$imm20, MR0:$m0), [],
+ "aif.fbci.ps", "$rd, $imm20, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+
+ multiclass ETOpsRdF1R2G<bits<7> funct7, string opcodestr> {
+ def "" : RVInstR<funct7, 0b001, OPC_ET_MEM_PS,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, GPRMemZeroOffset:$rs2),
+ opcodestr, "$rd, ${rs1}, ${rs2}">;
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1, GPRMemZeroOffset:$rs2, MR0:$m0), [],
+ opcodestr, "$rd, ${rs1}, ${rs2}, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, GPRMemZeroOffset:$rs2, MR0:$m0), [],
+ opcodestr, "$rd, ${rs1}, ${rs2}, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+ defm FGW_PS : ETOpsRdF1R2G<0b0110000, "aif.fgw.ps">;
+ defm FGH_PS : ETOpsRdF1R2G<0b0101000, "aif.fgh.ps">;
+ defm FGB_PS : ETOpsRdF1R2G<0b0100100, "aif.fgb.ps">;
+ }
+
+ multiclass ETOpsR3R1R2<bits<7> funct7, bits<3> funct3, string opcodestr> {
+ def "" : RVInstET12<funct7, funct3, OPC_ET_MEM_PS,
+ (outs),
+ (ins FPR256:$rs3, FPR256:$rs1, GPRMemZeroOffset:$rs2),
+ opcodestr, "$rs3, ${rs1}, ${rs2}">;
+ def _EX : Pseudo<(outs),
+ (ins FPR256:$rs3, FPR256:$rs1, GPRMemZeroOffset:$rs2, MR0:$m0), [],
+ opcodestr, "$rs3, ${rs1}, ${rs2}, $m0">;
+ }
+
+ let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+ defm FSCW_PS : ETOpsR3R1R2<0b1110000, 0b001, "aif.fscw.ps">;
+ defm FSCH_PS : ETOpsR3R1R2<0b1101000, 0b001, "aif.fsch.ps">;
+ defm FSCB_PS : ETOpsR3R1R2<0b1100100, 0b001, "aif.fscb.ps">;
+ }
+
+ multiclass ETOpsRdR1R2Rm<bits<7> funct7, RISCVOpcode opcode,
+ string opcodestr> {
+ def "" : RVInstET3<funct7, opcode,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2, frmarg:$rm),
+ opcodestr, "$rd, $rs1, $rs2$rm">;
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2, frmarg:$rm, MR0:$m0),
+ [], opcodestr, "$rd, $rs1, $rs2$rm, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, FPR256:$rs2, frmarg:$rm, MR0:$m0),
+ [], opcodestr, "$rd, $rs1, $rs2$rm, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ defm FADD_PS : ETOpsRdR1R2Rm<0b0000000, OPC_ET_OP_PS, "aif.fadd.ps">;
+ defm FSUB_PS : ETOpsRdR1R2Rm<0b0000100, OPC_ET_OP_PS, "aif.fsub.ps">;
+ defm FMUL_PS : ETOpsRdR1R2Rm<0b0001000, OPC_ET_OP_PS, "aif.fmul.ps">;
+ defm FDIV_PS : ETOpsRdR1R2Rm<0b0001100, OPC_ET_OP_PS, "aif.fdiv.ps">;
+
+ multiclass ETOpsRdR1R2<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode,
+ string opcodestr> {
+ def "" : RVInstR<funct7, funct3, opcode,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2),
+ opcodestr, "$rd, $rs1, $rs2">;
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2, MR0:$m0),
+ [], opcodestr, "$rd, $rs1, $rs2, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, FPR256:$rs2, MR0:$m0),
+ [], opcodestr, "$rd, $rs1, $rs2, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ defm FMIN_PS : ETOpsRdR1R2<0b0010100, 0b000, OPC_ET_OP_PS, "aif.fmin.ps">;
+ defm FMAX_PS : ETOpsRdR1R2<0b0010100, 0b001, OPC_ET_OP_PS, "aif.fmax.ps">;
+
+ multiclass ETOpsRdR1R2R3Rm<bits<2> funct2, RISCVOpcode opcode,
+ string opcodestr> {
+ def "" : RVInstET4<funct2, opcode,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2, FPR256:$rs3, frmarg:$rm),
+ opcodestr, "$rd, $rs1, $rs2, $rs3$rm">;
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1,
+ FPR256:$rs2, FPR256:$rs3, frmarg:$rm, MR0:$m0),
+ [], opcodestr, "$rd, $rs1, $rs2, $rs3$rm, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1,
+ FPR256:$rs2, FPR256:$rs3, frmarg:$rm, MR0:$m0),
+ [], opcodestr, "$rd, $rs1, $rs2, $rs3$rm, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ defm FMADD_PS : ETOpsRdR1R2R3Rm<0b00, OPC_ET_OP3_PS, "aif.fmadd.ps">;
+ defm FMSUB_PS : ETOpsRdR1R2R3Rm<0b01, OPC_ET_OP3_PS, "aif.fmsub.ps">;
+ defm FNMSUB_PS : ETOpsRdR1R2R3Rm<0b10, OPC_ET_OP3_PS, "aif.fnmsub.ps">;
+ defm FNMADD_PS : ETOpsRdR1R2R3Rm<0b11, OPC_ET_OP3_PS, "aif.fnmadd.ps">;
+
+ def FCMOV_PS : RVInstET4<0b10, OPC_ET_IMM10_PI,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2, FPR256:$rs3),
+ "aif.fcmov.ps", "$rd, $rs1, $rs2, $rs3"> {
+ let rm = 0b010;
+ }
+
+ def FCMOV_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2,
+ FPR256:$rs3, MR0:$m0), [],
+ "aif.fcmov.ps", "$rd, $rs1, $rs2, $rs3, $m0">;
+ def FCMOV_PS_PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, FPR256:$rs2,
+ FPR256:$rs3, MR0:$m0), [],
+ "aif.fcmov.ps", "$rd, $rs1, $rs2, $rs3, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+
+ def FSWIZZ_PS : RVInstET1<0b1110011, OPC_ET_OP_PS,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, uimm8:$imm),
+ "aif.fswizz.ps", "$rd, $rs1, $imm">;
+ def FSWIZZ_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1, uimm8:$imm, MR0:$m0),
+ [], "aif.fswizz.ps", "$rd, $rs1, $imm, $m0">;
+ def FSWIZZ_PS_PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, uimm8:$imm, MR0:$m0),
+ [], "aif.fswizz.ps", "$rd, $rs1, $imm, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+
+ multiclass ETOpsRdR1Rm<bits<7> funct7, bits<5> funct1, RISCVOpcode opcode,
+ string opcodestr> {
+ def "" : RVInstET3<funct7, opcode,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, frmarg:$rm),
+ opcodestr, "$rd, $rs1$rm"> {
+ let rs2 = funct1;
+ }
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1, frmarg:$rm, MR0:$m0),
+ [], opcodestr, "$rd, $rs1$rm, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, frmarg:$rm, MR0:$m0),
+ [], opcodestr, "$rd, $rs1$rm, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ defm FCVT_PW_PS : ETOpsRdR1Rm<0b1100000, 0, OPC_ET_OP_PS, "aif.fcvt.pw.ps">;
+ defm FCVT_PWU_PS : ETOpsRdR1Rm<0b1100000, 1, OPC_ET_OP_PS, "aif.fcvt.pwu.ps">;
+ defm FCVT_PS_PW : ETOpsRdR1Rm<0b1101000, 0, OPC_ET_OP_PS, "aif.fcvt.ps.pw">;
+ defm FCVT_PS_PWU : ETOpsRdR1Rm<0b1101000, 1, OPC_ET_OP_PS, "aif.fcvt.ps.pwu">;
+
+ class ETOpsRdR1Idx<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode,
+ string opcodestr> :
+ RVInstET5<funct7, funct3, opcode,
+ (outs GPR:$rd),
+ (ins FPR256:$rs1, uimm3:$idx),
+ opcodestr, "$rd, $rs1, $idx">;
+
+ def FMVZ_X_PS : ETOpsRdR1Idx<0b1110000, 0b000, OPC_ET_OP_PS, "aif.fmvz.x.ps">;
+ // no _EX variant
+ def FMVS_X_PS : ETOpsRdR1Idx<0b1110000, 0b010, OPC_ET_OP_PS, "aif.fmvs.x.ps">;
+ // no _EX variant
+
+ defm FSGNJN_PS : ETOpsRdR1R2<0b0010000, 0b001, OPC_ET_OP_PS, "aif.fsgnjn.ps">;
+ defm FSGNJ_PS : ETOpsRdR1R2<0b0010000, 0b000, OPC_ET_OP_PS, "aif.fsgnj.ps">;
+ defm FSGNJX_PS : ETOpsRdR1R2<0b0010000, 0b010, OPC_ET_OP_PS, "aif.fsgnjx.ps">;
+ defm FLE_PS : ETOpsRdR1R2<0b1010000, 0b000, OPC_ET_OP_PS, "aif.fle.ps">;
+ defm FLT_PS : ETOpsRdR1R2<0b1010000, 0b001, OPC_ET_OP_PS, "aif.flt.ps">;
+ defm FEQ_PS : ETOpsRdR1R2<0b1010000, 0b010, OPC_ET_OP_PS, "aif.feq.ps">;
+
+ multiclass ETOpsMdR1R2<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode,
+ string opcodestr> {
+ def "" : RVInstR<funct7, funct3, opcode,
+ (outs MR:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2),
+ opcodestr, "$rd, $rs1, $rs2">;
+ def _EX : Pseudo<(outs MR:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2, MR0:$m0), [],
+ opcodestr, "$rd, $rs1, $rs2, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs MR:$rd),
+ (ins MR:$in, FPR256:$rs1, FPR256:$rs2, MR0:$m0), [],
+ opcodestr, "$rd, $rs1, $rs2, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ defm FLEM_PS : ETOpsMdR1R2<0b1010000, 0b100, OPC_ET_OP_PS, "aif.flem.ps">;
+ defm FLTM_PS : ETOpsMdR1R2<0b1010000, 0b101, OPC_ET_OP_PS, "aif.fltm.ps">;
+ defm FEQM_PS : ETOpsMdR1R2<0b1010000, 0b110, OPC_ET_OP_PS, "aif.feqm.ps">;
+
+ multiclass ETOpsRdR1<bits<7> funct7, bits<5> funct5, bits<3> funct3,
+ RISCVOpcode opcode, string opcodestr> {
+ def "" : RVInstR<funct7, funct3, opcode,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1),
+ opcodestr, "$rd, $rs1"> {
+ let rs2 = funct5;
+ }
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, MR0:$m0), [],
+ opcodestr, "$rd, $rs1, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, MR0:$m0), [],
+ opcodestr, "$rd, $rs1, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ defm FCLASS_PS : ETOpsRdR1<0b1110000, 0b00000, 0b001, OPC_ET_OP_PS, "aif.fclass.ps">;
+
+ multiclass ETOpsCvt<bits<7> funct7, bits<5> funct5, string opcodestr> {
+ defm "" : ETOpsRdR1<funct7, funct5, 0b000,
+ OPC_ET_OP_PS, opcodestr>;
+ }
+
+ defm FCVT_PS_F10 : ETOpsCvt<0b1101000, 0b01000, "aif.fcvt.ps.f10">;
+ defm FCVT_PS_F11 : ETOpsCvt<0b1101000, 0b01001, "aif.fcvt.ps.f11">;
+ defm FCVT_PS_F16 : ETOpsCvt<0b1101000, 0b01010, "aif.fcvt.ps.f16">;
+ defm FCVT_PS_UN24 : ETOpsCvt<0b1101000, 0b10000, "aif.fcvt.ps.un24">;
+ defm FCVT_PS_UN16 : ETOpsCvt<0b1101000, 0b10001, "aif.fcvt.ps.un16">;
+ defm FCVT_PS_UN10 : ETOpsCvt<0b1101000, 0b10010, "aif.fcvt.ps.un10">;
+ defm FCVT_PS_UN8 : ETOpsCvt<0b1101000, 0b10011, "aif.fcvt.ps.un8">;
+ defm FCVT_PS_UN2 : ETOpsCvt<0b1101000, 0b10111, "aif.fcvt.ps.un2">;
+ defm FCVT_PS_SN16 : ETOpsCvt<0b1101000, 0b11001, "aif.fcvt.ps.sn16">;
+ defm FCVT_PS_SN8 : ETOpsCvt<0b1101000, 0b11011, "aif.fcvt.ps.sn8">;
+ defm FCVT_F11_PS : ETOpsCvt<0b1101100, 0b01000, "aif.fcvt.f11.ps">;
+ defm FCVT_F16_PS : ETOpsCvt<0b1101100, 0b01001, "aif.fcvt.f16.ps">;
+ defm FCVT_F10_PS : ETOpsCvt<0b1101100, 0b01011, "aif.fcvt.f10.ps">;
+ defm FCVT_UN24_PS : ETOpsCvt<0b1101100, 0b10000, "aif.fcvt.un24.ps">;
+ defm FCVT_UN16_PS : ETOpsCvt<0b1101100, 0b10001, "aif.fcvt.un16.ps">;
+ defm FCVT_UN10_PS : ETOpsCvt<0b1101100, 0b10010, "aif.fcvt.un10.ps">;
+ defm FCVT_UN8_PS : ETOpsCvt<0b1101100, 0b10011, "aif.fcvt.un8.ps">;
+ defm FCVT_UN2_PS : ETOpsCvt<0b1101100, 0b10111, "aif.fcvt.un2.ps">;
+ defm FCVT_SN16_PS : ETOpsCvt<0b1101100, 0b11001, "aif.fcvt.sn16.ps">;
+ defm FCVT_SN8_PS : ETOpsCvt<0b1101100, 0b11011, "aif.fcvt.sn8.ps">;
+
+ def FBCI_PI : RVInstU<OPC_ET_IMM_PI,
+ (outs FPR256:$rd),
+ (ins uimm20_lui:$imm20),
+ "aif.fbci.pi", "$rd, ${imm20}">;
+ def FBCI_PI_EX : Pseudo<(outs FPR256:$rd),
+ (ins uimm20_lui:$imm20, MR0:$m0), [],
+ "aif.fbci.pi", "$rd, ${imm20}, $m0">;
+ def FBCI_PI_PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, uimm20_lui:$imm20, MR0:$m0), [],
+ "aif.fbci.pi", "$rd, ${imm20}, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+
+ defm FADD_PI : ETOpsRdR1R2<0b0000011, 0b000, OPC_ET_OP_PS, "aif.fadd.pi">;
+ defm FSUB_PI : ETOpsRdR1R2<0b0000111, 0b000, OPC_ET_OP_PS, "aif.fsub.pi">;
+ defm FMUL_PI : ETOpsRdR1R2<0b0001011, 0b000, OPC_ET_OP_PS, "aif.fmul.pi">;
+ defm FMULH_PI : ETOpsRdR1R2<0b0001011, 0b001, OPC_ET_OP_PS, "aif.fmulh.pi">;
+ defm FMULHU_PI : ETOpsRdR1R2<0b0001011, 0b010, OPC_ET_OP_PS, "aif.fmulhu.pi">;
+ defm FDIV_PI : ETOpsRdR1R2<0b0001111, 0b000, OPC_ET_OP_PS, "aif.fdiv.pi">;
+ defm FDIVU_PI : ETOpsRdR1R2<0b0001111, 0b001, OPC_ET_OP_PS, "aif.fdivu.pi">;
+ defm FREM_PI : ETOpsRdR1R2<0b0001111, 0b010, OPC_ET_OP_PS, "aif.frem.pi">;
+ defm FREMU_PI : ETOpsRdR1R2<0b0001111, 0b011, OPC_ET_OP_PS, "aif.fremu.pi">;
+ defm FMIN_PI : ETOpsRdR1R2<0b0010111, 0b000, OPC_ET_OP_PS, "aif.fmin.pi">;
+ defm FMAX_PI : ETOpsRdR1R2<0b0010111, 0b001, OPC_ET_OP_PS, "aif.fmax.pi">;
+ defm FMINU_PI : ETOpsRdR1R2<0b0010111, 0b010, OPC_ET_OP_PS, "aif.fminu.pi">;
+ defm FMAXU_PI : ETOpsRdR1R2<0b0010111, 0b011, OPC_ET_OP_PS, "aif.fmaxu.pi">;
+
+ defm FLTM_PI : ETOpsMdR1R2<0b0011111, 0b000, OPC_ET_OP_PS, "aif.fltm.pi">;
+
+ defm FAND_PI : ETOpsRdR1R2<0b0000011, 0b111, OPC_ET_OP_PS, "aif.fand.pi">;
+ defm FOR_PI : ETOpsRdR1R2<0b0000011, 0b110, OPC_ET_OP_PS, "aif.for.pi">;
+ defm FNOT_PI : ETOpsRdR1<0b0000011, 0b00000, 0b010, OPC_ET_OP_PS, "aif.fnot.pi">;
+ defm FXOR_PI : ETOpsRdR1R2<0b0000011, 0b100, OPC_ET_OP_PS, "aif.fxor.pi">;
+ defm FSLL_PI : ETOpsRdR1R2<0b0000011, 0b001, OPC_ET_OP_PS, "aif.fsll.pi">;
+ defm FSRL_PI : ETOpsRdR1R2<0b0000011, 0b101, OPC_ET_OP_PS, "aif.fsrl.pi">;
+ defm FSRA_PI : ETOpsRdR1R2<0b0000111, 0b101, OPC_ET_OP_PS, "aif.fsra.pi">;
+ defm FLE_PI : ETOpsRdR1R2<0b1010011, 0b000, OPC_ET_OP_PS, "aif.fle.pi">;
+ defm FLT_PI : ETOpsRdR1R2<0b1010011, 0b001, OPC_ET_OP_PS, "aif.flt.pi">;
+ defm FEQ_PI : ETOpsRdR1R2<0b1010011, 0b010, OPC_ET_OP_PS, "aif.feq.pi">;
+ defm FLTU_PI : ETOpsRdR1R2<0b1010011, 0b011, OPC_ET_OP_PS, "aif.fltu.pi">;
+
+ multiclass ETOpsMdR1<bits<7> funct7, bits<3> funct3,
+ RISCVOpcode opcode, string opcodestr> {
+ def "" : RVInstR<funct7, funct3, opcode,
+ (outs MR:$rd),
+ (ins FPR256:$rs1),
+ opcodestr, "$rd, $rs1"> {
+ let rs2 = 0;
+ }
+ def _EX : Pseudo<(outs MR:$rd),
+ (ins FPR256:$rs1, MR0:$m0),
+ [], opcodestr, "$rd, $rs1, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs MR:$rd),
+ (ins MR:$in, FPR256:$rs1, MR0:$m0),
+ [], opcodestr, "$rd, $rs1, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ defm FSETM_PI : ETOpsMdR1<0b1010011, 0b100, OPC_ET_OP_PS, "aif.fsetm.pi">;
+
+ multiclass ETOpsRdR1I10<bits<3> funct3, RISCVOpcode opcode, string opcodestr> {
+ def "" : RVInstET2<funct3, opcode,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, simm10:$imm),
+ opcodestr, "$rd, $rs1, ${imm}">;
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, simm10:$imm, MR0:$m0), [],
+ opcodestr, "$rd, $rs1, ${imm}, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, simm10:$imm, MR0:$m0), [],
+ opcodestr, "$rd, $rs1, ${imm}, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ defm FADDI_PI : ETOpsRdR1I10<0b000, OPC_ET_IMM10_PI, "aif.faddi.pi">;
+ defm FANDI_PI : ETOpsRdR1I10<0b001, OPC_ET_IMM10_PI, "aif.fandi.pi">;
+
+ multiclass ETOpsRdR1I5<bits<3> funct3, RISCVOpcode opcode, string opcodestr> {
+ def "" : RVInstET6<funct3, opcode,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, uimm5:$imm),
+ opcodestr, "$rd, $rs1, ${imm}">;
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, uimm5:$imm, MR0:$m0), [],
+ opcodestr, "$rd, $rs1, ${imm}, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, uimm5:$imm, MR0:$m0), [],
+ opcodestr, "$rd, $rs1, ${imm}, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ defm FSLLI_PI : ETOpsRdR1I5<0b001, OPC_ET_OP_PS, "aif.fslli.pi">;
+ defm FSRLI_PI : ETOpsRdR1I5<0b101, OPC_ET_OP_PS, "aif.fsrli.pi">;
+ defm FSRAI_PI : ETOpsRdR1I5<0b111, OPC_ET_OP_PS, "aif.fsrai.pi">;
+
+ defm FSIN_PS : ETOpsRdR1<0b0101100, 0b00110, 0b000, OPC_ET_OP_PS, "aif.fsin.ps">;
+ defm FEXP_PS : ETOpsRdR1<0b0101100, 0b00100, 0b000, OPC_ET_OP_PS, "aif.fexp.ps">;
+ defm FLOG_PS : ETOpsRdR1<0b0101100, 0b00011, 0b000, OPC_ET_OP_PS, "aif.flog.ps">;
+ defm FFRC_PS : ETOpsRdR1<0b0101100, 0b00010, 0b000, OPC_ET_OP_PS, "aif.ffrc.ps">;
+
+ def FROUND_PS : RVInstET7<OPC_ET_OP_PS,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, frmarg:$rm),
+ "aif.fround.ps", "$rd, $rs1$rm">;
+ def FROUND_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1, frmarg:$rm, MR0:$m0),
+ [], "aif.fround.ps", "$rd, $rs1$rm, $m0">;
+
+ defm FSQRT_PS : ETOpsRdR1<0b0101100, 0b00000, 0b000, OPC_ET_OP_PS, "aif.fsqrt.ps">;
+ defm FRCP_PS : ETOpsRdR1<0b0101100, 0b00111, 0b000, OPC_ET_OP_PS, "aif.frcp.ps">;
+ defm FRSQ_PS : ETOpsRdR1<0b0101100, 0b01000, 0b000, OPC_ET_OP_PS, "aif.frsq.ps">;
+
+ defm CUBEFACE_PS : ETOpsRdR1R2<0b1000100, 0b000, OPC_ET_OP_PS, "aif.cubeface.ps">;
+ defm CUBEFACEIDX_PS : ETOpsRdR1R2<0b1000100, 0b001, OPC_ET_OP_PS, "aif.cubefaceidx.ps">;
+ defm CUBESGNSC_PS : ETOpsRdR1R2<0b1000100, 0b010, OPC_ET_OP_PS, "aif.cubesgnsc.ps">;
+ defm CUBESGNTC_PS : ETOpsRdR1R2<0b1000100, 0b011, OPC_ET_OP_PS, "aif.cubesgntc.ps">;
+
+ def PACKB : ALUW_rr<0b1000000, 0b110, "aif.packb">;
+ def BITMIXB : ALUW_rr<0b1000000, 0b111, "aif.bitmixb">;
+
+ def MOV_M_X : RVInstET8<OPC_ET_OP_PS,
+ (outs MR:$rd),
+ (ins GPR:$rs1, uimm8:$imm),
+ "aif.mov.m.x", "$rd, $rs1, $imm">;
+ def MOVA_X_M : RVInstR<0b1101011, 0b000, OPC_ET_OP_PS,
+ (outs GPR:$rd),
+ (ins),
+ "aif.mova.x.m", "$rd"> {
+ let rs1 = 0;
+ let rs2 = 0;
+ }
+
+ def MOVA_M_X : RVInstR<0b1101011, 0b001, OPC_ET_OP_PS,
+ (outs),
+ (ins GPR:$rs1),
+ "aif.mova.m.x", "$rs1"> {
+ let rd = 0;
+ let rs2 = 0;
+ }
+
+ class ETOpsMdM1M2<bits<3> funct3, string codestr> :
+ RVInstET9<funct3, OPC_ET_OP_PS, (outs MR:$rd),
+ (ins MR:$rs1, MR:$rs2), codestr, "$rd, $rs1, $rs2">;
+
+ def MASKAND : ETOpsMdM1M2<0b111, "aif.maskand">;
+ def MASKOR : ETOpsMdM1M2<0b110, "aif.maskor">;
+ def MASKNOT : RVInstET9<0b010, OPC_ET_OP_PS, (outs MR:$rd),
+ (ins MR:$rs1), "aif.masknot", "$rd, $rs1"> {
+ let rs2 = 0;
+ }
+ def MASKXOR : ETOpsMdM1M2<0b100, "aif.maskxor">;
+
+ class ETOpsRdM1<bits<2> funct2, string opcodestr> :
+ RVInstET10<funct2, OPC_ET_OP_PS, (outs GPR:$rd), (ins MR:$rs1),
+ opcodestr, "$rd, $rs1">;
+
+ def MASKPOPC : ETOpsRdM1<0b01,"aif.maskpopc">;
+ def MASKPOPCZ : ETOpsRdM1<0b10,"aif.maskpopcz">;
+
+ def MASKPOPC_ET_RAST :
+ RVInstET11<OPC_ET_OP_PS, (outs MR:$rd),
+ (ins MR:$rs1, MR:$rs2, uimm4:$imm),
+ "aif.maskpopc.rast", "$rd, $rs1, $rs2, $imm">;
+
+ defm FPACKREPB_PI :
+ ETOpsRdR1<0b0010011, 0b00000, 0b000, OPC_ET_OP_PS, "aif.fpackrepb.pi">;
+ defm FPACKREPH_PI :
+ ETOpsRdR1<0b0010011, 0b00000, 0b001, OPC_ET_OP_PS, "aif.fpackreph.pi">;
+
+ multiclass ETOpsRdR1R2G32<bits<7> funct7, string opcodestr> {
+ def "" : RVInstR<funct7, 0b001, OPC_ET_MEM_PS,
+ (outs FPR256:$rd),
+ (ins GPR:$rs1, GPRMemZeroOffset:$rs2),
+ opcodestr, "$rd, ${rs1}, ${rs2}">;
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins GPR:$rs1, GPRMemZeroOffset:$rs2, MR0:$m0), [],
+ opcodestr, "$rd, ${rs1}, ${rs2}, m0">;
+ }
+
+ let mayLoad = 1 in {
+ defm FG32W_PS : ETOpsRdR1R2G32<0b0010000, "aif.fg32w.ps">;
+ defm FG32H_PS : ETOpsRdR1R2G32<0b0001000, "aif.fg32h.ps">;
+ defm FG32B_PS : ETOpsRdR1R2G32<0b0000100, "aif.fg32b.ps">;
+ }
+
+ multiclass ETOpsR3R1R2SC32<bits<7> funct7, string opcodestr> {
+ def "" : RVInstET12<funct7, 0b001, OPC_ET_MEM_PS,
+ (outs),
+ (ins FPR256:$rs3, GPR:$rs1, GPRMemZeroOffset:$rs2),
+ opcodestr, "$rs3, ${rs1}, ${rs2}">;
+ def _EX : Pseudo<(outs),
+ (ins FPR256:$rs3, GPR:$rs1, GPRMemZeroOffset:$rs2, MR0:$m0), [],
+ opcodestr, "$rs3, ${rs1}, ${rs2}, $m0">;
+ }
+
+ let mayStore = 1 in {
+ defm FSC32W_PS : ETOpsR3R1R2SC32<0b1010000, "aif.fsc32w.ps">;
+ defm FSC32H_PS : ETOpsR3R1R2SC32<0b1001000, "aif.fsc32h.ps">;
+ defm FSC32B_PS : ETOpsR3R1R2SC32<0b1000100, "aif.fsc32b.ps">;
+ }
+
+ // Specialse FCMOVM has no implicit input since all of output
+ // is defined.
+ def FCMOVM_PS : RVInstR<0b0000000, 0b000, OPC_ET_CVT_PS,
+ (outs FPR256:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2),
+ "aif.fcmovm.ps", "$rd, $rs1, $rs2">;
+ def FCMOVM_PS_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1, FPR256:$rs2, MR0:$m0), [],
+ "aif.fcmovm.ps", "$rd, $rs1, $rs2, $m0">;
+
+ defm FRCP_FIX_RAST : ETOpsRdR1R2<0b0011000, 0b000, OPC_ET_OP_PS, "aif.frcp_fix.rast">;
+ defm FCVT_RAST_PS : ETOpsRdR1<0b1100000,0b00010,0b000, OPC_ET_OP_PS, "aif.fcvt.rast.ps">;
+ defm FCVT_PS_RAST : ETOpsRdR1<0b1101000, 0b00010, 0b000, OPC_ET_OP_PS, "aif.fcvt.ps.rast">;
+ defm FSAT8_PI : ETOpsRdR1<0b0000011, 0b00000, 0b011, OPC_ET_OP_PS, "aif.fsat8.pi">;
+ defm FSATU8_PI : ETOpsRdR1<0b0000011, 0b00001, 0b011, OPC_ET_OP_PS, "aif.fsatu8.pi">;
+
+ multiclass ETOpsFdR1<bits<7> funct7, string opcodestr> {
+ def "" : RVInstR<funct7,0b111,OPC_ET_MEM_PS,
+ (outs FPR256:$rd), (ins GPR:$rs1),
+ opcodestr, "$rd, (${rs1})"> {
+ let rs2 = 0;
+ }
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins GPR:$rs1, MR0:$m0), [],
+ opcodestr, "$rd, (${rs1}), $m0">;
+ }
+
+ let mayLoad = 1 in {
+ defm FLWL_PS : ETOpsFdR1<0b0001000, "aif.flwl.ps">;
+ defm FLWG_PS : ETOpsFdR1<0b0001001, "aif.flwg.ps">;
+ }
+
+ multiclass ETOpsFs3Rs1<bits<7> funct7, string opcodestr> {
+ def "" : RVInstET14<funct7,0b111,OPC_ET_MEM_PS,
+ (outs), (ins FPR256:$fs3, GPR:$rs1),
+ opcodestr, "$fs3, (${rs1})">;
+ def _EX : Pseudo<(outs), (ins FPR256:$fs3, GPR:$rs1, MR0:$m0), [],
+ opcodestr, "$fs3, (${rs1}), $m0">;
+ }
+
+ let mayStore = 1 in {
+ defm FSWL_PS : ETOpsFs3Rs1<0b0101000, "aif.fswl.ps">;
+ defm FSWG_PS : ETOpsFs3Rs1<0b0101001, "aif.fswg.ps">;
+ }
+
+ multiclass ETOpsRdR1R2FG<bits<7> funct7, bits<3> funct3, string opcodestr> {
+ def "" : RVInstR<funct7, funct3, OPC_ET_MEM_PS, (outs FPR256:$rd),
+ (ins FPR256:$rs1, GPRMemZeroOffset:$rs2), opcodestr,
+ "$rd, ${rs1}, ${rs2}">;
+ def _EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$rs1, GPRMemZeroOffset:$rs2, MR0:$m0), [], opcodestr,
+ "$rd, ${rs1}, ${rs2}, $m0">;
+ def _PASSTHRU_EX : Pseudo<(outs FPR256:$rd),
+ (ins FPR256:$in, FPR256:$rs1, GPRMemZeroOffset:$rs2, MR0:$m0), [], opcodestr,
+ "$rd, ${rs1}, ${rs2}, $m0"> {
+ let Constraints = "$rd = $in";
+ }
+ }
+
+ let mayLoad = 1 in {
+ defm FGBL_PS : ETOpsRdR1R2FG<0b1000000, 0b111, "aif.fgbl.ps">;
+ defm FGHL_PS : ETOpsRdR1R2FG<0b1000100, 0b111, "aif.fghl.ps">;
+ defm FGWL_PS : ETOpsRdR1R2FG<0b1001000, 0b111, "aif.fgwl.ps">;
+ }
+
+ multiclass ETOpsR3R1R2FS<bits<7> funct7, bits<3> funct3, string opcodestr> {
+ def "" : RVInstET12<funct7, funct3, OPC_ET_MEM_PS, (outs),
+ (ins FPR256:$rs3, FPR256:$rs1, GPRMemZeroOffset:$rs2), opcodestr,
+ "${rs3}, ${rs1}, ${rs2}">;
+ def _EX : Pseudo<(outs),
+ (ins FPR256:$rs3, FPR256:$rs1, GPRMemZeroOffset:$rs2, MR0:$m0),
+ [], opcodestr,
+ "${rs3}, ${rs1}, ${rs2}, $m0">;
+ }
+
+ let mayStore = 1 in {
+ defm FSCBL_PS : ETOpsR3R1R2FS<0b1100000, 0b111, "aif.fscbl.ps">;
+ defm FSCHL_PS : ETOpsR3R1R2FS<0b1100100, 0b111, "aif.fschl.ps">;
+ defm FSCWL_PS : ETOpsR3R1R2FS<0b1101000, 0b111, "aif.fscwl.ps">;
+ }
+
+ let mayLoad = 1 in {
+ defm FGBG_PS : ETOpsRdR1R2FG<0b1000001, 0b111, "aif.fgbg.ps">;
+ defm FGHG_PS : ETOpsRdR1R2FG<0b1000101, 0b111, "aif.fghg.ps">;
+ defm FGWG_PS : ETOpsRdR1R2FG<0b1001001, 0b111, "aif.fgwg.ps">;
+ }
+
+ let mayStore = 1 in {
+ defm FSCBG_PS : ETOpsR3R1R2FS<0b1100001, 0b111, "aif.fscbg.ps">;
+ defm FSCHG_PS : ETOpsR3R1R2FS<0b1100101, 0b111, "aif.fschg.ps">;
+ defm FSCWG_PS : ETOpsR3R1R2FS<0b1101001, 0b111, "aif.fscwg.ps">;
+ }
+
+ let mayLoad = 1, mayStore = 1 in {
+ defm FAMOADDL_PI : ETOpsRdR1R2FG<0b0000011, 0b100, "aif.famoaddl.pi">;
+ defm FAMOSWAPL_PI : ETOpsRdR1R2FG<0b0000111, 0b100, "aif.famoswapl.pi">;
+ defm FAMOANDL_PI : ETOpsRdR1R2FG<0b0001011, 0b100, "aif.famoandl.pi">;
+ defm FAMOORL_PI : ETOpsRdR1R2FG<0b0001111, 0b100, "aif.famoorl.pi">;
+ defm FAMOXORL_PI : ETOpsRdR1R2FG<0b0010011, 0b100, "aif.famoxorl.pi">;
+ defm FAMOMINL_PI : ETOpsRdR1R2FG<0b0010111, 0b100, "aif.famominl.pi">;
+ defm FAMOMAXL_PI : ETOpsRdR1R2FG<0b0011011, 0b100, "aif.famomaxl.pi">;
+ defm FAMOMINUL_PI : ETOpsRdR1R2FG<0b0011111, 0b100, "aif.famominul.pi">;
+ defm FAMOMAXUL_PI : ETOpsRdR1R2FG<0b0100011, 0b100, "aif.famomaxul.pi">;
+ defm FAMOMINL_PS : ETOpsRdR1R2FG<0b0011000, 0b100, "aif.famominl.ps">;
+ defm FAMOMAXL_PS : ETOpsRdR1R2FG<0b0010100, 0b100, "aif.famomaxl.ps">;
+
+ defm FAMOADDG_PI : ETOpsRdR1R2FG<0b1000011, 0b100, "aif.famoaddg.pi">;
+ defm FAMOSWAPG_PI : ETOpsRdR1R2FG<0b1000111, 0b100, "aif.famoswapg.pi">;
+ defm FAMOANDG_PI : ETOpsRdR1R2FG<0b1001011, 0b100, "aif.famoandg.pi">;
+ defm FAMOORG_PI : ETOpsRdR1R2FG<0b1001111, 0b100, "aif.famoorg.pi">;
+ defm FAMOXORG_PI : ETOpsRdR1R2FG<0b1010011, 0b100, "aif.famoxorg.pi">;
+ defm FAMOMING_PI : ETOpsRdR1R2FG<0b1010111, 0b100, "aif.famoming.pi">;
+ defm FAMOMAXG_PI : ETOpsRdR1R2FG<0b1011011, 0b100, "aif.famomaxg.pi">;
+ defm FAMOMINUG_PI : ETOpsRdR1R2FG<0b1011111, 0b100, "aif.famominug.pi">;
+ defm FAMOMAXUG_PI : ETOpsRdR1R2FG<0b1100011, 0b100, "aif.famomaxug.pi">;
+ defm FAMOMING_PS : ETOpsRdR1R2FG<0b1011000, 0b100, "aif.famoming.ps">;
+ defm FAMOMAXG_PS : ETOpsRdR1R2FG<0b1010100, 0b100, "aif.famomaxg.ps">;
+ }
+
+ class ETOpsR2R1<bits<7> funct7, bits<3> funct3, string opcodestr> :
+ RVInstR<funct7, funct3, OPC_OP_32, (outs GPR:$rd),
+ (ins GPR:$rs2, GPRMemZeroOffset:$rs1), opcodestr,
+ "${rd}, ${rs2}, ${rs1}">;
+
+ let mayLoad = 1, mayStore = 1 in {
+ def AMOSWAPL_W : ETOpsR2R1<0b0000100, 0b010, "aif.amoswapl.w">;
+ def AMOADDL_W : ETOpsR2R1<0b0000000, 0b010, "aif.amoaddl.w">;
+ def AMOXORL_W : ETOpsR2R1<0b0010000, 0b010, "aif.amoxorl.w">;
+ def AMOANDL_W : ETOpsR2R1<0b0110000, 0b010, "aif.amoandl.w">;
+ def AMOORL_W : ETOpsR2R1<0b0100000, 0b010, "aif.amoorl.w">;
+ def AMOMINL_W : ETOpsR2R1<0b1000000, 0b010, "aif.amominl.w">;
+ def AMOMAXL_W : ETOpsR2R1<0b1010000, 0b010, "aif.amomaxl.w">;
+ def AMOMINUL_W : ETOpsR2R1<0b1100000, 0b010, "aif.amominul.w">;
+ def AMOMAXUL_W : ETOpsR2R1<0b1110000, 0b010, "aif.amomaxul.w">;
+ def AMOCMPSWAPL_W : ETOpsR2R1<0b1111000, 0b010, "aif.amocmpswapl.w">;
+
+ def AMOSWAPG_W : ETOpsR2R1<0b0000101, 0b010, "aif.amoswapg.w">;
+ def AMOADDG_W : ETOpsR2R1<0b0000001, 0b010, "aif.amoaddg.w">;
+ def AMOXORG_W : ETOpsR2R1<0b0010001, 0b010, "aif.amoxorg.w">;
+ def AMOANDG_W : ETOpsR2R1<0b0110001, 0b010, "aif.amoandg.w">;
+ def AMOORG_W : ETOpsR2R1<0b0100001, 0b010, "aif.amoorg.w">;
+ def AMOMING_W : ETOpsR2R1<0b1000001, 0b010, "aif.amoming.w">;
+ def AMOMAXG_W : ETOpsR2R1<0b1010001, 0b010, "aif.amomaxg.w">;
+ def AMOMINUG_W : ETOpsR2R1<0b1100001, 0b010, "aif.amominug.w">;
+ def AMOMAXUG_W : ETOpsR2R1<0b1110001, 0b010, "aif.amomaxug.w">;
+ def AMOCMPSWAPG_W : ETOpsR2R1<0b1111001, 0b010, "aif.amocmpswapg.w">;
+
+ def AMOSWAPL_D : ETOpsR2R1<0b0000100, 0b011, "aif.amoswapl.d">;
+ def AMOADDL_D : ETOpsR2R1<0b0000000, 0b011, "aif.amoaddl.d">;
+ def AMOXORL_D : ETOpsR2R1<0b0010000, 0b011, "aif.amoxorl.d">;
+ def AMOANDL_D : ETOpsR2R1<0b0110000, 0b011, "aif.amoandl.d">;
+ def AMOORL_D : ETOpsR2R1<0b0100000, 0b011, "aif.amoorl.d">;
+ def AMOMINL_D : ETOpsR2R1<0b1000000, 0b011, "aif.amominl.d">;
+ def AMOMAXL_D : ETOpsR2R1<0b1010000, 0b011, "aif.amomaxl.d">;
+ def AMOMINUL_D : ETOpsR2R1<0b1100000, 0b011, "aif.amominul.d">;
+ def AMOMAXUL_D : ETOpsR2R1<0b1110000, 0b011, "aif.amomaxul.d">;
+ def AMOCMPSWAPL_D : ETOpsR2R1<0b1111000, 0b011, "aif.amocmpswapl.d">;
+
+ def AMOSWAPG_D : ETOpsR2R1<0b0000101, 0b011, "aif.amoswapg.d">;
+ def AMOADDG_D : ETOpsR2R1<0b0000001, 0b011, "aif.amoaddg.d">;
+ def AMOXORG_D : ETOpsR2R1<0b0010001, 0b011, "aif.amoxorg.d">;
+ def AMOANDG_D : ETOpsR2R1<0b0110001, 0b011, "aif.amoandg.d">;
+ def AMOORG_D : ETOpsR2R1<0b0100001, 0b011, "aif.amoorg.d">;
+ def AMOMING_D : ETOpsR2R1<0b1000001, 0b011, "aif.amoming.d">;
+ def AMOMAXG_D : ETOpsR2R1<0b1010001, 0b011, "aif.amomaxg.d">;
+ def AMOMINUG_D : ETOpsR2R1<0b1100001, 0b011, "aif.amominug.d">;
+ def AMOMAXUG_D : ETOpsR2R1<0b1110001, 0b011, "aif.amomaxug.d">;
+ def AMOCMPSWAPG_D : ETOpsR2R1<0b1111001, 0b011, "aif.amocmpswapg.d">;
+ } // let mayLoad = 1, mayStore =1 in
+
+ class ETOpsR1R2S<bits<7> funct7, bits<3> funct3, string opcodestr> :
+ RVInstR<funct7, funct3, OPC_OP_32, (outs),
+ (ins GPR:$rs2, GPRMemZeroOffset:$rs1), opcodestr,
+ "${rs2}, ${rs1}"> {
+ let rd = 0;
+ }
+
+ let mayLoad = 1 in {
+ def SBL : ETOpsR1R2S<0b0001000, 0b011, "aif.sbl">;
+ def SHL : ETOpsR1R2S<0b0001100, 0b011, "aif.shl">;
+ def SBG : ETOpsR1R2S<0b0001001, 0b011, "aif.sbg">;
+ def SHG : ETOpsR1R2S<0b0001101, 0b011, "aif.shg">;
+ }
+
+ // These pseudo operations are used for stack references
+ // where various places assume the offset immediate follows
+ // the address operand.
+ let mayStore = 1 in
+ def StackFSQ2 : Pseudo<(outs),
+ (ins FPR256:$rs2, GPR:$rs1, simm12_lo:$imm), [],
+ "aif.fsq2", "$rs2, ${imm}(${rs1})">;
+ let mayLoad = 1 in
+ def StackFLQ2 : Pseudo<(outs FPR256:$rd),
+ (ins GPR:$rs1, simm12_lo:$imm), [],
+ "aif.flq2", "$rd, ${imm}(${rs1})">;
+
+ // These pseudo operations are used for spill and reload
+ // of mask operations
+ let mayStore = 1 in
+ def StackMS : Pseudo<(outs),
+ (ins MR:$rs2, GPR:$rs1, simm12_lo:$imm), [],
+ "aif.ms", "$rs2, ${imm}(${rs1})">;
+ let mayLoad = 1 in
+ def StackML : Pseudo<(outs MR:$rd),
+ (ins GPR:$rs1, simm12_lo:$imm), [],
+ "aif.ml", "$rd, ${imm}(${rs1})">;
+
+ } // let hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+} // let Predicates = [HasXAIFET]
+} // let DecoderNamespace = "XAIF"
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 5becfd2ad502b..64328a7be21f2 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -881,3 +881,19 @@ def ANDES_AX45MPV : RISCVProcessorModel<"andes-ax45mpv",
FeatureStdExtV,
FeatureVendorXAndesPerf],
Andes45TuneFeatures>;
+
+def ESPERANTO_SOC1 : RISCVProcessorModel<"et-soc1",
+ NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtF,
+ FeatureStdExtC,
+ FeatureVendorXAIFET]>;
+
+def AINEKKO_ERBIUM : RISCVProcessorModel<"an-erbium",
+ NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtM,
+ FeatureStdExtF,
+ FeatureStdExtC,
+ FeatureVendorXAIFET]>;
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index e3657badfa9a4..f4d2504b9c6d3 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -901,3 +901,57 @@ let RegInfos = XLenRI in {
def TRM2 : RISCVRegisterClass<[untyped], 32, (add (decimate TR, 2))>;
def TRM4 : RISCVRegisterClass<[untyped], 32, (add (decimate TR, 4))>;
}
+
+//===----------------------------------------------------------------------===//
+// XAIFET registers
+//===----------------------------------------------------------------------===//
+
+// Each scalar floating point register is extended to a 256 bits wide vector.
+// The original scalar floating point register occupies the 32 LSB of the
+// vector.
+
+class RISCVReg256<RISCVReg32 subreg> :
+ RISCVRegWithSubRegs<subreg.HWEncoding{4-0}, subreg.AsmName, [subreg],
+ subreg.AltNames> {
+ let SubRegIndices = [sub_32];
+}
+
+let RegAltNameIndices = [ABIRegAltName] in {
+ foreach Index = 0-31 in {
+ def F#Index#_PS : RISCVReg256<!cast<RISCVReg32>("F"#Index#"_F")>,
+ DwarfRegNum<[!add(Index, 3088)]>;
+ }
+}
+
+// The order of registers represents the preferred allocation sequence,
+// meaning caller-save regs are listed before callee-save.
+
+def FPR256 : RISCVRegisterClass<[v8i32, v8f32], 256,
+ (add
+ (sequence "F%u_PS", 0, 7),
+ (sequence "F%u_PS", 10, 17),
+ (sequence "F%u_PS", 28, 31),
+ (sequence "F%u_PS", 8, 9),
+ (sequence "F%u_PS", 18, 27)
+ )> {
+ let RegInfos = RegInfoByHwMode<[RV32, RV64],
+ [RegInfo<256,256,32>, RegInfo<256,256,32>]>;
+}
+
+// Mask registers m0 to m7
+let RegAltNameIndices = [ABIRegAltName] in {
+ foreach Index = 0-7 in {
+ def M#Index : RISCVReg<Index, "m"#Index, ["m"#Index]>,
+ DwarfRegNum<[!add(Index, 4020)]>;
+ }
+}
+
+// Allowing i8 in addition to v8i simplifies the handling of builtins
+def MR : RISCVRegisterClass<[i8, v8i1], 8,
+ (add (sequence "M%u", 1, 7), M0)> {
+ let Size = 8;
+}
+
+def MR0 : RISCVRegisterClass<[i8, v8i1], 8, (add M0)> {
+ let Size = 8;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 7f038ee728284..66e3484ff0955 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -566,3 +566,61 @@ foreach i = 0 - 3 in {
def : SysReg<"qc.mwpendaddr" # i, !add(0x7D4, i)>;
}
} // FeatureVendorXqciint, isRV32Only
+
+// XAIFET
+let FeaturesRequired = [{ {RISCV::FeatureVendorXAIFET} }] in {
+ def : SysReg<"aif.cache_invalidate", 0x7d0>;
+ def : SysReg<"aif.dcache_debug", 0xfc0>;
+ def : SysReg<"aif.evict_sw", 0x7f9>;
+ def : SysReg<"aif.evict_va", 0x89f>;
+ def : SysReg<"aif.excl_mode", 0x7d3>;
+ def : SysReg<"aif.fcc", 0x821>;
+ def : SysReg<"aif.fccnb", 0xcc0>;
+ def : SysReg<"aif.flb", 0x820>;
+ def : SysReg<"aif.flush_sw", 0x7fb>;
+ def : SysReg<"aif.flush_va", 0x8bf>;
+ def : SysReg<"aif.gsc_progress", 0x840>;
+ def : SysReg<"aif.hartid", 0xcd0>;
+ def : SysReg<"aif.lock_sw", 0x7fd>;
+ def : SysReg<"aif.lock_va", 0x8df>;
+ def : SysReg<"aif.matp", 0x7c0>;
+ def : SysReg<"aif.mbusaddr", 0x7d5>;
+ def : SysReg<"aif.mcache_control", 0x7e0>;
+ def : SysReg<"aif.menable_shadows", 0x7d2>;
+ def : SysReg<"aif.minstmask", 0x7cd>;
+ def : SysReg<"aif.minstmatch", 0x7ce>;
+ def : SysReg<"aif.portctrl0", 0x9cc>;
+ def : SysReg<"aif.portctrl1", 0x9cd>;
+ def : SysReg<"aif.portctrl2", 0x9ce>;
+ def : SysReg<"aif.portctrl3", 0x9cf>;
+ def : SysReg<"aif.porthead0", 0xcc8>;
+ def : SysReg<"aif.porthead1", 0xcc9>;
+ def : SysReg<"aif.porthead2", 0xcca>;
+ def : SysReg<"aif.porthead3", 0xccb>;
+ def : SysReg<"aif.portheadnb0", 0xccc>;
+ def : SysReg<"aif.portheadnb1", 0xccd>;
+ def : SysReg<"aif.portheadnb2", 0xcce>;
+ def : SysReg<"aif.portheadnb3", 0xccf>;
+ def : SysReg<"aif.prefetch_va", 0x81f>;
+ def : SysReg<"aif.stall", 0x822>;
+ def : SysReg<"aif.tensor_conv_ctrl", 0x803>;
+ def : SysReg<"aif.tensor_conv_size", 0x802>;
+ def : SysReg<"aif.tensor_coop", 0x804>;
+ def : SysReg<"aif.tensor_error", 0x808>;
+ def : SysReg<"aif.tensor_fma", 0x801>;
+ def : SysReg<"aif.tensor_load", 0x83f>;
+ def : SysReg<"aif.tensor_load_l2", 0x85f>;
+ def : SysReg<"aif.tensor_mask", 0x805>;
+ def : SysReg<"aif.tensor_quant", 0x806>;
+ def : SysReg<"aif.tensor_reduce", 0x800>;
+ def : SysReg<"aif.tensor_store", 0x87f>;
+ def : SysReg<"aif.tensor_wait", 0x830>;
+ def : SysReg<"aif.tex_send", 0x807>;
+ def : SysReg<"aif.ucache_control", 0x810>;
+ def : SysReg<"aif.unlock_sw", 0x7ff>;
+ def : SysReg<"aif.unlock_va", 0x8ff>;
+ def : SysReg<"aif.validation0", 0x8d0>;
+ def : SysReg<"aif.validation1", 0x8d1>;
+ def : SysReg<"aif.validation2", 0x8d2>;
+ def : SysReg<"aif.validation3", 0x8d3>;
+} // FeatureVendorXAIFET
diff --git a/llvm/test/MC/RISCV/xaifet-amo-valid.s b/llvm/test/MC/RISCV/xaifet-amo-valid.s
new file mode 100644
index 0000000000000..7b3cea7447abc
--- /dev/null
+++ b/llvm/test/MC/RISCV/xaifet-amo-valid.s
@@ -0,0 +1,751 @@
+# XAIFET - AI Foundry ET AMO instructions
+
+# RUN: llvm-mc --arch=riscv64 -mattr=+xaifet --show-encoding %s | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+
+#====----------------------------------------------------------------------===//
+# Scalar INT AMO local|global
+#====----------------------------------------------------------------------===//
+
+# CHECK-INST: aif.amoaddg.d a4, s9, (t1)
+# CHECK-ENC: encoding: [0x3b,0x37,0x93,0x03]
+aif.amoaddg.d a4, s9, (t1)
+
+# CHECK-INST: aif.amoaddg.w t1, s5, (t0)
+# CHECK-ENC: encoding: [0x3b,0xa3,0x52,0x03]
+aif.amoaddg.w t1, s5, (t0)
+
+# CHECK-INST: aif.amoaddl.d a4, s4, (a6)
+# CHECK-ENC: encoding: [0x3b,0x37,0x48,0x01]
+aif.amoaddl.d a4, s4, (a6)
+
+# CHECK-INST: aif.amoaddl.w tp, t2, (gp)
+# CHECK-ENC: encoding: [0x3b,0xa2,0x71,0x00]
+aif.amoaddl.w tp, t2, (gp)
+
+# CHECK-INST: aif.amoandg.d s2, a5, (a2)
+# CHECK-ENC: encoding: [0x3b,0x39,0xf6,0x62]
+aif.amoandg.d s2, a5, (a2)
+
+# CHECK-INST: aif.amoandg.w t0, s8, (s2)
+# CHECK-ENC: encoding: [0xbb,0x22,0x89,0x63]
+aif.amoandg.w t0, s8, (s2)
+
+# CHECK-INST: aif.amoandl.d sp, ra, (a4)
+# CHECK-ENC: encoding: [0x3b,0x31,0x17,0x60]
+aif.amoandl.d sp, ra, (a4)
+
+# CHECK-INST: aif.amoandl.w t5, s0, (gp)
+# CHECK-ENC: encoding: [0x3b,0xaf,0x81,0x60]
+aif.amoandl.w t5, s0, (gp)
+
+# CHECK-INST: aif.amocmpswapg.d s0, gp, (a3)
+# CHECK-ENC: encoding: [0x3b,0xb4,0x36,0xf2]
+aif.amocmpswapg.d fp, gp, (a3)
+
+# CHECK-INST: aif.amocmpswapg.w a5, tp, (s8)
+# CHECK-ENC: encoding: [0xbb,0x27,0x4c,0xf2]
+aif.amocmpswapg.w a5, tp, (s8)
+
+# CHECK-INST: aif.amocmpswapl.d t5, s6, (s1)
+# CHECK-ENC: encoding: [0x3b,0xbf,0x64,0xf1]
+aif.amocmpswapl.d t5, s6, (s1)
+
+# CHECK-INST: aif.amocmpswapl.w a7, s0, (sp)
+# CHECK-ENC: encoding: [0xbb,0x28,0x81,0xf0]
+aif.amocmpswapl.w a7, s0, (sp)
+
+# CHECK-INST: aif.amomaxg.d tp, s10, (a2)
+# CHECK-ENC: encoding: [0x3b,0x32,0xa6,0xa3]
+aif.amomaxg.d tp, s10, (a2)
+
+# CHECK-INST: aif.amomaxg.w a0, s6, (a1)
+# CHECK-ENC: encoding: [0x3b,0xa5,0x65,0xa3]
+aif.amomaxg.w a0, s6, (a1)
+
+# CHECK-INST: aif.amomaxl.d a6, s7, (s4)
+# CHECK-ENC: encoding: [0x3b,0x38,0x7a,0xa1]
+aif.amomaxl.d a6, s7, (s4)
+
+# CHECK-INST: aif.amomaxl.w s4, s3, (a7)
+# CHECK-ENC: encoding: [0x3b,0xaa,0x38,0xa1]
+aif.amomaxl.w s4, s3, (a7)
+
+# CHECK-INST: aif.amomaxug.d t0, s4, (t2)
+# CHECK-ENC: encoding: [0xbb,0xb2,0x43,0xe3]
+aif.amomaxug.d t0, s4, (t2)
+
+# CHECK-INST: aif.amomaxug.w s5, t5, (t2)
+# CHECK-ENC: encoding: [0xbb,0xaa,0xe3,0xe3]
+aif.amomaxug.w s5, t5, (t2)
+
+# CHECK-INST: aif.amomaxul.d t2, t2, (tp)
+# CHECK-ENC: encoding: [0xbb,0x33,0x72,0xe0]
+aif.amomaxul.d t2, t2, (tp)
+
+# CHECK-INST: aif.amomaxul.w t5, a2, (t4)
+# CHECK-ENC: encoding: [0x3b,0xaf,0xce,0xe0]
+aif.amomaxul.w t5, a2, (t4)
+
+# CHECK-INST: aif.amoming.d s0, t0, (s1)
+# CHECK-ENC: encoding: [0x3b,0xb4,0x54,0x82]
+aif.amoming.d fp, t0, (s1)
+
+# CHECK-INST: aif.amoming.w a1, s4, (t2)
+# CHECK-ENC: encoding: [0xbb,0xa5,0x43,0x83]
+aif.amoming.w a1, s4, (t2)
+
+# CHECK-INST: aif.amominl.d t0, a5, (t3)
+# CHECK-ENC: encoding: [0xbb,0x32,0xfe,0x80]
+aif.amominl.d t0, a5, (t3)
+
+# CHECK-INST: aif.amominl.w t3, s5, (gp)
+# CHECK-ENC: encoding: [0x3b,0xae,0x51,0x81]
+aif.amominl.w t3, s5, (gp)
+
+# CHECK-INST: aif.amominug.d s9, t1, (s3)
+# CHECK-ENC: encoding: [0xbb,0xbc,0x69,0xc2]
+aif.amominug.d s9, t1, (s3)
+
+# CHECK-INST: aif.amominug.w a4, s0, (gp)
+# CHECK-ENC: encoding: [0x3b,0xa7,0x81,0xc2]
+aif.amominug.w a4, fp, (gp)
+
+# CHECK-INST: aif.amominul.d ra, a6, (ra)
+# CHECK-ENC: encoding: [0xbb,0xb0,0x00,0xc1]
+aif.amominul.d ra, a6, (ra)
+
+# CHECK-INST: aif.amominul.w a1, a3, (s8)
+# CHECK-ENC: encoding: [0xbb,0x25,0xdc,0xc0]
+aif.amominul.w a1, a3, (s8)
+
+# CHECK-INST: aif.amoorg.d a5, a7, (a4)
+# CHECK-ENC: encoding: [0xbb,0x37,0x17,0x43]
+aif.amoorg.d a5, a7, (a4)
+
+# CHECK-INST: aif.amoorg.w s10, a5, (s9)
+# CHECK-ENC: encoding: [0x3b,0xad,0xfc,0x42]
+aif.amoorg.w s10, a5, (s9)
+
+# CHECK-INST: aif.amoorl.d ra, t3, (zero)
+# CHECK-ENC: encoding: [0xbb,0x30,0xc0,0x41]
+aif.amoorl.d ra, t3, (zero)
+
+# CHECK-INST: aif.amoorl.w t5, a5, (a7)
+# CHECK-ENC: encoding: [0x3b,0xaf,0xf8,0x40]
+aif.amoorl.w t5, a5, (a7)
+
+# CHECK-INST: aif.amoswapg.d s7, sp, (sp)
+# CHECK-ENC: encoding: [0xbb,0x3b,0x21,0x0a]
+aif.amoswapg.d s7, sp, (sp)
+
+# CHECK-INST: aif.amoswapg.w a7, t3, (s9)
+# CHECK-ENC: encoding: [0xbb,0xa8,0xcc,0x0b]
+aif.amoswapg.w a7, t3, (s9)
+
+# CHECK-INST: aif.amoswapl.d sp, gp, (t5)
+# CHECK-ENC: encoding: [0x3b,0x31,0x3f,0x08]
+aif.amoswapl.d sp, gp, (t5)
+
+# CHECK-INST: aif.amoswapl.w s1, a7, (s9)
+# CHECK-ENC: encoding: [0xbb,0xa4,0x1c,0x09]
+aif.amoswapl.w s1, a7, (s9)
+
+# CHECK-INST: aif.amoxorg.d t4, s1, (s1)
+# CHECK-ENC: encoding: [0xbb,0xbe,0x94,0x22]
+aif.amoxorg.d t4, s1, (s1)
+
+# CHECK-INST: aif.amoxorg.w gp, a4, (sp)
+# CHECK-ENC: encoding: [0xbb,0x21,0xe1,0x22]
+aif.amoxorg.w gp, a4, (sp)
+
+# CHECK-INST: aif.amoxorl.d sp, a0, (a0)
+# CHECK-ENC: encoding: [0x3b,0x31,0xa5,0x20]
+aif.amoxorl.d sp, a0, (a0)
+
+# CHECK-INST: aif.amoxorl.w s1, a7, (s0)
+# CHECK-ENC: encoding: [0xbb,0x24,0x14,0x21]
+aif.amoxorl.w s1, a7, (fp)
+
+# CHECK-INST: aif.amoaddg.d a4, s9, (t1)
+# CHECK-ENC: encoding: [0x3b,0x37,0x93,0x03]
+aif.amoaddg.d a4, s9, 0(t1)
+
+# CHECK-INST: aif.amoaddg.w t1, s5, (t0)
+# CHECK-ENC: encoding: [0x3b,0xa3,0x52,0x03]
+aif.amoaddg.w t1, s5, 0(t0)
+
+# CHECK-INST: aif.amoaddl.d a4, s4, (a6)
+# CHECK-ENC: encoding: [0x3b,0x37,0x48,0x01]
+aif.amoaddl.d a4, s4, 0(a6)
+
+# CHECK-INST: aif.amoaddl.w tp, t2, (gp)
+# CHECK-ENC: encoding: [0x3b,0xa2,0x71,0x00]
+aif.amoaddl.w tp, t2, 0(gp)
+
+# CHECK-INST: aif.amoandg.d s2, a5, (a2)
+# CHECK-ENC: encoding: [0x3b,0x39,0xf6,0x62]
+aif.amoandg.d s2, a5, 0(a2)
+
+# CHECK-INST: aif.amoandg.w t0, s8, (s2)
+# CHECK-ENC: encoding: [0xbb,0x22,0x89,0x63]
+aif.amoandg.w t0, s8, 0(s2)
+
+# CHECK-INST: aif.amoandl.d sp, ra, (a4)
+# CHECK-ENC: encoding: [0x3b,0x31,0x17,0x60]
+aif.amoandl.d sp, ra, 0(a4)
+
+# CHECK-INST: aif.amoandl.w t5, s0, (gp)
+# CHECK-ENC: encoding: [0x3b,0xaf,0x81,0x60]
+aif.amoandl.w t5, s0, 0(gp)
+
+# CHECK-INST: aif.amocmpswapg.d s0, gp, (a3)
+# CHECK-ENC: encoding: [0x3b,0xb4,0x36,0xf2]
+aif.amocmpswapg.d fp, gp, 0(a3)
+
+# CHECK-INST: aif.amocmpswapg.w a5, tp, (s8)
+# CHECK-ENC: encoding: [0xbb,0x27,0x4c,0xf2]
+aif.amocmpswapg.w a5, tp, 0(s8)
+
+# CHECK-INST: aif.amocmpswapl.d t5, s6, (s1)
+# CHECK-ENC: encoding: [0x3b,0xbf,0x64,0xf1]
+aif.amocmpswapl.d t5, s6, 0(s1)
+
+# CHECK-INST: aif.amocmpswapl.w a7, s0, (sp)
+# CHECK-ENC: encoding: [0xbb,0x28,0x81,0xf0]
+aif.amocmpswapl.w a7, s0, 0(sp)
+
+# CHECK-INST: aif.amomaxg.d tp, s10, (a2)
+# CHECK-ENC: encoding: [0x3b,0x32,0xa6,0xa3]
+aif.amomaxg.d tp, s10, 0(a2)
+
+# CHECK-INST: aif.amomaxg.w a0, s6, (a1)
+# CHECK-ENC: encoding: [0x3b,0xa5,0x65,0xa3]
+aif.amomaxg.w a0, s6, 0(a1)
+
+# CHECK-INST: aif.amomaxl.d a6, s7, (s4)
+# CHECK-ENC: encoding: [0x3b,0x38,0x7a,0xa1]
+aif.amomaxl.d a6, s7, 0(s4)
+
+# CHECK-INST: aif.amomaxl.w s4, s3, (a7)
+# CHECK-ENC: encoding: [0x3b,0xaa,0x38,0xa1]
+aif.amomaxl.w s4, s3, 0(a7)
+
+# CHECK-INST: aif.amomaxug.d t0, s4, (t2)
+# CHECK-ENC: encoding: [0xbb,0xb2,0x43,0xe3]
+aif.amomaxug.d t0, s4, 0(t2)
+
+# CHECK-INST: aif.amomaxug.w s5, t5, (t2)
+# CHECK-ENC: encoding: [0xbb,0xaa,0xe3,0xe3]
+aif.amomaxug.w s5, t5, 0(t2)
+
+# CHECK-INST: aif.amomaxul.d t2, t2, (tp)
+# CHECK-ENC: encoding: [0xbb,0x33,0x72,0xe0]
+aif.amomaxul.d t2, t2, 0(tp)
+
+# CHECK-INST: aif.amomaxul.w t5, a2, (t4)
+# CHECK-ENC: encoding: [0x3b,0xaf,0xce,0xe0]
+aif.amomaxul.w t5, a2, 0(t4)
+
+# CHECK-INST: aif.amoming.d s0, t0, (s1)
+# CHECK-ENC: encoding: [0x3b,0xb4,0x54,0x82]
+aif.amoming.d fp, t0, 0(s1)
+
+# CHECK-INST: aif.amoming.w a1, s4, (t2)
+# CHECK-ENC: encoding: [0xbb,0xa5,0x43,0x83]
+aif.amoming.w a1, s4, 0(t2)
+
+# CHECK-INST: aif.amominl.d t0, a5, (t3)
+# CHECK-ENC: encoding: [0xbb,0x32,0xfe,0x80]
+aif.amominl.d t0, a5, 0(t3)
+
+# CHECK-INST: aif.amominl.w t3, s5, (gp)
+# CHECK-ENC: encoding: [0x3b,0xae,0x51,0x81]
+aif.amominl.w t3, s5, 0(gp)
+
+# CHECK-INST: aif.amominug.d s9, t1, (s3)
+# CHECK-ENC: encoding: [0xbb,0xbc,0x69,0xc2]
+aif.amominug.d s9, t1, 0(s3)
+
+# CHECK-INST: aif.amominug.w a4, s0, (gp)
+# CHECK-ENC: encoding: [0x3b,0xa7,0x81,0xc2]
+aif.amominug.w a4, fp, 0(gp)
+
+# CHECK-INST: aif.amominul.d ra, a6, (ra)
+# CHECK-ENC: encoding: [0xbb,0xb0,0x00,0xc1]
+aif.amominul.d ra, a6, 0(ra)
+
+# CHECK-INST: aif.amominul.w a1, a3, (s8)
+# CHECK-ENC: encoding: [0xbb,0x25,0xdc,0xc0]
+aif.amominul.w a1, a3, 0(s8)
+
+# CHECK-INST: aif.amoorg.d a5, a7, (a4)
+# CHECK-ENC: encoding: [0xbb,0x37,0x17,0x43]
+aif.amoorg.d a5, a7, 0(a4)
+
+# CHECK-INST: aif.amoorg.w s10, a5, (s9)
+# CHECK-ENC: encoding: [0x3b,0xad,0xfc,0x42]
+aif.amoorg.w s10, a5, 0(s9)
+
+# CHECK-INST: aif.amoorl.d ra, t3, (zero)
+# CHECK-ENC: encoding: [0xbb,0x30,0xc0,0x41]
+aif.amoorl.d ra, t3, 0(zero)
+
+# CHECK-INST: aif.amoorl.w t5, a5, (a7)
+# CHECK-ENC: encoding: [0x3b,0xaf,0xf8,0x40]
+aif.amoorl.w t5, a5, 0(a7)
+
+# CHECK-INST: aif.amoswapg.d s7, sp, (sp)
+# CHECK-ENC: encoding: [0xbb,0x3b,0x21,0x0a]
+aif.amoswapg.d s7, sp, 0(sp)
+
+# CHECK-INST: aif.amoswapg.w a7, t3, (s9)
+# CHECK-ENC: encoding: [0xbb,0xa8,0xcc,0x0b]
+aif.amoswapg.w a7, t3, 0(s9)
+
+# CHECK-INST: aif.amoswapl.d sp, gp, (t5)
+# CHECK-ENC: encoding: [0x3b,0x31,0x3f,0x08]
+aif.amoswapl.d sp, gp, 0(t5)
+
+# CHECK-INST: aif.amoswapl.w s1, a7, (s9)
+# CHECK-ENC: encoding: [0xbb,0xa4,0x1c,0x09]
+aif.amoswapl.w s1, a7, 0(s9)
+
+# CHECK-INST: aif.amoxorg.d t4, s1, (s1)
+# CHECK-ENC: encoding: [0xbb,0xbe,0x94,0x22]
+aif.amoxorg.d t4, s1, 0(s1)
+
+# CHECK-INST: aif.amoxorg.w gp, a4, (sp)
+# CHECK-ENC: encoding: [0xbb,0x21,0xe1,0x22]
+aif.amoxorg.w gp, a4, 0(sp)
+
+# CHECK-INST: aif.amoxorl.d sp, a0, (a0)
+# CHECK-ENC: encoding: [0x3b,0x31,0xa5,0x20]
+aif.amoxorl.d sp, a0, 0(a0)
+
+# CHECK-INST: aif.amoxorl.w s1, a7, (s0)
+# CHECK-ENC: encoding: [0xbb,0x24,0x14,0x21]
+aif.amoxorl.w s1, a7, 0(fp)
+
+#====----------------------------------------------------------------------===//
+# SIMD INT AMO local|global
+#====----------------------------------------------------------------------===//
+
+# CHECK-INST: aif.famoaddg.pi fa5, ft5, (a5)
+# CHECK-ENC: encoding: [0x8b,0xc7,0xf2,0x86]
+aif.famoaddg.pi fa5, ft5, (a5)
+
+# CHECK-INST: aif.famoaddl.pi fs3, ft1, (gp)
+# CHECK-ENC: encoding: [0x8b,0xc9,0x30,0x06]
+aif.famoaddl.pi fs3, ft1, (gp)
+
+# CHECK-INST: aif.famoandg.pi fs7, ft5, (s3)
+# CHECK-ENC: encoding: [0x8b,0xcb,0x32,0x97]
+aif.famoandg.pi fs7, ft5, (s3)
+
+# CHECK-INST: aif.famoandl.pi fs6, fs5, (a0)
+# CHECK-ENC: encoding: [0x0b,0xcb,0xaa,0x16]
+aif.famoandl.pi fs6, fs5, (a0)
+
+# CHECK-INST: aif.famomaxg.pi ft0, ft10, (s6)
+# CHECK-ENC: encoding: [0x0b,0x40,0x6f,0xb7]
+aif.famomaxg.pi ft0, ft10, (s6)
+
+# CHECK-INST: aif.famomaxg.ps fs1, fs9, (s7)
+# CHECK-ENC: encoding: [0x8b,0xc4,0x7c,0xa9]
+aif.famomaxg.ps fs1, fs9, (s7)
+
+# CHECK-INST: aif.famomaxl.pi ft11, ft6, (t5)
+# CHECK-ENC: encoding: [0x8b,0x4f,0xe3,0x37]
+aif.famomaxl.pi ft11, ft6, (t5)
+
+# CHECK-INST: aif.famomaxl.ps fs6, fs9, (zero)
+# CHECK-ENC: encoding: [0x0b,0xcb,0x0c,0x28]
+aif.famomaxl.ps fs6, fs9, (zero)
+
+# CHECK-INST: aif.famomaxug.pi ft9, fs1, (s5)
+# CHECK-ENC: encoding: [0x8b,0xce,0x54,0xc7]
+aif.famomaxug.pi ft9, fs1, (s5)
+
+# CHECK-INST: aif.famomaxul.pi ft11, fs3, (s4)
+# CHECK-ENC: encoding: [0x8b,0xcf,0x49,0x47]
+aif.famomaxul.pi ft11, fs3, (s4)
+
+# CHECK-INST: aif.famoming.pi fa5, ft6, (a7)
+# CHECK-ENC: encoding: [0x8b,0x47,0x13,0xaf]
+aif.famoming.pi fa5, ft6, (a7)
+
+# CHECK-INST: aif.famoming.ps ft2, ft8, (s0)
+# CHECK-ENC: encoding: [0x0b,0x41,0x8e,0xb0]
+aif.famoming.ps ft2, ft8, (fp)
+
+# CHECK-INST: aif.famominl.pi ft6, fs2, (a0)
+# CHECK-ENC: encoding: [0x0b,0x43,0xa9,0x2e]
+aif.famominl.pi ft6, fs2, (a0)
+
+# CHECK-INST: aif.famominl.ps ft5, ft4, (s3)
+# CHECK-ENC: encoding: [0x8b,0x42,0x32,0x31]
+aif.famominl.ps ft5, ft4, (s3)
+
+# CHECK-INST: aif.famominug.pi ft7, fs10, (s1)
+# CHECK-ENC: encoding: [0x8b,0x43,0x9d,0xbe]
+aif.famominug.pi ft7, fs10, (s1)
+
+# CHECK-INST: aif.famominul.pi fa6, fs10, (tp)
+# CHECK-ENC: encoding: [0x0b,0x48,0x4d,0x3e]
+aif.famominul.pi fa6, fs10, (tp)
+
+# CHECK-INST: aif.famoorg.pi ft9, fs8, (gp)
+# CHECK-ENC: encoding: [0x8b,0x4e,0x3c,0x9e]
+aif.famoorg.pi ft9, fs8, (gp)
+
+# CHECK-INST: aif.famoorl.pi fa0, ft8, (s5)
+# CHECK-ENC: encoding: [0x0b,0x45,0x5e,0x1f]
+aif.famoorl.pi fa0, ft8, (s5)
+
+# CHECK-INST: aif.famoswapg.pi fs5, fs9, (s10)
+# CHECK-ENC: encoding: [0x8b,0xca,0xac,0x8f]
+aif.famoswapg.pi fs5, fs9, (s10)
+
+# CHECK-INST: aif.famoswapl.pi fs0, fa4, (s10)
+# CHECK-ENC: encoding: [0x0b,0x44,0xa7,0x0f]
+aif.famoswapl.pi fs0, fa4, (s10)
+
+# CHECK-INST: aif.famoxorg.pi fs7, ft9, (t5)
+# CHECK-ENC: encoding: [0x8b,0xcb,0xee,0xa7]
+aif.famoxorg.pi fs7, ft9, (t5)
+
+# CHECK-INST: aif.famoxorl.pi fa7, fs7, (a4)
+# CHECK-ENC: encoding: [0x8b,0xc8,0xeb,0x26]
+aif.famoxorl.pi fa7, fs7, (a4)
+
+#====----------------------------------------------------------------------===//
+# SIMD global
+#====----------------------------------------------------------------------===//
+
+# CHECK-INST: aif.fgbg.ps fs7, fs6, (s0)
+# CHECK-ENC: encoding: [0x8b,0x7b,0x8b,0x82]
+aif.fgbg.ps fs7, fs6, (s0)
+
+# CHECK-INST: aif.fghg.ps fa4, fs8, (s6)
+# CHECK-ENC: encoding: [0x0b,0x77,0x6c,0x8b]
+aif.fghg.ps fa4, fs8, (s6)
+
+# CHECK-INST: aif.fgwg.ps fa6, fs6, (tp)
+# CHECK-ENC: encoding: [0x0b,0x78,0x4b,0x92]
+aif.fgwg.ps fa6, fs6, (tp)
+
+# CHECK-INST: aif.flwg.ps fs10, (a4)
+# CHECK-ENC: encoding: [0x0b,0x7d,0x07,0x12]
+aif.flwg.ps fs10, (a4)
+
+# CHECK-INST: aif.fscbg.ps fa6, fs5, (t0)
+# CHECK-ENC: encoding: [0x0b,0xf8,0x5a,0xc2]
+aif.fscbg.ps fa6, fs5, (t0)
+
+# CHECK-INST: aif.fschg.ps fa3, fs9, (s8)
+# CHECK-ENC: encoding: [0x8b,0xf6,0x8c,0xcb]
+aif.fschg.ps fa3, fs9, (s8)
+
+# CHECK-INST: aif.fscwg.ps ft4, fs9, (s0)
+# CHECK-ENC: encoding: [0x0b,0xf2,0x8c,0xd2]
+aif.fscwg.ps ft4, fs9, (s0)
+
+# CHECK-INST: aif.fswg.ps fa5, (t5)
+# CHECK-ENC: encoding: [0x8b,0x77,0x0f,0x52]
+aif.fswg.ps fa5, (t5)
+
+#====----------------------------------------------------------------------===//
+# SIMD local
+#====----------------------------------------------------------------------===//
+
+# CHECK-INST: aif.fgbl.ps fs3, ft11, (ra)
+# CHECK-ENC: encoding: [0x8b,0xf9,0x1f,0x80]
+aif.fgbl.ps fs3, ft11, (ra)
+
+# CHECK-INST: aif.fghl.ps ft1, fs2, (s5)
+# CHECK-ENC: encoding: [0x8b,0x70,0x59,0x89]
+aif.fghl.ps ft1, fs2, (s5)
+
+# CHECK-INST: aif.fgwl.ps ft6, fs2, (gp)
+# CHECK-ENC: encoding: [0x0b,0x73,0x39,0x90]
+aif.fgwl.ps ft6, fs2, (gp)
+
+# CHECK-INST: aif.flwl.ps fs1, (t2)
+# CHECK-ENC: encoding: [0x8b,0xf4,0x03,0x10]
+aif.flwl.ps fs1, (t2)
+
+# CHECK-INST: aif.fscbl.ps ft5, ft7, (s5)
+# CHECK-ENC: encoding: [0x8b,0xf2,0x53,0xc1]
+aif.fscbl.ps ft5, ft7, (s5)
+
+# CHECK-INST: aif.fschl.ps fs8, ft1, (t1)
+# CHECK-ENC: encoding: [0x0b,0xfc,0x60,0xc8]
+aif.fschl.ps fs8, ft1, (t1)
+
+# CHECK-INST: aif.fscwl.ps fs0, ft11, (ra)
+# CHECK-ENC: encoding: [0x0b,0xf4,0x1f,0xd0]
+aif.fscwl.ps fs0, ft11, (ra)
+
+# CHECK-INST: aif.fswl.ps ft7, (t2)
+# CHECK-ENC: encoding: [0x8b,0xf3,0x03,0x50]
+aif.fswl.ps ft7, (t2)
+
+#====----------------------------------------------------------------------===//
+# Scalar global
+#====----------------------------------------------------------------------===//
+
+# CHECK-INST: aif.sbg a6, (t4)
+# CHECK-ENC: encoding: [0x3b,0xb0,0x0e,0x13]
+aif.sbg a6, (t4)
+
+# CHECK-INST: aif.shg sp, (s6)
+# CHECK-ENC: encoding: [0x3b,0x30,0x2b,0x1a]
+aif.shg sp, (s6)
+
+# CHECK-INST: aif.sbg a6, (t4)
+# CHECK-ENC: encoding: [0x3b,0xb0,0x0e,0x13]
+aif.sbg a6, 0(t4)
+
+# CHECK-INST: aif.shg sp, (s6)
+# CHECK-ENC: encoding: [0x3b,0x30,0x2b,0x1a]
+aif.shg sp, 0(s6)
+
+#====----------------------------------------------------------------------===//
+# Scalar local
+#====----------------------------------------------------------------------===//
+
+# CHECK-INST: aif.sbl a3, (s0)
+# CHECK-ENC: encoding: [0x3b,0x30,0xd4,0x10]
+aif.sbl a3, (fp)
+
+# CHECK-INST: aif.shl s0, (s10)
+# CHECK-ENC: encoding: [0x3b,0x30,0x8d,0x18]
+aif.shl fp, (s10)
+
+# CHECK-INST: aif.sbl a3, (s0)
+# CHECK-ENC: encoding: [0x3b,0x30,0xd4,0x10]
+aif.sbl a3, 0(fp)
+
+# CHECK-INST: aif.shl s0, (s10)
+# CHECK-ENC: encoding: [0x3b,0x30,0x8d,0x18]
+aif.shl fp, 0(s10)
+
+#====----------------------------------------------------------------------===//
+# CSRs
+#====----------------------------------------------------------------------===//
+
+# CHECK-INST: csrwi aif.matp, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x0f,0x7c]
+csrwi aif.matp, 0x1f
+
+# CHECK-INST: csrwi aif.minstmask, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xdf,0x7c]
+csrwi aif.minstmask, 0x1f
+
+# CHECK-INST: csrwi aif.minstmatch, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xef,0x7c]
+csrwi aif.minstmatch, 0x1f
+
+# CHECK-INST: csrwi aif.cache_invalidate, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x0f,0x7d]
+csrwi aif.cache_invalidate, 0x1f
+
+# CHECK-INST: csrwi aif.menable_shadows, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x2f,0x7d]
+csrwi aif.menable_shadows, 0x1f
+
+# CHECK-INST: csrwi aif.excl_mode, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x3f,0x7d]
+csrwi aif.excl_mode, 0x1f
+
+# CHECK-INST: csrwi aif.mbusaddr, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x5f,0x7d]
+csrwi aif.mbusaddr, 0x1f
+
+# CHECK-INST: csrwi aif.mcache_control, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x0f,0x7e]
+csrwi aif.mcache_control, 0x1f
+
+# CHECK-INST: csrwi aif.evict_sw, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x9f,0x7f]
+csrwi aif.evict_sw, 0x1f
+
+# CHECK-INST: csrwi aif.flush_sw, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xbf,0x7f]
+csrwi aif.flush_sw, 0x1f
+
+# CHECK-INST: csrwi aif.lock_sw, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xdf,0x7f]
+csrwi aif.lock_sw, 0x1f
+
+# CHECK-INST: csrwi aif.unlock_sw, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xff,0x7f]
+csrwi aif.unlock_sw, 0x1f
+
+# CHECK-INST: csrwi aif.tensor_reduce, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x0f,0x80]
+csrwi aif.tensor_reduce, 0x1f
+
+# CHECK-INST: csrwi aif.tensor_fma, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x1f,0x80]
+csrwi aif.tensor_fma, 0x1f
+
+# CHECK-INST: csrwi aif.tensor_conv_size, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x2f,0x80]
+csrwi aif.tensor_conv_size, 0x1f
+
+# CHECK-INST: csrwi aif.tensor_conv_ctrl, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x3f,0x80]
+csrwi aif.tensor_conv_ctrl, 0x1f
+
+# CHECK-INST: csrwi aif.tensor_coop, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x4f,0x80]
+csrwi aif.tensor_coop, 0x1f
+
+# CHECK-INST: csrwi aif.tensor_mask, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x5f,0x80]
+csrwi aif.tensor_mask, 0x1f
+
+# CHECK-INST: csrwi aif.tensor_quant, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x6f,0x80]
+csrwi aif.tensor_quant, 0x1f
+
+# CHECK-INST: csrwi aif.tex_send, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x7f,0x80]
+csrwi aif.tex_send, 0x1f
+
+# CHECK-INST: csrwi aif.tensor_error, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x8f,0x80]
+csrwi aif.tensor_error, 0x1f
+
+# CHECK-INST: csrwi aif.ucache_control, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x0f,0x81]
+csrwi aif.ucache_control, 0x1f
+
+# CHECK-INST: csrwi aif.prefetch_va, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xff,0x81]
+csrwi aif.prefetch_va, 0x1f
+
+# CHECK-INST: csrwi aif.flb, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x0f,0x82]
+csrwi aif.flb, 0x1f
+
+# CHECK-INST: csrwi aif.fcc, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x1f,0x82]
+csrwi aif.fcc, 0x1f
+
+# CHECK-INST: csrwi aif.stall, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x2f,0x82]
+csrwi aif.stall, 0x1f
+
+# CHECK-INST: csrwi aif.tensor_wait, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x0f,0x83]
+csrwi aif.tensor_wait, 0x1f
+
+# CHECK-INST: csrwi aif.tensor_load, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xff,0x83]
+csrwi aif.tensor_load, 0x1f
+
+# CHECK-INST: csrwi aif.gsc_progress, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x0f,0x84]
+csrwi aif.gsc_progress, 0x1f
+
+# CHECK-INST: csrwi aif.tensor_load_l2, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xff,0x85]
+csrwi aif.tensor_load_l2, 0x1f
+
+# CHECK-INST: csrwi aif.tensor_store, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xff,0x87]
+csrwi aif.tensor_store, 0x1f
+
+# CHECK-INST: csrwi aif.evict_va, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xff,0x89]
+csrwi aif.evict_va, 0x1f
+
+# CHECK-INST: csrwi aif.flush_va, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xff,0x8b]
+csrwi aif.flush_va, 0x1f
+
+# CHECK-INST: csrwi aif.validation0, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x0f,0x8d]
+csrwi aif.validation0, 0x1f
+
+# CHECK-INST: csrwi aif.validation1, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x1f,0x8d]
+csrwi aif.validation1, 0x1f
+
+# CHECK-INST: csrwi aif.validation2, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x2f,0x8d]
+csrwi aif.validation2, 0x1f
+
+# CHECK-INST: csrwi aif.validation3, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x3f,0x8d]
+csrwi aif.validation3, 0x1f
+
+# CHECK-INST: csrwi aif.lock_va, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xff,0x8d]
+csrwi aif.lock_va, 0x1f
+
+# CHECK-INST: csrwi aif.unlock_va, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xff,0x8f]
+csrwi aif.unlock_va, 0x1f
+
+# CHECK-INST: csrwi aif.portctrl0, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xcf,0x9c]
+csrwi aif.portctrl0, 0x1f
+
+# CHECK-INST: csrwi aif.portctrl1, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xdf,0x9c]
+csrwi aif.portctrl1, 0x1f
+
+# CHECK-INST: csrwi aif.portctrl2, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xef,0x9c]
+csrwi aif.portctrl2, 0x1f
+
+# CHECK-INST: csrwi aif.portctrl3, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xff,0x9c]
+csrwi aif.portctrl3, 0x1f
+
+# CHECK-INST: csrwi aif.fccnb, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x0f,0xcc]
+csrwi aif.fccnb, 0x1f
+
+# CHECK-INST: csrwi aif.porthead0, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x8f,0xcc]
+csrwi aif.porthead0, 0x1f
+
+# CHECK-INST: csrwi aif.porthead1, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x9f,0xcc]
+csrwi aif.porthead1, 0x1f
+
+# CHECK-INST: csrwi aif.porthead2, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xaf,0xcc]
+csrwi aif.porthead2, 0x1f
+
+# CHECK-INST: csrwi aif.porthead3, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xbf,0xcc]
+csrwi aif.porthead3, 0x1f
+
+# CHECK-INST: csrwi aif.portheadnb0, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xcf,0xcc]
+csrwi aif.portheadnb0, 0x1f
+
+# CHECK-INST: csrwi aif.portheadnb1, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xdf,0xcc]
+csrwi aif.portheadnb1, 0x1f
+
+# CHECK-INST: csrwi aif.portheadnb2, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xef,0xcc]
+csrwi aif.portheadnb2, 0x1f
+
+# CHECK-INST: csrwi aif.portheadnb3, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0xff,0xcc]
+csrwi aif.portheadnb3, 0x1f
+
+# CHECK-INST: csrwi aif.hartid, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x0f,0xcd]
+csrwi aif.hartid, 0x1f
+
+# CHECK-INST: csrwi aif.dcache_debug, 31
+# CHECK-ENC: encoding: [0x73,0xd0,0x0f,0xfc]
+csrwi aif.dcache_debug, 0x1f
diff --git a/llvm/test/MC/RISCV/xaifet-simd-valid.s b/llvm/test/MC/RISCV/xaifet-simd-valid.s
new file mode 100644
index 0000000000000..5291ebeca65b3
--- /dev/null
+++ b/llvm/test/MC/RISCV/xaifet-simd-valid.s
@@ -0,0 +1,535 @@
+# XAIFET - AI Foundry ET SIMD instructions
+
+# RUN: llvm-mc --arch=riscv64 -mattr=+xaifet --show-encoding %s | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+
+# CHECK-INST: aif.bitmixb s7, gp, gp
+# CHECK-ENC: encoding: [0xbb,0xfb,0x31,0x80]
+aif.bitmixb s7, gp, gp
+
+# CHECK-INST: aif.cubefaceidx.ps fa0, fs9, ft9
+# CHECK-ENC: encoding: [0x7b,0x95,0xdc,0x89]
+aif.cubefaceidx.ps fa0, fs9, ft9
+
+# CHECK-INST: aif.cubeface.ps ft9, fa3, ft10
+# CHECK-ENC: encoding: [0xfb,0x8e,0xe6,0x89]
+aif.cubeface.ps ft9, fa3, ft10
+
+# CHECK-INST: aif.cubesgnsc.ps ft9, ft8, fs9
+# CHECK-ENC: encoding: [0xfb,0x2e,0x9e,0x89]
+aif.cubesgnsc.ps ft9, ft8, fs9
+
+# CHECK-INST: aif.cubesgntc.ps fs2, ft6, fa6
+# CHECK-ENC: encoding: [0x7b,0x39,0x03,0x89]
+aif.cubesgntc.ps fs2, ft6, fa6
+
+#====----------------------------------------------------------------------===//
+# SIMD FP|INT instructions
+#====----------------------------------------------------------------------===//
+
+# CHECK-INST: aif.faddi.pi fa4, ft1, -96
+# CHECK-ENC: encoding: [0x3f,0x87,0x00,0xec]
+aif.faddi.pi fa4, ft1, -96
+
+# CHECK-INST: aif.fadd.pi fs10, fa5, fs8
+# CHECK-ENC: encoding: [0x7b,0x8d,0x87,0x07]
+aif.fadd.pi fs10, fa5, fs8
+
+# CHECK-INST: aif.fadd.ps fs0, ft0, fs4, rtz
+# CHECK-ENC: encoding: [0x7b,0x14,0x40,0x01]
+aif.fadd.ps fs0, ft0, fs4, rtz
+
+# CHECK-INST: aif.fandi.pi fa7, fs1, 16
+# CHECK-ENC: encoding: [0xbf,0x98,0x04,0x05]
+aif.fandi.pi fa7, fs1, 16
+
+# CHECK-INST: aif.fand.pi ft2, fs8, fa1
+# CHECK-ENC: encoding: [0x7b,0x71,0xbc,0x06]
+aif.fand.pi ft2, fs8, fa1
+
+# CHECK-INST: aif.fbci.pi fs9, 1015523
+# CHECK-ENC: encoding: [0xdf,0x3c,0xee,0xf7]
+aif.fbci.pi fs9, 1015523
+
+# CHECK-INST: aif.fbci.ps fs9, 946477
+# CHECK-ENC: encoding: [0x9f,0xdc,0x12,0xe7]
+aif.fbci.ps fs9, 946477
+
+# CHECK-INST: aif.fbcx.ps fa3, s3
+# CHECK-ENC: encoding: [0x8b,0xb6,0x09,0x00]
+aif.fbcx.ps fa3, s3
+
+# CHECK-INST: aif.fbc.ps fs0, 1529(s9)
+# CHECK-ENC: encoding: [0x0b,0x84,0x9c,0x5f]
+aif.fbc.ps fs0, 1529(s9)
+
+# CHECK-INST: aif.fclass.ps fs0, fs8
+# CHECK-ENC: encoding: [0x7b,0x14,0x0c,0xe0]
+aif.fclass.ps fs0, fs8
+
+# CHECK-INST: aif.fcmovm.ps ft5, fa7, fs6
+# CHECK-ENC: encoding: [0xf7,0x82,0x68,0x01]
+aif.fcmovm.ps ft5, fa7, fs6
+
+# CHECK-INST: aif.fcmov.ps fs11, ft1, ft8, fa1
+# CHECK-ENC: encoding: [0xbf,0xad,0xc0,0x5d]
+aif.fcmov.ps fs11, ft1, ft8, fa1
+
+# CHECK-INST: aif.fcvt.f10.ps fa2, ft1
+# CHECK-ENC: encoding: [0x7b,0x86,0xb0,0xd8]
+aif.fcvt.f10.ps fa2, ft1
+
+# CHECK-INST: aif.fcvt.f11.ps fa0, ft4
+# CHECK-ENC: encoding: [0x7b,0x05,0x82,0xd8]
+aif.fcvt.f11.ps fa0, ft4
+
+# CHECK-INST: aif.fcvt.f16.ps ft1, fa2
+# CHECK-ENC: encoding: [0xfb,0x00,0x96,0xd8]
+aif.fcvt.f16.ps ft1, fa2
+
+# CHECK-INST: aif.fcvt.ps.f10 ft5, fa0
+# CHECK-ENC: encoding: [0xfb,0x02,0x85,0xd0]
+aif.fcvt.ps.f10 ft5, fa0
+
+# CHECK-INST: aif.fcvt.ps.f11 fa0, fa6
+# CHECK-ENC: encoding: [0x7b,0x05,0x98,0xd0]
+aif.fcvt.ps.f11 fa0, fa6
+
+# CHECK-INST: aif.fcvt.ps.f16 fa4, fs0
+# CHECK-ENC: encoding: [0x7b,0x07,0xa4,0xd0]
+aif.fcvt.ps.f16 fa4, fs0
+
+# CHECK-INST: aif.fcvt.ps.pw fs0, ft1, rtz
+# CHECK-ENC: encoding: [0x7b,0x94,0x00,0xd0]
+aif.fcvt.ps.pw fs0, ft1, rtz
+
+# CHECK-INST: aif.fcvt.ps.pwu ft8, ft0, rtz
+# CHECK-ENC: encoding: [0x7b,0x1e,0x10,0xd0]
+aif.fcvt.ps.pwu ft8, ft0, rtz
+
+# CHECK-INST: aif.fcvt.ps.rast ft7, fa0
+# CHECK-ENC: encoding: [0xfb,0x03,0x25,0xd0]
+aif.fcvt.ps.rast ft7, fa0
+
+# CHECK-INST: aif.fcvt.ps.sn16 ft11, fa2
+# CHECK-ENC: encoding: [0xfb,0x0f,0x96,0xd1]
+aif.fcvt.ps.sn16 ft11, fa2
+
+# CHECK-INST: aif.fcvt.ps.sn8 fs1, ft2
+# CHECK-ENC: encoding: [0xfb,0x04,0xb1,0xd1]
+aif.fcvt.ps.sn8 fs1, ft2
+
+# CHECK-INST: aif.fcvt.ps.un10 fs0, fs11
+# CHECK-ENC: encoding: [0x7b,0x84,0x2d,0xd1]
+aif.fcvt.ps.un10 fs0, fs11
+
+# CHECK-INST: aif.fcvt.ps.un16 fa7, ft5
+# CHECK-ENC: encoding: [0xfb,0x88,0x12,0xd1]
+aif.fcvt.ps.un16 fa7, ft5
+
+# CHECK-INST: aif.fcvt.ps.un2 fs0, fa7
+# CHECK-ENC: encoding: [0x7b,0x84,0x78,0xd1]
+aif.fcvt.ps.un2 fs0, fa7
+
+# CHECK-INST: aif.fcvt.ps.un24 ft6, ft1
+# CHECK-ENC: encoding: [0x7b,0x83,0x00,0xd1]
+aif.fcvt.ps.un24 ft6, ft1
+
+# CHECK-INST: aif.fcvt.ps.un8 fa3, fa4
+# CHECK-ENC: encoding: [0xfb,0x06,0x37,0xd1]
+aif.fcvt.ps.un8 fa3, fa4
+
+# CHECK-INST: aif.fcvt.pwu.ps ft10, ft1, rup
+# CHECK-ENC: encoding: [0x7b,0xbf,0x10,0xc0]
+aif.fcvt.pwu.ps ft10, ft1, rup
+
+# CHECK-INST: aif.fcvt.pw.ps fs6, ft5, rup
+# CHECK-ENC: encoding: [0x7b,0xbb,0x02,0xc0]
+aif.fcvt.pw.ps fs6, ft5, rup
+
+# CHECK-INST: aif.fcvt.rast.ps ft11, fs7
+# CHECK-ENC: encoding: [0xfb,0x8f,0x2b,0xc0]
+aif.fcvt.rast.ps ft11, fs7
+
+# CHECK-INST: aif.fcvt.sn16.ps ft1, fs7
+# CHECK-ENC: encoding: [0xfb,0x80,0x9b,0xd9]
+aif.fcvt.sn16.ps ft1, fs7
+
+# CHECK-INST: aif.fcvt.sn8.ps fs3, ft5
+# CHECK-ENC: encoding: [0xfb,0x89,0xb2,0xd9]
+aif.fcvt.sn8.ps fs3, ft5
+
+# CHECK-INST: aif.fcvt.un10.ps ft5, fa6
+# CHECK-ENC: encoding: [0xfb,0x02,0x28,0xd9]
+aif.fcvt.un10.ps ft5, fa6
+
+# CHECK-INST: aif.fcvt.un16.ps fs9, ft6
+# CHECK-ENC: encoding: [0xfb,0x0c,0x13,0xd9]
+aif.fcvt.un16.ps fs9, ft6
+
+# CHECK-INST: aif.fcvt.un24.ps fs8, ft8
+# CHECK-ENC: encoding: [0x7b,0x0c,0x0e,0xd9]
+aif.fcvt.un24.ps fs8, ft8
+
+# CHECK-INST: aif.fcvt.un2.ps fa0, fa3
+# CHECK-ENC: encoding: [0x7b,0x85,0x76,0xd9]
+aif.fcvt.un2.ps fa0, fa3
+
+# CHECK-INST: aif.fcvt.un8.ps fa0, ft2
+# CHECK-ENC: encoding: [0x7b,0x05,0x31,0xd9]
+aif.fcvt.un8.ps fa0, ft2
+
+# CHECK-INST: aif.fdivu.pi fa1, fa5, fa2
+# CHECK-ENC: encoding: [0xfb,0x95,0xc7,0x1e]
+aif.fdivu.pi fa1, fa5, fa2
+
+# CHECK-INST: aif.fdiv.pi ft3, fa0, fs4
+# CHECK-ENC: encoding: [0xfb,0x01,0x45,0x1f]
+aif.fdiv.pi ft3, fa0, fs4
+
+# CHECK-INST: aif.fdiv.ps fs10, ft5, fs11, rdn
+# CHECK-ENC: encoding: [0x7b,0xad,0xb2,0x19]
+aif.fdiv.ps fs10, ft5, fs11, rdn
+
+# CHECK-INST: aif.feqm.ps m4, ft5, ft8
+# CHECK-ENC: encoding: [0x7b,0xe2,0xc2,0xa1]
+aif.feqm.ps m4, ft5, ft8
+
+# CHECK-INST: aif.feq.pi ft10, fa1, fs0
+# CHECK-ENC: encoding: [0x7b,0xaf,0x85,0xa6]
+aif.feq.pi ft10, fa1, fs0
+
+# CHECK-INST: aif.feq.ps fa5, ft4, fs2
+# CHECK-ENC: encoding: [0xfb,0x27,0x22,0xa1]
+aif.feq.ps fa5, ft4, fs2
+
+# CHECK-INST: aif.fexp.ps fs10, ft3
+# CHECK-ENC: encoding: [0x7b,0x8d,0x41,0x58]
+aif.fexp.ps fs10, ft3
+
+# CHECK-INST: aif.flog.ps fa0, fs10
+# CHECK-ENC: encoding: [0x7b,0x05,0x3d,0x58]
+aif.flog.ps fa0, fs10
+
+# CHECK-INST: aif.ffrc.ps fs9, ft8
+# CHECK-ENC: encoding: [0xfb,0x0c,0x2e,0x58]
+aif.ffrc.ps fs9, ft8
+
+# CHECK-INST: aif.fg32b.ps fa2, a0, (s0)
+# CHECK-ENC: encoding: [0x0b,0x16,0x85,0x08]
+aif.fg32b.ps fa2, a0, (s0)
+
+# CHECK-INST: aif.fg32h.ps ft10, s6, (s9)
+# CHECK-ENC: encoding: [0x0b,0x1f,0x9b,0x11]
+aif.fg32h.ps ft10, s6, (s9)
+
+# CHECK-INST: aif.fg32w.ps fs5, ra, (a0)
+# CHECK-ENC: encoding: [0x8b,0x9a,0xa0,0x20]
+aif.fg32w.ps fs5, ra, (a0)
+
+# CHECK-INST: aif.fgb.ps fs11, ft7, (s4)
+# CHECK-ENC: encoding: [0x8b,0x9d,0x43,0x49]
+aif.fgb.ps fs11, ft7, (s4)
+
+# CHECK-INST: aif.fgh.ps ft3, ft7, (t5)
+# CHECK-ENC: encoding: [0x8b,0x91,0xe3,0x51]
+aif.fgh.ps ft3, ft7, (t5)
+
+# CHECK-INST: aif.fgw.ps fs10, fa7, (s3)
+# CHECK-ENC: encoding: [0x0b,0x9d,0x38,0x61]
+aif.fgw.ps fs10, fa7, (s3)
+
+# CHECK-INST: aif.flem.ps m6, ft4, ft3
+# CHECK-ENC: encoding: [0x7b,0x43,0x32,0xa0]
+aif.flem.ps m6, ft4, ft3
+
+# CHECK-INST: aif.fle.pi ft2, fs3, fa7
+# CHECK-ENC: encoding: [0x7b,0x81,0x19,0xa7]
+aif.fle.pi ft2, fs3, fa7
+
+# CHECK-INST: aif.fle.ps ft9, fs11, fa1
+# CHECK-ENC: encoding: [0xfb,0x8e,0xbd,0xa0]
+aif.fle.ps ft9, fs11, fa1
+
+# CHECK-INST: aif.flq2 fa5, -2020(sp)
+# CHECK-ENC: encoding: [0x87,0x57,0xc1,0x81]
+aif.flq2 fa5, -2020(sp)
+
+# CHECK-INST: aif.fltm.pi m0, ft3, fs1
+# CHECK-ENC: encoding: [0x7b,0x80,0x91,0x3e]
+aif.fltm.pi m0, ft3, fs1
+
+# CHECK-INST: aif.fltm.ps m6, ft2, fa3
+# CHECK-ENC: encoding: [0x7b,0x53,0xd1,0xa0]
+aif.fltm.ps m6, ft2, fa3
+
+# CHECK-INST: aif.fltu.pi ft5, fa1, fs10
+# CHECK-ENC: encoding: [0xfb,0xb2,0xa5,0xa7]
+aif.fltu.pi ft5, fa1, fs10
+
+# CHECK-INST: aif.flt.pi ft11, fa4, fs8
+# CHECK-ENC: encoding: [0xfb,0x1f,0x87,0xa7]
+aif.flt.pi ft11, fa4, fs8
+
+# CHECK-INST: aif.flt.ps fs11, fs3, fs5
+# CHECK-ENC: encoding: [0xfb,0x9d,0x59,0xa1]
+aif.flt.ps fs11, fs3, fs5
+
+# CHECK-INST: aif.flw.ps ft9, 1224(s5)
+# CHECK-ENC: encoding: [0x8b,0xae,0x8a,0x4c]
+aif.flw.ps ft9, 1224(s5)
+
+# CHECK-INST: aif.fmadd.ps fs0, fs2, ft8, ft8, rmm
+# CHECK-ENC: encoding: [0x5b,0x44,0xc9,0xe1]
+aif.fmadd.ps fs0, fs2, ft8, ft8, rmm
+
+# CHECK-INST: aif.fmaxu.pi ft10, fs3, fs11
+# CHECK-ENC: encoding: [0x7b,0xbf,0xb9,0x2f]
+aif.fmaxu.pi ft10, fs3, fs11
+
+# CHECK-INST: aif.fmax.pi ft3, fs1, fs6
+# CHECK-ENC: encoding: [0xfb,0x91,0x64,0x2f]
+aif.fmax.pi ft3, fs1, fs6
+
+# CHECK-INST: aif.fmax.ps fa0, fs2, ft3
+# CHECK-ENC: encoding: [0x7b,0x15,0x39,0x28]
+aif.fmax.ps fa0, fs2, ft3
+
+# CHECK-INST: aif.fminu.pi ft5, ft2, ft2
+# CHECK-ENC: encoding: [0xfb,0x22,0x21,0x2e]
+aif.fminu.pi ft5, ft2, ft2
+
+# CHECK-INST: aif.fmin.pi fs10, fs10, fs3
+# CHECK-ENC: encoding: [0x7b,0x0d,0x3d,0x2f]
+aif.fmin.pi fs10, fs10, fs3
+
+# CHECK-INST: aif.fmin.ps fa1, ft5, ft5
+# CHECK-ENC: encoding: [0xfb,0x85,0x52,0x28]
+aif.fmin.ps fa1, ft5, ft5
+
+# CHECK-INST: aif.fmsub.ps fs0, fs7, fs6, ft3, rmm
+# CHECK-ENC: encoding: [0x5b,0xc4,0x6b,0x1b]
+aif.fmsub.ps fs0, fs7, fs6, ft3, rmm
+
+# CHECK-INST: aif.fmulhu.pi ft6, fs7, fs4
+# CHECK-ENC: encoding: [0x7b,0xa3,0x4b,0x17]
+aif.fmulhu.pi ft6, fs7, fs4
+
+# CHECK-INST: aif.fmulh.pi fa3, fa3, fs1
+# CHECK-ENC: encoding: [0xfb,0x96,0x96,0x16]
+aif.fmulh.pi fa3, fa3, fs1
+
+# CHECK-INST: aif.fmul.pi ft4, ft7, ft4
+# CHECK-ENC: encoding: [0x7b,0x82,0x43,0x16]
+aif.fmul.pi ft4, ft7, ft4
+
+# CHECK-INST: aif.fmul.ps fa5, fa2, fs10, rtz
+# CHECK-ENC: encoding: [0xfb,0x17,0xa6,0x11]
+aif.fmul.ps fa5, fa2, fs10, rtz
+
+# CHECK-INST: aif.fmvs.x.ps s0, fs0, 6
+# CHECK-ENC: encoding: [0x7b,0x24,0x64,0xe0]
+aif.fmvs.x.ps fp, fs0, 6
+
+# CHECK-INST: aif.fmvz.x.ps a5, ft6, 6
+# CHECK-ENC: encoding: [0xfb,0x07,0x63,0xe0]
+aif.fmvz.x.ps a5, ft6, 6
+
+# CHECK-INST: aif.fnmadd.ps ft10, ft8, fs5, fs3, rdn
+# CHECK-ENC: encoding: [0x5b,0x2f,0x5e,0x9f]
+aif.fnmadd.ps ft10, ft8, fs5, fs3, rdn
+
+# CHECK-INST: aif.fnmsub.ps ft0, ft11, fs7, fa5, rtz
+# CHECK-ENC: encoding: [0x5b,0x90,0x7f,0x7d]
+aif.fnmsub.ps ft0, ft11, fs7, fa5, rtz
+
+# CHECK-INST: aif.fnot.pi fs10, fs6
+# CHECK-ENC: encoding: [0x7b,0x2d,0x0b,0x06]
+aif.fnot.pi fs10, fs6
+
+# CHECK-INST: aif.for.pi ft10, fa0, fa4
+# CHECK-ENC: encoding: [0x7b,0x6f,0xe5,0x06]
+aif.for.pi ft10, fa0, fa4
+
+# CHECK-INST: aif.fpackrepb.pi ft8, fs11
+# CHECK-ENC: encoding: [0x7b,0x8e,0x0d,0x26]
+aif.fpackrepb.pi ft8, fs11
+
+# CHECK-INST: aif.fpackreph.pi ft2, ft10
+# CHECK-ENC: encoding: [0x7b,0x11,0x0f,0x26]
+aif.fpackreph.pi ft2, ft10
+
+# CHECK-INST: aif.frcp_fix.rast ft3, fs0, fa1
+# CHECK-ENC: encoding: [0xfb,0x01,0xb4,0x30]
+aif.frcp_fix.rast ft3, fs0, fa1
+
+# CHECK-INST: aif.frcp.ps ft11, fs2
+# CHECK-ENC: encoding: [0xfb,0x0f,0x79,0x58]
+aif.frcp.ps ft11, fs2
+
+# CHECK-INST: aif.fremu.pi ft4, ft4, ft1
+# CHECK-ENC: encoding: [0x7b,0x32,0x12,0x1e]
+aif.fremu.pi ft4, ft4, ft1
+
+# CHECK-INST: aif.frem.pi fa2, fs10, ft1
+# CHECK-ENC: encoding: [0x7b,0x26,0x1d,0x1e]
+aif.frem.pi fa2, fs10, ft1
+
+# CHECK-INST: aif.fround.ps fa3, fs7, rtz
+# CHECK-ENC: encoding: [0xfb,0x96,0x1b,0x58]
+aif.fround.ps fa3, fs7, rtz
+
+# CHECK-INST: aif.frsq.ps fs1, fs1
+# CHECK-ENC: encoding: [0xfb,0x84,0x84,0x58]
+aif.frsq.ps fs1, fs1
+
+# CHECK-INST: aif.fsat8.pi ft1, fs7
+# CHECK-ENC: encoding: [0xfb,0xb0,0x0b,0x06]
+aif.fsat8.pi ft1, fs7
+
+# CHECK-INST: aif.fsatu8.pi fa1, fa2
+# CHECK-ENC: encoding: [0xfb,0x35,0x16,0x06]
+aif.fsatu8.pi fa1, fa2
+
+# CHECK-INST: aif.fsc32b.ps ft7, gp, (s3)
+# CHECK-ENC: encoding: [0x8b,0x93,0x31,0x89]
+aif.fsc32b.ps ft7, gp, (s3)
+
+# CHECK-INST: aif.fsc32h.ps fa3, s6, (tp)
+# CHECK-ENC: encoding: [0x8b,0x16,0x4b,0x90]
+aif.fsc32h.ps fa3, s6, (tp)
+
+# CHECK-INST: aif.fsc32w.ps ft0, t5, (a0)
+# CHECK-ENC: encoding: [0x0b,0x10,0xaf,0xa0]
+aif.fsc32w.ps ft0, t5, (a0)
+
+# CHECK-INST: aif.fscb.ps ft9, ft1, (zero)
+# CHECK-ENC: encoding: [0x8b,0x9e,0x00,0xc8]
+aif.fscb.ps ft9, ft1, (zero)
+
+# CHECK-INST: aif.fsch.ps fs2, fa0, (t5)
+# CHECK-ENC: encoding: [0x0b,0x19,0xe5,0xd1]
+aif.fsch.ps fs2, fa0, (t5)
+
+# CHECK-INST: aif.fscw.ps ft1, ft0, (a0)
+# CHECK-ENC: encoding: [0x8b,0x10,0xa0,0xe0]
+aif.fscw.ps ft1, ft0, (a0)
+
+# CHECK-INST: aif.fsetm.pi m0, fa5
+# CHECK-ENC: encoding: [0x7b,0xc0,0x07,0xa6]
+aif.fsetm.pi m0, fa5
+
+# CHECK-INST: aif.fsgnjn.ps ft6, fs10, ft2
+# CHECK-ENC: encoding: [0x7b,0x13,0x2d,0x20]
+aif.fsgnjn.ps ft6, fs10, ft2
+
+# CHECK-INST: aif.fsgnjx.ps ft9, fs2, fs0
+# CHECK-ENC: encoding: [0xfb,0x2e,0x89,0x20]
+aif.fsgnjx.ps ft9, fs2, fs0
+
+# CHECK-INST: aif.fsgnj.ps fs3, fa7, ft0
+# CHECK-ENC: encoding: [0xfb,0x89,0x08,0x20]
+aif.fsgnj.ps fs3, fa7, ft0
+
+# CHECK-INST: aif.fsin.ps ft2, ft4
+# CHECK-ENC: encoding: [0x7b,0x01,0x62,0x58]
+aif.fsin.ps ft2, ft4
+
+# CHECK-INST: aif.fslli.pi ft1, fs10, 25
+# CHECK-ENC: encoding: [0xfb,0x10,0x9d,0x4f]
+aif.fslli.pi ft1, fs10, 25
+
+# CHECK-INST: aif.fsll.pi ft3, ft9, fa7
+# CHECK-ENC: encoding: [0xfb,0x91,0x1e,0x07]
+aif.fsll.pi ft3, ft9, fa7
+
+# CHECK-INST: aif.fsq2 fa4, -1100(s5)
+# CHECK-ENC: encoding: [0x27,0xda,0xea,0xba]
+aif.fsq2 fa4, -1100(s5)
+
+# CHECK-INST: aif.fsqrt.ps ft2, fs11
+# CHECK-ENC: encoding: [0x7b,0x81,0x0d,0x58]
+aif.fsqrt.ps ft2, fs11
+
+# CHECK-INST: aif.fsrai.pi ft1, fs5, 5
+# CHECK-ENC: encoding: [0xfb,0xf0,0x5a,0x4e]
+aif.fsrai.pi ft1, fs5, 5
+
+# CHECK-INST: aif.fsra.pi fs1, ft11, ft2
+# CHECK-ENC: encoding: [0xfb,0xd4,0x2f,0x0e]
+aif.fsra.pi fs1, ft11, ft2
+
+# CHECK-INST: aif.fsrli.pi fs0, fa4, 5
+# CHECK-ENC: encoding: [0x7b,0x54,0x57,0x4e]
+aif.fsrli.pi fs0, fa4, 5
+
+# CHECK-INST: aif.fsrl.pi fa2, fs0, fa4
+# CHECK-ENC: encoding: [0x7b,0x56,0xe4,0x06]
+aif.fsrl.pi fa2, fs0, fa4
+
+# CHECK-INST: aif.fsub.pi ft0, ft10, ft9
+# CHECK-ENC: encoding: [0x7b,0x00,0xdf,0x0f]
+aif.fsub.pi ft0, ft10, ft9
+
+# CHECK-INST: aif.fsub.ps ft2, ft2, fs8
+# CHECK-ENC: encoding: [0x7b,0x71,0x81,0x09]
+aif.fsub.ps ft2, ft2, fs8, dyn
+
+# CHECK-INST: aif.fswizz.ps ft3, fa4, 188
+# CHECK-ENC: encoding: [0xfb,0x41,0x77,0xe7]
+aif.fswizz.ps ft3, fa4, 188
+
+# CHECK-INST: aif.fsw.ps fs4, 1772(a1)
+# CHECK-ENC: encoding: [0x0b,0xe6,0x45,0x6f]
+aif.fsw.ps fs4, 1772(a1)
+
+# CHECK-INST: aif.fxor.pi ft10, fa6, fs6
+# CHECK-ENC: encoding: [0x7b,0x4f,0x68,0x07]
+aif.fxor.pi ft10, fa6, fs6
+
+#====----------------------------------------------------------------------===//
+# Masking instructions
+#====----------------------------------------------------------------------===//
+
+# CHECK-INST: aif.maskand m3, m5, m0
+# CHECK-ENC: encoding: [0xfb,0xf1,0x02,0x66]
+aif.maskand m3, m5, m0
+
+# CHECK-INST: aif.masknot m6, m6
+# CHECK-ENC: encoding: [0x7b,0x23,0x03,0x66]
+aif.masknot m6, m6
+
+# CHECK-INST: aif.maskor m0, m7, m5
+# CHECK-ENC: encoding: [0x7b,0xe0,0x53,0x66]
+aif.maskor m0, m7, m5
+
+# CHECK-INST: aif.maskpopc s9, m7
+# CHECK-ENC: encoding: [0xfb,0x8c,0x03,0x52]
+aif.maskpopc s9, m7
+
+# CHECK-INST: aif.maskpopcz s10, m4
+# CHECK-ENC: encoding: [0x7b,0x0d,0x02,0x54]
+aif.maskpopcz s10, m4
+
+# CHECK-INST: aif.maskpopc.rast m1, m3, m2, 2
+# CHECK-ENC: encoding: [0xfb,0x80,0x29,0x5e]
+aif.maskpopc.rast m1, m3, m2, 2
+
+# CHECK-INST: aif.maskxor m6, m6, m2
+# CHECK-ENC: encoding: [0x7b,0x43,0x23,0x66]
+aif.maskxor m6, m6, m2
+
+# CHECK-INST: aif.mova.m.x t1
+# CHECK-ENC: encoding: [0x7b,0x10,0x03,0xd6]
+aif.mova.m.x t1
+
+# CHECK-INST: aif.mova.x.m s1
+# CHECK-ENC: encoding: [0xfb,0x04,0x00,0xd6]
+aif.mova.x.m s1
+
+# CHECK-INST: aif.mov.m.x m3, t0, 201
+# CHECK-ENC: encoding: [0xfb,0x91,0x92,0x57]
+aif.mov.m.x m3, t0, 201
+
+# CHECK-INST: aif.packb a1, a2, a4
+# CHECK-ENC: encoding: [0xbb,0x65,0xe6,0x80]
+aif.packb a1, a2, a4
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