[llvm] [AMDGPU][GlobalISel] Add RegBankLegalize support for G_FLDEXP (PR #175072)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 8 13:31:42 PST 2026
https://github.com/vangthao95 created https://github.com/llvm/llvm-project/pull/175072
None
>From beea8617a9af2a87f0db05495ea078ab568823c5 Mon Sep 17 00:00:00 2001
From: Vang Thao <vang.thao at amd.com>
Date: Thu, 8 Jan 2026 13:11:41 -0800
Subject: [PATCH] [AMDGPU][GlobalISel] Add RegBankLegalize support for G_FLDEXP
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 8 +
llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll | 51 ++++---
llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll | 143 ++++++++++++++++--
3 files changed, 174 insertions(+), 28 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index ab17d9e863d2b..0136049b4cfeb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -978,6 +978,14 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32, Vgpr32}})
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32, Vgpr32}});
+ addRulesForGOpcs({G_FLDEXP}, Standard)
+ .Uni(S16, {{UniInVgprS16}, {Vgpr16, Vgpr16}})
+ .Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
+ .Uni(S32, {{UniInVgprS32}, {Vgpr32, Vgpr32}})
+ .Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32}})
+ .Uni(S64, {{UniInVgprS64}, {Vgpr64, Vgpr32}})
+ .Div(S64, {{Vgpr64}, {Vgpr64, Vgpr32}});
+
addRulesForGOpcs({G_FMA}, Standard)
.Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16, Vgpr16}})
.Div(S32, {{Vgpr32}, {Vgpr32, Vgpr32, Vgpr32}})
diff --git a/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll b/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
index eb7698d3348ed..95d2f07402dd4 100644
--- a/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX10,GFX10-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX10,GFX10-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX10,GFX10-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
; Test fmul by power of 2 which is better emitted as ldexp
@@ -4216,19 +4216,34 @@ define <2 x half> @v_fma_mul_add_32_v2f16(<2 x half> %x, <2 x half> %y) {
}
define amdgpu_ps i32 @s_mul_32_f16(half inreg %x, half inreg %y) {
-; GFX9-LABEL: s_mul_32_f16:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: v_mov_b32_e32 v0, 0x5000
-; GFX9-NEXT: v_mul_f16_e32 v0, s0, v0
-; GFX9-NEXT: v_readfirstlane_b32 s0, v0
-; GFX9-NEXT: ; return to shader part epilog
+; GFX9-SDAG-LABEL: s_mul_32_f16:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, 0x5000
+; GFX9-SDAG-NEXT: v_mul_f16_e32 v0, s0, v0
+; GFX9-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-SDAG-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_mul_32_f16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_mul_f16_e64 v0, 0x5000, s0
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX9-GISEL-LABEL: s_mul_32_f16:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, 0x5000
+; GFX9-GISEL-NEXT: v_mul_f16_e32 v0, s0, v0
+; GFX9-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-GISEL-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX9-GISEL-NEXT: ; return to shader part epilog
+;
+; GFX10-SDAG-LABEL: s_mul_32_f16:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: v_mul_f16_e64 v0, 0x5000, s0
+; GFX10-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-SDAG-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX10-GISEL-LABEL: s_mul_32_f16:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: v_mul_f16_e64 v0, 0x5000, s0
+; GFX10-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-GISEL-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX10-GISEL-NEXT: ; return to shader part epilog
;
; GFX11-SDAG-TRUE16-LABEL: s_mul_32_f16:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -4247,15 +4262,15 @@ define amdgpu_ps i32 @s_mul_32_f16(half inreg %x, half inreg %y) {
; GFX11-GISEL-TRUE16-LABEL: s_mul_32_f16:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e64 v0.l, 0x5000, s0
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0
; GFX11-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-GISEL-TRUE16-NEXT: s_and_b32 s0, 0xffff, s0
; GFX11-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-GISEL-FAKE16-LABEL: s_mul_32_f16:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: v_mul_f16_e64 v0, 0x5000, s0
-; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-GISEL-FAKE16-NEXT: s_and_b32 s0, 0xffff, s0
; GFX11-GISEL-FAKE16-NEXT: ; return to shader part epilog
%mul = fmul contract half %x, 32.0
%cast = bitcast half %mul to i16
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll b/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
index 930fab95b863d..5fae6de4a9682 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll
@@ -5,11 +5,11 @@
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6,GFX6-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,GFX8,GFX8-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL-FAKE16 %s
define float @test_ldexp_f32_i32(ptr addrspace(1) %out, float %a, i32 %b) {
; GFX6-LABEL: test_ldexp_f32_i32:
@@ -772,6 +772,7 @@ define <3 x half> @test_ldexp_v3f16_v3i32(<3 x half> %a, <3 x i32> %b) {
; GFX9-GISEL-NEXT: v_med3_i32 v3, v4, v5, v6
; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v1, v1, v3
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: test_ldexp_v3f16_v3i32:
@@ -793,17 +794,20 @@ define <3 x half> @test_ldexp_v3f16_v3i32(<3 x half> %a, <3 x i32> %b) {
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v5, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v2, 0xffff8000, v2, v5
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v4, 0xffff8000, v4, v5
; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v3, 0xffff8000, v3, v5
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v2
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v1, v4
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v2, v6, v3
-; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v3, 0xffff8000, v4, v5
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v1, v3
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x half> @llvm.ldexp.v3f16.v3i32(<3 x half> %a, <3 x i32> %b)
ret <3 x half> %result
@@ -898,6 +902,7 @@ define <3 x half> @test_ldexp_v3f16_v3i16(<3 x half> %a, <3 x i16> %b) {
; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v1, v1, v3
; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v4
+; GFX9-GISEL-NEXT: v_lshl_or_b32 v1, s4, 16, v1
; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-TRUE16-LABEL: test_ldexp_v3f16_v3i16:
@@ -918,8 +923,11 @@ define <3 x half> @test_ldexp_v3f16_v3i16(<3 x half> %a, <3 x i16> %b) {
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v2, v4, v5
; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x half> @llvm.ldexp.v3f16.v3i16(<3 x half> %a, <3 x i16> %b)
ret <3 x half> %result
@@ -1256,6 +1264,121 @@ define <4 x half> @test_ldexp_v4f16_v4i16(<4 x half> %a, <4 x i16> %b) {
ret <4 x half> %result
}
+define amdgpu_ps half @test_ldexp_f16_i16_uniform(half inreg %a, i16 inreg %b) {
+; GFX6-SDAG-LABEL: test_ldexp_f16_i16_uniform:
+; GFX6-SDAG: ; %bb.0:
+; GFX6-SDAG-NEXT: v_cvt_f16_f32_e32 v0, s0
+; GFX6-SDAG-NEXT: s_sext_i32_i16 s0, s1
+; GFX6-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX6-SDAG-NEXT: v_ldexp_f32_e64 v0, v0, s0
+; GFX6-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: test_ldexp_f16_i16_uniform:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_ldexp_f16_e32 v0, s0, v0
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_ldexp_f16_i16_uniform:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_ldexp_f16_e32 v0, s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX11-SDAG-TRUE16-LABEL: test_ldexp_f16_i16_uniform:
+; GFX11-SDAG-TRUE16: ; %bb.0:
+; GFX11-SDAG-TRUE16-NEXT: v_ldexp_f16_e64 v0.l, s0, s1
+; GFX11-SDAG-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-SDAG-FAKE16-LABEL: test_ldexp_f16_i16_uniform:
+; GFX11-SDAG-FAKE16: ; %bb.0:
+; GFX11-SDAG-FAKE16-NEXT: v_ldexp_f16_e64 v0, s0, s1
+; GFX11-SDAG-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX6-GISEL-LABEL: test_ldexp_f16_i16_uniform:
+; GFX6-GISEL: ; %bb.0:
+; GFX6-GISEL-NEXT: v_cvt_f32_f16_e32 v0, s0
+; GFX6-GISEL-NEXT: s_sext_i32_i16 s0, s1
+; GFX6-GISEL-NEXT: v_ldexp_f32_e64 v0, v0, s0
+; GFX6-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX6-GISEL-NEXT: ; return to shader part epilog
+;
+; GFX11-GISEL-TRUE16-LABEL: test_ldexp_f16_i16_uniform:
+; GFX11-GISEL-TRUE16: ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e64 v0.l, s0, s1
+; GFX11-GISEL-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-GISEL-FAKE16-LABEL: test_ldexp_f16_i16_uniform:
+; GFX11-GISEL-FAKE16: ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e64 v0, s0, s1
+; GFX11-GISEL-FAKE16-NEXT: ; return to shader part epilog
+ %result = call half @llvm.ldexp.f16.i16(half %a, i16 %b)
+ ret half %result
+}
+
+define amdgpu_ps float @test_ldexp_f32_i32_uniform(float inreg %a, i32 inreg %b) {
+; GFX6-LABEL: test_ldexp_f32_i32_uniform:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v0, s1
+; GFX6-NEXT: v_ldexp_f32_e32 v0, s0, v0
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: test_ldexp_f32_i32_uniform:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_ldexp_f32_i32_uniform:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: test_ldexp_f32_i32_uniform:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_ldexp_f32 v0, s0, s1
+; GFX11-NEXT: ; return to shader part epilog
+ %result = call float @llvm.ldexp.f32.i32(float %a, i32 %b)
+ ret float %result
+}
+
+define amdgpu_ps double @test_ldexp_f64_i32_uniform(double inreg %a, i32 inreg %b) {
+; GFX6-LABEL: test_ldexp_f64_i32_uniform:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NEXT: v_ldexp_f64 v[0:1], s[0:1], v0
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8-LABEL: test_ldexp_f64_i32_uniform:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_ldexp_f64 v[0:1], s[0:1], v0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: ; return to shader part epilog
+;
+; GFX9-LABEL: test_ldexp_f64_i32_uniform:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_ldexp_f64 v[0:1], s[0:1], v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: test_ldexp_f64_i32_uniform:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_ldexp_f64 v[0:1], s[0:1], s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: v_readfirstlane_b32 s1, v1
+; GFX11-NEXT: ; return to shader part epilog
+ %result = call double @llvm.ldexp.f64.i32(double %a, i32 %b)
+ ret double %result
+}
+
declare float @llvm.ldexp.f32.i32(float, i32) #0
declare float @llvm.ldexp.f32.i16(float, i16) #0
declare float @llvm.ldexp.f32.i64(float, i64) #0
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