[llvm] [RISCV] AI Foundry ET extensions for RISC-V (PR #174571)

[Abel Bernabeu via llvm-commits]

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+//===-- RISCVInstrFormatXAIF.td ----------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Instruction formats for the AI Foundry ET extensions, formerly known as the
+// ET-SoC-1 Minion extensions by Esperanto Technologies.
+//
+// Full documentation for these extensions is publicly available at the
+// following URL:
+//
+//   https://github.com/aifoundry-org/et-man/blob/main/ET%20Programmer's%20Reference%20Manual.pdf
+//
+//===----------------------------------------------------------------------===//
+
+def OPC_ET_MEM_PS   : RISCVOpcode<"ET_MEM_PS",  0b0001011>;
+def OPC_ET_IMM_PS   : RISCVOpcode<"ET_IMM_PS",  0b0011111>;
+def OPC_ET_IMM10_PI : RISCVOpcode<"ET_IMM1_PI", 0b0111111>;
+def OPC_ET_OP3_PS   : RISCVOpcode<"ET_OP3_PS",  0b1011011>;
+def OPC_ET_IMM_PI   : RISCVOpcode<"ET_IMM_PI",  0b1011111>;
+def OPC_ET_CVT_PS   : RISCVOpcode<"ET_CVT_PS",  0b1110111>;
+def OPC_ET_OP_PS    : RISCVOpcode<"ET_OP_PS",   0b1111011>; // OPC_CUSTOM_3
+
+// Example: AIF.FSWIZZ.PS
+class RVInstET1<bits<7> funct7,RISCVOpcode opcode, dag outs, dag ins,
+                string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+  bits<5> rd;
+  bits<5> rs1;
+  bits<8> imm;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = imm{7-3};
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = imm{2-0};
+  let Inst{11-7} = rd;
+  let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FADDI.PS
+class RVInstET2<bits<3> funct3,RISCVOpcode opcode, dag outs, dag ins,
+                string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+  bits<10> imm;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-27} = imm{9-5};
+  let Inst{26-25} = 0b10;
+  let Inst{24-20} = imm{4-0};
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FADD.PS
+class RVInstET3<bits<7> funct7,RISCVOpcode opcode, dag outs, dag ins,
+                string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+  bits<5> rd;
+  bits<5> rs1;
+  bits<5> rs2;
+  bits<3> rm;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = rm;
+  let Inst{11-7} = rd;
+  let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FMADD.PS
+class RVInstET4<bits<2> funct2,RISCVOpcode opcode, dag outs, dag ins,
+                string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+  bits<5> rd;
+  bits<5> rs1;
+  bits<5> rs2;
+  bits<5> rs3;
+  bits<3> rm;
+
+  let Inst{31-27} = rs3;
+  let Inst{26-25} = funct2;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = rm;
+  let Inst{11-7} = rd;
+  let Inst{6-0} = opcode.Value;
+}
+
+// Example: AIF.FMVZ.X.PS
+class RVInstET5<bits<7> funct7,bits<3> funct3,
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abel-bernabeu wrote:

Agreed

https://github.com/llvm/llvm-project/pull/174571