[llvm] [RISCV] AI Foundry ET extensions for RISC-V (PR #174571)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,263 @@
+//===-- RISCVInstrFormatXAIF.td ----------------------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Instruction formats for the AI Foundry ET extensions, formerly known as the
+// ET-SoC-1 Minion extensions by Esperanto Technologies.
+//
+// Full documentation for these extensions is publicly available at the
+// following URL:
+//
+//   https://github.com/aifoundry-org/et-man/blob/main/ET%20Programmer's%20Reference%20Manual.pdf
+//
+//===----------------------------------------------------------------------===//
+
+def OPC_ET_MEM_PS   : RISCVOpcode<"ET_MEM_PS",  0b0001011>;
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topperc wrote:

RISCVOpcode has special code hooked up to it to generate names for `.insn` in asssembly. Is the intention here to add alias opcodes for `.insn` or is this just for readability in this file.

If it's just readability, please use `defvar OPC_ET_MEM_PS = OPC_CUSTOM_0;` so that it only creates an alias inside tablegen.

https://github.com/llvm/llvm-project/pull/174571