[llvm] [AMDGPU] using divergent/uniform information in ISel of zext (PR #174539)

[Zeng Wu via llvm-commits]

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zwu-2025 wrote:

the complete MIR is:
```
        bb.0.entry:
liveins: $sgpr4_sgpr5
%3:sgpr_64(p4) = COPY $sgpr4_sgpr5
%8:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
        early-clobber %9:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM_ec %3:sgpr_64(p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.out.kernarg.offset, align 4, addrspace 4)
        early-clobber %10:sreg_64_xexec = S_LOAD_DWORDX2_IMM_ec %3:sgpr_64(p4), 44, 0 :: (dereferenceable invariant load (s64) from %ir.val0.kernarg.offset, align 4, addrspace 4)
%11:sreg_32 = COPY %10.sub0:sreg_64_xexec
%12:sreg_32 = COPY %10.sub1:sreg_64_xexec
        S_CMP_EQ_U32 killed %11:sreg_32, killed %12:sreg_32, implicit-def $scc
%13:sreg_64 = COPY $scc
%15:sreg_32 = COPY %13:sreg_64
%14:sreg_32 = S_AND_B32 killed %15:sreg_32, 1, implicit-def dead $scc
%16:av_32 = COPY %14:sreg_32
        GLOBAL_STORE_DWORD_SADDR killed %8:vgpr_32, killed %16:av_32, killed %9:sreg_64_xexec_xnull, 0, 0, implicit $exec :: (store (s32) into %ir.out.load, addrspace 1)
        S_ENDPGM 0
```

https://github.com/llvm/llvm-project/pull/174539