[llvm] [RISCV] Bail out of combineNarrowableShiftedLoad for types other than scalar int (PR #175011)

[Alex Bradbury via llvm-commits]

https://github.com/asb created https://github.com/llvm/llvm-project/pull/175011

Introduced in #170483 this was only ever meant to trigger for scalar types. We get an error on rv32gcv for some inputs "Cannot implicitly convert a scalable size to a fixed-width size in `TypeSize::operator ScalarTy()`".

While we're editing this function, delete an accidentally repeated comment.

Minimal reproducer:
```
define <vscale x 4 x ptr> @ham() {
bb:
  %load = load <vscale x 4 x i32>, ptr null, align 4
  %ashr = ashr <vscale x 4 x i32> %load, splat (i32 1)
  %getelementptr = getelementptr i32, ptr null, <vscale x 4 x i32> %ashr
  ret <vscale x 4 x ptr> %getelementptr
}
```
---
Although I have a reproducer I haven't added it, largely because I'm not sure where it should live. Adding it to load-narrow-shift-mask-combine.ll would require changing the CHECK line names RV32I => RV32 and RV64I => RV64 and adding -mattr=+v with a comment for the test. Alternatively I add a new file named after whatever PR number this has. Or we decide it's a trivial fix that doesn't really need an explicit test. (This case was found via llvm-test-suite rv32gcv - once this batch of fixes lands we will get continual coverage of that in CI).

>From 2e968f62a70fbb2884133520249b113d6ae67d58 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb at igalia.com>
Date: Thu, 8 Jan 2026 16:12:15 +0000
Subject: [PATCH] [RISCV] Bail out of combineNarrowableShiftedLoad for types
 other than scalar int

Introduced in #170483 this was only ever meant to trigger for scalar
types. We get an error on rv32gcv for some inputs "Cannot implicitly
convert a scalable size to a fixed-width size in `TypeSize::operator
ScalarTy()`".

While we're editing this function, delete an accidentally repeated
comment.

Minimal reproducer:
```
define <vscale x 4 x ptr> @ham() {
bb:
  %load = load <vscale x 4 x i32>, ptr null, align 4
  %ashr = ashr <vscale x 4 x i32> %load, splat (i32 1)
  %getelementptr = getelementptr i32, ptr null, <vscale x 4 x i32> %ashr
  ret <vscale x 4 x ptr> %getelementptr
}
```
---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f87c45a77dc64..add1e71ca594e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -16704,7 +16704,10 @@ static SDValue reduceANDOfAtomicLoad(SDNode *N,
 // hidden by the intermediate shift. Detect that case and commute the
 // shift/and in order to enable load narrowing.
 static SDValue combineNarrowableShiftedLoad(SDNode *N, SelectionDAG &DAG) {
-  // (and (shl (load ...), ShiftAmt), Mask)
+  EVT VT = N->getValueType(0);
+  if (!VT.isScalarInteger())
+    return SDValue();
+
   using namespace SDPatternMatch;
   SDValue LoadNode;
   APInt MaskVal, ShiftVal;
@@ -16716,7 +16719,6 @@ static SDValue combineNarrowableShiftedLoad(SDNode *N, SelectionDAG &DAG) {
     return SDValue();
   }
 
-  EVT VT = N->getValueType(0);
   uint64_t ShiftAmt = ShiftVal.getZExtValue();
 
   if (ShiftAmt >= VT.getSizeInBits())