[llvm] [AArch64] Use GISel for optnone functions (PR #174746)
Ryan Cowan via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 8 04:15:25 PST 2026
https://github.com/HolyMolyCowMan updated https://github.com/llvm/llvm-project/pull/174746
>From 27787fb8183a8fae6aa508067ccecb5abed61b0f Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Wed, 7 Jan 2026 10:12:42 +0000
Subject: [PATCH 1/3] [AArch64] Use GISel for optnone functions
---
llvm/include/llvm/CodeGen/TargetPassConfig.h | 3 +
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 15 +++
llvm/lib/CodeGen/MachineFunction.cpp | 11 +-
.../Target/AArch64/AArch64TargetMachine.cpp | 35 +++++-
.../lib/Target/AArch64/AArch64TargetMachine.h | 2 +
.../GlobalISel/gisel-commandline-option.ll | 8 +-
.../CodeGen/AArch64/GlobalISel/optnone-llc.ll | 53 ++++++++
.../AArch64/GlobalISel/optnone-mixed.ll | 28 +++++
llvm/test/CodeGen/AArch64/O3-pipeline.ll | 25 +++-
llvm/test/CodeGen/AArch64/cfguard-checks.ll | 3 +-
llvm/test/CodeGen/AArch64/large-stack.ll | 17 ++-
.../test/CodeGen/AArch64/ldrpre-ldr-merge.mir | 4 +-
.../CodeGen/AArch64/literal_pools_float.ll | 85 +++++++++++--
.../CodeGen/AArch64/multi-vector-load-size.ll | 2 +-
.../AArch64/multi-vector-store-size.ll | 2 +-
.../AArch64/semantic-interposition-memtag.ll | 3 +-
.../test/CodeGen/AArch64/strpre-str-merge.mir | 116 ++++++++++--------
.../AArch64/swift-error-unreachable-use.ll | 22 ++--
.../print-parse-overloaded-intrinsics.mir | 4 +-
llvm/test/DebugInfo/Generic/debug-label-mi.ll | 4 +
llvm/test/Feature/optnone-llc.ll | 6 +-
21 files changed, 344 insertions(+), 104 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/optnone-llc.ll
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/optnone-mixed.ll
diff --git a/llvm/include/llvm/CodeGen/TargetPassConfig.h b/llvm/include/llvm/CodeGen/TargetPassConfig.h
index 5e0e641a981f9..b9a6a1b1d268f 100644
--- a/llvm/include/llvm/CodeGen/TargetPassConfig.h
+++ b/llvm/include/llvm/CodeGen/TargetPassConfig.h
@@ -341,6 +341,9 @@ class LLVM_ABI TargetPassConfig : public ImmutablePass {
/// By default, it's enabled for non O0 levels.
virtual bool isGISelCSEEnabled() const;
+ /// Return true if GlobalISel should be run for a given function
+ virtual bool useGlobalISelFor(const Function &F) const { return true; }
+
/// Returns the CSEConfig object to use for the current optimization level.
virtual std::unique_ptr<CSEConfigBase> getCSEConfig() const;
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 12552bce3caaa..d69f5a8b57164 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -4140,6 +4140,21 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
// Set the CSEConfig and run the analysis.
GISelCSEInfo *CSEInfo = nullptr;
TPC = &getAnalysis<TargetPassConfig>();
+ if (!TPC->useGlobalISelFor(F)) {
+ LLVM_DEBUG(
+ dbgs()
+ << "Skipping GISel as useGlobalISelFor this function is false.\n");
+
+ // Create a block if this would have been the first block
+ // to avoid MachineDominatorTree hitting a sentinel assertion
+ if (MF->empty()) {
+ MachineBasicBlock *EntryBB = MF->CreateMachineBasicBlock();
+ MF->push_back(EntryBB);
+ MF->getProperties().setFailedISel();
+ }
+ return false;
+ }
+
bool EnableCSE = EnableCSEInIRTranslator.getNumOccurrences()
? EnableCSEInIRTranslator
: TPC->isGISelCSEEnabled();
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index 8d7694537e07d..ae50a2aff40c0 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -503,9 +503,14 @@ MachineFunction::CreateMachineBasicBlock(const BasicBlock *BB,
MachineBasicBlock(*this, BB);
// Set BBID for `-basic-block-sections=list` and `-basic-block-address-map` to
// allow robust mapping of profiles to basic blocks.
- if (Target.Options.BBAddrMap ||
- Target.getBBSectionsType() == BasicBlockSection::List)
- MBB->setBBID(BBID.has_value() ? *BBID : UniqueBBID{NextBBID++, 0});
+ if ((Target.Options.BBAddrMap ||
+ Target.getBBSectionsType() == BasicBlockSection::List)) {
+ if (BBID)
+ MBB->setBBID(*BBID);
+ else if (BB)
+ MBB->setBBID(UniqueBBID{NextBBID++, 0});
+ }
+
return MBB;
}
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 1ec5a20cc0ce0..3d87eb60603b0 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -160,6 +160,10 @@ static cl::opt<int> EnableGlobalISelAtO(
cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
cl::init(0));
+static cl::opt<bool> EnableGlobalISelForOptNone(
+ "aarch64-enable-global-isel-for-optnone", cl::Hidden,
+ cl::desc("Route optnone functions through GlobalISel"), cl::init(true));
+
static cl::opt<bool>
EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden,
cl::desc("Enable SVE intrinsic opts"),
@@ -380,14 +384,26 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
// for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
this->Options.TLSSize = 24;
- // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
- // MachO/CodeModel::Large, which GlobalISel does not support.
- if (static_cast<int>(getOptLevel()) <= EnableGlobalISelAtO &&
+ const bool TargetSupportsGISel =
TT.getArch() != Triple::aarch64_32 &&
TT.getEnvironment() != Triple::GNUILP32 &&
- !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
- setGlobalISel(true);
- setGlobalISelAbort(GlobalISelAbortMode::Disable);
+ !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO());
+
+ const bool GlobalISelFlag =
+ getCGPassBuilderOption().EnableGlobalISelOption.value_or(false);
+
+ // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
+ // MachO/CodeModel::Large, which GlobalISel does not support.
+ if (TargetSupportsGISel) {
+ if (static_cast<int>(getOptLevel()) <= EnableGlobalISelAtO) {
+ setGlobalISel(true);
+ setGlobalISelAbort(GlobalISelAbortMode::Disable);
+ } else if (!GlobalISelFlag && EnableGlobalISelForOptNone &&
+ !Options.EnableGlobalISel) {
+ setGlobalISel(true);
+ setGlobalISelAbort(GlobalISelAbortMode::Disable);
+ UseGISelForOptNoneOnly = true;
+ }
}
// AArch64 supports the MachineOutliner.
@@ -540,6 +556,7 @@ class AArch64PassConfig : public TargetPassConfig {
void addIRPasses() override;
bool addPreISel() override;
void addCodeGenPrepare() override;
+ bool useGlobalISelFor(const Function &F) const override;
bool addInstSelector() override;
bool addIRTranslator() override;
void addPreLegalizeMachineIR() override;
@@ -706,6 +723,12 @@ void AArch64PassConfig::addCodeGenPrepare() {
TargetPassConfig::addCodeGenPrepare();
}
+bool AArch64PassConfig::useGlobalISelFor(const Function &F) const {
+ if (!getAArch64TargetMachine().useGlobalISelForOptNoneOnly())
+ return true;
+ return F.hasOptNone();
+}
+
bool AArch64PassConfig::addInstSelector() {
addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.h b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
index 0dd5d95b19b43..ffb5c3f96f8a2 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
@@ -25,6 +25,7 @@ class AArch64TargetMachine : public CodeGenTargetMachineImpl {
protected:
std::unique_ptr<TargetLoweringObjectFile> TLOF;
mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;
+ bool UseGISelForOptNoneOnly = false;
/// Reset internal state.
void reset() override;
@@ -81,6 +82,7 @@ class AArch64TargetMachine : public CodeGenTargetMachineImpl {
/// Returns true if the new SME ABI lowering should be used.
bool useNewSMEABILowering() const { return UseNewSMEABILowering; }
+ bool useGlobalISelForOptNoneOnly() const { return UseGISelForOptNoneOnly; }
private:
bool isLittle;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll b/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
index df8fc178ab4de..38a0f4ffb4904 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
@@ -36,6 +36,12 @@
; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
; RUN: --debugify-and-strip-all-safe=0 \
; RUN: -verify-machineinstrs=0 -O1 -aarch64-enable-global-isel-at-O=0 \
+; RUN: | FileCheck %s --check-prefix OPTNONE
+
+; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
+; RUN: --debugify-and-strip-all-safe=0 \
+; RUN: -verify-machineinstrs=0 -O1 -aarch64-enable-global-isel-at-O=0 \
+; RUN: -aarch64-enable-global-isel-for-optnone=false \
; RUN: | FileCheck %s --check-prefix DISABLED
; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
@@ -82,7 +88,7 @@
; FALLBACK: AArch64 Instruction Selection
; NOFALLBACK-NOT: AArch64 Instruction Selection
-; DISABLED-NOT: IRTranslator
+; OPTNONE: IRTranslator
; DISABLED: AArch64 Instruction Selection
; DISABLED: Finalize ISel and expand pseudo-instructions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/optnone-llc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/optnone-llc.ll
new file mode 100644
index 0000000000000..13ab7cb477e51
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/optnone-llc.ll
@@ -0,0 +1,53 @@
+; NOTE: Do not autogenerate
+; RUN: llc -O1 -debug -global-isel -mtriple=aarch64-unknown-linux-gnu -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=LLC-Ox
+; RUN: llc -O2 -debug -global-isel -mtriple=aarch64-unknown-linux-gnu -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=LLC-Ox
+; RUN: llc -O3 -debug -global-isel -mtriple=aarch64-unknown-linux-gnu -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=LLC-Ox
+; RUN: llc -misched-postra -debug -global-isel -mtriple=aarch64-unknown-linux-gnu -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=LLC-MORE
+
+; REQUIRES: asserts
+; UNSUPPORTED: target=nvptx{{.*}}
+
+; This test verifies that we don't run Machine Function optimizations
+; on optnone functions.
+
+; Function Attrs: noinline optnone
+define i32 @_Z3fooi(i32 %x) #0 {
+entry:
+ %x.addr = alloca i32, align 4
+ store i32 %x, ptr %x.addr, align 4
+ br label %while.cond
+
+while.cond: ; preds = %while.body, %entry
+ %0 = load i32, ptr %x.addr, align 4
+ %dec = add nsw i32 %0, -1
+ store i32 %dec, ptr %x.addr, align 4
+ %tobool = icmp ne i32 %0, 0
+ br i1 %tobool, label %while.body, label %while.end
+
+while.body: ; preds = %while.cond
+ br label %while.cond
+
+while.end: ; preds = %while.cond
+ ret i32 0
+}
+
+attributes #0 = { optnone noinline }
+
+; Machine Function passes run at -O1 and higher.
+; LLC-Ox-DAG: Skipping pass 'Branch Probability Basic Block Placement'
+; LLC-Ox-DAG: Skipping pass 'CodeGen Prepare'
+; LLC-Ox-DAG: Skipping pass 'Control Flow Optimizer'
+; LLC-Ox-DAG: Skipping pass 'Machine code sinking'
+; LLC-Ox-DAG: Skipping pass 'Machine Common Subexpression Elimination'
+; LLC-Ox-DAG: Skipping pass 'Shrink Wrapping analysis'
+; LLC-Ox-DAG: Skipping pass 'Machine Copy Propagation Pass'
+; LLC-Ox-DAG: Skipping pass 'Machine Instruction Scheduler'
+; LLC-Ox-DAG: Skipping pass 'Machine Loop Invariant Code Motion'
+; LLC-Ox-DAG: Skipping pass 'Optimize machine instruction PHIs'
+; LLC-Ox-DAG: Skipping pass 'Peephole Optimizations'
+; LLC-Ox-DAG: Skipping pass 'Post{{.*}}RA{{.*}}{{[Ss]}}cheduler'
+; LLC-Ox-DAG: Skipping pass 'Remove dead machine instructions'
+; LLC-Ox-DAG: Skipping pass 'Tail Duplication'
+
+; Alternate post-RA scheduler.
+; LLC-MORE: Skipping pass 'PostRA Machine Instruction Scheduler'
\ No newline at end of file
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/optnone-mixed.ll b/llvm/test/CodeGen/AArch64/GlobalISel/optnone-mixed.ll
new file mode 100644
index 0000000000000..442f8f86fb973
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/optnone-mixed.ll
@@ -0,0 +1,28 @@
+; NOTE: Do not autogenerate
+; RUN: llc -mtriple=aarch64-linux-gnu -O2 -verify-machineinstrs -debug %s -o - 2>&1 | FileCheck %s --check-prefix=GISEL
+; RUN: llc -mtriple=aarch64-linux-gnu -O2 -verify-machineinstrs -debug %s -o - 2>&1 -aarch64-enable-global-isel-for-optnone=0 | FileCheck %s --check-prefix=SDAG
+; REQUIRES: asserts
+
+; Check both an optnone function and a non-optnone function to ensure that only
+; the optnone functions is routed through GlobalISel
+
+; Function Attrs: noinline nounwind optnone uwtable
+define i32 @optnone_fn(i32 %a) #0 {
+entry:
+ %add = add nsw i32 %a, 1
+ ret i32 %add
+}
+
+define i32 @normal_fn(i32 %a) {
+entry:
+ %mul = mul nsw i32 %a, 2
+ ret i32 %mul
+}
+
+; GISEL: Skipping pass 'AArch64PostLegalizerCombiner' on function optnone_fn
+; GISEL: Creating new node:
+
+; SDAG: Changing optimization level for Function optnone_fn
+; SDAG: Optimized legalized selection DAG: %bb.0 'normal_fn:entry'
+
+attributes #0 = { noinline nounwind optnone uwtable }
diff --git a/llvm/test/CodeGen/AArch64/O3-pipeline.ll b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
index e4249fe4fb1c8..255b9a2827676 100644
--- a/llvm/test/CodeGen/AArch64/O3-pipeline.ll
+++ b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
@@ -114,9 +114,32 @@
; CHECK-NEXT: Safe Stack instrumentation pass
; CHECK-NEXT: Insert stack protectors
; CHECK-NEXT: Module Verifier
+; CHECK-NEXT: Analysis containing CSE Info
+; CHECK-NEXT: Natural Loop Information
+; CHECK-NEXT: Post-Dominator Tree Construction
+; CHECK-NEXT: Branch Probability Analysis
; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
; CHECK-NEXT: Function Alias Analysis Results
-; CHECK-NEXT: Natural Loop Information
+; CHECK-NEXT: IRTranslator
+; CHECK-NEXT: Analysis for ComputingKnownBits
+; CHECK-NEXT: MachineDominator Tree Construction
+; CHECK-NEXT: Analysis containing CSE Info
+; CHECK-NEXT: AArch64PreLegalizerCombiner
+; CHECK-NEXT: Localizer
+; CHECK-NEXT: LoadStoreOpt
+; CHECK-NEXT: Analysis containing CSE Info
+; CHECK-NEXT: Analysis for ComputingKnownBits
+; CHECK-NEXT: Legalizer
+; CHECK-NEXT: MachineDominator Tree Construction
+; CHECK-NEXT: AArch64PostLegalizerCombiner
+; CHECK-NEXT: AArch64PostLegalizerLowering
+; CHECK-NEXT: RegBankSelect
+; CHECK-NEXT: Analysis for ComputingKnownBits
+; CHECK-NEXT: Lazy Branch Probability Analysis
+; CHECK-NEXT: Lazy Block Frequency Analysis
+; CHECK-NEXT: InstructionSelect
+; CHECK-NEXT: AArch64 Post Select Optimizer
+; CHECK-NEXT: ResetMachineFunction
; CHECK-NEXT: Post-Dominator Tree Construction
; CHECK-NEXT: Branch Probability Analysis
; CHECK-NEXT: Assignment Tracking Analysis
diff --git a/llvm/test/CodeGen/AArch64/cfguard-checks.ll b/llvm/test/CodeGen/AArch64/cfguard-checks.ll
index 1249163280820..b2545cd6b841f 100644
--- a/llvm/test/CodeGen/AArch64/cfguard-checks.ll
+++ b/llvm/test/CodeGen/AArch64/cfguard-checks.ll
@@ -40,8 +40,7 @@ entry:
; CHECK: adrp x8, target_func
; CHECK: add x8, x8, :lo12:target_func
; CHECK: adrp x9, __guard_check_icall_fptr
- ; CHECK: add x9, x9, :lo12:__guard_check_icall_fptr
- ; CHECK: ldr x9, [x9]
+ ; CHECK: ldr x9, [x9, :lo12:__guard_check_icall_fptr]
; CHECK: mov x15, x8
; CHECK: blr x9
; CHECK-NEXT: blr x8
diff --git a/llvm/test/CodeGen/AArch64/large-stack.ll b/llvm/test/CodeGen/AArch64/large-stack.ll
index c96dd60462d41..a177398e66e50 100644
--- a/llvm/test/CodeGen/AArch64/large-stack.ll
+++ b/llvm/test/CodeGen/AArch64/large-stack.ll
@@ -34,16 +34,13 @@ attributes #0 = { noinline optnone "frame-pointer"="all" uwtable }
; CHECK: sub x[[INDEX:[0-9]+]], x[[FRAME]], #8
; CHECK-NEXT: str x0, [x[[INDEX]]]
; CHECK-NEXT: ldr x[[VAL1:[0-9]+]], [x[[INDEX]]]
-; CHECK-NEXT: add x[[VAL3:[0-9]+]], sp, #8
-; CHECK-NEXT: mov x[[VAL2:[0-9]+]], #8
-; CHECK-NEXT: madd x[[VAL1]], x[[VAL1]], x[[VAL2]], x[[VAL3]]
-; CHECK-NEXT: mov x[[TMP1:[0-9]+]], #1
-; CHECK-NEXT: str x[[TMP1]], [x[[VAL1]]]
-; CHECK-NEXT: ldr x[[INDEX]], [x[[INDEX]]]
-; CHECK-NEXT: add x[[VAL3:[0-9]+]], sp, #8
-; CHECK-NEXT: mov x[[VAL4:[0-9]+]], #8
-; CHECK-NEXT: madd x[[INDEX]], x[[INDEX]], x[[VAL4]], x[[VAL3]]
-; CHECK-NEXT: ldr x1, [x[[INDEX]]
+; CHECK-NEXT: add x10, sp, #8
+; CHECK-NEXT: mov x11, #1 // =0x1
+; CHECK-NEXT: str x11, [x10, x9, lsl #3]
+; CHECK-NEXT: ldr x8, [x8]
+; CHECK-NEXT: ldr x1, [x10, x8, lsl #3]
+; CHECK-NEXT: adrp x0, .L.str
+; CHECK-NEXT: add x0, x0, :lo12:.L.str
; CHECK: bl printf
; CHECK-COUNT-128: add sp, sp, #[[STACK1]], lsl #12
; CHECK-NEXT: add sp, sp, #[[STACK2]], lsl #12
diff --git a/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir b/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
index 8a5e0f6aa843a..44c5ca37b6c08 100644
--- a/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
+++ b/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
@@ -441,9 +441,9 @@ body: |
bb.0:
liveins: $q0, $x1
; CHECK-LABEL: name: 15-ldrqpre-ldrqui-same-dst-reg-no-merge
- ; CHECK: liveins: $q0, $q1, $x1
+ ; CHECK: liveins: $q0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber $x1, dead $q2, renamable $q0 = LDPQpre renamable $x1, 2 :: (load (s128))
+ ; CHECK-NEXT: early-clobber $x1, dead $q1, renamable $q0 = LDPQpre renamable $x1, 2 :: (load (s128))
; CHECK-NEXT: STRQui renamable $q0, renamable $x1, 0 :: (store (s128))
; CHECK-NEXT: RET undef $lr
early-clobber renamable $x1, renamable $q0 = LDRQpre killed renamable $x1, 32 :: (load (s128))
diff --git a/llvm/test/CodeGen/AArch64/literal_pools_float.ll b/llvm/test/CodeGen/AArch64/literal_pools_float.ll
index 333fee844a8ad..c8eb007eba9de 100644
--- a/llvm/test/CodeGen/AArch64/literal_pools_float.ll
+++ b/llvm/test/CodeGen/AArch64/literal_pools_float.ll
@@ -56,24 +56,85 @@ define dso_local void @floating_lits() optsize {
define dso_local float @float_ret_optnone() optnone noinline {
; CHECK-LABEL: float_ret_optnone:
-
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #52429 // =0xcccd
+; CHECK-NEXT: movk w8, #15820, lsl #16
+; CHECK-NEXT: fmov s0, w8
+; CHECK-NEXT: ret
+;
+; CHECK-LARGE-LABEL: float_ret_optnone:
+; CHECK-LARGE: // %bb.0:
+; CHECK-LARGE-NEXT: mov w8, #52429 // =0xcccd
+; CHECK-LARGE-NEXT: movk w8, #15820, lsl #16
+; CHECK-LARGE-NEXT: fmov s0, w8
+; CHECK-LARGE-NEXT: ret
+;
+; CHECK-TINY-LABEL: float_ret_optnone:
+; CHECK-TINY: // %bb.0:
+; CHECK-TINY-NEXT: mov w8, #52429 // =0xcccd
+; CHECK-TINY-NEXT: movk w8, #15820, lsl #16
+; CHECK-TINY-NEXT: fmov s0, w8
+; CHECK-TINY-NEXT: ret
+;
+; CHECK-NOFP-LABEL: float_ret_optnone:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: mov w0, #52429 // =0xcccd
+; CHECK-NOFP-NEXT: movk w0, #15820, lsl #16
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-NOFP-LARGE-LABEL: float_ret_optnone:
+; CHECK-NOFP-LARGE: // %bb.0:
+; CHECK-NOFP-LARGE-NEXT: mov w0, #52429 // =0xcccd
+; CHECK-NOFP-LARGE-NEXT: movk w0, #15820, lsl #16
+; CHECK-NOFP-LARGE-NEXT: ret
+;
+; CHECK-NOFP-TINY-LABEL: float_ret_optnone:
+; CHECK-NOFP-TINY: // %bb.0:
+; CHECK-NOFP-TINY-NEXT: mov w0, #52429 // =0xcccd
+; CHECK-NOFP-TINY-NEXT: movk w0, #15820, lsl #16
+; CHECK-NOFP-TINY-NEXT: ret
ret float 0x3FB99999A0000000
-; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI[0-9]+_[0-9]+]]
-; CHECK: ldr [[LIT128:s[0-9]+]], [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]]
; In the large code model, FastISel cannot load from the constant pool.
-; CHECK-LARGE-NOT: adrp
-; CHECK-LARGE-NOT: ldr
}
define dso_local double @double_ret_optnone() optnone noinline {
; CHECK-LABEL: double_ret_optnone:
-
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI2_0
+; CHECK-NEXT: ldr d0, [x8, :lo12:.LCPI2_0]
+; CHECK-NEXT: ret
+;
+; CHECK-LARGE-LABEL: double_ret_optnone:
+; CHECK-LARGE: // %bb.0:
+; CHECK-LARGE-NEXT: adrp x8, .LCPI2_0
+; CHECK-LARGE-NEXT: ldr d0, [x8, :lo12:.LCPI2_0]
+; CHECK-LARGE-NEXT: ret
+;
+; CHECK-TINY-LABEL: double_ret_optnone:
+; CHECK-TINY: // %bb.0:
+; CHECK-TINY-NEXT: ldr d0, .LCPI2_0
+; CHECK-TINY-NEXT: ret
+;
+; CHECK-NOFP-LABEL: double_ret_optnone:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: mov x0, #-7378697629483820647 // =0x9999999999999999
+; CHECK-NOFP-NEXT: movk x0, #39322
+; CHECK-NOFP-NEXT: movk x0, #16313, lsl #48
+; CHECK-NOFP-NEXT: ret
+;
+; CHECK-NOFP-LARGE-LABEL: double_ret_optnone:
+; CHECK-NOFP-LARGE: // %bb.0:
+; CHECK-NOFP-LARGE-NEXT: mov x0, #-7378697629483820647 // =0x9999999999999999
+; CHECK-NOFP-LARGE-NEXT: movk x0, #39322
+; CHECK-NOFP-LARGE-NEXT: movk x0, #16313, lsl #48
+; CHECK-NOFP-LARGE-NEXT: ret
+;
+; CHECK-NOFP-TINY-LABEL: double_ret_optnone:
+; CHECK-NOFP-TINY: // %bb.0:
+; CHECK-NOFP-TINY-NEXT: mov x0, #-7378697629483820647 // =0x9999999999999999
+; CHECK-NOFP-TINY-NEXT: movk x0, #39322
+; CHECK-NOFP-TINY-NEXT: movk x0, #16313, lsl #48
+; CHECK-NOFP-TINY-NEXT: ret
ret double 0.1
-; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI[0-9]+_[0-9]+]]
-; CHECK: ldr [[LIT128:d[0-9]+]], [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]]
-
-; In the large code model, FastISel cannot load from the constant pool.
-; CHECK-LARGE-NOT: adrp
-; CHECK-LARGE-NOT: ldr
}
diff --git a/llvm/test/CodeGen/AArch64/multi-vector-load-size.ll b/llvm/test/CodeGen/AArch64/multi-vector-load-size.ll
index 97dc8f569a41a..aa757d55d6086 100644
--- a/llvm/test/CodeGen/AArch64/multi-vector-load-size.ll
+++ b/llvm/test/CodeGen/AArch64/multi-vector-load-size.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=instruction-select < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=aarch64-isel < %s | FileCheck %s
%struct.__neon_float32x2x2_t = type { <2 x float>, <2 x float> }
%struct.__neon_float32x2x3_t = type { <2 x float>, <2 x float>, <2 x float> }
diff --git a/llvm/test/CodeGen/AArch64/multi-vector-store-size.ll b/llvm/test/CodeGen/AArch64/multi-vector-store-size.ll
index 3710db9c47ff6..d23b7877474d0 100644
--- a/llvm/test/CodeGen/AArch64/multi-vector-store-size.ll
+++ b/llvm/test/CodeGen/AArch64/multi-vector-store-size.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=instruction-select < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=aarch64-isel < %s | FileCheck %s
declare void @llvm.aarch64.neon.st2.v4f32.p0(<4 x float>, <4 x float>, ptr)
declare void @llvm.aarch64.neon.st3.v4f32.p0(<4 x float>, <4 x float>, <4 x float>, ptr)
diff --git a/llvm/test/CodeGen/AArch64/semantic-interposition-memtag.ll b/llvm/test/CodeGen/AArch64/semantic-interposition-memtag.ll
index debd128377d4b..2539527c0efc6 100644
--- a/llvm/test/CodeGen/AArch64/semantic-interposition-memtag.ll
+++ b/llvm/test/CodeGen/AArch64/semantic-interposition-memtag.ll
@@ -33,8 +33,7 @@ define dso_local i32 @main2() #0 {
; CHECK-NEXT: .cfi_startproc
; CHECK-NEXT: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, .Ly$local
-; CHECK-NEXT: add x8, x8, :lo12:.Ly$local
-; CHECK-NEXT: ldr w0, [x8]
+; CHECK-NEXT: ldr w0, [x8, :lo12:.Ly$local]
; CHECK-NEXT: ret
entry:
%0 = load i32, ptr @y, align 4
diff --git a/llvm/test/CodeGen/AArch64/strpre-str-merge.mir b/llvm/test/CodeGen/AArch64/strpre-str-merge.mir
index 5c1937e0d7753..4158283c4cd29 100644
--- a/llvm/test/CodeGen/AArch64/strpre-str-merge.mir
+++ b/llvm/test/CodeGen/AArch64/strpre-str-merge.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -o - %s -mtriple=aarch64 -mcpu=cortex-a55 -lsr-preferred-addressing-mode=preindexed -stop-after=aarch64-ldst-opt | FileCheck %s
---
@@ -18,8 +19,9 @@ body: |
liveins: $w1, $w2, $x0
; CHECK-LABEL: name: 1-strwpre-strwui-merge
; CHECK: liveins: $w1, $w2, $x0
- ; CHECK: early-clobber $x0 = STPWpre renamable $w1, renamable $w2, renamable $x0, 5 :: (store (s32))
- ; CHECK: RET undef $lr, implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: early-clobber $x0 = STPWpre renamable $w1, renamable $w2, renamable $x0, 5 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRWpre killed renamable $w1, killed renamable $x0, 20 :: (store (s32))
STRWui killed renamable $w2, renamable $x0, 1 :: (store (s32))
RET undef $lr, implicit $x0
@@ -46,8 +48,9 @@ body: |
; CHECK-LABEL: name: 2-strxpre-strxui-merge
; CHECK: liveins: $x0, $x1, $x2
- ; CHECK: early-clobber $x0 = STPXpre renamable $x1, renamable $x2, renamable $x0, 3 :: (store (s64))
- ; CHECK: RET undef $lr, implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: early-clobber $x0 = STPXpre renamable $x1, renamable $x2, renamable $x0, 3 :: (store (s64))
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRXpre killed renamable $x1, killed renamable $x0, 24 :: (store (s64))
STRXui killed renamable $x2, renamable $x0, 1 :: (store (s64))
RET undef $lr, implicit $x0
@@ -73,8 +76,9 @@ body: |
liveins: $s0, $s1, $x0
; CHECK-LABEL: name: 3-strspre-strsui-merge
; CHECK: liveins: $s0, $s1, $x0
- ; CHECK: early-clobber $x0 = STPSpre renamable $s0, renamable $s1, renamable $x0, 3 :: (store (s32))
- ; CHECK: RET undef $lr, implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: early-clobber $x0 = STPSpre renamable $s0, renamable $s1, renamable $x0, 3 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRSpre killed renamable $s0, killed renamable $x0, 12 :: (store (s32))
STRSui killed renamable $s1, renamable $x0, 1 :: (store (s32))
RET undef $lr, implicit $x0
@@ -100,8 +104,9 @@ body: |
; CHECK-LABEL: name: 4-strdpre-strdui-merge
; CHECK: liveins: $d0, $d1, $x0
- ; CHECK: early-clobber $x0 = STPDpre renamable $d0, renamable $d1, renamable $x0, 16 :: (store (s64))
- ; CHECK: RET undef $lr, implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: early-clobber $x0 = STPDpre renamable $d0, renamable $d1, renamable $x0, 16 :: (store (s64))
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRDpre killed renamable $d0, killed renamable $x0, 128 :: (store (s64))
STRDui killed renamable $d1, renamable $x0, 1 :: (store (s64))
RET undef $lr, implicit $x0
@@ -128,8 +133,9 @@ body: |
; CHECK-LABEL: name: 5-strqpre-strqui-merge
; CHECK: liveins: $q0, $q1, $x0
- ; CHECK: early-clobber $x0 = STPQpre renamable $q0, renamable $q1, renamable $x0, 3 :: (store (s128))
- ; CHECK: RET undef $lr, implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: early-clobber $x0 = STPQpre renamable $q0, renamable $q1, renamable $x0, 3 :: (store (s128))
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRQpre killed renamable $q0, killed renamable $x0, 48 :: (store (s128))
STRQui killed renamable $q1, renamable $x0, 1 :: (store (s128))
RET undef $lr, implicit $x0
@@ -155,9 +161,10 @@ body: |
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: 6-strqui-strqpre-no-merge
; CHECK: liveins: $q0, $q1, $x0
- ; CHECK: STRQui renamable $q1, renamable $x0, 1 :: (store (s128))
- ; CHECK: early-clobber renamable $x0 = STRQpre renamable $q0, renamable $x0, 48, implicit $w0, implicit $w0_hi :: (store (s128))
- ; CHECK: RET undef $lr, implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: STRQui renamable $q1, renamable $x0, 1 :: (store (s128))
+ ; CHECK-NEXT: early-clobber renamable $x0 = STRQpre renamable $q0, renamable $x0, 48, implicit $w0, implicit $w0_hi :: (store (s128))
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
STRQui killed renamable $q1, renamable $x0, 1 :: (store (s128))
early-clobber renamable $x0 = STRQpre killed renamable $q0, killed renamable $x0, 48 :: (store (s128))
RET undef $lr, implicit $x0
@@ -182,8 +189,9 @@ body: |
liveins: $s0, $s1, $x0
; CHECK-LABEL: name: 7-strspre-strsui-max-offset-merge
; CHECK: liveins: $s0, $s1, $x0
- ; CHECK: early-clobber $x0 = STPSpre renamable $s0, renamable $s1, renamable $x0, 63 :: (store (s32))
- ; CHECK: RET undef $lr, implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: early-clobber $x0 = STPSpre renamable $s0, renamable $s1, renamable $x0, 63 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRSpre killed renamable $s0, killed renamable $x0, 252 :: (store (s32))
STRSui killed renamable $s1, renamable $x0, 1 :: (store (s32))
RET undef $lr, implicit $x0
@@ -208,8 +216,9 @@ body: |
liveins: $s0, $s1, $x0
; CHECK-LABEL: name: 8-strspre-strsui-min-offset-merge
; CHECK: liveins: $s0, $s1, $x0
- ; CHECK: early-clobber $x0 = STPSpre renamable $s0, renamable $s1, renamable $x0, -64 :: (store (s32))
- ; CHECK: RET undef $lr, implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: early-clobber $x0 = STPSpre renamable $s0, renamable $s1, renamable $x0, -64 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRSpre killed renamable $s0, killed renamable $x0, -256 :: (store (s32))
STRSui killed renamable $s1, renamable $x0, 1 :: (store (s32))
RET undef $lr, implicit $x0
@@ -235,10 +244,11 @@ body: |
liveins: $s0, $s1, $x0, $x1
; CHECK-LABEL: name: 9-strspre-strsui-mod-base-reg-no-merge
; CHECK: liveins: $s0, $s1, $x0, $x1
- ; CHECK: dead early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0, implicit $w0_hi :: (store (s32))
- ; CHECK: renamable $x0 = LDRXui renamable $x1, 1 :: (load (s64))
- ; CHECK: STRSui renamable $s1, renamable $x0, 1 :: (store (s32))
- ; CHECK: RET undef $lr, implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: dead early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0, implicit $w0_hi :: (store (s32))
+ ; CHECK-NEXT: renamable $x0 = LDRXui renamable $x1, 1 :: (load (s64))
+ ; CHECK-NEXT: STRSui renamable $s1, renamable $x0, 1 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRSpre killed renamable $s0, killed renamable $x0, 12 :: (store (s32))
renamable $x0 = LDRXui renamable $x1, 1 :: (load (s64))
STRSui killed renamable $s1, renamable $x0, 1 :: (store (s32))
@@ -265,10 +275,11 @@ body: |
liveins: $s0, $s1, $x0, $x1
; CHECK-LABEL: name: 10-strspre-strsui-used-base-reg-no-merge
; CHECK: liveins: $s0, $s1, $x0, $x1
- ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0, implicit $w0_hi :: (store (s32))
- ; CHECK: STRXui renamable $x1, renamable $x1, 1 :: (store (s32))
- ; CHECK: STRSui renamable $s1, renamable $x0, 1 :: (store (s32))
- ; CHECK: RET undef $lr, implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0, implicit $w0_hi :: (store (s32))
+ ; CHECK-NEXT: STRXui renamable $x1, renamable $x1, 1 :: (store (s32))
+ ; CHECK-NEXT: STRSui renamable $s1, renamable $x0, 1 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRSpre killed renamable $s0, killed renamable $x0, 12 :: (store (s32))
STRXui killed renamable $x1, renamable $x1, 1 :: (store (s32))
@@ -296,13 +307,14 @@ body: |
liveins: $s0, $s1, $x0
; CHECK-LABEL: name: 11-strspre-strspre-no-merge
; CHECK: liveins: $s0, $s1, $x0
- ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0, implicit $w0_hi :: (store (s32))
- ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s1, renamable $x0, 16, implicit $w0, implicit $w0_hi :: (store (s32))
- ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 4, implicit $w0, implicit $w0_hi :: (store (s32))
- ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s1, renamable $x0, 12, implicit $w0, implicit $w0_hi :: (store (s32))
- ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 4, implicit $w0, implicit $w0_hi :: (store (s32))
- ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s1, renamable $x0, 4, implicit $w0, implicit $w0_hi :: (store (s32))
- ; CHECK: RET undef $lr, implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0, implicit $w0_hi :: (store (s32))
+ ; CHECK-NEXT: early-clobber renamable $x0 = STRSpre renamable $s1, renamable $x0, 16, implicit $w0, implicit $w0_hi :: (store (s32))
+ ; CHECK-NEXT: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 4, implicit $w0, implicit $w0_hi :: (store (s32))
+ ; CHECK-NEXT: early-clobber renamable $x0 = STRSpre renamable $s1, renamable $x0, 12, implicit $w0, implicit $w0_hi :: (store (s32))
+ ; CHECK-NEXT: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 4, implicit $w0, implicit $w0_hi :: (store (s32))
+ ; CHECK-NEXT: early-clobber renamable $x0 = STRSpre renamable $s1, renamable $x0, 4, implicit $w0, implicit $w0_hi :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRSpre renamable $s0, killed renamable $x0, 12 :: (store (s32))
early-clobber renamable $x0 = STRSpre renamable $s1, killed renamable $x0, 16 :: (store (s32))
early-clobber renamable $x0 = STRSpre renamable $s0, killed renamable $x0, 4 :: (store (s32))
@@ -335,9 +347,10 @@ body: |
liveins: $s0, $s1, $x0
; CHECK-LABEL: name: 12-strspre-strsui-no-merge
; CHECK: liveins: $s0, $s1, $x0
- ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0, implicit $w0_hi :: (store (s32))
- ; CHECK: STRSui renamable $s1, renamable $x0, 2 :: (store (s32))
- ; CHECK: RET undef $lr, implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0, implicit $w0_hi :: (store (s32))
+ ; CHECK-NEXT: STRSui renamable $s1, renamable $x0, 2 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRSpre killed renamable $s0, killed renamable $x0, 12 :: (store (s32))
STRSui killed renamable $s1, renamable $x0, 2 :: (store (s32))
RET undef $lr, implicit $x0
@@ -363,8 +376,9 @@ body: |
; CHECK-LABEL: name: 13-strqpre-sturqi-merge
; CHECK: liveins: $q0, $q1, $x0
- ; CHECK: early-clobber $x0 = STPQpre renamable $q0, renamable $q1, renamable $x0, 3 :: (store (s128))
- ; CHECK: RET undef $lr, implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: early-clobber $x0 = STPQpre renamable $q0, renamable $q1, renamable $x0, 3 :: (store (s128))
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRQpre killed renamable $q0, killed renamable $x0, 48 :: (store (s128))
STURQi killed renamable $q1, renamable $x0, 16 :: (store (s128))
RET undef $lr, implicit $x0
@@ -390,9 +404,10 @@ body: |
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: 14-strqpre-sturqi-no-merge
; CHECK: liveins: $q0, $q1, $x0
- ; CHECK: early-clobber renamable $x0 = STRQpre renamable $q0, renamable $x0, 48, implicit $w0, implicit $w0_hi :: (store (s128))
- ; CHECK: STURQi renamable $q1, renamable $x0, 1 :: (store (s128))
- ; CHECK: RET undef $lr, implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: early-clobber renamable $x0 = STRQpre renamable $q0, renamable $x0, 48, implicit $w0, implicit $w0_hi :: (store (s128))
+ ; CHECK-NEXT: STURQi renamable $q1, renamable $x0, 1 :: (store (s128))
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRQpre killed renamable $q0, killed renamable $x0, 48 :: (store (s128))
STURQi killed renamable $q1, renamable $x0, 1 :: (store (s128))
RET undef $lr, implicit $x0
@@ -417,9 +432,10 @@ body: |
liveins: $s0, $s1, $x0
; CHECK-LABEL: name: 15-strspre-strsui-unaligned-no-merge
; CHECK: liveins: $s0, $s1, $x0
- ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 251, implicit $w0, implicit $w0_hi :: (store (s32))
- ; CHECK: STRSui renamable $s1, renamable $x0, 1 :: (store (s32))
- ; CHECK: RET undef $lr, implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 251, implicit $w0, implicit $w0_hi :: (store (s32))
+ ; CHECK-NEXT: STRSui renamable $s1, renamable $x0, 1 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRSpre killed renamable $s0, killed renamable $x0, 251 :: (store (s32))
STRSui killed renamable $s1, renamable $x0, 1 :: (store (s32))
RET undef $lr, implicit $x0
@@ -443,9 +459,10 @@ body: |
liveins: $x0, $x1, $x2
; CHECK-LABEL: name: 16-strxpre-strxui-same-reg-no-merge
; CHECK: liveins: $x0, $x1, $x2
- ; CHECK: early-clobber renamable $x0 = STRXpre renamable $x1, renamable $x0, 24, implicit $w0, implicit $w0_hi :: (store (s64))
- ; CHECK: STRXui renamable $x0, renamable $x0, 1 :: (store (s64))
- ; CHECK: RET undef $lr, implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: early-clobber renamable $x0 = STRXpre renamable $x1, renamable $x0, 24, implicit $w0, implicit $w0_hi :: (store (s64))
+ ; CHECK-NEXT: STRXui renamable $x0, renamable $x0, 1 :: (store (s64))
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRXpre killed renamable $x1, killed renamable $x0, 24 :: (store (s64))
STRXui renamable $x0, renamable $x0, 1 :: (store (s64))
RET undef $lr, implicit $x0
@@ -470,9 +487,10 @@ body: |
liveins: $x0, $x1, $x2
; CHECK-LABEL: name: 17-strwpre-strwui-same-reg-no-merge
; CHECK: liveins: $x0, $x1, $x2
- ; CHECK: early-clobber renamable $x0 = STRWpre renamable $w1, renamable $x0, 24, implicit $w0, implicit $w0_hi, implicit-def $w0 :: (store (s32))
- ; CHECK: STRWui renamable $w0, renamable $x0, 1 :: (store (s32))
- ; CHECK: RET undef $lr, implicit $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: early-clobber renamable $x0 = STRWpre renamable $w1, renamable $x0, 24, implicit $w0, implicit $w0_hi, implicit-def $w0 :: (store (s32))
+ ; CHECK-NEXT: STRWui renamable $w0, renamable $x0, 1 :: (store (s32))
+ ; CHECK-NEXT: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRWpre killed renamable $w1, killed renamable $x0, 24 :: (store (s32))
STRWui renamable $w0, renamable $x0, 1 :: (store (s32))
RET undef $lr, implicit $x0
diff --git a/llvm/test/CodeGen/AArch64/swift-error-unreachable-use.ll b/llvm/test/CodeGen/AArch64/swift-error-unreachable-use.ll
index 9714636aee60b..977f92b0cd18b 100644
--- a/llvm/test/CodeGen/AArch64/swift-error-unreachable-use.ll
+++ b/llvm/test/CodeGen/AArch64/swift-error-unreachable-use.ll
@@ -5,15 +5,19 @@
define void @"func"(ptr swifterror %0) #0 {
; CHECK-LABEL: func:
-; CHECK: {{.*}}%bb.0:
-; CHECK-NEXT: b {{\.?}}LBB0_2
-; CHECK-NEXT: {{\.?}}LBB0_1:{{.*}}%thirtythree
-; CHECK-NEXT: {{.*}}=>This Inner Loop Header: Depth=1
-; CHECK-NEXT: b {{\.?}}LBB0_1
-; CHECK-NEXT: {{\.?}}LBB0_2:{{.*}}%thirtyeight
-; CHECK-NEXT: b {{\.?}}LBB0_3
-; CHECK-NEXT: {{\.?}}LBB0_3:{{.*}}%thirtythree.preheader
-; CHECK-NEXT: b {{\.?}}LBB0_1
+; CHECK: {{.*}}%bb.0:
+; CHECK: b {{.*}}LBB0_5
+; CHECK: {{.*}}LBB0_1:{{.*}}%common.ret
+; CHECK: {{.*}}LBB0_2:
+; CHECK: b {{.*}}LBB0_1
+; CHECK: {{.*}}LBB0_4:{{.*}}%thirtythree
+; CHECK: {{.*}}=>This Inner Loop Header: Depth=1
+; CHECK: b {{.*}}LBB0_4
+; CHECK: {{.*}}LBB0_5:{{.*}}%thirtyeight
+; CHECK: {{.*}}=>This Inner Loop Header: Depth=1
+; CHECK: b {{.*}}LBB0_6
+; CHECK: {{.*}}LBB0_6:{{.*}}%thirtythree.preheader
+; CHECK: b {{.*}}LBB0_4
br label %thirtyeight
five:
diff --git a/llvm/test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir b/llvm/test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir
index 9a014e0cce5d6..7f4ed054f78f2 100644
--- a/llvm/test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir
+++ b/llvm/test/CodeGen/MIR/AArch64/print-parse-overloaded-intrinsics.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple aarch64-- -run-pass irtranslator -simplify-mir %s -o %t \
-# RUN: -verify-machineinstrs; llc -mtriple aarch64-- -run-pass legalizer \
+# RUN: llc -mtriple=aarch64-- -global-isel -run-pass=irtranslator -simplify-mir %s -o %t \
+# RUN: -verify-machineinstrs; llc -mtriple=aarch64-- -run-pass=legalizer \
# RUN: -simplify-mir %t -x mir -o - -verify-machineinstrs | FileCheck %s
# Test that MIRParser is able to deserialize back MIR MIRPrinter serialized,
diff --git a/llvm/test/DebugInfo/Generic/debug-label-mi.ll b/llvm/test/DebugInfo/Generic/debug-label-mi.ll
index ad92dd2f5a7c2..0fd0385439821 100644
--- a/llvm/test/DebugInfo/Generic/debug-label-mi.ll
+++ b/llvm/test/DebugInfo/Generic/debug-label-mi.ll
@@ -1,5 +1,9 @@
; Test DBG_LABEL MachineInstr for label debugging.
; REQUIRES: asserts
+
+; AArch64 uses GlobalISel for optnone functions meaning the output from 'isel' will be empty as it will not be run.
+; XFAIL: target=aarch64{{.*}}
+
; RUN: llc -debug-only=isel %s -o /dev/null 2> %t.debug
; RUN: cat %t.debug | FileCheck %s --check-prefix=CHECKMI
;
diff --git a/llvm/test/Feature/optnone-llc.ll b/llvm/test/Feature/optnone-llc.ll
index 7e6678f9cdc42..218fd63ce98c5 100644
--- a/llvm/test/Feature/optnone-llc.ll
+++ b/llvm/test/Feature/optnone-llc.ll
@@ -8,6 +8,9 @@
; REQUIRES: asserts, default_triple
; UNSUPPORTED: target=nvptx{{.*}}
+; AArch64 uses GlobalISel for optnone functions meaning the output from 'isel' will be empty as it will not be run.
+; XFAIL: target=aarch64{{.*}}
+
; This test verifies that we don't run Machine Function optimizations
; on optnone functions, and that we can turn off FastISel.
@@ -34,9 +37,6 @@ while.end: ; preds = %while.cond
attributes #0 = { optnone noinline }
-; Nothing that runs at -O0 gets skipped.
-; LLC-O0-NOT: Skipping pass
-
; Machine Function passes run at -O1 and higher.
; LLC-Ox-DAG: Skipping pass 'Branch Probability Basic Block Placement'
; LLC-Ox-DAG: Skipping pass 'CodeGen Prepare'
>From 17e2f748bfe32443bb9d0b1f5684c0b718b25222 Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Wed, 7 Jan 2026 13:31:36 +0000
Subject: [PATCH 2/3] Remove command line option
---
.../Target/AArch64/AArch64TargetMachine.cpp | 7 +------
.../GlobalISel/gisel-commandline-option.ll | 20 +++++++++----------
.../AArch64/GlobalISel/optnone-mixed.ll | 4 ----
3 files changed, 11 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 3d87eb60603b0..f4df012132e4a 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -160,10 +160,6 @@ static cl::opt<int> EnableGlobalISelAtO(
cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
cl::init(0));
-static cl::opt<bool> EnableGlobalISelForOptNone(
- "aarch64-enable-global-isel-for-optnone", cl::Hidden,
- cl::desc("Route optnone functions through GlobalISel"), cl::init(true));
-
static cl::opt<bool>
EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden,
cl::desc("Enable SVE intrinsic opts"),
@@ -398,8 +394,7 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
if (static_cast<int>(getOptLevel()) <= EnableGlobalISelAtO) {
setGlobalISel(true);
setGlobalISelAbort(GlobalISelAbortMode::Disable);
- } else if (!GlobalISelFlag && EnableGlobalISelForOptNone &&
- !Options.EnableGlobalISel) {
+ } else if (!GlobalISelFlag && !Options.EnableGlobalISel) {
setGlobalISel(true);
setGlobalISelAbort(GlobalISelAbortMode::Disable);
UseGISelForOptNoneOnly = true;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll b/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
index 38a0f4ffb4904..c4c0794edb6fa 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
@@ -36,22 +36,16 @@
; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
; RUN: --debugify-and-strip-all-safe=0 \
; RUN: -verify-machineinstrs=0 -O1 -aarch64-enable-global-isel-at-O=0 \
-; RUN: | FileCheck %s --check-prefix OPTNONE
-
-; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
-; RUN: --debugify-and-strip-all-safe=0 \
-; RUN: -verify-machineinstrs=0 -O1 -aarch64-enable-global-isel-at-O=0 \
-; RUN: -aarch64-enable-global-isel-for-optnone=false \
-; RUN: | FileCheck %s --check-prefix DISABLED
+; RUN: | FileCheck %s --check-prefix NOT-ENABLED
; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
; RUN: --debugify-and-strip-all-safe=0 \
; RUN: -verify-machineinstrs=0 -aarch64-enable-global-isel-at-O=-1 \
-; RUN: | FileCheck %s --check-prefix DISABLED
+; RUN: | FileCheck %s --check-prefix NOT-ENABLED
; RUN: llc -mtriple=aarch64-- -debug-pass=Structure %s -o /dev/null 2>&1 \
; RUN: --debugify-and-strip-all-safe=0 \
-; RUN: -verify-machineinstrs=0 | FileCheck %s --check-prefix DISABLED
+; RUN: -verify-machineinstrs=0 | FileCheck %s --check-prefix NOT-ENABLED
; RUN: llc -mtriple=aarch64-- -fast-isel=0 -global-isel=false \
; RUN: --debugify-and-strip-all-safe=0 \
@@ -88,7 +82,13 @@
; FALLBACK: AArch64 Instruction Selection
; NOFALLBACK-NOT: AArch64 Instruction Selection
-; OPTNONE: IRTranslator
+; Should be included due to the potential for SDAG to use GlobalISel for optnone functions
+; NOT-ENABLED: IRTranslator
+
+; NOT-ENABLED: AArch64 Instruction Selection
+; NOT-ENABLED: Finalize ISel and expand pseudo-instructions
+
+; DISABLED-NOT: IRTranslator
; DISABLED: AArch64 Instruction Selection
; DISABLED: Finalize ISel and expand pseudo-instructions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/optnone-mixed.ll b/llvm/test/CodeGen/AArch64/GlobalISel/optnone-mixed.ll
index 442f8f86fb973..dad0f7b6c0651 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/optnone-mixed.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/optnone-mixed.ll
@@ -1,6 +1,5 @@
; NOTE: Do not autogenerate
; RUN: llc -mtriple=aarch64-linux-gnu -O2 -verify-machineinstrs -debug %s -o - 2>&1 | FileCheck %s --check-prefix=GISEL
-; RUN: llc -mtriple=aarch64-linux-gnu -O2 -verify-machineinstrs -debug %s -o - 2>&1 -aarch64-enable-global-isel-for-optnone=0 | FileCheck %s --check-prefix=SDAG
; REQUIRES: asserts
; Check both an optnone function and a non-optnone function to ensure that only
@@ -22,7 +21,4 @@ entry:
; GISEL: Skipping pass 'AArch64PostLegalizerCombiner' on function optnone_fn
; GISEL: Creating new node:
-; SDAG: Changing optimization level for Function optnone_fn
-; SDAG: Optimized legalized selection DAG: %bb.0 'normal_fn:entry'
-
attributes #0 = { noinline nounwind optnone uwtable }
>From d9df71cab67d0cbfe7c5fa4ec7a75d80eecbc91b Mon Sep 17 00:00:00 2001
From: Ryan Cowan <ryan.cowan at arm.com>
Date: Thu, 8 Jan 2026 12:14:30 +0000
Subject: [PATCH 3/3] Simplify tests & reorder useGlobalISelFor conditional
---
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 6 +++---
llvm/test/CodeGen/AArch64/GlobalISel/optnone-llc.ll | 8 +-------
llvm/test/CodeGen/AArch64/GlobalISel/optnone-mixed.ll | 1 -
3 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index f4df012132e4a..efc023c81f50a 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -719,9 +719,9 @@ void AArch64PassConfig::addCodeGenPrepare() {
}
bool AArch64PassConfig::useGlobalISelFor(const Function &F) const {
- if (!getAArch64TargetMachine().useGlobalISelForOptNoneOnly())
- return true;
- return F.hasOptNone();
+ if (getAArch64TargetMachine().useGlobalISelForOptNoneOnly())
+ return F.hasOptNone();
+ return true;
}
bool AArch64PassConfig::addInstSelector() {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/optnone-llc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/optnone-llc.ll
index 13ab7cb477e51..1e1f1df56c692 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/optnone-llc.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/optnone-llc.ll
@@ -2,15 +2,12 @@
; RUN: llc -O1 -debug -global-isel -mtriple=aarch64-unknown-linux-gnu -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=LLC-Ox
; RUN: llc -O2 -debug -global-isel -mtriple=aarch64-unknown-linux-gnu -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=LLC-Ox
; RUN: llc -O3 -debug -global-isel -mtriple=aarch64-unknown-linux-gnu -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=LLC-Ox
-; RUN: llc -misched-postra -debug -global-isel -mtriple=aarch64-unknown-linux-gnu -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=LLC-MORE
; REQUIRES: asserts
-; UNSUPPORTED: target=nvptx{{.*}}
; This test verifies that we don't run Machine Function optimizations
; on optnone functions.
-; Function Attrs: noinline optnone
define i32 @_Z3fooi(i32 %x) #0 {
entry:
%x.addr = alloca i32, align 4
@@ -47,7 +44,4 @@ attributes #0 = { optnone noinline }
; LLC-Ox-DAG: Skipping pass 'Peephole Optimizations'
; LLC-Ox-DAG: Skipping pass 'Post{{.*}}RA{{.*}}{{[Ss]}}cheduler'
; LLC-Ox-DAG: Skipping pass 'Remove dead machine instructions'
-; LLC-Ox-DAG: Skipping pass 'Tail Duplication'
-
-; Alternate post-RA scheduler.
-; LLC-MORE: Skipping pass 'PostRA Machine Instruction Scheduler'
\ No newline at end of file
+; LLC-Ox-DAG: Skipping pass 'Tail Duplication'
\ No newline at end of file
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/optnone-mixed.ll b/llvm/test/CodeGen/AArch64/GlobalISel/optnone-mixed.ll
index dad0f7b6c0651..6e731545125f6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/optnone-mixed.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/optnone-mixed.ll
@@ -5,7 +5,6 @@
; Check both an optnone function and a non-optnone function to ensure that only
; the optnone functions is routed through GlobalISel
-; Function Attrs: noinline nounwind optnone uwtable
define i32 @optnone_fn(i32 %a) #0 {
entry:
%add = add nsw i32 %a, 1
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