[llvm] AMDGPU: Teach lowering that sqrt never returns subnormal (PR #174838)

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Thu Jan 8 03:05:25 PST 2026


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@@ -4877,15 +4877,14 @@ define float @v_sqrt_f32__sqrt_known_not_denorm(float %x) {
 ; SDAG-IEEE-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v0
 ; SDAG-IEEE-NEXT:    v_cmp_gt_f32_e32 vcc, s6, v0
 ; SDAG-IEEE-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
-; SDAG-IEEE-NEXT:    v_sqrt_f32_e32 v1, v0
-; SDAG-IEEE-NEXT:    v_add_i32_e64 v3, s[4:5], -1, v1
-; SDAG-IEEE-NEXT:    v_fma_f32 v4, -v3, v1, v0
-; SDAG-IEEE-NEXT:    v_cmp_ge_f32_e64 s[4:5], 0, v4
-; SDAG-IEEE-NEXT:    v_cndmask_b32_e64 v3, v1, v3, s[4:5]
-; SDAG-IEEE-NEXT:    v_add_i32_e64 v4, s[4:5], 1, v1
-; SDAG-IEEE-NEXT:    v_fma_f32 v1, -v4, v1, v0
-; SDAG-IEEE-NEXT:    v_cmp_lt_f32_e64 s[4:5], 0, v1
-; SDAG-IEEE-NEXT:    v_cndmask_b32_e64 v1, v3, v4, s[4:5]
+; SDAG-IEEE-NEXT:    v_rsq_f32_e32 v1, v0
+; SDAG-IEEE-NEXT:    v_mul_f32_e32 v3, v0, v1
+; SDAG-IEEE-NEXT:    v_mul_f32_e32 v1, 0.5, v1
+; SDAG-IEEE-NEXT:    v_fma_f32 v4, -v1, v3, 0.5
+; SDAG-IEEE-NEXT:    v_fma_f32 v3, v3, v4, v3
+; SDAG-IEEE-NEXT:    v_fma_f32 v5, -v3, v3, v0
+; SDAG-IEEE-NEXT:    v_fma_f32 v1, v1, v4, v1
+; SDAG-IEEE-NEXT:    v_fma_f32 v1, v5, v1, v3
----------------
arsenm wrote:

I think I noticed this before, I'm not sure one of the fast paths for sqrt makes sense anymore 

https://github.com/llvm/llvm-project/pull/174838


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